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authorThomas Zimmermann <tzimmermann@suse.de>2019-10-24 10:14:03 +0200
committerThomas Zimmermann <tzimmermann@suse.de>2019-10-24 16:12:36 +0200
commitecad80f0865d69c8de37c7415dbf66ba372f2ca1 (patch)
treed0740c34701ee2861c286eaaed035a19e91142be
parenteddc0acfed094293a0ee5130cc8cd2b97be8ee84 (diff)
downloadlinux-ecad80f0865d69c8de37c7415dbf66ba372f2ca1.tar.bz2
drm/hisilicon/hibmc: Use GEM VRAM's prepare_fb() and cleanup_fb() helpers
This patch implements prepare_fb() and cleanup_fb() in hibmc with the GEM VRAM helpers. In the current code, pinning the BO is performed by hibmc_plane_atomic_update(), where the operation does not belong. This patch also fixes a bug where the pinned BO was never unpinned. Pinning multiple BOs would have exhaused the available VRAM and further pin operations would have failed, leaving the display in a corrupt state. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20191024081404.6978-4-tzimmermann@suse.de
-rw-r--r--drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c14
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
index cc4c41748cfb..6527a97f68a3 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c
@@ -96,7 +96,6 @@ static void hibmc_plane_atomic_update(struct drm_plane *plane,
{
struct drm_plane_state *state = plane->state;
u32 reg;
- int ret;
s64 gpu_addr = 0;
unsigned int line_l;
struct hibmc_drm_private *priv = plane->dev->dev_private;
@@ -109,16 +108,9 @@ static void hibmc_plane_atomic_update(struct drm_plane *plane,
hibmc_fb = to_hibmc_framebuffer(state->fb);
gbo = drm_gem_vram_of_gem(hibmc_fb->obj);
- ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM);
- if (ret) {
- DRM_ERROR("failed to pin bo: %d", ret);
- return;
- }
gpu_addr = drm_gem_vram_offset(gbo);
- if (gpu_addr < 0) {
- drm_gem_vram_unpin(gbo);
- return;
- }
+ if (WARN_ON_ONCE(gpu_addr < 0))
+ return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS);
@@ -157,6 +149,8 @@ static struct drm_plane_funcs hibmc_plane_funcs = {
};
static const struct drm_plane_helper_funcs hibmc_plane_helper_funcs = {
+ .prepare_fb = drm_gem_vram_plane_helper_prepare_fb,
+ .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb,
.atomic_check = hibmc_plane_atomic_check,
.atomic_update = hibmc_plane_atomic_update,
};