diff options
| author | Imre Deak <imre.deak@intel.com> | 2020-02-26 22:34:47 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2020-03-02 19:36:21 +0200 |
| commit | 6cbcd57680e170e80f1b1a90d6f2dc971636de3b (patch) | |
| tree | 30ab0afde1c99a568c4548bb4f8d508914832adf | |
| parent | 4ac7df1775f3c943216d7aaf158e5ad16a94dd7e (diff) | |
| download | linux-6cbcd57680e170e80f1b1a90d6f2dc971636de3b.tar.bz2 | |
drm/i915/hsw: Use the DPLL ID when calculating DPLL clock
Instead of converting DPLL ID to CLK_SEL to identify the DPLL use the
DPLL ID directly for this.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226203455.23032-6-imre.deak@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e09ab0d44afa..3375d63d543f 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -1729,26 +1729,25 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int link_clock = 0; - u32 val, pll; + u32 pll; - val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); - switch (val & PORT_CLK_SEL_MASK) { - case PORT_CLK_SEL_LCPLL_810: + switch (pipe_config->shared_dpll->info->id) { + case DPLL_ID_LCPLL_810: link_clock = 81000; break; - case PORT_CLK_SEL_LCPLL_1350: + case DPLL_ID_LCPLL_1350: link_clock = 135000; break; - case PORT_CLK_SEL_LCPLL_2700: + case DPLL_ID_LCPLL_2700: link_clock = 270000; break; - case PORT_CLK_SEL_WRPLL1: + case DPLL_ID_WRPLL1: link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); break; - case PORT_CLK_SEL_WRPLL2: + case DPLL_ID_WRPLL2: link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); break; - case PORT_CLK_SEL_SPLL: + case DPLL_ID_SPLL: pll = intel_de_read(dev_priv, SPLL_CTL) & SPLL_FREQ_MASK; if (pll == SPLL_FREQ_810MHz) link_clock = 81000; |