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| author | Robin Murphy <robin.murphy@arm.com> | 2018-02-16 17:04:23 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2018-02-17 08:37:05 +0000 |
| commit | e1a50de37860b3a93a9d643b09638db5aff47650 (patch) | |
| tree | 3074602e531f1cc551f6c8ef5ce268eab579f7b9 | |
| parent | 20a004e7b017cce282a46ac5d02c2b9c6b9bb1fa (diff) | |
| download | linux-e1a50de37860b3a93a9d643b09638db5aff47650.tar.bz2 | |
arm64: cputype: Silence Sparse warnings
Sparse makes a fair bit of noise about our MPIDR mask being implicitly
long - let's explicitly describe it as such rather than just relying on
the value forcing automatic promotion.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm64/include/asm/cputype.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index be7bd19c87ec..eda8c5f629fc 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -20,7 +20,7 @@ #define MPIDR_UP_BITMASK (0x1 << 30) #define MPIDR_MT_BITMASK (0x1 << 24) -#define MPIDR_HWID_BITMASK 0xff00ffffff +#define MPIDR_HWID_BITMASK 0xff00ffffffUL #define MPIDR_LEVEL_BITS_SHIFT 3 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) |