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authorPalmer Dabbelt <palmer@sifive.com>2017-11-28 14:06:17 -0800
committerPalmer Dabbelt <palmer@sifive.com>2017-11-28 14:06:17 -0800
commitc901e45a999a1935d7adf653e1cf12dfbcd737aa (patch)
tree2d30d6656ef0d3fd57f78045830b9c21ae69a5ae
parent21db403660d1433b8a02b26d5d4084921b857c40 (diff)
downloadlinux-c901e45a999a1935d7adf653e1cf12dfbcd737aa.tar.bz2
RISC-V: `sfence.vma` orderes the instruction cache
This is just a comment change, but it's one that bit me on the mailing list. It turns out that issuing a `sfence.vma` enforces instruction cache ordering in addition to TLB ordering. This isn't explicitly called out in the ISA manual, but Andrew will be making that more clear in a future revision. CC: Andrew Waterman <andrew@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
-rw-r--r--arch/riscv/include/asm/tlbflush.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index 5ee4ae370b5e..c79fab3d377d 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -17,7 +17,10 @@
#ifdef CONFIG_MMU
-/* Flush entire local TLB */
+/*
+ * Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
+ * cache as well, so a 'fence.i' is not necessary.
+ */
static inline void local_flush_tlb_all(void)
{
__asm__ __volatile__ ("sfence.vma" : : : "memory");