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authorArnd Bergmann <arnd@arndb.de>2017-06-23 16:44:36 +0200
committerArnd Bergmann <arnd@arndb.de>2017-06-23 16:44:36 +0200
commit30e3224e4ad3abe8438628b3df246ce53de1782e (patch)
tree3d73d80477a12f88dab8bc569bcb439201b4a21c
parentf61bbd39b47df6093685491daab9ef3d41abf99e (diff)
parent3c56909ec2672d74d30f32f1c0ed8cfd7d6e2b14 (diff)
downloadlinux-30e3224e4ad3abe8438628b3df246ce53de1782e.tar.bz2
Merge tag 'socfpga_dts_for_v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
Pull "SoCFPGA DTS updates for v4.13" from Dinh Nguyen: - Fix clocks node the EMACs - VINING board updtes - Remove I2C EEPROMs and LED node - Add QSPI device - Add 2nd ethernet alias - Add 'clock-frequency' binding for i2c node * tag 'socfpga_dts_for_v4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: ARM: dts: socfpga: set the i2c frequency ARM: dts: socfpga: Add second ethernet alias to VINING FPGA ARM: dts: socfpga: Drop LED node from VINING FPGA ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA ARM: dts: socfpga: Enable QSPI support on VINING FPGA ARM: dts: socfpga: Fix the ethernet clock phandle
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi4
-rw-r--r--arch/arm/boot/dts/socfpga_arria10_socdk.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts2
-rw-r--r--arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts101
5 files changed, 46 insertions, 65 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index b2674bdb8e6a..7e24dc8e82d4 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -557,7 +557,7 @@
interrupts = <0 115 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac0_clk>;
+ clocks = <&emac_0_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC0_RESET>;
reset-names = "stmmaceth";
@@ -575,7 +575,7 @@
interrupts = <0 120 4>;
interrupt-names = "macirq";
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
- clocks = <&emac1_clk>;
+ clocks = <&emac_1_clk>;
clock-names = "stmmaceth";
resets = <&rst EMAC1_RESET>;
reset-names = "stmmaceth";
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 94e088473823..3a32de9ded3b 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -130,13 +130,13 @@
};
&i2c1 {
- speed-mode = <0>;
status = "okay";
/*
* adjust the falling times to decrease the i2c frequency to 50Khz
* because the LCD module does not work at the standard 100Khz
*/
+ clock-frequency = <100000>;
i2c-sda-falling-time-ns = <6000>;
i2c-scl-falling-time-ns = <6000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
index 7b49395452b6..b280e6494193 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts
@@ -86,7 +86,7 @@
&i2c0 {
status = "okay";
- speed-mode = <0>;
+ clock-frequency = <100000>;
adxl345: adxl345@0 {
compatible = "adi,adxl345";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
index 21e397287e29..c2eb88aab8b3 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts
@@ -58,7 +58,7 @@
&i2c0 {
status = "okay";
- speed-mode = <0>;
+ clock-frequency = <100000>;
stmpe1: stmpe811@41 {
compatible = "st,stmpe811";
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index 893198049397..655fe87e272d 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -69,34 +69,7 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
- };
-
- leds {
- compatible = "gpio-leds";
-
- hps_led0 {
- label = "hps:green:led0"; /* ALIVE_LED_GR */
- gpios = <&portb 19 0>; /* HPS_GPIO48 */
- linux,default-trigger = "heartbeat";
- };
-
- hps_led1 {
- label = "hps:red:led0"; /* ALIVE_LED_RD */
- gpios = <&portb 24 0>; /* HPS_GPIO53 */
- linux,default-trigger = "none";
- };
-
- hps_led2 {
- label = "hps:green:led1"; /* LINK2HOST_LED_GR */
- gpios = <&portb 25 0>; /* HPS_GPIO54 */
- linux,default-trigger = "heartbeat";
- };
-
- hps_led3 {
- label = "hps:red:led1"; /* LINK2HOST_LED_RD */
- gpios = <&portc 7 0>; /* HPS_GPIO65 */
- linux,default-trigger = "none";
- };
+ ethernet1 = &gmac0;
};
gpio-keys {
@@ -203,69 +176,39 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
i2c@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
- eeprom@51 {
- compatible = "at,24c01";
- pagesize = <8>;
- reg = <0x51>;
- };
};
- i2c@6 {
+ i2c@6 { /* Backplane EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
@@ -276,7 +219,7 @@
};
};
- i2c@7 {
+ i2c@7 { /* Power board EEPROM */
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
@@ -300,6 +243,44 @@
};
};
+&qspi {
+ status = "okay";
+
+ n25q128@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+
+ n25q00@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <1>; /* chip select */
+ spi-max-frequency = <100000000>;
+ m25p,fast-read;
+
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <4>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ };
+};
+
&usb0 {
dr_mode = "host";
status = "okay";