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| author | Stephane Eranian <eranian@google.com> | 2020-11-26 20:09:22 +0900 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2020-12-03 10:00:26 +0100 |
| commit | fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27 (patch) | |
| tree | 4b0e517db83ad158f76421592fe2aa66507b5ac0 | |
| parent | 5debf02131227d39988e44adf5090fb796fa8466 (diff) | |
| download | linux-fc17db8aa4c53cbd2d5469bb0521ea0f0a6dbb27.tar.bz2 | |
perf/x86/intel: Check PEBS status correctly
The kernel cannot disambiguate when 2+ PEBS counters overflow at the
same time. This is what the comment for this code suggests. However,
I see the comparison is done with the unfiltered p->status which is a
copy of IA32_PERF_GLOBAL_STATUS at the time of the sample. This
register contains more than the PEBS counter overflow bits. It also
includes many other bits which could also be set.
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20201126110922.317681-2-namhyung@kernel.org
| -rw-r--r-- | arch/x86/events/intel/ds.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 89dba588636e..485c5066f8b8 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1916,7 +1916,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d * that caused the PEBS record. It's called collision. * If collision happened, the record will be dropped. */ - if (p->status != (1ULL << bit)) { + if (pebs_status != (1ULL << bit)) { for_each_set_bit(i, (unsigned long *)&pebs_status, size) error[i]++; continue; |