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authorArnd Bergmann <arnd@arndb.de>2017-10-19 17:43:43 +0200
committerArnd Bergmann <arnd@arndb.de>2017-10-19 17:43:43 +0200
commitbe2f9d36b2b39aaf986c2206a64f957c449ac182 (patch)
treefdf1deec504a0402de5c6d8e666dc1f9b667cb3a
parent611e91e15ef61e8c838c8695d593db919d9491c2 (diff)
parentf450f28e70a2378d9d6ded0932fe480055888cfa (diff)
downloadlinux-be2f9d36b2b39aaf986c2206a64f957c449ac182.tar.bz2
Merge tag 'reset-fixes-for-4.14-2' of git://git.pengutronix.de/git/pza/linux into fixes
Pull "Reset controller fixes for v4.14" from Philipp Zabel: Fix SoCFPGA reset controller for 64-bit systems. This patch removes the assumption that BITS_PER_LONG is 32, which is not the case on Stratix10. * tag 'reset-fixes-for-4.14-2' of git://git.pengutronix.de/git/pza/linux: reset: socfpga: fix for 64-bit compilation
-rw-r--r--drivers/reset/reset-socfpga.c17
1 files changed, 10 insertions, 7 deletions
diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c
index c60904ff40b8..3907bbc9c6cf 100644
--- a/drivers/reset/reset-socfpga.c
+++ b/drivers/reset/reset-socfpga.c
@@ -40,8 +40,9 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
struct socfpga_reset_data *data = container_of(rcdev,
struct socfpga_reset_data,
rcdev);
- int bank = id / BITS_PER_LONG;
- int offset = id % BITS_PER_LONG;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
unsigned long flags;
u32 reg;
@@ -61,8 +62,9 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
struct socfpga_reset_data,
rcdev);
- int bank = id / BITS_PER_LONG;
- int offset = id % BITS_PER_LONG;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
unsigned long flags;
u32 reg;
@@ -81,8 +83,9 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev,
{
struct socfpga_reset_data *data = container_of(rcdev,
struct socfpga_reset_data, rcdev);
- int bank = id / BITS_PER_LONG;
- int offset = id % BITS_PER_LONG;
+ int reg_width = sizeof(u32);
+ int bank = id / (reg_width * BITS_PER_BYTE);
+ int offset = id % (reg_width * BITS_PER_BYTE);
u32 reg;
reg = readl(data->membase + (bank * BANK_INCREMENT));
@@ -132,7 +135,7 @@ static int socfpga_reset_probe(struct platform_device *pdev)
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
+ data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE);
data->rcdev.ops = &socfpga_reset_ops;
data->rcdev.of_node = pdev->dev.of_node;