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| author | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-03 08:00:30 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-07-03 08:00:30 -0500 |
| commit | ecf75c46e6a43eb083c9dfbbe7903ec81dcd524a (patch) | |
| tree | 3f1d30f7c701640cbac69d67efad277a7ffafc9f | |
| parent | f011a5f8bacbf62f9de16c2a4c7e73dcabfae383 (diff) | |
| parent | 40aa52c46288ebe37117bea84b1da8edb38e8604 (diff) | |
| download | linux-ecf75c46e6a43eb083c9dfbbe7903ec81dcd524a.tar.bz2 | |
Merge branch 'pci/host-dra7xx' into next
* pci/host-dra7xx:
PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN
PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
| -rw-r--r-- | drivers/pci/dwc/Kconfig | 1 | ||||
| -rw-r--r-- | drivers/pci/dwc/pci-dra7xx.c | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index b7e15526d676..d34b6dfbb351 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -16,6 +16,7 @@ config PCIE_DW_EP config PCI_DRA7XX bool "TI DRA7xx PCIe controller" + depends on SOC_DRA7XX || COMPILE_TEST depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT depends on OF && HAS_IOMEM && TI_PIPE3 help diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index e4166032b3c6..f2fc5f47064e 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -174,7 +174,7 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci) static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) { dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, - ~LEG_EP_INTERRUPTS & ~MSI); + LEG_EP_INTERRUPTS | MSI); dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, @@ -184,7 +184,7 @@ static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx) static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx) { dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, - ~INTERRUPTS); + INTERRUPTS); dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS); } |