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| author | Dale Farnsworth <dale@farnsworth.org> | 2006-03-21 11:44:35 -0700 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-03-21 16:00:51 -0500 |
| commit | 6f059c3e9042bc4eaa4f7a8dd651bbed9be144f2 (patch) | |
| tree | 7f7793ab7f2e793286a844525f0ab4d057347b7c | |
| parent | 9362860fd1d9062ff9b3dca42aa3e1e68c2ddb67 (diff) | |
| download | linux-6f059c3e9042bc4eaa4f7a8dd651bbed9be144f2.tar.bz2 | |
[PATCH] mv643xx_eth: Cache align skb->data if CONFIG_NOT_COHERENT_CACHE
When I/O is non-cache-coherent, we need to ensure that the I/O buffers
we use don't share cache lines with other data.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
| -rw-r--r-- | drivers/net/mv643xx_eth.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h index 7754d1974b9e..4262c1da6d4a 100644 --- a/drivers/net/mv643xx_eth.h +++ b/drivers/net/mv643xx_eth.h @@ -42,13 +42,23 @@ #define MAX_DESCS_PER_SKB 1 #endif +/* + * The MV643XX HW requires 8-byte alignment. However, when I/O + * is non-cache-coherent, we need to ensure that the I/O buffers + * we use don't share cache lines with other data. + */ +#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_NOT_COHERENT_CACHE) +#define ETH_DMA_ALIGN L1_CACHE_BYTES +#else +#define ETH_DMA_ALIGN 8 +#endif + #define ETH_VLAN_HLEN 4 #define ETH_FCS_LEN 4 -#define ETH_DMA_ALIGN 8 /* hw requires 8-byte alignment */ -#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ +#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ - ETH_VLAN_HLEN + ETH_FCS_LEN) -#define ETH_RX_SKB_SIZE ((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7) + ETH_VLAN_HLEN + ETH_FCS_LEN) +#define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + ETH_DMA_ALIGN) #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ |