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authorAlex Deucher <alexdeucher@gmail.com>2010-10-18 23:45:39 -0400
committerDave Airlie <airlied@redhat.com>2010-10-26 14:47:44 +1000
commit354da653233898ed1e51f20cebac9705456bf9b1 (patch)
tree5a5dcd470d57ca867da35ea3f2b8fc7938efd51f
parent2281a378e1830d7ab78d3067f228e4e55d368b0d (diff)
downloadlinux-354da653233898ed1e51f20cebac9705456bf9b1.tar.bz2
drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker
macro tile heights are aligned to num channels, not num banks. Noticed by Dave Airlie. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index f82832780a7e..41802915f93f 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -229,7 +229,7 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
__func__, __LINE__, pitch);
return -EINVAL;
}
- if (!IS_ALIGNED((height / 8), track->nbanks)) {
+ if (!IS_ALIGNED((height / 8), track->npipes)) {
dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
__func__, __LINE__, height);
return -EINVAL;
@@ -378,7 +378,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
__func__, __LINE__, pitch);
return -EINVAL;
}
- if ((height / 8) & (track->nbanks - 1)) {
+ if (!IS_ALIGNED((height / 8), track->npipes)) {
dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
__func__, __LINE__, height);
return -EINVAL;