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author | Krzysztof Helt <krzysztof.h1@wp.pl> | 2009-03-31 15:25:17 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-04-01 08:59:29 -0700 |
commit | 4242a23c9e6b8e2462bb49bf78b76bfdf32158b5 (patch) | |
tree | 9339a9380bc5ae2f4eb0cf63444ffb02946a89c4 | |
parent | df3aafd57d590d6f3d95310fc3430f3a536d1e59 (diff) | |
download | linux-4242a23c9e6b8e2462bb49bf78b76bfdf32158b5.tar.bz2 |
cirrusfb: fix threshold register mask for Laguna chips
Fix threshold register mask for Laguna chips otherwise some 8bpp modes are
garbled after selecting a 24bpp mode.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r-- | drivers/video/cirrusfb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/video/cirrusfb.c b/drivers/video/cirrusfb.c index a364e1b0dcb7..9bb811d56721 100644 --- a/drivers/video/cirrusfb.c +++ b/drivers/video/cirrusfb.c @@ -875,7 +875,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info) threshold = fb_readw(cinfo->laguna_mmio + 0xea); control &= ~0x6800; format = 0; - threshold &= 0xffe0 & 0x3fbf; + threshold &= 0xffc0 & 0x3fbf; } if (nom) { tmp = den << 1; |