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authorGuilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>2017-09-21 16:29:01 -0300
committerPaul E. McKenney <paulmck@linux.vnet.ibm.com>2017-10-20 11:09:32 -0700
commit5692fcc671ac8a10bfd0e75d52f0259fe767b56c (patch)
tree46b532f50defd2f014896f0287074a18f52770e9 /Documentation/memory-barriers.txt
parentd92f842bb30f52beedad63a4a850b39ca0dbc45f (diff)
downloadlinux-5692fcc671ac8a10bfd0e75d52f0259fe767b56c.tar.bz2
doc: Rewrite confusing statement about memory barriers
The "Write (or store) memory barriers" bullet of the "Variety of memory barriers" section, calls out a sequential order of stores, which is confusing since sequential ordering is not guaranteed. This commit therefore rewords to avoid mentioning a sequence of stores to clarify the intent. Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Signed-off-by: Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Diffstat (limited to 'Documentation/memory-barriers.txt')
-rw-r--r--Documentation/memory-barriers.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index f37375544d71..519940ec767f 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -383,8 +383,8 @@ Memory barriers come in four basic varieties:
to have any effect on loads.
A CPU can be viewed as committing a sequence of store operations to the
- memory system as time progresses. All stores before a write barrier will
- occur in the sequence _before_ all the stores after the write barrier.
+ memory system as time progresses. All stores _before_ a write barrier
+ will occur _before_ all the stores after the write barrier.
[!] Note that write barriers should normally be paired with read or data
dependency barriers; see the "SMP barrier pairing" subsection.