/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_NIC4_QM1_REGS_H_ #define ASIC_REG_NIC4_QM1_REGS_H_ /* ***************************************** * NIC4_QM1 (Prototype: QMAN) ***************************************** */ #define mmNIC4_QM1_GLBL_CFG0 0xDE2000 #define mmNIC4_QM1_GLBL_CFG1 0xDE2004 #define mmNIC4_QM1_GLBL_PROT 0xDE2008 #define mmNIC4_QM1_GLBL_ERR_CFG 0xDE200C #define mmNIC4_QM1_GLBL_SECURE_PROPS_0 0xDE2010 #define mmNIC4_QM1_GLBL_SECURE_PROPS_1 0xDE2014 #define mmNIC4_QM1_GLBL_SECURE_PROPS_2 0xDE2018 #define mmNIC4_QM1_GLBL_SECURE_PROPS_3 0xDE201C #define mmNIC4_QM1_GLBL_SECURE_PROPS_4 0xDE2020 #define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_0 0xDE2024 #define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_1 0xDE2028 #define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_2 0xDE202C #define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_3 0xDE2030 #define mmNIC4_QM1_GLBL_NON_SECURE_PROPS_4 0xDE2034 #define mmNIC4_QM1_GLBL_STS0 0xDE2038 #define mmNIC4_QM1_GLBL_STS1_0 0xDE2040 #define mmNIC4_QM1_GLBL_STS1_1 0xDE2044 #define mmNIC4_QM1_GLBL_STS1_2 0xDE2048 #define mmNIC4_QM1_GLBL_STS1_3 0xDE204C #define mmNIC4_QM1_GLBL_STS1_4 0xDE2050 #define mmNIC4_QM1_GLBL_MSG_EN_0 0xDE2054 #define mmNIC4_QM1_GLBL_MSG_EN_1 0xDE2058 #define mmNIC4_QM1_GLBL_MSG_EN_2 0xDE205C #define mmNIC4_QM1_GLBL_MSG_EN_3 0xDE2060 #define mmNIC4_QM1_GLBL_MSG_EN_4 0xDE2068 #define mmNIC4_QM1_PQ_BASE_LO_0 0xDE2070 #define mmNIC4_QM1_PQ_BASE_LO_1 0xDE2074 #define mmNIC4_QM1_PQ_BASE_LO_2 0xDE2078 #define mmNIC4_QM1_PQ_BASE_LO_3 0xDE207C #define mmNIC4_QM1_PQ_BASE_HI_0 0xDE2080 #define mmNIC4_QM1_PQ_BASE_HI_1 0xDE2084 #define mmNIC4_QM1_PQ_BASE_HI_2 0xDE2088 #define mmNIC4_QM1_PQ_BASE_HI_3 0xDE208C #define mmNIC4_QM1_PQ_SIZE_0 0xDE2090 #define mmNIC4_QM1_PQ_SIZE_1 0xDE2094 #define mmNIC4_QM1_PQ_SIZE_2 0xDE2098 #define mmNIC4_QM1_PQ_SIZE_3 0xDE209C #define mmNIC4_QM1_PQ_PI_0 0xDE20A0 #define mmNIC4_QM1_PQ_PI_1 0xDE20A4 #define mmNIC4_QM1_PQ_PI_2 0xDE20A8 #define mmNIC4_QM1_PQ_PI_3 0xDE20AC #define mmNIC4_QM1_PQ_CI_0 0xDE20B0 #define mmNIC4_QM1_PQ_CI_1 0xDE20B4 #define mmNIC4_QM1_PQ_CI_2 0xDE20B8 #define mmNIC4_QM1_PQ_CI_3 0xDE20BC #define mmNIC4_QM1_PQ_CFG0_0 0xDE20C0 #define mmNIC4_QM1_PQ_CFG0_1 0xDE20C4 #define mmNIC4_QM1_PQ_CFG0_2 0xDE20C8 #define mmNIC4_QM1_PQ_CFG0_3 0xDE20CC #define mmNIC4_QM1_PQ_CFG1_0 0xDE20D0 #define mmNIC4_QM1_PQ_CFG1_1 0xDE20D4 #define mmNIC4_QM1_PQ_CFG1_2 0xDE20D8 #define mmNIC4_QM1_PQ_CFG1_3 0xDE20DC #define mmNIC4_QM1_PQ_ARUSER_31_11_0 0xDE20E0 #define mmNIC4_QM1_PQ_ARUSER_31_11_1 0xDE20E4 #define mmNIC4_QM1_PQ_ARUSER_31_11_2 0xDE20E8 #define mmNIC4_QM1_PQ_ARUSER_31_11_3 0xDE20EC #define mmNIC4_QM1_PQ_STS0_0 0xDE20F0 #define mmNIC4_QM1_PQ_STS0_1 0xDE20F4 #define mmNIC4_QM1_PQ_STS0_2 0xDE20F8 #define mmNIC4_QM1_PQ_STS0_3 0xDE20FC #define mmNIC4_QM1_PQ_STS1_0 0xDE2100 #define mmNIC4_QM1_PQ_STS1_1 0xDE2104 #define mmNIC4_QM1_PQ_STS1_2 0xDE2108 #define mmNIC4_QM1_PQ_STS1_3 0xDE210C #define mmNIC4_QM1_CQ_CFG0_0 0xDE2110 #define mmNIC4_QM1_CQ_CFG0_1 0xDE2114 #define mmNIC4_QM1_CQ_CFG0_2 0xDE2118 #define mmNIC4_QM1_CQ_CFG0_3 0xDE211C #define mmNIC4_QM1_CQ_CFG0_4 0xDE2120 #define mmNIC4_QM1_CQ_CFG1_0 0xDE2124 #define mmNIC4_QM1_CQ_CFG1_1 0xDE2128 #define mmNIC4_QM1_CQ_CFG1_2 0xDE212C #define mmNIC4_QM1_CQ_CFG1_3 0xDE2130 #define mmNIC4_QM1_CQ_CFG1_4 0xDE2134 #define mmNIC4_QM1_CQ_ARUSER_31_11_0 0xDE2138 #define mmNIC4_QM1_CQ_ARUSER_31_11_1 0xDE213C #define mmNIC4_QM1_CQ_ARUSER_31_11_2 0xDE2140 #define mmNIC4_QM1_CQ_ARUSER_31_11_3 0xDE2144 #define mmNIC4_QM1_CQ_ARUSER_31_11_4 0xDE2148 #define mmNIC4_QM1_CQ_STS0_0 0xDE214C #define mmNIC4_QM1_CQ_STS0_1 0xDE2150 #define mmNIC4_QM1_CQ_STS0_2 0xDE2154 #define mmNIC4_QM1_CQ_STS0_3 0xDE2158 #define mmNIC4_QM1_CQ_STS0_4 0xDE215C #define mmNIC4_QM1_CQ_STS1_0 0xDE2160 #define mmNIC4_QM1_CQ_STS1_1 0xDE2164 #define mmNIC4_QM1_CQ_STS1_2 0xDE2168 #define mmNIC4_QM1_CQ_STS1_3 0xDE216C #define mmNIC4_QM1_CQ_STS1_4 0xDE2170 #define mmNIC4_QM1_CQ_PTR_LO_0 0xDE2174 #define mmNIC4_QM1_CQ_PTR_HI_0 0xDE2178 #define mmNIC4_QM1_CQ_TSIZE_0 0xDE217C #define mmNIC4_QM1_CQ_CTL_0 0xDE2180 #define mmNIC4_QM1_CQ_PTR_LO_1 0xDE2184 #define mmNIC4_QM1_CQ_PTR_HI_1 0xDE2188 #define mmNIC4_QM1_CQ_TSIZE_1 0xDE218C #define mmNIC4_QM1_CQ_CTL_1 0xDE2190 #define mmNIC4_QM1_CQ_PTR_LO_2 0xDE2194 #define mmNIC4_QM1_CQ_PTR_HI_2 0xDE2198 #define mmNIC4_QM1_CQ_TSIZE_2 0xDE219C #define mmNIC4_QM1_CQ_CTL_2 0xDE21A0 #define mmNIC4_QM1_CQ_PTR_LO_3 0xDE21A4 #define mmNIC4_QM1_CQ_PTR_HI_3 0xDE21A8 #define mmNIC4_QM1_CQ_TSIZE_3 0xDE21AC #define mmNIC4_QM1_CQ_CTL_3 0xDE21B0 #define mmNIC4_QM1_CQ_PTR_LO_4 0xDE21B4 #define mmNIC4_QM1_CQ_PTR_HI_4 0xDE21B8 #define mmNIC4_QM1_CQ_TSIZE_4 0xDE21BC #define mmNIC4_QM1_CQ_CTL_4 0xDE21C0 #define mmNIC4_QM1_CQ_PTR_LO_STS_0 0xDE21C4 #define mmNIC4_QM1_CQ_PTR_LO_STS_1 0xDE21C8 #define mmNIC4_QM1_CQ_PTR_LO_STS_2 0xDE21CC #define mmNIC4_QM1_CQ_PTR_LO_STS_3 0xDE21D0 #define mmNIC4_QM1_CQ_PTR_LO_STS_4 0xDE21D4 #define mmNIC4_QM1_CQ_PTR_HI_STS_0 0xDE21D8 #define mmNIC4_QM1_CQ_PTR_HI_STS_1 0xDE21DC #define mmNIC4_QM1_CQ_PTR_HI_STS_2 0xDE21E0 #define mmNIC4_QM1_CQ_PTR_HI_STS_3 0xDE21E4 #define mmNIC4_QM1_CQ_PTR_HI_STS_4 0xDE21E8 #define mmNIC4_QM1_CQ_TSIZE_STS_0 0xDE21EC #define mmNIC4_QM1_CQ_TSIZE_STS_1 0xDE21F0 #define mmNIC4_QM1_CQ_TSIZE_STS_2 0xDE21F4 #define mmNIC4_QM1_CQ_TSIZE_STS_3 0xDE21F8 #define mmNIC4_QM1_CQ_TSIZE_STS_4 0xDE21FC #define mmNIC4_QM1_CQ_CTL_STS_0 0xDE2200 #define mmNIC4_QM1_CQ_CTL_STS_1 0xDE2204 #define mmNIC4_QM1_CQ_CTL_STS_2 0xDE2208 #define mmNIC4_QM1_CQ_CTL_STS_3 0xDE220C #define mmNIC4_QM1_CQ_CTL_STS_4 0xDE2210 #define mmNIC4_QM1_CQ_IFIFO_CNT_0 0xDE2214 #define mmNIC4_QM1_CQ_IFIFO_CNT_1 0xDE2218 #define mmNIC4_QM1_CQ_IFIFO_CNT_2 0xDE221C #define mmNIC4_QM1_CQ_IFIFO_CNT_3 0xDE2220 #define mmNIC4_QM1_CQ_IFIFO_CNT_4 0xDE2224 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_0 0xDE2228 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_1 0xDE222C #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_2 0xDE2230 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_3 0xDE2234 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_LO_4 0xDE2238 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_0 0xDE223C #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_1 0xDE2240 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_2 0xDE2244 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_3 0xDE2248 #define mmNIC4_QM1_CP_MSG_BASE0_ADDR_HI_4 0xDE224C #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_0 0xDE2250 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_1 0xDE2254 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_2 0xDE2258 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_3 0xDE225C #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_LO_4 0xDE2260 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_0 0xDE2264 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_1 0xDE2268 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_2 0xDE226C #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_3 0xDE2270 #define mmNIC4_QM1_CP_MSG_BASE1_ADDR_HI_4 0xDE2274 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_0 0xDE2278 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_1 0xDE227C #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_2 0xDE2280 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_3 0xDE2284 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_LO_4 0xDE2288 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_0 0xDE228C #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_1 0xDE2290 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_2 0xDE2294 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_3 0xDE2298 #define mmNIC4_QM1_CP_MSG_BASE2_ADDR_HI_4 0xDE229C #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_0 0xDE22A0 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_1 0xDE22A4 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_2 0xDE22A8 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_3 0xDE22AC #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_LO_4 0xDE22B0 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_0 0xDE22B4 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_1 0xDE22B8 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_2 0xDE22BC #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_3 0xDE22C0 #define mmNIC4_QM1_CP_MSG_BASE3_ADDR_HI_4 0xDE22C4 #define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_0 0xDE22C8 #define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_1 0xDE22CC #define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_2 0xDE22D0 #define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_3 0xDE22D4 #define mmNIC4_QM1_CP_LDMA_TSIZE_OFFSET_4 0xDE22D8 #define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDE22E0 #define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDE22E4 #define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDE22E8 #define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDE22EC #define mmNIC4_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDE22F0 #define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDE22F4 #define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDE22F8 #define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDE22FC #define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDE2300 #define mmNIC4_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDE2304 #define mmNIC4_QM1_CP_FENCE0_RDATA_0 0xDE2308 #define mmNIC4_QM1_CP_FENCE0_RDATA_1 0xDE230C #define mmNIC4_QM1_CP_FENCE0_RDATA_2 0xDE2310 #define mmNIC4_QM1_CP_FENCE0_RDATA_3 0xDE2314 #define mmNIC4_QM1_CP_FENCE0_RDATA_4 0xDE2318 #define mmNIC4_QM1_CP_FENCE1_RDATA_0 0xDE231C #define mmNIC4_QM1_CP_FENCE1_RDATA_1 0xDE2320 #define mmNIC4_QM1_CP_FENCE1_RDATA_2 0xDE2324 #define mmNIC4_QM1_CP_FENCE1_RDATA_3 0xDE2328 #define mmNIC4_QM1_CP_FENCE1_RDATA_4 0xDE232C #define mmNIC4_QM1_CP_FENCE2_RDATA_0 0xDE2330 #define mmNIC4_QM1_CP_FENCE2_RDATA_1 0xDE2334 #define mmNIC4_QM1_CP_FENCE2_RDATA_2 0xDE2338 #define mmNIC4_QM1_CP_FENCE2_RDATA_3 0xDE233C #define mmNIC4_QM1_CP_FENCE2_RDATA_4 0xDE2340 #define mmNIC4_QM1_CP_FENCE3_RDATA_0 0xDE2344 #define mmNIC4_QM1_CP_FENCE3_RDATA_1 0xDE2348 #define mmNIC4_QM1_CP_FENCE3_RDATA_2 0xDE234C #define mmNIC4_QM1_CP_FENCE3_RDATA_3 0xDE2350 #define mmNIC4_QM1_CP_FENCE3_RDATA_4 0xDE2354 #define mmNIC4_QM1_CP_FENCE0_CNT_0 0xDE2358 #define mmNIC4_QM1_CP_FENCE0_CNT_1 0xDE235C #define mmNIC4_QM1_CP_FENCE0_CNT_2 0xDE2360 #define mmNIC4_QM1_CP_FENCE0_CNT_3 0xDE2364 #define mmNIC4_QM1_CP_FENCE0_CNT_4 0xDE2368 #define mmNIC4_QM1_CP_FENCE1_CNT_0 0xDE236C #define mmNIC4_QM1_CP_FENCE1_CNT_1 0xDE2370 #define mmNIC4_QM1_CP_FENCE1_CNT_2 0xDE2374 #define mmNIC4_QM1_CP_FENCE1_CNT_3 0xDE2378 #define mmNIC4_QM1_CP_FENCE1_CNT_4 0xDE237C #define mmNIC4_QM1_CP_FENCE2_CNT_0 0xDE2380 #define mmNIC4_QM1_CP_FENCE2_CNT_1 0xDE2384 #define mmNIC4_QM1_CP_FENCE2_CNT_2 0xDE2388 #define mmNIC4_QM1_CP_FENCE2_CNT_3 0xDE238C #define mmNIC4_QM1_CP_FENCE2_CNT_4 0xDE2390 #define mmNIC4_QM1_CP_FENCE3_CNT_0 0xDE2394 #define mmNIC4_QM1_CP_FENCE3_CNT_1 0xDE2398 #define mmNIC4_QM1_CP_FENCE3_CNT_2 0xDE239C #define mmNIC4_QM1_CP_FENCE3_CNT_3 0xDE23A0 #define mmNIC4_QM1_CP_FENCE3_CNT_4 0xDE23A4 #define mmNIC4_QM1_CP_STS_0 0xDE23A8 #define mmNIC4_QM1_CP_STS_1 0xDE23AC #define mmNIC4_QM1_CP_STS_2 0xDE23B0 #define mmNIC4_QM1_CP_STS_3 0xDE23B4 #define mmNIC4_QM1_CP_STS_4 0xDE23B8 #define mmNIC4_QM1_CP_CURRENT_INST_LO_0 0xDE23BC #define mmNIC4_QM1_CP_CURRENT_INST_LO_1 0xDE23C0 #define mmNIC4_QM1_CP_CURRENT_INST_LO_2 0xDE23C4 #define mmNIC4_QM1_CP_CURRENT_INST_LO_3 0xDE23C8 #define mmNIC4_QM1_CP_CURRENT_INST_LO_4 0xDE23CC #define mmNIC4_QM1_CP_CURRENT_INST_HI_0 0xDE23D0 #define mmNIC4_QM1_CP_CURRENT_INST_HI_1 0xDE23D4 #define mmNIC4_QM1_CP_CURRENT_INST_HI_2 0xDE23D8 #define mmNIC4_QM1_CP_CURRENT_INST_HI_3 0xDE23DC #define mmNIC4_QM1_CP_CURRENT_INST_HI_4 0xDE23E0 #define mmNIC4_QM1_CP_BARRIER_CFG_0 0xDE23F4 #define mmNIC4_QM1_CP_BARRIER_CFG_1 0xDE23F8 #define mmNIC4_QM1_CP_BARRIER_CFG_2 0xDE23FC #define mmNIC4_QM1_CP_BARRIER_CFG_3 0xDE2400 #define mmNIC4_QM1_CP_BARRIER_CFG_4 0xDE2404 #define mmNIC4_QM1_CP_DBG_0_0 0xDE2408 #define mmNIC4_QM1_CP_DBG_0_1 0xDE240C #define mmNIC4_QM1_CP_DBG_0_2 0xDE2410 #define mmNIC4_QM1_CP_DBG_0_3 0xDE2414 #define mmNIC4_QM1_CP_DBG_0_4 0xDE2418 #define mmNIC4_QM1_CP_ARUSER_31_11_0 0xDE241C #define mmNIC4_QM1_CP_ARUSER_31_11_1 0xDE2420 #define mmNIC4_QM1_CP_ARUSER_31_11_2 0xDE2424 #define mmNIC4_QM1_CP_ARUSER_31_11_3 0xDE2428 #define mmNIC4_QM1_CP_ARUSER_31_11_4 0xDE242C #define mmNIC4_QM1_CP_AWUSER_31_11_0 0xDE2430 #define mmNIC4_QM1_CP_AWUSER_31_11_1 0xDE2434 #define mmNIC4_QM1_CP_AWUSER_31_11_2 0xDE2438 #define mmNIC4_QM1_CP_AWUSER_31_11_3 0xDE243C #define mmNIC4_QM1_CP_AWUSER_31_11_4 0xDE2440 #define mmNIC4_QM1_ARB_CFG_0 0xDE2A00 #define mmNIC4_QM1_ARB_CHOISE_Q_PUSH 0xDE2A04 #define mmNIC4_QM1_ARB_WRR_WEIGHT_0 0xDE2A08 #define mmNIC4_QM1_ARB_WRR_WEIGHT_1 0xDE2A0C #define mmNIC4_QM1_ARB_WRR_WEIGHT_2 0xDE2A10 #define mmNIC4_QM1_ARB_WRR_WEIGHT_3 0xDE2A14 #define mmNIC4_QM1_ARB_CFG_1 0xDE2A18 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_0 0xDE2A20 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_1 0xDE2A24 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_2 0xDE2A28 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_3 0xDE2A2C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_4 0xDE2A30 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_5 0xDE2A34 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_6 0xDE2A38 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_7 0xDE2A3C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_8 0xDE2A40 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_9 0xDE2A44 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_10 0xDE2A48 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_11 0xDE2A4C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_12 0xDE2A50 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_13 0xDE2A54 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_14 0xDE2A58 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_15 0xDE2A5C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_16 0xDE2A60 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_17 0xDE2A64 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_18 0xDE2A68 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_19 0xDE2A6C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_20 0xDE2A70 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_21 0xDE2A74 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_22 0xDE2A78 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_23 0xDE2A7C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_24 0xDE2A80 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_25 0xDE2A84 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_26 0xDE2A88 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_27 0xDE2A8C #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_28 0xDE2A90 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_29 0xDE2A94 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_30 0xDE2A98 #define mmNIC4_QM1_ARB_MST_AVAIL_CRED_31 0xDE2A9C #define mmNIC4_QM1_ARB_MST_CRED_INC 0xDE2AA0 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xDE2AA4 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xDE2AA8 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xDE2AAC #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xDE2AB0 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xDE2AB4 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xDE2AB8 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xDE2ABC #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xDE2AC0 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xDE2AC4 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xDE2AC8 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xDE2ACC #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xDE2AD0 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xDE2AD4 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xDE2AD8 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xDE2ADC #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xDE2AE0 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xDE2AE4 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xDE2AE8 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xDE2AEC #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xDE2AF0 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xDE2AF4 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xDE2AF8 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xDE2AFC #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xDE2B00 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xDE2B04 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xDE2B08 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xDE2B0C #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xDE2B10 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xDE2B14 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xDE2B18 #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xDE2B1C #define mmNIC4_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xDE2B20 #define mmNIC4_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xDE2B28 #define mmNIC4_QM1_ARB_MST_SLAVE_EN 0xDE2B2C #define mmNIC4_QM1_ARB_MST_QUIET_PER 0xDE2B34 #define mmNIC4_QM1_ARB_SLV_CHOISE_WDT 0xDE2B38 #define mmNIC4_QM1_ARB_SLV_ID 0xDE2B3C #define mmNIC4_QM1_ARB_MSG_MAX_INFLIGHT 0xDE2B44 #define mmNIC4_QM1_ARB_MSG_AWUSER_31_11 0xDE2B48 #define mmNIC4_QM1_ARB_MSG_AWUSER_SEC_PROP 0xDE2B4C #define mmNIC4_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xDE2B50 #define mmNIC4_QM1_ARB_BASE_LO 0xDE2B54 #define mmNIC4_QM1_ARB_BASE_HI 0xDE2B58 #define mmNIC4_QM1_ARB_STATE_STS 0xDE2B80 #define mmNIC4_QM1_ARB_CHOISE_FULLNESS_STS 0xDE2B84 #define mmNIC4_QM1_ARB_MSG_STS 0xDE2B88 #define mmNIC4_QM1_ARB_SLV_CHOISE_Q_HEAD 0xDE2B8C #define mmNIC4_QM1_ARB_ERR_CAUSE 0xDE2B9C #define mmNIC4_QM1_ARB_ERR_MSG_EN 0xDE2BA0 #define mmNIC4_QM1_ARB_ERR_STS_DRP 0xDE2BA8 #define mmNIC4_QM1_ARB_MST_CRED_STS_0 0xDE2BB0 #define mmNIC4_QM1_ARB_MST_CRED_STS_1 0xDE2BB4 #define mmNIC4_QM1_ARB_MST_CRED_STS_2 0xDE2BB8 #define mmNIC4_QM1_ARB_MST_CRED_STS_3 0xDE2BBC #define mmNIC4_QM1_ARB_MST_CRED_STS_4 0xDE2BC0 #define mmNIC4_QM1_ARB_MST_CRED_STS_5 0xDE2BC4 #define mmNIC4_QM1_ARB_MST_CRED_STS_6 0xDE2BC8 #define mmNIC4_QM1_ARB_MST_CRED_STS_7 0xDE2BCC #define mmNIC4_QM1_ARB_MST_CRED_STS_8 0xDE2BD0 #define mmNIC4_QM1_ARB_MST_CRED_STS_9 0xDE2BD4 #define mmNIC4_QM1_ARB_MST_CRED_STS_10 0xDE2BD8 #define mmNIC4_QM1_ARB_MST_CRED_STS_11 0xDE2BDC #define mmNIC4_QM1_ARB_MST_CRED_STS_12 0xDE2BE0 #define mmNIC4_QM1_ARB_MST_CRED_STS_13 0xDE2BE4 #define mmNIC4_QM1_ARB_MST_CRED_STS_14 0xDE2BE8 #define mmNIC4_QM1_ARB_MST_CRED_STS_15 0xDE2BEC #define mmNIC4_QM1_ARB_MST_CRED_STS_16 0xDE2BF0 #define mmNIC4_QM1_ARB_MST_CRED_STS_17 0xDE2BF4 #define mmNIC4_QM1_ARB_MST_CRED_STS_18 0xDE2BF8 #define mmNIC4_QM1_ARB_MST_CRED_STS_19 0xDE2BFC #define mmNIC4_QM1_ARB_MST_CRED_STS_20 0xDE2C00 #define mmNIC4_QM1_ARB_MST_CRED_STS_21 0xDE2C04 #define mmNIC4_QM1_ARB_MST_CRED_STS_22 0xDE2C08 #define mmNIC4_QM1_ARB_MST_CRED_STS_23 0xDE2C0C #define mmNIC4_QM1_ARB_MST_CRED_STS_24 0xDE2C10 #define mmNIC4_QM1_ARB_MST_CRED_STS_25 0xDE2C14 #define mmNIC4_QM1_ARB_MST_CRED_STS_26 0xDE2C18 #define mmNIC4_QM1_ARB_MST_CRED_STS_27 0xDE2C1C #define mmNIC4_QM1_ARB_MST_CRED_STS_28 0xDE2C20 #define mmNIC4_QM1_ARB_MST_CRED_STS_29 0xDE2C24 #define mmNIC4_QM1_ARB_MST_CRED_STS_30 0xDE2C28 #define mmNIC4_QM1_ARB_MST_CRED_STS_31 0xDE2C2C #define mmNIC4_QM1_CGM_CFG 0xDE2C70 #define mmNIC4_QM1_CGM_STS 0xDE2C74 #define mmNIC4_QM1_CGM_CFG1 0xDE2C78 #define mmNIC4_QM1_LOCAL_RANGE_BASE 0xDE2C80 #define mmNIC4_QM1_LOCAL_RANGE_SIZE 0xDE2C84 #define mmNIC4_QM1_CSMR_STRICT_PRIO_CFG 0xDE2C90 #define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_1 0xDE2C94 #define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_0 0xDE2C98 #define mmNIC4_QM1_LBW_WR_RATE_LIM_CFG_1 0xDE2C9C #define mmNIC4_QM1_HBW_RD_RATE_LIM_CFG_0 0xDE2CA0 #define mmNIC4_QM1_GLBL_AXCACHE 0xDE2CA4 #define mmNIC4_QM1_IND_GW_APB_CFG 0xDE2CB0 #define mmNIC4_QM1_IND_GW_APB_WDATA 0xDE2CB4 #define mmNIC4_QM1_IND_GW_APB_RDATA 0xDE2CB8 #define mmNIC4_QM1_IND_GW_APB_STATUS 0xDE2CBC #define mmNIC4_QM1_GLBL_ERR_ADDR_LO 0xDE2CD0 #define mmNIC4_QM1_GLBL_ERR_ADDR_HI 0xDE2CD4 #define mmNIC4_QM1_GLBL_ERR_WDATA 0xDE2CD8 #define mmNIC4_QM1_GLBL_MEM_INIT_BUSY 0xDE2D00 #endif /* ASIC_REG_NIC4_QM1_REGS_H_ */