/* SPDX-License-Identifier: GPL-2.0 * * Copyright 2016-2018 HabanaLabs, Ltd. * All Rights Reserved. * */ /************************************ ** This is an auto-generated file ** ** DO NOT EDIT BELOW ** ************************************/ #ifndef ASIC_REG_DMA5_QM_REGS_H_ #define ASIC_REG_DMA5_QM_REGS_H_ /* ***************************************** * DMA5_QM (Prototype: QMAN) ***************************************** */ #define mmDMA5_QM_GLBL_CFG0 0x5A8000 #define mmDMA5_QM_GLBL_CFG1 0x5A8004 #define mmDMA5_QM_GLBL_PROT 0x5A8008 #define mmDMA5_QM_GLBL_ERR_CFG 0x5A800C #define mmDMA5_QM_GLBL_SECURE_PROPS_0 0x5A8010 #define mmDMA5_QM_GLBL_SECURE_PROPS_1 0x5A8014 #define mmDMA5_QM_GLBL_SECURE_PROPS_2 0x5A8018 #define mmDMA5_QM_GLBL_SECURE_PROPS_3 0x5A801C #define mmDMA5_QM_GLBL_SECURE_PROPS_4 0x5A8020 #define mmDMA5_QM_GLBL_NON_SECURE_PROPS_0 0x5A8024 #define mmDMA5_QM_GLBL_NON_SECURE_PROPS_1 0x5A8028 #define mmDMA5_QM_GLBL_NON_SECURE_PROPS_2 0x5A802C #define mmDMA5_QM_GLBL_NON_SECURE_PROPS_3 0x5A8030 #define mmDMA5_QM_GLBL_NON_SECURE_PROPS_4 0x5A8034 #define mmDMA5_QM_GLBL_STS0 0x5A8038 #define mmDMA5_QM_GLBL_STS1_0 0x5A8040 #define mmDMA5_QM_GLBL_STS1_1 0x5A8044 #define mmDMA5_QM_GLBL_STS1_2 0x5A8048 #define mmDMA5_QM_GLBL_STS1_3 0x5A804C #define mmDMA5_QM_GLBL_STS1_4 0x5A8050 #define mmDMA5_QM_GLBL_MSG_EN_0 0x5A8054 #define mmDMA5_QM_GLBL_MSG_EN_1 0x5A8058 #define mmDMA5_QM_GLBL_MSG_EN_2 0x5A805C #define mmDMA5_QM_GLBL_MSG_EN_3 0x5A8060 #define mmDMA5_QM_GLBL_MSG_EN_4 0x5A8068 #define mmDMA5_QM_PQ_BASE_LO_0 0x5A8070 #define mmDMA5_QM_PQ_BASE_LO_1 0x5A8074 #define mmDMA5_QM_PQ_BASE_LO_2 0x5A8078 #define mmDMA5_QM_PQ_BASE_LO_3 0x5A807C #define mmDMA5_QM_PQ_BASE_HI_0 0x5A8080 #define mmDMA5_QM_PQ_BASE_HI_1 0x5A8084 #define mmDMA5_QM_PQ_BASE_HI_2 0x5A8088 #define mmDMA5_QM_PQ_BASE_HI_3 0x5A808C #define mmDMA5_QM_PQ_SIZE_0 0x5A8090 #define mmDMA5_QM_PQ_SIZE_1 0x5A8094 #define mmDMA5_QM_PQ_SIZE_2 0x5A8098 #define mmDMA5_QM_PQ_SIZE_3 0x5A809C #define mmDMA5_QM_PQ_PI_0 0x5A80A0 #define mmDMA5_QM_PQ_PI_1 0x5A80A4 #define mmDMA5_QM_PQ_PI_2 0x5A80A8 #define mmDMA5_QM_PQ_PI_3 0x5A80AC #define mmDMA5_QM_PQ_CI_0 0x5A80B0 #define mmDMA5_QM_PQ_CI_1 0x5A80B4 #define mmDMA5_QM_PQ_CI_2 0x5A80B8 #define mmDMA5_QM_PQ_CI_3 0x5A80BC #define mmDMA5_QM_PQ_CFG0_0 0x5A80C0 #define mmDMA5_QM_PQ_CFG0_1 0x5A80C4 #define mmDMA5_QM_PQ_CFG0_2 0x5A80C8 #define mmDMA5_QM_PQ_CFG0_3 0x5A80CC #define mmDMA5_QM_PQ_CFG1_0 0x5A80D0 #define mmDMA5_QM_PQ_CFG1_1 0x5A80D4 #define mmDMA5_QM_PQ_CFG1_2 0x5A80D8 #define mmDMA5_QM_PQ_CFG1_3 0x5A80DC #define mmDMA5_QM_PQ_ARUSER_31_11_0 0x5A80E0 #define mmDMA5_QM_PQ_ARUSER_31_11_1 0x5A80E4 #define mmDMA5_QM_PQ_ARUSER_31_11_2 0x5A80E8 #define mmDMA5_QM_PQ_ARUSER_31_11_3 0x5A80EC #define mmDMA5_QM_PQ_STS0_0 0x5A80F0 #define mmDMA5_QM_PQ_STS0_1 0x5A80F4 #define mmDMA5_QM_PQ_STS0_2 0x5A80F8 #define mmDMA5_QM_PQ_STS0_3 0x5A80FC #define mmDMA5_QM_PQ_STS1_0 0x5A8100 #define mmDMA5_QM_PQ_STS1_1 0x5A8104 #define mmDMA5_QM_PQ_STS1_2 0x5A8108 #define mmDMA5_QM_PQ_STS1_3 0x5A810C #define mmDMA5_QM_CQ_CFG0_0 0x5A8110 #define mmDMA5_QM_CQ_CFG0_1 0x5A8114 #define mmDMA5_QM_CQ_CFG0_2 0x5A8118 #define mmDMA5_QM_CQ_CFG0_3 0x5A811C #define mmDMA5_QM_CQ_CFG0_4 0x5A8120 #define mmDMA5_QM_CQ_CFG1_0 0x5A8124 #define mmDMA5_QM_CQ_CFG1_1 0x5A8128 #define mmDMA5_QM_CQ_CFG1_2 0x5A812C #define mmDMA5_QM_CQ_CFG1_3 0x5A8130 #define mmDMA5_QM_CQ_CFG1_4 0x5A8134 #define mmDMA5_QM_CQ_ARUSER_31_11_0 0x5A8138 #define mmDMA5_QM_CQ_ARUSER_31_11_1 0x5A813C #define mmDMA5_QM_CQ_ARUSER_31_11_2 0x5A8140 #define mmDMA5_QM_CQ_ARUSER_31_11_3 0x5A8144 #define mmDMA5_QM_CQ_ARUSER_31_11_4 0x5A8148 #define mmDMA5_QM_CQ_STS0_0 0x5A814C #define mmDMA5_QM_CQ_STS0_1 0x5A8150 #define mmDMA5_QM_CQ_STS0_2 0x5A8154 #define mmDMA5_QM_CQ_STS0_3 0x5A8158 #define mmDMA5_QM_CQ_STS0_4 0x5A815C #define mmDMA5_QM_CQ_STS1_0 0x5A8160 #define mmDMA5_QM_CQ_STS1_1 0x5A8164 #define mmDMA5_QM_CQ_STS1_2 0x5A8168 #define mmDMA5_QM_CQ_STS1_3 0x5A816C #define mmDMA5_QM_CQ_STS1_4 0x5A8170 #define mmDMA5_QM_CQ_PTR_LO_0 0x5A8174 #define mmDMA5_QM_CQ_PTR_HI_0 0x5A8178 #define mmDMA5_QM_CQ_TSIZE_0 0x5A817C #define mmDMA5_QM_CQ_CTL_0 0x5A8180 #define mmDMA5_QM_CQ_PTR_LO_1 0x5A8184 #define mmDMA5_QM_CQ_PTR_HI_1 0x5A8188 #define mmDMA5_QM_CQ_TSIZE_1 0x5A818C #define mmDMA5_QM_CQ_CTL_1 0x5A8190 #define mmDMA5_QM_CQ_PTR_LO_2 0x5A8194 #define mmDMA5_QM_CQ_PTR_HI_2 0x5A8198 #define mmDMA5_QM_CQ_TSIZE_2 0x5A819C #define mmDMA5_QM_CQ_CTL_2 0x5A81A0 #define mmDMA5_QM_CQ_PTR_LO_3 0x5A81A4 #define mmDMA5_QM_CQ_PTR_HI_3 0x5A81A8 #define mmDMA5_QM_CQ_TSIZE_3 0x5A81AC #define mmDMA5_QM_CQ_CTL_3 0x5A81B0 #define mmDMA5_QM_CQ_PTR_LO_4 0x5A81B4 #define mmDMA5_QM_CQ_PTR_HI_4 0x5A81B8 #define mmDMA5_QM_CQ_TSIZE_4 0x5A81BC #define mmDMA5_QM_CQ_CTL_4 0x5A81C0 #define mmDMA5_QM_CQ_PTR_LO_STS_0 0x5A81C4 #define mmDMA5_QM_CQ_PTR_LO_STS_1 0x5A81C8 #define mmDMA5_QM_CQ_PTR_LO_STS_2 0x5A81CC #define mmDMA5_QM_CQ_PTR_LO_STS_3 0x5A81D0 #define mmDMA5_QM_CQ_PTR_LO_STS_4 0x5A81D4 #define mmDMA5_QM_CQ_PTR_HI_STS_0 0x5A81D8 #define mmDMA5_QM_CQ_PTR_HI_STS_1 0x5A81DC #define mmDMA5_QM_CQ_PTR_HI_STS_2 0x5A81E0 #define mmDMA5_QM_CQ_PTR_HI_STS_3 0x5A81E4 #define mmDMA5_QM_CQ_PTR_HI_STS_4 0x5A81E8 #define mmDMA5_QM_CQ_TSIZE_STS_0 0x5A81EC #define mmDMA5_QM_CQ_TSIZE_STS_1 0x5A81F0 #define mmDMA5_QM_CQ_TSIZE_STS_2 0x5A81F4 #define mmDMA5_QM_CQ_TSIZE_STS_3 0x5A81F8 #define mmDMA5_QM_CQ_TSIZE_STS_4 0x5A81FC #define mmDMA5_QM_CQ_CTL_STS_0 0x5A8200 #define mmDMA5_QM_CQ_CTL_STS_1 0x5A8204 #define mmDMA5_QM_CQ_CTL_STS_2 0x5A8208 #define mmDMA5_QM_CQ_CTL_STS_3 0x5A820C #define mmDMA5_QM_CQ_CTL_STS_4 0x5A8210 #define mmDMA5_QM_CQ_IFIFO_CNT_0 0x5A8214 #define mmDMA5_QM_CQ_IFIFO_CNT_1 0x5A8218 #define mmDMA5_QM_CQ_IFIFO_CNT_2 0x5A821C #define mmDMA5_QM_CQ_IFIFO_CNT_3 0x5A8220 #define mmDMA5_QM_CQ_IFIFO_CNT_4 0x5A8224 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_0 0x5A8228 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_1 0x5A822C #define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_2 0x5A8230 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_3 0x5A8234 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_LO_4 0x5A8238 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_0 0x5A823C #define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_1 0x5A8240 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_2 0x5A8244 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_3 0x5A8248 #define mmDMA5_QM_CP_MSG_BASE0_ADDR_HI_4 0x5A824C #define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_0 0x5A8250 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_1 0x5A8254 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_2 0x5A8258 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_3 0x5A825C #define mmDMA5_QM_CP_MSG_BASE1_ADDR_LO_4 0x5A8260 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_0 0x5A8264 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_1 0x5A8268 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_2 0x5A826C #define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_3 0x5A8270 #define mmDMA5_QM_CP_MSG_BASE1_ADDR_HI_4 0x5A8274 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_0 0x5A8278 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_1 0x5A827C #define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_2 0x5A8280 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_3 0x5A8284 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_LO_4 0x5A8288 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_0 0x5A828C #define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_1 0x5A8290 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_2 0x5A8294 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_3 0x5A8298 #define mmDMA5_QM_CP_MSG_BASE2_ADDR_HI_4 0x5A829C #define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_0 0x5A82A0 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_1 0x5A82A4 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_2 0x5A82A8 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_3 0x5A82AC #define mmDMA5_QM_CP_MSG_BASE3_ADDR_LO_4 0x5A82B0 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_0 0x5A82B4 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_1 0x5A82B8 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_2 0x5A82BC #define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_3 0x5A82C0 #define mmDMA5_QM_CP_MSG_BASE3_ADDR_HI_4 0x5A82C4 #define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_0 0x5A82C8 #define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_1 0x5A82CC #define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_2 0x5A82D0 #define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_3 0x5A82D4 #define mmDMA5_QM_CP_LDMA_TSIZE_OFFSET_4 0x5A82D8 #define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5A82E0 #define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5A82E4 #define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5A82E8 #define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5A82EC #define mmDMA5_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5A82F0 #define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5A82F4 #define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5A82F8 #define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5A82FC #define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5A8300 #define mmDMA5_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5A8304 #define mmDMA5_QM_CP_FENCE0_RDATA_0 0x5A8308 #define mmDMA5_QM_CP_FENCE0_RDATA_1 0x5A830C #define mmDMA5_QM_CP_FENCE0_RDATA_2 0x5A8310 #define mmDMA5_QM_CP_FENCE0_RDATA_3 0x5A8314 #define mmDMA5_QM_CP_FENCE0_RDATA_4 0x5A8318 #define mmDMA5_QM_CP_FENCE1_RDATA_0 0x5A831C #define mmDMA5_QM_CP_FENCE1_RDATA_1 0x5A8320 #define mmDMA5_QM_CP_FENCE1_RDATA_2 0x5A8324 #define mmDMA5_QM_CP_FENCE1_RDATA_3 0x5A8328 #define mmDMA5_QM_CP_FENCE1_RDATA_4 0x5A832C #define mmDMA5_QM_CP_FENCE2_RDATA_0 0x5A8330 #define mmDMA5_QM_CP_FENCE2_RDATA_1 0x5A8334 #define mmDMA5_QM_CP_FENCE2_RDATA_2 0x5A8338 #define mmDMA5_QM_CP_FENCE2_RDATA_3 0x5A833C #define mmDMA5_QM_CP_FENCE2_RDATA_4 0x5A8340 #define mmDMA5_QM_CP_FENCE3_RDATA_0 0x5A8344 #define mmDMA5_QM_CP_FENCE3_RDATA_1 0x5A8348 #define mmDMA5_QM_CP_FENCE3_RDATA_2 0x5A834C #define mmDMA5_QM_CP_FENCE3_RDATA_3 0x5A8350 #define mmDMA5_QM_CP_FENCE3_RDATA_4 0x5A8354 #define mmDMA5_QM_CP_FENCE0_CNT_0 0x5A8358 #define mmDMA5_QM_CP_FENCE0_CNT_1 0x5A835C #define mmDMA5_QM_CP_FENCE0_CNT_2 0x5A8360 #define mmDMA5_QM_CP_FENCE0_CNT_3 0x5A8364 #define mmDMA5_QM_CP_FENCE0_CNT_4 0x5A8368 #define mmDMA5_QM_CP_FENCE1_CNT_0 0x5A836C #define mmDMA5_QM_CP_FENCE1_CNT_1 0x5A8370 #define mmDMA5_QM_CP_FENCE1_CNT_2 0x5A8374 #define mmDMA5_QM_CP_FENCE1_CNT_3 0x5A8378 #define mmDMA5_QM_CP_FENCE1_CNT_4 0x5A837C #define mmDMA5_QM_CP_FENCE2_CNT_0 0x5A8380 #define mmDMA5_QM_CP_FENCE2_CNT_1 0x5A8384 #define mmDMA5_QM_CP_FENCE2_CNT_2 0x5A8388 #define mmDMA5_QM_CP_FENCE2_CNT_3 0x5A838C #define mmDMA5_QM_CP_FENCE2_CNT_4 0x5A8390 #define mmDMA5_QM_CP_FENCE3_CNT_0 0x5A8394 #define mmDMA5_QM_CP_FENCE3_CNT_1 0x5A8398 #define mmDMA5_QM_CP_FENCE3_CNT_2 0x5A839C #define mmDMA5_QM_CP_FENCE3_CNT_3 0x5A83A0 #define mmDMA5_QM_CP_FENCE3_CNT_4 0x5A83A4 #define mmDMA5_QM_CP_STS_0 0x5A83A8 #define mmDMA5_QM_CP_STS_1 0x5A83AC #define mmDMA5_QM_CP_STS_2 0x5A83B0 #define mmDMA5_QM_CP_STS_3 0x5A83B4 #define mmDMA5_QM_CP_STS_4 0x5A83B8 #define mmDMA5_QM_CP_CURRENT_INST_LO_0 0x5A83BC #define mmDMA5_QM_CP_CURRENT_INST_LO_1 0x5A83C0 #define mmDMA5_QM_CP_CURRENT_INST_LO_2 0x5A83C4 #define mmDMA5_QM_CP_CURRENT_INST_LO_3 0x5A83C8 #define mmDMA5_QM_CP_CURRENT_INST_LO_4 0x5A83CC #define mmDMA5_QM_CP_CURRENT_INST_HI_0 0x5A83D0 #define mmDMA5_QM_CP_CURRENT_INST_HI_1 0x5A83D4 #define mmDMA5_QM_CP_CURRENT_INST_HI_2 0x5A83D8 #define mmDMA5_QM_CP_CURRENT_INST_HI_3 0x5A83DC #define mmDMA5_QM_CP_CURRENT_INST_HI_4 0x5A83E0 #define mmDMA5_QM_CP_BARRIER_CFG_0 0x5A83F4 #define mmDMA5_QM_CP_BARRIER_CFG_1 0x5A83F8 #define mmDMA5_QM_CP_BARRIER_CFG_2 0x5A83FC #define mmDMA5_QM_CP_BARRIER_CFG_3 0x5A8400 #define mmDMA5_QM_CP_BARRIER_CFG_4 0x5A8404 #define mmDMA5_QM_CP_DBG_0_0 0x5A8408 #define mmDMA5_QM_CP_DBG_0_1 0x5A840C #define mmDMA5_QM_CP_DBG_0_2 0x5A8410 #define mmDMA5_QM_CP_DBG_0_3 0x5A8414 #define mmDMA5_QM_CP_DBG_0_4 0x5A8418 #define mmDMA5_QM_CP_ARUSER_31_11_0 0x5A841C #define mmDMA5_QM_CP_ARUSER_31_11_1 0x5A8420 #define mmDMA5_QM_CP_ARUSER_31_11_2 0x5A8424 #define mmDMA5_QM_CP_ARUSER_31_11_3 0x5A8428 #define mmDMA5_QM_CP_ARUSER_31_11_4 0x5A842C #define mmDMA5_QM_CP_AWUSER_31_11_0 0x5A8430 #define mmDMA5_QM_CP_AWUSER_31_11_1 0x5A8434 #define mmDMA5_QM_CP_AWUSER_31_11_2 0x5A8438 #define mmDMA5_QM_CP_AWUSER_31_11_3 0x5A843C #define mmDMA5_QM_CP_AWUSER_31_11_4 0x5A8440 #define mmDMA5_QM_ARB_CFG_0 0x5A8A00 #define mmDMA5_QM_ARB_CHOISE_Q_PUSH 0x5A8A04 #define mmDMA5_QM_ARB_WRR_WEIGHT_0 0x5A8A08 #define mmDMA5_QM_ARB_WRR_WEIGHT_1 0x5A8A0C #define mmDMA5_QM_ARB_WRR_WEIGHT_2 0x5A8A10 #define mmDMA5_QM_ARB_WRR_WEIGHT_3 0x5A8A14 #define mmDMA5_QM_ARB_CFG_1 0x5A8A18 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_0 0x5A8A20 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_1 0x5A8A24 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_2 0x5A8A28 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_3 0x5A8A2C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_4 0x5A8A30 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_5 0x5A8A34 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_6 0x5A8A38 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_7 0x5A8A3C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_8 0x5A8A40 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_9 0x5A8A44 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_10 0x5A8A48 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_11 0x5A8A4C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_12 0x5A8A50 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_13 0x5A8A54 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_14 0x5A8A58 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_15 0x5A8A5C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_16 0x5A8A60 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_17 0x5A8A64 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_18 0x5A8A68 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_19 0x5A8A6C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_20 0x5A8A70 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_21 0x5A8A74 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_22 0x5A8A78 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_23 0x5A8A7C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_24 0x5A8A80 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_25 0x5A8A84 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_26 0x5A8A88 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_27 0x5A8A8C #define mmDMA5_QM_ARB_MST_AVAIL_CRED_28 0x5A8A90 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_29 0x5A8A94 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_30 0x5A8A98 #define mmDMA5_QM_ARB_MST_AVAIL_CRED_31 0x5A8A9C #define mmDMA5_QM_ARB_MST_CRED_INC 0x5A8AA0 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5A8AA4 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5A8AA8 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5A8AAC #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5A8AB0 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5A8AB4 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5A8AB8 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5A8ABC #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5A8AC0 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5A8AC4 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5A8AC8 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5A8ACC #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5A8AD0 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5A8AD4 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5A8AD8 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5A8ADC #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5A8AE0 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5A8AE4 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5A8AE8 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5A8AEC #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5A8AF0 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5A8AF4 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5A8AF8 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5A8AFC #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5A8B00 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5A8B04 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5A8B08 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5A8B0C #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5A8B10 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5A8B14 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5A8B18 #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5A8B1C #define mmDMA5_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5A8B20 #define mmDMA5_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5A8B28 #define mmDMA5_QM_ARB_MST_SLAVE_EN 0x5A8B2C #define mmDMA5_QM_ARB_MST_QUIET_PER 0x5A8B34 #define mmDMA5_QM_ARB_SLV_CHOISE_WDT 0x5A8B38 #define mmDMA5_QM_ARB_SLV_ID 0x5A8B3C #define mmDMA5_QM_ARB_MSG_MAX_INFLIGHT 0x5A8B44 #define mmDMA5_QM_ARB_MSG_AWUSER_31_11 0x5A8B48 #define mmDMA5_QM_ARB_MSG_AWUSER_SEC_PROP 0x5A8B4C #define mmDMA5_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5A8B50 #define mmDMA5_QM_ARB_BASE_LO 0x5A8B54 #define mmDMA5_QM_ARB_BASE_HI 0x5A8B58 #define mmDMA5_QM_ARB_STATE_STS 0x5A8B80 #define mmDMA5_QM_ARB_CHOISE_FULLNESS_STS 0x5A8B84 #define mmDMA5_QM_ARB_MSG_STS 0x5A8B88 #define mmDMA5_QM_ARB_SLV_CHOISE_Q_HEAD 0x5A8B8C #define mmDMA5_QM_ARB_ERR_CAUSE 0x5A8B9C #define mmDMA5_QM_ARB_ERR_MSG_EN 0x5A8BA0 #define mmDMA5_QM_ARB_ERR_STS_DRP 0x5A8BA8 #define mmDMA5_QM_ARB_MST_CRED_STS_0 0x5A8BB0 #define mmDMA5_QM_ARB_MST_CRED_STS_1 0x5A8BB4 #define mmDMA5_QM_ARB_MST_CRED_STS_2 0x5A8BB8 #define mmDMA5_QM_ARB_MST_CRED_STS_3 0x5A8BBC #define mmDMA5_QM_ARB_MST_CRED_STS_4 0x5A8BC0 #define mmDMA5_QM_ARB_MST_CRED_STS_5 0x5A8BC4 #define mmDMA5_QM_ARB_MST_CRED_STS_6 0x5A8BC8 #define mmDMA5_QM_ARB_MST_CRED_STS_7 0x5A8BCC #define mmDMA5_QM_ARB_MST_CRED_STS_8 0x5A8BD0 #define mmDMA5_QM_ARB_MST_CRED_STS_9 0x5A8BD4 #define mmDMA5_QM_ARB_MST_CRED_STS_10 0x5A8BD8 #define mmDMA5_QM_ARB_MST_CRED_STS_11 0x5A8BDC #define mmDMA5_QM_ARB_MST_CRED_STS_12 0x5A8BE0 #define mmDMA5_QM_ARB_MST_CRED_STS_13 0x5A8BE4 #define mmDMA5_QM_ARB_MST_CRED_STS_14 0x5A8BE8 #define mmDMA5_QM_ARB_MST_CRED_STS_15 0x5A8BEC #define mmDMA5_QM_ARB_MST_CRED_STS_16 0x5A8BF0 #define mmDMA5_QM_ARB_MST_CRED_STS_17 0x5A8BF4 #define mmDMA5_QM_ARB_MST_CRED_STS_18 0x5A8BF8 #define mmDMA5_QM_ARB_MST_CRED_STS_19 0x5A8BFC #define mmDMA5_QM_ARB_MST_CRED_STS_20 0x5A8C00 #define mmDMA5_QM_ARB_MST_CRED_STS_21 0x5A8C04 #define mmDMA5_QM_ARB_MST_CRED_STS_22 0x5A8C08 #define mmDMA5_QM_ARB_MST_CRED_STS_23 0x5A8C0C #define mmDMA5_QM_ARB_MST_CRED_STS_24 0x5A8C10 #define mmDMA5_QM_ARB_MST_CRED_STS_25 0x5A8C14 #define mmDMA5_QM_ARB_MST_CRED_STS_26 0x5A8C18 #define mmDMA5_QM_ARB_MST_CRED_STS_27 0x5A8C1C #define mmDMA5_QM_ARB_MST_CRED_STS_28 0x5A8C20 #define mmDMA5_QM_ARB_MST_CRED_STS_29 0x5A8C24 #define mmDMA5_QM_ARB_MST_CRED_STS_30 0x5A8C28 #define mmDMA5_QM_ARB_MST_CRED_STS_31 0x5A8C2C #define mmDMA5_QM_CGM_CFG 0x5A8C70 #define mmDMA5_QM_CGM_STS 0x5A8C74 #define mmDMA5_QM_CGM_CFG1 0x5A8C78 #define mmDMA5_QM_LOCAL_RANGE_BASE 0x5A8C80 #define mmDMA5_QM_LOCAL_RANGE_SIZE 0x5A8C84 #define mmDMA5_QM_CSMR_STRICT_PRIO_CFG 0x5A8C90 #define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_1 0x5A8C94 #define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_0 0x5A8C98 #define mmDMA5_QM_LBW_WR_RATE_LIM_CFG_1 0x5A8C9C #define mmDMA5_QM_HBW_RD_RATE_LIM_CFG_0 0x5A8CA0 #define mmDMA5_QM_GLBL_AXCACHE 0x5A8CA4 #define mmDMA5_QM_IND_GW_APB_CFG 0x5A8CB0 #define mmDMA5_QM_IND_GW_APB_WDATA 0x5A8CB4 #define mmDMA5_QM_IND_GW_APB_RDATA 0x5A8CB8 #define mmDMA5_QM_IND_GW_APB_STATUS 0x5A8CBC #define mmDMA5_QM_GLBL_ERR_ADDR_LO 0x5A8CD0 #define mmDMA5_QM_GLBL_ERR_ADDR_HI 0x5A8CD4 #define mmDMA5_QM_GLBL_ERR_WDATA 0x5A8CD8 #define mmDMA5_QM_GLBL_MEM_INIT_BUSY 0x5A8D00 #endif /* ASIC_REG_DMA5_QM_REGS_H_ */