# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Synopsys DWC PCIe RP/EP controller

maintainers:
  - Jingoo Han <jingoohan1@gmail.com>
  - Gustavo Pimentel <gustavo.pimentel@synopsys.com>

description:
  Generic Synopsys DesignWare PCIe Root Port and Endpoint controller
  properties.

select: false

properties:
  reg:
    description:
      DWC PCIe CSR space is normally accessed over the dedicated Data Bus
      Interface - DBI. In accordance with the reference manual the register
      configuration space belongs to the Configuration-Dependent Module (CDM)
      and is split up into several sub-parts Standard PCIe configuration
      space, Port Logic Registers (PL), Shadow Config-space Registers,
      iATU/eDMA registers. The particular sub-space is selected by the
      CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
      configuration provides a flexible interface for the system engineers to
      either map the particular space at a desired MMIO address or just leave
      them in a contiguous memory space if pure Native or AXI Bridge DBI access
      is selected. Note the PCIe CFG-space, PL and Shadow registers are
      specific for each activated function, while the rest of the sub-spaces
      are common for all of them (if there are more than one).
    minItems: 2
    maxItems: 6

  reg-names:
    minItems: 2
    maxItems: 6

  interrupts:
    description:
      There are two main sub-blocks which are normally capable of
      generating interrupts. It's System Information Interface and MSI
      interface. While the former one has some common for the Host and
      Endpoint controllers IRQ-signals, the later interface is obviously
      Root Complex specific since it's responsible for the incoming MSI
      messages signalling. The System Information IRQ signals are mainly
      responsible for reporting the generic PCIe hierarchy and Root
      Complex events like VPD IO request, general AER, PME, Hot-plug, link
      bandwidth change, link equalization request, INTx asserted/deasserted
      Message detection, embedded DMA Tx/Rx/Error.
    minItems: 1
    maxItems: 26

  interrupt-names:
    minItems: 1
    maxItems: 26

  phys:
    description:
      There can be up to the number of possible lanes PHYs specified placed in
      the phandle array in the line-based order. Obviously each the specified
      PHYs are supposed to be able to work in the PCIe mode with a speed
      implied by the DWC PCIe controller they are attached to.
    minItems: 1
    maxItems: 16

  phy-names:
    minItems: 1
    maxItems: 16
    oneOf:
      - description: Generic PHY names
        items:
          pattern: '^pcie[0-9]+$'
      - description:
          Vendor-specific PHY names. Consider using the generic
          names above for new bindings.
        items:
          oneOf:
            - pattern: '^pcie(-?phy[0-9]*)?$'
            - pattern: '^p2u-[0-7]$'

  reset-gpio:
    deprecated: true
    description:
      Reference to the GPIO-controlled PERST# signal. It is used to reset all
      the peripheral devices available on the PCIe bus.
    maxItems: 1

  reset-gpios:
    description:
      Reference to the GPIO-controlled PERST# signal. It is used to reset all
      the peripheral devices available on the PCIe bus.
    maxItems: 1

  max-link-speed:
    maximum: 5

  num-lanes:
    description:
      Number of PCIe link lanes to use. Can be omitted if the already brought
      up link is supposed to be preserved.
    maximum: 16

  num-ob-windows:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of outbound address translation windows. This parameter can be
      auto-detected based on the iATU memory writability. So there is no
      point in having a dedicated DT-property for it.
    maximum: 256

  num-ib-windows:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of inbound address translation windows. In the same way as
      for the outbound AT windows, this parameter can be auto-detected based
      on the iATU memory writability. There is no point having a dedicated
      DT-property for it either.
    maximum: 256

  num-viewport:
    $ref: /schemas/types.yaml#/definitions/uint32
    deprecated: true
    description:
      Number of outbound view ports configured in hardware. It's the same as
      the number of outbound AT windows.
    maximum: 256

  snps,enable-cdm-check:
    $ref: /schemas/types.yaml#/definitions/flag
    description:
      Enable automatic checking of CDM (Configuration Dependent Module)
      registers for data corruption. CDM registers include standard PCIe
      configuration space registers, Port Logic registers, DMA and iATU
      registers. This feature has been available since DWC PCIe v4.80a.

additionalProperties: true

...