From b25658ed7d24cd8b1f9a72148e80e216b6a0c17a Mon Sep 17 00:00:00 2001 From: Jörg Krause Date: Fri, 13 Jan 2017 21:44:28 +0100 Subject: ASoC: mxs-saif: fix setting SAIF1 register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If SAIF0 is used in master and SAIF1 in slave mode setting the SAIF1 register in mxs_saif_set_dai_fmt() does not have any effect on the interface as the clk gate needs to be cleared before the register can be written. Signed-off-by: Jörg Krause Signed-off-by: Mark Brown --- sound/soc/mxs/mxs-saif.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'sound') diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c index a002ab892772..9012a2036131 100644 --- a/sound/soc/mxs/mxs-saif.c +++ b/sound/soc/mxs/mxs-saif.c @@ -299,6 +299,16 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) return -EBUSY; } + /* If SAIF1 is configured as slave, the clk gate needs to be cleared + * before the register can be written. + */ + if (saif->id != saif->master_id) { + __raw_writel(BM_SAIF_CTRL_SFTRST, + saif->base + SAIF_CTRL + MXS_CLR_ADDR); + __raw_writel(BM_SAIF_CTRL_CLKGATE, + saif->base + SAIF_CTRL + MXS_CLR_ADDR); + } + scr0 = __raw_readl(saif->base + SAIF_CTRL); scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; -- cgit v1.2.3 From bcb8c270829a639b8b838809d7c2b540e65f4e01 Mon Sep 17 00:00:00 2001 From: Jörg Krause Date: Fri, 13 Jan 2017 21:44:27 +0100 Subject: ASoC: mxs-saif: fix setting master base rate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SAIF base oversample rates are either 512*fs or 384*fs. An additional divider exists within the SAIF to generate sub-multiples of these two base rates if MCLK is required by the codec. * The sub-rates for the 512x base rate are: 256x, 128x, 64x, and 32x. * The sub-rates for the 384x base rate are: 192x, 96x, and 48x. Setting the base rate depending on the modulo operation with 32 and 48 give wrong results for some mclk. If mclk=18.432MHz both modulo operations results in 0. As testing the result with 32 is done first, a wrong base rate of 512*fs is set instead of the correct 384*fs. Fix this by setting the base rate depending on the calculated sub-rate. Signed-off-by: Jörg Krause Signed-off-by: Mark Brown --- sound/soc/mxs/mxs-saif.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) (limited to 'sound') diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c index 9012a2036131..b42f301c6b96 100644 --- a/sound/soc/mxs/mxs-saif.c +++ b/sound/soc/mxs/mxs-saif.c @@ -119,23 +119,33 @@ static int mxs_saif_set_clk(struct mxs_saif *saif, * Set SAIF clock * * The SAIF clock should be either 384*fs or 512*fs. - * If MCLK is used, the SAIF clk ratio need to match mclk ratio. - * For 32x mclk, set saif clk as 512*fs. - * For 48x mclk, set saif clk as 384*fs. + * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. + * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. + * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. * * If MCLK is not used, we just set saif clk to 512*fs. */ clk_prepare_enable(master_saif->clk); if (master_saif->mclk_in_use) { - if (mclk % 32 == 0) { + switch (mclk / rate) { + case 32: + case 64: + case 128: + case 256: + case 512: scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; ret = clk_set_rate(master_saif->clk, 512 * rate); - } else if (mclk % 48 == 0) { + break; + case 48: + case 96: + case 192: + case 384: scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; ret = clk_set_rate(master_saif->clk, 384 * rate); - } else { - /* SAIF MCLK should be either 32x or 48x */ + break; + default: + /* SAIF MCLK should be a sub-rate of 512x or 384x */ clk_disable_unprepare(master_saif->clk); return -EINVAL; } -- cgit v1.2.3 From ebad64d19377957976963f99ce1fcf2f09796357 Mon Sep 17 00:00:00 2001 From: Mylène Josserand Date: Tue, 17 Jan 2017 15:02:21 +0100 Subject: ASoC: sun4i-i2s: Increase DMA max burst to 8 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As done previously for sun4i-codec, the DMA maxburst of 4 is not supported by every SoCs so the DMA controller engine returns "unsupported value". As a maxburst of 8 is supported by all variants, this patch increases it to 8. For more details, see commit from Chen-Yu Tsai: commit 730e2dd0cbc7 ("ASoC: sun4i-codec: Increase DMA max burst to 8") Signed-off-by: Mylène Josserand Acked-by: Maxime Ripard Signed-off-by: Mark Brown --- sound/soc/sunxi/sun4i-i2s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index f24d19526603..4237323ef594 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -694,10 +694,10 @@ static int sun4i_i2s_probe(struct platform_device *pdev) } i2s->playback_dma_data.addr = res->start + SUN4I_I2S_FIFO_TX_REG; - i2s->playback_dma_data.maxburst = 4; + i2s->playback_dma_data.maxburst = 8; i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG; - i2s->capture_dma_data.maxburst = 4; + i2s->capture_dma_data.maxburst = 8; pm_runtime_enable(&pdev->dev); if (!pm_runtime_enabled(&pdev->dev)) { -- cgit v1.2.3