From 63a450aa4d08ccf4f53e9fa59144e746e2288319 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 19 Apr 2016 15:19:02 +0100 Subject: ASoC: da7219: Update PLL ranges and dividers to improve locking The expected MCLK frequency ranges and the associated dividers are updated to improve PLL locking in a corner scenario, with low MCLK frequency near an input divider change boundary. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7219.c | 28 ++++++++++++++-------------- sound/soc/codecs/da7219.h | 20 ++++++++++---------- 2 files changed, 24 insertions(+), 24 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c index 81c0708b85c1..3b1d65badbda 100644 --- a/sound/soc/codecs/da7219.c +++ b/sound/soc/codecs/da7219.c @@ -1079,21 +1079,21 @@ static int da7219_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, dev_err(codec->dev, "PLL input clock %d below valid range\n", da7219->mclk_rate); return -EINVAL; - } else if (da7219->mclk_rate <= 5000000) { - indiv_bits = DA7219_PLL_INDIV_2_5_MHZ; - indiv = DA7219_PLL_INDIV_2_5_MHZ_VAL; - } else if (da7219->mclk_rate <= 10000000) { - indiv_bits = DA7219_PLL_INDIV_5_10_MHZ; - indiv = DA7219_PLL_INDIV_5_10_MHZ_VAL; - } else if (da7219->mclk_rate <= 20000000) { - indiv_bits = DA7219_PLL_INDIV_10_20_MHZ; - indiv = DA7219_PLL_INDIV_10_20_MHZ_VAL; - } else if (da7219->mclk_rate <= 40000000) { - indiv_bits = DA7219_PLL_INDIV_20_40_MHZ; - indiv = DA7219_PLL_INDIV_20_40_MHZ_VAL; + } else if (da7219->mclk_rate <= 4500000) { + indiv_bits = DA7219_PLL_INDIV_2_TO_4_5_MHZ; + indiv = DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL; + } else if (da7219->mclk_rate <= 9000000) { + indiv_bits = DA7219_PLL_INDIV_4_5_TO_9_MHZ; + indiv = DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL; + } else if (da7219->mclk_rate <= 18000000) { + indiv_bits = DA7219_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7219_PLL_INDIV_9_TO_18_MHZ_VAL; + } else if (da7219->mclk_rate <= 36000000) { + indiv_bits = DA7219_PLL_INDIV_18_TO_36_MHZ; + indiv = DA7219_PLL_INDIV_18_TO_36_MHZ_VAL; } else if (da7219->mclk_rate <= 54000000) { - indiv_bits = DA7219_PLL_INDIV_40_54_MHZ; - indiv = DA7219_PLL_INDIV_40_54_MHZ_VAL; + indiv_bits = DA7219_PLL_INDIV_36_TO_54_MHZ; + indiv = DA7219_PLL_INDIV_36_TO_54_MHZ_VAL; } else { dev_err(codec->dev, "PLL input clock %d above valid range\n", da7219->mclk_rate); diff --git a/sound/soc/codecs/da7219.h b/sound/soc/codecs/da7219.h index 5a787e738084..ff2a2f02ce40 100644 --- a/sound/soc/codecs/da7219.h +++ b/sound/soc/codecs/da7219.h @@ -194,11 +194,11 @@ /* DA7219_PLL_CTRL = 0x20 */ #define DA7219_PLL_INDIV_SHIFT 2 #define DA7219_PLL_INDIV_MASK (0x7 << 2) -#define DA7219_PLL_INDIV_2_5_MHZ (0x0 << 2) -#define DA7219_PLL_INDIV_5_10_MHZ (0x1 << 2) -#define DA7219_PLL_INDIV_10_20_MHZ (0x2 << 2) -#define DA7219_PLL_INDIV_20_40_MHZ (0x3 << 2) -#define DA7219_PLL_INDIV_40_54_MHZ (0x4 << 2) +#define DA7219_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 2) +#define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2) +#define DA7219_PLL_INDIV_9_TO_18_MHZ (0x2 << 2) +#define DA7219_PLL_INDIV_18_TO_36_MHZ (0x3 << 2) +#define DA7219_PLL_INDIV_36_TO_54_MHZ (0x4 << 2) #define DA7219_PLL_MCLK_SQR_EN_SHIFT 5 #define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5) #define DA7219_PLL_MODE_SHIFT 6 @@ -761,11 +761,11 @@ #define DA7219_PLL_FREQ_OUT_98304 98304000 /* PLL Frequency Dividers */ -#define DA7219_PLL_INDIV_2_5_MHZ_VAL 1 -#define DA7219_PLL_INDIV_5_10_MHZ_VAL 2 -#define DA7219_PLL_INDIV_10_20_MHZ_VAL 4 -#define DA7219_PLL_INDIV_20_40_MHZ_VAL 8 -#define DA7219_PLL_INDIV_40_54_MHZ_VAL 16 +#define DA7219_PLL_INDIV_2_TO_4_5_MHZ_VAL 1 +#define DA7219_PLL_INDIV_4_5_TO_9_MHZ_VAL 2 +#define DA7219_PLL_INDIV_9_TO_18_MHZ_VAL 4 +#define DA7219_PLL_INDIV_18_TO_36_MHZ_VAL 8 +#define DA7219_PLL_INDIV_36_TO_54_MHZ_VAL 16 /* SRM */ #define DA7219_SRM_CHECK_RETRIES 8 -- cgit v1.2.3 From fb137ba64a6415ddf231495f6d1a82de1cd69ed0 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 19 Apr 2016 15:19:03 +0100 Subject: ASoC: da7219: Disallow unsupported 32KHz clock setting in set_dai_sysclk() The PLL function was updated to disallow 32KHz in commit 501f72e9c520 ("ASoC: da7219: Remove support for 32KHz PLL mode"), but set_dai_sysclk() was missed and still permits it. This patch resolves that discrepancy. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7219.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c index 3b1d65badbda..caea2ee19d9a 100644 --- a/sound/soc/codecs/da7219.c +++ b/sound/soc/codecs/da7219.c @@ -1025,7 +1025,7 @@ static int da7219_set_dai_sysclk(struct snd_soc_dai *codec_dai, if ((da7219->clk_src == clk_id) && (da7219->mclk_rate == freq)) return 0; - if (((freq < 2000000) && (freq != 32768)) || (freq > 54000000)) { + if ((freq < 2000000) || (freq > 54000000)) { dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", freq); return -EINVAL; -- cgit v1.2.3 From ae48a35c408732413880d0ac0d6467baa5b3d68a Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Fri, 22 Apr 2016 14:16:26 +0100 Subject: ASoC: da7218: Update PLL ranges and dividers to improve locking The expected MCLK frequency ranges and the associated dividers are updated to improve PLL locking in a corner scenario, with low MCLK frequency near an input divider change boundary. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7218.c | 32 ++++++++++++++++---------------- sound/soc/codecs/da7218.h | 21 ++++++++++++--------- 2 files changed, 28 insertions(+), 25 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/da7218.c b/sound/soc/codecs/da7218.c index 93575f251866..99ce23e113bf 100644 --- a/sound/soc/codecs/da7218.c +++ b/sound/soc/codecs/da7218.c @@ -1868,27 +1868,27 @@ static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, /* Verify 32KHz, 2MHz - 54MHz MCLK provided, and set input divider */ if (da7218->mclk_rate == 32768) { - indiv_bits = DA7218_PLL_INDIV_2_5_MHZ; - indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL; + indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL; } else if (da7218->mclk_rate < 2000000) { dev_err(codec->dev, "PLL input clock %d below valid range\n", da7218->mclk_rate); return -EINVAL; - } else if (da7218->mclk_rate <= 5000000) { - indiv_bits = DA7218_PLL_INDIV_2_5_MHZ; - indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL; - } else if (da7218->mclk_rate <= 10000000) { - indiv_bits = DA7218_PLL_INDIV_5_10_MHZ; - indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL; - } else if (da7218->mclk_rate <= 20000000) { - indiv_bits = DA7218_PLL_INDIV_10_20_MHZ; - indiv = DA7218_PLL_INDIV_10_20_MHZ_VAL; - } else if (da7218->mclk_rate <= 40000000) { - indiv_bits = DA7218_PLL_INDIV_20_40_MHZ; - indiv = DA7218_PLL_INDIV_20_40_MHZ_VAL; + } else if (da7218->mclk_rate <= 4500000) { + indiv_bits = DA7218_PLL_INDIV_2_TO_4_5_MHZ; + indiv = DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL; + } else if (da7218->mclk_rate <= 9000000) { + indiv_bits = DA7218_PLL_INDIV_4_5_TO_9_MHZ; + indiv = DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL; + } else if (da7218->mclk_rate <= 18000000) { + indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL; + } else if (da7218->mclk_rate <= 36000000) { + indiv_bits = DA7218_PLL_INDIV_18_TO_36_MHZ; + indiv = DA7218_PLL_INDIV_18_TO_36_MHZ_VAL; } else if (da7218->mclk_rate <= 54000000) { - indiv_bits = DA7218_PLL_INDIV_40_54_MHZ; - indiv = DA7218_PLL_INDIV_40_54_MHZ_VAL; + indiv_bits = DA7218_PLL_INDIV_36_TO_54_MHZ; + indiv = DA7218_PLL_INDIV_36_TO_54_MHZ_VAL; } else { dev_err(codec->dev, "PLL input clock %d above valid range\n", da7218->mclk_rate); diff --git a/sound/soc/codecs/da7218.h b/sound/soc/codecs/da7218.h index c2c59049a2ad..477cd37723cf 100644 --- a/sound/soc/codecs/da7218.h +++ b/sound/soc/codecs/da7218.h @@ -876,15 +876,11 @@ /* DA7218_PLL_CTRL = 0x91 */ #define DA7218_PLL_INDIV_SHIFT 0 #define DA7218_PLL_INDIV_MASK (0x7 << 0) -#define DA7218_PLL_INDIV_2_5_MHZ (0x0 << 0) -#define DA7218_PLL_INDIV_5_10_MHZ (0x1 << 0) -#define DA7218_PLL_INDIV_10_20_MHZ (0x2 << 0) -#define DA7218_PLL_INDIV_20_40_MHZ (0x3 << 0) -#define DA7218_PLL_INDIV_40_54_MHZ (0x4 << 0) -#define DA7218_PLL_INDIV_2_10_MHZ_VAL 2 -#define DA7218_PLL_INDIV_10_20_MHZ_VAL 4 -#define DA7218_PLL_INDIV_20_40_MHZ_VAL 8 -#define DA7218_PLL_INDIV_40_54_MHZ_VAL 16 +#define DA7218_PLL_INDIV_2_TO_4_5_MHZ (0x0 << 0) +#define DA7218_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 0) +#define DA7218_PLL_INDIV_9_TO_18_MHZ (0x2 << 0) +#define DA7218_PLL_INDIV_18_TO_36_MHZ (0x3 << 0) +#define DA7218_PLL_INDIV_36_TO_54_MHZ (0x4 << 0) #define DA7218_PLL_MCLK_SQR_EN_SHIFT 4 #define DA7218_PLL_MCLK_SQR_EN_MASK (0x1 << 4) #define DA7218_PLL_MODE_SHIFT 6 @@ -1336,6 +1332,13 @@ #define DA7218_PLL_FREQ_OUT_90316 90316800 #define DA7218_PLL_FREQ_OUT_98304 98304000 +/* PLL Frequency Dividers */ +#define DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL 1 +#define DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL 2 +#define DA7218_PLL_INDIV_9_TO_18_MHZ_VAL 4 +#define DA7218_PLL_INDIV_18_TO_36_MHZ_VAL 8 +#define DA7218_PLL_INDIV_36_TO_54_MHZ_VAL 16 + /* ALC Calibration */ #define DA7218_ALC_CALIB_DELAY_MIN 2500 #define DA7218_ALC_CALIB_DELAY_MAX 5000 -- cgit v1.2.3 From a34b027dca5ea840fbc84121db66488375acfdea Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Mon, 25 Apr 2016 13:39:38 +0000 Subject: ASoC: bcm2835: add 24bit support This adds 24 bit support to the I2S driver of the BCM2835 Code ported from bcm2708-i2s driver in Raspberry Pi tree. Signed-off-by: Florian Meier Signed-off-by: Matthias Reichl Signed-off-by: Martin Sperl Signed-off-by: Mark Brown --- sound/soc/bcm/bcm2835-i2s.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/bcm/bcm2835-i2s.c b/sound/soc/bcm/bcm2835-i2s.c index 1c1f2210387b..d2663e79ece1 100644 --- a/sound/soc/bcm/bcm2835-i2s.c +++ b/sound/soc/bcm/bcm2835-i2s.c @@ -259,6 +259,9 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream, case SNDRV_PCM_FORMAT_S16_LE: data_length = 16; break; + case SNDRV_PCM_FORMAT_S24_LE: + data_length = 24; + break; case SNDRV_PCM_FORMAT_S32_LE: data_length = 32; break; @@ -279,7 +282,7 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream, /* Setup the frame format */ format = BCM2835_I2S_CHEN; - if (data_length > 24) + if (data_length >= 24) format |= BCM2835_I2S_CHWEX; format |= BCM2835_I2S_CHWID((data_length-8)&0xf); @@ -570,6 +573,7 @@ static struct snd_soc_dai_driver bcm2835_i2s_dai = { .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE + | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE }, .capture = { @@ -577,6 +581,7 @@ static struct snd_soc_dai_driver bcm2835_i2s_dai = { .channels_max = 2, .rates = SNDRV_PCM_RATE_8000_192000, .formats = SNDRV_PCM_FMTBIT_S16_LE + | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE }, .ops = &bcm2835_i2s_dai_ops, -- cgit v1.2.3 From 60507fe191f524e82986fa737e5b27b4d3ad9289 Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Mon, 25 Apr 2016 13:39:39 +0000 Subject: ASoC: bcm2835: setup clock only if CPU is clock master We only need to enable the clock if we are a clock master. Code ported from bcm2708-i2s driver in Raspberry Pi tree. Original work by Zoltan Szenczi. Signed-off-by: Matthias Reichl Signed-off-by: Martin Sperl Signed-off-by: Mark Brown --- sound/soc/bcm/bcm2835-i2s.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/bcm/bcm2835-i2s.c b/sound/soc/bcm/bcm2835-i2s.c index d2663e79ece1..a0026e2d2f0a 100644 --- a/sound/soc/bcm/bcm2835-i2s.c +++ b/sound/soc/bcm/bcm2835-i2s.c @@ -276,8 +276,15 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream, /* otherwise calculate a fitting block ratio */ bclk_ratio = 2 * data_length; - /* set target clock rate*/ - clk_set_rate(dev->clk, sampling_rate * bclk_ratio); + /* Clock should only be set up here if CPU is clock master */ + switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + case SND_SOC_DAIFMT_CBS_CFM: + clk_set_rate(dev->clk, sampling_rate * bclk_ratio); + break; + default: + break; + } /* Setup the frame format */ format = BCM2835_I2S_CHEN; -- cgit v1.2.3 From de06f22f717b30641229036439b804ae79a7ad4d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 25 Apr 2016 19:30:39 -0400 Subject: ASoC: cs42l56: Use IS_ENABLED() instead of checking for built-in or module The IS_ENABLED() macro checks if a Kconfig symbol has been enabled either built-in or as a module, use that macro instead of open coding the same. Signed-off-by: Javier Martinez Canillas Signed-off-by: Mark Brown --- sound/soc/codecs/cs42l56.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/codecs/cs42l56.c b/sound/soc/codecs/cs42l56.c index 7cd5f769bb61..eec1ff853b98 100644 --- a/sound/soc/codecs/cs42l56.c +++ b/sound/soc/codecs/cs42l56.c @@ -56,7 +56,7 @@ struct cs42l56_private { u8 iface; u8 iface_fmt; u8 iface_inv; -#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) +#if IS_ENABLED(CONFIG_INPUT) struct input_dev *beep; struct work_struct beep_work; int beep_rate; -- cgit v1.2.3 From beff053c0ef6983897e3481169292e6435ef0a2d Mon Sep 17 00:00:00 2001 From: Matthias Reichl Date: Wed, 27 Apr 2016 15:26:52 +0200 Subject: ASoC: bcm2835: Add S16_LE support via packed DMA transfers The bcm2835-i2s driver already has support for the S16_LE format but that format hasn't been made available because dmaengine_pcm didn't support packed data transfers. bcm2835-i2s needs 16-bit left+right channel data to be packed into a 32-bit word, the FIFO register is 32-bit only and doesn't support 16-bit access. Now that dmaengine_pcm supports packed transfers the format can be made available by setting the SND_DMAENGINE_PCM_DAI_FLAG_PACK flag. No further configuration is necessary: - snd_dmaengine_dai_dma_data.addr_width is already set to DMA_SLAVE_BUSWIDTH_4_BYTES to force 32-bit DMA transfers - dmaengine_pcm will pick up the S16_LE format from the DAI configuration and make it available since it's no longer masked out due to the PACK flag. - there are no further corner cases to catch in hw_params, since the channel count is fixed at 2 we always have two 16-bit stereo samples that can be transferred via 32-bit DMA Signed-off-by: Matthias Reichl Tested-by: Martin Sperl Signed-off-by: Mark Brown --- sound/soc/bcm/bcm2835-i2s.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'sound') diff --git a/sound/soc/bcm/bcm2835-i2s.c b/sound/soc/bcm/bcm2835-i2s.c index a0026e2d2f0a..6ba20498202e 100644 --- a/sound/soc/bcm/bcm2835-i2s.c +++ b/sound/soc/bcm/bcm2835-i2s.c @@ -690,6 +690,15 @@ static int bcm2835_i2s_probe(struct platform_device *pdev) dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2; dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2; + /* + * Set the PACK flag to enable S16_LE support (2 S16_LE values + * packed into 32-bit transfers). + */ + dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].flags = + SND_DMAENGINE_PCM_DAI_FLAG_PACK; + dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].flags = + SND_DMAENGINE_PCM_DAI_FLAG_PACK; + /* BCLK ratio - use default */ dev->bclk_ratio = 0; -- cgit v1.2.3 From 5181365f5312d67dcdc9e4bc22516c48a83c8754 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Thu, 5 May 2016 11:53:06 +0100 Subject: ASoC: da7219: Add initial ACPI id for device This adds "DLGS7219" ACPI id for the codec. Signed-off-by: Adam Thomson Tested-by: Sathyanarayana Nujella Signed-off-by: Mark Brown --- sound/soc/codecs/da7219.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'sound') diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c index caea2ee19d9a..17e2119f211b 100644 --- a/sound/soc/codecs/da7219.c +++ b/sound/soc/codecs/da7219.c @@ -1426,6 +1426,12 @@ static const struct of_device_id da7219_of_match[] = { }; MODULE_DEVICE_TABLE(of, da7219_of_match); +static const struct acpi_device_id da7219_acpi_match[] = { + { .id = "DLGS7219", }, + { } +}; +MODULE_DEVICE_TABLE(acpi, da7219_acpi_match); + static enum da7219_micbias_voltage da7219_of_micbias_lvl(struct snd_soc_codec *codec, u32 val) { @@ -1955,6 +1961,7 @@ static struct i2c_driver da7219_i2c_driver = { .driver = { .name = "da7219", .of_match_table = of_match_ptr(da7219_of_match), + .acpi_match_table = ACPI_PTR(da7219_acpi_match), }, .probe = da7219_i2c_probe, .remove = da7219_i2c_remove, -- cgit v1.2.3 From b58cea7355875d6ae7aacb66c105f5c99f489909 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Fri, 6 May 2016 18:13:17 +0100 Subject: ASoC: da7129: Add missing include of acpi.h Reported-by: Stephen Rothwell Signed-off-by: Mark Brown --- sound/soc/codecs/da7219.c | 1 + 1 file changed, 1 insertion(+) (limited to 'sound') diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c index 17e2119f211b..5c93899f1f0e 100644 --- a/sound/soc/codecs/da7219.c +++ b/sound/soc/codecs/da7219.c @@ -11,6 +11,7 @@ * option) any later version. */ +#include #include #include #include -- cgit v1.2.3 From a0d5caeaebfd00853efa0080afc850e10be7b39a Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 10 May 2016 16:11:04 +0100 Subject: ASoC: da7213: Add DAI DAPM event to control DAI clocks Currently, when Codec is I2S master DAI clocks are continuously generated even if all audio streams have stopped. To improve efficiency, control of the DAI clocks for master mode have been moved to a DAPM widget event so they're only enabled as required. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7213.c | 35 ++++++++++++++++++++++++++++++++--- sound/soc/codecs/da7213.h | 2 -- 2 files changed, 32 insertions(+), 5 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c index 7278f93460c1..701bd6204747 100644 --- a/sound/soc/codecs/da7213.c +++ b/sound/soc/codecs/da7213.c @@ -725,6 +725,36 @@ static const struct snd_kcontrol_new da7213_dapm_mixoutr_controls[] = { }; +/* + * DAPM Events + */ + +static int da7213_dai_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); + struct da7213_priv *da7213 = snd_soc_codec_get_drvdata(codec); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + /* Enable DAI clks for master mode */ + if (da7213->master) + snd_soc_update_bits(codec, DA7213_DAI_CLK_MODE, + DA7213_DAI_CLK_EN_MASK, + DA7213_DAI_CLK_EN_MASK); + return 0; + case SND_SOC_DAPM_POST_PMD: + /* Disable DAI clks if in master mode */ + if (da7213->master) + snd_soc_update_bits(codec, DA7213_DAI_CLK_MODE, + DA7213_DAI_CLK_EN_MASK, 0); + return 0; + default: + return -EINVAL; + } +} + + /* * DAPM widgets */ @@ -736,7 +766,8 @@ static const struct snd_soc_dapm_widget da7213_dapm_widgets[] = { /* Use a supply here as this controls both input & output DAIs */ SND_SOC_DAPM_SUPPLY("DAI", DA7213_DAI_CTRL, DA7213_DAI_EN_SHIFT, - DA7213_NO_INVERT, NULL, 0), + DA7213_NO_INVERT, da7213_dai_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), /* * Input @@ -1143,11 +1174,9 @@ static int da7213_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) /* Set master/slave mode */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: - dai_clk_mode |= DA7213_DAI_CLK_EN_MASTER_MODE; da7213->master = true; break; case SND_SOC_DAIFMT_CBS_CFS: - dai_clk_mode |= DA7213_DAI_CLK_EN_SLAVE_MODE; da7213->master = false; break; default: diff --git a/sound/soc/codecs/da7213.h b/sound/soc/codecs/da7213.h index 030fd691b076..5de5c2997e0c 100644 --- a/sound/soc/codecs/da7213.h +++ b/sound/soc/codecs/da7213.h @@ -178,8 +178,6 @@ #define DA7213_DAI_BCLKS_PER_WCLK_MASK (0x3 << 0) #define DA7213_DAI_CLK_POL_INV (0x1 << 2) #define DA7213_DAI_WCLK_POL_INV (0x1 << 3) -#define DA7213_DAI_CLK_EN_SLAVE_MODE (0x0 << 7) -#define DA7213_DAI_CLK_EN_MASTER_MODE (0x1 << 7) #define DA7213_DAI_CLK_EN_MASK (0x1 << 7) /* DA7213_DAI_CTRL = 0x29 */ -- cgit v1.2.3 From d575b0b0f01a805508c5cf48b540f004e9b5de07 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 10 May 2016 16:11:05 +0100 Subject: ASoC: da7213: Add checking of SRM lock status before enabling DAI When the codec is DAI clk slave, and the SRM feature of the PLL is being used, the enabling of the DAI should occur only after the PLL has locked to the incoming WCLK. This update adds checking to the the DAI widget event, so it waits for SRM to lock. There is also a timeout if that lock doesn't occur within a given time. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7213.c | 23 +++++++++++++++++++++++ sound/soc/codecs/da7213.h | 4 ++++ 2 files changed, 27 insertions(+) (limited to 'sound') diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c index 701bd6204747..680d11116ccf 100644 --- a/sound/soc/codecs/da7213.c +++ b/sound/soc/codecs/da7213.c @@ -734,6 +734,9 @@ static int da7213_dai_event(struct snd_soc_dapm_widget *w, { struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); struct da7213_priv *da7213 = snd_soc_codec_get_drvdata(codec); + u8 pll_ctrl, pll_status; + int i = 0; + bool srm_lock = false; switch (event) { case SND_SOC_DAPM_PRE_PMU: @@ -742,6 +745,26 @@ static int da7213_dai_event(struct snd_soc_dapm_widget *w, snd_soc_update_bits(codec, DA7213_DAI_CLK_MODE, DA7213_DAI_CLK_EN_MASK, DA7213_DAI_CLK_EN_MASK); + + /* Slave mode, if SRM not enabled no need for status checks */ + pll_ctrl = snd_soc_read(codec, DA7213_PLL_CTRL); + if (!(pll_ctrl & DA7213_PLL_SRM_EN)) + return 0; + + /* Check SRM has locked */ + do { + pll_status = snd_soc_read(codec, DA7213_PLL_STATUS); + if (pll_status & DA7219_PLL_SRM_LOCK) { + srm_lock = true; + } else { + ++i; + msleep(50); + } + } while ((i < DA7213_SRM_CHECK_RETRIES) & (!srm_lock)); + + if (!srm_lock) + dev_warn(codec->dev, "SRM failed to lock\n"); + return 0; case SND_SOC_DAPM_POST_PMD: /* Disable DAI clks if in master mode */ diff --git a/sound/soc/codecs/da7213.h b/sound/soc/codecs/da7213.h index 5de5c2997e0c..af75340dea63 100644 --- a/sound/soc/codecs/da7213.h +++ b/sound/soc/codecs/da7213.h @@ -142,6 +142,9 @@ * Bit fields */ +/* DA7213_PLL_STATUS = 0x03 */ +#define DA7219_PLL_SRM_LOCK (0x1 << 1) + /* DA7213_SR = 0x22 */ #define DA7213_SR_8000 (0x1 << 0) #define DA7213_SR_11025 (0x2 << 0) @@ -502,6 +505,7 @@ #define DA7213_PLL_INDIV_10_20_MHZ_VAL 4 #define DA7213_PLL_INDIV_20_40_MHZ_VAL 8 #define DA7213_PLL_INDIV_40_54_MHZ_VAL 16 +#define DA7213_SRM_CHECK_RETRIES 8 enum da7213_clk_src { DA7213_CLKSRC_MCLK = 0, -- cgit v1.2.3 From 7e28fd469624fc41ec326a31abbc63a7afdd10f5 Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 10 May 2016 16:11:06 +0100 Subject: ASoC: da7213: Default PC counter to free-running when DAI disabled Currently PC counter is always synchronised to DAI which means that when the DAI is disabled, features such as ALC calibration cannot be executed successfully. This patch makes sure that when the DAI is disabled, PC counter is set to free-running. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7213.c | 13 +++++++++++++ sound/soc/codecs/da7213.h | 3 +++ 2 files changed, 16 insertions(+) (limited to 'sound') diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c index 680d11116ccf..657b7eba9954 100644 --- a/sound/soc/codecs/da7213.c +++ b/sound/soc/codecs/da7213.c @@ -746,6 +746,10 @@ static int da7213_dai_event(struct snd_soc_dapm_widget *w, DA7213_DAI_CLK_EN_MASK, DA7213_DAI_CLK_EN_MASK); + /* PC synchronised to DAI */ + snd_soc_update_bits(codec, DA7213_PC_COUNT, + DA7213_PC_FREERUN_MASK, 0); + /* Slave mode, if SRM not enabled no need for status checks */ pll_ctrl = snd_soc_read(codec, DA7213_PLL_CTRL); if (!(pll_ctrl & DA7213_PLL_SRM_EN)) @@ -767,6 +771,11 @@ static int da7213_dai_event(struct snd_soc_dapm_widget *w, return 0; case SND_SOC_DAPM_POST_PMD: + /* PC free-running */ + snd_soc_update_bits(codec, DA7213_PC_COUNT, + DA7213_PC_FREERUN_MASK, + DA7213_PC_FREERUN_MASK); + /* Disable DAI clks if in master mode */ if (da7213->master) snd_soc_update_bits(codec, DA7213_DAI_CLK_MODE, @@ -1599,6 +1608,10 @@ static int da7213_probe(struct snd_soc_codec *codec) /* Default to using SRM for slave mode */ da7213->srm_en = true; + /* Default PC counter to free-running */ + snd_soc_update_bits(codec, DA7213_PC_COUNT, DA7213_PC_FREERUN_MASK, + DA7213_PC_FREERUN_MASK); + /* Enable all Gain Ramps */ snd_soc_update_bits(codec, DA7213_AUX_L_CTRL, DA7213_GAIN_RAMP_EN, DA7213_GAIN_RAMP_EN); diff --git a/sound/soc/codecs/da7213.h b/sound/soc/codecs/da7213.h index af75340dea63..26b87e3c3088 100644 --- a/sound/soc/codecs/da7213.h +++ b/sound/soc/codecs/da7213.h @@ -413,6 +413,9 @@ #define DA7213_DMIC_CLK_RATE_SHIFT 2 #define DA7213_DMIC_CLK_RATE_MASK (0x1 << 2) +/* DA7213_PC_COUNT = 0x94 */ +#define DA7213_PC_FREERUN_MASK (0x1 << 0) + /* DA7213_DIG_CTRL = 0x99 */ #define DA7213_DAC_L_INV_SHIFT 3 #define DA7213_DAC_R_INV_SHIFT 7 -- cgit v1.2.3 From 1e62c52ddc2d23a02ac2308cc1bb6ff18f0cf3cd Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 10 May 2016 16:11:07 +0100 Subject: ASoC: da7213: Update PLL ranges to improve locking at frequency boundary This update changes the dividers used for ranges of input MCLK frequencies, to improve PLL locking for a corner case when at edge of MCLK frequency input divider range. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7213.c | 26 +++++++++++++------------- sound/soc/codecs/da7213.h | 28 ++++++++++++++-------------- 2 files changed, 27 insertions(+), 27 deletions(-) (limited to 'sound') diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c index 657b7eba9954..a233fe7f12eb 100644 --- a/sound/soc/codecs/da7213.c +++ b/sound/soc/codecs/da7213.c @@ -1344,26 +1344,26 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, /* Workout input divider based on MCLK rate */ if ((da7213->mclk_rate == 32768) && (source == DA7213_SYSCLK_PLL)) { /* 32KHz PLL Mode */ - indiv_bits = DA7213_PLL_INDIV_10_20_MHZ; - indiv = DA7213_PLL_INDIV_10_20_MHZ_VAL; + indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL; freq_ref = 3750000; pll_ctrl |= DA7213_PLL_32K_MODE; } else { /* 5 - 54MHz MCLK */ if (da7213->mclk_rate < 5000000) { goto pll_err; - } else if (da7213->mclk_rate <= 10000000) { - indiv_bits = DA7213_PLL_INDIV_5_10_MHZ; - indiv = DA7213_PLL_INDIV_5_10_MHZ_VAL; - } else if (da7213->mclk_rate <= 20000000) { - indiv_bits = DA7213_PLL_INDIV_10_20_MHZ; - indiv = DA7213_PLL_INDIV_10_20_MHZ_VAL; - } else if (da7213->mclk_rate <= 40000000) { - indiv_bits = DA7213_PLL_INDIV_20_40_MHZ; - indiv = DA7213_PLL_INDIV_20_40_MHZ_VAL; + } else if (da7213->mclk_rate <= 9000000) { + indiv_bits = DA7213_PLL_INDIV_5_TO_9_MHZ; + indiv = DA7213_PLL_INDIV_5_TO_9_MHZ_VAL; + } else if (da7213->mclk_rate <= 18000000) { + indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ; + indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL; + } else if (da7213->mclk_rate <= 36000000) { + indiv_bits = DA7213_PLL_INDIV_18_TO_36_MHZ; + indiv = DA7213_PLL_INDIV_18_TO_36_MHZ_VAL; } else if (da7213->mclk_rate <= 54000000) { - indiv_bits = DA7213_PLL_INDIV_40_54_MHZ; - indiv = DA7213_PLL_INDIV_40_54_MHZ_VAL; + indiv_bits = DA7213_PLL_INDIV_36_TO_54_MHZ; + indiv = DA7213_PLL_INDIV_36_TO_54_MHZ_VAL; } else { goto pll_err; } diff --git a/sound/soc/codecs/da7213.h b/sound/soc/codecs/da7213.h index 26b87e3c3088..fbb7a356a501 100644 --- a/sound/soc/codecs/da7213.h +++ b/sound/soc/codecs/da7213.h @@ -163,10 +163,10 @@ #define DA7213_VMID_EN (0x1 << 7) /* DA7213_PLL_CTRL = 0x27 */ -#define DA7213_PLL_INDIV_5_10_MHZ (0x0 << 2) -#define DA7213_PLL_INDIV_10_20_MHZ (0x1 << 2) -#define DA7213_PLL_INDIV_20_40_MHZ (0x2 << 2) -#define DA7213_PLL_INDIV_40_54_MHZ (0x3 << 2) +#define DA7213_PLL_INDIV_5_TO_9_MHZ (0x0 << 2) +#define DA7213_PLL_INDIV_9_TO_18_MHZ (0x1 << 2) +#define DA7213_PLL_INDIV_18_TO_36_MHZ (0x2 << 2) +#define DA7213_PLL_INDIV_36_TO_54_MHZ (0x3 << 2) #define DA7213_PLL_INDIV_MASK (0x3 << 2) #define DA7213_PLL_MCLK_SQR_EN (0x1 << 4) #define DA7213_PLL_32K_MODE (0x1 << 5) @@ -499,16 +499,16 @@ #define DA7213_ALC_AVG_ITERATIONS 5 /* PLL related */ -#define DA7213_SYSCLK_MCLK 0 -#define DA7213_SYSCLK_PLL 1 -#define DA7213_PLL_FREQ_OUT_90316800 90316800 -#define DA7213_PLL_FREQ_OUT_98304000 98304000 -#define DA7213_PLL_FREQ_OUT_94310400 94310400 -#define DA7213_PLL_INDIV_5_10_MHZ_VAL 2 -#define DA7213_PLL_INDIV_10_20_MHZ_VAL 4 -#define DA7213_PLL_INDIV_20_40_MHZ_VAL 8 -#define DA7213_PLL_INDIV_40_54_MHZ_VAL 16 -#define DA7213_SRM_CHECK_RETRIES 8 +#define DA7213_SYSCLK_MCLK 0 +#define DA7213_SYSCLK_PLL 1 +#define DA7213_PLL_FREQ_OUT_90316800 90316800 +#define DA7213_PLL_FREQ_OUT_98304000 98304000 +#define DA7213_PLL_FREQ_OUT_94310400 94310400 +#define DA7213_PLL_INDIV_5_TO_9_MHZ_VAL 2 +#define DA7213_PLL_INDIV_9_TO_18_MHZ_VAL 4 +#define DA7213_PLL_INDIV_18_TO_36_MHZ_VAL 8 +#define DA7213_PLL_INDIV_36_TO_54_MHZ_VAL 16 +#define DA7213_SRM_CHECK_RETRIES 8 enum da7213_clk_src { DA7213_CLKSRC_MCLK = 0, -- cgit v1.2.3 From abc189eadf6c12e60f95030e9c84083175526eaf Mon Sep 17 00:00:00 2001 From: Adam Thomson Date: Tue, 10 May 2016 16:11:08 +0100 Subject: ASoC: da7213: Allow PLL disable/bypass when using 32KHz sysclk Current checking for PLL 32KHz mode fails in driver code when bypassing the PLL. This is due to an incorrect check of PLL source type when 32KHz clock is provided. Removal of this check resolves the issue. Signed-off-by: Adam Thomson Signed-off-by: Mark Brown --- sound/soc/codecs/da7213.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'sound') diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c index a233fe7f12eb..e5527bc570ae 100644 --- a/sound/soc/codecs/da7213.c +++ b/sound/soc/codecs/da7213.c @@ -1342,7 +1342,7 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, pll_ctrl = 0; /* Workout input divider based on MCLK rate */ - if ((da7213->mclk_rate == 32768) && (source == DA7213_SYSCLK_PLL)) { + if (da7213->mclk_rate == 32768) { /* 32KHz PLL Mode */ indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ; indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL; -- cgit v1.2.3