From fc9fdd61c4809b14faa9b84fe3d8f4167a836326 Mon Sep 17 00:00:00 2001 From: Sanyog Kale Date: Tue, 13 Mar 2018 09:02:25 +0530 Subject: ASoC: Intel: Skylake: Disable clock and power gating during FW/LIB download In order to achieve better DMA performance and reduce download time for firmware and library, it is recommended to disable dynamic clock and power gating. In some scenarios, DMA may wait to accumulate more data and last chunk of data never gets completed if dynamic clock and power gating is kept enabled. This patch adds support to disable/enable dynamic clock and power gating and use it during firmware and library download. Signed-off-by: Rakesh Ughreja Signed-off-by: Sanyog Kale Signed-off-by: Guneshwor Singh Signed-off-by: Mark Brown --- sound/soc/intel/skylake/skl-messages.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'sound/soc/intel/skylake/skl-messages.c') diff --git a/sound/soc/intel/skylake/skl-messages.c b/sound/soc/intel/skylake/skl-messages.c index f161907859f3..57d4a58522a6 100644 --- a/sound/soc/intel/skylake/skl-messages.c +++ b/sound/soc/intel/skylake/skl-messages.c @@ -417,11 +417,16 @@ int skl_resume_dsp(struct skl *skl) if (skl->skl_sst->is_first_boot == true) return 0; - /* disable dynamic clock gating during fw and lib download */ + /* + * Disable dynamic clock and power gating during firmware + * and library download + */ ctx->enable_miscbdcge(ctx->dev, false); + ctx->clock_power_gating(ctx->dev, false); ret = skl_dsp_wake(ctx->dsp); ctx->enable_miscbdcge(ctx->dev, true); + ctx->clock_power_gating(ctx->dev, true); if (ret < 0) return ret; -- cgit v1.2.3