From ba0b3a977ecf525231d36f2d9f3a6ea05c35090a Mon Sep 17 00:00:00 2001 From: Curtis Malainey Date: Tue, 5 Nov 2019 17:13:35 -0800 Subject: ASoC: rt5677: Set ADC clock to use PLL and enable ASRC Use the PLL to kept the correct 24M clock rate so frequency shift does not occur when using the DSP VAD. Signed-off-by: Curtis Malainey Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org Signed-off-by: Mark Brown --- sound/soc/codecs/rt5677.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'sound/soc/codecs/rt5677.h') diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h index f8ada967fdbc..944ae02aafc2 100644 --- a/sound/soc/codecs/rt5677.h +++ b/sound/soc/codecs/rt5677.h @@ -1336,6 +1336,8 @@ #define RT5677_PLL_M_SFT 12 #define RT5677_PLL_M_BP (0x1 << 11) #define RT5677_PLL_M_BP_SFT 11 +#define RT5677_PLL_UPDATE_PLL1 (0x1 << 1) +#define RT5677_PLL_UPDATE_PLL1_SFT 1 /* Global Clock Control 1 (0x80) */ #define RT5677_SCLK_SRC_MASK (0x3 << 14) -- cgit v1.2.3