From fdbd256175a1e11c1ba827112d56b9a3952e1219 Mon Sep 17 00:00:00 2001 From: Richard Fitzgerald Date: Fri, 15 Oct 2021 14:36:16 +0100 Subject: ASoC: cs42l42: Set correct SRC MCLK According to the datasheet the SRC MCLK must be as near as possible to (125 * sample rate). This means it should be ~6MHz for rates up to 48k and ~12MHz for rates above that. As per datasheet table 4-21. Signed-off-by: Richard Fitzgerald Link: https://lore.kernel.org/r/20211015133619.4698-14-rf@opensource.cirrus.com Signed-off-by: Mark Brown --- sound/soc/codecs/cs42l42.h | 1 + 1 file changed, 1 insertion(+) (limited to 'sound/soc/codecs/cs42l42.h') diff --git a/sound/soc/codecs/cs42l42.h b/sound/soc/codecs/cs42l42.h index ded61af6ea8b..d13749e9d8c5 100644 --- a/sound/soc/codecs/cs42l42.h +++ b/sound/soc/codecs/cs42l42.h @@ -288,6 +288,7 @@ #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A) #define CS42L42_CLK_IASRC_SEL_SHIFT 0 #define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT) +#define CS42L42_CLK_IASRC_SEL_6 0 #define CS42L42_CLK_IASRC_SEL_12 1 #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B) -- cgit v1.2.3