From c4a11bf423ec84a16f7df0773041c29f2f305cc1 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sat, 16 Oct 2021 14:33:21 +0100 Subject: dt-bindings: Rename Ingenic CGU headers to ingenic,*.h Tidy up a bit the tree, by prefixing all include/dt-bindings/clock/ files related to Ingenic SoCs with 'ingenic,'. Signed-off-by: Paul Cercueil Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20211016133322.40771-1-paul@crapouillou.net --- include/dt-bindings/clock/ingenic,jz4725b-cgu.h | 36 ++++++++++ include/dt-bindings/clock/ingenic,jz4740-cgu.h | 39 +++++++++++ include/dt-bindings/clock/ingenic,jz4760-cgu.h | 54 +++++++++++++++ include/dt-bindings/clock/ingenic,jz4770-cgu.h | 58 ++++++++++++++++ include/dt-bindings/clock/ingenic,jz4780-cgu.h | 91 +++++++++++++++++++++++++ include/dt-bindings/clock/ingenic,x1000-cgu.h | 54 +++++++++++++++ include/dt-bindings/clock/ingenic,x1830-cgu.h | 57 ++++++++++++++++ include/dt-bindings/clock/jz4725b-cgu.h | 36 ---------- include/dt-bindings/clock/jz4740-cgu.h | 39 ----------- include/dt-bindings/clock/jz4760-cgu.h | 54 --------------- include/dt-bindings/clock/jz4770-cgu.h | 58 ---------------- include/dt-bindings/clock/jz4780-cgu.h | 91 ------------------------- include/dt-bindings/clock/x1000-cgu.h | 54 --------------- include/dt-bindings/clock/x1830-cgu.h | 57 ---------------- 14 files changed, 389 insertions(+), 389 deletions(-) create mode 100644 include/dt-bindings/clock/ingenic,jz4725b-cgu.h create mode 100644 include/dt-bindings/clock/ingenic,jz4740-cgu.h create mode 100644 include/dt-bindings/clock/ingenic,jz4760-cgu.h create mode 100644 include/dt-bindings/clock/ingenic,jz4770-cgu.h create mode 100644 include/dt-bindings/clock/ingenic,jz4780-cgu.h create mode 100644 include/dt-bindings/clock/ingenic,x1000-cgu.h create mode 100644 include/dt-bindings/clock/ingenic,x1830-cgu.h delete mode 100644 include/dt-bindings/clock/jz4725b-cgu.h delete mode 100644 include/dt-bindings/clock/jz4740-cgu.h delete mode 100644 include/dt-bindings/clock/jz4760-cgu.h delete mode 100644 include/dt-bindings/clock/jz4770-cgu.h delete mode 100644 include/dt-bindings/clock/jz4780-cgu.h delete mode 100644 include/dt-bindings/clock/x1000-cgu.h delete mode 100644 include/dt-bindings/clock/x1830-cgu.h (limited to 'include') diff --git a/include/dt-bindings/clock/ingenic,jz4725b-cgu.h b/include/dt-bindings/clock/ingenic,jz4725b-cgu.h new file mode 100644 index 000000000000..31f1ab0fe42c --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4725b-cgu.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ + +#define JZ4725B_CLK_EXT 0 +#define JZ4725B_CLK_OSC32K 1 +#define JZ4725B_CLK_PLL 2 +#define JZ4725B_CLK_PLL_HALF 3 +#define JZ4725B_CLK_CCLK 4 +#define JZ4725B_CLK_HCLK 5 +#define JZ4725B_CLK_PCLK 6 +#define JZ4725B_CLK_MCLK 7 +#define JZ4725B_CLK_IPU 8 +#define JZ4725B_CLK_LCD 9 +#define JZ4725B_CLK_I2S 10 +#define JZ4725B_CLK_SPI 11 +#define JZ4725B_CLK_MMC_MUX 12 +#define JZ4725B_CLK_UDC 13 +#define JZ4725B_CLK_UART 14 +#define JZ4725B_CLK_DMA 15 +#define JZ4725B_CLK_ADC 16 +#define JZ4725B_CLK_I2C 17 +#define JZ4725B_CLK_AIC 18 +#define JZ4725B_CLK_MMC0 19 +#define JZ4725B_CLK_MMC1 20 +#define JZ4725B_CLK_BCH 21 +#define JZ4725B_CLK_TCU 22 +#define JZ4725B_CLK_EXT512 23 +#define JZ4725B_CLK_RTC 24 +#define JZ4725B_CLK_UDC_PHY 25 + +#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,jz4740-cgu.h b/include/dt-bindings/clock/ingenic,jz4740-cgu.h new file mode 100644 index 000000000000..e82d77028581 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4740-cgu.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4740 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ + +#define JZ4740_CLK_EXT 0 +#define JZ4740_CLK_RTC 1 +#define JZ4740_CLK_PLL 2 +#define JZ4740_CLK_PLL_HALF 3 +#define JZ4740_CLK_CCLK 4 +#define JZ4740_CLK_HCLK 5 +#define JZ4740_CLK_PCLK 6 +#define JZ4740_CLK_MCLK 7 +#define JZ4740_CLK_LCD 8 +#define JZ4740_CLK_LCD_PCLK 9 +#define JZ4740_CLK_I2S 10 +#define JZ4740_CLK_SPI 11 +#define JZ4740_CLK_MMC 12 +#define JZ4740_CLK_UHC 13 +#define JZ4740_CLK_UDC 14 +#define JZ4740_CLK_UART0 15 +#define JZ4740_CLK_UART1 16 +#define JZ4740_CLK_DMA 17 +#define JZ4740_CLK_IPU 18 +#define JZ4740_CLK_ADC 19 +#define JZ4740_CLK_I2C 20 +#define JZ4740_CLK_AIC 21 +#define JZ4740_CLK_TCU 22 + +#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,jz4760-cgu.h b/include/dt-bindings/clock/ingenic,jz4760-cgu.h new file mode 100644 index 000000000000..4bb2e19c4743 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4760-cgu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4760-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ + +#define JZ4760_CLK_EXT 0 +#define JZ4760_CLK_OSC32K 1 +#define JZ4760_CLK_PLL0 2 +#define JZ4760_CLK_PLL0_HALF 3 +#define JZ4760_CLK_PLL1 4 +#define JZ4760_CLK_CCLK 5 +#define JZ4760_CLK_HCLK 6 +#define JZ4760_CLK_SCLK 7 +#define JZ4760_CLK_H2CLK 8 +#define JZ4760_CLK_MCLK 9 +#define JZ4760_CLK_PCLK 10 +#define JZ4760_CLK_MMC_MUX 11 +#define JZ4760_CLK_MMC0 12 +#define JZ4760_CLK_MMC1 13 +#define JZ4760_CLK_MMC2 14 +#define JZ4760_CLK_CIM 15 +#define JZ4760_CLK_UHC 16 +#define JZ4760_CLK_GPU 17 +#define JZ4760_CLK_GPS 18 +#define JZ4760_CLK_SSI_MUX 19 +#define JZ4760_CLK_PCM 20 +#define JZ4760_CLK_I2S 21 +#define JZ4760_CLK_OTG 22 +#define JZ4760_CLK_SSI0 23 +#define JZ4760_CLK_SSI1 24 +#define JZ4760_CLK_SSI2 25 +#define JZ4760_CLK_DMA 26 +#define JZ4760_CLK_I2C0 27 +#define JZ4760_CLK_I2C1 28 +#define JZ4760_CLK_UART0 29 +#define JZ4760_CLK_UART1 30 +#define JZ4760_CLK_UART2 31 +#define JZ4760_CLK_UART3 32 +#define JZ4760_CLK_IPU 33 +#define JZ4760_CLK_ADC 34 +#define JZ4760_CLK_AIC 35 +#define JZ4760_CLK_VPU 36 +#define JZ4760_CLK_UHC_PHY 37 +#define JZ4760_CLK_OTG_PHY 38 +#define JZ4760_CLK_EXT512 39 +#define JZ4760_CLK_RTC 40 +#define JZ4760_CLK_LPCLK_DIV 41 +#define JZ4760_CLK_TVE 42 +#define JZ4760_CLK_LPCLK 43 + +#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,jz4770-cgu.h b/include/dt-bindings/clock/ingenic,jz4770-cgu.h new file mode 100644 index 000000000000..d68a7695a1f8 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4770-cgu.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ + +#define JZ4770_CLK_EXT 0 +#define JZ4770_CLK_OSC32K 1 +#define JZ4770_CLK_PLL0 2 +#define JZ4770_CLK_PLL1 3 +#define JZ4770_CLK_CCLK 4 +#define JZ4770_CLK_H0CLK 5 +#define JZ4770_CLK_H1CLK 6 +#define JZ4770_CLK_H2CLK 7 +#define JZ4770_CLK_C1CLK 8 +#define JZ4770_CLK_PCLK 9 +#define JZ4770_CLK_MMC0_MUX 10 +#define JZ4770_CLK_MMC0 11 +#define JZ4770_CLK_MMC1_MUX 12 +#define JZ4770_CLK_MMC1 13 +#define JZ4770_CLK_MMC2_MUX 14 +#define JZ4770_CLK_MMC2 15 +#define JZ4770_CLK_CIM 16 +#define JZ4770_CLK_UHC 17 +#define JZ4770_CLK_GPU 18 +#define JZ4770_CLK_BCH 19 +#define JZ4770_CLK_LPCLK_MUX 20 +#define JZ4770_CLK_GPS 21 +#define JZ4770_CLK_SSI_MUX 22 +#define JZ4770_CLK_PCM_MUX 23 +#define JZ4770_CLK_I2S 24 +#define JZ4770_CLK_OTG 25 +#define JZ4770_CLK_SSI0 26 +#define JZ4770_CLK_SSI1 27 +#define JZ4770_CLK_SSI2 28 +#define JZ4770_CLK_PCM0 29 +#define JZ4770_CLK_PCM1 30 +#define JZ4770_CLK_DMA 31 +#define JZ4770_CLK_I2C0 32 +#define JZ4770_CLK_I2C1 33 +#define JZ4770_CLK_I2C2 34 +#define JZ4770_CLK_UART0 35 +#define JZ4770_CLK_UART1 36 +#define JZ4770_CLK_UART2 37 +#define JZ4770_CLK_UART3 38 +#define JZ4770_CLK_IPU 39 +#define JZ4770_CLK_ADC 40 +#define JZ4770_CLK_AIC 41 +#define JZ4770_CLK_AUX 42 +#define JZ4770_CLK_VPU 43 +#define JZ4770_CLK_UHC_PHY 44 +#define JZ4770_CLK_OTG_PHY 45 +#define JZ4770_CLK_EXT512 46 +#define JZ4770_CLK_RTC 47 + +#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,jz4780-cgu.h b/include/dt-bindings/clock/ingenic,jz4780-cgu.h new file mode 100644 index 000000000000..85cf8eb5081b --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4780-cgu.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4780 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ + +#define JZ4780_CLK_EXCLK 0 +#define JZ4780_CLK_RTCLK 1 +#define JZ4780_CLK_APLL 2 +#define JZ4780_CLK_MPLL 3 +#define JZ4780_CLK_EPLL 4 +#define JZ4780_CLK_VPLL 5 +#define JZ4780_CLK_OTGPHY 6 +#define JZ4780_CLK_SCLKA 7 +#define JZ4780_CLK_CPUMUX 8 +#define JZ4780_CLK_CPU 9 +#define JZ4780_CLK_L2CACHE 10 +#define JZ4780_CLK_AHB0 11 +#define JZ4780_CLK_AHB2PMUX 12 +#define JZ4780_CLK_AHB2 13 +#define JZ4780_CLK_PCLK 14 +#define JZ4780_CLK_DDR 15 +#define JZ4780_CLK_VPU 16 +#define JZ4780_CLK_I2SPLL 17 +#define JZ4780_CLK_I2S 18 +#define JZ4780_CLK_LCD0PIXCLK 19 +#define JZ4780_CLK_LCD1PIXCLK 20 +#define JZ4780_CLK_MSCMUX 21 +#define JZ4780_CLK_MSC0 22 +#define JZ4780_CLK_MSC1 23 +#define JZ4780_CLK_MSC2 24 +#define JZ4780_CLK_UHC 25 +#define JZ4780_CLK_SSIPLL 26 +#define JZ4780_CLK_SSI 27 +#define JZ4780_CLK_CIMMCLK 28 +#define JZ4780_CLK_PCMPLL 29 +#define JZ4780_CLK_PCM 30 +#define JZ4780_CLK_GPU 31 +#define JZ4780_CLK_HDMI 32 +#define JZ4780_CLK_BCH 33 +#define JZ4780_CLK_NEMC 34 +#define JZ4780_CLK_OTG0 35 +#define JZ4780_CLK_SSI0 36 +#define JZ4780_CLK_SMB0 37 +#define JZ4780_CLK_SMB1 38 +#define JZ4780_CLK_SCC 39 +#define JZ4780_CLK_AIC 40 +#define JZ4780_CLK_TSSI0 41 +#define JZ4780_CLK_OWI 42 +#define JZ4780_CLK_KBC 43 +#define JZ4780_CLK_SADC 44 +#define JZ4780_CLK_UART0 45 +#define JZ4780_CLK_UART1 46 +#define JZ4780_CLK_UART2 47 +#define JZ4780_CLK_UART3 48 +#define JZ4780_CLK_SSI1 49 +#define JZ4780_CLK_SSI2 50 +#define JZ4780_CLK_PDMA 51 +#define JZ4780_CLK_GPS 52 +#define JZ4780_CLK_MAC 53 +#define JZ4780_CLK_SMB2 54 +#define JZ4780_CLK_CIM 55 +#define JZ4780_CLK_LCD 56 +#define JZ4780_CLK_TVE 57 +#define JZ4780_CLK_IPU 58 +#define JZ4780_CLK_DDR0 59 +#define JZ4780_CLK_DDR1 60 +#define JZ4780_CLK_SMB3 61 +#define JZ4780_CLK_TSSI1 62 +#define JZ4780_CLK_COMPRESS 63 +#define JZ4780_CLK_AIC1 64 +#define JZ4780_CLK_GPVLC 65 +#define JZ4780_CLK_OTG1 66 +#define JZ4780_CLK_UART4 67 +#define JZ4780_CLK_AHBMON 68 +#define JZ4780_CLK_SMB4 69 +#define JZ4780_CLK_DES 70 +#define JZ4780_CLK_X2D 71 +#define JZ4780_CLK_CORE1 72 +#define JZ4780_CLK_EXCLK_DIV512 73 +#define JZ4780_CLK_RTC 74 + +#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,x1000-cgu.h b/include/dt-bindings/clock/ingenic,x1000-cgu.h new file mode 100644 index 000000000000..f187e0719fd3 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,x1000-cgu.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1000-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1000 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ + +#define X1000_CLK_EXCLK 0 +#define X1000_CLK_RTCLK 1 +#define X1000_CLK_APLL 2 +#define X1000_CLK_MPLL 3 +#define X1000_CLK_OTGPHY 4 +#define X1000_CLK_SCLKA 5 +#define X1000_CLK_CPUMUX 6 +#define X1000_CLK_CPU 7 +#define X1000_CLK_L2CACHE 8 +#define X1000_CLK_AHB0 9 +#define X1000_CLK_AHB2PMUX 10 +#define X1000_CLK_AHB2 11 +#define X1000_CLK_PCLK 12 +#define X1000_CLK_DDR 13 +#define X1000_CLK_MAC 14 +#define X1000_CLK_LCD 15 +#define X1000_CLK_MSCMUX 16 +#define X1000_CLK_MSC0 17 +#define X1000_CLK_MSC1 18 +#define X1000_CLK_OTG 19 +#define X1000_CLK_SSIPLL 20 +#define X1000_CLK_SSIPLL_DIV2 21 +#define X1000_CLK_SSIMUX 22 +#define X1000_CLK_EMC 23 +#define X1000_CLK_EFUSE 24 +#define X1000_CLK_SFC 25 +#define X1000_CLK_I2C0 26 +#define X1000_CLK_I2C1 27 +#define X1000_CLK_I2C2 28 +#define X1000_CLK_UART0 29 +#define X1000_CLK_UART1 30 +#define X1000_CLK_UART2 31 +#define X1000_CLK_TCU 32 +#define X1000_CLK_SSI 33 +#define X1000_CLK_OST 34 +#define X1000_CLK_PDMA 35 +#define X1000_CLK_EXCLK_DIV512 36 +#define X1000_CLK_RTC 37 + +#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/ingenic,x1830-cgu.h b/include/dt-bindings/clock/ingenic,x1830-cgu.h new file mode 100644 index 000000000000..88455376a950 --- /dev/null +++ b/include/dt-bindings/clock/ingenic,x1830-cgu.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x1830-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x1830 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ +#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ + +#define X1830_CLK_EXCLK 0 +#define X1830_CLK_RTCLK 1 +#define X1830_CLK_APLL 2 +#define X1830_CLK_MPLL 3 +#define X1830_CLK_EPLL 4 +#define X1830_CLK_VPLL 5 +#define X1830_CLK_OTGPHY 6 +#define X1830_CLK_SCLKA 7 +#define X1830_CLK_CPUMUX 8 +#define X1830_CLK_CPU 9 +#define X1830_CLK_L2CACHE 10 +#define X1830_CLK_AHB0 11 +#define X1830_CLK_AHB2PMUX 12 +#define X1830_CLK_AHB2 13 +#define X1830_CLK_PCLK 14 +#define X1830_CLK_DDR 15 +#define X1830_CLK_MAC 16 +#define X1830_CLK_LCD 17 +#define X1830_CLK_MSCMUX 18 +#define X1830_CLK_MSC0 19 +#define X1830_CLK_MSC1 20 +#define X1830_CLK_SSIPLL 21 +#define X1830_CLK_SSIPLL_DIV2 22 +#define X1830_CLK_SSIMUX 23 +#define X1830_CLK_EMC 24 +#define X1830_CLK_EFUSE 25 +#define X1830_CLK_OTG 26 +#define X1830_CLK_SSI0 27 +#define X1830_CLK_SMB0 28 +#define X1830_CLK_SMB1 29 +#define X1830_CLK_SMB2 30 +#define X1830_CLK_UART0 31 +#define X1830_CLK_UART1 32 +#define X1830_CLK_SSI1 33 +#define X1830_CLK_SFC 34 +#define X1830_CLK_PDMA 35 +#define X1830_CLK_TCU 36 +#define X1830_CLK_DTRNG 37 +#define X1830_CLK_OST 38 +#define X1830_CLK_EXCLK_DIV512 39 +#define X1830_CLK_RTC 40 + +#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4725b-cgu.h b/include/dt-bindings/clock/jz4725b-cgu.h deleted file mode 100644 index 31f1ab0fe42c..000000000000 --- a/include/dt-bindings/clock/jz4725b-cgu.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4725b-cgu DT binding. - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ - -#define JZ4725B_CLK_EXT 0 -#define JZ4725B_CLK_OSC32K 1 -#define JZ4725B_CLK_PLL 2 -#define JZ4725B_CLK_PLL_HALF 3 -#define JZ4725B_CLK_CCLK 4 -#define JZ4725B_CLK_HCLK 5 -#define JZ4725B_CLK_PCLK 6 -#define JZ4725B_CLK_MCLK 7 -#define JZ4725B_CLK_IPU 8 -#define JZ4725B_CLK_LCD 9 -#define JZ4725B_CLK_I2S 10 -#define JZ4725B_CLK_SPI 11 -#define JZ4725B_CLK_MMC_MUX 12 -#define JZ4725B_CLK_UDC 13 -#define JZ4725B_CLK_UART 14 -#define JZ4725B_CLK_DMA 15 -#define JZ4725B_CLK_ADC 16 -#define JZ4725B_CLK_I2C 17 -#define JZ4725B_CLK_AIC 18 -#define JZ4725B_CLK_MMC0 19 -#define JZ4725B_CLK_MMC1 20 -#define JZ4725B_CLK_BCH 21 -#define JZ4725B_CLK_TCU 22 -#define JZ4725B_CLK_EXT512 23 -#define JZ4725B_CLK_RTC 24 -#define JZ4725B_CLK_UDC_PHY 25 - -#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4740-cgu.h b/include/dt-bindings/clock/jz4740-cgu.h deleted file mode 100644 index e82d77028581..000000000000 --- a/include/dt-bindings/clock/jz4740-cgu.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the jz4740 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ - -#define JZ4740_CLK_EXT 0 -#define JZ4740_CLK_RTC 1 -#define JZ4740_CLK_PLL 2 -#define JZ4740_CLK_PLL_HALF 3 -#define JZ4740_CLK_CCLK 4 -#define JZ4740_CLK_HCLK 5 -#define JZ4740_CLK_PCLK 6 -#define JZ4740_CLK_MCLK 7 -#define JZ4740_CLK_LCD 8 -#define JZ4740_CLK_LCD_PCLK 9 -#define JZ4740_CLK_I2S 10 -#define JZ4740_CLK_SPI 11 -#define JZ4740_CLK_MMC 12 -#define JZ4740_CLK_UHC 13 -#define JZ4740_CLK_UDC 14 -#define JZ4740_CLK_UART0 15 -#define JZ4740_CLK_UART1 16 -#define JZ4740_CLK_DMA 17 -#define JZ4740_CLK_IPU 18 -#define JZ4740_CLK_ADC 19 -#define JZ4740_CLK_I2C 20 -#define JZ4740_CLK_AIC 21 -#define JZ4740_CLK_TCU 22 - -#endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4760-cgu.h b/include/dt-bindings/clock/jz4760-cgu.h deleted file mode 100644 index 4bb2e19c4743..000000000000 --- a/include/dt-bindings/clock/jz4760-cgu.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4760-cgu DT binding. - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ - -#define JZ4760_CLK_EXT 0 -#define JZ4760_CLK_OSC32K 1 -#define JZ4760_CLK_PLL0 2 -#define JZ4760_CLK_PLL0_HALF 3 -#define JZ4760_CLK_PLL1 4 -#define JZ4760_CLK_CCLK 5 -#define JZ4760_CLK_HCLK 6 -#define JZ4760_CLK_SCLK 7 -#define JZ4760_CLK_H2CLK 8 -#define JZ4760_CLK_MCLK 9 -#define JZ4760_CLK_PCLK 10 -#define JZ4760_CLK_MMC_MUX 11 -#define JZ4760_CLK_MMC0 12 -#define JZ4760_CLK_MMC1 13 -#define JZ4760_CLK_MMC2 14 -#define JZ4760_CLK_CIM 15 -#define JZ4760_CLK_UHC 16 -#define JZ4760_CLK_GPU 17 -#define JZ4760_CLK_GPS 18 -#define JZ4760_CLK_SSI_MUX 19 -#define JZ4760_CLK_PCM 20 -#define JZ4760_CLK_I2S 21 -#define JZ4760_CLK_OTG 22 -#define JZ4760_CLK_SSI0 23 -#define JZ4760_CLK_SSI1 24 -#define JZ4760_CLK_SSI2 25 -#define JZ4760_CLK_DMA 26 -#define JZ4760_CLK_I2C0 27 -#define JZ4760_CLK_I2C1 28 -#define JZ4760_CLK_UART0 29 -#define JZ4760_CLK_UART1 30 -#define JZ4760_CLK_UART2 31 -#define JZ4760_CLK_UART3 32 -#define JZ4760_CLK_IPU 33 -#define JZ4760_CLK_ADC 34 -#define JZ4760_CLK_AIC 35 -#define JZ4760_CLK_VPU 36 -#define JZ4760_CLK_UHC_PHY 37 -#define JZ4760_CLK_OTG_PHY 38 -#define JZ4760_CLK_EXT512 39 -#define JZ4760_CLK_RTC 40 -#define JZ4760_CLK_LPCLK_DIV 41 -#define JZ4760_CLK_TVE 42 -#define JZ4760_CLK_LPCLK 43 - -#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4770-cgu.h b/include/dt-bindings/clock/jz4770-cgu.h deleted file mode 100644 index d68a7695a1f8..000000000000 --- a/include/dt-bindings/clock/jz4770-cgu.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4770-cgu DT binding. - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ - -#define JZ4770_CLK_EXT 0 -#define JZ4770_CLK_OSC32K 1 -#define JZ4770_CLK_PLL0 2 -#define JZ4770_CLK_PLL1 3 -#define JZ4770_CLK_CCLK 4 -#define JZ4770_CLK_H0CLK 5 -#define JZ4770_CLK_H1CLK 6 -#define JZ4770_CLK_H2CLK 7 -#define JZ4770_CLK_C1CLK 8 -#define JZ4770_CLK_PCLK 9 -#define JZ4770_CLK_MMC0_MUX 10 -#define JZ4770_CLK_MMC0 11 -#define JZ4770_CLK_MMC1_MUX 12 -#define JZ4770_CLK_MMC1 13 -#define JZ4770_CLK_MMC2_MUX 14 -#define JZ4770_CLK_MMC2 15 -#define JZ4770_CLK_CIM 16 -#define JZ4770_CLK_UHC 17 -#define JZ4770_CLK_GPU 18 -#define JZ4770_CLK_BCH 19 -#define JZ4770_CLK_LPCLK_MUX 20 -#define JZ4770_CLK_GPS 21 -#define JZ4770_CLK_SSI_MUX 22 -#define JZ4770_CLK_PCM_MUX 23 -#define JZ4770_CLK_I2S 24 -#define JZ4770_CLK_OTG 25 -#define JZ4770_CLK_SSI0 26 -#define JZ4770_CLK_SSI1 27 -#define JZ4770_CLK_SSI2 28 -#define JZ4770_CLK_PCM0 29 -#define JZ4770_CLK_PCM1 30 -#define JZ4770_CLK_DMA 31 -#define JZ4770_CLK_I2C0 32 -#define JZ4770_CLK_I2C1 33 -#define JZ4770_CLK_I2C2 34 -#define JZ4770_CLK_UART0 35 -#define JZ4770_CLK_UART1 36 -#define JZ4770_CLK_UART2 37 -#define JZ4770_CLK_UART3 38 -#define JZ4770_CLK_IPU 39 -#define JZ4770_CLK_ADC 40 -#define JZ4770_CLK_AIC 41 -#define JZ4770_CLK_AUX 42 -#define JZ4770_CLK_VPU 43 -#define JZ4770_CLK_UHC_PHY 44 -#define JZ4770_CLK_OTG_PHY 45 -#define JZ4770_CLK_EXT512 46 -#define JZ4770_CLK_RTC 47 - -#endif /* __DT_BINDINGS_CLOCK_JZ4770_CGU_H__ */ diff --git a/include/dt-bindings/clock/jz4780-cgu.h b/include/dt-bindings/clock/jz4780-cgu.h deleted file mode 100644 index 85cf8eb5081b..000000000000 --- a/include/dt-bindings/clock/jz4780-cgu.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,jz4780-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the jz4780 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ -#define __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ - -#define JZ4780_CLK_EXCLK 0 -#define JZ4780_CLK_RTCLK 1 -#define JZ4780_CLK_APLL 2 -#define JZ4780_CLK_MPLL 3 -#define JZ4780_CLK_EPLL 4 -#define JZ4780_CLK_VPLL 5 -#define JZ4780_CLK_OTGPHY 6 -#define JZ4780_CLK_SCLKA 7 -#define JZ4780_CLK_CPUMUX 8 -#define JZ4780_CLK_CPU 9 -#define JZ4780_CLK_L2CACHE 10 -#define JZ4780_CLK_AHB0 11 -#define JZ4780_CLK_AHB2PMUX 12 -#define JZ4780_CLK_AHB2 13 -#define JZ4780_CLK_PCLK 14 -#define JZ4780_CLK_DDR 15 -#define JZ4780_CLK_VPU 16 -#define JZ4780_CLK_I2SPLL 17 -#define JZ4780_CLK_I2S 18 -#define JZ4780_CLK_LCD0PIXCLK 19 -#define JZ4780_CLK_LCD1PIXCLK 20 -#define JZ4780_CLK_MSCMUX 21 -#define JZ4780_CLK_MSC0 22 -#define JZ4780_CLK_MSC1 23 -#define JZ4780_CLK_MSC2 24 -#define JZ4780_CLK_UHC 25 -#define JZ4780_CLK_SSIPLL 26 -#define JZ4780_CLK_SSI 27 -#define JZ4780_CLK_CIMMCLK 28 -#define JZ4780_CLK_PCMPLL 29 -#define JZ4780_CLK_PCM 30 -#define JZ4780_CLK_GPU 31 -#define JZ4780_CLK_HDMI 32 -#define JZ4780_CLK_BCH 33 -#define JZ4780_CLK_NEMC 34 -#define JZ4780_CLK_OTG0 35 -#define JZ4780_CLK_SSI0 36 -#define JZ4780_CLK_SMB0 37 -#define JZ4780_CLK_SMB1 38 -#define JZ4780_CLK_SCC 39 -#define JZ4780_CLK_AIC 40 -#define JZ4780_CLK_TSSI0 41 -#define JZ4780_CLK_OWI 42 -#define JZ4780_CLK_KBC 43 -#define JZ4780_CLK_SADC 44 -#define JZ4780_CLK_UART0 45 -#define JZ4780_CLK_UART1 46 -#define JZ4780_CLK_UART2 47 -#define JZ4780_CLK_UART3 48 -#define JZ4780_CLK_SSI1 49 -#define JZ4780_CLK_SSI2 50 -#define JZ4780_CLK_PDMA 51 -#define JZ4780_CLK_GPS 52 -#define JZ4780_CLK_MAC 53 -#define JZ4780_CLK_SMB2 54 -#define JZ4780_CLK_CIM 55 -#define JZ4780_CLK_LCD 56 -#define JZ4780_CLK_TVE 57 -#define JZ4780_CLK_IPU 58 -#define JZ4780_CLK_DDR0 59 -#define JZ4780_CLK_DDR1 60 -#define JZ4780_CLK_SMB3 61 -#define JZ4780_CLK_TSSI1 62 -#define JZ4780_CLK_COMPRESS 63 -#define JZ4780_CLK_AIC1 64 -#define JZ4780_CLK_GPVLC 65 -#define JZ4780_CLK_OTG1 66 -#define JZ4780_CLK_UART4 67 -#define JZ4780_CLK_AHBMON 68 -#define JZ4780_CLK_SMB4 69 -#define JZ4780_CLK_DES 70 -#define JZ4780_CLK_X2D 71 -#define JZ4780_CLK_CORE1 72 -#define JZ4780_CLK_EXCLK_DIV512 73 -#define JZ4780_CLK_RTC 74 - -#endif /* __DT_BINDINGS_CLOCK_JZ4780_CGU_H__ */ diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h deleted file mode 100644 index f187e0719fd3..000000000000 --- a/include/dt-bindings/clock/x1000-cgu.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,x1000-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the x1000 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__ -#define __DT_BINDINGS_CLOCK_X1000_CGU_H__ - -#define X1000_CLK_EXCLK 0 -#define X1000_CLK_RTCLK 1 -#define X1000_CLK_APLL 2 -#define X1000_CLK_MPLL 3 -#define X1000_CLK_OTGPHY 4 -#define X1000_CLK_SCLKA 5 -#define X1000_CLK_CPUMUX 6 -#define X1000_CLK_CPU 7 -#define X1000_CLK_L2CACHE 8 -#define X1000_CLK_AHB0 9 -#define X1000_CLK_AHB2PMUX 10 -#define X1000_CLK_AHB2 11 -#define X1000_CLK_PCLK 12 -#define X1000_CLK_DDR 13 -#define X1000_CLK_MAC 14 -#define X1000_CLK_LCD 15 -#define X1000_CLK_MSCMUX 16 -#define X1000_CLK_MSC0 17 -#define X1000_CLK_MSC1 18 -#define X1000_CLK_OTG 19 -#define X1000_CLK_SSIPLL 20 -#define X1000_CLK_SSIPLL_DIV2 21 -#define X1000_CLK_SSIMUX 22 -#define X1000_CLK_EMC 23 -#define X1000_CLK_EFUSE 24 -#define X1000_CLK_SFC 25 -#define X1000_CLK_I2C0 26 -#define X1000_CLK_I2C1 27 -#define X1000_CLK_I2C2 28 -#define X1000_CLK_UART0 29 -#define X1000_CLK_UART1 30 -#define X1000_CLK_UART2 31 -#define X1000_CLK_TCU 32 -#define X1000_CLK_SSI 33 -#define X1000_CLK_OST 34 -#define X1000_CLK_PDMA 35 -#define X1000_CLK_EXCLK_DIV512 36 -#define X1000_CLK_RTC 37 - -#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h deleted file mode 100644 index 88455376a950..000000000000 --- a/include/dt-bindings/clock/x1830-cgu.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides clock numbers for the ingenic,x1830-cgu DT binding. - * - * They are roughly ordered as: - * - external clocks - * - PLLs - * - muxes/dividers in the order they appear in the x1830 programmers manual - * - gates in order of their bit in the CLKGR* registers - */ - -#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__ -#define __DT_BINDINGS_CLOCK_X1830_CGU_H__ - -#define X1830_CLK_EXCLK 0 -#define X1830_CLK_RTCLK 1 -#define X1830_CLK_APLL 2 -#define X1830_CLK_MPLL 3 -#define X1830_CLK_EPLL 4 -#define X1830_CLK_VPLL 5 -#define X1830_CLK_OTGPHY 6 -#define X1830_CLK_SCLKA 7 -#define X1830_CLK_CPUMUX 8 -#define X1830_CLK_CPU 9 -#define X1830_CLK_L2CACHE 10 -#define X1830_CLK_AHB0 11 -#define X1830_CLK_AHB2PMUX 12 -#define X1830_CLK_AHB2 13 -#define X1830_CLK_PCLK 14 -#define X1830_CLK_DDR 15 -#define X1830_CLK_MAC 16 -#define X1830_CLK_LCD 17 -#define X1830_CLK_MSCMUX 18 -#define X1830_CLK_MSC0 19 -#define X1830_CLK_MSC1 20 -#define X1830_CLK_SSIPLL 21 -#define X1830_CLK_SSIPLL_DIV2 22 -#define X1830_CLK_SSIMUX 23 -#define X1830_CLK_EMC 24 -#define X1830_CLK_EFUSE 25 -#define X1830_CLK_OTG 26 -#define X1830_CLK_SSI0 27 -#define X1830_CLK_SMB0 28 -#define X1830_CLK_SMB1 29 -#define X1830_CLK_SMB2 30 -#define X1830_CLK_UART0 31 -#define X1830_CLK_UART1 32 -#define X1830_CLK_SSI1 33 -#define X1830_CLK_SFC 34 -#define X1830_CLK_PDMA 35 -#define X1830_CLK_TCU 36 -#define X1830_CLK_DTRNG 37 -#define X1830_CLK_OST 38 -#define X1830_CLK_EXCLK_DIV512 39 -#define X1830_CLK_RTC 40 - -#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ -- cgit v1.2.3