From 0c6609805b638debcb7d9d44556546b043ded2e9 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 16 May 2018 09:35:57 +0200 Subject: mfd: stm32-timers: Add support for DMAs STM32 Timers can support up to 7 DMA requests: - 4 channels, update, compare and trigger. Optionally request part, or all DMAs from stm32-timers MFD core. Also add routine to implement burst reads using DMA from timer registers. This is exported. So, it can be used by child drivers, PWM capture for instance (but not limited to). Signed-off-by: Fabrice Gasnier Reviewed-by: Benjamin Gaignard Signed-off-by: Lee Jones --- include/linux/mfd/stm32-timers.h | 46 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'include') diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 2aadab6f34a1..9596d5c58859 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -8,6 +8,8 @@ #define _LINUX_STM32_GPTIMER_H_ #include +#include +#include #include #define TIM_CR1 0x00 /* Control Register 1 */ @@ -27,6 +29,8 @@ #define TIM_CCR3 0x3C /* Capt/Comp Register 3 */ #define TIM_CCR4 0x40 /* Capt/Comp Register 4 */ #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ +#define TIM_DCR 0x48 /* DMA control register */ +#define TIM_DMAR 0x4C /* DMA register for transfer */ #define TIM_CR1_CEN BIT(0) /* Counter Enable */ #define TIM_CR1_DIR BIT(4) /* Counter Direction */ @@ -36,6 +40,13 @@ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ #define TIM_DIER_UIE BIT(0) /* Update interrupt */ +#define TIM_DIER_UDE BIT(8) /* Update DMA request Enable */ +#define TIM_DIER_CC1DE BIT(9) /* CC1 DMA request Enable */ +#define TIM_DIER_CC2DE BIT(10) /* CC2 DMA request Enable */ +#define TIM_DIER_CC3DE BIT(11) /* CC3 DMA request Enable */ +#define TIM_DIER_CC4DE BIT(12) /* CC4 DMA request Enable */ +#define TIM_DIER_COMDE BIT(13) /* COM DMA request Enable */ +#define TIM_DIER_TDE BIT(14) /* Trigger DMA request Enable */ #define TIM_SR_UIF BIT(0) /* Update interrupt flag */ #define TIM_EGR_UG BIT(0) /* Update Generation */ #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ @@ -56,6 +67,8 @@ #define TIM_BDTR_BK2F (BIT(20) | BIT(21) | BIT(22) | BIT(23)) #define TIM_BDTR_BK2E BIT(24) /* Break 2 input enable */ #define TIM_BDTR_BK2P BIT(25) /* Break 2 input polarity */ +#define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */ +#define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */ #define MAX_TIM_PSC 0xFFFF #define TIM_CR2_MMS_SHIFT 4 @@ -65,9 +78,42 @@ #define TIM_BDTR_BKF_SHIFT 16 #define TIM_BDTR_BK2F_SHIFT 20 +enum stm32_timers_dmas { + STM32_TIMERS_DMA_CH1, + STM32_TIMERS_DMA_CH2, + STM32_TIMERS_DMA_CH3, + STM32_TIMERS_DMA_CH4, + STM32_TIMERS_DMA_UP, + STM32_TIMERS_DMA_TRIG, + STM32_TIMERS_DMA_COM, + STM32_TIMERS_MAX_DMAS, +}; + +/** + * struct stm32_timers_dma - STM32 timer DMA handling. + * @completion: end of DMA transfer completion + * @phys_base: control registers physical base address + * @lock: protect DMA access + * @chan: DMA channel in use + * @chans: DMA channels available for this timer instance + */ +struct stm32_timers_dma { + struct completion completion; + phys_addr_t phys_base; + struct mutex lock; + struct dma_chan *chan; + struct dma_chan *chans[STM32_TIMERS_MAX_DMAS]; +}; + struct stm32_timers { struct clk *clk; struct regmap *regmap; u32 max_arr; + struct stm32_timers_dma dma; /* Only to be used by the parent */ }; + +int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, + enum stm32_timers_dmas id, u32 reg, + unsigned int num_reg, unsigned int bursts, + unsigned long tmo_ms); #endif -- cgit v1.2.3 From 53e38fe73f941291fd20794c15c3bb7b104a4a17 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 16 May 2018 09:35:58 +0200 Subject: pwm: stm32: Add capture support Add support for PMW input mode on pwm-stm32. STM32 timers support period and duty cycle capture as long as they have at least two PWM channels. One capture channel is used for period (rising-edge), one for duty-cycle (falling-edge). When there's only one channel available, only period can be captured. Duty-cycle is simply zero'ed in such a case. Capture requires exclusive access (e.g. no pwm output running at the same time, to protect common prescaler). Timer DMA burst mode (from MFD core) is being used, to take two snapshots of capture registers (upon each period rising edge). Signed-off-by: Fabrice Gasnier Reviewed-by: Benjamin Gaignard Acked-by: Thierry Reding Signed-off-by: Lee Jones --- drivers/pwm/pwm-stm32.c | 176 +++++++++++++++++++++++++++++++++++++++ include/linux/mfd/stm32-timers.h | 11 +++ 2 files changed, 187 insertions(+) (limited to 'include') diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index 2708212933f7..ed3961b7b938 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -25,6 +25,7 @@ struct stm32_pwm { struct regmap *regmap; u32 max_arr; bool have_complementary_output; + u32 capture[4] ____cacheline_aligned; /* DMA'able buffer */ }; struct stm32_breakinput { @@ -62,6 +63,178 @@ static int write_ccrx(struct stm32_pwm *dev, int ch, u32 value) return -EINVAL; } +#define TIM_CCER_CC12P (TIM_CCER_CC1P | TIM_CCER_CC2P) +#define TIM_CCER_CC12E (TIM_CCER_CC1E | TIM_CCER_CC2E) +#define TIM_CCER_CC34P (TIM_CCER_CC3P | TIM_CCER_CC4P) +#define TIM_CCER_CC34E (TIM_CCER_CC3E | TIM_CCER_CC4E) + +/* + * Capture using PWM input mode: + * ___ ___ + * TI[1, 2, 3 or 4]: ........._| |________| + * ^0 ^1 ^2 + * . . . + * . . XXXXX + * . . XXXXX | + * . XXXXX . | + * XXXXX . . | + * COUNTER: ______XXXXX . . . |_XXX + * start^ . . . ^stop + * . . . . + * v v . v + * v + * CCR1/CCR3: tx..........t0...........t2 + * CCR2/CCR4: tx..............t1......... + * + * DMA burst transfer: | | + * v v + * DMA buffer: { t0, tx } { t2, t1 } + * DMA done: ^ + * + * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 + * + DMA transfer CCR[1/3] & CCR[2/4] values (t0, tx: doesn't care) + * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 + * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 + * + DMA transfer CCR[1/3] & CCR[2/4] values (t2, t1) + * + * DMA done, compute: + * - Period = t2 - t0 + * - Duty cycle = t1 - t0 + */ +static int stm32_pwm_raw_capture(struct stm32_pwm *priv, struct pwm_device *pwm, + unsigned long tmo_ms, u32 *raw_prd, + u32 *raw_dty) +{ + struct device *parent = priv->chip.dev->parent; + enum stm32_timers_dmas dma_id; + u32 ccen, ccr; + int ret; + + /* Ensure registers have been updated, enable counter and capture */ + regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); + + /* Use cc1 or cc3 DMA resp for PWM input channels 1 & 2 or 3 & 4 */ + dma_id = pwm->hwpwm < 2 ? STM32_TIMERS_DMA_CH1 : STM32_TIMERS_DMA_CH3; + ccen = pwm->hwpwm < 2 ? TIM_CCER_CC12E : TIM_CCER_CC34E; + ccr = pwm->hwpwm < 2 ? TIM_CCR1 : TIM_CCR3; + regmap_update_bits(priv->regmap, TIM_CCER, ccen, ccen); + + /* + * Timer DMA burst mode. Request 2 registers, 2 bursts, to get both + * CCR1 & CCR2 (or CCR3 & CCR4) on each capture event. + * We'll get two capture snapchots: { CCR1, CCR2 }, { CCR1, CCR2 } + * or { CCR3, CCR4 }, { CCR3, CCR4 } + */ + ret = stm32_timers_dma_burst_read(parent, priv->capture, dma_id, ccr, 2, + 2, tmo_ms); + if (ret) + goto stop; + + /* Period: t2 - t0 (take care of counter overflow) */ + if (priv->capture[0] <= priv->capture[2]) + *raw_prd = priv->capture[2] - priv->capture[0]; + else + *raw_prd = priv->max_arr - priv->capture[0] + priv->capture[2]; + + /* Duty cycle capture requires at least two capture units */ + if (pwm->chip->npwm < 2) + *raw_dty = 0; + else if (priv->capture[0] <= priv->capture[3]) + *raw_dty = priv->capture[3] - priv->capture[0]; + else + *raw_dty = priv->max_arr - priv->capture[0] + priv->capture[3]; + + if (*raw_dty > *raw_prd) { + /* + * Race beetween PWM input and DMA: it may happen + * falling edge triggers new capture on TI2/4 before DMA + * had a chance to read CCR2/4. It means capture[1] + * contains period + duty_cycle. So, subtract period. + */ + *raw_dty -= *raw_prd; + } + +stop: + regmap_update_bits(priv->regmap, TIM_CCER, ccen, 0); + regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); + + return ret; +} + +static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_capture *result, unsigned long tmo_ms) +{ + struct stm32_pwm *priv = to_stm32_pwm_dev(chip); + unsigned long long prd, div, dty; + unsigned long rate; + unsigned int psc = 0; + u32 raw_prd, raw_dty; + int ret = 0; + + mutex_lock(&priv->lock); + + if (active_channels(priv)) { + ret = -EBUSY; + goto unlock; + } + + ret = clk_enable(priv->clk); + if (ret) { + dev_err(priv->chip.dev, "failed to enable counter clock\n"); + goto unlock; + } + + rate = clk_get_rate(priv->clk); + if (!rate) { + ret = -EINVAL; + goto clk_dis; + } + + /* prescaler: fit timeout window provided by upper layer */ + div = (unsigned long long)rate * (unsigned long long)tmo_ms; + do_div(div, MSEC_PER_SEC); + prd = div; + while ((div > priv->max_arr) && (psc < MAX_TIM_PSC)) { + psc++; + div = prd; + do_div(div, psc + 1); + } + regmap_write(priv->regmap, TIM_ARR, priv->max_arr); + regmap_write(priv->regmap, TIM_PSC, psc); + + /* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */ + regmap_update_bits(priv->regmap, + pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, + TIM_CCMR_CC1S | TIM_CCMR_CC2S, pwm->hwpwm & 0x1 ? + TIM_CCMR_CC1S_TI2 | TIM_CCMR_CC2S_TI2 : + TIM_CCMR_CC1S_TI1 | TIM_CCMR_CC2S_TI1); + + /* Capture period on IC1/3 rising edge, duty cycle on IC2/4 falling. */ + regmap_update_bits(priv->regmap, TIM_CCER, pwm->hwpwm < 2 ? + TIM_CCER_CC12P : TIM_CCER_CC34P, pwm->hwpwm < 2 ? + TIM_CCER_CC2P : TIM_CCER_CC4P); + + ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty); + if (ret) + goto stop; + + prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; + result->period = DIV_ROUND_UP_ULL(prd, rate); + dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; + result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); +stop: + regmap_write(priv->regmap, TIM_CCER, 0); + regmap_write(priv->regmap, pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, 0); + regmap_write(priv->regmap, TIM_PSC, 0); +clk_dis: + clk_disable(priv->clk); +unlock: + mutex_unlock(&priv->lock); + + return ret; +} + static int stm32_pwm_config(struct stm32_pwm *priv, int ch, int duty_ns, int period_ns) { @@ -230,6 +403,9 @@ static int stm32_pwm_apply_locked(struct pwm_chip *chip, struct pwm_device *pwm, static const struct pwm_ops stm32pwm_ops = { .owner = THIS_MODULE, .apply = stm32_pwm_apply_locked, +#if IS_ENABLED(CONFIG_DMA_ENGINE) + .capture = stm32_pwm_capture, +#endif }; static int stm32_pwm_set_breakinput(struct stm32_pwm *priv, diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 9596d5c58859..d46f5500928e 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -51,13 +51,24 @@ #define TIM_EGR_UG BIT(0) /* Update Generation */ #define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */ #define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */ +#define TIM_CCMR_CC1S (BIT(0) | BIT(1)) /* Capture/compare 1 sel */ +#define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */ +#define TIM_CCMR_CC2S (BIT(8) | BIT(9)) /* Capture/compare 2 sel */ +#define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */ +#define TIM_CCMR_CC1S_TI1 BIT(0) /* IC1/IC3 selects TI1/TI3 */ +#define TIM_CCMR_CC1S_TI2 BIT(1) /* IC1/IC3 selects TI2/TI4 */ +#define TIM_CCMR_CC2S_TI2 BIT(8) /* IC2/IC4 selects TI2/TI4 */ +#define TIM_CCMR_CC2S_TI1 BIT(9) /* IC2/IC4 selects TI1/TI3 */ #define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */ #define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */ #define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */ #define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */ #define TIM_CCER_CC2E BIT(4) /* Capt/Comp 2 out Ena */ +#define TIM_CCER_CC2P BIT(5) /* Capt/Comp 2 Polarity */ #define TIM_CCER_CC3E BIT(8) /* Capt/Comp 3 out Ena */ +#define TIM_CCER_CC3P BIT(9) /* Capt/Comp 3 Polarity */ #define TIM_CCER_CC4E BIT(12) /* Capt/Comp 4 out Ena */ +#define TIM_CCER_CC4P BIT(13) /* Capt/Comp 4 Polarity */ #define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12)) #define TIM_BDTR_BKE BIT(12) /* Break input enable */ #define TIM_BDTR_BKP BIT(13) /* Break input polarity */ -- cgit v1.2.3 From ab3a897847834bf3e864fb07b733c444895a24ba Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 16 May 2018 09:36:00 +0200 Subject: pwm: stm32: Use input prescaler to improve period capture Using input prescaler, capture unit will trigger DMA once every configurable /2, /4 or /8 events (rising edge). This helps improve period (only) capture accuracy at high rates. Signed-off-by: Fabrice Gasnier Reviewed-by: Benjamin Gaignard Acked-by: Thierry Reding Signed-off-by: Lee Jones --- drivers/pwm/pwm-stm32.c | 63 ++++++++++++++++++++++++++++++++++++++-- include/linux/mfd/stm32-timers.h | 1 + 2 files changed, 62 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index 9a50acde1e61..60bfc07c4912 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -8,6 +8,7 @@ * pwm-atmel.c from Bo Shen */ +#include #include #include #include @@ -168,7 +169,7 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, struct stm32_pwm *priv = to_stm32_pwm_dev(chip); unsigned long long prd, div, dty; unsigned long rate; - unsigned int psc = 0, scale; + unsigned int psc = 0, icpsc, scale; u32 raw_prd, raw_dty; int ret = 0; @@ -222,6 +223,7 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, /* * Got a capture. Try to improve accuracy at high rates: * - decrease counter clock prescaler, scale up to max rate. + * - use input prescaler, capture once every /2 /4 or /8 edges. */ if (raw_prd) { u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ @@ -241,8 +243,65 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, goto stop; } + /* Compute intermediate period not to exceed timeout at low rates */ prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; - result->period = DIV_ROUND_UP_ULL(prd, rate); + do_div(prd, rate); + + for (icpsc = 0; icpsc < MAX_TIM_ICPSC ; icpsc++) { + /* input prescaler: also keep arbitrary margin */ + if (raw_prd >= (priv->max_arr - 0x1000) >> (icpsc + 1)) + break; + if (prd >= (tmo_ms * NSEC_PER_MSEC) >> (icpsc + 2)) + break; + } + + if (!icpsc) + goto done; + + /* Last chance to improve period accuracy, using input prescaler */ + regmap_update_bits(priv->regmap, + pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2, + TIM_CCMR_IC1PSC | TIM_CCMR_IC2PSC, + FIELD_PREP(TIM_CCMR_IC1PSC, icpsc) | + FIELD_PREP(TIM_CCMR_IC2PSC, icpsc)); + + ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, &raw_dty); + if (ret) + goto stop; + + if (raw_dty >= (raw_prd >> icpsc)) { + /* + * We may fall here using input prescaler, when input + * capture starts on high side (before falling edge). + * Example with icpsc to capture on each 4 events: + * + * start 1st capture 2nd capture + * v v v + * ___ _____ _____ _____ _____ ____ + * TI1..4 |__| |__| |__| |__| |__| + * v v . . . . . v v + * icpsc1/3: . 0 . 1 . 2 . 3 . 0 + * icpsc2/4: 0 1 2 3 0 + * v v v v + * CCR1/3 ......t0..............................t2 + * CCR2/4 ..t1..............................t1'... + * . . . + * Capture0: .<----------------------------->. + * Capture1: .<-------------------------->. . + * . . . + * Period: .<------> . . + * Low side: .<>. + * + * Result: + * - Period = Capture0 / icpsc + * - Duty = Period - Low side = Period - (Capture0 - Capture1) + */ + raw_dty = (raw_prd >> icpsc) - (raw_prd - raw_dty); + } + +done: + prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; + result->period = DIV_ROUND_UP_ULL(prd, rate << icpsc); dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC; result->duty_cycle = DIV_ROUND_UP_ULL(dty, rate); stop: diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index d46f5500928e..9da1d7ece079 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -82,6 +82,7 @@ #define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */ #define MAX_TIM_PSC 0xFFFF +#define MAX_TIM_ICPSC 0x3 #define TIM_CR2_MMS_SHIFT 4 #define TIM_CR2_MMS2_SHIFT 20 #define TIM_SMCR_TS_SHIFT 4 -- cgit v1.2.3 From 30feec093021ef665233a3c78a99f444673389a2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Jan 2018 19:59:21 +0100 Subject: mfd: syscon: Remove unused Exynos PMU headers Since commit 5812f0106c44 ("phy: exynos4: Remove duplicated defines of PHY register defines") and commit 7a66647b25b6 ("phy: exynos: Use one define for enable bit") all users of syscon Exynos PMU headers (for PHY drivers) are converted to use different headers so these can be removed. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Lee Jones --- include/linux/mfd/syscon/exynos4-pmu.h | 21 --------------------- include/linux/mfd/syscon/exynos5-pmu.h | 19 ------------------- 2 files changed, 40 deletions(-) delete mode 100644 include/linux/mfd/syscon/exynos4-pmu.h delete mode 100644 include/linux/mfd/syscon/exynos5-pmu.h (limited to 'include') diff --git a/include/linux/mfd/syscon/exynos4-pmu.h b/include/linux/mfd/syscon/exynos4-pmu.h deleted file mode 100644 index 278b1b1549e9..000000000000 --- a/include/linux/mfd/syscon/exynos4-pmu.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2015 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ -#define _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ - -/* Exynos4 PMU register definitions */ - -/* MIPI_PHYn_CONTROL register offset: n = 0..1 */ -#define EXYNOS4_MIPI_PHY_CONTROL(n) (0x710 + (n) * 4) -#define EXYNOS4_MIPI_PHY_ENABLE (1 << 0) -#define EXYNOS4_MIPI_PHY_SRESETN (1 << 1) -#define EXYNOS4_MIPI_PHY_MRESETN (1 << 2) -#define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1) - -#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ */ diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h deleted file mode 100644 index b4942a32b81d..000000000000 --- a/include/linux/mfd/syscon/exynos5-pmu.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Exynos5 SoC series Power Management Unit (PMU) register offsets - * and bit definitions. - * - * Copyright (C) 2014 Samsung Electronics Co., Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ -#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ - -#define EXYNOS5_PHY_ENABLE BIT(0) -#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) -#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) - -#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */ -- cgit v1.2.3 From efc9b2048c7f6bb52f70cc84b8b8b8dcc685a0d6 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Thu, 15 Feb 2018 22:17:05 -0600 Subject: mfd: tps65218: Reorder tps65218_regulator_id enum Commit 2dc4940360d4 ("regulator: tps65218: Remove all the compatibles") changes the probe function of drivers/regulator/tps65218-regulator.c so that it iterates through all available regulators and assumes that the regulator IDs are sequential and match the order present in the enum tps65218_regulator_id. However, for some reason the much older commit c0ea88b890d6 ("regulator: tps65218: add support for LS3 current regulator") updated all arrays with LS3 at the end but added it second to last for the enum. Because of this long standing mismatch in order between the tps65218_regulator_id enum and the regulator_desc array in the tps65218 regulator driver, the new probe function causes the strobe values to be associated with the wrong regulator ID. This causes LDO1 to fail to suspend in tps65218_pmic_set_suspend_disable due to not having anything probes for its strobe value. Fix the order in the enum so the probe function works as the update intended. Fixes: 2dc4940360d4 ("regulator: tps65218: Remove all the compatibles") Signed-off-by: Dave Gerlach Signed-off-by: Lee Jones --- include/linux/mfd/tps65218.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/mfd/tps65218.h b/include/linux/mfd/tps65218.h index f069c518c0ed..c204d9a79436 100644 --- a/include/linux/mfd/tps65218.h +++ b/include/linux/mfd/tps65218.h @@ -205,10 +205,10 @@ enum tps65218_regulator_id { TPS65218_DCDC_4, TPS65218_DCDC_5, TPS65218_DCDC_6, - /* LS's */ - TPS65218_LS_3, /* LDOs */ TPS65218_LDO_1, + /* LS's */ + TPS65218_LS_3, }; #define TPS65218_MAX_REG_ID TPS65218_LDO_1 -- cgit v1.2.3 From 37c089d1facaf03969f66a5469c169a2c73429f6 Mon Sep 17 00:00:00 2001 From: Rajmohan Mani Date: Tue, 20 Feb 2018 15:54:07 -0800 Subject: mfd: Update to SPDX license identifier Remove the GPL v2 license boilerplate and update with the SPDX license identifier. Signed-off-by: Rajmohan Mani Signed-off-by: Lee Jones --- drivers/mfd/tps68470.c | 10 +--------- include/linux/mfd/tps68470.h | 17 +++-------------- 2 files changed, 4 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/mfd/tps68470.c b/drivers/mfd/tps68470.c index 189efaea054c..a5981a79b29a 100644 --- a/drivers/mfd/tps68470.c +++ b/drivers/mfd/tps68470.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * TPS68470 chip Parent driver * @@ -8,15 +9,6 @@ * Tianshu Qiu * Jian Xu Zheng * Yuning Pu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include diff --git a/include/linux/mfd/tps68470.h b/include/linux/mfd/tps68470.h index 44f9d9f647ed..ffe81127d91c 100644 --- a/include/linux/mfd/tps68470.h +++ b/include/linux/mfd/tps68470.h @@ -1,17 +1,6 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * Functions to access TPS68470 power management chip. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2017 Intel Corporation */ +/* Functions to access TPS68470 power management chip. */ #ifndef __LINUX_MFD_TPS68470_H #define __LINUX_MFD_TPS68470_H -- cgit v1.2.3 From 99fb0f25c448ab72481bd700b66e0e48c583ef5a Mon Sep 17 00:00:00 2001 From: Wenkai Du Date: Thu, 22 Feb 2018 13:30:52 -0800 Subject: Revert "mfd: cros_ec: Add ACPI GPE handler for LID0 devices" This reverts commit e04653a9dcf4d98defe2149c885382e5cc72082f. It is no longer needed to install Chrome EC GPE handler to have GPE enabled in suspend to idle path. It is found that with this handler installed, EC wake up doesn't work because default EC event handler that can wake up system is not getting called. Signed-off-by: Wenkai Du Acked-by: Benson Leung Signed-off-by: Lee Jones --- drivers/mfd/Makefile | 1 - drivers/mfd/cros_ec.c | 15 ++---- drivers/mfd/cros_ec_acpi_gpe.c | 103 ----------------------------------------- include/linux/mfd/cros_ec.h | 18 ------- 4 files changed, 3 insertions(+), 134 deletions(-) delete mode 100644 drivers/mfd/cros_ec_acpi_gpe.c (limited to 'include') diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index d9d2cf0d32ef..e9fd20dba18d 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -13,7 +13,6 @@ obj-$(CONFIG_MFD_ASIC3) += asic3.o tmio_core.o obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o obj-$(CONFIG_MFD_BD9571MWV) += bd9571mwv.o cros_ec_core-objs := cros_ec.o -cros_ec_core-$(CONFIG_ACPI) += cros_ec_acpi_gpe.o obj-$(CONFIG_MFD_CROS_EC) += cros_ec_core.o obj-$(CONFIG_MFD_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_MFD_CROS_EC_SPI) += cros_ec_spi.o diff --git a/drivers/mfd/cros_ec.c b/drivers/mfd/cros_ec.c index d61024141e2b..c221163d5b9e 100644 --- a/drivers/mfd/cros_ec.c +++ b/drivers/mfd/cros_ec.c @@ -173,8 +173,6 @@ int cros_ec_register(struct cros_ec_device *ec_dev) dev_info(dev, "Chrome EC device registered\n"); - cros_ec_acpi_install_gpe_handler(dev); - return 0; fail_mfd: @@ -188,8 +186,6 @@ int cros_ec_remove(struct cros_ec_device *ec_dev) { mfd_remove_devices(ec_dev->dev); - cros_ec_acpi_remove_gpe_handler(); - if (ec_dev->irq) free_irq(ec_dev->irq, ec_dev); @@ -204,14 +200,9 @@ int cros_ec_suspend(struct cros_ec_device *ec_dev) int ret; u8 sleep_event; - if (!IS_ENABLED(CONFIG_ACPI) || pm_suspend_via_firmware()) { - sleep_event = HOST_SLEEP_EVENT_S3_SUSPEND; - } else { - sleep_event = HOST_SLEEP_EVENT_S0IX_SUSPEND; - - /* Clearing the GPE status for any pending event */ - cros_ec_acpi_clear_gpe(); - } + sleep_event = (!IS_ENABLED(CONFIG_ACPI) || pm_suspend_via_firmware()) ? + HOST_SLEEP_EVENT_S3_SUSPEND : + HOST_SLEEP_EVENT_S0IX_SUSPEND; ret = cros_ec_sleep_event(ec_dev, sleep_event); if (ret < 0) diff --git a/drivers/mfd/cros_ec_acpi_gpe.c b/drivers/mfd/cros_ec_acpi_gpe.c deleted file mode 100644 index 56d305dab2d4..000000000000 --- a/drivers/mfd/cros_ec_acpi_gpe.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * ChromeOS EC multi-function device - * - * Copyright (C) 2017 Google, Inc - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * The ChromeOS EC multi function device is used to mux all the requests - * to the EC device for its multiple features: keyboard controller, - * battery charging and regulator control, firmware update. - */ -#include - -#define ACPI_LID_DEVICE "LID0" - -static int ec_wake_gpe = -EINVAL; - -/* - * This handler indicates to ACPI core that this GPE should stay enabled for - * lid to work in suspend to idle path. - */ -static u32 cros_ec_gpe_handler(acpi_handle gpe_device, u32 gpe_number, - void *data) -{ - return ACPI_INTERRUPT_HANDLED | ACPI_REENABLE_GPE; -} - -/* - * Get ACPI GPE for LID0 device. - */ -static int cros_ec_get_ec_wake_gpe(struct device *dev) -{ - struct acpi_device *cros_acpi_dev; - struct acpi_device *adev; - acpi_handle handle; - acpi_status status; - int ret; - - cros_acpi_dev = ACPI_COMPANION(dev); - - if (!cros_acpi_dev || !cros_acpi_dev->parent || - !cros_acpi_dev->parent->handle) - return -EINVAL; - - status = acpi_get_handle(cros_acpi_dev->parent->handle, ACPI_LID_DEVICE, - &handle); - if (ACPI_FAILURE(status)) - return -EINVAL; - - ret = acpi_bus_get_device(handle, &adev); - if (ret) - return ret; - - return adev->wakeup.gpe_number; -} - -int cros_ec_acpi_install_gpe_handler(struct device *dev) -{ - acpi_status status; - - ec_wake_gpe = cros_ec_get_ec_wake_gpe(dev); - - if (ec_wake_gpe < 0) - return ec_wake_gpe; - - status = acpi_install_gpe_handler(NULL, ec_wake_gpe, - ACPI_GPE_EDGE_TRIGGERED, - &cros_ec_gpe_handler, NULL); - if (ACPI_FAILURE(status)) - return -ENODEV; - - dev_info(dev, "Initialized, GPE = 0x%x\n", ec_wake_gpe); - - return 0; -} - -void cros_ec_acpi_remove_gpe_handler(void) -{ - acpi_status status; - - if (ec_wake_gpe < 0) - return; - - status = acpi_remove_gpe_handler(NULL, ec_wake_gpe, - &cros_ec_gpe_handler); - if (ACPI_FAILURE(status)) - pr_err("failed to remove gpe handler\n"); -} - -void cros_ec_acpi_clear_gpe(void) -{ - if (ec_wake_gpe < 0) - return; - - acpi_clear_gpe(NULL, ec_wake_gpe); -} diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h index 2d4e23c9ea0a..4ff0cec979b0 100644 --- a/include/linux/mfd/cros_ec.h +++ b/include/linux/mfd/cros_ec.h @@ -328,22 +328,4 @@ extern struct attribute_group cros_ec_vbc_attr_group; int cros_ec_debugfs_init(struct cros_ec_dev *ec); void cros_ec_debugfs_remove(struct cros_ec_dev *ec); -/* ACPI GPE handler */ -#ifdef CONFIG_ACPI - -int cros_ec_acpi_install_gpe_handler(struct device *dev); -void cros_ec_acpi_remove_gpe_handler(void); -void cros_ec_acpi_clear_gpe(void); - -#else /* CONFIG_ACPI */ - -static inline int cros_ec_acpi_install_gpe_handler(struct device *dev) -{ - return -ENODEV; -} -static inline void cros_ec_acpi_remove_gpe_handler(void) {} -static inline void cros_ec_acpi_clear_gpe(void) {} - -#endif /* CONFIG_ACPI */ - #endif /* __LINUX_MFD_CROS_EC_H */ -- cgit v1.2.3 From c18604660ad02324dfc21de5dfd0c8d15e9070a5 Mon Sep 17 00:00:00 2001 From: Charles Keepax Date: Mon, 12 Mar 2018 15:52:00 +0000 Subject: mfd: arizona: Update reset pin to use GPIOD Now GPIOD has support for both pdata systems and for non-standard DT bindings the Arizona reset GPIO can be converted to use it. Worth noting gpiod_set_raw_value_cansleep is used to match the behaviour of the old GPIOs. This is because the part is fairly widely used and it is unknown how many DTs are correctly setting active low through device tree, so to avoid breaking any existing users it is best to match the previous behaviour. Signed-off-by: Charles Keepax Reviewed-by: Linus Walleij Signed-off-by: Lee Jones --- drivers/mfd/arizona-core.c | 53 ++++++++++++++++++++++++++------------- include/linux/mfd/arizona/pdata.h | 3 ++- 2 files changed, 37 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c index 77875250abe5..83f1c5a516d9 100644 --- a/drivers/mfd/arizona-core.c +++ b/drivers/mfd/arizona-core.c @@ -13,13 +13,12 @@ #include #include #include -#include +#include #include #include #include #include #include -#include #include #include #include @@ -279,7 +278,7 @@ static int arizona_wait_for_boot(struct arizona *arizona) static inline void arizona_enable_reset(struct arizona *arizona) { if (arizona->pdata.reset) - gpio_set_value_cansleep(arizona->pdata.reset, 0); + gpiod_set_raw_value_cansleep(arizona->pdata.reset, 0); } static void arizona_disable_reset(struct arizona *arizona) @@ -295,7 +294,7 @@ static void arizona_disable_reset(struct arizona *arizona) break; } - gpio_set_value_cansleep(arizona->pdata.reset, 1); + gpiod_set_raw_value_cansleep(arizona->pdata.reset, 1); usleep_range(1000, 5000); } } @@ -799,14 +798,27 @@ static int arizona_of_get_core_pdata(struct arizona *arizona) struct arizona_pdata *pdata = &arizona->pdata; int ret, i; - pdata->reset = of_get_named_gpio(arizona->dev->of_node, "wlf,reset", 0); - if (pdata->reset == -EPROBE_DEFER) { - return pdata->reset; - } else if (pdata->reset < 0) { - dev_err(arizona->dev, "Reset GPIO missing/malformed: %d\n", - pdata->reset); + /* Handle old non-standard DT binding */ + pdata->reset = devm_gpiod_get_from_of_node(arizona->dev, + arizona->dev->of_node, + "wlf,reset", 0, + GPIOD_OUT_LOW, + "arizona /RESET"); + if (IS_ERR(pdata->reset)) { + ret = PTR_ERR(pdata->reset); - pdata->reset = 0; + /* + * Reset missing will be caught when other binding is read + * but all other errors imply this binding is in use but has + * encountered a problem so should be handled. + */ + if (ret == -EPROBE_DEFER) + return ret; + else if (ret != -ENOENT && ret != -ENOSYS) + dev_err(arizona->dev, "Reset GPIO malformed: %d\n", + ret); + + pdata->reset = NULL; } ret = of_property_read_u32_array(arizona->dev->of_node, @@ -1050,14 +1062,19 @@ int arizona_dev_init(struct arizona *arizona) goto err_early; } - if (arizona->pdata.reset) { + if (!arizona->pdata.reset) { /* Start out with /RESET low to put the chip into reset */ - ret = devm_gpio_request_one(arizona->dev, arizona->pdata.reset, - GPIOF_DIR_OUT | GPIOF_INIT_LOW, - "arizona /RESET"); - if (ret != 0) { - dev_err(dev, "Failed to request /RESET: %d\n", ret); - goto err_dcvdd; + arizona->pdata.reset = devm_gpiod_get(arizona->dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(arizona->pdata.reset)) { + ret = PTR_ERR(arizona->pdata.reset); + if (ret == -EPROBE_DEFER) + goto err_dcvdd; + + dev_err(arizona->dev, + "Reset GPIO missing/malformed: %d\n", ret); + + arizona->pdata.reset = NULL; } } diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h index f72dc53848d7..0013075d4cda 100644 --- a/include/linux/mfd/arizona/pdata.h +++ b/include/linux/mfd/arizona/pdata.h @@ -56,6 +56,7 @@ #define ARIZONA_MAX_PDM_SPK 2 struct regulator_init_data; +struct gpio_desc; struct arizona_micbias { int mV; /** Regulated voltage */ @@ -77,7 +78,7 @@ struct arizona_micd_range { }; struct arizona_pdata { - int reset; /** GPIO controlling /RESET, if any */ + struct gpio_desc *reset; /** GPIO controlling /RESET, if any */ /** Regulator configuration for MICVDD */ struct arizona_micsupp_pdata micvdd; -- cgit v1.2.3 From 531a469ead6ad1e79e8c84ffd4787c0747336e5a Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 29 Mar 2018 12:31:13 +0800 Subject: mfd: axp20x: Constify struct mfd_cell and struct resource The axp20x driver has lots of mfd_cell and resource structs. These can all be const-ified. Signed-off-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- drivers/mfd/axp20x.c | 44 ++++++++++++++++++++++---------------------- include/linux/mfd/axp20x.h | 2 +- 2 files changed, 23 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index aaf2acbef701..14be0f658d74 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -169,18 +169,18 @@ static const struct regmap_access_table axp806_volatile_table = { .n_yes_ranges = ARRAY_SIZE(axp806_volatile_ranges), }; -static struct resource axp152_pek_resources[] = { +static const struct resource axp152_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_RIS_EDGE, "PEK_DBR"), DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"), }; -static struct resource axp20x_ac_power_supply_resources[] = { +static const struct resource axp20x_ac_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"), }; -static struct resource axp20x_pek_resources[] = { +static const struct resource axp20x_pek_resources[] = { { .name = "PEK_DBR", .start = AXP20X_IRQ_PEK_RIS_EDGE, @@ -194,19 +194,19 @@ static struct resource axp20x_pek_resources[] = { }, }; -static struct resource axp20x_usb_power_supply_resources[] = { +static const struct resource axp20x_usb_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_VALID, "VBUS_VALID"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"), }; -static struct resource axp22x_usb_power_supply_resources[] = { +static const struct resource axp22x_usb_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP22X_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), }; -static struct resource axp22x_pek_resources[] = { +static const struct resource axp22x_pek_resources[] = { { .name = "PEK_DBR", .start = AXP22X_IRQ_PEK_RIS_EDGE, @@ -220,7 +220,7 @@ static struct resource axp22x_pek_resources[] = { }, }; -static struct resource axp288_power_button_resources[] = { +static const struct resource axp288_power_button_resources[] = { { .name = "PEK_DBR", .start = AXP288_IRQ_POKP, @@ -235,7 +235,7 @@ static struct resource axp288_power_button_resources[] = { }, }; -static struct resource axp288_fuel_gauge_resources[] = { +static const struct resource axp288_fuel_gauge_resources[] = { { .start = AXP288_IRQ_QWBTU, .end = AXP288_IRQ_QWBTU, @@ -268,7 +268,7 @@ static struct resource axp288_fuel_gauge_resources[] = { }, }; -static struct resource axp803_pek_resources[] = { +static const struct resource axp803_pek_resources[] = { { .name = "PEK_DBR", .start = AXP803_IRQ_PEK_RIS_EDGE, @@ -282,7 +282,7 @@ static struct resource axp803_pek_resources[] = { }, }; -static struct resource axp809_pek_resources[] = { +static const struct resource axp809_pek_resources[] = { { .name = "PEK_DBR", .start = AXP809_IRQ_PEK_RIS_EDGE, @@ -648,7 +648,7 @@ static const struct regmap_irq_chip axp809_regmap_irq_chip = { .num_regs = 5, }; -static struct mfd_cell axp20x_cells[] = { +static const struct mfd_cell axp20x_cells[] = { { .name = "axp20x-gpio", .of_compatible = "x-powers,axp209-gpio", @@ -677,7 +677,7 @@ static struct mfd_cell axp20x_cells[] = { }, }; -static struct mfd_cell axp221_cells[] = { +static const struct mfd_cell axp221_cells[] = { { .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp22x_pek_resources), @@ -703,7 +703,7 @@ static struct mfd_cell axp221_cells[] = { }, }; -static struct mfd_cell axp223_cells[] = { +static const struct mfd_cell axp223_cells[] = { { .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp22x_pek_resources), @@ -729,7 +729,7 @@ static struct mfd_cell axp223_cells[] = { }, }; -static struct mfd_cell axp152_cells[] = { +static const struct mfd_cell axp152_cells[] = { { .name = "axp20x-pek", .num_resources = ARRAY_SIZE(axp152_pek_resources), @@ -737,7 +737,7 @@ static struct mfd_cell axp152_cells[] = { }, }; -static struct resource axp288_adc_resources[] = { +static const struct resource axp288_adc_resources[] = { { .name = "GPADC", .start = AXP288_IRQ_GPADC, @@ -746,7 +746,7 @@ static struct resource axp288_adc_resources[] = { }, }; -static struct resource axp288_extcon_resources[] = { +static const struct resource axp288_extcon_resources[] = { { .start = AXP288_IRQ_VBUS_FALL, .end = AXP288_IRQ_VBUS_FALL, @@ -769,7 +769,7 @@ static struct resource axp288_extcon_resources[] = { }, }; -static struct resource axp288_charger_resources[] = { +static const struct resource axp288_charger_resources[] = { { .start = AXP288_IRQ_OV, .end = AXP288_IRQ_OV, @@ -817,7 +817,7 @@ static struct resource axp288_charger_resources[] = { }, }; -static struct mfd_cell axp288_cells[] = { +static const struct mfd_cell axp288_cells[] = { { .name = "axp288_adc", .num_resources = ARRAY_SIZE(axp288_adc_resources), @@ -848,7 +848,7 @@ static struct mfd_cell axp288_cells[] = { }, }; -static struct mfd_cell axp803_cells[] = { +static const struct mfd_cell axp803_cells[] = { { .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp803_pek_resources), @@ -857,14 +857,14 @@ static struct mfd_cell axp803_cells[] = { { .name = "axp20x-regulator" }, }; -static struct mfd_cell axp806_cells[] = { +static const struct mfd_cell axp806_cells[] = { { .id = 2, .name = "axp20x-regulator", }, }; -static struct mfd_cell axp809_cells[] = { +static const struct mfd_cell axp809_cells[] = { { .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp809_pek_resources), @@ -875,7 +875,7 @@ static struct mfd_cell axp809_cells[] = { }, }; -static struct mfd_cell axp813_cells[] = { +static const struct mfd_cell axp813_cells[] = { { .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp803_pek_resources), diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 82bf7747b312..a2489363a998 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -642,7 +642,7 @@ struct axp20x_dev { struct regmap_irq_chip_data *regmap_irqc; long variant; int nr_cells; - struct mfd_cell *cells; + const struct mfd_cell *cells; const struct regmap_config *regmap_cfg; const struct regmap_irq_chip *regmap_irq_chip; }; -- cgit v1.2.3 From eef2b53a3ec6b1919d32bd722d2f5d33769a1f48 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 29 Mar 2018 12:31:15 +0800 Subject: mfd: axp20x: Correct AXP806 POK interrupt prefix When AXP806 support was added, POK was incorrectly expanded to PWROK. However, the datasheet lists them as POK[LSNP], which is the same as on the AXP288. Furthermore, the registers associated with POK functions are the same as the PEK on the other AXP PMICs. This suggests that "POK" means "Power On Key", much like "PEK" means "Power Enable Key", instead of "Power OK". This patch changes the "PWROK" prefix to "POK" for these interrupts. Signed-off-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- drivers/mfd/axp20x.c | 8 ++++---- include/linux/mfd/axp20x.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index b3051e1c3ddc..9a2ef3d9b8f8 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -450,11 +450,11 @@ static const struct regmap_irq axp806_regmap_irqs[] = { INIT_REGMAP_IRQ(AXP806, DCDCC_V_LOW, 0, 5), INIT_REGMAP_IRQ(AXP806, DCDCD_V_LOW, 0, 6), INIT_REGMAP_IRQ(AXP806, DCDCE_V_LOW, 0, 7), - INIT_REGMAP_IRQ(AXP806, PWROK_LONG, 1, 0), - INIT_REGMAP_IRQ(AXP806, PWROK_SHORT, 1, 1), + INIT_REGMAP_IRQ(AXP806, POK_LONG, 1, 0), + INIT_REGMAP_IRQ(AXP806, POK_SHORT, 1, 1), INIT_REGMAP_IRQ(AXP806, WAKEUP, 1, 4), - INIT_REGMAP_IRQ(AXP806, PWROK_FALL, 1, 5), - INIT_REGMAP_IRQ(AXP806, PWROK_RISE, 1, 6), + INIT_REGMAP_IRQ(AXP806, POK_FALL, 1, 5), + INIT_REGMAP_IRQ(AXP806, POK_RISE, 1, 6), }; static const struct regmap_irq axp809_regmap_irqs[] = { diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index a2489363a998..517e60eecbcb 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -592,11 +592,11 @@ enum axp806_irqs { AXP806_IRQ_DCDCC_V_LOW, AXP806_IRQ_DCDCD_V_LOW, AXP806_IRQ_DCDCE_V_LOW, - AXP806_IRQ_PWROK_LONG, - AXP806_IRQ_PWROK_SHORT, + AXP806_IRQ_POK_LONG, + AXP806_IRQ_POK_SHORT, AXP806_IRQ_WAKEUP, - AXP806_IRQ_PWROK_FALL, - AXP806_IRQ_PWROK_RISE, + AXP806_IRQ_POK_FALL, + AXP806_IRQ_POK_RISE, }; enum axp809_irqs { -- cgit v1.2.3 From 44d99d737279eb2021b2c66df3cee6f8a21ff4e4 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Wed, 18 Apr 2018 12:24:00 +0200 Subject: mfd: cros_ec: Don't try to grab log when suspended We should stop our worker thread while we're suspended. If we don't then we'll get messages like: cros-ec-spi spi5.0: spi transfer failed: -108 cros-ec-spi spi5.0: cs-deassert spi transfer failed: -108 cros-ec-ctl cros-ec-ctl.0.auto: EC communication failed Signed-off-by: Douglas Anderson Signed-off-by: Enric Balletbo i Serra Reviewed-by: Andy Shevchenko Signed-off-by: Lee Jones --- drivers/mfd/cros_ec_dev.c | 4 ++++ drivers/platform/chrome/cros_ec_debugfs.c | 20 ++++++++++++++++++++ include/linux/mfd/cros_ec.h | 2 ++ 3 files changed, 26 insertions(+) (limited to 'include') diff --git a/drivers/mfd/cros_ec_dev.c b/drivers/mfd/cros_ec_dev.c index eafd06f62a3a..5a7d4e1dea70 100644 --- a/drivers/mfd/cros_ec_dev.c +++ b/drivers/mfd/cros_ec_dev.c @@ -466,6 +466,8 @@ static __maybe_unused int ec_device_suspend(struct device *dev) { struct cros_ec_dev *ec = dev_get_drvdata(dev); + cros_ec_debugfs_suspend(ec); + lb_suspend(ec); return 0; @@ -475,6 +477,8 @@ static __maybe_unused int ec_device_resume(struct device *dev) { struct cros_ec_dev *ec = dev_get_drvdata(dev); + cros_ec_debugfs_resume(ec); + lb_resume(ec); return 0; diff --git a/drivers/platform/chrome/cros_ec_debugfs.c b/drivers/platform/chrome/cros_ec_debugfs.c index cc265ed8deb7..c62ee8e610a0 100644 --- a/drivers/platform/chrome/cros_ec_debugfs.c +++ b/drivers/platform/chrome/cros_ec_debugfs.c @@ -470,3 +470,23 @@ void cros_ec_debugfs_remove(struct cros_ec_dev *ec) cros_ec_cleanup_console_log(ec->debug_info); } EXPORT_SYMBOL(cros_ec_debugfs_remove); + +void cros_ec_debugfs_suspend(struct cros_ec_dev *ec) +{ + /* + * cros_ec_debugfs_init() failures are non-fatal; it's also possible + * that we initted things but decided that console log wasn't supported. + * We'll use the same set of checks that cros_ec_debugfs_remove() + + * cros_ec_cleanup_console_log() end up using to handle those cases. + */ + if (ec->debug_info && ec->debug_info->log_buffer.buf) + cancel_delayed_work_sync(&ec->debug_info->log_poll_work); +} +EXPORT_SYMBOL(cros_ec_debugfs_suspend); + +void cros_ec_debugfs_resume(struct cros_ec_dev *ec) +{ + if (ec->debug_info && ec->debug_info->log_buffer.buf) + schedule_delayed_work(&ec->debug_info->log_poll_work, 0); +} +EXPORT_SYMBOL(cros_ec_debugfs_resume); diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h index 4ff0cec979b0..b8e750d91200 100644 --- a/include/linux/mfd/cros_ec.h +++ b/include/linux/mfd/cros_ec.h @@ -327,5 +327,7 @@ extern struct attribute_group cros_ec_vbc_attr_group; /* debugfs stuff */ int cros_ec_debugfs_init(struct cros_ec_dev *ec); void cros_ec_debugfs_remove(struct cros_ec_dev *ec); +void cros_ec_debugfs_suspend(struct cros_ec_dev *ec); +void cros_ec_debugfs_resume(struct cros_ec_dev *ec); #endif /* __LINUX_MFD_CROS_EC_H */ -- cgit v1.2.3 From d95c9760d9c8e046b09b54a3bb6dd0c9aa7a0eff Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Fri, 18 May 2018 17:24:03 +0200 Subject: mfd: stm32-timers: Fix pwm-stm32 linker issue with COMPILE_TEST This is seen when COMPILE_TEST=y and MFD_STM32_TIMERS=n. drivers/pwm/pwm-stm32.o: In function 'stm32_pwm_raw_capture': pwm-stm32.c:... undefined reference to 'stm32_timers_dma_burst_read' Fixes: 0c6609805b63 ("mfd: stm32-timers: Add support for DMAs") Signed-off-by: Fabrice Gasnier Reported-by: Randy Dunlap Tested-by: Randy Dunlap Signed-off-by: Lee Jones --- include/linux/mfd/stm32-timers.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 9da1d7ece079..067d14655c28 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -124,8 +124,20 @@ struct stm32_timers { struct stm32_timers_dma dma; /* Only to be used by the parent */ }; +#if IS_REACHABLE(CONFIG_MFD_STM32_TIMERS) int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, enum stm32_timers_dmas id, u32 reg, unsigned int num_reg, unsigned int bursts, unsigned long tmo_ms); +#else +static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, + enum stm32_timers_dmas id, + u32 reg, + unsigned int num_reg, + unsigned int bursts, + unsigned long tmo_ms) +{ + return -ENODEV; +} +#endif #endif -- cgit v1.2.3