From ef74f70e5a10cc2a78cc5529e564170cabcda9af Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Sat, 19 Jan 2019 15:42:42 -0500 Subject: gpio: add irq domain activate/deactivate functions This adds the two new functions gpiochip_irq_domain_activate and gpiochip_irq_domain_deactivate that can be used as the activate and deactivate functions in the struct irq_domain_ops. This is for situations where only gpiochip_{lock,unlock}_as_irq needs to be called. SPMI and SSBI GPIO are two users that will initially use these functions. Signed-off-by: Brian Masney Suggested-by: Stephen Boyd Reviewed-by: Stephen Boyd Signed-off-by: Linus Walleij --- include/linux/gpio/driver.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 07cddbf45186..01497910f023 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -472,6 +472,11 @@ int gpiochip_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq); void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq); +int gpiochip_irq_domain_activate(struct irq_domain *domain, + struct irq_data *data, bool reserve); +void gpiochip_irq_domain_deactivate(struct irq_domain *domain, + struct irq_data *data); + void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip, struct irq_chip *irqchip, unsigned int parent_irq, -- cgit v1.2.3 From ede033e1e863c36729de25b57145fff287415830 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 7 Feb 2019 17:28:55 +0100 Subject: dt-bindings: gpio: document the new pull-up/pull-down flags This commit extends the flags that can be used in GPIO specifiers to indicate if a pull-up resistor or pull-down resistor should be enabled. While some pinctrl DT bindings already offer the capability of configuring pull-up/pull-down resistors at the pin level, a number of simple GPIO controllers don't have any pinmuxing capability, and therefore do not rely on the pinctrl DT bindings. Such simple GPIO controllers however sometimes allow to configure pull-up and pull-down resistors on a per-pin basis, and whether such resistors should be enabled or not is a highly board-specific HW characteristic. By using two additional bits of the GPIO flag specifier, we can easily allow the Device Tree to describe which GPIOs should have their pull-up or pull-down resistors enabled. Even though the two options are mutually exclusive, we still need two bits to encode at least three states: no pull-up/pull-down, pull-up, pull-down. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/gpio.txt | 12 ++++++++++++ include/dt-bindings/gpio/gpio.h | 6 ++++++ 2 files changed, 18 insertions(+) (limited to 'include') diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index f0ba154b5723..a8895d339bfe 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -67,6 +67,18 @@ Optional standard bitfield specifiers for the last cell: https://en.wikipedia.org/wiki/Open_collector - Bit 3: 0 means the output should be maintained during sleep/low-power mode 1 means the output state can be lost during sleep/low-power mode +- Bit 4: 0 means no pull-up resistor should be enabled + 1 means a pull-up resistor should be enabled + This setting only applies to hardware with a simple on/off + control for pull-up configuration. If the hardware has more + elaborate pull-up configuration, it should be represented + using a pin control binding. +- Bit 5: 0 means no pull-down resistor should be enabled + 1 means a pull-down resistor should be enabled + This setting only applies to hardware with a simple on/off + control for pull-down configuration. If the hardware has more + elaborate pull-down configuration, it should be represented + using a pin control binding. 1.1) GPIO specifier best practices ---------------------------------- diff --git a/include/dt-bindings/gpio/gpio.h b/include/dt-bindings/gpio/gpio.h index 2cc10ae4bbb7..c029467e828b 100644 --- a/include/dt-bindings/gpio/gpio.h +++ b/include/dt-bindings/gpio/gpio.h @@ -33,4 +33,10 @@ #define GPIO_PERSISTENT 0 #define GPIO_TRANSITORY 8 +/* Bit 4 express pull up */ +#define GPIO_PULL_UP 16 + +/* Bit 5 express pull down */ +#define GPIO_PULL_DOWN 32 + #endif -- cgit v1.2.3 From d449991c4d1d0663b42db7648510a9911de21298 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 7 Feb 2019 17:28:58 +0100 Subject: gpio: add core support for pull-up/pull-down configuration This commit adds support for configuring the pull-up and pull-down resistors available in some GPIO controllers. While configuring pull-up/pull-down is already possible through the pinctrl subsystem, some GPIO controllers, especially simple ones such as GPIO expanders on I2C, don't have any pinmuxing capability and therefore do not use the pinctrl subsystem. This commit implements the GPIO_PULL_UP and GPIO_PULL_DOWN flags, which can be used from the Device Tree, to enable a pull-up or pull-down resistor on a given GPIO. The flag is simply propagated all the way to the core GPIO subsystem, where it is used to call the gpio_chip ->set_config callback with the appropriate existing PIN_CONFIG_BIAS_* values. Signed-off-by: Thomas Petazzoni Signed-off-by: Linus Walleij --- drivers/gpio/gpiolib-of.c | 5 +++++ drivers/gpio/gpiolib.c | 18 ++++++++++++++++++ drivers/gpio/gpiolib.h | 2 ++ include/linux/gpio/machine.h | 2 ++ include/linux/of_gpio.h | 2 ++ 5 files changed, 29 insertions(+) (limited to 'include') diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index a6e1891217e2..9a8b78477f79 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -345,6 +345,11 @@ struct gpio_desc *of_find_gpio(struct device *dev, const char *con_id, if (of_flags & OF_GPIO_TRANSITORY) *flags |= GPIO_TRANSITORY; + if (of_flags & OF_GPIO_PULL_UP) + *flags |= GPIO_PULL_UP; + if (of_flags & OF_GPIO_PULL_DOWN) + *flags |= GPIO_PULL_DOWN; + return desc; } diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 1f239aac43df..22d8b37f5319 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -2573,6 +2573,13 @@ int gpiod_direction_input(struct gpio_desc *desc) if (status == 0) clear_bit(FLAG_IS_OUT, &desc->flags); + if (test_bit(FLAG_PULL_UP, &desc->flags)) + gpio_set_config(chip, gpio_chip_hwgpio(desc), + PIN_CONFIG_BIAS_PULL_UP); + else if (test_bit(FLAG_PULL_DOWN, &desc->flags)) + gpio_set_config(chip, gpio_chip_hwgpio(desc), + PIN_CONFIG_BIAS_PULL_DOWN); + trace_gpio_direction(desc_to_gpio(desc), 1, status); return status; @@ -4050,6 +4057,17 @@ int gpiod_configure_flags(struct gpio_desc *desc, const char *con_id, if (lflags & GPIO_OPEN_SOURCE) set_bit(FLAG_OPEN_SOURCE, &desc->flags); + if ((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DOWN)) { + gpiod_err(desc, + "both pull-up and pull-down enabled, invalid configuration\n"); + return -EINVAL; + } + + if (lflags & GPIO_PULL_UP) + set_bit(FLAG_PULL_UP, &desc->flags); + else if (lflags & GPIO_PULL_DOWN) + set_bit(FLAG_PULL_DOWN, &desc->flags); + status = gpiod_set_transitory(desc, (lflags & GPIO_TRANSITORY)); if (status < 0) return status; diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h index bc57f0dc5953..078ab17b96bf 100644 --- a/drivers/gpio/gpiolib.h +++ b/drivers/gpio/gpiolib.h @@ -219,6 +219,8 @@ struct gpio_desc { #define FLAG_IRQ_IS_ENABLED 10 /* GPIO is connected to an enabled IRQ */ #define FLAG_IS_HOGGED 11 /* GPIO is hogged */ #define FLAG_TRANSITORY 12 /* GPIO may lose value in sleep or reset */ +#define FLAG_PULL_UP 13 /* GPIO has pull up enabled */ +#define FLAG_PULL_DOWN 14 /* GPIO has pull down enabled */ /* Connection label */ const char *label; diff --git a/include/linux/gpio/machine.h b/include/linux/gpio/machine.h index daa44eac9241..69673be10213 100644 --- a/include/linux/gpio/machine.h +++ b/include/linux/gpio/machine.h @@ -12,6 +12,8 @@ enum gpio_lookup_flags { GPIO_OPEN_SOURCE = (1 << 2), GPIO_PERSISTENT = (0 << 3), GPIO_TRANSITORY = (1 << 3), + GPIO_PULL_UP = (1 << 4), + GPIO_PULL_DOWN = (1 << 5), }; /** diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h index 163b79ecd01a..f9737dea9d1f 100644 --- a/include/linux/of_gpio.h +++ b/include/linux/of_gpio.h @@ -28,6 +28,8 @@ enum of_gpio_flags { OF_GPIO_SINGLE_ENDED = 0x2, OF_GPIO_OPEN_DRAIN = 0x4, OF_GPIO_TRANSITORY = 0x8, + OF_GPIO_PULL_UP = 0x10, + OF_GPIO_PULL_DOWN = 0x20, }; #ifdef CONFIG_OF_GPIO -- cgit v1.2.3 From b5c231d8c8037f63d34199ea1667bbe1cd9f940f Mon Sep 17 00:00:00 2001 From: Brian Masney Date: Thu, 7 Feb 2019 21:16:22 -0500 Subject: genirq: introduce irq_domain_translate_twocell Add a new function irq_domain_translate_twocell() that is to be used as the translate function in struct irq_domain_ops for the v2 IRQ API. This patch also changes irq_domain_xlate_twocell() from the v1 IRQ API to call irq_domain_translate_twocell() in the v2 IRQ API. This required changes to of_phandle_args_to_fwspec()'s arguments so that it can be called from multiple places. Cc: Thomas Gleixner Reviewed-by: Marc Zyngier Signed-off-by: Brian Masney Signed-off-by: Linus Walleij --- include/linux/irqdomain.h | 5 +++++ kernel/irq/irqdomain.c | 45 ++++++++++++++++++++++++++++++++++----------- 2 files changed, 39 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h index 35965f41d7be..fcefe0c7263f 100644 --- a/include/linux/irqdomain.h +++ b/include/linux/irqdomain.h @@ -419,6 +419,11 @@ int irq_domain_xlate_onetwocell(struct irq_domain *d, struct device_node *ctrlr, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type); +int irq_domain_translate_twocell(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *out_hwirq, + unsigned int *out_type); + /* IPI functions */ int irq_reserve_ipi(struct irq_domain *domain, const struct cpumask *dest); int irq_destroy_ipi(unsigned int irq, const struct cpumask *dest); diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 8b0be4bd6565..56a30d542b8e 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -729,16 +729,17 @@ static int irq_domain_translate(struct irq_domain *d, return 0; } -static void of_phandle_args_to_fwspec(struct of_phandle_args *irq_data, +static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, + unsigned int count, struct irq_fwspec *fwspec) { int i; - fwspec->fwnode = irq_data->np ? &irq_data->np->fwnode : NULL; - fwspec->param_count = irq_data->args_count; + fwspec->fwnode = np ? &np->fwnode : NULL; + fwspec->param_count = count; - for (i = 0; i < irq_data->args_count; i++) - fwspec->param[i] = irq_data->args[i]; + for (i = 0; i < count; i++) + fwspec->param[i] = args[i]; } unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) @@ -836,7 +837,9 @@ unsigned int irq_create_of_mapping(struct of_phandle_args *irq_data) { struct irq_fwspec fwspec; - of_phandle_args_to_fwspec(irq_data, &fwspec); + of_phandle_args_to_fwspec(irq_data->np, irq_data->args, + irq_data->args_count, &fwspec); + return irq_create_fwspec_mapping(&fwspec); } EXPORT_SYMBOL_GPL(irq_create_of_mapping); @@ -928,11 +931,10 @@ int irq_domain_xlate_twocell(struct irq_domain *d, struct device_node *ctrlr, const u32 *intspec, unsigned int intsize, irq_hw_number_t *out_hwirq, unsigned int *out_type) { - if (WARN_ON(intsize < 2)) - return -EINVAL; - *out_hwirq = intspec[0]; - *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; - return 0; + struct irq_fwspec fwspec; + + of_phandle_args_to_fwspec(ctrlr, intspec, intsize, &fwspec); + return irq_domain_translate_twocell(d, &fwspec, out_hwirq, out_type); } EXPORT_SYMBOL_GPL(irq_domain_xlate_twocell); @@ -968,6 +970,27 @@ const struct irq_domain_ops irq_domain_simple_ops = { }; EXPORT_SYMBOL_GPL(irq_domain_simple_ops); +/** + * irq_domain_translate_twocell() - Generic translate for direct two cell + * bindings + * + * Device Tree IRQ specifier translation function which works with two cell + * bindings where the cell values map directly to the hwirq number + * and linux irq flags. + */ +int irq_domain_translate_twocell(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *out_hwirq, + unsigned int *out_type) +{ + if (WARN_ON(fwspec->param_count < 2)) + return -EINVAL; + *out_hwirq = fwspec->param[0]; + *out_type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; + return 0; +} +EXPORT_SYMBOL_GPL(irq_domain_translate_twocell); + int irq_domain_alloc_descs(int virq, unsigned int cnt, irq_hw_number_t hwirq, int node, const struct irq_affinity_desc *affinity) { -- cgit v1.2.3 From 5aa5bd563ce041d931c0dc1fc436dd18c27c60a7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 7 Feb 2019 21:16:23 -0500 Subject: genirq: introduce irq_chip_mask_ack_parent() The hierarchical irqchip never before ran into a situation where the parent is not "simple", i.e. does not implement .irq_ack() and .irq_mask() like most, but the qcom-pm8xxx.c happens to implement only .irq_mask_ack(). Since we want to make ssbi-gpio a hierarchical child of this irqchip, it must *also* only implement .irq_mask_ack() and call down to the parent, and for this we of course need irq_chip_mask_ack_parent(). Cc: Marc Zyngier Cc: Thomas Gleixner Acked-by: Marc Zyngier Signed-off-by: Brian Masney Signed-off-by: Linus Walleij --- include/linux/irq.h | 1 + kernel/irq/chip.c | 11 +++++++++++ 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/include/linux/irq.h b/include/linux/irq.h index def2b2aac8b1..9a1a67d2e07d 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -605,6 +605,7 @@ extern void irq_chip_disable_parent(struct irq_data *data); extern void irq_chip_ack_parent(struct irq_data *data); extern int irq_chip_retrigger_hierarchy(struct irq_data *data); extern void irq_chip_mask_parent(struct irq_data *data); +extern void irq_chip_mask_ack_parent(struct irq_data *data); extern void irq_chip_unmask_parent(struct irq_data *data); extern void irq_chip_eoi_parent(struct irq_data *data); extern int irq_chip_set_affinity_parent(struct irq_data *data, diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c index 34e969069488..982b75e127c5 100644 --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c @@ -1277,6 +1277,17 @@ void irq_chip_mask_parent(struct irq_data *data) } EXPORT_SYMBOL_GPL(irq_chip_mask_parent); +/** + * irq_chip_mask_ack_parent - Mask and acknowledge the parent interrupt + * @data: Pointer to interrupt specific data + */ +void irq_chip_mask_ack_parent(struct irq_data *data) +{ + data = data->parent_data; + data->chip->irq_mask_ack(data); +} +EXPORT_SYMBOL_GPL(irq_chip_mask_ack_parent); + /** * irq_chip_unmask_parent - Unmask the parent interrupt * @data: Pointer to interrupt specific data -- cgit v1.2.3 From 7945f929f1a77a1c8887a97ca07f87626858ff42 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 20 Feb 2019 11:12:39 +0000 Subject: drivers: provide devm_platform_ioremap_resource() There are currently 1200+ instances of using platform_get_resource() and devm_ioremap_resource() together in the kernel tree. This patch wraps these two calls in a single helper. Thanks to that we don't have to declare a local variable for struct resource * and can omit the redundant argument for resource type. We also have one function call less. Signed-off-by: Bartosz Golaszewski Acked-by: Greg Kroah-Hartman Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij --- drivers/base/platform.c | 18 ++++++++++++++++++ include/linux/platform_device.h | 3 +++ 2 files changed, 21 insertions(+) (limited to 'include') diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 1c958eb33ef4..f82691e1c26c 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -79,6 +79,24 @@ struct resource *platform_get_resource(struct platform_device *dev, } EXPORT_SYMBOL_GPL(platform_get_resource); +/** + * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform + * device + * + * @pdev: platform device to use both for memory resource lookup as well as + * resource managemend + * @index: resource index + */ +void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, index); + return devm_ioremap_resource(&pdev->dev, res); +} +EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource); + /** * platform_get_irq - get an IRQ for a device * @dev: platform device diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index c7c081dc6034..b126b73ed8ef 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -52,6 +52,9 @@ extern struct device platform_bus; extern void arch_setup_pdev_archdata(struct platform_device *); extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int); +extern void __iomem * +devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index); extern int platform_get_irq(struct platform_device *, unsigned int); extern int platform_irq_count(struct platform_device *); extern struct resource *platform_get_resource_byname(struct platform_device *, -- cgit v1.2.3 From e09d168f13f0d63df7fe095d52be04c16cbe1cef Mon Sep 17 00:00:00 2001 From: "Enrico Weigelt, metux IT consult" Date: Fri, 22 Feb 2019 10:54:15 +0100 Subject: gpio: AMD G-Series PCH gpio driver GPIO platform driver for the AMD G-series PCH (eg. on GX-412TC) This driver doesn't registers itself automatically, as it needs to be provided with platform specific configuration, provided by some board driver setup code. Didn't implement oftree probing yet, as it's rarely found on x86. Cc: linux-gpio@vger.kernel.org Cc: linus.walleij@linaro.org Cc: bgolaszewski@baylibre.com Cc: dvhart@infradead.org Cc: platform-driver-x86@vger.kernel.org Reviewed-by: Andy Shevchenko Signed-off-by: Enrico Weigelt, metux IT consult Signed-off-by: Linus Walleij --- MAINTAINERS | 7 + drivers/gpio/Kconfig | 9 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-amd-fch.c | 185 ++++++++++++++++++++++++ include/linux/platform_data/gpio/gpio-amd-fch.h | 46 ++++++ 5 files changed, 248 insertions(+) create mode 100644 drivers/gpio/gpio-amd-fch.c create mode 100644 include/linux/platform_data/gpio/gpio-amd-fch.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 9919840d54cd..5e4135c78862 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -766,6 +766,13 @@ S: Supported F: Documentation/hwmon/fam15h_power F: drivers/hwmon/fam15h_power.c +AMD FCH GPIO DRIVER +M: Enrico Weigelt, metux IT consult +L: linux-gpio@vger.kernel.org +S: Maintained +F: drivers/gpio/gpio-amd-fch.c +F: include/linux/platform_data/gpio/gpio-amd-fch.h + AMD GEODE CS5536 USB DEVICE CONTROLLER DRIVER L: linux-geode@lists.infradead.org (moderated for non-subscribers) S: Orphan diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 486d9de2716a..3f50526a771f 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -655,6 +655,15 @@ config GPIO_LOONGSON1 help Say Y or M here to support GPIO on Loongson1 SoCs. +config GPIO_AMD_FCH + tristate "GPIO support for AMD Fusion Controller Hub (G-series SOCs)" + help + This option enables driver for GPIO on AMDs Fusion Controller Hub, + as found on G-series SOCs (eg. GX-412TC) + + Note: This driver doesn't registers itself automatically, as it + needs to be provided with platform specific configuration. + (See eg. CONFIG_PCENGINES_APU2.) endmenu menu "Port-mapped I/O GPIO drivers" diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9655927a3dcf..54d55274b93a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o obj-$(CONFIG_GPIO_ADP5588) += gpio-adp5588.o obj-$(CONFIG_GPIO_ALTERA) += gpio-altera.o obj-$(CONFIG_GPIO_ALTERA_A10SR) += gpio-altera-a10sr.o +obj-$(CONFIG_GPIO_AMD_FCH) += gpio-amd-fch.o obj-$(CONFIG_GPIO_AMD8111) += gpio-amd8111.o obj-$(CONFIG_GPIO_AMDPT) += gpio-amdpt.o obj-$(CONFIG_GPIO_ARIZONA) += gpio-arizona.o diff --git a/drivers/gpio/gpio-amd-fch.c b/drivers/gpio/gpio-amd-fch.c new file mode 100644 index 000000000000..3b4fdce325c1 --- /dev/null +++ b/drivers/gpio/gpio-amd-fch.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * GPIO driver for the AMD G series FCH (eg. GX-412TC) + * + * Copyright (C) 2018 metux IT consult + * Author: Enrico Weigelt, metux IT consult + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define AMD_FCH_MMIO_BASE 0xFED80000 +#define AMD_FCH_GPIO_BANK0_BASE 0x1500 +#define AMD_FCH_GPIO_SIZE 0x0300 + +#define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23) +#define AMD_FCH_GPIO_FLAG_WRITE BIT(22) +#define AMD_FCH_GPIO_FLAG_READ BIT(16) + +static const struct resource amd_fch_gpio_iores = + DEFINE_RES_MEM_NAMED( + AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE, + AMD_FCH_GPIO_SIZE, + "amd-fch-gpio-iomem"); + +struct amd_fch_gpio_priv { + struct platform_device *pdev; + struct gpio_chip gc; + void __iomem *base; + struct amd_fch_gpio_pdata *pdata; + spinlock_t lock; +}; + +static void *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv, + unsigned int gpio) +{ + return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32); +} + +static int amd_fch_gpio_direction_input(struct gpio_chip *gc, + unsigned int offset) +{ + unsigned long flags; + struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); + void *ptr = amd_fch_gpio_addr(priv, offset); + + spin_lock_irqsave(&priv->lock, flags); + writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int amd_fch_gpio_direction_output(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + unsigned long flags; + struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); + void *ptr = amd_fch_gpio_addr(priv, gpio); + + spin_lock_irqsave(&priv->lock, flags); + writel_relaxed(readl_relaxed(ptr) | AMD_FCH_GPIO_FLAG_DIRECTION, ptr); + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) +{ + int ret; + unsigned long flags; + struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); + void *ptr = amd_fch_gpio_addr(priv, gpio); + + spin_lock_irqsave(&priv->lock, flags); + ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static void amd_fch_gpio_set(struct gpio_chip *gc, + unsigned int gpio, int value) +{ + unsigned long flags; + struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); + void *ptr = amd_fch_gpio_addr(priv, gpio); + u32 mask; + + spin_lock_irqsave(&priv->lock, flags); + + mask = readl_relaxed(ptr); + if (value) + mask |= AMD_FCH_GPIO_FLAG_WRITE; + else + mask &= ~AMD_FCH_GPIO_FLAG_WRITE; + writel_relaxed(mask, ptr); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +static int amd_fch_gpio_get(struct gpio_chip *gc, + unsigned int offset) +{ + unsigned long flags; + int ret; + struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc); + void *ptr = amd_fch_gpio_addr(priv, offset); + + spin_lock_irqsave(&priv->lock, flags); + ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} + +static int amd_fch_gpio_request(struct gpio_chip *chip, + unsigned int gpio_pin) +{ + return 0; +} + +static int amd_fch_gpio_probe(struct platform_device *pdev) +{ + struct amd_fch_gpio_priv *priv; + struct amd_fch_gpio_pdata *pdata; + + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) { + dev_err(&pdev->dev, "no platform_data\n"); + return -ENOENT; + } + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pdata = pdata; + priv->pdev = pdev; + + priv->gc.owner = THIS_MODULE; + priv->gc.parent = &pdev->dev; + priv->gc.label = dev_name(&pdev->dev); + priv->gc.ngpio = priv->pdata->gpio_num; + priv->gc.names = priv->pdata->gpio_names; + priv->gc.base = -1; + priv->gc.request = amd_fch_gpio_request; + priv->gc.direction_input = amd_fch_gpio_direction_input; + priv->gc.direction_output = amd_fch_gpio_direction_output; + priv->gc.get_direction = amd_fch_gpio_get_direction; + priv->gc.get = amd_fch_gpio_get; + priv->gc.set = amd_fch_gpio_set; + + spin_lock_init(&priv->lock); + + priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + platform_set_drvdata(pdev, priv); + + return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv); +} + +static struct platform_driver amd_fch_gpio_driver = { + .driver = { + .name = AMD_FCH_GPIO_DRIVER_NAME, + }, + .probe = amd_fch_gpio_probe, +}; + +module_platform_driver(amd_fch_gpio_driver); + +MODULE_AUTHOR("Enrico Weigelt, metux IT consult "); +MODULE_DESCRIPTION("AMD G-series FCH GPIO driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME); diff --git a/include/linux/platform_data/gpio/gpio-amd-fch.h b/include/linux/platform_data/gpio/gpio-amd-fch.h new file mode 100644 index 000000000000..a867637e172d --- /dev/null +++ b/include/linux/platform_data/gpio/gpio-amd-fch.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL+ */ + +/* + * AMD FCH gpio driver platform-data + * + * Copyright (C) 2018 metux IT consult + * Author: Enrico Weigelt + * + */ + +#ifndef __LINUX_PLATFORM_DATA_GPIO_AMD_FCH_H +#define __LINUX_PLATFORM_DATA_GPIO_AMD_FCH_H + +#define AMD_FCH_GPIO_DRIVER_NAME "gpio_amd_fch" + +/* + * gpio register index definitions + */ +#define AMD_FCH_GPIO_REG_GPIO49 0x40 +#define AMD_FCH_GPIO_REG_GPIO50 0x41 +#define AMD_FCH_GPIO_REG_GPIO51 0x42 +#define AMD_FCH_GPIO_REG_GPIO59_DEVSLP0 0x43 +#define AMD_FCH_GPIO_REG_GPIO57 0x44 +#define AMD_FCH_GPIO_REG_GPIO58 0x45 +#define AMD_FCH_GPIO_REG_GPIO59_DEVSLP1 0x46 +#define AMD_FCH_GPIO_REG_GPIO64 0x47 +#define AMD_FCH_GPIO_REG_GPIO68 0x48 +#define AMD_FCH_GPIO_REG_GPIO66_SPKR 0x5B +#define AMD_FCH_GPIO_REG_GPIO71 0x4D +#define AMD_FCH_GPIO_REG_GPIO32_GE1 0x59 +#define AMD_FCH_GPIO_REG_GPIO33_GE2 0x5A +#define AMT_FCH_GPIO_REG_GEVT22 0x09 + +/* + * struct amd_fch_gpio_pdata - GPIO chip platform data + * @gpio_num: number of entries + * @gpio_reg: array of gpio registers + * @gpio_names: array of gpio names + */ +struct amd_fch_gpio_pdata { + int gpio_num; + int *gpio_reg; + const char * const *gpio_names; +}; + +#endif /* __LINUX_PLATFORM_DATA_GPIO_AMD_FCH_H */ -- cgit v1.2.3