From ad668599f263988eaac74354349d64e3c0990a77 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Sat, 27 Oct 2007 03:06:22 +0200 Subject: PCI: make pci_restore_bars() static This patch makes the needlessly global pci_restore_bars() static. Signed-off-by: Adrian Bunk Signed-off-by: Greg Kroah-Hartman --- include/linux/pci.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index ae1006322f80..169899b5c555 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -576,7 +576,6 @@ int pcie_set_readrq(struct pci_dev *dev, int rq); void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); int __must_check pci_assign_resource(struct pci_dev *dev, int i); int __must_check pci_assign_resource_fixed(struct pci_dev *dev, int i); -void pci_restore_bars(struct pci_dev *dev); int pci_select_bars(struct pci_dev *dev, unsigned long flags); /* ROM control related routines */ -- cgit v1.2.3 From b09549ef9b66b9547520572bedd7af3c1f0747d7 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Sat, 27 Oct 2007 03:06:25 +0200 Subject: PCI: drivers/pci/rom.c: #if 0 two functions This patch #if 0's the following unused global functions: - rom.c: pci_map_rom_copy() - rom.c: pci_remove_rom() Signed-off-by: Adrian Bunk Signed-off-by: Greg Kroah-Hartman --- drivers/pci/rom.c | 6 ++++-- include/linux/pci.h | 2 -- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c index dbbcc04abd1a..a98b2470b9ea 100644 --- a/drivers/pci/rom.c +++ b/drivers/pci/rom.c @@ -162,6 +162,7 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size) return rom; } +#if 0 /** * pci_map_rom_copy - map a PCI ROM to kernel space, create a copy * @pdev: pointer to pci device struct @@ -196,6 +197,7 @@ void __iomem *pci_map_rom_copy(struct pci_dev *pdev, size_t *size) return (void __iomem *)(unsigned long)res->start; } +#endif /* 0 */ /** * pci_unmap_rom - unmap the ROM from kernel space @@ -218,6 +220,7 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom) pci_disable_rom(pdev); } +#if 0 /** * pci_remove_rom - disable the ROM and remove its sysfs attribute * @pdev: pointer to pci device struct @@ -236,6 +239,7 @@ void pci_remove_rom(struct pci_dev *pdev) IORESOURCE_ROM_COPY))) pci_disable_rom(pdev); } +#endif /* 0 */ /** * pci_cleanup_rom - internal routine for freeing the ROM copy created @@ -256,6 +260,4 @@ void pci_cleanup_rom(struct pci_dev *pdev) } EXPORT_SYMBOL(pci_map_rom); -EXPORT_SYMBOL(pci_map_rom_copy); EXPORT_SYMBOL(pci_unmap_rom); -EXPORT_SYMBOL(pci_remove_rom); diff --git a/include/linux/pci.h b/include/linux/pci.h index 169899b5c555..d2cae79f3bea 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -580,9 +580,7 @@ int pci_select_bars(struct pci_dev *dev, unsigned long flags); /* ROM control related routines */ void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size); -void __iomem __must_check *pci_map_rom_copy(struct pci_dev *pdev, size_t *size); void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom); -void pci_remove_rom(struct pci_dev *pdev); size_t pci_get_rom_size(void __iomem *rom, size_t size); /* Power management related routines */ -- cgit v1.2.3 From 4348a2dc49f9baecd34a9b0904245488c6189398 Mon Sep 17 00:00:00 2001 From: Shaohua Li Date: Wed, 24 Oct 2007 10:45:08 +0800 Subject: pcie: utilize pcie transaction pending bit PCIE has a mechanism to wait for Non-Posted request to complete. I think pci_disable_device is a good place to do this. Signed-off-by: Shaohua Li Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci.c | 21 +++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 23 insertions(+) (limited to 'include') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 089184bc327d..d30e802d9a1a 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -314,6 +314,24 @@ int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) } EXPORT_SYMBOL_GPL(pci_find_ht_capability); +void pcie_wait_pending_transaction(struct pci_dev *dev) +{ + int pos; + u16 reg16; + + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (!pos) + return; + while (1) { + pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16); + if (!(reg16 & PCI_EXP_DEVSTA_TRPND)) + break; + cpu_relax(); + } + +} +EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction); + /** * pci_find_parent_resource - return resource region of parent bus of given region * @dev: PCI device structure contains resources to be searched @@ -884,6 +902,9 @@ pci_disable_device(struct pci_dev *dev) if (atomic_sub_return(1, &dev->enable_cnt) != 0) return; + /* Wait for all transactions are finished before disabling the device */ + pcie_wait_pending_transaction(dev); + pci_read_config_word(dev, PCI_COMMAND, &pci_command); if (pci_command & PCI_COMMAND_MASTER) { pci_command &= ~PCI_COMMAND_MASTER; diff --git a/include/linux/pci.h b/include/linux/pci.h index d2cae79f3bea..bdff18b7fbc6 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -498,6 +498,7 @@ int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); int pci_find_ext_capability (struct pci_dev *dev, int cap); int pci_find_ht_capability (struct pci_dev *dev, int ht_cap); int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap); +void pcie_wait_pending_transaction(struct pci_dev *dev); struct pci_bus *pci_find_next_bus(const struct pci_bus *from); struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, @@ -759,6 +760,7 @@ static inline void pci_unregister_driver(struct pci_driver *drv) { } static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; } static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; } static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; } +static inline void pcie_wait_pending_transaction(struct pci_dev *dev) {} /* Power management related routines */ static inline int pci_save_state(struct pci_dev *dev) { return 0; } -- cgit v1.2.3 From 10d7425d201e866ee0c57424860e06118dae2500 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Wed, 21 Nov 2007 15:07:07 -0800 Subject: PCI: get rid of pci_dev::{vendor,device}_compatible fields The vendor_compatible and device_compatible fields in struct pci_dev aren't used anywhere, and are somewhat pointless. Assuming that these are historical artifacts, remove them. Signed-off-by: Lennert Buytenhek Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- include/linux/pci.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index bdff18b7fbc6..c53d6cf723d1 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -66,7 +66,6 @@ enum pci_mmap_state { #define PCI_DMA_FROMDEVICE 2 #define PCI_DMA_NONE 3 -#define DEVICE_COUNT_COMPATIBLE 4 #define DEVICE_COUNT_RESOURCE 12 typedef int __bitwise pci_power_t; @@ -167,10 +166,6 @@ struct pci_dev { pci_channel_state_t error_state; /* current connectivity state */ struct device dev; /* Generic device interface */ - /* device is compatible with these IDs */ - unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE]; - unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE]; - int cfg_size; /* Size of configuration space */ /* -- cgit v1.2.3 From 94688cf2454986309fbcd495233ba2423786a14a Mon Sep 17 00:00:00 2001 From: Linas Vepstas Date: Wed, 7 Nov 2007 15:43:59 -0600 Subject: PCI: export pci_restore_msi_state() PCI error recovery usually involves the PCI adapter being reset. If the device is using MSI, the reset will cause the MSI state to be lost; the device driver needs to restore the MSI state. The pci_restore_msi_state() routine is currently protected by CONFIG_PM; remove this, and also export the symbol, so that it can be used in a modle. Signed-off-by: Linas Vepstas Signed-off-by: Greg Kroah-Hartman --- drivers/pci/msi.c | 3 +-- drivers/pci/pci.h | 6 ------ include/linux/pci.h | 2 ++ 3 files changed, 3 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 07c9f09c856d..30de51fcd68c 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -230,7 +230,6 @@ static void pci_intx_for_msi(struct pci_dev *dev, int enable) pci_intx(dev, enable); } -#ifdef CONFIG_PM static void __pci_restore_msi_state(struct pci_dev *dev) { int pos; @@ -288,7 +287,7 @@ void pci_restore_msi_state(struct pci_dev *dev) __pci_restore_msi_state(dev); __pci_restore_msix_state(dev); } -#endif /* CONFIG_PM */ +EXPORT_SYMBOL_GPL(pci_restore_msi_state); /** * msi_capability_init - configure device's MSI capability structure diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index fc87e14b50de..4c4613387786 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -45,12 +45,6 @@ static inline void pci_no_msi(void) { } static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } #endif -#if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM) -void pci_restore_msi_state(struct pci_dev *dev); -#else -static inline void pci_restore_msi_state(struct pci_dev *dev) {} -#endif - #ifdef CONFIG_PCIEAER void pci_no_aer(void); #else diff --git a/include/linux/pci.h b/include/linux/pci.h index c53d6cf723d1..87aab07e239a 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -668,6 +668,7 @@ static inline int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec) {return -1;} static inline void pci_disable_msix(struct pci_dev *dev) {} static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {} +static inline void pci_restore_msi_state(struct pci_dev *dev) {} #else extern int pci_enable_msi(struct pci_dev *dev); extern void pci_disable_msi(struct pci_dev *dev); @@ -675,6 +676,7 @@ extern int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec); extern void pci_disable_msix(struct pci_dev *dev); extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); +extern void pci_restore_msi_state(struct pci_dev *dev); #endif #ifdef CONFIG_HT_IRQ -- cgit v1.2.3 From c40a22e0ce5eb400f27449e59e43d021bee58b8d Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Mon, 10 Dec 2007 17:32:15 +1100 Subject: PCI: Fix bus resource assignment on 32 bits with 64b resources The current pci_assign_unassigned_resources() code doesn't work properly on 32 bits platforms with 64 bits resources. The main reason is the use of unsigned long in various places instead of resource_size_t. This is a pre-requisite for making powerpc use the generic code instead of its own half-useful implementation. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Greg Kroah-Hartman --- drivers/pci/setup-bus.c | 64 ++++++++++++++++++++++++++++++------------------- include/linux/pci.h | 4 ++-- 2 files changed, 42 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 401e03c920bd..8a7232feb553 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -89,8 +89,9 @@ void pci_setup_cardbus(struct pci_bus *bus) * The IO resource is allocated a range twice as large as it * would normally need. This allows us to set both IO regs. */ - printk(" IO window: %08lx-%08lx\n", - region.start, region.end); + printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", + (unsigned long)region.start, + (unsigned long)region.end); pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, region.start); pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, @@ -99,8 +100,9 @@ void pci_setup_cardbus(struct pci_bus *bus) pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); if (bus->resource[1]->flags & IORESOURCE_IO) { - printk(" IO window: %08lx-%08lx\n", - region.start, region.end); + printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n", + (unsigned long)region.start, + (unsigned long)region.end); pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, region.start); pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, @@ -109,8 +111,9 @@ void pci_setup_cardbus(struct pci_bus *bus) pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); if (bus->resource[2]->flags & IORESOURCE_MEM) { - printk(" PREFETCH window: %08lx-%08lx\n", - region.start, region.end); + printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n", + (unsigned long)region.start, + (unsigned long)region.end); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, region.start); pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, @@ -119,8 +122,9 @@ void pci_setup_cardbus(struct pci_bus *bus) pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); if (bus->resource[3]->flags & IORESOURCE_MEM) { - printk(" MEM window: %08lx-%08lx\n", - region.start, region.end); + printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", + (unsigned long)region.start, + (unsigned long)region.end); pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, region.start); pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, @@ -145,7 +149,7 @@ pci_setup_bridge(struct pci_bus *bus) { struct pci_dev *bridge = bus->self; struct pci_bus_region region; - u32 l, io_upper16; + u32 l, bu, lu, io_upper16; DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); @@ -159,7 +163,8 @@ pci_setup_bridge(struct pci_bus *bus) /* Set up upper 16 bits of I/O base/limit. */ io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); DBG(KERN_INFO " IO window: %04lx-%04lx\n", - region.start, region.end); + (unsigned long)region.start, + (unsigned long)region.end); } else { /* Clear upper 16 bits of I/O base/limit. */ @@ -180,8 +185,9 @@ pci_setup_bridge(struct pci_bus *bus) if (bus->resource[1]->flags & IORESOURCE_MEM) { l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; - DBG(KERN_INFO " MEM window: %08lx-%08lx\n", - region.start, region.end); + DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n", + (unsigned long)region.start, + (unsigned long)region.end); } else { l = 0x0000fff0; @@ -195,12 +201,18 @@ pci_setup_bridge(struct pci_bus *bus) pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); /* Set up PREF base/limit. */ + bu = lu = 0; pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; - DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n", - region.start, region.end); +#ifdef CONFIG_RESOURCES_64BIT + bu = region.start >> 32; + lu = region.end >> 32; +#endif + DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n", + (unsigned long long)region.start, + (unsigned long long)region.end); } else { l = 0x0000fff0; @@ -208,8 +220,9 @@ pci_setup_bridge(struct pci_bus *bus) } pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); - /* Clear out the upper 32 bits of PREF base. */ - pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0); + /* Set the upper 32 bits of PREF base & limit. */ + pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); + pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); } @@ -323,8 +336,8 @@ static void pbus_size_io(struct pci_bus *bus) static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) { struct pci_dev *dev; - unsigned long min_align, align, size; - unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */ + resource_size_t min_align, align, size; + resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ int order, max_order; struct resource *b_res = find_free_bus_resource(bus, type); @@ -340,7 +353,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long for (i = 0; i < PCI_NUM_RESOURCES; i++) { struct resource *r = &dev->resource[i]; - unsigned long r_size; + resource_size_t r_size; if (r->parent || (r->flags & mask) != type) continue; @@ -350,10 +363,10 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long order = __ffs(align) - 20; if (order > 11) { printk(KERN_WARNING "PCI: region %s/%d " - "too large: %llx-%llx\n", + "too large: 0x%016llx-0x%016llx\n", pci_name(dev), i, - (unsigned long long)r->start, - (unsigned long long)r->end); + (unsigned long long)r->start, + (unsigned long long)r->end); r->flags = 0; continue; } @@ -372,8 +385,11 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long align = 0; min_align = 0; for (order = 0; order <= max_order; order++) { - unsigned long align1 = 1UL << (order + 20); - +#ifdef CONFIG_RESOURCES_64BIT + resource_size_t align1 = 1ULL << (order + 20); +#else + resource_size_t align1 = 1U << (order + 20); +#endif if (!align) min_align = align1; else if (ALIGN(align + min_align, min_align) < align1) diff --git a/include/linux/pci.h b/include/linux/pci.h index 87aab07e239a..4b4d711a5da8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -309,8 +309,8 @@ struct pci_raw_ops { extern struct pci_raw_ops *raw_pci_ops; struct pci_bus_region { - unsigned long start; - unsigned long end; + resource_size_t start; + resource_size_t end; }; struct pci_dynids { -- cgit v1.2.3 From b718989da7cf1f77ed5665dba0d2c73bd9dfe2d7 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 20 Dec 2007 15:28:08 +1100 Subject: PCI: Add pci_enable_device_{io,mem} intefaces The pci_enable_device_bars() interface isn't well suited to PCI because you can't actually enable/disable BARs individually on a device. So for example, if a device has 2 memory BARs 0 and 1, and one of them (let's say 1) has not been successfully allocated by the firmware or the kernel, then enabling memory decoding shouldn't be permitted for the entire device since it will decode whatever random address is still in that BAR 1. So a device must be either fully enabled for IO, for Memory, or for both. Not on a per-BAR basis. This provides two new functions, pci_enable_device_io() and pci_enable_device_mem() to replace pci_enable_device_bars(). The implementation internally builds a BAR mask in order to be able to use existing arch infrastructure. Signed-off-by: Benjamin Herrenschmidt Acked-by: Ivan Kokshaysky Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++- include/linux/pci.h | 2 ++ 2 files changed, 50 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7248e9fb12bd..5027e4d08b48 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -764,6 +764,51 @@ pci_enable_device_bars(struct pci_dev *dev, int bars) return err; } +static int __pci_enable_device_flags(struct pci_dev *dev, + resource_size_t flags) +{ + int err; + int i, bars = 0; + + if (atomic_add_return(1, &dev->enable_cnt) > 1) + return 0; /* already enabled */ + + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) + if (dev->resource[i].flags & flags) + bars |= (1 << i); + + err = do_pci_enable_device(dev, bars); + if (err < 0) + atomic_dec(&dev->enable_cnt); + return err; +} + +/** + * pci_enable_device_io - Initialize a device for use with IO space + * @dev: PCI device to be initialized + * + * Initialize device before it's used by a driver. Ask low-level code + * to enable I/O resources. Wake up the device if it was suspended. + * Beware, this function can fail. + */ +int pci_enable_device_io(struct pci_dev *dev) +{ + return __pci_enable_device_flags(dev, IORESOURCE_IO); +} + +/** + * pci_enable_device_mem - Initialize a device for use with Memory space + * @dev: PCI device to be initialized + * + * Initialize device before it's used by a driver. Ask low-level code + * to enable Memory resources. Wake up the device if it was suspended. + * Beware, this function can fail. + */ +int pci_enable_device_mem(struct pci_dev *dev) +{ + return __pci_enable_device_flags(dev, IORESOURCE_MEM); +} + /** * pci_enable_device - Initialize device before it's used by a driver. * @dev: PCI device to be initialized @@ -777,7 +822,7 @@ pci_enable_device_bars(struct pci_dev *dev, int bars) */ int pci_enable_device(struct pci_dev *dev) { - return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); + return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); } /* @@ -1651,6 +1696,8 @@ device_initcall(pci_init); EXPORT_SYMBOL(pci_reenable_device); EXPORT_SYMBOL(pci_enable_device_bars); +EXPORT_SYMBOL(pci_enable_device_io); +EXPORT_SYMBOL(pci_enable_device_mem); EXPORT_SYMBOL(pci_enable_device); EXPORT_SYMBOL(pcim_enable_device); EXPORT_SYMBOL(pcim_pin_device); diff --git a/include/linux/pci.h b/include/linux/pci.h index 4b4d711a5da8..e4c1dacb6636 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -544,6 +544,8 @@ static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val int __must_check pci_enable_device(struct pci_dev *dev); int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask); +int __must_check pci_enable_device_io(struct pci_dev *dev); +int __must_check pci_enable_device_mem(struct pci_dev *dev); int __must_check pci_reenable_device(struct pci_dev *); int __must_check pcim_enable_device(struct pci_dev *pdev); void pcim_pin_device(struct pci_dev *pdev); -- cgit v1.2.3 From 7cbe5b6005f80de33a205d3052cdc89aacaac07c Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 20 Dec 2007 15:28:10 +1100 Subject: PCI: Remove pci_enable_device_bars() Now that all in-tree users are gone, this removes pci_enable_device_bars() completely. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci.c | 24 ------------------------ include/linux/pci.h | 1 - 2 files changed, 25 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 5027e4d08b48..35f78f1628fc 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -741,29 +741,6 @@ int pci_reenable_device(struct pci_dev *dev) return 0; } -/** - * pci_enable_device_bars - Initialize some of a device for use - * @dev: PCI device to be initialized - * @bars: bitmask of BAR's that must be configured - * - * Initialize device before it's used by a driver. Ask low-level code - * to enable selected I/O and memory resources. Wake up the device if it - * was suspended. Beware, this function can fail. - */ -int -pci_enable_device_bars(struct pci_dev *dev, int bars) -{ - int err; - - if (atomic_add_return(1, &dev->enable_cnt) > 1) - return 0; /* already enabled */ - - err = do_pci_enable_device(dev, bars); - if (err < 0) - atomic_dec(&dev->enable_cnt); - return err; -} - static int __pci_enable_device_flags(struct pci_dev *dev, resource_size_t flags) { @@ -1695,7 +1672,6 @@ early_param("pci", pci_setup); device_initcall(pci_init); EXPORT_SYMBOL(pci_reenable_device); -EXPORT_SYMBOL(pci_enable_device_bars); EXPORT_SYMBOL(pci_enable_device_io); EXPORT_SYMBOL(pci_enable_device_mem); EXPORT_SYMBOL(pci_enable_device); diff --git a/include/linux/pci.h b/include/linux/pci.h index e4c1dacb6636..13813b0592fc 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -543,7 +543,6 @@ static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val } int __must_check pci_enable_device(struct pci_dev *dev); -int __must_check pci_enable_device_bars(struct pci_dev *dev, int mask); int __must_check pci_enable_device_io(struct pci_dev *dev); int __must_check pci_enable_device_mem(struct pci_dev *dev); int __must_check pci_reenable_device(struct pci_dev *); -- cgit v1.2.3 From c2778357234f84668eab5558b54ad28478439d0b Mon Sep 17 00:00:00 2001 From: Andrew Patterson Date: Tue, 22 Jan 2008 17:18:12 -0700 Subject: PCI ACPI: Added a function to register _OSC with only PCIe devices. The function pci_osc_support_set() traverses every root bridge when checking for _OSC support for a capability. It quits as soon as it finds a device/bridge that doesn't support the requested capability. This won't work for systems that have mixed PCI and PCIe bridges when checking for PCIe features. I split this function into two -- pci_osc_support_set() and pcie_osc_support_set(). The latter is used when only PCIe devices should be traversed. Signed-off-by: Andrew Patterson Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci-acpi.c | 6 +++--- include/linux/pci-acpi.h | 11 ++++++++++- 2 files changed, 13 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 02e4876b3b2c..e569645d59e2 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -156,13 +156,13 @@ run_osc_out: } /** - * pci_osc_support_set - register OS support to Firmware + * __pci_osc_support_set - register OS support to Firmware * @flags: OS support bits * * Update OS support fields and doing a _OSC Query to obtain an update * from Firmware on supported control bits. **/ -acpi_status pci_osc_support_set(u32 flags) +acpi_status __pci_osc_support_set(u32 flags, const char *hid) { u32 temp; acpi_status retval; @@ -176,7 +176,7 @@ acpi_status pci_osc_support_set(u32 flags) temp = ctrlset_buf[OSC_CONTROL_TYPE]; ctrlset_buf[OSC_QUERY_TYPE] = OSC_QUERY_ENABLE; ctrlset_buf[OSC_CONTROL_TYPE] = OSC_CONTROL_MASKS; - acpi_get_devices ( PCI_ROOT_HID_STRING, + acpi_get_devices(hid, acpi_query_osc, ctrlset_buf, (void **) &retval ); diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h index 936ef82ed76a..3ba25065fa96 100644 --- a/include/linux/pci-acpi.h +++ b/include/linux/pci-acpi.h @@ -48,7 +48,15 @@ #ifdef CONFIG_ACPI extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags); -extern acpi_status pci_osc_support_set(u32 flags); +extern acpi_status __pci_osc_support_set(u32 flags, const char *hid); +static inline acpi_status pci_osc_support_set(u32 flags) +{ + return __pci_osc_support_set(flags, PCI_ROOT_HID_STRING); +} +static inline acpi_status pcie_osc_support_set(u32 flags) +{ + return __pci_osc_support_set(flags, PCI_EXPRESS_ROOT_HID_STRING); +} #else #if !defined(AE_ERROR) typedef u32 acpi_status; @@ -57,6 +65,7 @@ typedef u32 acpi_status; static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags) {return AE_ERROR;} static inline acpi_status pci_osc_support_set(u32 flags) {return AE_ERROR;} +static inline acpi_status pcie_osc_support_set(u32 flags) {return AE_ERROR;} #endif #endif /* _PCI_ACPI_H_ */ -- cgit v1.2.3 From 6c723d5bd89f03fc3ef627d50f89ade054d2ee3b Mon Sep 17 00:00:00 2001 From: Shaohua Li Date: Thu, 24 Jan 2008 10:21:57 +0800 Subject: PCI: PCIE ASPM support PCI Express ASPM defines a protocol for PCI Express components in the D0 state to reduce Link power by placing their Links into a low power state and instructing the other end of the Link to do likewise. This capability allows hardware-autonomous, dynamic Link power reduction beyond what is achievable by software-only controlled power management. However, The device should be configured by software appropriately. Enabling ASPM will save power, but will introduce device latency. This patch adds ASPM support in Linux. It introduces a global policy for ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control it. The interface can be used as a boot option too. Currently we have below setting: -default, BIOS default setting -powersave, highest power saving mode, enable all available ASPM state and clock power management -performance, highest performance, disable ASPM and clock power management By default, the 'default' policy is used currently. In my test, power difference between powersave mode and performance mode is about 1.3w in a system with 3 PCIE links. Signed-off-by: Shaohua Li Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci-sysfs.c | 5 + drivers/pci/pci.c | 4 + drivers/pci/pcie/Kconfig | 20 ++ drivers/pci/pcie/Makefile | 3 + drivers/pci/pcie/aspm.c | 802 ++++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/probe.c | 5 + drivers/pci/remove.c | 4 + include/linux/aspm.h | 44 +++ include/linux/pci.h | 5 + include/linux/pci_regs.h | 8 + 10 files changed, 900 insertions(+) create mode 100644 drivers/pci/pcie/aspm.c create mode 100644 include/linux/aspm.h (limited to 'include') diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 7d1877341aad..d05c1b252386 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -21,6 +21,7 @@ #include #include #include +#include #include "pci.h" static int sysfs_initialized; /* = 0 */ @@ -650,6 +651,8 @@ int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev) if (pcibios_add_platform_entries(pdev)) goto err_rom_file; + pcie_aspm_create_sysfs_dev_files(pdev); + return 0; err_rom_file: @@ -679,6 +682,8 @@ void pci_remove_sysfs_dev_files(struct pci_dev *pdev) if (!sysfs_initialized) return; + pcie_aspm_remove_sysfs_dev_files(pdev); + if (pdev->cfg_size < 4096) sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr); else diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 35f78f1628fc..1f1693161956 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -18,6 +18,7 @@ #include #include #include +#include #include /* isa_dma_bridge_buggy */ #include "pci.h" @@ -519,6 +520,9 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state) if (need_restore) pci_restore_bars(dev); + if (dev->bus->self) + pcie_aspm_pm_state_change(dev->bus->self); + return 0; } diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 287a9311716c..60104cf98796 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -26,3 +26,23 @@ config HOTPLUG_PCI_PCIE When in doubt, say N. source "drivers/pci/pcie/aer/Kconfig" + +# +# PCI Express ASPM +# +config PCIEASPM + bool "PCI Express ASPM support(Experimental)" + depends on PCI && EXPERIMENTAL + default y + help + This enables PCI Express ASPM (Active State Power Management) and + Clock Power Management. ASPM supports state L0/L0s/L1. + + When in doubt, say N. +config PCIEASPM_DEBUG + bool "Debug PCI Express ASPM" + depends on PCIEASPM + default n + help + This enables PCI Express ASPM debug support. It will add per-device + interface to control ASPM. diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index e00fb99acf44..11f6bb1eae24 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -2,6 +2,9 @@ # Makefile for PCI-Express PORT Driver # +# Build PCI Express ASPM if needed +obj-$(CONFIG_PCIEASPM) += aspm.o + pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c new file mode 100644 index 000000000000..1a5adeb10c95 --- /dev/null +++ b/drivers/pci/pcie/aspm.c @@ -0,0 +1,802 @@ +/* + * File: drivers/pci/pcie/aspm.c + * Enabling PCIE link L0s/L1 state and Clock Power Management + * + * Copyright (C) 2007 Intel + * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com) + * Copyright (C) Shaohua Li (shaohua.li@intel.com) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../pci.h" + +#ifdef MODULE_PARAM_PREFIX +#undef MODULE_PARAM_PREFIX +#endif +#define MODULE_PARAM_PREFIX "pcie_aspm." + +struct endpoint_state { + unsigned int l0s_acceptable_latency; + unsigned int l1_acceptable_latency; +}; + +struct pcie_link_state { + struct list_head sibiling; + struct pci_dev *pdev; + + /* ASPM state */ + unsigned int support_state; + unsigned int enabled_state; + unsigned int bios_aspm_state; + /* upstream component */ + unsigned int l0s_upper_latency; + unsigned int l1_upper_latency; + /* downstream component */ + unsigned int l0s_down_latency; + unsigned int l1_down_latency; + /* Clock PM state*/ + unsigned int clk_pm_capable; + unsigned int clk_pm_enabled; + unsigned int bios_clk_state; + + /* + * A pcie downstream port only has one slot under it, so at most there + * are 8 functions + */ + struct endpoint_state endpoints[8]; +}; + +static int aspm_disabled; +static DEFINE_MUTEX(aspm_lock); +static LIST_HEAD(link_list); + +#define POLICY_DEFAULT 0 /* BIOS default setting */ +#define POLICY_PERFORMANCE 1 /* high performance */ +#define POLICY_POWERSAVE 2 /* high power saving */ +static int aspm_policy; +static const char *policy_str[] = { + [POLICY_DEFAULT] = "default", + [POLICY_PERFORMANCE] = "performance", + [POLICY_POWERSAVE] = "powersave" +}; + +static int policy_to_aspm_state(struct pci_dev *pdev) +{ + struct pcie_link_state *link_state = pdev->link_state; + + switch (aspm_policy) { + case POLICY_PERFORMANCE: + /* Disable ASPM and Clock PM */ + return 0; + case POLICY_POWERSAVE: + /* Enable ASPM L0s/L1 */ + return PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1; + case POLICY_DEFAULT: + return link_state->bios_aspm_state; + } + return 0; +} + +static int policy_to_clkpm_state(struct pci_dev *pdev) +{ + struct pcie_link_state *link_state = pdev->link_state; + + switch (aspm_policy) { + case POLICY_PERFORMANCE: + /* Disable ASPM and Clock PM */ + return 0; + case POLICY_POWERSAVE: + /* Disable Clock PM */ + return 1; + case POLICY_DEFAULT: + return link_state->bios_clk_state; + } + return 0; +} + +static void pcie_set_clock_pm(struct pci_dev *pdev, int enable) +{ + struct pci_dev *child_dev; + int pos; + u16 reg16; + struct pcie_link_state *link_state = pdev->link_state; + + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { + pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); + if (!pos) + return; + pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16); + if (enable) + reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN; + else + reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN; + pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16); + } + link_state->clk_pm_enabled = !!enable; +} + +static void pcie_check_clock_pm(struct pci_dev *pdev) +{ + int pos; + u32 reg32; + u16 reg16; + int capable = 1, enabled = 1; + struct pci_dev *child_dev; + struct pcie_link_state *link_state = pdev->link_state; + + /* All functions should have the same cap and state, take the worst */ + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { + pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); + if (!pos) + return; + pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, ®32); + if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { + capable = 0; + enabled = 0; + break; + } + pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, ®16); + if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN)) + enabled = 0; + } + link_state->clk_pm_capable = capable; + link_state->clk_pm_enabled = enabled; + link_state->bios_clk_state = enabled; + pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev)); +} + +/* + * pcie_aspm_configure_common_clock: check if the 2 ends of a link + * could use common clock. If they are, configure them to use the + * common clock. That will reduce the ASPM state exit latency. + */ +static void pcie_aspm_configure_common_clock(struct pci_dev *pdev) +{ + int pos, child_pos; + u16 reg16 = 0; + struct pci_dev *child_dev; + int same_clock = 1; + + /* + * all functions of a slot should have the same Slot Clock + * Configuration, so just check one function + * */ + child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev, + bus_list); + BUG_ON(!child_dev->is_pcie); + + /* Check downstream component if bit Slot Clock Configuration is 1 */ + child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); + pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, ®16); + if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + same_clock = 0; + + /* Check upstream component if bit Slot Clock Configuration is 1 */ + pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); + pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16); + if (!(reg16 & PCI_EXP_LNKSTA_SLC)) + same_clock = 0; + + /* Configure downstream component, all functions */ + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { + child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); + pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL, + ®16); + if (same_clock) + reg16 |= PCI_EXP_LNKCTL_CCC; + else + reg16 &= ~PCI_EXP_LNKCTL_CCC; + pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL, + reg16); + } + + /* Configure upstream component */ + pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); + if (same_clock) + reg16 |= PCI_EXP_LNKCTL_CCC; + else + reg16 &= ~PCI_EXP_LNKCTL_CCC; + pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); + + /* retrain link */ + reg16 |= PCI_EXP_LNKCTL_RL; + pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); + + /* Wait for link training end */ + while (1) { + pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, ®16); + if (!(reg16 & PCI_EXP_LNKSTA_LT)) + break; + cpu_relax(); + } +} + +/* + * calc_L0S_latency: Convert L0s latency encoding to ns + */ +static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac) +{ + unsigned int ns = 64; + + if (latency_encoding == 0x7) { + if (ac) + ns = -1U; + else + ns = 5*1000; /* > 4us */ + } else + ns *= (1 << latency_encoding); + return ns; +} + +/* + * calc_L1_latency: Convert L1 latency encoding to ns + */ +static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac) +{ + unsigned int ns = 1000; + + if (latency_encoding == 0x7) { + if (ac) + ns = -1U; + else + ns = 65*1000; /* > 64us */ + } else + ns *= (1 << latency_encoding); + return ns; +} + +static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state, + unsigned int *l0s, unsigned int *l1, unsigned int *enabled) +{ + int pos; + u16 reg16; + u32 reg32; + unsigned int latency; + + pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); + pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, ®32); + *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; + if (*state != PCIE_LINK_STATE_L0S && + *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S)) + * state = 0; + if (*state == 0) + return; + + latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; + *l0s = calc_L0S_latency(latency, 0); + if (*state & PCIE_LINK_STATE_L1) { + latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; + *l1 = calc_L1_latency(latency, 0); + } + pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); + *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1); +} + +static void pcie_aspm_cap_init(struct pci_dev *pdev) +{ + struct pci_dev *child_dev; + u32 state, tmp; + struct pcie_link_state *link_state = pdev->link_state; + + /* upstream component states */ + pcie_aspm_get_cap_device(pdev, &link_state->support_state, + &link_state->l0s_upper_latency, + &link_state->l1_upper_latency, + &link_state->enabled_state); + /* downstream component states, all functions have the same setting */ + child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev, + bus_list); + pcie_aspm_get_cap_device(child_dev, &state, + &link_state->l0s_down_latency, + &link_state->l1_down_latency, + &tmp); + link_state->support_state &= state; + if (!link_state->support_state) + return; + link_state->enabled_state &= link_state->support_state; + link_state->bios_aspm_state = link_state->enabled_state; + + /* ENDPOINT states*/ + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { + int pos; + u32 reg32; + unsigned int latency; + struct endpoint_state *ep_state = + &link_state->endpoints[PCI_FUNC(child_dev->devfn)]; + + if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT && + child_dev->pcie_type != PCI_EXP_TYPE_LEG_END) + continue; + + pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP); + pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, ®32); + latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6; + latency = calc_L0S_latency(latency, 1); + ep_state->l0s_acceptable_latency = latency; + if (link_state->support_state & PCIE_LINK_STATE_L1) { + latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9; + latency = calc_L1_latency(latency, 1); + ep_state->l1_acceptable_latency = latency; + } + } +} + +static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev, + unsigned int state) +{ + struct pci_dev *parent_dev, *tmp_dev; + unsigned int latency, l1_latency = 0; + struct pcie_link_state *link_state; + struct endpoint_state *ep_state; + + parent_dev = pdev->bus->self; + link_state = parent_dev->link_state; + state &= link_state->support_state; + if (state == 0) + return 0; + ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)]; + + /* + * Check latency for endpoint device. + * TBD: The latency from the endpoint to root complex vary per + * switch's upstream link state above the device. Here we just do a + * simple check which assumes all links above the device can be in L1 + * state, that is we just consider the worst case. If switch's upstream + * link can't be put into L0S/L1, then our check is too strictly. + */ + tmp_dev = pdev; + while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { + parent_dev = tmp_dev->bus->self; + link_state = parent_dev->link_state; + if (state & PCIE_LINK_STATE_L0S) { + latency = max_t(unsigned int, + link_state->l0s_upper_latency, + link_state->l0s_down_latency); + if (latency > ep_state->l0s_acceptable_latency) + state &= ~PCIE_LINK_STATE_L0S; + } + if (state & PCIE_LINK_STATE_L1) { + latency = max_t(unsigned int, + link_state->l1_upper_latency, + link_state->l1_down_latency); + if (latency + l1_latency > + ep_state->l1_acceptable_latency) + state &= ~PCIE_LINK_STATE_L1; + } + if (!parent_dev->bus->self) /* parent_dev is a root port */ + break; + else { + /* + * parent_dev is the downstream port of a switch, make + * tmp_dev the upstream port of the switch + */ + tmp_dev = parent_dev->bus->self; + /* + * every switch on the path to root complex need 1 more + * microsecond for L1. Spec doesn't mention L0S. + */ + if (state & PCIE_LINK_STATE_L1) + l1_latency += 1000; + } + } + return state; +} + +static unsigned int pcie_aspm_check_state(struct pci_dev *pdev, + unsigned int state) +{ + struct pci_dev *child_dev; + + /* If no child, disable the link */ + if (list_empty(&pdev->subordinate->devices)) + return 0; + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { + if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { + /* + * If downstream component of a link is pci bridge, we + * disable ASPM for now for the link + * */ + state = 0; + break; + } + if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT && + child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)) + continue; + /* Device not in D0 doesn't need check latency */ + if (child_dev->current_state == PCI_D1 || + child_dev->current_state == PCI_D2 || + child_dev->current_state == PCI_D3hot || + child_dev->current_state == PCI_D3cold) + continue; + state = __pcie_aspm_check_state_one(child_dev, state); + } + return state; +} + +static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state) +{ + u16 reg16; + int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); + + pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, ®16); + reg16 &= ~0x3; + reg16 |= state; + pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16); +} + +static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state) +{ + struct pci_dev *child_dev; + int valid = 1; + struct pcie_link_state *link_state = pdev->link_state; + + /* + * if the downstream component has pci bridge function, don't do ASPM + * now + */ + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) { + if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) { + valid = 0; + break; + } + } + if (!valid) + return; + + /* + * spec 2.0 suggests all functions should be configured the same + * setting for ASPM. Enabling ASPM L1 should be done in upstream + * component first and then downstream, and vice versa for disabling + * ASPM L1. Spec doesn't mention L0S. + */ + if (state & PCIE_LINK_STATE_L1) + __pcie_aspm_config_one_dev(pdev, state); + + list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) + __pcie_aspm_config_one_dev(child_dev, state); + + if (!(state & PCIE_LINK_STATE_L1)) + __pcie_aspm_config_one_dev(pdev, state); + + link_state->enabled_state = state; +} + +static void __pcie_aspm_configure_link_state(struct pci_dev *pdev, + unsigned int state) +{ + struct pcie_link_state *link_state = pdev->link_state; + + if (link_state->support_state == 0) + return; + state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1; + + /* state 0 means disabling aspm */ + state = pcie_aspm_check_state(pdev, state); + if (link_state->enabled_state == state) + return; + __pcie_aspm_config_link(pdev, state); +} + +/* + * pcie_aspm_configure_link_state: enable/disable PCI express link state + * @pdev: the root port or switch downstream port + */ +static void pcie_aspm_configure_link_state(struct pci_dev *pdev, + unsigned int state) +{ + down_read(&pci_bus_sem); + mutex_lock(&aspm_lock); + __pcie_aspm_configure_link_state(pdev, state); + mutex_unlock(&aspm_lock); + up_read(&pci_bus_sem); +} + +static void free_link_state(struct pci_dev *pdev) +{ + kfree(pdev->link_state); + pdev->link_state = NULL; +} + +/* + * pcie_aspm_init_link_state: Initiate PCI express link state. + * It is called after the pcie and its children devices are scaned. + * @pdev: the root port or switch downstream port + */ +void pcie_aspm_init_link_state(struct pci_dev *pdev) +{ + unsigned int state; + struct pcie_link_state *link_state; + int error = 0; + + if (aspm_disabled || !pdev->is_pcie || pdev->link_state) + return; + if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && + pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) + return; + down_read(&pci_bus_sem); + if (list_empty(&pdev->subordinate->devices)) + goto out; + + mutex_lock(&aspm_lock); + + link_state = kzalloc(sizeof(*link_state), GFP_KERNEL); + if (!link_state) + goto unlock_out; + pdev->link_state = link_state; + + pcie_aspm_configure_common_clock(pdev); + + pcie_aspm_cap_init(pdev); + + /* config link state to avoid BIOS error */ + state = pcie_aspm_check_state(pdev, policy_to_aspm_state(pdev)); + __pcie_aspm_config_link(pdev, state); + + pcie_check_clock_pm(pdev); + + link_state->pdev = pdev; + list_add(&link_state->sibiling, &link_list); + +unlock_out: + if (error) + free_link_state(pdev); + mutex_unlock(&aspm_lock); +out: + up_read(&pci_bus_sem); +} + +/* @pdev: the endpoint device */ +void pcie_aspm_exit_link_state(struct pci_dev *pdev) +{ + struct pci_dev *parent = pdev->bus->self; + struct pcie_link_state *link_state = parent->link_state; + + if (aspm_disabled || !pdev->is_pcie || !parent || !link_state) + return; + if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT && + parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) + return; + down_read(&pci_bus_sem); + mutex_lock(&aspm_lock); + + /* + * All PCIe functions are in one slot, remove one function will remove + * the the whole slot, so just wait + */ + if (!list_empty(&parent->subordinate->devices)) + goto out; + + /* All functions are removed, so just disable ASPM for the link */ + __pcie_aspm_config_one_dev(parent, 0); + list_del(&link_state->sibiling); + /* Clock PM is for endpoint device */ + + free_link_state(parent); +out: + mutex_unlock(&aspm_lock); + up_read(&pci_bus_sem); +} + +/* @pdev: the root port or switch downstream port */ +void pcie_aspm_pm_state_change(struct pci_dev *pdev) +{ + struct pcie_link_state *link_state = pdev->link_state; + + if (aspm_disabled || !pdev->is_pcie || !pdev->link_state) + return; + if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && + pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM) + return; + /* + * devices changed PM state, we should recheck if latency meets all + * functions' requirement + */ + pcie_aspm_configure_link_state(pdev, link_state->enabled_state); +} + +/* + * pci_disable_link_state - disable pci device's link state, so the link will + * never enter specific states + */ +void pci_disable_link_state(struct pci_dev *pdev, int state) +{ + struct pci_dev *parent = pdev->bus->self; + struct pcie_link_state *link_state; + + if (aspm_disabled || !pdev->is_pcie) + return; + if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT || + pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM) + parent = pdev; + if (!parent) + return; + + down_read(&pci_bus_sem); + mutex_lock(&aspm_lock); + link_state = parent->link_state; + link_state->support_state &= + ~(state & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1)); + if (state & PCIE_LINK_STATE_CLKPM) + link_state->clk_pm_capable = 0; + + __pcie_aspm_configure_link_state(parent, link_state->enabled_state); + if (!link_state->clk_pm_capable && link_state->clk_pm_enabled) + pcie_set_clock_pm(parent, 0); + mutex_unlock(&aspm_lock); + up_read(&pci_bus_sem); +} +EXPORT_SYMBOL(pci_disable_link_state); + +static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp) +{ + int i; + struct pci_dev *pdev; + struct pcie_link_state *link_state; + + for (i = 0; i < ARRAY_SIZE(policy_str); i++) + if (!strncmp(val, policy_str[i], strlen(policy_str[i]))) + break; + if (i >= ARRAY_SIZE(policy_str)) + return -EINVAL; + if (i == aspm_policy) + return 0; + + down_read(&pci_bus_sem); + mutex_lock(&aspm_lock); + aspm_policy = i; + list_for_each_entry(link_state, &link_list, sibiling) { + pdev = link_state->pdev; + __pcie_aspm_configure_link_state(pdev, + policy_to_aspm_state(pdev)); + if (link_state->clk_pm_capable && + link_state->clk_pm_enabled != policy_to_clkpm_state(pdev)) + pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev)); + + } + mutex_unlock(&aspm_lock); + up_read(&pci_bus_sem); + return 0; +} + +static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp) +{ + int i, cnt = 0; + for (i = 0; i < ARRAY_SIZE(policy_str); i++) + if (i == aspm_policy) + cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]); + else + cnt += sprintf(buffer + cnt, "%s ", policy_str[i]); + return cnt; +} + +module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy, + NULL, 0644); + +#ifdef CONFIG_PCIEASPM_DEBUG +static ssize_t link_state_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pci_device = to_pci_dev(dev); + struct pcie_link_state *link_state = pci_device->link_state; + + return sprintf(buf, "%d\n", link_state->enabled_state); +} + +static ssize_t link_state_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t n) +{ + struct pci_dev *pci_device = to_pci_dev(dev); + int state; + + if (n < 1) + return -EINVAL; + state = buf[0]-'0'; + if (state >= 0 && state <= 3) { + /* setup link aspm state */ + pcie_aspm_configure_link_state(pci_device, state); + return n; + } + + return -EINVAL; +} + +static ssize_t clk_ctl_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pci_device = to_pci_dev(dev); + struct pcie_link_state *link_state = pci_device->link_state; + + return sprintf(buf, "%d\n", link_state->clk_pm_enabled); +} + +static ssize_t clk_ctl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t n) +{ + struct pci_dev *pci_device = to_pci_dev(dev); + int state; + + if (n < 1) + return -EINVAL; + state = buf[0]-'0'; + + down_read(&pci_bus_sem); + mutex_lock(&aspm_lock); + pcie_set_clock_pm(pci_device, !!state); + mutex_unlock(&aspm_lock); + up_read(&pci_bus_sem); + + return n; +} + +static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store); +static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store); + +static char power_group[] = "power"; +void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) +{ + struct pcie_link_state *link_state = pdev->link_state; + + if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && + pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) + return; + + if (link_state->support_state) + sysfs_add_file_to_group(&pdev->dev.kobj, + &dev_attr_link_state.attr, power_group); + if (link_state->clk_pm_capable) + sysfs_add_file_to_group(&pdev->dev.kobj, + &dev_attr_clk_ctl.attr, power_group); +} + +void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) +{ + struct pcie_link_state *link_state = pdev->link_state; + + if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT && + pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)) + return; + + if (link_state->support_state) + sysfs_remove_file_from_group(&pdev->dev.kobj, + &dev_attr_link_state.attr, power_group); + if (link_state->clk_pm_capable) + sysfs_remove_file_from_group(&pdev->dev.kobj, + &dev_attr_clk_ctl.attr, power_group); +} +#endif + +static int __init pcie_aspm_disable(char *str) +{ + aspm_disabled = 1; + return 1; +} + +__setup("pcie_noaspm", pcie_aspm_disable); + +static int __init pcie_aspm_init(void) +{ + if (aspm_disabled) + return 0; + pci_osc_support_set(OSC_ACTIVE_STATE_PWR_SUPPORT| + OSC_CLOCK_PWR_CAPABILITY_SUPPORT); + return 0; +} + +fs_initcall(pcie_aspm_init); diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 4262dfec5676..9b4673df27e7 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -9,6 +9,7 @@ #include #include #include +#include #include "pci.h" #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ @@ -1010,6 +1011,10 @@ int pci_scan_slot(struct pci_bus *bus, int devfn) break; } } + + if (bus->self) + pcie_aspm_init_link_state(bus->self); + return nr; } diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index 430281b2e921..05c9ad2a7f8b 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -1,5 +1,6 @@ #include #include +#include #include "pci.h" static void pci_free_resources(struct pci_dev *dev) @@ -30,6 +31,9 @@ static void pci_stop_dev(struct pci_dev *dev) dev->global_list.next = dev->global_list.prev = NULL; up_write(&pci_bus_sem); } + + if (dev->bus->self) + pcie_aspm_exit_link_state(dev); } static void pci_destroy_dev(struct pci_dev *dev) diff --git a/include/linux/aspm.h b/include/linux/aspm.h new file mode 100644 index 000000000000..f41a69895485 --- /dev/null +++ b/include/linux/aspm.h @@ -0,0 +1,44 @@ +/* + * aspm.h + * + * PCI Express ASPM defines and function prototypes + * + * Copyright (C) 2007 Intel Corp. + * Zhang Yanmin (yanmin.zhang@intel.com) + * Shaohua Li (shaohua.li@intel.com) + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI Express Specification + */ + +#ifndef LINUX_ASPM_H +#define LINUX_ASPM_H + +#include + +#define PCIE_LINK_STATE_L0S 1 +#define PCIE_LINK_STATE_L1 2 +#define PCIE_LINK_STATE_CLKPM 4 + +#ifdef CONFIG_PCIEASPM +extern void pcie_aspm_init_link_state(struct pci_dev *pdev); +extern void pcie_aspm_exit_link_state(struct pci_dev *pdev); +extern void pcie_aspm_pm_state_change(struct pci_dev *pdev); +extern void pci_disable_link_state(struct pci_dev *pdev, int state); +#else +#define pcie_aspm_init_link_state(pdev) do {} while (0) +#define pcie_aspm_exit_link_state(pdev) do {} while (0) +#define pcie_aspm_pm_state_change(pdev) do {} while (0) +#define pci_disable_link_state(pdev, state) do {} while (0) +#endif + +#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */ +extern void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev); +extern void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev); +#else +#define pcie_aspm_create_sysfs_dev_files(pdev) do {} while (0) +#define pcie_aspm_remove_sysfs_dev_files(pdev) do {} while (0) +#endif +#endif /* LINUX_ASPM_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 13813b0592fc..163b45241729 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -128,6 +128,7 @@ struct pci_cap_saved_state { u32 data[0]; }; +struct pcie_link_state; /* * The pci_dev structure is used to describe PCI devices. */ @@ -163,6 +164,10 @@ struct pci_dev { this is D0-D3, D0 being fully functional, and D3 being off. */ +#ifdef CONFIG_PCIEASPM + struct pcie_link_state *link_state; /* ASPM link state. */ +#endif + pci_channel_state_t error_state; /* current connectivity state */ struct device dev; /* Generic device interface */ diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index c1914a8b94a9..c0c1223c9194 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h @@ -395,9 +395,17 @@ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_LNKCAP 12 /* Link Capabilities */ +#define PCI_EXP_LNKCAP_ASPMS 0xc00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_L0SEL 0x7000 /* L0s Exit Latency */ +#define PCI_EXP_LNKCAP_L1EL 0x38000 /* L1 Exit Latency */ +#define PCI_EXP_LNKCAP_CLKPM 0x40000 /* L1 Clock Power Management */ #define PCI_EXP_LNKCTL 16 /* Link Control */ +#define PCI_EXP_LNKCTL_RL 0x20 /* Retrain Link */ +#define PCI_EXP_LNKCTL_CCC 0x40 /* Common Clock COnfiguration */ #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */ #define PCI_EXP_LNKSTA 18 /* Link Status */ +#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ +#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ -- cgit v1.2.3 From 05cca6e52a5a75ffd491fb50a9f636075b2d77ba Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 30 Jan 2008 15:21:33 -0800 Subject: PCI: fix codingstyle issues in include/linux/pci.h Fixes a number of coding style issues in pci.h. It's a tad more readable now... Signed-off-by: Greg Kroah-Hartman --- include/linux/pci.h | 343 ++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 236 insertions(+), 107 deletions(-) (limited to 'include') diff --git a/include/linux/pci.h b/include/linux/pci.h index 163b45241729..616f7ee8633f 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -28,7 +28,7 @@ * 7:3 = slot * 2:0 = function */ -#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) +#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) #define PCI_FUNC(devfn) ((devfn) & 0x07) @@ -219,7 +219,7 @@ static inline int pci_channel_offline(struct pci_dev *pdev) } static inline struct pci_cap_saved_state *pci_find_saved_cap( - struct pci_dev *pci_dev,char cap) + struct pci_dev *pci_dev, char cap) { struct pci_cap_saved_state *tmp; struct hlist_node *pos; @@ -351,11 +351,10 @@ enum pci_ers_result { }; /* PCI bus error event callbacks */ -struct pci_error_handlers -{ +struct pci_error_handlers { /* PCI bus error detected on this device */ pci_ers_result_t (*error_detected)(struct pci_dev *dev, - enum pci_channel_state error); + enum pci_channel_state error); /* MMIO has been re-enabled, but not DMA */ pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev); @@ -390,7 +389,7 @@ struct pci_driver { struct pci_dynids dynids; }; -#define to_pci_driver(drv) container_of(drv,struct pci_driver, driver) +#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) /** * PCI_DEVICE - macro used to describe a specific pci device @@ -448,7 +447,7 @@ extern int no_pci_devices(void); void pcibios_fixup_bus(struct pci_bus *); int __must_check pcibios_enable_device(struct pci_dev *, int mask); -char *pcibios_setup (char *str); +char *pcibios_setup(char *str); /* Used only when drivers/pci/setup.c is used */ void pcibios_align_resource(void *, struct resource *, resource_size_t, @@ -459,8 +458,10 @@ void pcibios_update_irq(struct pci_dev *, int irq); extern struct pci_bus *pci_find_bus(int domain, int busnr); void pci_bus_add_devices(struct pci_bus *bus); -struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); -static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata) +struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, + struct pci_ops *ops, void *sysdata); +static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, + void *sysdata) { struct pci_bus *root_bus; root_bus = pci_scan_bus_parented(NULL, bus, ops, sysdata); @@ -468,15 +469,18 @@ static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *s pci_bus_add_devices(root_bus); return root_bus; } -struct pci_bus *pci_create_bus(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); -struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); +struct pci_bus *pci_create_bus(struct device *parent, int bus, + struct pci_ops *ops, void *sysdata); +struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, + int busnr); int pci_scan_slot(struct pci_bus *bus, int devfn); -struct pci_dev * pci_scan_single_device(struct pci_bus *bus, int devfn); +struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn); void pci_device_add(struct pci_dev *dev, struct pci_bus *bus); unsigned int pci_scan_child_bus(struct pci_bus *bus); int __must_check pci_bus_add_device(struct pci_dev *dev); void pci_read_bridge_bases(struct pci_bus *child); -struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res); +struct resource *pci_find_parent_resource(const struct pci_dev *dev, + struct resource *res); int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); extern struct pci_dev *pci_dev_get(struct pci_dev *dev); extern void pci_dev_put(struct pci_dev *dev); @@ -489,15 +493,18 @@ extern void pci_sort_breadthfirst(void); /* Generic PCI functions exported to card drivers */ #ifdef CONFIG_PCI_LEGACY -struct pci_dev __deprecated *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from); -struct pci_dev __deprecated *pci_find_slot (unsigned int bus, unsigned int devfn); +struct pci_dev __deprecated *pci_find_device(unsigned int vendor, + unsigned int device, + const struct pci_dev *from); +struct pci_dev __deprecated *pci_find_slot(unsigned int bus, + unsigned int devfn); #endif /* CONFIG_PCI_LEGACY */ -int pci_find_capability (struct pci_dev *dev, int cap); -int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap); -int pci_find_ext_capability (struct pci_dev *dev, int cap); -int pci_find_ht_capability (struct pci_dev *dev, int ht_cap); -int pci_find_next_ht_capability (struct pci_dev *dev, int pos, int ht_cap); +int pci_find_capability(struct pci_dev *dev, int cap); +int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); +int pci_find_ext_capability(struct pci_dev *dev, int cap); +int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); +int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); void pcie_wait_pending_transaction(struct pci_dev *dev); struct pci_bus *pci_find_next_bus(const struct pci_bus *from); @@ -506,45 +513,53 @@ struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *pci_get_device_reverse(unsigned int vendor, unsigned int device, struct pci_dev *from); -struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device, +struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from); -struct pci_dev *pci_get_slot (struct pci_bus *bus, unsigned int devfn); -struct pci_dev *pci_get_bus_and_slot (unsigned int bus, unsigned int devfn); -struct pci_dev *pci_get_class (unsigned int class, struct pci_dev *from); +struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); +struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn); +struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from); int pci_dev_present(const struct pci_device_id *ids); const struct pci_device_id *pci_find_present(const struct pci_device_id *ids); -int pci_bus_read_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 *val); -int pci_bus_read_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 *val); -int pci_bus_read_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 *val); -int pci_bus_write_config_byte (struct pci_bus *bus, unsigned int devfn, int where, u8 val); -int pci_bus_write_config_word (struct pci_bus *bus, unsigned int devfn, int where, u16 val); -int pci_bus_write_config_dword (struct pci_bus *bus, unsigned int devfn, int where, u32 val); +int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 *val); +int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 *val); +int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 *val); +int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn, + int where, u8 val); +int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn, + int where, u16 val); +int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn, + int where, u32 val); static inline int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val) { - return pci_bus_read_config_byte (dev->bus, dev->devfn, where, val); + return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); } static inline int pci_read_config_word(struct pci_dev *dev, int where, u16 *val) { - return pci_bus_read_config_word (dev->bus, dev->devfn, where, val); + return pci_bus_read_config_word(dev->bus, dev->devfn, where, val); } -static inline int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val) +static inline int pci_read_config_dword(struct pci_dev *dev, int where, + u32 *val) { - return pci_bus_read_config_dword (dev->bus, dev->devfn, where, val); + return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); } static inline int pci_write_config_byte(struct pci_dev *dev, int where, u8 val) { - return pci_bus_write_config_byte (dev->bus, dev->devfn, where, val); + return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val); } static inline int pci_write_config_word(struct pci_dev *dev, int where, u16 val) { - return pci_bus_write_config_word (dev->bus, dev->devfn, where, val); + return pci_bus_write_config_word(dev->bus, dev->devfn, where, val); } -static inline int pci_write_config_dword(struct pci_dev *dev, int where, u32 val) +static inline int pci_write_config_dword(struct pci_dev *dev, int where, + u32 val) { - return pci_bus_write_config_dword (dev->bus, dev->devfn, where, val); + return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); } int __must_check pci_enable_device(struct pci_dev *dev); @@ -593,7 +608,7 @@ pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); /* Functions for PCI Hotplug drivers to use */ -int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap); +int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap); /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ void pci_bus_assign_resources(struct pci_bus *bus); @@ -630,16 +645,18 @@ static inline int __must_check pci_register_driver(struct pci_driver *driver) return __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME); } -void pci_unregister_driver(struct pci_driver *); -void pci_remove_behind_bridge(struct pci_dev *); -struct pci_driver *pci_dev_driver(const struct pci_dev *); -const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, struct pci_dev *dev); -int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass); +void pci_unregister_driver(struct pci_driver *dev); +void pci_remove_behind_bridge(struct pci_dev *dev); +struct pci_driver *pci_dev_driver(const struct pci_dev *dev); +const struct pci_device_id *pci_match_id(const struct pci_device_id *ids, + struct pci_dev *dev); +int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, + int pass); void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *), void *userdata); int pci_cfg_space_size(struct pci_dev *dev); -unsigned char pci_bus_max_busnr(struct pci_bus* bus); +unsigned char pci_bus_max_busnr(struct pci_bus *bus); /* kmem_cache style wrapper around pci_alloc_consistent() */ @@ -668,17 +685,32 @@ struct msix_entry { #ifndef CONFIG_PCI_MSI -static inline int pci_enable_msi(struct pci_dev *dev) {return -1;} -static inline void pci_disable_msi(struct pci_dev *dev) {} -static inline int pci_enable_msix(struct pci_dev* dev, - struct msix_entry *entries, int nvec) {return -1;} -static inline void pci_disable_msix(struct pci_dev *dev) {} -static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) {} -static inline void pci_restore_msi_state(struct pci_dev *dev) {} +static inline int pci_enable_msi(struct pci_dev *dev) +{ + return -1; +} + +static inline void pci_disable_msi(struct pci_dev *dev) +{ } + +static inline int pci_enable_msix(struct pci_dev *dev, + struct msix_entry *entries, int nvec) +{ + return -1; +} + +static inline void pci_disable_msix(struct pci_dev *dev) +{ } + +static inline void msi_remove_pci_irq_vectors(struct pci_dev *dev) +{ } + +static inline void pci_restore_msi_state(struct pci_dev *dev) +{ } #else extern int pci_enable_msi(struct pci_dev *dev); extern void pci_disable_msi(struct pci_dev *dev); -extern int pci_enable_msix(struct pci_dev* dev, +extern int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec); extern void pci_disable_msix(struct pci_dev *dev); extern void msi_remove_pci_irq_vectors(struct pci_dev *dev); @@ -703,7 +735,11 @@ extern void pci_unblock_user_cfg_access(struct pci_dev *dev); extern int pci_domains_supported; #else enum { pci_domains_supported = 0 }; -static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } +static inline int pci_domain_nr(struct pci_bus *bus) +{ + return 0; +} + static inline int pci_proc_domain(struct pci_bus *bus) { return 0; @@ -717,68 +753,161 @@ static inline int pci_proc_domain(struct pci_bus *bus) * these as simple inline functions to avoid hair in drivers. */ -#define _PCI_NOP(o,s,t) \ - static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \ +#define _PCI_NOP(o, s, t) \ + static inline int pci_##o##_config_##s(struct pci_dev *dev, \ + int where, t val) \ { return PCIBIOS_FUNC_NOT_SUPPORTED; } -#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \ - _PCI_NOP(o,word,u16 x) \ - _PCI_NOP(o,dword,u32 x) + +#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \ + _PCI_NOP(o, word, u16 x) \ + _PCI_NOP(o, dword, u32 x) _PCI_NOP_ALL(read, *) _PCI_NOP_ALL(write,) -static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from) -{ return NULL; } +static inline struct pci_dev *pci_find_device(unsigned int vendor, + unsigned int device, + const struct pci_dev *from) +{ + return NULL; +} -static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn) -{ return NULL; } +static inline struct pci_dev *pci_find_slot(unsigned int bus, + unsigned int devfn) +{ + return NULL; +} static inline struct pci_dev *pci_get_device(unsigned int vendor, - unsigned int device, struct pci_dev *from) -{ return NULL; } + unsigned int device, + struct pci_dev *from) +{ + return NULL; +} static inline struct pci_dev *pci_get_device_reverse(unsigned int vendor, - unsigned int device, struct pci_dev *from) -{ return NULL; } + unsigned int device, + struct pci_dev *from) +{ + return NULL; +} -static inline struct pci_dev *pci_get_subsys (unsigned int vendor, unsigned int device, -unsigned int ss_vendor, unsigned int ss_device, struct pci_dev *from) -{ return NULL; } +static inline struct pci_dev *pci_get_subsys(unsigned int vendor, + unsigned int device, + unsigned int ss_vendor, + unsigned int ss_device, + struct pci_dev *from) +{ + return NULL; +} -static inline struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from) -{ return NULL; } +static inline struct pci_dev *pci_get_class(unsigned int class, + struct pci_dev *from) +{ + return NULL; +} #define pci_dev_present(ids) (0) #define no_pci_devices() (1) #define pci_find_present(ids) (NULL) #define pci_dev_put(dev) do { } while (0) -static inline void pci_set_master(struct pci_dev *dev) { } -static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } -static inline void pci_disable_device(struct pci_dev *dev) { } -static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } -static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;} -static inline int __pci_register_driver(struct pci_driver *drv, struct module *owner) { return 0;} -static inline int pci_register_driver(struct pci_driver *drv) { return 0;} -static inline void pci_unregister_driver(struct pci_driver *drv) { } -static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; } -static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; } -static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; } -static inline void pcie_wait_pending_transaction(struct pci_dev *dev) {} +static inline void pci_set_master(struct pci_dev *dev) +{ } + +static inline int pci_enable_device(struct pci_dev *dev) +{ + return -EIO; +} + +static inline void pci_disable_device(struct pci_dev *dev) +{ } + +static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) +{ + return -EIO; +} + +static inline int pci_assign_resource(struct pci_dev *dev, int i) +{ + return -EBUSY; +} + +static inline int __pci_register_driver(struct pci_driver *drv, + struct module *owner) +{ + return 0; +} + +static inline int pci_register_driver(struct pci_driver *drv) +{ + return 0; +} + +static inline void pci_unregister_driver(struct pci_driver *drv) +{ } + +static inline int pci_find_capability(struct pci_dev *dev, int cap) +{ + return 0; +} + +static inline int pci_find_next_capability(struct pci_dev *dev, u8 post, + int cap) +{ + return 0; +} + +static inline int pci_find_ext_capability(struct pci_dev *dev, int cap) +{ + return 0; +} + +static inline void pcie_wait_pending_transaction(struct pci_dev *dev) +{ } /* Power management related routines */ -static inline int pci_save_state(struct pci_dev *dev) { return 0; } -static inline int pci_restore_state(struct pci_dev *dev) { return 0; } -static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) { return 0; } -static inline pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) { return PCI_D0; } -static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable) { return 0; } +static inline int pci_save_state(struct pci_dev *dev) +{ + return 0; +} + +static inline int pci_restore_state(struct pci_dev *dev) +{ + return 0; +} -static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) { return -EIO; } -static inline void pci_release_regions(struct pci_dev *dev) { } +static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state) +{ + return 0; +} + +static inline pci_power_t pci_choose_state(struct pci_dev *dev, + pm_message_t state) +{ + return PCI_D0; +} + +static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, + int enable) +{ + return 0; +} + +static inline int pci_request_regions(struct pci_dev *dev, const char *res_name) +{ + return -EIO; +} + +static inline void pci_release_regions(struct pci_dev *dev) +{ } #define pci_dma_burst_advice(pdev, strat, strategy_parameter) do { } while (0) -static inline void pci_block_user_cfg_access(struct pci_dev *dev) { } -static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) { } +static inline void pci_block_user_cfg_access(struct pci_dev *dev) +{ } + +static inline void pci_unblock_user_cfg_access(struct pci_dev *dev) +{ } static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from) { return NULL; } @@ -799,27 +928,27 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, /* these helpers provide future and backwards compatibility * for accessing popular PCI BAR info */ -#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start) -#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end) -#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags) +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) +#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) +#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) #define pci_resource_len(dev,bar) \ - ((pci_resource_start((dev),(bar)) == 0 && \ - pci_resource_end((dev),(bar)) == \ - pci_resource_start((dev),(bar))) ? 0 : \ - \ - (pci_resource_end((dev),(bar)) - \ - pci_resource_start((dev),(bar)) + 1)) + ((pci_resource_start((dev), (bar)) == 0 && \ + pci_resource_end((dev), (bar)) == \ + pci_resource_start((dev), (bar))) ? 0 : \ + \ + (pci_resource_end((dev), (bar)) - \ + pci_resource_start((dev), (bar)) + 1)) /* Similar to the helpers above, these manipulate per-pci_dev * driver-specific data. They are really just a wrapper around * the generic device structure functions of these calls. */ -static inline void *pci_get_drvdata (struct pci_dev *pdev) +static inline void *pci_get_drvdata(struct pci_dev *pdev) { return dev_get_drvdata(&pdev->dev); } -static inline void pci_set_drvdata (struct pci_dev *pdev, void *data) +static inline void pci_set_drvdata(struct pci_dev *pdev, void *data) { dev_set_drvdata(&pdev->dev, data); } @@ -838,7 +967,7 @@ static inline char *pci_name(struct pci_dev *pdev) */ #ifndef HAVE_ARCH_PCI_RESOURCE_TO_USER static inline void pci_resource_to_user(const struct pci_dev *dev, int bar, - const struct resource *rsrc, resource_size_t *start, + const struct resource *rsrc, resource_size_t *start, resource_size_t *end) { *start = rsrc->start; @@ -890,9 +1019,9 @@ enum pci_fixup_pass { void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); -void __iomem * pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); +void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen); void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr); -void __iomem * const * pcim_iomap_table(struct pci_dev *pdev); +void __iomem * const *pcim_iomap_table(struct pci_dev *pdev); int pcim_iomap_regions(struct pci_dev *pdev, u16 mask, const char *name); void pcim_iounmap_regions(struct pci_dev *pdev, u16 mask); -- cgit v1.2.3 From fd7d1ced29e5beb88c9068801da7a362606d8273 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 22 May 2007 22:47:54 -0400 Subject: PCI: make pci_bus a struct device This moves the pci_bus class device to be a real struct device and at the same time, place it in the device tree in the correct location. Note, the old "bridge" symlink is now gone, but this was a non-standard link and no userspace program used it. If you need to determine the device that the bus is on, follow the standard device symlink, or walk up the device tree. Signed-off-by: Greg Kroah-Hartman --- drivers/pci/bus.c | 17 +++++++++---- drivers/pci/pci-sysfs.c | 6 ++--- drivers/pci/pci.h | 2 +- drivers/pci/probe.c | 64 +++++++++++++++++++------------------------------ drivers/pci/remove.c | 6 ++--- include/linux/pci.h | 4 ++-- 6 files changed, 46 insertions(+), 53 deletions(-) (limited to 'include') diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c index 863340a7b77f..ef5a6a245f5f 100644 --- a/drivers/pci/bus.c +++ b/drivers/pci/bus.c @@ -108,6 +108,7 @@ int pci_bus_add_device(struct pci_dev *dev) void pci_bus_add_devices(struct pci_bus *bus) { struct pci_dev *dev; + struct pci_bus *child_bus; int retval; list_for_each_entry(dev, &bus->devices, bus_list) { @@ -138,11 +139,19 @@ void pci_bus_add_devices(struct pci_bus *bus) up_write(&pci_bus_sem); } pci_bus_add_devices(dev->subordinate); - retval = sysfs_create_link(&dev->subordinate->class_dev.kobj, - &dev->dev.kobj, "bridge"); + + /* register the bus with sysfs as the parent is now + * properly registered. */ + child_bus = dev->subordinate; + child_bus->dev.parent = child_bus->bridge; + retval = device_register(&child_bus->dev); + if (!retval) + retval = device_create_file(&child_bus->dev, + &dev_attr_cpuaffinity); if (retval) - dev_err(&dev->dev, "Error creating sysfs " - "bridge symlink, continuing...\n"); + dev_err(&dev->dev, "Error registering pci_bus" + " device bridge symlink," + " continuing...\n"); } } } diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index d05c1b252386..abf4203304e4 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -359,7 +359,7 @@ pci_read_legacy_io(struct kobject *kobj, struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct pci_bus *bus = to_pci_bus(container_of(kobj, - struct class_device, + struct device, kobj)); /* Only support 1, 2 or 4 byte accesses */ @@ -384,7 +384,7 @@ pci_write_legacy_io(struct kobject *kobj, struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count) { struct pci_bus *bus = to_pci_bus(container_of(kobj, - struct class_device, + struct device, kobj)); /* Only support 1, 2 or 4 byte accesses */ if (count != 1 && count != 2 && count != 4) @@ -408,7 +408,7 @@ pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr, struct vm_area_struct *vma) { struct pci_bus *bus = to_pci_bus(container_of(kobj, - struct class_device, + struct device, kobj)); return pci_mmap_legacy_page_range(bus, vma); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 79887efbd986..eabeb1f2ec99 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -64,7 +64,7 @@ static inline int pci_no_d1d2(struct pci_dev *dev) } extern int pcie_mch_quirk; extern struct device_attribute pci_dev_attrs[]; -extern struct class_device_attribute class_device_attr_cpuaffinity; +extern struct device_attribute dev_attr_cpuaffinity; /** * pci_match_one_device - Tell if a PCI device structure has a matching diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 9b4673df27e7..8b505bd925aa 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -54,7 +54,7 @@ static void pci_create_legacy_files(struct pci_bus *b) b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; b->legacy_io->read = pci_read_legacy_io; b->legacy_io->write = pci_write_legacy_io; - class_device_create_bin_file(&b->class_dev, b->legacy_io); + device_create_bin_file(&b->dev, b->legacy_io); /* Allocated above after the legacy_io struct */ b->legacy_mem = b->legacy_io + 1; @@ -62,15 +62,15 @@ static void pci_create_legacy_files(struct pci_bus *b) b->legacy_mem->size = 1024*1024; b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; b->legacy_mem->mmap = pci_mmap_legacy_mem; - class_device_create_bin_file(&b->class_dev, b->legacy_mem); + device_create_bin_file(&b->dev, b->legacy_mem); } } void pci_remove_legacy_files(struct pci_bus *b) { if (b->legacy_io) { - class_device_remove_bin_file(&b->class_dev, b->legacy_io); - class_device_remove_bin_file(&b->class_dev, b->legacy_mem); + device_remove_bin_file(&b->dev, b->legacy_io); + device_remove_bin_file(&b->dev, b->legacy_mem); kfree(b->legacy_io); /* both are allocated here */ } } @@ -82,26 +82,27 @@ void pci_remove_legacy_files(struct pci_bus *bus) { return; } /* * PCI Bus Class Devices */ -static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, +static ssize_t pci_bus_show_cpuaffinity(struct device *dev, + struct device_attribute *attr, char *buf) { int ret; cpumask_t cpumask; - cpumask = pcibus_to_cpumask(to_pci_bus(class_dev)); + cpumask = pcibus_to_cpumask(to_pci_bus(dev)); ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask); if (ret < PAGE_SIZE) buf[ret++] = '\n'; return ret; } -CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL); +DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL); /* * PCI Bus Class */ -static void release_pcibus_dev(struct class_device *class_dev) +static void release_pcibus_dev(struct device *dev) { - struct pci_bus *pci_bus = to_pci_bus(class_dev); + struct pci_bus *pci_bus = to_pci_bus(dev); if (pci_bus->bridge) put_device(pci_bus->bridge); @@ -110,7 +111,7 @@ static void release_pcibus_dev(struct class_device *class_dev) static struct class pcibus_class = { .name = "pci_bus", - .release = &release_pcibus_dev, + .dev_release = &release_pcibus_dev, }; static int __init pcibus_class_init(void) @@ -393,7 +394,6 @@ pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) { struct pci_bus *child; int i; - int retval; /* * Allocate a new bus, and inherit stuff from the parent.. @@ -409,15 +409,12 @@ pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) child->bus_flags = parent->bus_flags; child->bridge = get_device(&bridge->dev); - child->class_dev.class = &pcibus_class; - sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr); - retval = class_device_register(&child->class_dev); - if (retval) - goto error_register; - retval = class_device_create_file(&child->class_dev, - &class_device_attr_cpuaffinity); - if (retval) - goto error_file_create; + /* initialize some portions of the bus device, but don't register it + * now as the parent is not properly set up yet. This device will get + * registered later in pci_bus_add_devices() + */ + child->dev.class = &pcibus_class; + sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr); /* * Set up the primary, secondary and subordinate @@ -435,12 +432,6 @@ pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) bridge->subordinate = child; return child; - -error_file_create: - class_device_unregister(&child->class_dev); -error_register: - kfree(child); - return NULL; } struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) @@ -1107,32 +1098,27 @@ struct pci_bus * pci_create_bus(struct device *parent, goto dev_reg_err; b->bridge = get_device(dev); - b->class_dev.class = &pcibus_class; - sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus); - error = class_device_register(&b->class_dev); + b->dev.class = &pcibus_class; + b->dev.parent = b->bridge; + sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus); + error = device_register(&b->dev); if (error) goto class_dev_reg_err; - error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity); + error = device_create_file(&b->dev, &dev_attr_cpuaffinity); if (error) - goto class_dev_create_file_err; + goto dev_create_file_err; /* Create legacy_io and legacy_mem files for this bus */ pci_create_legacy_files(b); - error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge"); - if (error) - goto sys_create_link_err; - b->number = b->secondary = bus; b->resource[0] = &ioport_resource; b->resource[1] = &iomem_resource; return b; -sys_create_link_err: - class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity); -class_dev_create_file_err: - class_device_unregister(&b->class_dev); +dev_create_file_err: + device_unregister(&b->dev); class_dev_reg_err: device_unregister(dev); dev_reg_err: diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index 05c9ad2a7f8b..ec4a82ba29a8 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -78,10 +78,8 @@ void pci_remove_bus(struct pci_bus *pci_bus) list_del(&pci_bus->node); up_write(&pci_bus_sem); pci_remove_legacy_files(pci_bus); - class_device_remove_file(&pci_bus->class_dev, - &class_device_attr_cpuaffinity); - sysfs_remove_link(&pci_bus->class_dev.kobj, "bridge"); - class_device_unregister(&pci_bus->class_dev); + device_remove_file(&pci_bus->dev, &dev_attr_cpuaffinity); + device_unregister(&pci_bus->dev); } EXPORT_SYMBOL(pci_remove_bus); diff --git a/include/linux/pci.h b/include/linux/pci.h index 616f7ee8633f..4f96f1d94ac4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -278,13 +278,13 @@ struct pci_bus { unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ pci_bus_flags_t bus_flags; /* Inherited by child busses */ struct device *bridge; - struct class_device class_dev; + struct device dev; struct bin_attribute *legacy_io; /* legacy I/O for this bus */ struct bin_attribute *legacy_mem; /* legacy mem */ }; #define pci_bus_b(n) list_entry(n, struct pci_bus, node) -#define to_pci_bus(n) container_of(n, struct pci_bus, class_dev) +#define to_pci_bus(n) container_of(n, struct pci_bus, dev) /* * Error values that may be returned by PCI functions. -- cgit v1.2.3