From b56bae2dd6fda6baf3bb74af3812676eebdd52f2 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Fri, 9 Sep 2022 13:31:13 +0100 Subject: clk: microchip: mpfs: add reset controller Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com --- include/soc/microchip/mpfs.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include/soc') diff --git a/include/soc/microchip/mpfs.h b/include/soc/microchip/mpfs.h index 6466515262bd..f916dcde457f 100644 --- a/include/soc/microchip/mpfs.h +++ b/include/soc/microchip/mpfs.h @@ -40,4 +40,12 @@ struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev); #endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */ +#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) + +u32 mpfs_reset_read(struct device *dev); + +void mpfs_reset_write(struct device *dev, u32 val); + +#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */ + #endif /* __SOC_MPFS_H__ */ -- cgit v1.2.3