From 2c61a5459932f68af51306302ab128a623f37e96 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Sun, 12 May 2019 10:17:08 +0000 Subject: dt-bindings: clock: imx8mm: Add GPIO clocks Add macro for the GPIO clocks of the i.MX8MM. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Signed-off-by: Shawn Guo --- include/dt-bindings/clock/imx8mm-clock.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 1b4353e7b486..fe47798f95df 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -239,6 +239,12 @@ #define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK 222 -#define IMX8MM_CLK_END 223 +#define IMX8MM_CLK_GPIO1_ROOT 223 +#define IMX8MM_CLK_GPIO2_ROOT 224 +#define IMX8MM_CLK_GPIO3_ROOT 225 +#define IMX8MM_CLK_GPIO4_ROOT 226 +#define IMX8MM_CLK_GPIO5_ROOT 227 + +#define IMX8MM_CLK_END 228 #endif -- cgit v1.2.3 From 4ef69160b3ed62379ef853c512d3785bf2ea57e6 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 15 May 2019 01:09:24 +0000 Subject: dt-bindings: clock: imx8mq: Add SNVS clock Add macro for the SNVS clock of the i.MX8MQ. Signed-off-by: Anson Huang Reviewed-by: Leonard Crestez Signed-off-by: Shawn Guo --- include/dt-bindings/clock/imx8mq-clock.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 6677e920dc2d..0233bb1e6bf8 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -400,5 +400,7 @@ #define IMX8MQ_CLK_GPIO4_ROOT 262 #define IMX8MQ_CLK_GPIO5_ROOT 263 -#define IMX8MQ_CLK_END 264 +#define IMX8MQ_CLK_SNVS_ROOT 264 + +#define IMX8MQ_CLK_END 265 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- cgit v1.2.3 From 2b2ebb9acb89cf968bb08b488362383ae795e6b1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 15 May 2019 01:29:53 +0000 Subject: dt-bindings: clock: imx8mm: Add SNVS clock Add macro for the SNVS clock of the i.MX8MM. Signed-off-by: Anson Huang Reviewed-by: Leonard Crestez Signed-off-by: Shawn Guo --- include/dt-bindings/clock/imx8mm-clock.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index fe47798f95df..83f667368d55 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -245,6 +245,8 @@ #define IMX8MM_CLK_GPIO4_ROOT 226 #define IMX8MM_CLK_GPIO5_ROOT 227 -#define IMX8MM_CLK_END 228 +#define IMX8MM_CLK_SNVS_ROOT 228 + +#define IMX8MM_CLK_END 229 #endif -- cgit v1.2.3 From 87def8d0d5bfc32bf8a221b63addb8a051cbf017 Mon Sep 17 00:00:00 2001 From: Leonard Crestez Date: Wed, 22 May 2019 09:48:29 +0000 Subject: dt-bindings: clock: imx8m: Add GIC clock This should be defined in the clock tree so that parents are not shutdown by accident Signed-off-by: Leonard Crestez Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- include/dt-bindings/clock/imx8mm-clock.h | 3 ++- include/dt-bindings/clock/imx8mq-clock.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 83f667368d55..07e6c686f3ef 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -246,7 +246,8 @@ #define IMX8MM_CLK_GPIO5_ROOT 227 #define IMX8MM_CLK_SNVS_ROOT 228 +#define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 229 +#define IMX8MM_CLK_END 230 #endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 0233bb1e6bf8..65463673d25e 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -401,6 +401,7 @@ #define IMX8MQ_CLK_GPIO5_ROOT 263 #define IMX8MQ_CLK_SNVS_ROOT 264 +#define IMX8MQ_CLK_GIC 265 -#define IMX8MQ_CLK_END 265 +#define IMX8MQ_CLK_END 266 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ -- cgit v1.2.3 From cc9bdecf4b8d20b3d3d0f8a6cb3e577548b5539f Mon Sep 17 00:00:00 2001 From: Lukasz Luba Date: Wed, 5 Jun 2019 18:53:58 +0200 Subject: clk: samsung: add needed IDs for DMC clocks in Exynos5420 Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Acked-by: Rob Herring Acked-by: Chanwoo Choi Acked-by: Krzysztof Kozlowski Signed-off-by: Lukasz Luba Signed-off-by: Sylwester Nawrocki --- include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469943f1..02d5ac469a3d 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,16 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +228,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +261,11 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 +#define CLK_DOUT_PCLK_DREX0 798 +#define CLK_DOUT_PCLK_DREX1 799 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 800 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ -- cgit v1.2.3 From 3d8b6e9c774ff57ad2860f79abd9cdb8f29ecaf8 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Thu, 2 May 2019 14:18:42 +0200 Subject: dt-bindings: mediatek: audsys: add support for MT8516 Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC. Signed-off-by: Fabien Parent Reviewed-by: Rob Herring Signed-off-by: Stephen Boyd --- .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + include/dt-bindings/clock/mt8516-clk.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'include/dt-bindings') diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt index f3cef1a6d95c..07c9d813465c 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt @@ -10,6 +10,7 @@ Required Properties: - "mediatek,mt7622-audsys", "syscon" - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" - "mediatek,mt8183-audiosys", "syscon" + - "mediatek,mt8516-audsys", "syscon" - #clock-cells: Must be 1 The AUDSYS controller uses the common clk binding from diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h index 9cfca53cd78d..816447b98edd 100644 --- a/include/dt-bindings/clock/mt8516-clk.h +++ b/include/dt-bindings/clock/mt8516-clk.h @@ -208,4 +208,21 @@ #define CLK_TOP_MSDC2_INFRA 176 #define CLK_TOP_NR_CLK 177 +/* AUDSYS */ + +#define CLK_AUD_AFE 0 +#define CLK_AUD_I2S 1 +#define CLK_AUD_22M 2 +#define CLK_AUD_24M 3 +#define CLK_AUD_INTDIR 4 +#define CLK_AUD_APLL2_TUNER 5 +#define CLK_AUD_APLL_TUNER 6 +#define CLK_AUD_HDMI 7 +#define CLK_AUD_SPDF 8 +#define CLK_AUD_ADC 9 +#define CLK_AUD_DAC 10 +#define CLK_AUD_DAC_PREDIS 11 +#define CLK_AUD_TML 12 +#define CLK_AUD_NR_CLK 13 + #endif /* _DT_BINDINGS_CLK_MT8516_H */ -- cgit v1.2.3 From 072a551fd5cff2329ad151c7c25b7958afc0f149 Mon Sep 17 00:00:00 2001 From: Jeffrey Hugo Date: Tue, 28 May 2019 09:47:40 -0700 Subject: dt-bindings: clock: Document gpucc for msm8998 The GPU for msm8998 has its own clock controller. Document it. Signed-off-by: Jeffrey Hugo Signed-off-by: Stephen Boyd --- .../devicetree/bindings/clock/qcom,gpucc.txt | 4 ++- include/dt-bindings/clock/qcom,gpucc-msm8998.h | 29 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,gpucc-msm8998.h (limited to 'include/dt-bindings') diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt index 4e5215ef1acd..269afe8a757e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.txt @@ -2,13 +2,15 @@ Qualcomm Graphics Clock & Reset Controller Binding -------------------------------------------------- Required properties : -- compatible : shall contain "qcom,sdm845-gpucc" +- compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc" - reg : shall contain base register location and length - #clock-cells : from common clock binding, shall contain 1 - #reset-cells : from common reset binding, shall contain 1 - #power-domain-cells : from generic power domain binding, shall contain 1 - clocks : shall contain the XO clock + shall contain the gpll0 out main clock (msm8998) - clock-names : shall be "xo" + shall be "gpll0" (msm8998) Example: gpucc: clock-controller@5090000 { diff --git a/include/dt-bindings/clock/qcom,gpucc-msm8998.h b/include/dt-bindings/clock/qcom,gpucc-msm8998.h new file mode 100644 index 000000000000..2623570ee974 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-msm8998.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Jeffrey Hugo + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GPUCC_8998_H +#define _DT_BINDINGS_CLK_MSM_GPUCC_8998_H + +#define GPUPLL0 0 +#define GPUPLL0_OUT_EVEN 1 +#define RBCPR_CLK_SRC 2 +#define GFX3D_CLK_SRC 3 +#define RBBMTIMER_CLK_SRC 4 +#define GFX3D_ISENSE_CLK_SRC 5 +#define RBCPR_CLK 6 +#define GFX3D_CLK 7 +#define RBBMTIMER_CLK 8 +#define GFX3D_ISENSE_CLK 9 +#define GPUCC_CXO_CLK 10 + +#define GPU_CX_BCR 0 +#define RBCPR_BCR 1 +#define GPU_GX_BCR 2 +#define GPU_ISENSE_BCR 3 + +#define GPU_CX_GDSC 1 +#define GPU_GX_GDSC 2 + +#endif -- cgit v1.2.3 From e5bbbff5b7d7e76ccfe922a014ba628c558eff2f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 8 May 2019 15:39:22 -0700 Subject: clk: gcc-qcs404: Add PCIe resets Enabling PCIe requires several of the PCIe related resets from GCC, so add them all. Reviewed-by: Niklas Cassel Acked-by: Rob Herring Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Signed-off-by: Stephen Boyd --- drivers/clk/qcom/gcc-qcs404.c | 7 +++++++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++ 2 files changed, 14 insertions(+) (limited to 'include/dt-bindings') diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index a54807eb3b28..29cf464dd2c8 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2766,6 +2766,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, [GCC_EMAC_BCR] = { 0x4e000 }, }; diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index 454b3f43f538..2cd62c98561f 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -166,5 +166,12 @@ #define GCC_PCIEPHY_0_PHY_BCR 12 #define GCC_EMAC_BCR 13 #define GCC_CDSP_RESTART 14 +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15 +#define GCC_PCIE_0_AHB_ARES 16 +#define GCC_PCIE_0_AXI_SLAVE_ARES 17 +#define GCC_PCIE_0_AXI_MASTER_ARES 18 +#define GCC_PCIE_0_CORE_STICKY_ARES 19 +#define GCC_PCIE_0_SLEEP_ARES 20 +#define GCC_PCIE_0_PIPE_ARES 21 #endif -- cgit v1.2.3 From a987be182c309f565a2d3545f2e9c9a4f8d07a4d Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 20 May 2019 22:03:16 +0200 Subject: dt-bindings: clock: meson8b: add the audio clocks The audio controllers on Meson8, Meson8b and Meson8m2 use similar (potentially the same) audio clocks as GXBB, GXL and GXM. Add the CLKID_CTS_AMCLK, CLKID_CTS_MCLK_I958 and CLKID_CTS_I958 clock IDs so they can be used for the audio controllers. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet --- include/dt-bindings/clock/meson8b-clkc.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index 47556539f0ee..68862aaf977e 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -112,5 +112,8 @@ #define CLKID_VDEC_HCODEC 199 #define CLKID_VDEC_2 202 #define CLKID_VDEC_HEVC 206 +#define CLKID_CTS_AMCLK 209 +#define CLKID_CTS_MCLK_I958 212 +#define CLKID_CTS_I958 213 #endif /* __MESON8B_CLKC_H */ -- cgit v1.2.3 From 6e47ef34db571e3eebda46ddaddae00d369df5f9 Mon Sep 17 00:00:00 2001 From: Guillaume La Roque Date: Fri, 12 Apr 2019 12:02:20 +0200 Subject: dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs Add clock ids used by the temperature sensors of the G12A Socs Reviewed-by: Martin Blumenstingl Acked-by: Rob Herring Signed-off-by: Guillaume La Roque Signed-off-by: Jerome Brunet [fixed commit message] --- include/dt-bindings/clock/g12a-clkc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h index 82c9e0c020b2..cfda463091b7 100644 --- a/include/dt-bindings/clock/g12a-clkc.h +++ b/include/dt-bindings/clock/g12a-clkc.h @@ -136,5 +136,6 @@ #define CLKID_VDEC_1 204 #define CLKID_VDEC_HEVC 207 #define CLKID_VDEC_HEVCF 210 +#define CLKID_TS 212 #endif /* __G12A_CLKC_H */ -- cgit v1.2.3 From 7ef91224c4864202958b018cd5612db5cc9dc67d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 18 Jun 2019 21:05:26 +0200 Subject: clk: samsung: Add bus clock for GPU/G3D on Exynos4412 Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sylwester Nawrocki --- drivers/clk/samsung/clk-exynos4.c | 1 + include/dt-bindings/clock/exynos4.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include/dt-bindings') diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index d2a68a792a21..ed4af7da9c4f 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -961,6 +961,7 @@ static const struct samsung_gate_clock exynos4210_gate_clks[] __initconst = { /* list of gate clocks supported in exynos4x12 soc */ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { + GATE(CLK_ASYNC_G3D, "async_g3d", "aclk200", GATE_IP_LEFTBUS, 6, 0, 0), GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index a0439ce8e8d3..88ec3968b90a 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -187,6 +187,7 @@ #define CLK_MIPI_HSI 349 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 +#define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ -- cgit v1.2.3 From 3b5015c4d834a70233c4419b07375254e4675e0b Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 24 Jun 2019 16:47:10 -0500 Subject: clk: socfpga: stratix10: add additional clocks needed for the NAND IP The nand_clk is actually called the nand_x_clk and the parent is the l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the nand_x_clk and has a fixed divider of 4. The same is true for the nand_ecc_clk. Signed-off-by: Dinh Nguyen Signed-off-by: Stephen Boyd --- drivers/clk/socfpga/clk-s10.c | 6 +++++- include/dt-bindings/clock/stratix10-clock.h | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include/dt-bindings') diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c index 8281dfbf38c2..609dd722675e 100644 --- a/drivers/clk/socfpga/clk-s10.c +++ b/drivers/clk/socfpga/clk-s10.c @@ -161,8 +161,12 @@ static const struct stratix10_gate_clock s10_gate_clks[] = { 8, 0, 0, 0, 0, 0, 0}, { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 9, 0, 0, 0, 0, 0, 0}, - { STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4, + { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 10, 0, 0, 0, 0, 0, 0}, + { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4, + 10, 0, 0, 0, 0, 0, 4}, + { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4, + 10, 0, 0, 0, 0, 0, 4}, }; static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, diff --git a/include/dt-bindings/clock/stratix10-clock.h b/include/dt-bindings/clock/stratix10-clock.h index 0ac1c90a18bf..08b98e20b7cc 100644 --- a/include/dt-bindings/clock/stratix10-clock.h +++ b/include/dt-bindings/clock/stratix10-clock.h @@ -79,6 +79,8 @@ #define STRATIX10_USB_CLK 59 #define STRATIX10_SPI_M_CLK 60 #define STRATIX10_NAND_CLK 61 -#define STRATIX10_NUM_CLKS 62 +#define STRATIX10_NAND_X_CLK 62 +#define STRATIX10_NAND_ECC_CLK 63 +#define STRATIX10_NUM_CLKS 64 #endif /* __STRATIX10_CLOCK_H */ -- cgit v1.2.3 From 0dc14b013f7982de6e81b5b2931a2131d20cbb6d Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 15 Jun 2019 14:18:17 +0200 Subject: clk: rockchip: add clock id for watchdog pclk on rk3328 Needed to export that added clock. Signed-off-by: Heiko Stuebner --- include/dt-bindings/clock/rk3328-cru.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index bcaa4559ab1b..6ad54c39f8da 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -173,6 +173,7 @@ #define PCLK_DCF 233 #define PCLK_SARADC 234 #define PCLK_ACODECPHY 235 +#define PCLK_WDT 236 /* hclk gates */ #define HCLK_PERI 308 -- cgit v1.2.3 From dbc08f18ea49bd1952fb1158a56d400b77117403 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 14 Jun 2019 10:58:04 +0200 Subject: clk: rockchip: add clock id for hdmi_phy special clock on rk3228 Add the needed clock id to enable clock settings from devicetree. Signed-off-by: Heiko Stuebner Tested-by: Justin Swartz --- include/dt-bindings/clock/rk3228-cru.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/dt-bindings') diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 55655ab0a4c4..a0422f62c040 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -73,6 +73,7 @@ #define SCLK_WIFI 141 #define SCLK_OTGPHY0 142 #define SCLK_OTGPHY1 143 +#define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 -- cgit v1.2.3