From da53cc634cea6eb5d21809512ef348f6d4130850 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 16 Nov 2021 14:54:06 +0200 Subject: gpio: bd70528 Drop BD70528 support The only known BD70528 use-cases are such that the PMIC is controlled from separate MCU which is not running Linux. I am not aware of any Linux driver users. Furthermore, it seems there is no demand for this IC. Let's ease the maintenance burden and drop the driver. We can always add it back if there is sudden need for it. Signed-off-by: Matti Vaittinen Acked-by: Bartosz Golaszewski Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/4eff6bd5eff8afc137dd8c1697cb5c6b2e3aacd2.1637066805.git.matti.vaittinen@fi.rohmeurope.com --- drivers/gpio/Kconfig | 11 --- drivers/gpio/Makefile | 1 - drivers/gpio/gpio-bd70528.c | 230 -------------------------------------------- 3 files changed, 242 deletions(-) delete mode 100644 drivers/gpio/gpio-bd70528.c (limited to 'drivers') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 072ed610f9c6..4c02ee52b701 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1132,17 +1132,6 @@ config GPIO_ARIZONA help Support for GPIOs on Wolfson Arizona class devices. -config GPIO_BD70528 - tristate "ROHM BD70528 GPIO support" - depends on MFD_ROHM_BD70528 - help - Support for GPIOs on ROHM BD70528 PMIC. There are four GPIOs - available on the ROHM PMIC in total. The GPIOs can also - generate interrupts. - - This driver can also be built as a module. If so, the module - will be called gpio-bd70528. - config GPIO_BD71815 tristate "ROHM BD71815 PMIC GPIO support" depends on MFD_ROHM_BD71828 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 71ee9fc2ff83..ed5f9b1a75ce 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o obj-$(CONFIG_GPIO_ATH79) += gpio-ath79.o obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o -obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o diff --git a/drivers/gpio/gpio-bd70528.c b/drivers/gpio/gpio-bd70528.c deleted file mode 100644 index 397a50d6bc65..000000000000 --- a/drivers/gpio/gpio-bd70528.c +++ /dev/null @@ -1,230 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -// Copyright (C) 2018 ROHM Semiconductors -// gpio-bd70528.c ROHM BD70528MWV gpio driver - -#include -#include -#include -#include -#include - -#define GPIO_IN_REG(offset) (BD70528_REG_GPIO1_IN + (offset) * 2) -#define GPIO_OUT_REG(offset) (BD70528_REG_GPIO1_OUT + (offset) * 2) - -struct bd70528_gpio { - struct regmap *regmap; - struct device *dev; - struct gpio_chip gpio; -}; - -static int bd70528_set_debounce(struct bd70528_gpio *bdgpio, - unsigned int offset, unsigned int debounce) -{ - u8 val; - - switch (debounce) { - case 0: - val = BD70528_DEBOUNCE_DISABLE; - break; - case 1 ... 15000: - val = BD70528_DEBOUNCE_15MS; - break; - case 15001 ... 30000: - val = BD70528_DEBOUNCE_30MS; - break; - case 30001 ... 50000: - val = BD70528_DEBOUNCE_50MS; - break; - default: - dev_err(bdgpio->dev, - "Invalid debounce value %u\n", debounce); - return -EINVAL; - } - return regmap_update_bits(bdgpio->regmap, GPIO_IN_REG(offset), - BD70528_DEBOUNCE_MASK, val); -} - -static int bd70528_get_direction(struct gpio_chip *chip, unsigned int offset) -{ - struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); - int val, ret; - - /* Do we need to do something to IRQs here? */ - ret = regmap_read(bdgpio->regmap, GPIO_OUT_REG(offset), &val); - if (ret) { - dev_err(bdgpio->dev, "Could not read gpio direction\n"); - return ret; - } - if (val & BD70528_GPIO_OUT_EN_MASK) - return GPIO_LINE_DIRECTION_OUT; - - return GPIO_LINE_DIRECTION_IN; -} - -static int bd70528_gpio_set_config(struct gpio_chip *chip, unsigned int offset, - unsigned long config) -{ - struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); - - switch (pinconf_to_config_param(config)) { - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - return regmap_update_bits(bdgpio->regmap, - GPIO_OUT_REG(offset), - BD70528_GPIO_DRIVE_MASK, - BD70528_GPIO_OPEN_DRAIN); - break; - case PIN_CONFIG_DRIVE_PUSH_PULL: - return regmap_update_bits(bdgpio->regmap, - GPIO_OUT_REG(offset), - BD70528_GPIO_DRIVE_MASK, - BD70528_GPIO_PUSH_PULL); - break; - case PIN_CONFIG_INPUT_DEBOUNCE: - return bd70528_set_debounce(bdgpio, offset, - pinconf_to_config_argument(config)); - break; - default: - break; - } - return -ENOTSUPP; -} - -static int bd70528_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); - - /* Do we need to do something to IRQs here? */ - return regmap_update_bits(bdgpio->regmap, GPIO_OUT_REG(offset), - BD70528_GPIO_OUT_EN_MASK, - BD70528_GPIO_OUT_DISABLE); -} - -static void bd70528_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) -{ - int ret; - struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); - u8 val = (value) ? BD70528_GPIO_OUT_HI : BD70528_GPIO_OUT_LO; - - ret = regmap_update_bits(bdgpio->regmap, GPIO_OUT_REG(offset), - BD70528_GPIO_OUT_MASK, val); - if (ret) - dev_err(bdgpio->dev, "Could not set gpio to %d\n", value); -} - -static int bd70528_direction_output(struct gpio_chip *chip, unsigned int offset, - int value) -{ - struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); - - bd70528_gpio_set(chip, offset, value); - return regmap_update_bits(bdgpio->regmap, GPIO_OUT_REG(offset), - BD70528_GPIO_OUT_EN_MASK, - BD70528_GPIO_OUT_ENABLE); -} - -#define GPIO_IN_STATE_MASK(offset) (BD70528_GPIO_IN_STATE_BASE << (offset)) - -static int bd70528_gpio_get_o(struct bd70528_gpio *bdgpio, unsigned int offset) -{ - int ret; - unsigned int val; - - ret = regmap_read(bdgpio->regmap, GPIO_OUT_REG(offset), &val); - if (!ret) - ret = !!(val & BD70528_GPIO_OUT_MASK); - else - dev_err(bdgpio->dev, "GPIO (out) state read failed\n"); - - return ret; -} - -static int bd70528_gpio_get_i(struct bd70528_gpio *bdgpio, unsigned int offset) -{ - unsigned int val; - int ret; - - ret = regmap_read(bdgpio->regmap, BD70528_REG_GPIO_STATE, &val); - - if (!ret) - ret = !(val & GPIO_IN_STATE_MASK(offset)); - else - dev_err(bdgpio->dev, "GPIO (in) state read failed\n"); - - return ret; -} - -static int bd70528_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - int ret; - struct bd70528_gpio *bdgpio = gpiochip_get_data(chip); - - /* - * There is a race condition where someone might be changing the - * GPIO direction after we get it but before we read the value. But - * application design where GPIO direction may be changed just when - * we read GPIO value would be pointless as reader could not know - * whether the returned high/low state is caused by input or output. - * Or then there must be other ways to mitigate the issue. Thus - * locking would make no sense. - */ - ret = bd70528_get_direction(chip, offset); - if (ret == GPIO_LINE_DIRECTION_OUT) - ret = bd70528_gpio_get_o(bdgpio, offset); - else if (ret == GPIO_LINE_DIRECTION_IN) - ret = bd70528_gpio_get_i(bdgpio, offset); - else - dev_err(bdgpio->dev, "failed to read GPIO direction\n"); - - return ret; -} - -static int bd70528_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct bd70528_gpio *bdgpio; - int ret; - - bdgpio = devm_kzalloc(dev, sizeof(*bdgpio), GFP_KERNEL); - if (!bdgpio) - return -ENOMEM; - bdgpio->dev = dev; - bdgpio->gpio.parent = dev->parent; - bdgpio->gpio.label = "bd70528-gpio"; - bdgpio->gpio.owner = THIS_MODULE; - bdgpio->gpio.get_direction = bd70528_get_direction; - bdgpio->gpio.direction_input = bd70528_direction_input; - bdgpio->gpio.direction_output = bd70528_direction_output; - bdgpio->gpio.set_config = bd70528_gpio_set_config; - bdgpio->gpio.can_sleep = true; - bdgpio->gpio.get = bd70528_gpio_get; - bdgpio->gpio.set = bd70528_gpio_set; - bdgpio->gpio.ngpio = 4; - bdgpio->gpio.base = -1; -#ifdef CONFIG_OF_GPIO - bdgpio->gpio.of_node = dev->parent->of_node; -#endif - bdgpio->regmap = dev_get_regmap(dev->parent, NULL); - if (!bdgpio->regmap) - return -ENODEV; - - ret = devm_gpiochip_add_data(dev, &bdgpio->gpio, bdgpio); - if (ret) - dev_err(dev, "gpio_init: Failed to add bd70528-gpio\n"); - - return ret; -} - -static struct platform_driver bd70528_gpio = { - .driver = { - .name = "bd70528-gpio" - }, - .probe = bd70528_probe, -}; - -module_platform_driver(bd70528_gpio); - -MODULE_AUTHOR("Matti Vaittinen "); -MODULE_DESCRIPTION("BD70528 voltage regulator driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:bd70528-gpio"); -- cgit v1.2.3 From 306456c21c792ac633e660bc45f0854b612a0e98 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 16 Nov 2021 14:54:35 +0200 Subject: mfd: bd70528: Drop BD70528 support The only known BD70528 use-cases are such that the PMIC is controlled from separate MCU which is not running Linux. I am not aware of any Linux driver users. Furthermore, it seems there is no demand for this IC. Let's ease the maintenance burden and drop the driver. We can always add it back if there is sudden need for it. Signed-off-by: Matti Vaittinen Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/cf7dfd98b3403ad363b2b48b57bdbfd57a6416cb.1637066805.git.matti.vaittinen@fi.rohmeurope.com --- drivers/mfd/Kconfig | 17 -- drivers/mfd/Makefile | 1 - drivers/mfd/rohm-bd70528.c | 314 ------------------------------- include/linux/mfd/rohm-bd70528.h | 389 --------------------------------------- include/linux/mfd/rohm-generic.h | 1 - 5 files changed, 722 deletions(-) delete mode 100644 drivers/mfd/rohm-bd70528.c delete mode 100644 include/linux/mfd/rohm-bd70528.h (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3fb480818599..34c7d9d6b580 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1945,23 +1945,6 @@ config MFD_ROHM_BD718XX NXP i.MX8. It contains 8 BUCK outputs and 7 LDOs, voltage monitoring and emergency shut down as well as 32,768KHz clock output. -config MFD_ROHM_BD70528 - tristate "ROHM BD70528 Power Management IC" - depends on I2C=y - depends on OF - select REGMAP_I2C - select REGMAP_IRQ - select MFD_CORE - help - Select this option to get support for the ROHM BD70528 Power - Management IC. BD71837 is general purpose single-chip power - management IC for battery-powered portable devices. It contains - 3 ultra-low current consumption buck converters, 3 LDOs and 2 LED - drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz - crystal oscillator, high-accuracy VREF for use with an external ADC, - 10 bits SAR ADC for battery temperature monitor and 1S battery - charger. - config MFD_ROHM_BD71828 tristate "ROHM BD71828 and BD71815 Power Management IC" depends on I2C=y diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 0b1b629aef3e..4d53e951a92d 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -257,7 +257,6 @@ obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o obj-$(CONFIG_MFD_SC27XX_PMIC) += sprd-sc27xx-spi.o obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o -obj-$(CONFIG_MFD_ROHM_BD70528) += rohm-bd70528.o obj-$(CONFIG_MFD_ROHM_BD71828) += rohm-bd71828.o obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o obj-$(CONFIG_MFD_ROHM_BD957XMUF) += rohm-bd9576.o diff --git a/drivers/mfd/rohm-bd70528.c b/drivers/mfd/rohm-bd70528.c deleted file mode 100644 index 5c44d3b77b3e..000000000000 --- a/drivers/mfd/rohm-bd70528.c +++ /dev/null @@ -1,314 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// -// Copyright (C) 2019 ROHM Semiconductors -// -// ROHM BD70528 PMIC driver - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define BD70528_NUM_OF_GPIOS 4 - -static const struct resource rtc_irqs[] = { - DEFINE_RES_IRQ_NAMED(BD70528_INT_RTC_ALARM, "bd70528-rtc-alm"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_ELPS_TIM, "bd70528-elapsed-timer"), -}; - -static const struct resource charger_irqs[] = { - DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_RES, "bd70528-bat-ov-res"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_OV_DET, "bd70528-bat-ov-det"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DBAT_DET, "bd70528-bat-dead"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_RES, "bd70528-bat-warmed"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_COLD_DET, "bd70528-bat-cold"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_RES, "bd70528-bat-cooled"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BATTSD_HOT_DET, "bd70528-bat-hot"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_CHG_TSD, "bd70528-chg-tshd"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_RMV, "bd70528-bat-removed"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_BAT_DET, "bd70528-bat-detected"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_RES, "bd70528-dcin2-ov-res"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_OV_DET, "bd70528-dcin2-ov-det"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_RMV, "bd70528-dcin2-removed"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN2_DET, "bd70528-dcin2-detected"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_RMV, "bd70528-dcin1-removed"), - DEFINE_RES_IRQ_NAMED(BD70528_INT_DCIN1_DET, "bd70528-dcin1-detected"), -}; - -static struct mfd_cell bd70528_mfd_cells[] = { - { .name = "bd70528-pmic", }, - { .name = "bd70528-gpio", }, - /* - * We use BD71837 driver to drive the clock block. Only differences to - * BD70528 clock gate are the register address and mask. - */ - { .name = "bd70528-clk", }, - { .name = "bd70528-wdt", }, - { - .name = "bd70528-power", - .resources = charger_irqs, - .num_resources = ARRAY_SIZE(charger_irqs), - }, { - .name = "bd70528-rtc", - .resources = rtc_irqs, - .num_resources = ARRAY_SIZE(rtc_irqs), - }, -}; - -static const struct regmap_range volatile_ranges[] = { - { - .range_min = BD70528_REG_INT_MAIN, - .range_max = BD70528_REG_INT_OP_FAIL, - }, { - .range_min = BD70528_REG_RTC_COUNT_H, - .range_max = BD70528_REG_RTC_ALM_REPEAT, - }, { - /* - * WDT control reg is special. Magic values must be written to - * it in order to change the control. Should not be cached. - */ - .range_min = BD70528_REG_WDT_CTRL, - .range_max = BD70528_REG_WDT_CTRL, - }, { - /* - * BD70528 also contains a few other registers which require - * magic sequences to be written in order to update the value. - * At least SHIPMODE, HWRESET, WARMRESET,and STANDBY - */ - .range_min = BD70528_REG_SHIPMODE, - .range_max = BD70528_REG_STANDBY, - }, -}; - -static const struct regmap_access_table volatile_regs = { - .yes_ranges = &volatile_ranges[0], - .n_yes_ranges = ARRAY_SIZE(volatile_ranges), -}; - -static struct regmap_config bd70528_regmap = { - .reg_bits = 8, - .val_bits = 8, - .volatile_table = &volatile_regs, - .max_register = BD70528_MAX_REGISTER, - .cache_type = REGCACHE_RBTREE, -}; - -/* - * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can - * access corect sub-IRQ registers based on bits that are set in main IRQ - * register. - */ - -static unsigned int bit0_offsets[] = {0}; /* Shutdown */ -static unsigned int bit1_offsets[] = {1}; /* Power failure */ -static unsigned int bit2_offsets[] = {2}; /* VR FAULT */ -static unsigned int bit3_offsets[] = {3}; /* PMU interrupts */ -static unsigned int bit4_offsets[] = {4, 5}; /* Charger 1 and Charger 2 */ -static unsigned int bit5_offsets[] = {6}; /* RTC */ -static unsigned int bit6_offsets[] = {7}; /* GPIO */ -static unsigned int bit7_offsets[] = {8}; /* Invalid operation */ - -static struct regmap_irq_sub_irq_map bd70528_sub_irq_offsets[] = { - REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), - REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), -}; - -static struct regmap_irq bd70528_irqs[] = { - REGMAP_IRQ_REG(BD70528_INT_LONGPUSH, 0, BD70528_INT_LONGPUSH_MASK), - REGMAP_IRQ_REG(BD70528_INT_WDT, 0, BD70528_INT_WDT_MASK), - REGMAP_IRQ_REG(BD70528_INT_HWRESET, 0, BD70528_INT_HWRESET_MASK), - REGMAP_IRQ_REG(BD70528_INT_RSTB_FAULT, 0, BD70528_INT_RSTB_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_VBAT_UVLO, 0, BD70528_INT_VBAT_UVLO_MASK), - REGMAP_IRQ_REG(BD70528_INT_TSD, 0, BD70528_INT_TSD_MASK), - REGMAP_IRQ_REG(BD70528_INT_RSTIN, 0, BD70528_INT_RSTIN_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK1_FAULT, 1, - BD70528_INT_BUCK1_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK2_FAULT, 1, - BD70528_INT_BUCK2_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK3_FAULT, 1, - BD70528_INT_BUCK3_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_LDO1_FAULT, 1, BD70528_INT_LDO1_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_LDO2_FAULT, 1, BD70528_INT_LDO2_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_LDO3_FAULT, 1, BD70528_INT_LDO3_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_LED1_FAULT, 1, BD70528_INT_LED1_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_LED2_FAULT, 1, BD70528_INT_LED2_FAULT_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK1_OCP, 2, BD70528_INT_BUCK1_OCP_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK2_OCP, 2, BD70528_INT_BUCK2_OCP_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK3_OCP, 2, BD70528_INT_BUCK3_OCP_MASK), - REGMAP_IRQ_REG(BD70528_INT_LED1_OCP, 2, BD70528_INT_LED1_OCP_MASK), - REGMAP_IRQ_REG(BD70528_INT_LED2_OCP, 2, BD70528_INT_LED2_OCP_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK1_FULLON, 2, - BD70528_INT_BUCK1_FULLON_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK2_FULLON, 2, - BD70528_INT_BUCK2_FULLON_MASK), - REGMAP_IRQ_REG(BD70528_INT_SHORTPUSH, 3, BD70528_INT_SHORTPUSH_MASK), - REGMAP_IRQ_REG(BD70528_INT_AUTO_WAKEUP, 3, - BD70528_INT_AUTO_WAKEUP_MASK), - REGMAP_IRQ_REG(BD70528_INT_STATE_CHANGE, 3, - BD70528_INT_STATE_CHANGE_MASK), - REGMAP_IRQ_REG(BD70528_INT_BAT_OV_RES, 4, BD70528_INT_BAT_OV_RES_MASK), - REGMAP_IRQ_REG(BD70528_INT_BAT_OV_DET, 4, BD70528_INT_BAT_OV_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_DBAT_DET, 4, BD70528_INT_DBAT_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_RES, 4, - BD70528_INT_BATTSD_COLD_RES_MASK), - REGMAP_IRQ_REG(BD70528_INT_BATTSD_COLD_DET, 4, - BD70528_INT_BATTSD_COLD_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_RES, 4, - BD70528_INT_BATTSD_HOT_RES_MASK), - REGMAP_IRQ_REG(BD70528_INT_BATTSD_HOT_DET, 4, - BD70528_INT_BATTSD_HOT_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_CHG_TSD, 4, BD70528_INT_CHG_TSD_MASK), - REGMAP_IRQ_REG(BD70528_INT_BAT_RMV, 5, BD70528_INT_BAT_RMV_MASK), - REGMAP_IRQ_REG(BD70528_INT_BAT_DET, 5, BD70528_INT_BAT_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_RES, 5, - BD70528_INT_DCIN2_OV_RES_MASK), - REGMAP_IRQ_REG(BD70528_INT_DCIN2_OV_DET, 5, - BD70528_INT_DCIN2_OV_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_DCIN2_RMV, 5, BD70528_INT_DCIN2_RMV_MASK), - REGMAP_IRQ_REG(BD70528_INT_DCIN2_DET, 5, BD70528_INT_DCIN2_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_DCIN1_RMV, 5, BD70528_INT_DCIN1_RMV_MASK), - REGMAP_IRQ_REG(BD70528_INT_DCIN1_DET, 5, BD70528_INT_DCIN1_DET_MASK), - REGMAP_IRQ_REG(BD70528_INT_RTC_ALARM, 6, BD70528_INT_RTC_ALARM_MASK), - REGMAP_IRQ_REG(BD70528_INT_ELPS_TIM, 6, BD70528_INT_ELPS_TIM_MASK), - REGMAP_IRQ_REG(BD70528_INT_GPIO0, 7, BD70528_INT_GPIO0_MASK), - REGMAP_IRQ_REG(BD70528_INT_GPIO1, 7, BD70528_INT_GPIO1_MASK), - REGMAP_IRQ_REG(BD70528_INT_GPIO2, 7, BD70528_INT_GPIO2_MASK), - REGMAP_IRQ_REG(BD70528_INT_GPIO3, 7, BD70528_INT_GPIO3_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK1_DVS_OPFAIL, 8, - BD70528_INT_BUCK1_DVS_OPFAIL_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK2_DVS_OPFAIL, 8, - BD70528_INT_BUCK2_DVS_OPFAIL_MASK), - REGMAP_IRQ_REG(BD70528_INT_BUCK3_DVS_OPFAIL, 8, - BD70528_INT_BUCK3_DVS_OPFAIL_MASK), - REGMAP_IRQ_REG(BD70528_INT_LED1_VOLT_OPFAIL, 8, - BD70528_INT_LED1_VOLT_OPFAIL_MASK), - REGMAP_IRQ_REG(BD70528_INT_LED2_VOLT_OPFAIL, 8, - BD70528_INT_LED2_VOLT_OPFAIL_MASK), -}; - -static struct regmap_irq_chip bd70528_irq_chip = { - .name = "bd70528_irq", - .main_status = BD70528_REG_INT_MAIN, - .irqs = &bd70528_irqs[0], - .num_irqs = ARRAY_SIZE(bd70528_irqs), - .status_base = BD70528_REG_INT_SHDN, - .mask_base = BD70528_REG_INT_SHDN_MASK, - .ack_base = BD70528_REG_INT_SHDN, - .type_base = BD70528_REG_GPIO1_IN, - .init_ack_masked = true, - .num_regs = 9, - .num_main_regs = 1, - .num_type_reg = 4, - .sub_reg_offsets = &bd70528_sub_irq_offsets[0], - .num_main_status_bits = 8, - .irq_reg_stride = 1, -}; - -static int bd70528_i2c_probe(struct i2c_client *i2c, - const struct i2c_device_id *id) -{ - struct bd70528_data *bd70528; - struct regmap_irq_chip_data *irq_data; - int ret, i; - - if (!i2c->irq) { - dev_err(&i2c->dev, "No IRQ configured\n"); - return -EINVAL; - } - - bd70528 = devm_kzalloc(&i2c->dev, sizeof(*bd70528), GFP_KERNEL); - if (!bd70528) - return -ENOMEM; - - mutex_init(&bd70528->rtc_timer_lock); - - dev_set_drvdata(&i2c->dev, &bd70528->chip); - - bd70528->chip.regmap = devm_regmap_init_i2c(i2c, &bd70528_regmap); - if (IS_ERR(bd70528->chip.regmap)) { - dev_err(&i2c->dev, "Failed to initialize Regmap\n"); - return PTR_ERR(bd70528->chip.regmap); - } - - /* - * Disallow type setting for all IRQs by default as most of them do not - * support setting type. - */ - for (i = 0; i < ARRAY_SIZE(bd70528_irqs); i++) - bd70528_irqs[i].type.types_supported = 0; - - /* Set IRQ typesetting information for GPIO pins 0 - 3 */ - for (i = 0; i < BD70528_NUM_OF_GPIOS; i++) { - struct regmap_irq_type *type; - - type = &bd70528_irqs[BD70528_INT_GPIO0 + i].type; - type->type_reg_offset = 2 * i; - type->type_rising_val = 0x20; - type->type_falling_val = 0x10; - type->type_level_high_val = 0x40; - type->type_level_low_val = 0x50; - type->types_supported = (IRQ_TYPE_EDGE_BOTH | - IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); - } - - ret = devm_regmap_add_irq_chip(&i2c->dev, bd70528->chip.regmap, - i2c->irq, IRQF_ONESHOT, 0, - &bd70528_irq_chip, &irq_data); - if (ret) { - dev_err(&i2c->dev, "Failed to add IRQ chip\n"); - return ret; - } - dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", - bd70528_irq_chip.num_irqs); - - /* - * BD70528 IRQ controller is not touching the main mask register. - * So enable the GPIO block interrupts at main level. We can just leave - * them enabled as the IRQ controller should disable IRQs from - * sub-registers when IRQ is disabled or freed. - */ - ret = regmap_update_bits(bd70528->chip.regmap, - BD70528_REG_INT_MAIN_MASK, - BD70528_INT_GPIO_MASK, 0); - - ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, - bd70528_mfd_cells, - ARRAY_SIZE(bd70528_mfd_cells), NULL, 0, - regmap_irq_get_domain(irq_data)); - if (ret) - dev_err(&i2c->dev, "Failed to create subdevices\n"); - - return ret; -} - -static const struct of_device_id bd70528_of_match[] = { - { .compatible = "rohm,bd70528", }, - { }, -}; -MODULE_DEVICE_TABLE(of, bd70528_of_match); - -static struct i2c_driver bd70528_drv = { - .driver = { - .name = "rohm-bd70528", - .of_match_table = bd70528_of_match, - }, - .probe = &bd70528_i2c_probe, -}; - -module_i2c_driver(bd70528_drv); - -MODULE_AUTHOR("Matti Vaittinen "); -MODULE_DESCRIPTION("ROHM BD70528 Power Management IC driver"); -MODULE_LICENSE("GPL"); diff --git a/include/linux/mfd/rohm-bd70528.h b/include/linux/mfd/rohm-bd70528.h deleted file mode 100644 index 4a5966475a35..000000000000 --- a/include/linux/mfd/rohm-bd70528.h +++ /dev/null @@ -1,389 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* Copyright (C) 2018 ROHM Semiconductors */ - -#ifndef __LINUX_MFD_BD70528_H__ -#define __LINUX_MFD_BD70528_H__ - -#include -#include -#include -#include -#include - -enum { - BD70528_BUCK1, - BD70528_BUCK2, - BD70528_BUCK3, - BD70528_LDO1, - BD70528_LDO2, - BD70528_LDO3, - BD70528_LED1, - BD70528_LED2, -}; - -struct bd70528_data { - struct rohm_regmap_dev chip; - struct mutex rtc_timer_lock; -}; - -#define BD70528_BUCK_VOLTS 0x10 -#define BD70528_LDO_VOLTS 0x20 - -#define BD70528_REG_BUCK1_EN 0x0F -#define BD70528_REG_BUCK1_VOLT 0x15 -#define BD70528_REG_BUCK2_EN 0x10 -#define BD70528_REG_BUCK2_VOLT 0x16 -#define BD70528_REG_BUCK3_EN 0x11 -#define BD70528_REG_BUCK3_VOLT 0x17 -#define BD70528_REG_LDO1_EN 0x1b -#define BD70528_REG_LDO1_VOLT 0x1e -#define BD70528_REG_LDO2_EN 0x1c -#define BD70528_REG_LDO2_VOLT 0x1f -#define BD70528_REG_LDO3_EN 0x1d -#define BD70528_REG_LDO3_VOLT 0x20 -#define BD70528_REG_LED_CTRL 0x2b -#define BD70528_REG_LED_VOLT 0x29 -#define BD70528_REG_LED_EN 0x2a - -/* main irq registers */ -#define BD70528_REG_INT_MAIN 0x7E -#define BD70528_REG_INT_MAIN_MASK 0x74 - -/* 'sub irq' registers */ -#define BD70528_REG_INT_SHDN 0x7F -#define BD70528_REG_INT_PWR_FLT 0x80 -#define BD70528_REG_INT_VR_FLT 0x81 -#define BD70528_REG_INT_MISC 0x82 -#define BD70528_REG_INT_BAT1 0x83 -#define BD70528_REG_INT_BAT2 0x84 -#define BD70528_REG_INT_RTC 0x85 -#define BD70528_REG_INT_GPIO 0x86 -#define BD70528_REG_INT_OP_FAIL 0x87 - -#define BD70528_REG_INT_SHDN_MASK 0x75 -#define BD70528_REG_INT_PWR_FLT_MASK 0x76 -#define BD70528_REG_INT_VR_FLT_MASK 0x77 -#define BD70528_REG_INT_MISC_MASK 0x78 -#define BD70528_REG_INT_BAT1_MASK 0x79 -#define BD70528_REG_INT_BAT2_MASK 0x7a -#define BD70528_REG_INT_RTC_MASK 0x7b -#define BD70528_REG_INT_GPIO_MASK 0x7c -#define BD70528_REG_INT_OP_FAIL_MASK 0x7d - -/* Reset related 'magic' registers */ -#define BD70528_REG_SHIPMODE 0x03 -#define BD70528_REG_HWRESET 0x04 -#define BD70528_REG_WARMRESET 0x05 -#define BD70528_REG_STANDBY 0x06 - -/* GPIO registers */ -#define BD70528_REG_GPIO_STATE 0x8F - -#define BD70528_REG_GPIO1_IN 0x4d -#define BD70528_REG_GPIO2_IN 0x4f -#define BD70528_REG_GPIO3_IN 0x51 -#define BD70528_REG_GPIO4_IN 0x53 -#define BD70528_REG_GPIO1_OUT 0x4e -#define BD70528_REG_GPIO2_OUT 0x50 -#define BD70528_REG_GPIO3_OUT 0x52 -#define BD70528_REG_GPIO4_OUT 0x54 - -/* RTC */ - -#define BD70528_REG_RTC_COUNT_H 0x2d -#define BD70528_REG_RTC_COUNT_L 0x2e -#define BD70528_REG_RTC_SEC 0x2f -#define BD70528_REG_RTC_MINUTE 0x30 -#define BD70528_REG_RTC_HOUR 0x31 -#define BD70528_REG_RTC_WEEK 0x32 -#define BD70528_REG_RTC_DAY 0x33 -#define BD70528_REG_RTC_MONTH 0x34 -#define BD70528_REG_RTC_YEAR 0x35 - -#define BD70528_REG_RTC_ALM_SEC 0x36 -#define BD70528_REG_RTC_ALM_START BD70528_REG_RTC_ALM_SEC -#define BD70528_REG_RTC_ALM_MINUTE 0x37 -#define BD70528_REG_RTC_ALM_HOUR 0x38 -#define BD70528_REG_RTC_ALM_WEEK 0x39 -#define BD70528_REG_RTC_ALM_DAY 0x3a -#define BD70528_REG_RTC_ALM_MONTH 0x3b -#define BD70528_REG_RTC_ALM_YEAR 0x3c -#define BD70528_REG_RTC_ALM_MASK 0x3d -#define BD70528_REG_RTC_ALM_REPEAT 0x3e -#define BD70528_REG_RTC_START BD70528_REG_RTC_SEC - -#define BD70528_REG_RTC_WAKE_SEC 0x43 -#define BD70528_REG_RTC_WAKE_START BD70528_REG_RTC_WAKE_SEC -#define BD70528_REG_RTC_WAKE_MIN 0x44 -#define BD70528_REG_RTC_WAKE_HOUR 0x45 -#define BD70528_REG_RTC_WAKE_CTRL 0x46 - -#define BD70528_REG_ELAPSED_TIMER_EN 0x42 -#define BD70528_REG_WAKE_EN 0x46 - -/* WDT registers */ -#define BD70528_REG_WDT_CTRL 0x4A -#define BD70528_REG_WDT_HOUR 0x49 -#define BD70528_REG_WDT_MINUTE 0x48 -#define BD70528_REG_WDT_SEC 0x47 - -/* Charger / Battery */ -#define BD70528_REG_CHG_CURR_STAT 0x59 -#define BD70528_REG_CHG_BAT_STAT 0x57 -#define BD70528_REG_CHG_BAT_TEMP 0x58 -#define BD70528_REG_CHG_IN_STAT 0x56 -#define BD70528_REG_CHG_DCIN_ILIM 0x5d -#define BD70528_REG_CHG_CHG_CURR_WARM 0x61 -#define BD70528_REG_CHG_CHG_CURR_COLD 0x62 - -/* Masks for main IRQ register bits */ -enum { - BD70528_INT_SHDN, -#define BD70528_INT_SHDN_MASK BIT(BD70528_INT_SHDN) - BD70528_INT_PWR_FLT, -#define BD70528_INT_PWR_FLT_MASK BIT(BD70528_INT_PWR_FLT) - BD70528_INT_VR_FLT, -#define BD70528_INT_VR_FLT_MASK BIT(BD70528_INT_VR_FLT) - BD70528_INT_MISC, -#define BD70528_INT_MISC_MASK BIT(BD70528_INT_MISC) - BD70528_INT_BAT1, -#define BD70528_INT_BAT1_MASK BIT(BD70528_INT_BAT1) - BD70528_INT_RTC, -#define BD70528_INT_RTC_MASK BIT(BD70528_INT_RTC) - BD70528_INT_GPIO, -#define BD70528_INT_GPIO_MASK BIT(BD70528_INT_GPIO) - BD70528_INT_OP_FAIL, -#define BD70528_INT_OP_FAIL_MASK BIT(BD70528_INT_OP_FAIL) -}; - -/* IRQs */ -enum { - /* Shutdown register IRQs */ - BD70528_INT_LONGPUSH, - BD70528_INT_WDT, - BD70528_INT_HWRESET, - BD70528_INT_RSTB_FAULT, - BD70528_INT_VBAT_UVLO, - BD70528_INT_TSD, - BD70528_INT_RSTIN, - /* Power failure register IRQs */ - BD70528_INT_BUCK1_FAULT, - BD70528_INT_BUCK2_FAULT, - BD70528_INT_BUCK3_FAULT, - BD70528_INT_LDO1_FAULT, - BD70528_INT_LDO2_FAULT, - BD70528_INT_LDO3_FAULT, - BD70528_INT_LED1_FAULT, - BD70528_INT_LED2_FAULT, - /* VR FAULT register IRQs */ - BD70528_INT_BUCK1_OCP, - BD70528_INT_BUCK2_OCP, - BD70528_INT_BUCK3_OCP, - BD70528_INT_LED1_OCP, - BD70528_INT_LED2_OCP, - BD70528_INT_BUCK1_FULLON, - BD70528_INT_BUCK2_FULLON, - /* PMU register interrupts */ - BD70528_INT_SHORTPUSH, - BD70528_INT_AUTO_WAKEUP, - BD70528_INT_STATE_CHANGE, - /* Charger 1 register IRQs */ - BD70528_INT_BAT_OV_RES, - BD70528_INT_BAT_OV_DET, - BD70528_INT_DBAT_DET, - BD70528_INT_BATTSD_COLD_RES, - BD70528_INT_BATTSD_COLD_DET, - BD70528_INT_BATTSD_HOT_RES, - BD70528_INT_BATTSD_HOT_DET, - BD70528_INT_CHG_TSD, - /* Charger 2 register IRQs */ - BD70528_INT_BAT_RMV, - BD70528_INT_BAT_DET, - BD70528_INT_DCIN2_OV_RES, - BD70528_INT_DCIN2_OV_DET, - BD70528_INT_DCIN2_RMV, - BD70528_INT_DCIN2_DET, - BD70528_INT_DCIN1_RMV, - BD70528_INT_DCIN1_DET, - /* RTC register IRQs */ - BD70528_INT_RTC_ALARM, - BD70528_INT_ELPS_TIM, - /* GPIO register IRQs */ - BD70528_INT_GPIO0, - BD70528_INT_GPIO1, - BD70528_INT_GPIO2, - BD70528_INT_GPIO3, - /* Invalid operation register IRQs */ - BD70528_INT_BUCK1_DVS_OPFAIL, - BD70528_INT_BUCK2_DVS_OPFAIL, - BD70528_INT_BUCK3_DVS_OPFAIL, - BD70528_INT_LED1_VOLT_OPFAIL, - BD70528_INT_LED2_VOLT_OPFAIL, -}; - -/* Masks */ -#define BD70528_INT_LONGPUSH_MASK 0x1 -#define BD70528_INT_WDT_MASK 0x2 -#define BD70528_INT_HWRESET_MASK 0x4 -#define BD70528_INT_RSTB_FAULT_MASK 0x8 -#define BD70528_INT_VBAT_UVLO_MASK 0x10 -#define BD70528_INT_TSD_MASK 0x20 -#define BD70528_INT_RSTIN_MASK 0x40 - -#define BD70528_INT_BUCK1_FAULT_MASK 0x1 -#define BD70528_INT_BUCK2_FAULT_MASK 0x2 -#define BD70528_INT_BUCK3_FAULT_MASK 0x4 -#define BD70528_INT_LDO1_FAULT_MASK 0x8 -#define BD70528_INT_LDO2_FAULT_MASK 0x10 -#define BD70528_INT_LDO3_FAULT_MASK 0x20 -#define BD70528_INT_LED1_FAULT_MASK 0x40 -#define BD70528_INT_LED2_FAULT_MASK 0x80 - -#define BD70528_INT_BUCK1_OCP_MASK 0x1 -#define BD70528_INT_BUCK2_OCP_MASK 0x2 -#define BD70528_INT_BUCK3_OCP_MASK 0x4 -#define BD70528_INT_LED1_OCP_MASK 0x8 -#define BD70528_INT_LED2_OCP_MASK 0x10 -#define BD70528_INT_BUCK1_FULLON_MASK 0x20 -#define BD70528_INT_BUCK2_FULLON_MASK 0x40 - -#define BD70528_INT_SHORTPUSH_MASK 0x1 -#define BD70528_INT_AUTO_WAKEUP_MASK 0x2 -#define BD70528_INT_STATE_CHANGE_MASK 0x10 - -#define BD70528_INT_BAT_OV_RES_MASK 0x1 -#define BD70528_INT_BAT_OV_DET_MASK 0x2 -#define BD70528_INT_DBAT_DET_MASK 0x4 -#define BD70528_INT_BATTSD_COLD_RES_MASK 0x8 -#define BD70528_INT_BATTSD_COLD_DET_MASK 0x10 -#define BD70528_INT_BATTSD_HOT_RES_MASK 0x20 -#define BD70528_INT_BATTSD_HOT_DET_MASK 0x40 -#define BD70528_INT_CHG_TSD_MASK 0x80 - -#define BD70528_INT_BAT_RMV_MASK 0x1 -#define BD70528_INT_BAT_DET_MASK 0x2 -#define BD70528_INT_DCIN2_OV_RES_MASK 0x4 -#define BD70528_INT_DCIN2_OV_DET_MASK 0x8 -#define BD70528_INT_DCIN2_RMV_MASK 0x10 -#define BD70528_INT_DCIN2_DET_MASK 0x20 -#define BD70528_INT_DCIN1_RMV_MASK 0x40 -#define BD70528_INT_DCIN1_DET_MASK 0x80 - -#define BD70528_INT_RTC_ALARM_MASK 0x1 -#define BD70528_INT_ELPS_TIM_MASK 0x2 - -#define BD70528_INT_GPIO0_MASK 0x1 -#define BD70528_INT_GPIO1_MASK 0x2 -#define BD70528_INT_GPIO2_MASK 0x4 -#define BD70528_INT_GPIO3_MASK 0x8 - -#define BD70528_INT_BUCK1_DVS_OPFAIL_MASK 0x1 -#define BD70528_INT_BUCK2_DVS_OPFAIL_MASK 0x2 -#define BD70528_INT_BUCK3_DVS_OPFAIL_MASK 0x4 -#define BD70528_INT_LED1_VOLT_OPFAIL_MASK 0x10 -#define BD70528_INT_LED2_VOLT_OPFAIL_MASK 0x20 - -#define BD70528_DEBOUNCE_MASK 0x3 - -#define BD70528_DEBOUNCE_DISABLE 0 -#define BD70528_DEBOUNCE_15MS 1 -#define BD70528_DEBOUNCE_30MS 2 -#define BD70528_DEBOUNCE_50MS 3 - -#define BD70528_GPIO_DRIVE_MASK 0x2 -#define BD70528_GPIO_PUSH_PULL 0x0 -#define BD70528_GPIO_OPEN_DRAIN 0x2 - -#define BD70528_GPIO_OUT_EN_MASK 0x80 -#define BD70528_GPIO_OUT_ENABLE 0x80 -#define BD70528_GPIO_OUT_DISABLE 0x0 - -#define BD70528_GPIO_OUT_HI 0x1 -#define BD70528_GPIO_OUT_LO 0x0 -#define BD70528_GPIO_OUT_MASK 0x1 - -#define BD70528_GPIO_IN_STATE_BASE 1 - -/* RTC masks to mask out reserved bits */ - -#define BD70528_MASK_ELAPSED_TIMER_EN 0x1 -/* Mask second, min and hour fields - * HW would support ALM irq for over 24h - * (by setting day, month and year too) - * but as we wish to keep this same as for - * wake-up we limit ALM to 24H and only - * unmask sec, min and hour - */ -#define BD70528_MASK_WAKE_EN 0x1 - -/* WDT masks */ -#define BD70528_MASK_WDT_EN 0x1 -#define BD70528_MASK_WDT_HOUR 0x1 -#define BD70528_MASK_WDT_MINUTE 0x7f -#define BD70528_MASK_WDT_SEC 0x7f - -#define BD70528_WDT_STATE_BIT 0x1 -#define BD70528_ELAPSED_STATE_BIT 0x2 -#define BD70528_WAKE_STATE_BIT 0x4 - -/* Charger masks */ -#define BD70528_MASK_CHG_STAT 0x7f -#define BD70528_MASK_CHG_BAT_TIMER 0x20 -#define BD70528_MASK_CHG_BAT_OVERVOLT 0x10 -#define BD70528_MASK_CHG_BAT_DETECT 0x1 -#define BD70528_MASK_CHG_DCIN1_UVLO 0x1 -#define BD70528_MASK_CHG_DCIN_ILIM 0x3f -#define BD70528_MASK_CHG_CHG_CURR 0x1f -#define BD70528_MASK_CHG_TRICKLE_CURR 0x10 - -/* - * Note, external battery register is the lonely rider at - * address 0xc5. See how to stuff that in the regmap - */ -#define BD70528_MAX_REGISTER 0x94 - -/* Buck control masks */ -#define BD70528_MASK_RUN_EN 0x4 -#define BD70528_MASK_STBY_EN 0x2 -#define BD70528_MASK_IDLE_EN 0x1 -#define BD70528_MASK_LED1_EN 0x1 -#define BD70528_MASK_LED2_EN 0x10 - -#define BD70528_MASK_BUCK_VOLT 0xf -#define BD70528_MASK_LDO_VOLT 0x1f -#define BD70528_MASK_LED1_VOLT 0x1 -#define BD70528_MASK_LED2_VOLT 0x10 - -/* Misc irq masks */ -#define BD70528_INT_MASK_SHORT_PUSH 1 -#define BD70528_INT_MASK_AUTO_WAKE 2 -#define BD70528_INT_MASK_POWER_STATE 4 - -#define BD70528_MASK_BUCK_RAMP 0x10 -#define BD70528_SIFT_BUCK_RAMP 4 - -#if IS_ENABLED(CONFIG_BD70528_WATCHDOG) - -int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, int *old_state); -void bd70528_wdt_lock(struct rohm_regmap_dev *data); -void bd70528_wdt_unlock(struct rohm_regmap_dev *data); - -#else /* CONFIG_BD70528_WATCHDOG */ - -static inline int bd70528_wdt_set(struct rohm_regmap_dev *data, int enable, - int *old_state) -{ - return 0; -} - -static inline void bd70528_wdt_lock(struct rohm_regmap_dev *data) -{ -} - -static inline void bd70528_wdt_unlock(struct rohm_regmap_dev *data) -{ -} - -#endif /* CONFIG_BD70528_WATCHDOG */ - -#endif /* __LINUX_MFD_BD70528_H__ */ diff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h index 35b392a0d73a..8fb763a2265a 100644 --- a/include/linux/mfd/rohm-generic.h +++ b/include/linux/mfd/rohm-generic.h @@ -12,7 +12,6 @@ enum rohm_chip_type { ROHM_CHIP_TYPE_BD9573, ROHM_CHIP_TYPE_BD9574, ROHM_CHIP_TYPE_BD9576, - ROHM_CHIP_TYPE_BD70528, ROHM_CHIP_TYPE_BD71815, ROHM_CHIP_TYPE_BD71828, ROHM_CHIP_TYPE_BD71837, -- cgit v1.2.3 From 8b2051a1defe26bd3c83595521e000405fda0835 Mon Sep 17 00:00:00 2001 From: Ed Schaller Date: Tue, 23 Nov 2021 12:01:14 -0600 Subject: mfd: intel-lpss: Add Intel Lakefield PCH PCI IDs Add new IDs of the Intel Lakefield chip to the list of supported devices. Signed-off-by: Ed Schaller Reviewed-by: Andy Shevchenko Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211123180114.GA4747@darkmist.net --- drivers/mfd/intel-lpss-pci.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index a872b4485eac..9700e5acd0cd 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -359,7 +359,14 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { /* LKF */ { PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info }, { PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x98aa), (kernel_ulong_t)&bxt_info }, + { PCI_VDEVICE(INTEL, 0x98c5), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98c6), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x98c7), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x98e8), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98e9), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98ea), (kernel_ulong_t)&bxt_i2c_info }, + { PCI_VDEVICE(INTEL, 0x98eb), (kernel_ulong_t)&bxt_i2c_info }, /* SPT-LP */ { PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info }, { PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info }, -- cgit v1.2.3 From 8c0fad75dcaa650e3f3145a2c35847bc6a65cb7f Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 28 Oct 2021 16:51:37 +0300 Subject: mfd: atmel-flexcom: Remove #ifdef CONFIG_PM_SLEEP Remove compilation flag and use __maybe_unused and pm_ptr instead. Signed-off-by: Claudiu Beznea Acked-by: Nicolas Ferre Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211028135138.3481166-2-claudiu.beznea@microchip.com --- drivers/mfd/atmel-flexcom.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index d2f5c073fdf3..962f66dc8813 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -87,8 +87,7 @@ static const struct of_device_id atmel_flexcom_of_match[] = { }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match); -#ifdef CONFIG_PM_SLEEP -static int atmel_flexcom_resume(struct device *dev) +static int __maybe_unused atmel_flexcom_resume(struct device *dev) { struct atmel_flexcom *ddata = dev_get_drvdata(dev); int err; @@ -105,7 +104,6 @@ static int atmel_flexcom_resume(struct device *dev) return 0; } -#endif static SIMPLE_DEV_PM_OPS(atmel_flexcom_pm_ops, NULL, atmel_flexcom_resume); @@ -114,7 +112,7 @@ static struct platform_driver atmel_flexcom_driver = { .probe = atmel_flexcom_probe, .driver = { .name = "atmel_flexcom", - .pm = &atmel_flexcom_pm_ops, + .pm = pm_ptr(&atmel_flexcom_pm_ops), .of_match_table = atmel_flexcom_of_match, }, }; -- cgit v1.2.3 From 5d051cf94fd5834a1513aa77e542c49fd973988a Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 28 Oct 2021 16:51:38 +0300 Subject: mfd: atmel-flexcom: Use .resume_noirq Flexcom IP embeds 3 other IPs: usart, i2c, spi and selects the operation mode (usart, i2c, spi) via mode register (FLEX_MR). On i2c bus there might be connected critical devices (like PMIC) which on suspend/resume should be suspended/resumed at the end/beginning. i2c uses .suspend_noirq/.resume_noirq for this kind of purposes. Align flexcom to use .resume_noirq as it should be resumed before the embedded IPs. Otherwise the embedded devices might behave badly. Fixes: 7fdec11015c3 ("atmel_flexcom: Support resuming after a chip reset") Signed-off-by: Claudiu Beznea Tested-by: Codrin Ciubotariu Acked-by: Nicolas Ferre Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211028135138.3481166-3-claudiu.beznea@microchip.com --- drivers/mfd/atmel-flexcom.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c index 962f66dc8813..559eb4d352b6 100644 --- a/drivers/mfd/atmel-flexcom.c +++ b/drivers/mfd/atmel-flexcom.c @@ -87,7 +87,7 @@ static const struct of_device_id atmel_flexcom_of_match[] = { }; MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match); -static int __maybe_unused atmel_flexcom_resume(struct device *dev) +static int __maybe_unused atmel_flexcom_resume_noirq(struct device *dev) { struct atmel_flexcom *ddata = dev_get_drvdata(dev); int err; @@ -105,8 +105,9 @@ static int __maybe_unused atmel_flexcom_resume(struct device *dev) return 0; } -static SIMPLE_DEV_PM_OPS(atmel_flexcom_pm_ops, NULL, - atmel_flexcom_resume); +static const struct dev_pm_ops atmel_flexcom_pm_ops = { + .resume_noirq = atmel_flexcom_resume_noirq, +}; static struct platform_driver atmel_flexcom_driver = { .probe = atmel_flexcom_probe, -- cgit v1.2.3 From 786c6f140bb67ba315962b4742326e93e8b3207c Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Wed, 27 Oct 2021 10:21:55 +0200 Subject: mfd: stmpe: Support disabling sub-functions Add support of sub-functions disabling. It allows one to define an stmpe sub-function device in devicetree, but keep it disabled. Signed-off-by: Oleksandr Suvorov Signed-off-by: Francesco Dolcini Reviewed-by: Linus Walleij Reviewed-by: Marcel Ziswiler Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211027082155.206449-1-francesco.dolcini@toradex.com --- drivers/mfd/stmpe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index e928df95e316..aeb9ea55f97d 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -1361,7 +1361,7 @@ static void stmpe_of_probe(struct stmpe_platform_data *pdata, pdata->autosleep = (pdata->autosleep_timeout) ? true : false; - for_each_child_of_node(np, child) { + for_each_available_child_of_node(np, child) { if (of_node_name_eq(child, "stmpe_gpio")) { pdata->blocks |= STMPE_BLOCK_GPIO; } else if (of_node_name_eq(child, "stmpe_keypad")) { -- cgit v1.2.3 From c9e143084d1a602f829115612e1ec79df3727c8b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 1 Nov 2021 21:00:08 +0200 Subject: mfd: intel-lpss: Fix too early PM enablement in the ACPI ->probe() The runtime PM callback may be called as soon as the runtime PM facility is enabled and activated. It means that ->suspend() may be called before we finish probing the device in the ACPI case. Hence, NULL pointer dereference: intel-lpss INT34BA:00: IRQ index 0 not found BUG: kernel NULL pointer dereference, address: 0000000000000030 ... Workqueue: pm pm_runtime_work RIP: 0010:intel_lpss_suspend+0xb/0x40 [intel_lpss] To fix this, first try to register the device and only after that enable runtime PM facility. Fixes: 4b45efe85263 ("mfd: Add support for Intel Sunrisepoint LPSS devices") Reported-by: Orlando Chamberlain Reported-by: Aditya Garg Signed-off-by: Andy Shevchenko Tested-by: Aditya Garg Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211101190008.86473-1-andriy.shevchenko@linux.intel.com --- drivers/mfd/intel-lpss-acpi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c index 3f1d976eb67c..f2ea6540a01e 100644 --- a/drivers/mfd/intel-lpss-acpi.c +++ b/drivers/mfd/intel-lpss-acpi.c @@ -136,6 +136,7 @@ static int intel_lpss_acpi_probe(struct platform_device *pdev) { struct intel_lpss_platform_info *info; const struct acpi_device_id *id; + int ret; id = acpi_match_device(intel_lpss_acpi_ids, &pdev->dev); if (!id) @@ -149,10 +150,14 @@ static int intel_lpss_acpi_probe(struct platform_device *pdev) info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); info->irq = platform_get_irq(pdev, 0); + ret = intel_lpss_probe(&pdev->dev, info); + if (ret) + return ret; + pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); - return intel_lpss_probe(&pdev->dev, info); + return 0; } static int intel_lpss_acpi_remove(struct platform_device *pdev) -- cgit v1.2.3 From 9651cf2cb14726c785240e9dc01b274a68e9959e Mon Sep 17 00:00:00 2001 From: Orlando Chamberlain Date: Wed, 24 Nov 2021 09:19:44 +0000 Subject: mfd: intel-lpss-pci: Fix clock speed for 38a8 UART This device is found in the MacBookPro16,2, and as the MacBookPro16,1 is from the same generation of MacBooks and has a UART with bxt_uart_info, it was incorrectly assumed that the MacBookPro16,2's UART would have the same info. This led to the wrong clock speed being used, and the Bluetooth controller exposed by the UART receiving and sending random data, which was incorrectly assumed to be an issue with the Bluetooth stuff, not an error with the UART side of things. Changing the info to spt_uart_info changes the clock speed and makes it send and receive data correctly. Fixes: ddb1ada416fd ("mfd: intel-lpss: Add support for MacBookPro16,2 ICL-N UART") Signed-off-by: Orlando Chamberlain Reviewed-by: Andy Shevchenko Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211124091846.11114-1-redecorating@protonmail.com --- drivers/mfd/intel-lpss-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index 9700e5acd0cd..a59aa147959b 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -254,7 +254,7 @@ static const struct pci_device_id intel_lpss_pci_ids[] = { { PCI_VDEVICE(INTEL, 0x34eb), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x34fb), (kernel_ulong_t)&spt_info }, /* ICL-N */ - { PCI_VDEVICE(INTEL, 0x38a8), (kernel_ulong_t)&bxt_uart_info }, + { PCI_VDEVICE(INTEL, 0x38a8), (kernel_ulong_t)&spt_uart_info }, /* TGL-H */ { PCI_VDEVICE(INTEL, 0x43a7), (kernel_ulong_t)&bxt_uart_info }, { PCI_VDEVICE(INTEL, 0x43a8), (kernel_ulong_t)&bxt_uart_info }, -- cgit v1.2.3 From 5c6f0f456351f5ca7d3b1a82060821eac4a7dc5c Mon Sep 17 00:00:00 2001 From: Andrej Picej Date: Wed, 24 Nov 2021 07:51:19 +0100 Subject: mfd: da9062: Support SMBus and I2C mode Enable the I2C bus mode if I2C_FUNC_I2C is set. Based on da6093 commit: "586478bfc9f7 mfd: da9063: Support SMBus and I2C mode" Signed-off-by: Andrej Picej Reviewed-by: Adam Thomson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211124065119.2514872-1-andrej.picej@norik.com --- drivers/mfd/da9062-core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/da9062-core.c b/drivers/mfd/da9062-core.c index 01f8e10dfa55..2774b2cbaea6 100644 --- a/drivers/mfd/da9062-core.c +++ b/drivers/mfd/da9062-core.c @@ -556,6 +556,7 @@ static const struct regmap_range da9062_aa_writeable_ranges[] = { regmap_reg_range(DA9062AA_VBUCK3_B, DA9062AA_VBUCK3_B), regmap_reg_range(DA9062AA_VLDO1_B, DA9062AA_VLDO4_B), regmap_reg_range(DA9062AA_BBAT_CONT, DA9062AA_BBAT_CONT), + regmap_reg_range(DA9062AA_CONFIG_J, DA9062AA_CONFIG_J), regmap_reg_range(DA9062AA_GP_ID_0, DA9062AA_GP_ID_19), }; @@ -674,6 +675,17 @@ static int da9062_i2c_probe(struct i2c_client *i2c, return ret; } + /* If SMBus is not available and only I2C is possible, enter I2C mode */ + if (i2c_check_functionality(i2c->adapter, I2C_FUNC_I2C)) { + dev_info(chip->dev, "Entering I2C mode!\n"); + ret = regmap_clear_bits(chip->regmap, DA9062AA_CONFIG_J, + DA9062AA_TWOWIRE_TO_MASK); + if (ret < 0) { + dev_err(chip->dev, "Failed to set Two-Wire Bus Mode.\n"); + return ret; + } + } + ret = da9062_clear_fault_log(chip); if (ret < 0) dev_warn(chip->dev, "Cannot clear fault log\n"); -- cgit v1.2.3 From 54d4c88b37595173d7039ea9a57913edfee48f47 Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 29 Nov 2021 14:23:56 +0100 Subject: mfd: Kconfig: Change INTEL_SOC_PMIC_CHTDC_TI to bool The INTEL_SOC_PMIC_CHTDC_TI should be initialized early, before loading the fbcon driver, as otherwise the i915 driver will fail to configure pwm: [ 13.674287] fb0: switching to inteldrmfb from EFI VGA [ 13.682380] Console: switching to colour dummy device 80x25 [ 13.682468] i915 0000:00:02.0: vgaarb: deactivate vga console [ 13.682686] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). [ 13.685773] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem [ 13.686219] i915 0000:00:02.0: [drm] *ERROR* Failed to configure the pwm chip [ 13.699572] [drm] Initialized i915 1.6.0 20200313 for 0000:00:02.0 on minor 0 [ 13.739044] fbcon: i915drmfb (fb0) is primary device [ 14.037792] intel_soc_pmic_exec_mipi_pmic_seq_element: No PMIC registered ... [ 24.621403] intel_pmic_install_opregion_handler: Ask to register OpRegion for bus ID=PMI2, HID=INT33F5 [ 24.630540] intel_pmic_install_opregion_handler: OpRegion registered (some extra debug printk's were added to the above) As suggested by Hans, this patch also addresses an issue with the dependencies, as, for this driver to be a bool, it also need the I2C core and the I2C_DESIGNWARE driver to be builtin. Suggested-by: Hans de Goede Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Hans de Goede Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/86f546b3233fd799b0c39b83afc521440ebfe004.1638192232.git.mchehab+huawei@kernel.org --- drivers/mfd/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 34c7d9d6b580..a21cbdf89477 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -634,7 +634,7 @@ config INTEL_SOC_PMIC_CHTWC config INTEL_SOC_PMIC_CHTDC_TI tristate "Support for Intel Cherry Trail Dollar Cove TI PMIC" depends on GPIOLIB - depends on I2C + depends on I2C=y && I2C_DESIGNWARE_PLATFORM=y depends on ACPI depends on X86 select MFD_CORE @@ -644,6 +644,10 @@ config INTEL_SOC_PMIC_CHTDC_TI Select this option for supporting Dollar Cove (TI version) PMIC device that is found on some Intel Cherry Trail systems. + This option is a bool as it provides an ACPI OpRegion which must be + available before any devices using it are probed. This option also + needs the designware-i2c driver to be builtin for the same reason. + config INTEL_SOC_PMIC_MRFLD tristate "Support for Intel Merrifield Basin Cove PMIC" depends on GPIOLIB -- cgit v1.2.3 From e6b142060b24014bfcf86ae5b1facc5e99e84176 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 3 Dec 2021 12:51:08 +0100 Subject: mfd: intel-lpss: Fix I2C4 not being available on the Microsoft Surface Go & Go 2 Many DSDTs for Kaby Lake and Kaby Lake Refresh models contain a _SB.PCI0.GEXP ACPI Device node describing an I2C attached PCA953x GPIO expander. This seems to be something which is copy and pasted from the DSDT from some reference design since this ACPI Device is present even on models where no such GPIO expander is used at all, such as on the Microsoft Surface Go & Go 2. This ACPI Device is a problem because it contains a SystemMemory OperationRegion which covers the MMIO for the I2C4 I2C controller. This causes the MFD cell for the I2C4 controller to not be instantiated due to a resource conflict, requiring the use of acpi_enforce_resources=lax to work around this. I have done an extensive analysis of all the ACPI tables on the Microsoft Surface Go and the _SB.PCI0.GEXP ACPI Device's methods are not used by any code in the ACPI tables, neither are any of them directly called by any Linux kernel code. This is unsurprising since running i2cdetect on the I2C4 bus shows that there is no GPIO expander chip present on these devices at all. This commit adds a PCI subsystem vendor:device table listing PCI devices where it is known to be safe to ignore resource conflicts with ACPI declared SystemMemory regions. This makes the I2C4 bus work out of the box on the Microsoft Surface Go & Go 2, which is necessary for the cameras on these devices to work. Signed-off-by: Hans de Goede Reviewed-by: Laurent Pinchart Reviewed-by: Andy Shevchenko Acked-by: Mika Westerberg Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211203115108.89661-1-hdegoede@redhat.com --- drivers/mfd/intel-lpss-pci.c | 12 ++++++++++++ drivers/mfd/intel-lpss.c | 1 + drivers/mfd/intel-lpss.h | 1 + 3 files changed, 14 insertions(+) (limited to 'drivers') diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c index a59aa147959b..5513fae6be92 100644 --- a/drivers/mfd/intel-lpss-pci.c +++ b/drivers/mfd/intel-lpss-pci.c @@ -17,6 +17,15 @@ #include "intel-lpss.h" +/* Some DSDTs have an unused GEXP ACPI device conflicting with I2C4 resources */ +static const struct pci_device_id ignore_resource_conflicts_ids[] = { + /* Microsoft Surface Go (version 1) I2C4 */ + { PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1182), }, + /* Microsoft Surface Go 2 I2C4 */ + { PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, 0x9d64, 0x152d, 0x1237), }, + { } +}; + static int intel_lpss_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -35,6 +44,9 @@ static int intel_lpss_pci_probe(struct pci_dev *pdev, info->mem = &pdev->resource[0]; info->irq = pdev->irq; + if (pci_match_id(ignore_resource_conflicts_ids, pdev)) + info->ignore_resource_conflicts = true; + pdev->d3cold_delay = 0; /* Probably it is enough to set this for iDMA capable devices only */ diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c index 0e15afc39f54..cfbee2cfba6b 100644 --- a/drivers/mfd/intel-lpss.c +++ b/drivers/mfd/intel-lpss.c @@ -401,6 +401,7 @@ int intel_lpss_probe(struct device *dev, return ret; lpss->cell->swnode = info->swnode; + lpss->cell->ignore_resource_conflicts = info->ignore_resource_conflicts; intel_lpss_init_dev(lpss); diff --git a/drivers/mfd/intel-lpss.h b/drivers/mfd/intel-lpss.h index 22dbc4aed793..062ce95b68b9 100644 --- a/drivers/mfd/intel-lpss.h +++ b/drivers/mfd/intel-lpss.h @@ -19,6 +19,7 @@ struct software_node; struct intel_lpss_platform_info { struct resource *mem; + bool ignore_resource_conflicts; int irq; unsigned long clk_rate; const char *clk_con_id; -- cgit v1.2.3 From 5b78223f55a0f516a1639dbe11cd4324d4aaee20 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 6 Dec 2021 18:48:06 +0100 Subject: mfd: intel_soc_pmic: Use CPU-id check instead of _HRV check to differentiate variants The Intel Crystal Cove PMIC has 2 different variants, one for use with Bay Trail (BYT) SoCs and one for use with Cherry Trail (CHT) SoCs. So far we have been using an ACPI _HRV check to differentiate between the 2, but at least on the Microsoft Surface 3, which is a CHT device, the wrong _HRV value is reported by ACPI. So instead switch to a CPU-ID check which prevents us from relying on the possibly wrong ACPI _HRV value. Signed-off-by: Hans de Goede Reported-by: Tsuchiya Yuto Reviewed-by: Andy Shevchenko Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211206174806.197772-2-hdegoede@redhat.com --- drivers/mfd/intel_soc_pmic_core.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c index ddd64f9e3341..47cb7f00dfcf 100644 --- a/drivers/mfd/intel_soc_pmic_core.c +++ b/drivers/mfd/intel_soc_pmic_core.c @@ -14,15 +14,12 @@ #include #include #include +#include #include #include #include "intel_soc_pmic_core.h" -/* Crystal Cove PMIC shares same ACPI ID between different platforms */ -#define BYT_CRC_HRV 2 -#define CHT_CRC_HRV 3 - /* PWM consumed by the Intel GFX */ static struct pwm_lookup crc_pwm_lookup[] = { PWM_LOOKUP("crystal_cove_pwm", 0, "0000:00:02.0", "pwm_pmic_backlight", 0, PWM_POLARITY_NORMAL), @@ -34,31 +31,12 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c, struct device *dev = &i2c->dev; struct intel_soc_pmic_config *config; struct intel_soc_pmic *pmic; - unsigned long long hrv; - acpi_status status; int ret; - /* - * There are 2 different Crystal Cove PMICs a Bay Trail and Cherry - * Trail version, use _HRV to differentiate between the 2. - */ - status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv); - if (ACPI_FAILURE(status)) { - dev_err(dev, "Failed to get PMIC hardware revision\n"); - return -ENODEV; - } - - switch (hrv) { - case BYT_CRC_HRV: + if (soc_intel_is_byt()) config = &intel_soc_pmic_config_byt_crc; - break; - case CHT_CRC_HRV: + else config = &intel_soc_pmic_config_cht_crc; - break; - default: - dev_warn(dev, "Unknown hardware rev %llu, assuming BYT\n", hrv); - config = &intel_soc_pmic_config_byt_crc; - } pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) -- cgit v1.2.3 From 7620ad0bdfac1efff4a1228cd36ae62a9d8206b0 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 24 Nov 2021 22:01:04 +0300 Subject: mfd: tps65910: Set PWR_OFF bit during driver probe The PWR_OFF bit needs to be set in order to power off properly, without hanging PMIC. This bit needs to be set early in order to allow thermal protection of NVIDIA Terga SoCs to power off hardware properly, otherwise a battery re-plug may be needed on some devices to recover after the hang. Cc: Signed-off-by: Dmitry Osipenko Tested-by: Svyatoslav Ryhel # ASUS TF201 Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20211124190104.23554-1-digetx@gmail.com --- drivers/mfd/tps65910.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/mfd/tps65910.c b/drivers/mfd/tps65910.c index 6e105cca27d4..67e2707af4bc 100644 --- a/drivers/mfd/tps65910.c +++ b/drivers/mfd/tps65910.c @@ -436,15 +436,6 @@ static void tps65910_power_off(void) tps65910 = dev_get_drvdata(&tps65910_i2c_client->dev); - /* - * The PWR_OFF bit needs to be set separately, before transitioning - * to the OFF state. It enables the "sequential" power-off mode on - * TPS65911, it's a NO-OP on TPS65910. - */ - if (regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL, - DEVCTRL_PWR_OFF_MASK) < 0) - return; - regmap_update_bits(tps65910->regmap, TPS65910_DEVCTRL, DEVCTRL_DEV_OFF_MASK | DEVCTRL_DEV_ON_MASK, DEVCTRL_DEV_OFF_MASK); @@ -504,6 +495,19 @@ static int tps65910_i2c_probe(struct i2c_client *i2c, tps65910_sleepinit(tps65910, pmic_plat_data); if (pmic_plat_data->pm_off && !pm_power_off) { + /* + * The PWR_OFF bit needs to be set separately, before + * transitioning to the OFF state. It enables the "sequential" + * power-off mode on TPS65911, it's a NO-OP on TPS65910. + */ + ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL, + DEVCTRL_PWR_OFF_MASK); + if (ret) { + dev_err(&i2c->dev, "failed to set power-off mode: %d\n", + ret); + return ret; + } + tps65910_i2c_client = i2c; pm_power_off = tps65910_power_off; } -- cgit v1.2.3