From 39eb56da2b53bec6720181ed6dc29390a1d91f25 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Jun 2014 19:42:59 -0500 Subject: pcmcia: Remove m8xx_pcmcia driver This driver doesn't build, and apparently has not built since arch/ppc was removed in 2008 (when mk_int_int_mask was removed from asm/irq.h, among other build errors). A few weeks ago I asked whether anyone was actively maintaining this code, and got no positive response: http://patchwork.ozlabs.org/patch/352082/ So, let's remove it. Signed-off-by: Scott Wood Cc: Vitaly Bordug Cc: linux-pcmcia@lists.infradead.org Cc: Paul Bolle --- drivers/pcmcia/Kconfig | 10 - drivers/pcmcia/Makefile | 1 - drivers/pcmcia/m8xx_pcmcia.c | 1168 ------------------------------------------ 3 files changed, 1179 deletions(-) delete mode 100644 drivers/pcmcia/m8xx_pcmcia.c (limited to 'drivers') diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 0c657d6af03d..087d7d7eda76 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -144,16 +144,6 @@ config TCIC "Bridge" is the name used for the hardware inside your computer that PCMCIA cards are plugged into. If unsure, say N. -config PCMCIA_M8XX - tristate "MPC8xx PCMCIA support" - depends on PCCARD && PPC && 8xx - select PCCARD_IODYN if PCMCIA != n - help - Say Y here to include support for PowerPC 8xx series PCMCIA - controller. - - This driver is also available as a module called m8xx_pcmcia. - config PCMCIA_ALCHEMY_DEVBOARD tristate "Alchemy Db/Pb1xxx PCMCIA socket services" depends on MIPS_ALCHEMY && PCMCIA diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 7745b512a87c..e62c26bc7a5f 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -23,7 +23,6 @@ obj-$(CONFIG_PD6729) += pd6729.o obj-$(CONFIG_I82365) += i82365.o obj-$(CONFIG_I82092) += i82092.o obj-$(CONFIG_TCIC) += tcic.o -obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o obj-$(CONFIG_PCMCIA_SOC_COMMON) += soc_common.o obj-$(CONFIG_PCMCIA_SA11XX_BASE) += sa11xx_base.o obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o diff --git a/drivers/pcmcia/m8xx_pcmcia.c b/drivers/pcmcia/m8xx_pcmcia.c deleted file mode 100644 index 182034d2ef58..000000000000 --- a/drivers/pcmcia/m8xx_pcmcia.c +++ /dev/null @@ -1,1168 +0,0 @@ -/* - * m8xx_pcmcia.c - Linux PCMCIA socket driver for the mpc8xx series. - * - * (C) 1999-2000 Magnus Damm - * (C) 2001-2002 Montavista Software, Inc. - * - * - * Support for two slots by Cyclades Corporation - * - * Further fixes, v2.6 kernel port - * - * - * Some fixes, additions (C) 2005-2007 Montavista Software, Inc. - * - * - * "The ExCA standard specifies that socket controllers should provide - * two IO and five memory windows per socket, which can be independently - * configured and positioned in the host address space and mapped to - * arbitrary segments of card address space. " - David A Hinds. 1999 - * - * This controller does _not_ meet the ExCA standard. - * - * m8xx pcmcia controller brief info: - * + 8 windows (attrib, mem, i/o) - * + up to two slots (SLOT_A and SLOT_B) - * + inputpins, outputpins, event and mask registers. - * - no offset register. sigh. - * - * Because of the lacking offset register we must map the whole card. - * We assign each memory window PCMCIA_MEM_WIN_SIZE address space. - * Make sure there is (PCMCIA_MEM_WIN_SIZE * PCMCIA_MEM_WIN_NO - * * PCMCIA_SOCKETS_NO) bytes at PCMCIA_MEM_WIN_BASE. - * The i/o windows are dynamically allocated at PCMCIA_IO_WIN_BASE. - * They are maximum 64KByte each... - */ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -#define pcmcia_info(args...) printk(KERN_INFO "m8xx_pcmcia: "args) -#define pcmcia_error(args...) printk(KERN_ERR "m8xx_pcmcia: "args) - -static const char *version = "Version 0.06, Aug 2005"; -MODULE_LICENSE("Dual MPL/GPL"); - -#if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) - -/* The ADS board use SLOT_A */ -#ifdef CONFIG_ADS -#define CONFIG_PCMCIA_SLOT_A -#define CONFIG_BD_IS_MHZ -#endif - -/* The FADS series are a mess */ -#ifdef CONFIG_FADS -#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC860) || defined(CONFIG_MPC821) -#define CONFIG_PCMCIA_SLOT_A -#else -#define CONFIG_PCMCIA_SLOT_B -#endif -#endif - -#if defined(CONFIG_MPC885ADS) -#define CONFIG_PCMCIA_SLOT_A -#define PCMCIA_GLITCHY_CD -#endif - -/* Cyclades ACS uses both slots */ -#ifdef CONFIG_PRxK -#define CONFIG_PCMCIA_SLOT_A -#define CONFIG_PCMCIA_SLOT_B -#endif - -#endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ - -#if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) - -#define PCMCIA_SOCKETS_NO 2 -/* We have only 8 windows, dualsocket support will be limited. */ -#define PCMCIA_MEM_WIN_NO 2 -#define PCMCIA_IO_WIN_NO 2 -#define PCMCIA_SLOT_MSG "SLOT_A and SLOT_B" - -#elif defined(CONFIG_PCMCIA_SLOT_A) || defined(CONFIG_PCMCIA_SLOT_B) - -#define PCMCIA_SOCKETS_NO 1 -/* full support for one slot */ -#define PCMCIA_MEM_WIN_NO 5 -#define PCMCIA_IO_WIN_NO 2 - -/* define _slot_ to be able to optimize macros */ - -#ifdef CONFIG_PCMCIA_SLOT_A -#define _slot_ 0 -#define PCMCIA_SLOT_MSG "SLOT_A" -#else -#define _slot_ 1 -#define PCMCIA_SLOT_MSG "SLOT_B" -#endif - -#else -#error m8xx_pcmcia: Bad configuration! -#endif - -/* ------------------------------------------------------------------------- */ - -#define PCMCIA_MEM_WIN_BASE 0xe0000000 /* base address for memory window 0 */ -#define PCMCIA_MEM_WIN_SIZE 0x04000000 /* each memory window is 64 MByte */ -#define PCMCIA_IO_WIN_BASE _IO_BASE /* base address for io window 0 */ -/* ------------------------------------------------------------------------- */ - -static int pcmcia_schlvl; - -static DEFINE_SPINLOCK(events_lock); - -#define PCMCIA_SOCKET_KEY_5V 1 -#define PCMCIA_SOCKET_KEY_LV 2 - -/* look up table for pgcrx registers */ -static u32 *m8xx_pgcrx[2]; - -/* - * This structure is used to address each window in the PCMCIA controller. - * - * Keep in mind that we assume that pcmcia_win[n+1] is mapped directly - * after pcmcia_win[n]... - */ - -struct pcmcia_win { - u32 br; - u32 or; -}; - -/* - * For some reason the hardware guys decided to make both slots share - * some registers. - * - * Could someone invent object oriented hardware ? - * - * The macros are used to get the right bit from the registers. - * SLOT_A : slot = 0 - * SLOT_B : slot = 1 - */ - -#define M8XX_PCMCIA_VS1(slot) (0x80000000 >> (slot << 4)) -#define M8XX_PCMCIA_VS2(slot) (0x40000000 >> (slot << 4)) -#define M8XX_PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4)) -#define M8XX_PCMCIA_VS_SHIFT(slot) (30 - (slot << 4)) - -#define M8XX_PCMCIA_WP(slot) (0x20000000 >> (slot << 4)) -#define M8XX_PCMCIA_CD2(slot) (0x10000000 >> (slot << 4)) -#define M8XX_PCMCIA_CD1(slot) (0x08000000 >> (slot << 4)) -#define M8XX_PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4)) -#define M8XX_PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4)) -#define M8XX_PCMCIA_RDY(slot) (0x01000000 >> (slot << 4)) -#define M8XX_PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4)) -#define M8XX_PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4)) -#define M8XX_PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4)) -#define M8XX_PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4)) -#define M8XX_PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4)) - -#define M8XX_PCMCIA_POR_VALID 0x00000001 -#define M8XX_PCMCIA_POR_WRPROT 0x00000002 -#define M8XX_PCMCIA_POR_ATTRMEM 0x00000010 -#define M8XX_PCMCIA_POR_IO 0x00000018 -#define M8XX_PCMCIA_POR_16BIT 0x00000040 - -#define M8XX_PGCRX(slot) m8xx_pgcrx[slot] - -#define M8XX_PGCRX_CXOE 0x00000080 -#define M8XX_PGCRX_CXRESET 0x00000040 - -/* we keep one lookup table per socket to check flags */ - -#define PCMCIA_EVENTS_MAX 5 /* 4 max at a time + termination */ - -struct event_table { - u32 regbit; - u32 eventbit; -}; - -static const char driver_name[] = "m8xx-pcmcia"; - -struct socket_info { - void (*handler) (void *info, u32 events); - void *info; - - u32 slot; - pcmconf8xx_t *pcmcia; - u32 bus_freq; - int hwirq; - - socket_state_t state; - struct pccard_mem_map mem_win[PCMCIA_MEM_WIN_NO]; - struct pccard_io_map io_win[PCMCIA_IO_WIN_NO]; - struct event_table events[PCMCIA_EVENTS_MAX]; - struct pcmcia_socket socket; -}; - -static struct socket_info socket[PCMCIA_SOCKETS_NO]; - -/* - * Search this table to see if the windowsize is - * supported... - */ - -#define M8XX_SIZES_NO 32 - -static const u32 m8xx_size_to_gray[M8XX_SIZES_NO] = { - 0x00000001, 0x00000002, 0x00000008, 0x00000004, - 0x00000080, 0x00000040, 0x00000010, 0x00000020, - 0x00008000, 0x00004000, 0x00001000, 0x00002000, - 0x00000100, 0x00000200, 0x00000800, 0x00000400, - - 0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff, - 0x01000000, 0x02000000, 0xffffffff, 0x04000000, - 0x00010000, 0x00020000, 0x00080000, 0x00040000, - 0x00800000, 0x00400000, 0x00100000, 0x00200000 -}; - -/* ------------------------------------------------------------------------- */ - -static irqreturn_t m8xx_interrupt(int irq, void *dev); - -#define PCMCIA_BMT_LIMIT (15*4) /* Bus Monitor Timeout value */ - -/* FADS Boards from Motorola */ - -#if defined(CONFIG_FADS) - -#define PCMCIA_BOARD_MSG "FADS" - -static int voltage_set(int slot, int vcc, int vpp) -{ - u32 reg = 0; - - switch (vcc) { - case 0: - break; - case 33: - reg |= BCSR1_PCCVCC0; - break; - case 50: - reg |= BCSR1_PCCVCC1; - break; - default: - return 1; - } - - switch (vpp) { - case 0: - break; - case 33: - case 50: - if (vcc == vpp) - reg |= BCSR1_PCCVPP1; - else - return 1; - break; - case 120: - if ((vcc == 33) || (vcc == 50)) - reg |= BCSR1_PCCVPP0; - else - return 1; - default: - return 1; - } - - /* first, turn off all power */ - out_be32((u32 *) BCSR1, - in_be32((u32 *) BCSR1) & ~(BCSR1_PCCVCC_MASK | - BCSR1_PCCVPP_MASK)); - - /* enable new powersettings */ - out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | reg); - - return 0; -} - -#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V - -static void hardware_enable(int slot) -{ - out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) & ~BCSR1_PCCEN); -} - -static void hardware_disable(int slot) -{ - out_be32((u32 *) BCSR1, in_be32((u32 *) BCSR1) | BCSR1_PCCEN); -} - -#endif - -/* MPC885ADS Boards */ - -#if defined(CONFIG_MPC885ADS) - -#define PCMCIA_BOARD_MSG "MPC885ADS" -#define socket_get(_slot_) PCMCIA_SOCKET_KEY_5V - -static inline void hardware_enable(int slot) -{ - m8xx_pcmcia_ops.hw_ctrl(slot, 1); -} - -static inline void hardware_disable(int slot) -{ - m8xx_pcmcia_ops.hw_ctrl(slot, 0); -} - -static inline int voltage_set(int slot, int vcc, int vpp) -{ - return m8xx_pcmcia_ops.voltage_set(slot, vcc, vpp); -} - -#endif - -#if defined(CONFIG_PRxK) -#include -extern volatile fpga_pc_regs *fpga_pc; - -#define PCMCIA_BOARD_MSG "MPC855T" - -static int voltage_set(int slot, int vcc, int vpp) -{ - u8 reg = 0; - u8 regread; - cpld_regs *ccpld = get_cpld(); - - switch (vcc) { - case 0: - break; - case 33: - reg |= PCMCIA_VCC_33; - break; - case 50: - reg |= PCMCIA_VCC_50; - break; - default: - return 1; - } - - switch (vpp) { - case 0: - break; - case 33: - case 50: - if (vcc == vpp) - reg |= PCMCIA_VPP_VCC; - else - return 1; - break; - case 120: - if ((vcc == 33) || (vcc == 50)) - reg |= PCMCIA_VPP_12; - else - return 1; - default: - return 1; - } - - reg = reg >> (slot << 2); - regread = in_8(&ccpld->fpga_pc_ctl); - if (reg != - (regread & ((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> (slot << 2)))) { - /* enable new powersettings */ - regread = - regread & ~((PCMCIA_VCC_MASK | PCMCIA_VPP_MASK) >> - (slot << 2)); - out_8(&ccpld->fpga_pc_ctl, reg | regread); - msleep(100); - } - - return 0; -} - -#define socket_get(_slot_) PCMCIA_SOCKET_KEY_LV -#define hardware_enable(_slot_) /* No hardware to enable */ -#define hardware_disable(_slot_) /* No hardware to disable */ - -#endif /* CONFIG_PRxK */ - -static u32 pending_events[PCMCIA_SOCKETS_NO]; -static DEFINE_SPINLOCK(pending_event_lock); - -static irqreturn_t m8xx_interrupt(int irq, void *dev) -{ - struct socket_info *s; - struct event_table *e; - unsigned int i, events, pscr, pipr, per; - pcmconf8xx_t *pcmcia = socket[0].pcmcia; - - pr_debug("m8xx_pcmcia: Interrupt!\n"); - /* get interrupt sources */ - - pscr = in_be32(&pcmcia->pcmc_pscr); - pipr = in_be32(&pcmcia->pcmc_pipr); - per = in_be32(&pcmcia->pcmc_per); - - for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { - s = &socket[i]; - e = &s->events[0]; - events = 0; - - while (e->regbit) { - if (pscr & e->regbit) - events |= e->eventbit; - - e++; - } - - /* - * report only if both card detect signals are the same - * not too nice done, - * we depend on that CD2 is the bit to the left of CD1... - */ - if (events & SS_DETECT) - if (((pipr & M8XX_PCMCIA_CD2(i)) >> 1) ^ - (pipr & M8XX_PCMCIA_CD1(i))) { - events &= ~SS_DETECT; - } -#ifdef PCMCIA_GLITCHY_CD - /* - * I've experienced CD problems with my ADS board. - * We make an extra check to see if there was a - * real change of Card detection. - */ - - if ((events & SS_DETECT) && - ((pipr & - (M8XX_PCMCIA_CD2(i) | M8XX_PCMCIA_CD1(i))) == 0) && - (s->state.Vcc | s->state.Vpp)) { - events &= ~SS_DETECT; - /*printk( "CD glitch workaround - CD = 0x%08x!\n", - (pipr & (M8XX_PCMCIA_CD2(i) - | M8XX_PCMCIA_CD1(i)))); */ - } -#endif - - /* call the handler */ - - pr_debug("m8xx_pcmcia: slot %u: events = 0x%02x, pscr = 0x%08x, " - "pipr = 0x%08x\n", i, events, pscr, pipr); - - if (events) { - spin_lock(&pending_event_lock); - pending_events[i] |= events; - spin_unlock(&pending_event_lock); - /* - * Turn off RDY_L bits in the PER mask on - * CD interrupt receival. - * - * They can generate bad interrupts on the - * ACS4,8,16,32. - marcelo - */ - per &= ~M8XX_PCMCIA_RDY_L(0); - per &= ~M8XX_PCMCIA_RDY_L(1); - - out_be32(&pcmcia->pcmc_per, per); - - if (events) - pcmcia_parse_events(&socket[i].socket, events); - } - } - - /* clear the interrupt sources */ - out_be32(&pcmcia->pcmc_pscr, pscr); - - pr_debug("m8xx_pcmcia: Interrupt done.\n"); - - return IRQ_HANDLED; -} - -static u32 m8xx_get_graycode(u32 size) -{ - u32 k; - - for (k = 0; k < M8XX_SIZES_NO; k++) - if (m8xx_size_to_gray[k] == size) - break; - - if ((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1)) - k = -1; - - return k; -} - -static u32 m8xx_get_speed(u32 ns, u32 is_io, u32 bus_freq) -{ - u32 reg, clocks, psst, psl, psht; - - if (!ns) { - - /* - * We get called with IO maps setup to 0ns - * if not specified by the user. - * They should be 255ns. - */ - - if (is_io) - ns = 255; - else - ns = 100; /* fast memory if 0 */ - } - - /* - * In PSST, PSL, PSHT fields we tell the controller - * timing parameters in CLKOUT clock cycles. - * CLKOUT is the same as GCLK2_50. - */ - -/* how we want to adjust the timing - in percent */ - -#define ADJ 180 /* 80 % longer accesstime - to be sure */ - - clocks = ((bus_freq / 1000) * ns) / 1000; - clocks = (clocks * ADJ) / (100 * 1000); - if (clocks >= PCMCIA_BMT_LIMIT) { - printk("Max access time limit reached\n"); - clocks = PCMCIA_BMT_LIMIT - 1; - } - - psst = clocks / 7; /* setup time */ - psht = clocks / 7; /* hold time */ - psl = (clocks * 5) / 7; /* strobe length */ - - psst += clocks - (psst + psht + psl); - - reg = psst << 12; - reg |= psl << 7; - reg |= psht << 16; - - return reg; -} - -static int m8xx_get_status(struct pcmcia_socket *sock, unsigned int *value) -{ - int lsock = container_of(sock, struct socket_info, socket)->slot; - struct socket_info *s = &socket[lsock]; - unsigned int pipr, reg; - pcmconf8xx_t *pcmcia = s->pcmcia; - - pipr = in_be32(&pcmcia->pcmc_pipr); - - *value = ((pipr & (M8XX_PCMCIA_CD1(lsock) - | M8XX_PCMCIA_CD2(lsock))) == 0) ? SS_DETECT : 0; - *value |= (pipr & M8XX_PCMCIA_WP(lsock)) ? SS_WRPROT : 0; - - if (s->state.flags & SS_IOCARD) - *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_STSCHG : 0; - else { - *value |= (pipr & M8XX_PCMCIA_RDY(lsock)) ? SS_READY : 0; - *value |= (pipr & M8XX_PCMCIA_BVD1(lsock)) ? SS_BATDEAD : 0; - *value |= (pipr & M8XX_PCMCIA_BVD2(lsock)) ? SS_BATWARN : 0; - } - - if (s->state.Vcc | s->state.Vpp) - *value |= SS_POWERON; - - /* - * Voltage detection: - * This driver only supports 16-Bit pc-cards. - * Cardbus is not handled here. - * - * To determine what voltage to use we must read the VS1 and VS2 pin. - * Depending on what socket type is present, - * different combinations mean different things. - * - * Card Key Socket Key VS1 VS2 Card Vcc for CIS parse - * - * 5V 5V, LV* NC NC 5V only 5V (if available) - * - * 5V 5V, LV* GND NC 5 or 3.3V as low as possible - * - * 5V 5V, LV* GND GND 5, 3.3, x.xV as low as possible - * - * LV* 5V - - shall not fit into socket - * - * LV* LV* GND NC 3.3V only 3.3V - * - * LV* LV* NC GND x.xV x.xV (if avail.) - * - * LV* LV* GND GND 3.3 or x.xV as low as possible - * - * *LV means Low Voltage - * - * - * That gives us the following table: - * - * Socket VS1 VS2 Voltage - * - * 5V NC NC 5V - * 5V NC GND none (should not be possible) - * 5V GND NC >= 3.3V - * 5V GND GND >= x.xV - * - * LV NC NC 5V (if available) - * LV NC GND x.xV (if available) - * LV GND NC 3.3V - * LV GND GND >= x.xV - * - * So, how do I determine if I have a 5V or a LV - * socket on my board? Look at the socket! - * - * - * Socket with 5V key: - * ++--------------------------------------------+ - * || | - * || || - * || || - * | | - * +---------------------------------------------+ - * - * Socket with LV key: - * ++--------------------------------------------+ - * || | - * | || - * | || - * | | - * +---------------------------------------------+ - * - * - * With other words - LV only cards does not fit - * into the 5V socket! - */ - - /* read out VS1 and VS2 */ - - reg = (pipr & M8XX_PCMCIA_VS_MASK(lsock)) - >> M8XX_PCMCIA_VS_SHIFT(lsock); - - if (socket_get(lsock) == PCMCIA_SOCKET_KEY_LV) { - switch (reg) { - case 1: - *value |= SS_3VCARD; - break; /* GND, NC - 3.3V only */ - case 2: - *value |= SS_XVCARD; - break; /* NC. GND - x.xV only */ - }; - } - - pr_debug("m8xx_pcmcia: GetStatus(%d) = %#2.2x\n", lsock, *value); - return 0; -} - -static int m8xx_set_socket(struct pcmcia_socket *sock, socket_state_t * state) -{ - int lsock = container_of(sock, struct socket_info, socket)->slot; - struct socket_info *s = &socket[lsock]; - struct event_table *e; - unsigned int reg; - unsigned long flags; - pcmconf8xx_t *pcmcia = socket[0].pcmcia; - - pr_debug("m8xx_pcmcia: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, " - "io_irq %d, csc_mask %#2.2x)\n", lsock, state->flags, - state->Vcc, state->Vpp, state->io_irq, state->csc_mask); - - /* First, set voltage - bail out if invalid */ - if (voltage_set(lsock, state->Vcc, state->Vpp)) - return -EINVAL; - - /* Take care of reset... */ - if (state->flags & SS_RESET) - out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXRESET); /* active high */ - else - out_be32(M8XX_PGCRX(lsock), - in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXRESET); - - /* ... and output enable. */ - - /* The CxOE signal is connected to a 74541 on the ADS. - I guess most other boards used the ADS as a reference. - I tried to control the CxOE signal with SS_OUTPUT_ENA, - but the reset signal seems connected via the 541. - If the CxOE is left high are some signals tristated and - no pullups are present -> the cards act weird. - So right now the buffers are enabled if the power is on. */ - - if (state->Vcc || state->Vpp) - out_be32(M8XX_PGCRX(lsock), in_be32(M8XX_PGCRX(lsock)) & ~M8XX_PGCRX_CXOE); /* active low */ - else - out_be32(M8XX_PGCRX(lsock), - in_be32(M8XX_PGCRX(lsock)) | M8XX_PGCRX_CXOE); - - /* - * We'd better turn off interrupts before - * we mess with the events-table.. - */ - - spin_lock_irqsave(&events_lock, flags); - - /* - * Play around with the interrupt mask to be able to - * give the events the generic pcmcia driver wants us to. - */ - - e = &s->events[0]; - reg = 0; - - if (state->csc_mask & SS_DETECT) { - e->eventbit = SS_DETECT; - reg |= e->regbit = (M8XX_PCMCIA_CD2(lsock) - | M8XX_PCMCIA_CD1(lsock)); - e++; - } - if (state->flags & SS_IOCARD) { - /* - * I/O card - */ - if (state->csc_mask & SS_STSCHG) { - e->eventbit = SS_STSCHG; - reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); - e++; - } - /* - * If io_irq is non-zero we should enable irq. - */ - if (state->io_irq) { - out_be32(M8XX_PGCRX(lsock), - in_be32(M8XX_PGCRX(lsock)) | - mk_int_int_mask(s->hwirq) << 24); - /* - * Strange thing here: - * The manual does not tell us which interrupt - * the sources generate. - * Anyhow, I found out that RDY_L generates IREQLVL. - * - * We use level triggerd interrupts, and they don't - * have to be cleared in PSCR in the interrupt handler. - */ - reg |= M8XX_PCMCIA_RDY_L(lsock); - } else - out_be32(M8XX_PGCRX(lsock), - in_be32(M8XX_PGCRX(lsock)) & 0x00ffffff); - } else { - /* - * Memory card - */ - if (state->csc_mask & SS_BATDEAD) { - e->eventbit = SS_BATDEAD; - reg |= e->regbit = M8XX_PCMCIA_BVD1(lsock); - e++; - } - if (state->csc_mask & SS_BATWARN) { - e->eventbit = SS_BATWARN; - reg |= e->regbit = M8XX_PCMCIA_BVD2(lsock); - e++; - } - /* What should I trigger on - low/high,raise,fall? */ - if (state->csc_mask & SS_READY) { - e->eventbit = SS_READY; - reg |= e->regbit = 0; //?? - e++; - } - } - - e->regbit = 0; /* terminate list */ - - /* - * Clear the status changed . - * Port A and Port B share the same port. - * Writing ones will clear the bits. - */ - - out_be32(&pcmcia->pcmc_pscr, reg); - - /* - * Write the mask. - * Port A and Port B share the same port. - * Need for read-modify-write. - * Ones will enable the interrupt. - */ - - reg |= - in_be32(&pcmcia-> - pcmc_per) & (M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); - out_be32(&pcmcia->pcmc_per, reg); - - spin_unlock_irqrestore(&events_lock, flags); - - /* copy the struct and modify the copy */ - - s->state = *state; - - return 0; -} - -static int m8xx_set_io_map(struct pcmcia_socket *sock, struct pccard_io_map *io) -{ - int lsock = container_of(sock, struct socket_info, socket)->slot; - - struct socket_info *s = &socket[lsock]; - struct pcmcia_win *w; - unsigned int reg, winnr; - pcmconf8xx_t *pcmcia = s->pcmcia; - -#define M8XX_SIZE (io->stop - io->start + 1) -#define M8XX_BASE (PCMCIA_IO_WIN_BASE + io->start) - - pr_debug("m8xx_pcmcia: SetIOMap(%d, %d, %#2.2x, %d ns, " - "%#4.4llx-%#4.4llx)\n", lsock, io->map, io->flags, - io->speed, (unsigned long long)io->start, - (unsigned long long)io->stop); - - if ((io->map >= PCMCIA_IO_WIN_NO) || (io->start > 0xffff) - || (io->stop > 0xffff) || (io->stop < io->start)) - return -EINVAL; - - if ((reg = m8xx_get_graycode(M8XX_SIZE)) == -1) - return -EINVAL; - - if (io->flags & MAP_ACTIVE) { - - pr_debug("m8xx_pcmcia: io->flags & MAP_ACTIVE\n"); - - winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) - + (lsock * PCMCIA_IO_WIN_NO) + io->map; - - /* setup registers */ - - w = (void *)&pcmcia->pcmc_pbr0; - w += winnr; - - out_be32(&w->or, 0); /* turn off window first */ - out_be32(&w->br, M8XX_BASE); - - reg <<= 27; - reg |= M8XX_PCMCIA_POR_IO | (lsock << 2); - - reg |= m8xx_get_speed(io->speed, 1, s->bus_freq); - - if (io->flags & MAP_WRPROT) - reg |= M8XX_PCMCIA_POR_WRPROT; - - /*if(io->flags & (MAP_16BIT | MAP_AUTOSZ)) */ - if (io->flags & MAP_16BIT) - reg |= M8XX_PCMCIA_POR_16BIT; - - if (io->flags & MAP_ACTIVE) - reg |= M8XX_PCMCIA_POR_VALID; - - out_be32(&w->or, reg); - - pr_debug("m8xx_pcmcia: Socket %u: Mapped io window %u at " - "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or); - } else { - /* shutdown IO window */ - winnr = (PCMCIA_MEM_WIN_NO * PCMCIA_SOCKETS_NO) - + (lsock * PCMCIA_IO_WIN_NO) + io->map; - - /* setup registers */ - - w = (void *)&pcmcia->pcmc_pbr0; - w += winnr; - - out_be32(&w->or, 0); /* turn off window */ - out_be32(&w->br, 0); /* turn off base address */ - - pr_debug("m8xx_pcmcia: Socket %u: Unmapped io window %u at " - "%#8.8x, OR = %#8.8x.\n", lsock, io->map, w->br, w->or); - } - - /* copy the struct and modify the copy */ - s->io_win[io->map] = *io; - s->io_win[io->map].flags &= (MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); - pr_debug("m8xx_pcmcia: SetIOMap exit\n"); - - return 0; -} - -static int m8xx_set_mem_map(struct pcmcia_socket *sock, - struct pccard_mem_map *mem) -{ - int lsock = container_of(sock, struct socket_info, socket)->slot; - struct socket_info *s = &socket[lsock]; - struct pcmcia_win *w; - struct pccard_mem_map *old; - unsigned int reg, winnr; - pcmconf8xx_t *pcmcia = s->pcmcia; - - pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, " - "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags, - mem->speed, (unsigned long long)mem->static_start, - mem->card_start); - - if ((mem->map >= PCMCIA_MEM_WIN_NO) -// || ((mem->s) >= PCMCIA_MEM_WIN_SIZE) - || (mem->card_start >= 0x04000000) - || (mem->static_start & 0xfff) /* 4KByte resolution */ - ||(mem->card_start & 0xfff)) - return -EINVAL; - - if ((reg = m8xx_get_graycode(PCMCIA_MEM_WIN_SIZE)) == -1) { - printk("Cannot set size to 0x%08x.\n", PCMCIA_MEM_WIN_SIZE); - return -EINVAL; - } - reg <<= 27; - - winnr = (lsock * PCMCIA_MEM_WIN_NO) + mem->map; - - /* Setup the window in the pcmcia controller */ - - w = (void *)&pcmcia->pcmc_pbr0; - w += winnr; - - reg |= lsock << 2; - - reg |= m8xx_get_speed(mem->speed, 0, s->bus_freq); - - if (mem->flags & MAP_ATTRIB) - reg |= M8XX_PCMCIA_POR_ATTRMEM; - - if (mem->flags & MAP_WRPROT) - reg |= M8XX_PCMCIA_POR_WRPROT; - - if (mem->flags & MAP_16BIT) - reg |= M8XX_PCMCIA_POR_16BIT; - - if (mem->flags & MAP_ACTIVE) - reg |= M8XX_PCMCIA_POR_VALID; - - out_be32(&w->or, reg); - - pr_debug("m8xx_pcmcia: Socket %u: Mapped memory window %u at %#8.8x, " - "OR = %#8.8x.\n", lsock, mem->map, w->br, w->or); - - if (mem->flags & MAP_ACTIVE) { - /* get the new base address */ - mem->static_start = PCMCIA_MEM_WIN_BASE + - (PCMCIA_MEM_WIN_SIZE * winnr) - + mem->card_start; - } - - pr_debug("m8xx_pcmcia: SetMemMap(%d, %d, %#2.2x, %d ns, " - "%#5.5llx, %#5.5x)\n", lsock, mem->map, mem->flags, - mem->speed, (unsigned long long)mem->static_start, - mem->card_start); - - /* copy the struct and modify the copy */ - - old = &s->mem_win[mem->map]; - - *old = *mem; - old->flags &= (MAP_ATTRIB | MAP_WRPROT | MAP_16BIT | MAP_ACTIVE); - - return 0; -} - -static int m8xx_sock_init(struct pcmcia_socket *sock) -{ - int i; - pccard_io_map io = { 0, 0, 0, 0, 1 }; - pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 }; - - pr_debug("m8xx_pcmcia: sock_init(%d)\n", s); - - m8xx_set_socket(sock, &dead_socket); - for (i = 0; i < PCMCIA_IO_WIN_NO; i++) { - io.map = i; - m8xx_set_io_map(sock, &io); - } - for (i = 0; i < PCMCIA_MEM_WIN_NO; i++) { - mem.map = i; - m8xx_set_mem_map(sock, &mem); - } - - return 0; - -} - -static int m8xx_sock_suspend(struct pcmcia_socket *sock) -{ - return m8xx_set_socket(sock, &dead_socket); -} - -static struct pccard_operations m8xx_services = { - .init = m8xx_sock_init, - .suspend = m8xx_sock_suspend, - .get_status = m8xx_get_status, - .set_socket = m8xx_set_socket, - .set_io_map = m8xx_set_io_map, - .set_mem_map = m8xx_set_mem_map, -}; - -static int __init m8xx_probe(struct platform_device *ofdev) -{ - struct pcmcia_win *w; - unsigned int i, m, hwirq; - pcmconf8xx_t *pcmcia; - int status; - struct device_node *np = ofdev->dev.of_node; - - pcmcia_info("%s\n", version); - - pcmcia = of_iomap(np, 0); - if (pcmcia == NULL) - return -EINVAL; - - pcmcia_schlvl = irq_of_parse_and_map(np, 0); - hwirq = irq_map[pcmcia_schlvl].hwirq; - if (pcmcia_schlvl < 0) { - iounmap(pcmcia); - return -EINVAL; - } - - m8xx_pgcrx[0] = &pcmcia->pcmc_pgcra; - m8xx_pgcrx[1] = &pcmcia->pcmc_pgcrb; - - pcmcia_info(PCMCIA_BOARD_MSG " using " PCMCIA_SLOT_MSG - " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq); - - /* Configure Status change interrupt */ - - if (request_irq(pcmcia_schlvl, m8xx_interrupt, IRQF_SHARED, - driver_name, socket)) { - pcmcia_error("Cannot allocate IRQ %u for SCHLVL!\n", - pcmcia_schlvl); - iounmap(pcmcia); - return -1; - } - - w = (void *)&pcmcia->pcmc_pbr0; - - out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); - clrbits32(&pcmcia->pcmc_per, M8XX_PCMCIA_MASK(0) | M8XX_PCMCIA_MASK(1)); - - /* connect interrupt and disable CxOE */ - - out_be32(M8XX_PGCRX(0), - M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); - out_be32(M8XX_PGCRX(1), - M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); - - /* initialize the fixed memory windows */ - - for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { - for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { - out_be32(&w->br, PCMCIA_MEM_WIN_BASE + - (PCMCIA_MEM_WIN_SIZE - * (m + i * PCMCIA_MEM_WIN_NO))); - - out_be32(&w->or, 0); /* set to not valid */ - - w++; - } - } - - /* turn off voltage */ - voltage_set(0, 0, 0); - voltage_set(1, 0, 0); - - /* Enable external hardware */ - hardware_enable(0); - hardware_enable(1); - - for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { - socket[i].slot = i; - socket[i].socket.owner = THIS_MODULE; - socket[i].socket.features = - SS_CAP_PCCARD | SS_CAP_MEM_ALIGN | SS_CAP_STATIC_MAP; - socket[i].socket.irq_mask = 0x000; - socket[i].socket.map_size = 0x1000; - socket[i].socket.io_offset = 0; - socket[i].socket.pci_irq = pcmcia_schlvl; - socket[i].socket.ops = &m8xx_services; - socket[i].socket.resource_ops = &pccard_iodyn_ops; - socket[i].socket.cb_dev = NULL; - socket[i].socket.dev.parent = &ofdev->dev; - socket[i].pcmcia = pcmcia; - socket[i].bus_freq = ppc_proc_freq; - socket[i].hwirq = hwirq; - - } - - for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { - status = pcmcia_register_socket(&socket[i].socket); - if (status < 0) - pcmcia_error("Socket register failed\n"); - } - - return 0; -} - -static int m8xx_remove(struct platform_device *ofdev) -{ - u32 m, i; - struct pcmcia_win *w; - pcmconf8xx_t *pcmcia = socket[0].pcmcia; - - for (i = 0; i < PCMCIA_SOCKETS_NO; i++) { - w = (void *)&pcmcia->pcmc_pbr0; - - out_be32(&pcmcia->pcmc_pscr, M8XX_PCMCIA_MASK(i)); - out_be32(&pcmcia->pcmc_per, - in_be32(&pcmcia->pcmc_per) & ~M8XX_PCMCIA_MASK(i)); - - /* turn off interrupt and disable CxOE */ - out_be32(M8XX_PGCRX(i), M8XX_PGCRX_CXOE); - - /* turn off memory windows */ - for (m = 0; m < PCMCIA_MEM_WIN_NO; m++) { - out_be32(&w->or, 0); /* set to not valid */ - w++; - } - - /* turn off voltage */ - voltage_set(i, 0, 0); - - /* disable external hardware */ - hardware_disable(i); - } - for (i = 0; i < PCMCIA_SOCKETS_NO; i++) - pcmcia_unregister_socket(&socket[i].socket); - iounmap(pcmcia); - - free_irq(pcmcia_schlvl, NULL); - - return 0; -} - -static const struct of_device_id m8xx_pcmcia_match[] = { - { - .type = "pcmcia", - .compatible = "fsl,pq-pcmcia", - }, - {}, -}; - -MODULE_DEVICE_TABLE(of, m8xx_pcmcia_match); - -static struct platform_driver m8xx_pcmcia_driver = { - .driver = { - .name = driver_name, - .owner = THIS_MODULE, - .of_match_table = m8xx_pcmcia_match, - }, - .probe = m8xx_probe, - .remove = m8xx_remove, -}; - -module_platform_driver(m8xx_pcmcia_driver); -- cgit v1.2.3 From 087dfae3fe3fe6f8b18285890eb9255ec8478d52 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Jun 2014 19:55:33 -0500 Subject: powerpc/8xx: Remove empty asm/mpc8xx.h m8xx_pcmcia_ops was the only thing in this file (other than a comment that describes a usage that doesn't match the file's contents); now that m8xx_pcmcia_ops is gone, remove the empty file. Signed-off-by: Scott Wood Cc: Pantelis Antoniou Cc: Vitaly Bordug Cc: netdev@vger.kernel.org --- arch/powerpc/include/asm/fs_pd.h | 1 - arch/powerpc/include/asm/mpc8xx.h | 10 ---------- arch/powerpc/platforms/8xx/m8xx_setup.c | 1 - arch/powerpc/platforms/8xx/mpc885ads_setup.c | 1 - arch/powerpc/platforms/8xx/tqm8xx_setup.c | 1 - arch/powerpc/sysdev/micropatch.c | 1 - drivers/net/ethernet/freescale/fs_enet/mac-fec.c | 1 - drivers/net/ethernet/freescale/fs_enet/mac-scc.c | 1 - 8 files changed, 17 deletions(-) delete mode 100644 arch/powerpc/include/asm/mpc8xx.h (limited to 'drivers') diff --git a/arch/powerpc/include/asm/fs_pd.h b/arch/powerpc/include/asm/fs_pd.h index 9361cd5342cc..f79d6c74eb2a 100644 --- a/arch/powerpc/include/asm/fs_pd.h +++ b/arch/powerpc/include/asm/fs_pd.h @@ -28,7 +28,6 @@ #ifdef CONFIG_8xx #include -#include extern immap_t __iomem *mpc8xx_immr; diff --git a/arch/powerpc/include/asm/mpc8xx.h b/arch/powerpc/include/asm/mpc8xx.h deleted file mode 100644 index 8ab22e85aba7..000000000000 --- a/arch/powerpc/include/asm/mpc8xx.h +++ /dev/null @@ -1,10 +0,0 @@ -/* This is the single file included by all MPC8xx build options. - * Since there are many different boards and no standard configuration, - * we have a unique include file for each. Rather than change every - * file that has to include MPC8xx configuration, they all include - * this one and the configuration switching is done here. - */ -#ifndef __CONFIG_8xx_DEFS -#define __CONFIG_8xx_DEFS - -#endif /* __CONFIG_8xx_DEFS */ diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c index 623bb43f2b48..d3037747031d 100644 --- a/arch/powerpc/platforms/8xx/m8xx_setup.c +++ b/arch/powerpc/platforms/8xx/m8xx_setup.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c index 3d5e4e151ca8..5921dcb498fd 100644 --- a/arch/powerpc/platforms/8xx/mpc885ads_setup.c +++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c @@ -35,7 +35,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/powerpc/platforms/8xx/tqm8xx_setup.c b/arch/powerpc/platforms/8xx/tqm8xx_setup.c index 251aba8759e4..dda607807def 100644 --- a/arch/powerpc/platforms/8xx/tqm8xx_setup.c +++ b/arch/powerpc/platforms/8xx/tqm8xx_setup.c @@ -37,7 +37,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/powerpc/sysdev/micropatch.c b/arch/powerpc/sysdev/micropatch.c index c0bb76ef7242..6727dc54d549 100644 --- a/arch/powerpc/sysdev/micropatch.c +++ b/arch/powerpc/sysdev/micropatch.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c index fc5413488496..1eedfba2ad3c 100644 --- a/drivers/net/ethernet/freescale/fs_enet/mac-fec.c +++ b/drivers/net/ethernet/freescale/fs_enet/mac-fec.c @@ -41,7 +41,6 @@ #ifdef CONFIG_8xx #include #include -#include #include #endif diff --git a/drivers/net/ethernet/freescale/fs_enet/mac-scc.c b/drivers/net/ethernet/freescale/fs_enet/mac-scc.c index b4bf02f57d43..90b3b19b7cd3 100644 --- a/drivers/net/ethernet/freescale/fs_enet/mac-scc.c +++ b/drivers/net/ethernet/freescale/fs_enet/mac-scc.c @@ -40,7 +40,6 @@ #ifdef CONFIG_8xx #include #include -#include #include #endif -- cgit v1.2.3 From 54afbec0d57f322127e3886b04fe4fd860519bfb Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Wed, 2 Jul 2014 18:52:11 -0500 Subject: memory: Freescale CoreNet Coherency Fabric error reporting driver The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: Scott Wood Reviewed-by: Bharat Bhushan --- arch/powerpc/configs/corenet32_smp_defconfig | 1 + arch/powerpc/configs/corenet64_smp_defconfig | 1 + drivers/memory/Kconfig | 10 ++ drivers/memory/Makefile | 1 + drivers/memory/fsl-corenet-cf.c | 251 +++++++++++++++++++++++++++ 5 files changed, 264 insertions(+) create mode 100644 drivers/memory/fsl-corenet-cf.c (limited to 'drivers') diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 7d0c837f8e0c..6a3c58adf253 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig @@ -180,3 +180,4 @@ CONFIG_CRYPTO_SHA512=y CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_FSL_CORENET_CF=y diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 6ae07e113479..4b07bade1ba9 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig @@ -179,3 +179,4 @@ CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_FSL_CORENET_CF=y diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index c59e9c96e86d..fab81a143bd7 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -61,6 +61,16 @@ config TEGRA30_MC analysis, especially for IOMMU/SMMU(System Memory Management Unit) module. +config FSL_CORENET_CF + tristate "Freescale CoreNet Error Reporting" + depends on FSL_SOC_BOOKE + help + Say Y for reporting of errors from the Freescale CoreNet + Coherency Fabric. Errors reported include accesses to + physical addresses that mapped by no local access window + (LAW) or an invalid LAW, as well as bad cache state that + represents a coherency violation. + config FSL_IFC bool depends on FSL_SOC diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index 71160a2b7313..4055c47f45ab 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_OF) += of_memory.o endif obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o +obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o diff --git a/drivers/memory/fsl-corenet-cf.c b/drivers/memory/fsl-corenet-cf.c new file mode 100644 index 000000000000..c9443fc136db --- /dev/null +++ b/drivers/memory/fsl-corenet-cf.c @@ -0,0 +1,251 @@ +/* + * CoreNet Coherency Fabric error reporting + * + * Copyright 2014 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum ccf_version { + CCF1, + CCF2, +}; + +struct ccf_info { + enum ccf_version version; + int err_reg_offs; +}; + +static const struct ccf_info ccf1_info = { + .version = CCF1, + .err_reg_offs = 0xa00, +}; + +static const struct ccf_info ccf2_info = { + .version = CCF2, + .err_reg_offs = 0xe40, +}; + +static const struct of_device_id ccf_matches[] = { + { + .compatible = "fsl,corenet1-cf", + .data = &ccf1_info, + }, + { + .compatible = "fsl,corenet2-cf", + .data = &ccf2_info, + }, + {} +}; + +struct ccf_err_regs { + u32 errdet; /* 0x00 Error Detect Register */ + /* 0x04 Error Enable (ccf1)/Disable (ccf2) Register */ + u32 errdis; + /* 0x08 Error Interrupt Enable Register (ccf2 only) */ + u32 errinten; + u32 cecar; /* 0x0c Error Capture Attribute Register */ + u32 cecaddrh; /* 0x10 Error Capture Address High */ + u32 cecaddrl; /* 0x14 Error Capture Address Low */ + u32 cecar2; /* 0x18 Error Capture Attribute Register 2 */ +}; + +/* LAE/CV also valid for errdis and errinten */ +#define ERRDET_LAE (1 << 0) /* Local Access Error */ +#define ERRDET_CV (1 << 1) /* Coherency Violation */ +#define ERRDET_CTYPE_SHIFT 26 /* Capture Type (ccf2 only) */ +#define ERRDET_CTYPE_MASK (0x1f << ERRDET_CTYPE_SHIFT) +#define ERRDET_CAP (1 << 31) /* Capture Valid (ccf2 only) */ + +#define CECAR_VAL (1 << 0) /* Valid (ccf1 only) */ +#define CECAR_UVT (1 << 15) /* Unavailable target ID (ccf1) */ +#define CECAR_SRCID_SHIFT_CCF1 24 +#define CECAR_SRCID_MASK_CCF1 (0xff << CECAR_SRCID_SHIFT_CCF1) +#define CECAR_SRCID_SHIFT_CCF2 18 +#define CECAR_SRCID_MASK_CCF2 (0xff << CECAR_SRCID_SHIFT_CCF2) + +#define CECADDRH_ADDRH 0xff + +struct ccf_private { + const struct ccf_info *info; + struct device *dev; + void __iomem *regs; + struct ccf_err_regs __iomem *err_regs; +}; + +static irqreturn_t ccf_irq(int irq, void *dev_id) +{ + struct ccf_private *ccf = dev_id; + static DEFINE_RATELIMIT_STATE(ratelimit, DEFAULT_RATELIMIT_INTERVAL, + DEFAULT_RATELIMIT_BURST); + u32 errdet, cecar, cecar2; + u64 addr; + u32 src_id; + bool uvt = false; + bool cap_valid = false; + + errdet = ioread32be(&ccf->err_regs->errdet); + cecar = ioread32be(&ccf->err_regs->cecar); + cecar2 = ioread32be(&ccf->err_regs->cecar2); + addr = ioread32be(&ccf->err_regs->cecaddrl); + addr |= ((u64)(ioread32be(&ccf->err_regs->cecaddrh) & + CECADDRH_ADDRH)) << 32; + + if (!__ratelimit(&ratelimit)) + goto out; + + switch (ccf->info->version) { + case CCF1: + if (cecar & CECAR_VAL) { + if (cecar & CECAR_UVT) + uvt = true; + + src_id = (cecar & CECAR_SRCID_MASK_CCF1) >> + CECAR_SRCID_SHIFT_CCF1; + cap_valid = true; + } + + break; + case CCF2: + if (errdet & ERRDET_CAP) { + src_id = (cecar & CECAR_SRCID_MASK_CCF2) >> + CECAR_SRCID_SHIFT_CCF2; + cap_valid = true; + } + + break; + } + + dev_crit(ccf->dev, "errdet 0x%08x cecar 0x%08x cecar2 0x%08x\n", + errdet, cecar, cecar2); + + if (errdet & ERRDET_LAE) { + if (uvt) + dev_crit(ccf->dev, "LAW Unavailable Target ID\n"); + else + dev_crit(ccf->dev, "Local Access Window Error\n"); + } + + if (errdet & ERRDET_CV) + dev_crit(ccf->dev, "Coherency Violation\n"); + + if (cap_valid) { + dev_crit(ccf->dev, "address 0x%09llx, src id 0x%x\n", + addr, src_id); + } + +out: + iowrite32be(errdet, &ccf->err_regs->errdet); + return errdet ? IRQ_HANDLED : IRQ_NONE; +} + +static int ccf_probe(struct platform_device *pdev) +{ + struct ccf_private *ccf; + struct resource *r; + const struct of_device_id *match; + int ret, irq; + + match = of_match_device(ccf_matches, &pdev->dev); + if (WARN_ON(!match)) + return -ENODEV; + + ccf = devm_kzalloc(&pdev->dev, sizeof(*ccf), GFP_KERNEL); + if (!ccf) + return -ENOMEM; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) { + dev_err(&pdev->dev, "%s: no mem resource\n", __func__); + return -ENXIO; + } + + ccf->regs = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(ccf->regs)) { + dev_err(&pdev->dev, "%s: can't map mem resource\n", __func__); + return PTR_ERR(ccf->regs); + } + + ccf->dev = &pdev->dev; + ccf->info = match->data; + ccf->err_regs = ccf->regs + ccf->info->err_reg_offs; + + dev_set_drvdata(&pdev->dev, ccf); + + irq = platform_get_irq(pdev, 0); + if (!irq) { + dev_err(&pdev->dev, "%s: no irq\n", __func__); + return -ENXIO; + } + + ret = devm_request_irq(&pdev->dev, irq, ccf_irq, 0, pdev->name, ccf); + if (ret) { + dev_err(&pdev->dev, "%s: can't request irq\n", __func__); + return ret; + } + + switch (ccf->info->version) { + case CCF1: + /* On CCF1 this register enables rather than disables. */ + iowrite32be(ERRDET_LAE | ERRDET_CV, &ccf->err_regs->errdis); + break; + + case CCF2: + iowrite32be(0, &ccf->err_regs->errdis); + iowrite32be(ERRDET_LAE | ERRDET_CV, &ccf->err_regs->errinten); + break; + } + + return 0; +} + +static int ccf_remove(struct platform_device *pdev) +{ + struct ccf_private *ccf = dev_get_drvdata(&pdev->dev); + + switch (ccf->info->version) { + case CCF1: + iowrite32be(0, &ccf->err_regs->errdis); + break; + + case CCF2: + /* + * We clear errdis on ccf1 because that's the only way to + * disable interrupts, but on ccf2 there's no need to disable + * detection. + */ + iowrite32be(0, &ccf->err_regs->errinten); + break; + } + + return 0; +} + +static struct platform_driver ccf_driver = { + .driver = { + .name = KBUILD_MODNAME, + .owner = THIS_MODULE, + .of_match_table = ccf_matches, + }, + .probe = ccf_probe, + .remove = ccf_remove, +}; + +module_platform_driver(ccf_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Freescale CoreNet Coherency Fabric error reporting"); -- cgit v1.2.3 From 1b69be5e8afc634f39ad695a6ab6aad0cf0975c7 Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Tue, 10 Jun 2014 11:41:57 +1000 Subject: drivers/vfio: EEH support for VFIO PCI device The patch adds new IOCTL commands for sPAPR VFIO container device to support EEH functionality for PCI devices, which have been passed through from host to somebody else via VFIO. Signed-off-by: Gavin Shan Acked-by: Alexander Graf Acked-by: Alex Williamson Signed-off-by: Benjamin Herrenschmidt --- Documentation/vfio.txt | 87 +++++++++++++++++++++++++++++++++++-- drivers/vfio/Makefile | 1 + drivers/vfio/pci/vfio_pci.c | 18 ++++++-- drivers/vfio/vfio_iommu_spapr_tce.c | 17 +++++++- drivers/vfio/vfio_spapr_eeh.c | 87 +++++++++++++++++++++++++++++++++++++ include/linux/vfio.h | 23 ++++++++++ include/uapi/linux/vfio.h | 34 +++++++++++++++ 7 files changed, 259 insertions(+), 8 deletions(-) create mode 100644 drivers/vfio/vfio_spapr_eeh.c (limited to 'drivers') diff --git a/Documentation/vfio.txt b/Documentation/vfio.txt index b9ca02370d46..96978eced341 100644 --- a/Documentation/vfio.txt +++ b/Documentation/vfio.txt @@ -305,7 +305,15 @@ faster, the map/unmap handling has been implemented in real mode which provides an excellent performance which has limitations such as inability to do locked pages accounting in real time. -So 3 additional ioctls have been added: +4) According to sPAPR specification, A Partitionable Endpoint (PE) is an I/O +subtree that can be treated as a unit for the purposes of partitioning and +error recovery. A PE may be a single or multi-function IOA (IO Adapter), a +function of a multi-function IOA, or multiple IOAs (possibly including switch +and bridge structures above the multiple IOAs). PPC64 guests detect PCI errors +and recover from them via EEH RTAS services, which works on the basis of +additional ioctl commands. + +So 4 additional ioctls have been added: VFIO_IOMMU_SPAPR_TCE_GET_INFO - returns the size and the start of the DMA window on the PCI bus. @@ -316,9 +324,12 @@ So 3 additional ioctls have been added: VFIO_IOMMU_DISABLE - disables the container. + VFIO_EEH_PE_OP - provides an API for EEH setup, error detection and recovery. The code flow from the example above should be slightly changed: + struct vfio_eeh_pe_op pe_op = { .argsz = sizeof(pe_op), .flags = 0 }; + ..... /* Add the group to the container */ ioctl(group, VFIO_GROUP_SET_CONTAINER, &container); @@ -342,9 +353,79 @@ The code flow from the example above should be slightly changed: dma_map.flags = VFIO_DMA_MAP_FLAG_READ | VFIO_DMA_MAP_FLAG_WRITE; /* Check here is .iova/.size are within DMA window from spapr_iommu_info */ - ioctl(container, VFIO_IOMMU_MAP_DMA, &dma_map); - ..... + + /* Get a file descriptor for the device */ + device = ioctl(group, VFIO_GROUP_GET_DEVICE_FD, "0000:06:0d.0"); + + .... + + /* Gratuitous device reset and go... */ + ioctl(device, VFIO_DEVICE_RESET); + + /* Make sure EEH is supported */ + ioctl(container, VFIO_CHECK_EXTENSION, VFIO_EEH); + + /* Enable the EEH functionality on the device */ + pe_op.op = VFIO_EEH_PE_ENABLE; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + /* You're suggested to create additional data struct to represent + * PE, and put child devices belonging to same IOMMU group to the + * PE instance for later reference. + */ + + /* Check the PE's state and make sure it's in functional state */ + pe_op.op = VFIO_EEH_PE_GET_STATE; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + /* Save device state using pci_save_state(). + * EEH should be enabled on the specified device. + */ + + .... + + /* When 0xFF's returned from reading PCI config space or IO BARs + * of the PCI device. Check the PE's state to see if that has been + * frozen. + */ + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + /* Waiting for pending PCI transactions to be completed and don't + * produce any more PCI traffic from/to the affected PE until + * recovery is finished. + */ + + /* Enable IO for the affected PE and collect logs. Usually, the + * standard part of PCI config space, AER registers are dumped + * as logs for further analysis. + */ + pe_op.op = VFIO_EEH_PE_UNFREEZE_IO; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + /* + * Issue PE reset: hot or fundamental reset. Usually, hot reset + * is enough. However, the firmware of some PCI adapters would + * require fundamental reset. + */ + pe_op.op = VFIO_EEH_PE_RESET_HOT; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + pe_op.op = VFIO_EEH_PE_RESET_DEACTIVATE; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + /* Configure the PCI bridges for the affected PE */ + pe_op.op = VFIO_EEH_PE_CONFIGURE; + ioctl(container, VFIO_EEH_PE_OP, &pe_op); + + /* Restored state we saved at initialization time. pci_restore_state() + * is good enough as an example. + */ + + /* Hopefully, error is recovered successfully. Now, you can resume to + * start PCI traffic to/from the affected PE. + */ + + .... ------------------------------------------------------------------------------- diff --git a/drivers/vfio/Makefile b/drivers/vfio/Makefile index 72bfabc8629e..50e30bc75e85 100644 --- a/drivers/vfio/Makefile +++ b/drivers/vfio/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_VFIO) += vfio.o obj-$(CONFIG_VFIO_IOMMU_TYPE1) += vfio_iommu_type1.o obj-$(CONFIG_VFIO_IOMMU_SPAPR_TCE) += vfio_iommu_spapr_tce.o +obj-$(CONFIG_EEH) += vfio_spapr_eeh.o obj-$(CONFIG_VFIO_PCI) += pci/ diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c index 010e0f8b8e4f..e2ee80f36e3e 100644 --- a/drivers/vfio/pci/vfio_pci.c +++ b/drivers/vfio/pci/vfio_pci.c @@ -157,8 +157,10 @@ static void vfio_pci_release(void *device_data) { struct vfio_pci_device *vdev = device_data; - if (atomic_dec_and_test(&vdev->refcnt)) + if (atomic_dec_and_test(&vdev->refcnt)) { + vfio_spapr_pci_eeh_release(vdev->pdev); vfio_pci_disable(vdev); + } module_put(THIS_MODULE); } @@ -166,19 +168,27 @@ static void vfio_pci_release(void *device_data) static int vfio_pci_open(void *device_data) { struct vfio_pci_device *vdev = device_data; + int ret; if (!try_module_get(THIS_MODULE)) return -ENODEV; if (atomic_inc_return(&vdev->refcnt) == 1) { - int ret = vfio_pci_enable(vdev); + ret = vfio_pci_enable(vdev); + if (ret) + goto error; + + ret = vfio_spapr_pci_eeh_open(vdev->pdev); if (ret) { - module_put(THIS_MODULE); - return ret; + vfio_pci_disable(vdev); + goto error; } } return 0; +error: + module_put(THIS_MODULE); + return ret; } static int vfio_pci_get_irq_count(struct vfio_pci_device *vdev, int irq_type) diff --git a/drivers/vfio/vfio_iommu_spapr_tce.c b/drivers/vfio/vfio_iommu_spapr_tce.c index a84788ba662c..730b4ef3e0cc 100644 --- a/drivers/vfio/vfio_iommu_spapr_tce.c +++ b/drivers/vfio/vfio_iommu_spapr_tce.c @@ -156,7 +156,16 @@ static long tce_iommu_ioctl(void *iommu_data, switch (cmd) { case VFIO_CHECK_EXTENSION: - return (arg == VFIO_SPAPR_TCE_IOMMU) ? 1 : 0; + switch (arg) { + case VFIO_SPAPR_TCE_IOMMU: + ret = 1; + break; + default: + ret = vfio_spapr_iommu_eeh_ioctl(NULL, cmd, arg); + break; + } + + return (ret < 0) ? 0 : ret; case VFIO_IOMMU_SPAPR_TCE_GET_INFO: { struct vfio_iommu_spapr_tce_info info; @@ -283,6 +292,12 @@ static long tce_iommu_ioctl(void *iommu_data, tce_iommu_disable(container); mutex_unlock(&container->lock); return 0; + case VFIO_EEH_PE_OP: + if (!container->tbl || !container->tbl->it_group) + return -ENODEV; + + return vfio_spapr_iommu_eeh_ioctl(container->tbl->it_group, + cmd, arg); } return -ENOTTY; diff --git a/drivers/vfio/vfio_spapr_eeh.c b/drivers/vfio/vfio_spapr_eeh.c new file mode 100644 index 000000000000..f834b4ce1431 --- /dev/null +++ b/drivers/vfio/vfio_spapr_eeh.c @@ -0,0 +1,87 @@ +/* + * EEH functionality support for VFIO devices. The feature is only + * available on sPAPR compatible platforms. + * + * Copyright Gavin Shan, IBM Corporation 2014. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include + +/* We might build address mapping here for "fast" path later */ +int vfio_spapr_pci_eeh_open(struct pci_dev *pdev) +{ + return eeh_dev_open(pdev); +} + +void vfio_spapr_pci_eeh_release(struct pci_dev *pdev) +{ + eeh_dev_release(pdev); +} + +long vfio_spapr_iommu_eeh_ioctl(struct iommu_group *group, + unsigned int cmd, unsigned long arg) +{ + struct eeh_pe *pe; + struct vfio_eeh_pe_op op; + unsigned long minsz; + long ret = -EINVAL; + + switch (cmd) { + case VFIO_CHECK_EXTENSION: + if (arg == VFIO_EEH) + ret = eeh_enabled() ? 1 : 0; + else + ret = 0; + break; + case VFIO_EEH_PE_OP: + pe = eeh_iommu_group_to_pe(group); + if (!pe) + return -ENODEV; + + minsz = offsetofend(struct vfio_eeh_pe_op, op); + if (copy_from_user(&op, (void __user *)arg, minsz)) + return -EFAULT; + if (op.argsz < minsz || op.flags) + return -EINVAL; + + switch (op.op) { + case VFIO_EEH_PE_DISABLE: + ret = eeh_pe_set_option(pe, EEH_OPT_DISABLE); + break; + case VFIO_EEH_PE_ENABLE: + ret = eeh_pe_set_option(pe, EEH_OPT_ENABLE); + break; + case VFIO_EEH_PE_UNFREEZE_IO: + ret = eeh_pe_set_option(pe, EEH_OPT_THAW_MMIO); + break; + case VFIO_EEH_PE_UNFREEZE_DMA: + ret = eeh_pe_set_option(pe, EEH_OPT_THAW_DMA); + break; + case VFIO_EEH_PE_GET_STATE: + ret = eeh_pe_get_state(pe); + break; + case VFIO_EEH_PE_RESET_DEACTIVATE: + ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE); + break; + case VFIO_EEH_PE_RESET_HOT: + ret = eeh_pe_reset(pe, EEH_RESET_HOT); + break; + case VFIO_EEH_PE_RESET_FUNDAMENTAL: + ret = eeh_pe_reset(pe, EEH_RESET_FUNDAMENTAL); + break; + case VFIO_EEH_PE_CONFIGURE: + ret = eeh_pe_configure(pe); + break; + default: + ret = -EINVAL; + } + } + + return ret; +} diff --git a/include/linux/vfio.h b/include/linux/vfio.h index 8ec980b5e3af..25a0fbd4b998 100644 --- a/include/linux/vfio.h +++ b/include/linux/vfio.h @@ -98,4 +98,27 @@ extern int vfio_external_user_iommu_id(struct vfio_group *group); extern long vfio_external_check_extension(struct vfio_group *group, unsigned long arg); +#ifdef CONFIG_EEH +extern int vfio_spapr_pci_eeh_open(struct pci_dev *pdev); +extern void vfio_spapr_pci_eeh_release(struct pci_dev *pdev); +extern long vfio_spapr_iommu_eeh_ioctl(struct iommu_group *group, + unsigned int cmd, + unsigned long arg); +#else +static inline int vfio_spapr_pci_eeh_open(struct pci_dev *pdev) +{ + return 0; +} + +static inline void vfio_spapr_pci_eeh_release(struct pci_dev *pdev) +{ +} + +static inline long vfio_spapr_iommu_eeh_ioctl(struct iommu_group *group, + unsigned int cmd, + unsigned long arg) +{ + return -ENOTTY; +} +#endif /* CONFIG_EEH */ #endif /* VFIO_H */ diff --git a/include/uapi/linux/vfio.h b/include/uapi/linux/vfio.h index cb9023d4f063..6612974c64bf 100644 --- a/include/uapi/linux/vfio.h +++ b/include/uapi/linux/vfio.h @@ -30,6 +30,9 @@ */ #define VFIO_DMA_CC_IOMMU 4 +/* Check if EEH is supported */ +#define VFIO_EEH 5 + /* * The IOCTL interface is designed for extensibility by embedding the * structure length (argsz) and flags into structures passed between @@ -455,6 +458,37 @@ struct vfio_iommu_spapr_tce_info { #define VFIO_IOMMU_SPAPR_TCE_GET_INFO _IO(VFIO_TYPE, VFIO_BASE + 12) +/* + * EEH PE operation struct provides ways to: + * - enable/disable EEH functionality; + * - unfreeze IO/DMA for frozen PE; + * - read PE state; + * - reset PE; + * - configure PE. + */ +struct vfio_eeh_pe_op { + __u32 argsz; + __u32 flags; + __u32 op; +}; + +#define VFIO_EEH_PE_DISABLE 0 /* Disable EEH functionality */ +#define VFIO_EEH_PE_ENABLE 1 /* Enable EEH functionality */ +#define VFIO_EEH_PE_UNFREEZE_IO 2 /* Enable IO for frozen PE */ +#define VFIO_EEH_PE_UNFREEZE_DMA 3 /* Enable DMA for frozen PE */ +#define VFIO_EEH_PE_GET_STATE 4 /* PE state retrieval */ +#define VFIO_EEH_PE_STATE_NORMAL 0 /* PE in functional state */ +#define VFIO_EEH_PE_STATE_RESET 1 /* PE reset in progress */ +#define VFIO_EEH_PE_STATE_STOPPED 2 /* Stopped DMA and IO */ +#define VFIO_EEH_PE_STATE_STOPPED_DMA 4 /* Stopped DMA only */ +#define VFIO_EEH_PE_STATE_UNAVAIL 5 /* State unavailable */ +#define VFIO_EEH_PE_RESET_DEACTIVATE 5 /* Deassert PE reset */ +#define VFIO_EEH_PE_RESET_HOT 6 /* Assert hot reset */ +#define VFIO_EEH_PE_RESET_FUNDAMENTAL 7 /* Assert fundamental reset */ +#define VFIO_EEH_PE_CONFIGURE 8 /* PE configuration */ + +#define VFIO_EEH_PE_OP _IO(VFIO_TYPE, VFIO_BASE + 21) + /* ***************************************************************** */ #endif /* _UAPIVFIO_H */ -- cgit v1.2.3 From 6174bac8c7ff73a86ae9a967d1c9cadc478023ae Mon Sep 17 00:00:00 2001 From: Vaidyanathan Srinivasan Date: Sun, 3 Aug 2014 14:54:05 +0530 Subject: powerpc/cpufreq: Add pr_warn() on OPAL firmware failures Cpufreq depends on platform firmware to implement PStates. In case of platform firmware failure, cpufreq should not panic host kernel with BUG_ON(). Less severe pr_warn() will suffice. Add firmware_has_feature(FW_FEATURE_OPALv3) check to skip probing for device-tree on non-powernv platforms. Signed-off-by: Vaidyanathan Srinivasan Acked-by: Gautham R. Shenoy CC: Signed-off-by: Benjamin Herrenschmidt --- drivers/cpufreq/powernv-cpufreq.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/cpufreq/powernv-cpufreq.c b/drivers/cpufreq/powernv-cpufreq.c index bb1d08dc8cc8..379c0837f5a9 100644 --- a/drivers/cpufreq/powernv-cpufreq.c +++ b/drivers/cpufreq/powernv-cpufreq.c @@ -28,6 +28,7 @@ #include #include +#include #include #include /* Required for cpu_sibling_mask() in UP configs */ @@ -98,7 +99,11 @@ static int init_powernv_pstates(void) return -ENODEV; } - WARN_ON(len_ids != len_freqs); + if (len_ids != len_freqs) { + pr_warn("Entries in ibm,pstate-ids and " + "ibm,pstate-frequencies-mhz does not match\n"); + } + nr_pstates = min(len_ids, len_freqs) / sizeof(u32); if (!nr_pstates) { pr_warn("No PStates found\n"); @@ -131,7 +136,12 @@ static unsigned int pstate_id_to_freq(int pstate_id) int i; i = powernv_pstate_info.max - pstate_id; - BUG_ON(i >= powernv_pstate_info.nr_pstates || i < 0); + if (i >= powernv_pstate_info.nr_pstates || i < 0) { + pr_warn("PState id %d outside of PState table, " + "reporting nominal id %d instead\n", + pstate_id, powernv_pstate_info.nominal); + i = powernv_pstate_info.max - powernv_pstate_info.nominal; + } return powernv_freqs[i].frequency; } @@ -321,6 +331,10 @@ static int __init powernv_cpufreq_init(void) { int rc = 0; + /* Don't probe on pseries (guest) platforms */ + if (!firmware_has_feature(FW_FEATURE_OPALv3)) + return -ENODEV; + /* Discover pstates from device tree and init */ rc = init_powernv_pstates(); if (rc) { -- cgit v1.2.3 From 95707d852856aec1cbdad1873ff2dc5161a5cb91 Mon Sep 17 00:00:00 2001 From: Vaidyanathan Srinivasan Date: Sun, 3 Aug 2014 13:23:08 +0530 Subject: powerpc/cpuidle: Fix parsing of idle state flags from device-tree Flags from device-tree need to be parsed with accessors for interpreting correct value in little-endian. Signed-off-by: Vaidyanathan Srinivasan Reviewed-by: Preeti U. Murthy CC: Signed-off-by: Benjamin Herrenschmidt --- drivers/cpuidle/cpuidle-powernv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c index 74f5788d50b1..a64be578dab2 100644 --- a/drivers/cpuidle/cpuidle-powernv.c +++ b/drivers/cpuidle/cpuidle-powernv.c @@ -160,10 +160,10 @@ static int powernv_cpuidle_driver_init(void) static int powernv_add_idle_states(void) { struct device_node *power_mgt; - struct property *prop; int nr_idle_states = 1; /* Snooze */ int dt_idle_states; - u32 *flags; + const __be32 *idle_state_flags; + u32 len_flags, flags; int i; /* Currently we have snooze statically defined */ @@ -174,18 +174,18 @@ static int powernv_add_idle_states(void) return nr_idle_states; } - prop = of_find_property(power_mgt, "ibm,cpu-idle-state-flags", NULL); - if (!prop) { + idle_state_flags = of_get_property(power_mgt, "ibm,cpu-idle-state-flags", &len_flags); + if (!idle_state_flags) { pr_warn("DT-PowerMgmt: missing ibm,cpu-idle-state-flags\n"); return nr_idle_states; } - dt_idle_states = prop->length / sizeof(u32); - flags = (u32 *) prop->value; + dt_idle_states = len_flags / sizeof(u32); for (i = 0; i < dt_idle_states; i++) { - if (flags[i] & IDLE_USE_INST_NAP) { + flags = be32_to_cpu(idle_state_flags[i]); + if (flags & IDLE_USE_INST_NAP) { /* Add NAP state */ strcpy(powernv_states[nr_idle_states].name, "Nap"); strcpy(powernv_states[nr_idle_states].desc, "Nap"); @@ -196,7 +196,7 @@ static int powernv_add_idle_states(void) nr_idle_states++; } - if (flags[i] & IDLE_USE_INST_SLEEP) { + if (flags & IDLE_USE_INST_SLEEP) { /* Add FASTSLEEP state */ strcpy(powernv_states[nr_idle_states].name, "FastSleep"); strcpy(powernv_states[nr_idle_states].desc, "FastSleep"); -- cgit v1.2.3