From c7785ea0d279322bf92107d9a4fee195f5148c08 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Wed, 3 Apr 2013 13:28:26 +0200 Subject: clocksource: nomadik-mtu: support of probe Support device tree probe of the nomadik-mtu clocksource. Signed-off-by: Rabin Vincent --- drivers/clocksource/nomadik-mtu.c | 70 ++++++++++++++++++++++++++++++++------- 1 file changed, 58 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c index e405531e1cc5..7982cb0f25f2 100644 --- a/drivers/clocksource/nomadik-mtu.c +++ b/drivers/clocksource/nomadik-mtu.c @@ -13,6 +13,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -188,22 +191,15 @@ static struct irqaction nmdk_timer_irq = { .dev_id = &nmdk_clkevt, }; -void __init nmdk_timer_init(void __iomem *base, int irq) +static void __init __nmdk_timer_init(void __iomem *base, int irq, + struct clk *pclk, struct clk *clk) { unsigned long rate; - struct clk *clk0, *pclk0; mtu_base = base; - pclk0 = clk_get_sys("mtu0", "apb_pclk"); - BUG_ON(IS_ERR(pclk0)); - BUG_ON(clk_prepare(pclk0) < 0); - BUG_ON(clk_enable(pclk0) < 0); - - clk0 = clk_get_sys("mtu0", NULL); - BUG_ON(IS_ERR(clk0)); - BUG_ON(clk_prepare(clk0) < 0); - BUG_ON(clk_enable(clk0) < 0); + BUG_ON(clk_prepare_enable(pclk)); + BUG_ON(clk_prepare_enable(clk)); /* * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz @@ -213,7 +209,7 @@ void __init nmdk_timer_init(void __iomem *base, int irq) * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer * with 16 gives too low timer resolution. */ - rate = clk_get_rate(clk0); + rate = clk_get_rate(clk); if (rate > 32000000) { rate /= 16; clk_prescale = MTU_CRn_PRESCALE_16; @@ -247,3 +243,53 @@ void __init nmdk_timer_init(void __iomem *base, int irq) mtu_delay_timer.freq = rate; register_current_timer_delay(&mtu_delay_timer); } + +void __init nmdk_timer_init(void __iomem *base, int irq) +{ + struct clk *clk0, *pclk0; + + pclk0 = clk_get_sys("mtu0", "apb_pclk"); + BUG_ON(IS_ERR(pclk0)); + clk0 = clk_get_sys("mtu0", NULL); + BUG_ON(IS_ERR(clk0)); + + __nmdk_timer_init(base, irq, pclk0, clk0); +} + +static struct of_device_id nmdk_timer_match[] __initconst = { + { .compatible = "st,nomadik-mtu" }, + {} +}; + +static void __init nmdk_timer_of_init(void) +{ + struct device_node *node; + struct clk *pclk; + struct clk *clk; + void __iomem *base; + int irq; + + node = of_find_matching_node(NULL, nmdk_timer_match); + if (!node) + panic("No timer node"); + + base = of_iomap(node, 0); + if (!base) + panic("Can't remap registers"); + + pclk = of_clk_get_by_name(node, "apb_pclk"); + if (IS_ERR(pclk)) + panic("could not get apb_pclk"); + + clk = of_clk_get_by_name(node, "timclk"); + if (IS_ERR(clk)) + panic("could not get timclk"); + + irq = irq_of_parse_and_map(node, 0); + if (irq <= 0) + panic("Can't parse IRQ"); + + __nmdk_timer_init(base, irq, pclk, clk); +} +CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu", + nmdk_timer_of_init); -- cgit v1.2.3 From 6e2b07a172b6ed98c7cdc301333b2d9f86c11880 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 16 Apr 2013 21:38:29 +0200 Subject: ARM: nomadik: convert all clocks except timer to dt This moves all Nomadik clocks except the one used for the timer/clocksource over to the device tree. Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- .../devicetree/bindings/arm/ste-nomadik.txt | 5 ++ arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 54 ++++++++++++++++++++++ arch/arm/mach-nomadik/cpu-8815.c | 20 +------- drivers/clk/clk-nomadik.c | 26 +++-------- 4 files changed, 68 insertions(+), 37 deletions(-) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt index 19bca04b81c9..6256ec31666d 100644 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ b/Documentation/devicetree/bindings/arm/ste-nomadik.txt @@ -3,6 +3,11 @@ ST-Ericsson Nomadik Device Tree Bindings For various board the "board" node may contain specific properties that pertain to this particular board, such as board-specific GPIOs. +Required root node property: src +- Nomadik System and reset controller used for basic chip control, clock + and reset line control. +- compatible: must be "stericsson,nomadik,src" + Boards with the Nomadik SoC include: S8815 "MiniKit" manufactured by Calao Systems: diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 4a4aab395141..f0df9482cb6f 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -45,6 +45,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <0>; + clocks = <&pclk>; }; gpio1: gpio@101e5000 { @@ -57,6 +58,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <1>; + clocks = <&pclk>; }; gpio2: gpio@101e6000 { @@ -69,6 +71,7 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <2>; + clocks = <&pclk>; }; gpio3: gpio@101e7000 { @@ -81,12 +84,50 @@ gpio-controller; #gpio-cells = <2>; gpio-bank = <3>; + clocks = <&pclk>; }; pinctrl { compatible = "stericsson,nmk-pinctrl-stn8815"; }; + src: src@101e0000 { + compatible = "stericsson,nomadik-src"; + reg = <0x101e0000 0x1000>; + clocks { + /* + * Dummy clock for primecells + */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <2400000>; + }; + /* + * The 2.4 MHz TIMCLK reference clock is active at + * boot time, this is actually the MXTALCLK @19.2 MHz + * divided by 8. This clock is used by the timers and + * watchdog. See page 105 ff. + */ + timclk: timclk@2.4M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <2400000>; + }; + /* + * At boot time, PLL2 is set to generate a set of + * fixed clocks, one of them is CLK48, the 48 MHz + * clock, routed to the UART, MMC/SD, I2C, IrDA, + * USB and SSP blocks. + */ + clk48: clk48@48M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + }; + }; + /* A NAND flash of 128 MiB */ fsmc: flash@40000000 { compatible = "stericsson,fsmc-nand"; @@ -97,6 +138,7 @@ <0x41000000 0x2000>, /* NAND Base ADDR */ <0x40800000 0x2000>; /* NAND Base CMD */ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; + clocks = <&pclk>; status = "okay"; partition@0 { @@ -211,6 +253,8 @@ reg = <0x101fd000 0x1000>; interrupt-parent = <&vica>; interrupts = <12>; + clocks = <&clk48>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; uart1: uart@101fb000 { @@ -218,6 +262,8 @@ reg = <0x101fb000 0x1000>; interrupt-parent = <&vica>; interrupts = <17>; + clocks = <&clk48>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; }; uart2: uart@101f2000 { @@ -225,17 +271,23 @@ reg = <0x101f2000 0x1000>; interrupt-parent = <&vica>; interrupts = <28>; + clocks = <&clk48>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; rng: rng@101b0000 { compatible = "arm,primecell"; reg = <0x101b0000 0x1000>; + clocks = <&clk48>, <&pclk>; + clock-names = "rng", "apb_pclk"; }; rtc: rtc@101e8000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x101e8000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; interrupt-parent = <&vica>; interrupts = <10>; }; @@ -243,6 +295,8 @@ mmcsd: sdi@101f6000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x101f6000 0x1000>; + clocks = <&clk48>, <&pclk>; + clock-names = "mclk", "apb_pclk"; interrupt-parent = <&vica>; interrupts = <22>; max-frequency = <48000000>; diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 59f6ff5c9bae..0e2c5e0cd65e 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -280,28 +280,12 @@ device_initcall(cpu8815_mmcsd_init); /* These are mostly to get the right device names for the clock lookups */ static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE, - "gpio.0", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE, - "gpio.1", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE, - "gpio.2", NULL), - OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE, - "gpio.3", NULL), OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0, "pinctrl-stn8815", NULL), - OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE, - "uart0", NULL), - OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE, - "uart1", NULL), - OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE, - "rng", NULL), - OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE, - "rtc-pl031", NULL), OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE, - "fsmc-nand", &cpu8815_nand_data), + NULL, &cpu8815_nand_data), OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE, - "mmci", &mmcsd_plat_data), + NULL, &mmcsd_plat_data), { /* sentinel */ }, }; diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 6b4c70f7d23d..19f197ccf28d 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -3,24 +3,24 @@ #include #include #include +#include /* * The Nomadik clock tree is described in the STN8815A12 DB V4.2 * reference manual for the chip, page 94 ff. */ +static const __initconst struct of_device_id cpu8815_clk_match[] = { + { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, + { /* sentinel */ } +}; + void __init nomadik_clk_init(void) { struct clk *clk; clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); clk_register_clkdev(clk, "apb_pclk", NULL); - clk_register_clkdev(clk, NULL, "gpio.0"); - clk_register_clkdev(clk, NULL, "gpio.1"); - clk_register_clkdev(clk, NULL, "gpio.2"); - clk_register_clkdev(clk, NULL, "gpio.3"); - clk_register_clkdev(clk, NULL, "rng"); - clk_register_clkdev(clk, NULL, "fsmc-nand"); /* * The 2.4 MHz TIMCLK reference clock is active at boot time, this is @@ -32,17 +32,5 @@ void __init nomadik_clk_init(void) clk_register_clkdev(clk, NULL, "mtu0"); clk_register_clkdev(clk, NULL, "mtu1"); - /* - * At boot time, PLL2 is set to generate a set of fixed clocks, - * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD - * I2C, IrDA, USB and SSP blocks. - */ - clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT, - 48000000); - clk_register_clkdev(clk, NULL, "uart0"); - clk_register_clkdev(clk, NULL, "uart1"); - clk_register_clkdev(clk, NULL, "mmci"); - clk_register_clkdev(clk, NULL, "ssp"); - clk_register_clkdev(clk, NULL, "nmk-i2c.0"); - clk_register_clkdev(clk, NULL, "nmk-i2c.1"); + of_clk_init(cpu8815_clk_match); } -- cgit v1.2.3 From 7690fbb293df83025cffb608f9c2e81414c468a8 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 16 Apr 2013 23:44:31 +0200 Subject: ARM: nomadik: register clocksource from device tree This switches the Nomadik platform to also registering its clocksource from the device tree, removing unused support code as we go along. Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 11 ++++++++--- arch/arm/mach-nomadik/Kconfig | 1 + arch/arm/mach-nomadik/cpu-8815.c | 6 +++--- drivers/clk/clk-nomadik.c | 15 --------------- 4 files changed, 12 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index f0df9482cb6f..51a33e080ca9 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -21,18 +21,23 @@ cache-level = <2>; }; - mtu0 { + mtu0: mtu@101e2000 { /* Nomadik system timer */ + compatible = "st,nomadik-mtu"; reg = <0x101e2000 0x1000>; interrupt-parent = <&vica>; interrupts = <4>; + clocks = <&timclk>, <&pclk>; + clock-names = "timclk", "apb_pclk"; }; - mtu1 { + mtu1: mtu@101e3000 { /* Secondary timer */ reg = <0x101e3000 0x1000>; interrupt-parent = <&vica>; interrupts = <5>; + clocks = <&timclk>, <&pclk>; + clock-names = "timclk", "apb_pclk"; }; gpio0: gpio@101e4000 { @@ -101,7 +106,7 @@ pclk: pclk@0 { #clock-cells = <0>; compatible = "fixed-clock"; - clock-frequency = <2400000>; + clock-frequency = <0>; }; /* * The 2.4 MHz TIMCLK reference clock is active at diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index 9b9d105f194c..5981c3db9b41 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -6,6 +6,7 @@ config ARCH_NOMADIK select ARM_VIC select CLKSRC_NOMADIK_MTU select CLKSRC_NOMADIK_MTU_SCHED_CLOCK + select CLKSRC_OF select COMMON_CLK select CPU_ARM926T select GENERIC_CLOCKEVENTS diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 0e2c5e0cd65e..e73a71f78b4d 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -172,7 +172,7 @@ static void __init cpu8815_timer_init_of(void) /* We need this to be up now */ nomadik_clk_init(); - mtu = of_find_node_by_path("/mtu0"); + mtu = of_find_node_by_path("/mtu@101e2000"); if (!mtu) return; base = of_iomap(mtu, 0); @@ -188,7 +188,7 @@ static void __init cpu8815_timer_init_of(void) src_cr |= SRC_CR_INIT_VAL; writel(src_cr, base); - nmdk_timer_init(base, irq); + clocksource_of_init(); } static struct fsmc_nand_timings cpu8815_nand_timings = { diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 19f197ccf28d..4a1ab27ee87f 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -17,20 +17,5 @@ static const __initconst struct of_device_id cpu8815_clk_match[] = { void __init nomadik_clk_init(void) { - struct clk *clk; - - clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); - clk_register_clkdev(clk, "apb_pclk", NULL); - - /* - * The 2.4 MHz TIMCLK reference clock is active at boot time, this is - * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used - * by the timers and watchdog. See page 105 ff. - */ - clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT, - 2400000); - clk_register_clkdev(clk, NULL, "mtu0"); - clk_register_clkdev(clk, NULL, "mtu1"); - of_clk_init(cpu8815_clk_match); } -- cgit v1.2.3 From c2dade34eaa2384f2921b0a29bb8ac43848e0317 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 16 May 2013 12:27:25 +0100 Subject: crypto: ux500/cryp - Enable DT probing of the driver By providing an OF match table with a suitable compatible string, we can ensure the ux500-crypt driver is probed by supplying an associated DT node in a given platform's Device Tree. Cc: linux-crypto@vger.kernel.org Acked-by: Herbert Xu Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/crypto/ux500/cryp/cryp_core.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c index 32f480622b97..8c2777cf02f6 100644 --- a/drivers/crypto/ux500/cryp/cryp_core.c +++ b/drivers/crypto/ux500/cryp/cryp_core.c @@ -1743,6 +1743,11 @@ static int ux500_cryp_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(ux500_cryp_pm, ux500_cryp_suspend, ux500_cryp_resume); +static const struct of_device_id ux500_cryp_match[] = { + { .compatible = "stericsson,ux500-cryp" }, + { }, +}; + static struct platform_driver cryp_driver = { .probe = ux500_cryp_probe, .remove = ux500_cryp_remove, @@ -1750,6 +1755,7 @@ static struct platform_driver cryp_driver = { .driver = { .owner = THIS_MODULE, .name = "cryp1", + .of_match_table = ux500_cryp_match, .pm = &ux500_cryp_pm, } }; -- cgit v1.2.3 From 4a2e2d0d6bb3689fd317b1c89b7b6eb19b632600 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 16 May 2013 12:27:26 +0100 Subject: crypto: ux500/hash - Enable DT probing of the driver By providing an OF match table with a suitable compatible string, we can ensure the ux500-hasht driver is probed by supplying an associated DT node in a given platform's Device Tree. Cc: linux-crypto@vger.kernel.org Acked-by: Herbert Xu Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_core.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers') diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index cf5508967539..3b8f661d0edf 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -1961,6 +1961,11 @@ static int ux500_hash_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume); +static const struct of_device_id ux500_hash_match[] = { + { .compatible = "stericsson,ux500-hash" }, + { }, +}; + static struct platform_driver hash_driver = { .probe = ux500_hash_probe, .remove = ux500_hash_remove, @@ -1968,6 +1973,7 @@ static struct platform_driver hash_driver = { .driver = { .owner = THIS_MODULE, .name = "hash1", + .of_match_table = ux500_hash_match, .pm = &ux500_hash_pm, } }; -- cgit v1.2.3 From 6b09a83429816e71c18a8d5518618e3f5f30b7fd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 22 May 2013 15:23:00 +0100 Subject: pinctrl/nomadik: Standardise Pinctrl compat string for DBx5x based platforms Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-nomadik.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 34281754b629..7c44f1a57e7c 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -2108,11 +2108,11 @@ static const struct of_device_id nmk_pinctrl_match[] = { .data = (void *)PINCTRL_NMK_STN8815, }, { - .compatible = "stericsson,nmk-pinctrl", + .compatible = "stericsson,db8500-pinctrl", .data = (void *)PINCTRL_NMK_DB8500, }, { - .compatible = "stericsson,nmk-pinctrl-db8540", + .compatible = "stericsson,db8540-pinctrl", .data = (void *)PINCTRL_NMK_DB8540, }, {}, -- cgit v1.2.3 From 3fd765a91749b14af7e76bec7f6e0b364f8d99af Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 22 May 2013 15:22:59 +0100 Subject: pinctrl/nomadik: Standardise Pinctrl compat string for Nomadik based platforms Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-nomadik.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 34281754b629..7712d9318202 100644 --- a/drivers/pinctrl/pinctrl-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c @@ -2104,7 +2104,7 @@ static struct pinctrl_desc nmk_pinctrl_desc = { static const struct of_device_id nmk_pinctrl_match[] = { { - .compatible = "stericsson,nmk-pinctrl-stn8815", + .compatible = "stericsson,stn8815-pinctrl", .data = (void *)PINCTRL_NMK_STN8815, }, { -- cgit v1.2.3 From 3c09f4daeee83b76779dec766f57e9e883402bb1 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 31 May 2013 17:49:28 +0200 Subject: ARM: nomadik: fix clocksource warning The clocksource API has changed slightly, which causes a harmless warning: /git/arm-soc/drivers/clocksource/nomadik-mtu.c:259:28: warning: 'nmdk_timer_match' defined but not used [-Wunused-variable] static struct of_device_id nmdk_timer_match[] __initconst = { ^ Fortunately, the same API change also lets us simplify the code while removing the warning. Signed-off-by: Arnd Bergmann Signed-off-by: Olof Johansson --- drivers/clocksource/nomadik-mtu.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c index 7982cb0f25f2..b9415b622f55 100644 --- a/drivers/clocksource/nomadik-mtu.c +++ b/drivers/clocksource/nomadik-mtu.c @@ -256,23 +256,13 @@ void __init nmdk_timer_init(void __iomem *base, int irq) __nmdk_timer_init(base, irq, pclk0, clk0); } -static struct of_device_id nmdk_timer_match[] __initconst = { - { .compatible = "st,nomadik-mtu" }, - {} -}; - -static void __init nmdk_timer_of_init(void) +static void __init nmdk_timer_of_init(struct device_node *node) { - struct device_node *node; struct clk *pclk; struct clk *clk; void __iomem *base; int irq; - node = of_find_matching_node(NULL, nmdk_timer_match); - if (!node) - panic("No timer node"); - base = of_iomap(node, 0); if (!base) panic("Can't remap registers"); -- cgit v1.2.3 From 5510ed9f051d1d412309d3beafed7d2ef9a59b28 Mon Sep 17 00:00:00 2001 From: Fabio Baltieri Date: Thu, 30 May 2013 15:27:42 +0200 Subject: ARM: ux500: Correct anamic2 typo in DT files Fix typo of VAMIC2 LDO regulator name in some DT-related files. This patch replaces all occurrences with the right name. Signed-off-by: Fabio Baltieri Acked-by: Lee Jones Signed-off-by: Linus Walleij --- arch/arm/boot/dts/dbx5x0.dtsi | 4 ++-- arch/arm/boot/dts/href.dtsi | 2 +- arch/arm/boot/dts/hrefv60plus.dts | 2 +- arch/arm/boot/dts/snowball.dts | 2 +- drivers/regulator/ab8500.c | 8 ++++---- 5 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi index 07c8c0f82c9d..27e7dafbc12c 100644 --- a/arch/arm/boot/dts/dbx5x0.dtsi +++ b/arch/arm/boot/dts/dbx5x0.dtsi @@ -500,8 +500,8 @@ }; // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { - regulator-compatible = "ab8500_ldo_amamic2"; + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { + regulator-compatible = "ab8500_ldo_anamic2"; }; // supply for v-dmic; VDMIC LDO diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi index 0485519673c2..080c53065dd6 100644 --- a/arch/arm/boot/dts/href.dtsi +++ b/arch/arm/boot/dts/href.dtsi @@ -283,7 +283,7 @@ regulator-name = "V-AMIC1"; }; - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { regulator-name = "V-AMIC2"; }; diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts index b4b05df36733..3d580d6447f9 100644 --- a/arch/arm/boot/dts/hrefv60plus.dts +++ b/arch/arm/boot/dts/hrefv60plus.dts @@ -192,7 +192,7 @@ regulator-name = "V-AMIC1"; }; - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { regulator-name = "V-AMIC2"; }; diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index 06982dd74e5c..92c2f5ad0ac1 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts @@ -342,7 +342,7 @@ regulator-name = "V-AMIC1"; }; - ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { + ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 { regulator-name = "V-AMIC2"; }; diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c index f6656b8c28b6..a19045ee0ec4 100644 --- a/drivers/regulator/ab8500.c +++ b/drivers/regulator/ab8500.c @@ -2901,7 +2901,7 @@ static struct of_regulator_match ab8500_regulator_match[] = { { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8500_LDO_TVOUT, }, { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8500_LDO_AUDIO, }, { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, }, - { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, + { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, }, { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8500_LDO_DMIC, }, { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8500_LDO_ANA, }, }; @@ -2917,7 +2917,7 @@ static struct of_regulator_match ab8505_regulator_match[] = { { .name = "ab8500_ldo_adc", .driver_data = (void *) AB8505_LDO_ADC, }, { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8505_LDO_AUDIO, }, { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, }, - { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, + { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, }, { .name = "ab8500_ldo_aux8", .driver_data = (void *) AB8505_LDO_AUX8, }, { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8505_LDO_ANA, }, }; @@ -2933,7 +2933,7 @@ static struct of_regulator_match ab8540_regulator_match[] = { { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB8540_LDO_TVOUT, }, { .name = "ab8500_ldo_audio", .driver_data = (void *) AB8540_LDO_AUDIO, }, { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, }, - { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, }, + { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, }, { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB8540_LDO_DMIC, }, { .name = "ab8500_ldo_ana", .driver_data = (void *) AB8540_LDO_ANA, }, { .name = "ab8500_ldo_sdio", .driver_data = (void *) AB8540_LDO_SDIO, }, @@ -2948,7 +2948,7 @@ static struct of_regulator_match ab9540_regulator_match[] = { { .name = "ab8500_ldo_tvout", .driver_data = (void *) AB9540_LDO_TVOUT, }, { .name = "ab8500_ldo_audio", .driver_data = (void *) AB9540_LDO_AUDIO, }, { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, }, - { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, }, + { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, }, { .name = "ab8500_ldo_dmic", .driver_data = (void *) AB9540_LDO_DMIC, }, { .name = "ab8500_ldo_ana", .driver_data = (void *) AB9540_LDO_ANA, }, }; -- cgit v1.2.3 From 5cd644d837ae8c825066c225480647eb691e027d Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Mon, 10 Jun 2013 17:49:41 +0900 Subject: clk: exynos4: Add additional G2D clocks Add G2D clocks for Exynos4x12 SoC and sclk_fimg2d required by G2D IP. Signed-off-by: Sachin Kamat Cc: Thomas Abraham Acked-by: Mike Turquette Signed-off-by: Kukjin Kim --- Documentation/devicetree/bindings/clock/exynos4-clock.txt | 3 ++- drivers/clk/samsung/clk-exynos4.c | 9 +++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index ea5e26f16aec..14d5c2af26f4 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -102,6 +102,7 @@ Exynos4 SoC and this is specified where applicable. sclk_spi0_isp 174 Exynos4x12 sclk_spi1_isp 175 Exynos4x12 sclk_uart_isp 176 Exynos4x12 + sclk_fimg2d 177 [Peripheral Clock Gates] @@ -129,7 +130,7 @@ Exynos4 SoC and this is specified where applicable. smmu_mfcl 274 smmu_mfcr 275 g3d 276 - g2d 277 Exynos4210 + g2d 277 rotator 278 Exynos4210 mdma 279 Exynos4210 smmu_g2d 280 Exynos4210 diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3c1f88868f29..addc738a06fb 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -151,7 +151,7 @@ enum exynos4_clks { sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, - sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, + sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, /* gate clocks */ fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, @@ -484,6 +484,9 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), + MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), + MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), + MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), }; /* list of divider clocks supported in all exynos4 soc's */ @@ -552,7 +555,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = { /* list of divider clocks supported in exynos4210 soc */ struct samsung_div_clock exynos4210_div_clks[] __initdata = { DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), - DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4), + DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), @@ -582,6 +585,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = { DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), + DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -909,6 +913,7 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { CLK_IGNORE_UNUSED, 0), GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED, 0), + GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), }; /* -- cgit v1.2.3 From 85bf6d4e4b100efda8169f6f98fd65d0029c7813 Mon Sep 17 00:00:00 2001 From: Huang Shijie Date: Tue, 28 May 2013 14:20:07 +0800 Subject: drivers: bus: add a new driver for WEIM The WEIM(Wireless External Interface Module) works like a bus. You can attach many different devices on it, such as NOR, onenand. In the case of i.MX6q-sabreauto, the NOR is connected to WEIM. This patch also adds the devicetree binding document. The driver only works when the devicetree is enabled. Signed-off-by: Huang Shijie Acked-by: Sascha Hauer Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/bus/imx-weim.txt | 49 ++++++++ drivers/bus/Kconfig | 9 ++ drivers/bus/Makefile | 1 + drivers/bus/imx-weim.c | 138 +++++++++++++++++++++ 4 files changed, 197 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/imx-weim.txt create mode 100644 drivers/bus/imx-weim.c (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/bus/imx-weim.txt b/Documentation/devicetree/bindings/bus/imx-weim.txt new file mode 100644 index 000000000000..cedc2a9c4785 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/imx-weim.txt @@ -0,0 +1,49 @@ +Device tree bindings for i.MX Wireless External Interface Module (WEIM) + +The term "wireless" does not imply that the WEIM is literally an interface +without wires. It simply means that this module was originally designed for +wireless and mobile applications that use low-power technology. + +The actual devices are instantiated from the child nodes of a WEIM node. + +Required properties: + + - compatible: Should be set to "fsl,imx6q-weim" + - reg: A resource specifier for the register space + (see the example below) + - clocks: the clock, see the example below. + - #address-cells: Must be set to 2 to allow memory address translation + - #size-cells: Must be set to 1 to allow CS address passing + - ranges: Must be set up to reflect the memory layout with four + integer values for each chip-select line in use: + + 0 + +Timing property for child nodes. It is mandatory, not optional. + + - fsl,weim-cs-timing: The timing array, contains 6 timing values for the + child node. We can get the CS index from the child + node's "reg" property. This property contains the values + for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1, + EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order. + +Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM: + + weim: weim@021b8000 { + compatible = "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + clocks = <&clks 196>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x08000000 0x08000000>; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; + }; diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index b05ecab915c4..46cd5bb098a9 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -4,6 +4,15 @@ menu "Bus devices" +config IMX_WEIM + bool "Freescale EIM DRIVER" + depends on ARCH_MXC + help + Driver for i.MX6 WEIM controller. + The WEIM(Wireless External Interface Module) works like a bus. + You can attach many different devices on it, such as NOR, onenand. + But now, we only support the Parallel NOR. + config MVEBU_MBUS bool depends on PLAT_ORION diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 3c7b53c12091..436bbccf4894 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -2,6 +2,7 @@ # Makefile for the bus drivers. # +obj-$(CONFIG_IMX_WEIM) += imx-weim.o obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c new file mode 100644 index 000000000000..349f14e886b7 --- /dev/null +++ b/drivers/bus/imx-weim.c @@ -0,0 +1,138 @@ +/* + * EIM driver for Freescale's i.MX chips + * + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include +#include +#include +#include + +struct imx_weim { + void __iomem *base; + struct clk *clk; +}; + +static const struct of_device_id weim_id_table[] = { + { .compatible = "fsl,imx6q-weim", }, + {} +}; +MODULE_DEVICE_TABLE(of, weim_id_table); + +#define CS_TIMING_LEN 6 +#define CS_REG_RANGE 0x18 + +/* Parse and set the timing for this device. */ +static int +weim_timing_setup(struct platform_device *pdev, struct device_node *np) +{ + struct imx_weim *weim = platform_get_drvdata(pdev); + u32 value[CS_TIMING_LEN]; + u32 cs_idx; + int ret; + int i; + + /* get the CS index from this child node's "reg" property. */ + ret = of_property_read_u32(np, "reg", &cs_idx); + if (ret) + return ret; + + /* The weim has four chip selects. */ + if (cs_idx > 3) + return -EINVAL; + + ret = of_property_read_u32_array(np, "fsl,weim-cs-timing", + value, CS_TIMING_LEN); + if (ret) + return ret; + + /* set the timing for WEIM */ + for (i = 0; i < CS_TIMING_LEN; i++) + writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4); + return 0; +} + +static int weim_parse_dt(struct platform_device *pdev) +{ + struct device_node *child; + int ret; + + for_each_child_of_node(pdev->dev.of_node, child) { + if (!child->name) + continue; + + ret = weim_timing_setup(pdev, child); + if (ret) { + dev_err(&pdev->dev, "%s set timing failed.\n", + child->full_name); + return ret; + } + } + + ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); + if (ret) + dev_err(&pdev->dev, "%s fail to create devices.\n", + pdev->dev.of_node->full_name); + return ret; +} + +static int weim_probe(struct platform_device *pdev) +{ + struct imx_weim *weim; + struct resource *res; + int ret = -EINVAL; + + weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL); + if (!weim) { + ret = -ENOMEM; + goto weim_err; + } + platform_set_drvdata(pdev, weim); + + /* get the resource */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + weim->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(weim->base)) { + ret = PTR_ERR(weim->base); + goto weim_err; + } + + /* get the clock */ + weim->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(weim->clk)) + goto weim_err; + + ret = clk_prepare_enable(weim->clk); + if (ret) + goto weim_err; + + /* parse the device node */ + ret = weim_parse_dt(pdev); + if (ret) { + clk_disable_unprepare(weim->clk); + goto weim_err; + } + + dev_info(&pdev->dev, "WEIM driver registered.\n"); + return 0; + +weim_err: + return ret; +} + +static struct platform_driver weim_driver = { + .driver = { + .name = "imx-weim", + .of_match_table = weim_id_table, + }, + .probe = weim_probe, +}; + +module_platform_driver(weim_driver); +MODULE_AUTHOR("Freescale Semiconductor Inc."); +MODULE_DESCRIPTION("i.MX EIM Controller Driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 894db164260c39870ea79e473e1307b4aa5e4257 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Thu, 13 Jun 2013 11:23:38 +0200 Subject: irqchip: renesas-intc-irqpin: DT binding for sense bitfield width Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: Guennadi Liakhovetski Acked-by: Arnd Bergmann Signed-off-by: Simon Horman --- .../bindings/interrupt-controller/renesas,intc-irqpin.txt | 14 ++++++++++++++ drivers/irqchip/irq-renesas-intc-irqpin.c | 4 ++++ 2 files changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt new file mode 100644 index 000000000000..66fcaf5b09ff --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -0,0 +1,14 @@ +DT bindings for the R-/SH-Mobile irqpin controller + +Required properties: + +- compatible: has to be "renesas,intc-irqpin" +- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in + interrupts.txt in this directory + +Optional properties: + +- any properties, listed in interrupts.txt, and any standard resource allocation + properties +- sense-bitfield-width: width of a single sense bitfield in the SENSE register, + if different from the default 4 bits diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 5a68e5accec1..4aca1b2bcc48 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -18,6 +18,7 @@ */ #include +#include #include #include #include @@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device *pdev) /* deal with driver instance configuration */ if (pdata) memcpy(&p->config, pdata, sizeof(*pdata)); + else + of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", + &p->config.sense_bitfield_width); if (!p->config.sense_bitfield_width) p->config.sense_bitfield_width = 4; /* default to 4 bits */ -- cgit v1.2.3 From c4fa4946f177ae214523586cd794ac18d34b1430 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Wed, 19 Jun 2013 07:53:09 +0200 Subject: ARM: shmobile: irqpin: add a DT property to enable masking on parent To disable spurious interrupts, that get triggered on certain hardware, the irqpin driver masks them on the parent interrupt controller. To specify such broken devices a .control_parent parameter can be provided in the platform data. In the DT case we need a property, to do the same. Signed-off-by: Guennadi Liakhovetski Acked-by: Magnus Damm Signed-off-by: Simon Horman --- .../bindings/interrupt-controller/renesas,intc-irqpin.txt | 2 ++ drivers/irqchip/irq-renesas-intc-irqpin.c | 7 +++++-- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt index 66fcaf5b09ff..1f8b0c507c26 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt @@ -12,3 +12,5 @@ Optional properties: properties - sense-bitfield-width: width of a single sense bitfield in the SENSE register, if different from the default 4 bits +- control-parent: disable and enable interrupts on the parent interrupt + controller, needed for some broken implementations diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c index 4aca1b2bcc48..82cec63a9011 100644 --- a/drivers/irqchip/irq-renesas-intc-irqpin.c +++ b/drivers/irqchip/irq-renesas-intc-irqpin.c @@ -348,11 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev) } /* deal with driver instance configuration */ - if (pdata) + if (pdata) { memcpy(&p->config, pdata, sizeof(*pdata)); - else + } else { of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", &p->config.sense_bitfield_width); + p->config.control_parent = of_property_read_bool(pdev->dev.of_node, + "control-parent"); + } if (!p->config.sense_bitfield_width) p->config.sense_bitfield_width = 4; /* default to 4 bits */ -- cgit v1.2.3 From ef6eb322ce574ba73658a677e83e5da3cfab301b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 4 Jun 2013 23:17:21 +0200 Subject: clk: nomadik: implement the Nomadik clocks properly The Nomadik clock implementation was a stub just using fixed clocks. This implements the clocks properly instead of relying on them all being on at boot and leaving them all on. The PLLs are on the top locking to the main chrystal oscillator, then the HCLK for the peripherals are below PLL2. The gated clocks are implemented with zero cells and given the clock ID as a property of each node, so every gate need to have its own node in the device tree. This is because the gate registers contain both HCLK gates and PCLK gates, where the latter has HCLK as parent. As can be seen from the register layout, this is a complete mixup, which means all these gates need their own node to properly model parent/child relations for PCLKs apart from the HCLKs. This driver also adds a helpful debugfs file to inspect the hardware state of the clock gates. This is the end result in /clk/clk_summary after applying a proper device tree: ulpiclk 0 0 60000000 mxtal 3 3 19200000 pll2 1 1 864000000 clk48 3 3 48000000 rngcclk 1 1 48000000 usbmclk 0 0 48000000 mshcclk 0 0 48000000 mspclk3 0 0 48000000 x3dclk 0 0 48000000 skeclk 0 0 48000000 owmclk 0 0 48000000 mspclk2 0 0 48000000 mspclk1 0 0 48000000 uart2clk 0 0 48000000 ipbmcclk 0 0 48000000 ipi2cclk 0 0 48000000 usbclk 0 0 48000000 mspclk0 0 0 48000000 uart1clk 1 2 48000000 i2c1clk 0 0 48000000 i2c0clk 0 0 48000000 sdiclk 1 1 48000000 uart0clk 0 0 48000000 sspiclk 0 0 48000000 irdaclk 0 0 48000000 clk72 0 0 72000000 difclk 0 0 72000000 clcdclk 0 0 72000000 clk216 0 0 216000000 hsiclkrx 0 0 216000000 clk108 0 0 108000000 hsiclktx 0 0 108000000 clk27 0 0 27000000 pll1 1 1 264000000 hclk 3 3 264000000 hclkrng 1 1 264000000 hclkusbm 0 0 264000000 hclkcryp 0 0 264000000 hclkhash 0 0 264000000 hclk3d 0 0 264000000 hclkhpi 0 0 264000000 hclksva 0 0 264000000 hclksaa 0 0 264000000 hclkdif 0 0 264000000 hclkusb 0 0 264000000 hclkclcd 0 0 264000000 hclkdma1 0 0 264000000 hclksdram 0 0 264000000 hclksmc 1 1 264000000 hclkdma0 0 0 264000000 pclk 7 9 264000000 pclkmsp3 0 0 264000000 pclkmshc 0 0 264000000 pclkhsem 0 0 264000000 pclkske 0 0 264000000 pclkowm 0 0 264000000 pclkmsp2 0 0 264000000 pclkmsp1 0 0 264000000 pclkuart2 0 0 264000000 pclkxti 0 0 264000000 pclkhsi 0 0 264000000 pclkmsp0 0 0 264000000 pclkuart1 1 1 264000000 pclki2c1 0 0 264000000 pclki2c0 0 0 264000000 pclksdi 1 1 264000000 pclkuart0 1 1 264000000 pclkssp 0 0 264000000 pclkirda 0 0 264000000 timclk 1 1 2400000 Acked-by: Mike Turquette Signed-off-by: Linus Walleij --- .../devicetree/bindings/clock/st,nomadik.txt | 104 ++++ drivers/clk/clk-nomadik.c | 551 ++++++++++++++++++++- 2 files changed, 652 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/st,nomadik.txt (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt new file mode 100644 index 000000000000..7fc09773de46 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/st,nomadik.txt @@ -0,0 +1,104 @@ +ST Microelectronics Nomadik SRC System Reset and Control + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The Nomadik SRC controller is responsible of controlling chrystals, +PLLs and clock gates. + +Required properties for the SRC node: +- compatible: must be "stericsson,nomadik-src" +- reg: must contain the SRC register base and size + +Optional properties for the SRC node: +- disable-sxtalo: if present this will disable the SXTALO + i.e. the driver output for the slow 32kHz chrystal, if the + board has its own circuitry for providing this oscillator +- disable-mxtal: if present this will disable the MXTALO, + i.e. the driver output for the main (~19.2 MHz) chrystal, + if the board has its own circuitry for providing this + osciallator + + +PLL nodes: these nodes represent the two PLLs on the system, +which should both have the main chrystal, represented as a +fixed frequency clock, as parent. + +Required properties for the two PLL nodes: +- compatible: must be "st,nomadik-pll-clock" +- clock-cells: must be 0 +- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively +- clocks: this clock will have main chrystal as parent + + +HCLK nodes: these represent the clock gates on individual +lines from the HCLK clock tree and the gate for individual +lines from the PCLK clock tree. + +Requires properties for the HCLK nodes: +- compatible: must be "st,nomadik-hclk-clock" +- clock-cells: must be 0 +- clock-id: must be the clock ID from 0 to 63 according to + this table: + + 0: HCLKDMA0 + 1: HCLKSMC + 2: HCLKSDRAM + 3: HCLKDMA1 + 4: HCLKCLCD + 5: PCLKIRDA + 6: PCLKSSP + 7: PCLKUART0 + 8: PCLKSDI + 9: PCLKI2C0 + 10: PCLKI2C1 + 11: PCLKUART1 + 12: PCLMSP0 + 13: HCLKUSB + 14: HCLKDIF + 15: HCLKSAA + 16: HCLKSVA + 17: PCLKHSI + 18: PCLKXTI + 19: PCLKUART2 + 20: PCLKMSP1 + 21: PCLKMSP2 + 22: PCLKOWM + 23: HCLKHPI + 24: PCLKSKE + 25: PCLKHSEM + 26: HCLK3D + 27: HCLKHASH + 28: HCLKCRYP + 29: PCLKMSHC + 30: HCLKUSBM + 31: HCLKRNG + (32, 33, 34, 35 RESERVED) + 36: CLDCLK + 37: IRDACLK + 38: SSPICLK + 39: UART0CLK + 40: SDICLK + 41: I2C0CLK + 42: I2C1CLK + 43: UART1CLK + 44: MSPCLK0 + 45: USBCLK + 46: DIFCLK + 47: IPI2CCLK + 48: IPBMCCLK + 49: HSICLKRX + 50: HSICLKTX + 51: UART2CLK + 52: MSPCLK1 + 53: MSPCLK2 + 54: OWMCLK + (55 RESERVED) + 56: SKECLK + (57 RESERVED) + 58: 3DCLK + 59: PCLKMSP3 + 60: MSPCLK3 + 61: MSHCCLK + 62: USBMCLK + 63: RNGCCLK diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c index 4a1ab27ee87f..6d819a37f647 100644 --- a/drivers/clk/clk-nomadik.c +++ b/drivers/clk/clk-nomadik.c @@ -1,21 +1,566 @@ +/* + * Nomadik clock implementation + * Copyright (C) 2013 ST-Ericsson AB + * License terms: GNU General Public License (GPL) version 2 + * Author: Linus Walleij + */ + +#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt + +#include #include #include #include #include #include #include +#include +#include +#include +#include +#include /* * The Nomadik clock tree is described in the STN8815A12 DB V4.2 * reference manual for the chip, page 94 ff. + * Clock IDs are in the STn8815 Reference Manual table 3, page 27. + */ + +#define SRC_CR 0x00U +#define SRC_XTALCR 0x0CU +#define SRC_XTALCR_XTALTIMEN BIT(20) +#define SRC_XTALCR_SXTALDIS BIT(19) +#define SRC_XTALCR_MXTALSTAT BIT(2) +#define SRC_XTALCR_MXTALEN BIT(1) +#define SRC_XTALCR_MXTALOVER BIT(0) +#define SRC_PLLCR 0x10U +#define SRC_PLLCR_PLLTIMEN BIT(29) +#define SRC_PLLCR_PLL2EN BIT(28) +#define SRC_PLLCR_PLL1STAT BIT(2) +#define SRC_PLLCR_PLL1EN BIT(1) +#define SRC_PLLCR_PLL1OVER BIT(0) +#define SRC_PLLFR 0x14U +#define SRC_PCKEN0 0x24U +#define SRC_PCKDIS0 0x28U +#define SRC_PCKENSR0 0x2CU +#define SRC_PCKSR0 0x30U +#define SRC_PCKEN1 0x34U +#define SRC_PCKDIS1 0x38U +#define SRC_PCKENSR1 0x3CU +#define SRC_PCKSR1 0x40U + +/* Lock protecting the SRC_CR register */ +static DEFINE_SPINLOCK(src_lock); +/* Base address of the SRC */ +static void __iomem *src_base; + +/** + * struct clk_pll1 - Nomadik PLL1 clock + * @hw: corresponding clock hardware entry + * @id: PLL instance: 1 or 2 + */ +struct clk_pll { + struct clk_hw hw; + int id; +}; + +/** + * struct clk_src - Nomadik src clock + * @hw: corresponding clock hardware entry + * @id: the clock ID + * @group1: true if the clock is in group1, else it is in group0 + * @clkbit: bit 0...31 corresponding to the clock in each clock register + */ +struct clk_src { + struct clk_hw hw; + int id; + bool group1; + u32 clkbit; +}; + +#define to_pll(_hw) container_of(_hw, struct clk_pll, hw) +#define to_src(_hw) container_of(_hw, struct clk_src, hw) + +static int pll_clk_enable(struct clk_hw *hw) +{ + struct clk_pll *pll = to_pll(hw); + u32 val; + + spin_lock(&src_lock); + val = readl(src_base + SRC_PLLCR); + if (pll->id == 1) { + if (val & SRC_PLLCR_PLL1OVER) { + val |= SRC_PLLCR_PLL1EN; + writel(val, src_base + SRC_PLLCR); + } + } else if (pll->id == 2) { + val |= SRC_PLLCR_PLL2EN; + writel(val, src_base + SRC_PLLCR); + } + spin_unlock(&src_lock); + return 0; +} + +static void pll_clk_disable(struct clk_hw *hw) +{ + struct clk_pll *pll = to_pll(hw); + u32 val; + + spin_lock(&src_lock); + val = readl(src_base + SRC_PLLCR); + if (pll->id == 1) { + if (val & SRC_PLLCR_PLL1OVER) { + val &= ~SRC_PLLCR_PLL1EN; + writel(val, src_base + SRC_PLLCR); + } + } else if (pll->id == 2) { + val &= ~SRC_PLLCR_PLL2EN; + writel(val, src_base + SRC_PLLCR); + } + spin_unlock(&src_lock); +} + +static int pll_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_pll *pll = to_pll(hw); + u32 val; + + val = readl(src_base + SRC_PLLCR); + if (pll->id == 1) { + if (val & SRC_PLLCR_PLL1OVER) + return !!(val & SRC_PLLCR_PLL1EN); + } else if (pll->id == 2) { + return !!(val & SRC_PLLCR_PLL2EN); + } + return 1; +} + +static unsigned long pll_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_pll *pll = to_pll(hw); + u32 val; + + val = readl(src_base + SRC_PLLFR); + + if (pll->id == 1) { + u8 mul; + u8 div; + + mul = (val >> 8) & 0x3FU; + mul += 2; + div = val & 0x07U; + return (parent_rate * mul) >> div; + } + + if (pll->id == 2) { + u8 mul; + + mul = (val >> 24) & 0x3FU; + mul += 2; + return (parent_rate * mul); + } + + /* Unknown PLL */ + return 0; +} + + +static const struct clk_ops pll_clk_ops = { + .enable = pll_clk_enable, + .disable = pll_clk_disable, + .is_enabled = pll_clk_is_enabled, + .recalc_rate = pll_clk_recalc_rate, +}; + +static struct clk * __init +pll_clk_register(struct device *dev, const char *name, + const char *parent_name, u32 id) +{ + struct clk *clk; + struct clk_pll *pll; + struct clk_init_data init; + + if (id != 1 && id != 2) { + pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__); + return ERR_PTR(-EINVAL); + } + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) { + pr_err("%s: could not allocate PLL clk\n", __func__); + return ERR_PTR(-ENOMEM); + } + + init.name = name; + init.ops = &pll_clk_ops; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + pll->hw.init = &init; + pll->id = id; + + pr_debug("register PLL1 clock \"%s\"\n", name); + + clk = clk_register(dev, &pll->hw); + if (IS_ERR(clk)) + kfree(pll); + + return clk; +} + +/* + * The Nomadik SRC clocks are gated, but not in the sense that + * you read-modify-write a register. Instead there are separate + * clock enable and clock disable registers. Writing a '1' bit in + * the enable register for a certain clock ungates that clock without + * affecting the other clocks. The disable register works the opposite + * way. */ -static const __initconst struct of_device_id cpu8815_clk_match[] = { - { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, +static int src_clk_enable(struct clk_hw *hw) +{ + struct clk_src *sclk = to_src(hw); + u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0; + u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; + + writel(sclk->clkbit, src_base + enreg); + /* spin until enabled */ + while (!(readl(src_base + sreg) & sclk->clkbit)) + cpu_relax(); + return 0; +} + +static void src_clk_disable(struct clk_hw *hw) +{ + struct clk_src *sclk = to_src(hw); + u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0; + u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; + + writel(sclk->clkbit, src_base + disreg); + /* spin until disabled */ + while (readl(src_base + sreg) & sclk->clkbit) + cpu_relax(); +} + +static int src_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_src *sclk = to_src(hw); + u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0; + u32 val = readl(src_base + sreg); + + return !!(val & sclk->clkbit); +} + +static unsigned long +src_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate; +} + +static const struct clk_ops src_clk_ops = { + .enable = src_clk_enable, + .disable = src_clk_disable, + .is_enabled = src_clk_is_enabled, + .recalc_rate = src_clk_recalc_rate, +}; + +static struct clk * __init +src_clk_register(struct device *dev, const char *name, + const char *parent_name, u8 id) +{ + struct clk *clk; + struct clk_src *sclk; + struct clk_init_data init; + + sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); + if (!sclk) { + pr_err("could not allocate SRC clock %s\n", + name); + return ERR_PTR(-ENOMEM); + } + init.name = name; + init.ops = &src_clk_ops; + /* Do not force-disable the static SDRAM controller */ + if (id == 2) + init.flags = CLK_IGNORE_UNUSED; + else + init.flags = 0; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + sclk->hw.init = &init; + sclk->id = id; + sclk->group1 = (id > 31); + sclk->clkbit = BIT(id & 0x1f); + + pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n", + name, id, sclk->group1, sclk->clkbit); + + clk = clk_register(dev, &sclk->hw); + if (IS_ERR(clk)) + kfree(sclk); + + return clk; +} + +#ifdef CONFIG_DEBUG_FS + +static u32 src_pcksr0_boot; +static u32 src_pcksr1_boot; + +static const char * const src_clk_names[] = { + "HCLKDMA0 ", + "HCLKSMC ", + "HCLKSDRAM ", + "HCLKDMA1 ", + "HCLKCLCD ", + "PCLKIRDA ", + "PCLKSSP ", + "PCLKUART0 ", + "PCLKSDI ", + "PCLKI2C0 ", + "PCLKI2C1 ", + "PCLKUART1 ", + "PCLMSP0 ", + "HCLKUSB ", + "HCLKDIF ", + "HCLKSAA ", + "HCLKSVA ", + "PCLKHSI ", + "PCLKXTI ", + "PCLKUART2 ", + "PCLKMSP1 ", + "PCLKMSP2 ", + "PCLKOWM ", + "HCLKHPI ", + "PCLKSKE ", + "PCLKHSEM ", + "HCLK3D ", + "HCLKHASH ", + "HCLKCRYP ", + "PCLKMSHC ", + "HCLKUSBM ", + "HCLKRNG ", + "RESERVED ", + "RESERVED ", + "RESERVED ", + "RESERVED ", + "CLDCLK ", + "IRDACLK ", + "SSPICLK ", + "UART0CLK ", + "SDICLK ", + "I2C0CLK ", + "I2C1CLK ", + "UART1CLK ", + "MSPCLK0 ", + "USBCLK ", + "DIFCLK ", + "IPI2CCLK ", + "IPBMCCLK ", + "HSICLKRX ", + "HSICLKTX ", + "UART2CLK ", + "MSPCLK1 ", + "MSPCLK2 ", + "OWMCLK ", + "RESERVED ", + "SKECLK ", + "RESERVED ", + "3DCLK ", + "PCLKMSP3 ", + "MSPCLK3 ", + "MSHCCLK ", + "USBMCLK ", + "RNGCCLK ", +}; + +static int nomadik_src_clk_show(struct seq_file *s, void *what) +{ + int i; + u32 src_pcksr0 = readl(src_base + SRC_PCKSR0); + u32 src_pcksr1 = readl(src_base + SRC_PCKSR1); + u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0); + u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1); + + seq_printf(s, "Clock: Boot: Now: Request: ASKED:\n"); + for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) { + u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot; + u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1; + u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1; + u32 mask = BIT(i & 0x1f); + + seq_printf(s, "%s %s %s %s\n", + src_clk_names[i], + (pcksrb & mask) ? "on " : "off", + (pcksr & mask) ? "on " : "off", + (pckreq & mask) ? "on " : "off"); + } + return 0; +} + +static int nomadik_src_clk_open(struct inode *inode, struct file *file) +{ + return single_open(file, nomadik_src_clk_show, NULL); +} + +static const struct file_operations nomadik_src_clk_debugfs_ops = { + .open = nomadik_src_clk_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init nomadik_src_clk_init_debugfs(void) +{ + src_pcksr0_boot = readl(src_base + SRC_PCKSR0); + src_pcksr1_boot = readl(src_base + SRC_PCKSR1); + debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO, + NULL, NULL, &nomadik_src_clk_debugfs_ops); + return 0; +} + +module_init(nomadik_src_clk_init_debugfs); + +#endif + +static void __init of_nomadik_pll_setup(struct device_node *np) +{ + struct clk *clk = ERR_PTR(-EINVAL); + const char *clk_name = np->name; + const char *parent_name; + u32 pll_id; + + if (of_property_read_u32(np, "pll-id", &pll_id)) { + pr_err("%s: PLL \"%s\" missing pll-id property\n", + __func__, clk_name); + return; + } + parent_name = of_clk_get_parent_name(np, 0); + clk = pll_clk_register(NULL, clk_name, parent_name, pll_id); + if (!IS_ERR(clk)) + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} + +static void __init of_nomadik_hclk_setup(struct device_node *np) +{ + struct clk *clk = ERR_PTR(-EINVAL); + const char *clk_name = np->name; + const char *parent_name; + + parent_name = of_clk_get_parent_name(np, 0); + /* + * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4. + */ + clk = clk_register_divider(NULL, clk_name, parent_name, + 0, src_base + SRC_CR, + 13, 2, + CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + &src_lock); + if (!IS_ERR(clk)) + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} + +static void __init of_nomadik_src_clk_setup(struct device_node *np) +{ + struct clk *clk = ERR_PTR(-EINVAL); + const char *clk_name = np->name; + const char *parent_name; + u32 clk_id; + + if (of_property_read_u32(np, "clock-id", &clk_id)) { + pr_err("%s: SRC clock \"%s\" missing clock-id property\n", + __func__, clk_name); + return; + } + parent_name = of_clk_get_parent_name(np, 0); + clk = src_clk_register(NULL, clk_name, parent_name, clk_id); + if (!IS_ERR(clk)) + of_clk_add_provider(np, of_clk_src_simple_get, clk); +} + +static const __initconst struct of_device_id nomadik_src_match[] = { + { .compatible = "stericsson,nomadik-src" }, { /* sentinel */ } }; +static const __initconst struct of_device_id nomadik_src_clk_match[] = { + { + .compatible = "fixed-clock", + .data = of_fixed_clk_setup, + }, + { + .compatible = "fixed-factor-clock", + .data = of_fixed_factor_clk_setup, + }, + { + .compatible = "st,nomadik-pll-clock", + .data = of_nomadik_pll_setup, + }, + { + .compatible = "st,nomadik-hclk-clock", + .data = of_nomadik_hclk_setup, + }, + { + .compatible = "st,nomadik-src-clock", + .data = of_nomadik_src_clk_setup, + }, + { /* sentinel */ } +}; + +static int nomadik_clk_reboot_handler(struct notifier_block *this, + unsigned long code, + void *unused) +{ + u32 val; + + /* The main chrystal need to be enabled for reboot to work */ + val = readl(src_base + SRC_XTALCR); + val &= ~SRC_XTALCR_MXTALOVER; + val |= SRC_XTALCR_MXTALEN; + pr_crit("force-enabling MXTALO\n"); + writel(val, src_base + SRC_XTALCR); + return NOTIFY_OK; +} + +static struct notifier_block nomadik_clk_reboot_notifier = { + .notifier_call = nomadik_clk_reboot_handler, +}; + void __init nomadik_clk_init(void) { - of_clk_init(cpu8815_clk_match); + struct device_node *np; + u32 val; + + np = of_find_matching_node(NULL, nomadik_src_match); + if (!np) { + pr_crit("no matching node for SRC, aborting clock init\n"); + return; + } + src_base = of_iomap(np, 0); + if (!src_base) { + pr_err("%s: must have src parent node with REGS (%s)\n", + __func__, np->name); + return; + } + val = readl(src_base + SRC_XTALCR); + pr_info("SXTALO is %s\n", + (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); + pr_info("MXTAL is %s\n", + (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled"); + if (of_property_read_bool(np, "disable-sxtalo")) { + /* The machine uses an external oscillator circuit */ + val |= SRC_XTALCR_SXTALDIS; + pr_info("disabling SXTALO\n"); + } + if (of_property_read_bool(np, "disable-mxtalo")) { + /* Disable this too: also run by external oscillator */ + val |= SRC_XTALCR_MXTALOVER; + val &= ~SRC_XTALCR_MXTALEN; + pr_info("disabling MXTALO\n"); + } + writel(val, src_base + SRC_XTALCR); + register_reboot_notifier(&nomadik_clk_reboot_notifier); + + of_clk_init(nomadik_src_clk_match); } -- cgit v1.2.3