From 9a519f62a18c258c8ba695f82b6a9542bde4ca06 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Thu, 8 Nov 2007 14:44:44 +0900 Subject: rtc: rtc-sh: SH-5 support. Trivial support for the SH-5 (sh64) on-chip RTC. Signed-off-by: Paul Mundt --- drivers/rtc/Kconfig | 2 +- drivers/rtc/rtc-sh.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 1e6715ec51ef..5900c772a1bc 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -404,7 +404,7 @@ config RTC_DRV_SA1100 config RTC_DRV_SH tristate "SuperH On-Chip RTC" - depends on RTC_CLASS && (CPU_SH3 || CPU_SH4) + depends on RTC_CLASS && (CPU_SH3 || CPU_SH4 || CPU_SH5) help Say Y here to enable support for the on-chip RTC found in most SuperH processors. diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c index 8e8c8b8e81ee..a1d5d55985f6 100644 --- a/drivers/rtc/rtc-sh.c +++ b/drivers/rtc/rtc-sh.c @@ -26,7 +26,7 @@ #include #define DRV_NAME "sh-rtc" -#define DRV_VERSION "0.1.3" +#define DRV_VERSION "0.1.4" #ifdef CONFIG_CPU_SH3 #define rtc_reg_size sizeof(u16) @@ -36,6 +36,10 @@ #define rtc_reg_size sizeof(u32) #define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR +#elif defined(CONFIG_CPU_SH5) +#define rtc_reg_size sizeof(u32) +#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */ +#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR #endif #define RTC_REG(r) ((r) * rtc_reg_size) -- cgit v1.2.3 From ff1b7506051014cc38036401b89e426bf3d6a608 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 26 Nov 2007 17:56:31 +0900 Subject: rtc: rtc-sh: SH-2A support. Trivial support for the SH-2A on-chip RTC. Signed-off-by: Paul Mundt --- drivers/rtc/Kconfig | 2 +- drivers/rtc/rtc-sh.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 5900c772a1bc..45e4b9648176 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -404,7 +404,7 @@ config RTC_DRV_SA1100 config RTC_DRV_SH tristate "SuperH On-Chip RTC" - depends on RTC_CLASS && (CPU_SH3 || CPU_SH4 || CPU_SH5) + depends on RTC_CLASS && SUPERH help Say Y here to enable support for the on-chip RTC found in most SuperH processors. diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c index a1d5d55985f6..af9bc57c8920 100644 --- a/drivers/rtc/rtc-sh.c +++ b/drivers/rtc/rtc-sh.c @@ -26,9 +26,13 @@ #include #define DRV_NAME "sh-rtc" -#define DRV_VERSION "0.1.4" +#define DRV_VERSION "0.1.5" -#ifdef CONFIG_CPU_SH3 +#ifdef CONFIG_CPU_SH2A +#define rtc_reg_size sizeof(u16) +#define RTC_BIT_INVERTED 0 +#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR +#elif defined(CONFIG_CPU_SH3) #define rtc_reg_size sizeof(u16) #define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */ #define RTC_DEF_CAPABILITIES 0UL @@ -62,6 +66,18 @@ #define RCR1 RTC_REG(14) /* Control */ #define RCR2 RTC_REG(15) /* Control */ +/* + * Note on RYRAR and RCR3: Up until this point most of the register + * definitions are consistent across all of the available parts. However, + * the placement of the optional RYRAR and RCR3 (the RYRAR control + * register used to control RYRCNT/RYRAR compare) varies considerably + * across various parts, occasionally being mapped in to a completely + * unrelated address space. For proper RYRAR support a separate resource + * would have to be handed off, but as this is purely optional in + * practice, we simply opt not to support it, thereby keeping the code + * quite a bit more simplified. + */ + /* ALARM Bits - or with BCD encoded value */ #define AR_ENB 0x80 /* Enable for alarm cmp */ -- cgit v1.2.3 From 6d01f51086cf6c475470cdae67d2f45e5fb57833 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 26 Nov 2007 18:17:21 +0900 Subject: sh: Add SH7203 CPU support. This adds support for the SH7203 (SH-2A) CPU. Signed-off-by: Kieran Bingham Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 8 +- arch/sh/Kconfig.debug | 1 + arch/sh/kernel/cpu/sh2a/Makefile | 1 + arch/sh/kernel/cpu/sh2a/clock-sh7203.c | 89 +++++++++++ arch/sh/kernel/cpu/sh2a/probe.c | 19 ++- arch/sh/kernel/cpu/sh2a/setup-sh7203.c | 281 +++++++++++++++++++++++++++++++++ arch/sh/kernel/setup.c | 1 + arch/sh/kernel/timers/timer-cmt.c | 2 +- drivers/serial/sh-sci.h | 6 +- include/asm-sh/bugs.h | 2 +- include/asm-sh/cpu-sh2a/freq.h | 2 - include/asm-sh/processor.h | 2 +- 12 files changed, 399 insertions(+), 15 deletions(-) create mode 100644 arch/sh/kernel/cpu/sh2a/clock-sh7203.c create mode 100644 arch/sh/kernel/cpu/sh2a/setup-sh7203.c (limited to 'drivers') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index d99ba375cc87..d8f62b842656 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -158,6 +158,10 @@ config CPU_SUBTYPE_SH7619 # SH-2A Processor Support +config CPU_SUBTYPE_SH7203 + bool "Support SH7203 processor" + select CPU_SH2A + config CPU_SUBTYPE_SH7206 bool "Support SH7206 processor" select CPU_SH2A @@ -556,7 +560,7 @@ config SH_PCLK_FREQ default "32000000" if CPU_SUBTYPE_SH7722 default "33333333" if CPU_SUBTYPE_SH7770 || \ CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \ - CPU_SUBTYPE_SH7206 + CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R default "66000000" if CPU_SUBTYPE_SH4_202 default "50000000" @@ -567,7 +571,7 @@ config SH_PCLK_FREQ config SH_CLK_MD int "CPU Mode Pin Setting" - depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206 + depends on CPU_SH2 default 6 if CPU_SUBTYPE_SH7206 default 5 if CPU_SUBTYPE_SH7619 default 0 diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 89bc174f25c7..f7e362c9d76d 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -32,6 +32,7 @@ config EARLY_SCIF_CONSOLE_PORT depends on EARLY_SCIF_CONSOLE default "0xffe00000" if CPU_SUBTYPE_SH7780 default "0xffea0000" if CPU_SUBTYPE_SH7785 + default "0xfffe8000" if CPU_SUBTYPE_SH7203 default "0xfffe9800" if CPU_SUBTYPE_SH7206 default "0xf8420000" if CPU_SUBTYPE_SH7619 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index 965fa2572b23..5286eeff1cc3 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -7,3 +7,4 @@ obj-y := common.o probe.o opcode_helper.o common-y += $(addprefix ../sh2/, ex.o entry.o) obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o +obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c new file mode 100644 index 000000000000..3feb95a4fcbc --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c @@ -0,0 +1,89 @@ +/* + * arch/sh/kernel/cpu/sh2a/clock-sh7203.c + * + * SH7203 support for the clock framework + * + * Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd) + * + * Based on clock-sh7263.c + * Copyright (C) 2006 Yoshinori Sato + * + * Based on clock-sh4.c + * Copyright (C) 2005 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +const static int pll1rate[]={8,12,16,0}; +const static int pfc_divisors[]={1,2,3,4,6,8,12}; +#define ifc_divisors pfc_divisors + +#if (CONFIG_SH_CLK_MD == 0) +#define PLL2 (1) +#elif (CONFIG_SH_CLK_MD == 1) +#define PLL2 (2) +#elif (CONFIG_SH_CLK_MD == 2) +#define PLL2 (4) +#elif (CONFIG_SH_CLK_MD == 3) +#define PLL2 (4) +#else +#error "Illegal Clock Mode!" +#endif + +static void master_clk_init(struct clk *clk) +{ + clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ; +} + +static struct clk_ops sh7203_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(FREQCR) & 0x0007); + clk->rate = clk->parent->rate / pfc_divisors[idx]; +} + +static struct clk_ops sh7203_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = (ctrl_inw(FREQCR) & 0x0007); + clk->rate = clk->parent->rate / pfc_divisors[idx-2]; +} + +static struct clk_ops sh7203_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate; +} + +static struct clk_ops sh7203_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *sh7203_clk_ops[] = { + &sh7203_master_clk_ops, + &sh7203_module_clk_ops, + &sh7203_bus_clk_ops, + &sh7203_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + if (idx < ARRAY_SIZE(sh7203_clk_ops)) + *ops = sh7203_clk_ops[idx]; +} diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 6d02465704b9..64f10102b720 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -3,25 +3,33 @@ * * CPU Subtype Probing for SH-2A. * - * Copyright (C) 2004, 2005 Paul Mundt + * Copyright (C) 2004 - 2007 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ - #include #include #include int __init detect_cpu_and_cache_system(void) { - /* Just SH7206 for now .. */ - boot_cpu_data.type = CPU_SH7206; + /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */ boot_cpu_data.flags |= CPU_HAS_OP32; +#if defined(CONFIG_CPU_SUBTYPE_SH7203) + boot_cpu_data.type = CPU_SH7203; + /* SH7203 has an FPU.. */ + boot_cpu_data.flags |= CPU_HAS_FPU; +#elif defined(CONFIG_CPU_SUBTYPE_SH7206) + boot_cpu_data.type = CPU_SH7206; + /* While SH7206 has a DSP.. */ + boot_cpu_data.flags |= CPU_HAS_DSP; +#endif + boot_cpu_data.dcache.ways = 4; - boot_cpu_data.dcache.way_incr = (1 << 11); + boot_cpu_data.dcache.way_incr = (1 << 11); boot_cpu_data.dcache.sets = 128; boot_cpu_data.dcache.entry_shift = 4; boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; @@ -37,4 +45,3 @@ int __init detect_cpu_and_cache_system(void) return 0; } - diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c new file mode 100644 index 000000000000..06f27c8b8583 --- /dev/null +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c @@ -0,0 +1,281 @@ +/* + * SH7203 Setup + * + * Copyright (C) 2007 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +enum { + UNUSED = 0, + + /* interrupt sources */ + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, + DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI, + DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI, + DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI, + DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI, + USB, LCDC, CMT0, CMT1, BSC, WDT, + MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D, + MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F, + MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U, + MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U, + MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V, + MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V, + ADC_ADI, + IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI, + IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI, + IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI, + IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI, + SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI, + SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI, + SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI, + SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI, + SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI, + SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI, + SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + RTC_ARM, RTC_PRD, RTC_CUP, + RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE, + RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE, + + /* interrupt groups */ + PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, + MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, + MTU3_ABCD, MTU4_ABCD, + IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3, + SSU0, SSU1, FLCTL, RTC, RCAN0, RCAN1 +}; + +static struct intc_vect vectors[] __initdata = { + INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), + INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), + INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), + INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), + INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), + INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), + INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), + INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), + INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109), + INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113), + INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117), + INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121), + INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125), + INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129), + INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133), + INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137), + INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141), + INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143), + INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145), + INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147), + INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149), + INTC_IRQ(MTU2_TCI0V, 150), + INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152), + INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154), + INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156), + INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158), + INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160), + INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162), + INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164), + INTC_IRQ(MTU2_TCI3V, 165), + INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167), + INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169), + INTC_IRQ(MTU2_TCI4V, 170), + INTC_IRQ(ADC_ADI, 171), + INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173), + INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175), + INTC_IRQ(IIC30_TEI, 176), + INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178), + INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180), + INTC_IRQ(IIC31_TEI, 181), + INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183), + INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185), + INTC_IRQ(IIC32_TEI, 186), + INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188), + INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190), + INTC_IRQ(IIC33_TEI, 191), + INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193), + INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195), + INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197), + INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199), + INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201), + INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203), + INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205), + INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207), + INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209), + INTC_IRQ(SSU0_SSTXI, 210), + INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212), + INTC_IRQ(SSU1_SSTXI, 213), + INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215), + INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217), + INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225), + INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227), + INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232), + INTC_IRQ(RTC_CUP, 233), + INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235), + INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237), + INTC_IRQ(RCAN0_SLE, 238), + INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240), + INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242), + INTC_IRQ(RCAN1_SLE, 243), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, + PINT4, PINT5, PINT6, PINT7), + INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI), + INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI), + INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI), + INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI), + INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI), + INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI), + INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI), + INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI), + INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D), + INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F), + INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B), + INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U), + INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B), + INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U), + INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D), + INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D), + INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, + IIC30_TEI), + INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, + IIC31_TEI), + INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, + IIC32_TEI), + INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, + IIC33_TEI), + INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI), + INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI), + INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), + INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI), + INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI), + INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI), + INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, + FLCTL_FLTREQ1I), + INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP), + INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, + RCAN0_SLE), + INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, + RCAN1_SLE), +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, + { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, + { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } }, + { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } }, + { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } }, + { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } }, + { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } }, + { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB, + MTU2_VU } }, + { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD, + MTU2_TCI4V } }, + { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } }, + { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } }, + { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } }, + { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, + SSI3_SSII, 0 } }, + { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } }, + { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } }, +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xfffe0808, 0, 16, /* PINTER */ + { 0, 0, 0, 0, 0, 0, 0, 0, + PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, + NULL, mask_registers, prio_registers, NULL); + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xfffe8000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 193, 194, 195, 192 }, + }, { + .mapbase = 0xfffe8800, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 197, 198, 199, 196 }, + }, { + .mapbase = 0xfffe9000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 201, 202, 203, 200 }, + }, { + .mapbase = 0xfffe9800, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 205, 206, 207, 204 }, + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xffff2000, + .end = 0xffff2000 + 0x58 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 232, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 233, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 231, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static struct platform_device *sh7203_devices[] __initdata = { + &sci_device, + &rtc_device, +}; + +static int __init sh7203_devices_setup(void) +{ + return platform_add_devices(sh7203_devices, + ARRAY_SIZE(sh7203_devices)); +} +__initcall(sh7203_devices_setup); + +void __init plat_irq_setup(void) +{ + register_intc_controller(&intc_desc); +} diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 1ec40091a4e8..c5a453fb19ca 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -294,6 +294,7 @@ void __init setup_arch(char **cmdline_p) } static const char *cpu_name[] = { + [CPU_SH7203] = "SH7203", [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c index 82de6895ade5..4828a53d81ea 100644 --- a/arch/sh/kernel/timers/timer-cmt.c +++ b/arch/sh/kernel/timers/timer-cmt.c @@ -31,7 +31,7 @@ #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0) #define CMT_CMCSR_INIT 0x0040 #define CMT_CMCSR_CALIB 0x0000 -#elif defined(CONFIG_CPU_SUBTYPE_SH7206) +#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || defined(CONFIG_CPU_SUBTYPE_SH7206) #define CMT_CMSTR 0xfffec000 #define CMT_CMCSR_0 0xfffec002 #define CMT_CMCNT_0 0xfffec004 diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index d24621ce799a..cde06a481829 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -142,7 +142,8 @@ # define SCIF_OPER 0x0001 /* Overrun error bit */ # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ # define SCIF_ONLY -#elif defined(CONFIG_CPU_SUBTYPE_SH7206) +#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ + defined(CONFIG_CPU_SUBTYPE_SH7206) # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ @@ -617,7 +618,8 @@ static inline int sci_rxd_in(struct uart_port *port) return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ return 1; } -#elif defined(CONFIG_CPU_SUBTYPE_SH7206) +#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ + defined(CONFIG_CPU_SUBTYPE_SH7206) static inline int sci_rxd_in(struct uart_port *port) { if (port->mapbase == 0xfffe8000) diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h index e2d79567e2a9..94149c8a759c 100644 --- a/include/asm-sh/bugs.h +++ b/include/asm-sh/bugs.h @@ -25,7 +25,7 @@ static void __init check_bugs(void) case CPU_SH7619: *p++ = '2'; break; - case CPU_SH7206: + case CPU_SH7203 ... CPU_SH7206: *p++ = '2'; *p++ = 'a'; break; diff --git a/include/asm-sh/cpu-sh2a/freq.h b/include/asm-sh/cpu-sh2a/freq.h index e518fff6d10f..830fd43b6cdc 100644 --- a/include/asm-sh/cpu-sh2a/freq.h +++ b/include/asm-sh/cpu-sh2a/freq.h @@ -10,9 +10,7 @@ #ifndef __ASM_CPU_SH2A_FREQ_H #define __ASM_CPU_SH2A_FREQ_H -#if defined(CONFIG_CPU_SUBTYPE_SH7206) #define FREQCR 0xfffe0010 -#endif #endif /* __ASM_CPU_SH2A_FREQ_H */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 3ae2a1c223f2..70f083f07d71 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -17,7 +17,7 @@ enum cpu_type { CPU_SH7619, /* SH-2A types */ - CPU_SH7206, + CPU_SH7203, CPU_SH7206, /* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707, -- cgit v1.2.3 From a8f67f4b4d4b74cd14d3540ade8657ebee543340 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Mon, 26 Nov 2007 19:54:02 +0900 Subject: sh: Add SH7263 CPU support. This adds support for the SH7263 (SH-2A) CPU. This particular CPU is a superset of SH7203, adding some additional peripheral blocks and hooking up additional (reserved on SH7203) vectors in the INTC block. No visibly nasty surprises, yet.. Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 7 +++++- arch/sh/Kconfig.debug | 2 +- arch/sh/kernel/cpu/sh2a/Makefile | 1 + arch/sh/kernel/cpu/sh2a/probe.c | 3 +++ arch/sh/kernel/cpu/sh2a/setup-sh7203.c | 42 ++++++++++++++++++++++++++++++++-- arch/sh/kernel/setup.c | 2 +- arch/sh/kernel/timers/timer-cmt.c | 4 +++- drivers/serial/sh-sci.h | 6 +++-- include/asm-sh/bugs.h | 2 +- include/asm-sh/processor.h | 2 +- 10 files changed, 61 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index d8f62b842656..c18a5512ac82 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -166,6 +166,10 @@ config CPU_SUBTYPE_SH7206 bool "Support SH7206 processor" select CPU_SH2A +config CPU_SUBTYPE_SH7263 + bool "Support SH7263 processor" + select CPU_SH2A + # SH-3 Processor Support config CPU_SUBTYPE_SH7705 @@ -560,7 +564,8 @@ config SH_PCLK_FREQ default "32000000" if CPU_SUBTYPE_SH7722 default "33333333" if CPU_SUBTYPE_SH7770 || \ CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \ - CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 + CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \ + CPU_SUBTYPE_SH7263 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R default "66000000" if CPU_SUBTYPE_SH4_202 default "50000000" diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index f7e362c9d76d..b0dcb240d798 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -33,7 +33,7 @@ config EARLY_SCIF_CONSOLE_PORT default "0xffe00000" if CPU_SUBTYPE_SH7780 default "0xffea0000" if CPU_SUBTYPE_SH7785 default "0xfffe8000" if CPU_SUBTYPE_SH7203 - default "0xfffe9800" if CPU_SUBTYPE_SH7206 + default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 default "0xf8420000" if CPU_SUBTYPE_SH7619 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 default "0xa4430000" if CPU_SUBTYPE_SH7720 diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile index 5286eeff1cc3..50e4d0ffdd6f 100644 --- a/arch/sh/kernel/cpu/sh2a/Makefile +++ b/arch/sh/kernel/cpu/sh2a/Makefile @@ -8,3 +8,4 @@ common-y += $(addprefix ../sh2/, ex.o entry.o) obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o +obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c index 64f10102b720..6910e2664468 100644 --- a/arch/sh/kernel/cpu/sh2a/probe.c +++ b/arch/sh/kernel/cpu/sh2a/probe.c @@ -22,6 +22,9 @@ int __init detect_cpu_and_cache_system(void) boot_cpu_data.type = CPU_SH7203; /* SH7203 has an FPU.. */ boot_cpu_data.flags |= CPU_HAS_FPU; +#elif defined(CONFIG_CPU_SUBTYPE_SH7263) + boot_cpu_data.type = CPU_SH7263; + boot_cpu_data.flags |= CPU_HAS_FPU; #elif defined(CONFIG_CPU_SUBTYPE_SH7206) boot_cpu_data.type = CPU_SH7206; /* While SH7206 has a DSP.. */ diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index 06f27c8b8583..3518f9c37d93 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c @@ -1,5 +1,5 @@ /* - * SH7203 Setup + * SH7203 and SH7263 Setup * * Copyright (C) 2007 Paul Mundt * @@ -41,17 +41,27 @@ enum { SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI, SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII, + + /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */ + ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF, + ROMDEC_IREADY, + FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I, + + SDHI3, SDHI0, SDHI1, + RTC_ARM, RTC_PRD, RTC_CUP, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE, + SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI, + /* interrupt groups */ PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7, MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU, MTU3_ABCD, MTU4_ABCD, IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3, - SSU0, SSU1, FLCTL, RTC, RCAN0, RCAN1 + SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC }; static struct intc_vect vectors[] __initdata = { @@ -125,6 +135,20 @@ static struct intc_vect vectors[] __initdata = { INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240), INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242), INTC_IRQ(RCAN1_SLE, 243), + + /* SH7263-specific trash */ +#ifdef CONFIG_CPU_SUBTYPE_SH7263 + INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219), + INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221), + INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223), + + INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230), + + INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245), + INTC_IRQ(SRC_IDEI, 246), + + INTC_IRQ(IEBI, 247), +#endif }; static struct intc_group groups[] __initdata = { @@ -167,6 +191,13 @@ static struct intc_group groups[] __initdata = { RCAN0_SLE), INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE), + +#ifdef CONFIG_CPU_SUBTYPE_SH7263 + INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, + ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY), + INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1), + INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI), +#endif }; static struct intc_prio_reg prio_registers[] __initdata = { @@ -184,10 +215,17 @@ static struct intc_prio_reg prio_registers[] __initdata = { { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } }, { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } }, { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } }, +#ifdef CONFIG_CPU_SUBTYPE_SH7203 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, SSI3_SSII, 0 } }, { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } }, { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } }, +#else + { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII, + SSI3_SSII, ROMDEC } }, + { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } }, + { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } }, +#endif }; static struct intc_mask_reg mask_registers[] __initdata = { diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index c5a453fb19ca..6891cc93548e 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -294,7 +294,7 @@ void __init setup_arch(char **cmdline_p) } static const char *cpu_name[] = { - [CPU_SH7203] = "SH7203", + [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c index 4828a53d81ea..499e07beebe2 100644 --- a/arch/sh/kernel/timers/timer-cmt.c +++ b/arch/sh/kernel/timers/timer-cmt.c @@ -31,7 +31,9 @@ #define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0) #define CMT_CMCSR_INIT 0x0040 #define CMT_CMCSR_CALIB 0x0000 -#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || defined(CONFIG_CPU_SUBTYPE_SH7206) +#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ + defined(CONFIG_CPU_SUBTYPE_SH7206) || \ + defined(CONFIG_CPU_SUBTYPE_SH7263) #define CMT_CMSTR 0xfffec000 #define CMT_CMCSR_0 0xfffec002 #define CMT_CMCNT_0 0xfffec004 diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index cde06a481829..0187dccfe8c1 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -143,7 +143,8 @@ # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ # define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ - defined(CONFIG_CPU_SUBTYPE_SH7206) + defined(CONFIG_CPU_SUBTYPE_SH7206) || \ + defined(CONFIG_CPU_SUBTYPE_SH7263) # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ @@ -619,7 +620,8 @@ static inline int sci_rxd_in(struct uart_port *port) return 1; } #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \ - defined(CONFIG_CPU_SUBTYPE_SH7206) + defined(CONFIG_CPU_SUBTYPE_SH7206) || \ + defined(CONFIG_CPU_SUBTYPE_SH7263) static inline int sci_rxd_in(struct uart_port *port) { if (port->mapbase == 0xfffe8000) diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h index 94149c8a759c..9ce67fd51190 100644 --- a/include/asm-sh/bugs.h +++ b/include/asm-sh/bugs.h @@ -25,7 +25,7 @@ static void __init check_bugs(void) case CPU_SH7619: *p++ = '2'; break; - case CPU_SH7203 ... CPU_SH7206: + case CPU_SH7203 ... CPU_SH7263: *p++ = '2'; *p++ = 'a'; break; diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index 70f083f07d71..bbbdaab8de5f 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -17,7 +17,7 @@ enum cpu_type { CPU_SH7619, /* SH-2A types */ - CPU_SH7203, CPU_SH7206, + CPU_SH7203, CPU_SH7206, CPU_SH7263, /* SH-3 types */ CPU_SH7705, CPU_SH7706, CPU_SH7707, -- cgit v1.2.3 From c019fd8839503a91c556ae68d773e3bbb9b476e1 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 28 Nov 2007 19:14:23 +0900 Subject: rtc: rtc-sh: Split out the CPU defs to asm/cpu/. With all of the different CPU types this was getting a but unwieldly. Since sh64 is now integrated, we don't have to worry about multiple architectures caring about the header definitions. Split out the defs for each asm/cpu/ to make rtc-sh slightly less visually offensive. Signed-off-by: Paul Mundt --- drivers/rtc/rtc-sh.c | 20 +------------------- include/asm-sh/cpu-sh2/rtc.h | 8 ++++++++ include/asm-sh/cpu-sh2a/rtc.h | 8 ++++++++ include/asm-sh/cpu-sh3/rtc.h | 8 ++++++++ include/asm-sh/cpu-sh4/rtc.h | 8 ++++++++ include/asm-sh/cpu-sh5/rtc.h | 8 ++++++++ include/asm-sh/rtc.h | 2 ++ 7 files changed, 43 insertions(+), 19 deletions(-) create mode 100644 include/asm-sh/cpu-sh2/rtc.h create mode 100644 include/asm-sh/cpu-sh2a/rtc.h create mode 100644 include/asm-sh/cpu-sh3/rtc.h create mode 100644 include/asm-sh/cpu-sh4/rtc.h create mode 100644 include/asm-sh/cpu-sh5/rtc.h (limited to 'drivers') diff --git a/drivers/rtc/rtc-sh.c b/drivers/rtc/rtc-sh.c index af9bc57c8920..c1d6a1880ccf 100644 --- a/drivers/rtc/rtc-sh.c +++ b/drivers/rtc/rtc-sh.c @@ -26,25 +26,7 @@ #include #define DRV_NAME "sh-rtc" -#define DRV_VERSION "0.1.5" - -#ifdef CONFIG_CPU_SH2A -#define rtc_reg_size sizeof(u16) -#define RTC_BIT_INVERTED 0 -#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR -#elif defined(CONFIG_CPU_SH3) -#define rtc_reg_size sizeof(u16) -#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */ -#define RTC_DEF_CAPABILITIES 0UL -#elif defined(CONFIG_CPU_SH4) -#define rtc_reg_size sizeof(u32) -#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ -#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR -#elif defined(CONFIG_CPU_SH5) -#define rtc_reg_size sizeof(u32) -#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */ -#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR -#endif +#define DRV_VERSION "0.1.6" #define RTC_REG(r) ((r) * rtc_reg_size) diff --git a/include/asm-sh/cpu-sh2/rtc.h b/include/asm-sh/cpu-sh2/rtc.h new file mode 100644 index 000000000000..39e2d6e94782 --- /dev/null +++ b/include/asm-sh/cpu-sh2/rtc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_CPU_SH2_RTC_H +#define __ASM_SH_CPU_SH2_RTC_H + +#define rtc_reg_size sizeof(u16) +#define RTC_BIT_INVERTED 0 +#define RTC_DEF_CAPABILITIES 0UL + +#endif /* __ASM_SH_CPU_SH2_RTC_H */ diff --git a/include/asm-sh/cpu-sh2a/rtc.h b/include/asm-sh/cpu-sh2a/rtc.h new file mode 100644 index 000000000000..afb511e2bed7 --- /dev/null +++ b/include/asm-sh/cpu-sh2a/rtc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_CPU_SH2A_RTC_H +#define __ASM_SH_CPU_SH2A_RTC_H + +#define rtc_reg_size sizeof(u16) +#define RTC_BIT_INVERTED 0 +#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR + +#endif /* __ASM_SH_CPU_SH2A_RTC_H */ diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h new file mode 100644 index 000000000000..319404aaee37 --- /dev/null +++ b/include/asm-sh/cpu-sh3/rtc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_CPU_SH3_RTC_H +#define __ASM_SH_CPU_SH3_RTC_H + +#define rtc_reg_size sizeof(u16) +#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */ +#define RTC_DEF_CAPABILITIES 0UL + +#endif /* __ASM_SH_CPU_SH3_RTC_H */ diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h new file mode 100644 index 000000000000..f3d0f53275e4 --- /dev/null +++ b/include/asm-sh/cpu-sh4/rtc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_CPU_SH4_RTC_H +#define __ASM_SH_CPU_SH4_RTC_H + +#define rtc_reg_size sizeof(u32) +#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ +#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR + +#endif /* __ASM_SH_CPU_SH4_RTC_H */ diff --git a/include/asm-sh/cpu-sh5/rtc.h b/include/asm-sh/cpu-sh5/rtc.h new file mode 100644 index 000000000000..12ea0ed144e1 --- /dev/null +++ b/include/asm-sh/cpu-sh5/rtc.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_CPU_SH5_RTC_H +#define __ASM_SH_CPU_SH5_RTC_H + +#define rtc_reg_size sizeof(u32) +#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */ +#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR + +#endif /* __ASM_SH_CPU_SH5_RTC_H */ diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h index 858da99d37e0..ec45ba8e11d9 100644 --- a/include/asm-sh/rtc.h +++ b/include/asm-sh/rtc.h @@ -11,4 +11,6 @@ struct sh_rtc_platform_info { unsigned long capabilities; }; +#include + #endif /* _ASM_RTC_H */ -- cgit v1.2.3 From 31a49c4bf8f964b7a9897baa889916d71b51d9c1 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Wed, 26 Dec 2007 11:45:06 +0900 Subject: sh: Add support for SH7721 CPU subtype. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 7 +++++++ arch/sh/Kconfig.debug | 2 +- arch/sh/drivers/dma/Kconfig | 2 +- arch/sh/drivers/dma/dma-sh.c | 2 ++ arch/sh/kernel/cpu/sh3/Makefile | 1 + arch/sh/kernel/cpu/sh3/probe.c | 3 +++ arch/sh/kernel/cpu/sh3/setup-sh7720.c | 11 +++++++++-- arch/sh/kernel/early_printk.c | 12 ++++++++---- arch/sh/kernel/setup.c | 8 ++++---- arch/sh/kernel/timers/timer-tmu.c | 1 + drivers/serial/sh-sci.c | 2 +- drivers/serial/sh-sci.h | 21 ++++++++++++++------- include/asm-sh/cpu-sh3/cache.h | 3 ++- include/asm-sh/cpu-sh3/dma.h | 4 +++- include/asm-sh/cpu-sh3/gpio.h | 3 ++- include/asm-sh/cpu-sh3/mmu_context.h | 3 ++- include/asm-sh/cpu-sh3/timer.h | 7 ++++--- include/asm-sh/cpu-sh3/ubc.h | 3 ++- include/asm-sh/processor.h | 2 +- 19 files changed, 68 insertions(+), 29 deletions(-) (limited to 'drivers') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 538631ca10a6..d2f557719489 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -214,6 +214,13 @@ config CPU_SUBTYPE_SH7720 help Select SH7720 if you have a SH3-DSP SH7720 CPU. +config CPU_SUBTYPE_SH7721 + bool "Support SH7721 processor" + select CPU_SH3 + select CPU_HAS_DSP + help + Select SH7721 if you have a SH3-DSP SH7721 CPU. + # SH-4 Processor Support config CPU_SUBTYPE_SH7750 diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 2881d8471a17..dde00d5c2478 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -35,7 +35,7 @@ config EARLY_SCIF_CONSOLE_PORT default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 default "0xf8420000" if CPU_SUBTYPE_SH7619 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705 - default "0xa4430000" if CPU_SUBTYPE_SH7720 + default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721 default "0xffc30000" if CPU_SUBTYPE_SHX3 default "0xffe80000" if CPU_SH4 default "0x00000000" diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig index 4e711a0c3dae..01936368b8b0 100644 --- a/arch/sh/drivers/dma/Kconfig +++ b/arch/sh/drivers/dma/Kconfig @@ -12,7 +12,7 @@ config SH_DMA config NR_ONCHIP_DMA_CHANNELS int depends on SH_DMA - default "6" if CPU_SUBTYPE_SH7720 + default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R default "12" if CPU_SUBTYPE_SH7780 default "4" diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index 958bac1c585a..5c3359756a92 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -25,6 +25,7 @@ static int dmte_irq_map[] = { DMTE2_IRQ, DMTE3_IRQ, #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ defined(CONFIG_CPU_SUBTYPE_SH7760) || \ defined(CONFIG_CPU_SUBTYPE_SH7709) || \ @@ -203,6 +204,7 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan) } #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) #define dmaor_read_reg() ctrl_inw(DMAOR) #define dmaor_write_reg(data) ctrl_outw(data, DMAOR) diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile index 646eb6933614..1afd05e62d1c 100644 --- a/arch/sh/kernel/cpu/sh3/Makefile +++ b/arch/sh/kernel/cpu/sh3/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o +obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SH3) := clock-sh3.o diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c index 22070e43e34d..fcc80bb7bee7 100644 --- a/arch/sh/kernel/cpu/sh3/probe.c +++ b/arch/sh/kernel/cpu/sh3/probe.c @@ -84,6 +84,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void) #if defined(CONFIG_CPU_SUBTYPE_SH7720) boot_cpu_data.type = CPU_SH7720; #endif +#if defined(CONFIG_CPU_SUBTYPE_SH7721) + boot_cpu_data.type = CPU_SH7721; +#endif #if defined(CONFIG_CPU_SUBTYPE_SH7705) boot_cpu_data.type = CPU_SH7705; diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index a0929b8a95ae..00facd028a08 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c @@ -127,8 +127,11 @@ static struct intc_vect vectors[] __initdata = { INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800), INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840), INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900), - INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20), - INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60), +#if defined(CONFIG_CPU_SUBTYPE_SH7720) + INTC_VECT(SSL, 0x980), +#endif + INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40), + INTC_VECT(USBHI, 0xa60), INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0), INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80), @@ -168,7 +171,11 @@ static struct intc_prio_reg prio_registers[] __initdata = { { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } }, { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } }, +#if defined(CONFIG_CPU_SUBTYPE_SH7720) { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } }, +#else + { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } }, +#endif { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } }, { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } }, { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } }, diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c index 2f30977558ad..957f25611543 100644 --- a/arch/sh/kernel/early_printk.c +++ b/arch/sh/kernel/early_printk.c @@ -63,7 +63,8 @@ static struct console bios_console = { #include #include "../../../drivers/serial/sh-sci.h" -#if defined(CONFIG_CPU_SUBTYPE_SH7720) +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define EPK_SCSMR_VALUE 0x000 #define EPK_SCBRR_VALUE 0x00C #define EPK_FIFO_SIZE 64 @@ -117,7 +118,8 @@ static struct console scif_console = { }; #if !defined(CONFIG_SH_STANDARD_BIOS) -#if defined(CONFIG_CPU_SUBTYPE_SH7720) +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) static void scif_sercon_init(char *s) { sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */ @@ -208,9 +210,11 @@ static int __init setup_early_printk(char *buf) if (!strncmp(buf, "serial", 6)) { early_console = &scif_console; -#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \ - !defined(CONFIG_SH_STANDARD_BIOS) +#if !defined(CONFIG_SH_STANDARD_BIOS) +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) scif_sercon_init(buf + 6); +#endif #endif } #endif diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 9c105c827e86..48cd576754b5 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -314,10 +314,10 @@ static const char *cpu_name[] = { [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710", [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720", - [CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750", - [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R", - [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R", - [CPU_SH7760] = "SH7760", + [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729", + [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S", + [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751", + [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760", [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501", [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c index 628ec9a15e38..8935570008d2 100644 --- a/arch/sh/kernel/timers/timer-tmu.c +++ b/arch/sh/kernel/timers/timer-tmu.c @@ -174,6 +174,7 @@ static int tmu_timer_init(void) tmu_timer_stop(); #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \ + !defined(CONFIG_CPU_SUBTYPE_SH7721) && \ !defined(CONFIG_CPU_SUBTYPE_SH7760) && \ !defined(CONFIG_CPU_SUBTYPE_SH7785) && \ !defined(CONFIG_CPU_SUBTYPE_SHX3) diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index 73440e26834b..6fbfd140b7e7 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c @@ -302,7 +302,7 @@ static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) } sci_out(port, SCFCR, fcr_val); } -#elif defined(CONFIG_CPU_SUBTYPE_SH7720) +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 0187dccfe8c1..85562040a6d3 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -46,7 +46,8 @@ */ # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 # define SCIF_ONLY -#elif defined(CONFIG_CPU_SUBTYPE_SH7720) +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define SCIF_ONLY #define SCIF_ORER 0x0200 /* overrun error bit */ @@ -216,7 +217,8 @@ #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define SCIF_ORER 0x0200 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) #define SCIF_RFDC_MASK 0x007f @@ -254,7 +256,8 @@ # define SCxSR_PER(port) SCIF_PER # define SCxSR_BRK(port) SCIF_BRK #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73) # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf) @@ -363,7 +366,8 @@ #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define SCIF_FNS(name, scif_offset, scif_size) \ CPU_SCIF_FNS(name, scif_offset, scif_size) #else @@ -390,7 +394,8 @@ #endif #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -512,7 +517,8 @@ static inline void set_sh771x_scif_pfc(struct uart_port *port) return; } } -#elif defined(CONFIG_CPU_SUBTYPE_SH7720) +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) static inline int sci_rxd_in(struct uart_port *port) { if (port->mapbase == 0xa4430000) @@ -696,7 +702,8 @@ static inline int sci_rxd_in(struct uart_port *port) defined(CONFIG_CPU_SUBTYPE_SH7785) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1) diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h index 77dd45d82414..56bd838b7db4 100644 --- a/include/asm-sh/cpu-sh3/cache.h +++ b/include/asm-sh/cpu-sh3/cache.h @@ -33,7 +33,8 @@ #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ defined(CONFIG_CPU_SUBTYPE_SH7710) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define CCR3 0xa40000b4 #define CCR_CACHE_16KB 0x00010000 #define CCR_CACHE_32KB 0x00020000 diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h index 54bfece328c2..092ff9d872c3 100644 --- a/include/asm-sh/cpu-sh3/dma.h +++ b/include/asm-sh/cpu-sh3/dma.h @@ -2,7 +2,9 @@ #define __ASM_CPU_SH3_DMA_H -#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) #define SH_DMAC_BASE 0xa4010020 #define DMTE0_IRQ 48 diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h index 48770c1c7bdf..4e53eb314b8f 100644 --- a/include/asm-sh/cpu-sh3/gpio.h +++ b/include/asm-sh/cpu-sh3/gpio.h @@ -12,7 +12,8 @@ #ifndef _CPU_SH3_GPIO_H #define _CPU_SH3_GPIO_H -#if defined(CONFIG_CPU_SUBTYPE_SH7720) +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) /* Control registers */ #define PORT_PACR 0xA4050100UL diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h index 16c2d63b7e39..ab09da73ce77 100644 --- a/include/asm-sh/cpu-sh3/mmu_context.h +++ b/include/asm-sh/cpu-sh3/mmu_context.h @@ -33,7 +33,8 @@ defined(CONFIG_CPU_SUBTYPE_SH7709) || \ defined(CONFIG_CPU_SUBTYPE_SH7710) || \ defined(CONFIG_CPU_SUBTYPE_SH7712) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ #else #define INTEVT 0xffffffd8 diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h index 7b795ac5477c..793acf12aa08 100644 --- a/include/asm-sh/cpu-sh3/timer.h +++ b/include/asm-sh/cpu-sh3/timer.h @@ -23,12 +23,13 @@ * --------------------------------------------------------------------------- */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7720) +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721) #define TMU_TOCR 0xfffffe90 /* Byte access */ #endif #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define TMU_012_TSTR 0xa412fe92 /* Byte access */ #define TMU0_TCOR 0xa412fe94 /* Long access */ @@ -57,7 +58,7 @@ #define TMU2_TCOR 0xfffffeac /* Long access */ #define TMU2_TCNT 0xfffffeb0 /* Long access */ #define TMU2_TCR 0xfffffeb4 /* Word access */ -#if !defined(CONFIG_CPU_SUBTYPE_SH7720) +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721) #define TMU2_TCPR2 0xfffffeb8 /* Long access */ #endif #endif diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h index 18467c574534..4e6381d5ff7a 100644 --- a/include/asm-sh/cpu-sh3/ubc.h +++ b/include/asm-sh/cpu-sh3/ubc.h @@ -12,7 +12,8 @@ #define __ASM_CPU_SH3_UBC_H #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ - defined(CONFIG_CPU_SUBTYPE_SH7720) + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) #define UBC_BARA 0xa4ffffb0 #define UBC_BAMRA 0xa4ffffb4 #define UBC_BBRA 0xa4ffffb8 diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index bbbdaab8de5f..f4a8da71ba45 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -23,7 +23,7 @@ enum cpu_type { CPU_SH7705, CPU_SH7706, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712, - CPU_SH7720, CPU_SH7729, + CPU_SH7720, CPU_SH7721, CPU_SH7729, /* SH-4 types */ CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, -- cgit v1.2.3 From 7d740a066fb9c6681c2898c7977209725c9e552f Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 7 Jan 2008 14:40:07 +0900 Subject: sh: Add support for SH7763 CPU subtype. Signed-off-by: Yoshihiro Shimoda Signed-off-by: Paul Mundt --- arch/sh/Kconfig | 9 +- arch/sh/Kconfig.debug | 2 +- arch/sh/drivers/pci/Makefile | 1 + arch/sh/drivers/pci/pci-sh4.h | 4 +- arch/sh/drivers/pci/pci-sh7780.c | 1 + arch/sh/drivers/pci/pci-sh7780.h | 1 + arch/sh/kernel/cpu/sh4/probe.c | 2 + arch/sh/kernel/cpu/sh4a/Makefile | 2 + arch/sh/kernel/cpu/sh4a/clock-sh7763.c | 126 +++++++++++ arch/sh/kernel/cpu/sh4a/setup-sh7763.c | 390 +++++++++++++++++++++++++++++++++ arch/sh/kernel/setup.c | 8 +- drivers/serial/sh-sci.c | 4 +- drivers/serial/sh-sci.h | 19 +- include/asm-sh/bugs.h | 2 +- include/asm-sh/cpu-sh4/freq.h | 3 +- include/asm-sh/processor.h | 2 +- 16 files changed, 564 insertions(+), 12 deletions(-) create mode 100644 arch/sh/kernel/cpu/sh4a/clock-sh7763.c create mode 100644 arch/sh/kernel/cpu/sh4a/setup-sh7763.c (limited to 'drivers') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index d2f557719489..ddbd610d27e7 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -265,6 +265,12 @@ config CPU_SUBTYPE_SH4_202 # SH-4A Processor Support +config CPU_SUBTYPE_SH7763 + bool "Support SH7763 processor" + select CPU_SH4A + help + Select SH7763 if you have a SH4A SH7763(R5S77631) CPU. + config CPU_SUBTYPE_SH7770 bool "Support SH7770 processor" select CPU_SH4A @@ -551,7 +557,8 @@ config SH_MTU2 config SH_TIMER_IRQ int - default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 + default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \ + CPU_SUBTYPE_SH7763 default "86" if CPU_SUBTYPE_SH7619 default "140" if CPU_SUBTYPE_SH7206 default "16" diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index dde00d5c2478..f7c716166ce8 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -29,7 +29,7 @@ config EARLY_SCIF_CONSOLE config EARLY_SCIF_CONSOLE_PORT hex depends on EARLY_SCIF_CONSOLE - default "0xffe00000" if CPU_SUBTYPE_SH7780 + default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 default "0xffea0000" if CPU_SUBTYPE_SH7785 default "0xfffe8000" if CPU_SUBTYPE_SH7203 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile index 172e81db9530..1086cf111f8b 100644 --- a/arch/sh/drivers/pci/Makefile +++ b/arch/sh/drivers/pci/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o +obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h index 1901c33cde6a..4925c79ea959 100644 --- a/arch/sh/drivers/pci/pci-sh4.h +++ b/arch/sh/drivers/pci/pci-sh4.h @@ -1,7 +1,9 @@ #ifndef __PCI_SH4_H #define __PCI_SH4_H -#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785) +#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ + defined(CONFIG_CPU_SUBTYPE_SH7785) || \ + defined(CONFIG_CPU_SUBTYPE_SH7763) #include "pci-sh7780.h" #else #include "pci-sh7751.h" diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c index e516087fb435..7d797f4de5e7 100644 --- a/arch/sh/drivers/pci/pci-sh7780.c +++ b/arch/sh/drivers/pci/pci-sh7780.c @@ -58,6 +58,7 @@ static int __init sh7780_pci_init(void) id = pci_read_reg(SH7780_PCIVID); if ((id & 0xffff) == SH7780_VENDOR_ID) { switch ((id >> 16) & 0xffff) { + case SH7763_DEVICE_ID: case SH7780_DEVICE_ID: case SH7781_DEVICE_ID: case SH7785_DEVICE_ID: diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h index 1d069a859de2..97b2c98f05c4 100644 --- a/arch/sh/drivers/pci/pci-sh7780.h +++ b/arch/sh/drivers/pci/pci-sh7780.h @@ -16,6 +16,7 @@ #define SH7780_VENDOR_ID 0x1912 #define SH7781_DEVICE_ID 0x0001 #define SH7780_DEVICE_ID 0x0002 +#define SH7763_DEVICE_ID 0x0004 #define SH7785_DEVICE_ID 0x0007 /* SH7780 Control Registers */ diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index bc9c28a69bf1..f2b9238cda04 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c @@ -98,6 +98,8 @@ int __init detect_cpu_and_cache_system(void) case 0x200A: if (prr == 0x61) boot_cpu_data.type = CPU_SH7781; + else if (prr == 0xa1) + boot_cpu_data.type = CPU_SH7763; else boot_cpu_data.type = CPU_SH7780; diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile index 24539873943a..08ac6387bf17 100644 --- a/arch/sh/kernel/cpu/sh4a/Makefile +++ b/arch/sh/kernel/cpu/sh4a/Makefile @@ -3,6 +3,7 @@ # # CPU subtype setup +obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o @@ -14,6 +15,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o # Primary on-chip clocks (common) +clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c new file mode 100644 index 000000000000..45889d412c80 --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c @@ -0,0 +1,126 @@ +/* + * arch/sh/kernel/cpu/sh4a/clock-sh7763.c + * + * SH7763 support for the clock framework + * + * Copyright (C) 2005 Paul Mundt + * Copyright (C) 2007 Yoshihiro Shimoda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; +static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; +static int p1fc_divisors[] = { 1, 1, 1, 16, 1, 1, 1, 1 }; +static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; + +static void master_clk_init(struct clk *clk) +{ + clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; +} + +static struct clk_ops sh7763_master_clk_ops = { + .init = master_clk_init, +}; + +static void module_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); + clk->rate = clk->parent->rate / p0fc_divisors[idx]; +} + +static struct clk_ops sh7763_module_clk_ops = { + .recalc = module_clk_recalc, +}; + +static void bus_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); + clk->rate = clk->parent->rate / bfc_divisors[idx]; +} + +static struct clk_ops sh7763_bus_clk_ops = { + .recalc = bus_clk_recalc, +}; + +static void cpu_clk_recalc(struct clk *clk) +{ + clk->rate = clk->parent->rate; +} + +static struct clk_ops sh7763_cpu_clk_ops = { + .recalc = cpu_clk_recalc, +}; + +static struct clk_ops *sh7763_clk_ops[] = { + &sh7763_master_clk_ops, + &sh7763_module_clk_ops, + &sh7763_bus_clk_ops, + &sh7763_cpu_clk_ops, +}; + +void __init arch_init_clk_ops(struct clk_ops **ops, int idx) +{ + if (idx < ARRAY_SIZE(sh7763_clk_ops)) + *ops = sh7763_clk_ops[idx]; +} + +static void shyway_clk_recalc(struct clk *clk) +{ + int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); + clk->rate = clk->parent->rate / cfc_divisors[idx]; +} + +static struct clk_ops sh7763_shyway_clk_ops = { + .recalc = shyway_clk_recalc, +}; + +static struct clk sh7763_shyway_clk = { + .name = "shyway_clk", + .flags = CLK_ALWAYS_ENABLED, + .ops = &sh7763_shyway_clk_ops, +}; + +/* + * Additional SH7763-specific on-chip clocks that aren't already part of the + * clock framework + */ +static struct clk *sh7763_onchip_clocks[] = { + &sh7763_shyway_clk, +}; + +static int __init sh7763_clk_init(void) +{ + struct clk *clk = clk_get(NULL, "master_clk"); + int i; + + for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { + struct clk *clkp = sh7763_onchip_clocks[i]; + + clkp->parent = clk; + clk_register(clkp); + clk_enable(clkp); + } + + /* + * Now that we have the rest of the clocks registered, we need to + * force the parent clock to propagate so that these clocks will + * automatically figure out their rate. We cheat by handing the + * parent clock its current rate and forcing child propagation. + */ + clk_set_rate(clk, clk_get_rate(clk)); + + clk_put(clk); + + return 0; +} + +arch_initcall(sh7763_clk_init); + diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c new file mode 100644 index 000000000000..eabd5386812d --- /dev/null +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c @@ -0,0 +1,390 @@ +/* + * SH7763 Setup + * + * Copyright (C) 2006 Paul Mundt + * Copyright (C) 2007 Yoshihiro Shimoda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xffe80000, + .end = 0xffe80000 + 0x58 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 21, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 22, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 20, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xffe00000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 40, 41, 43, 42 }, + }, { + .mapbase = 0xffe08000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 76, 77, 79, 78 }, + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct resource usb_ohci_resources[] = { + [0] = { + .start = 0xffec8000, + .end = 0xffec80ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 83, + .end = 83, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 usb_ohci_dma_mask = 0xffffffffUL; +static struct platform_device usb_ohci_device = { + .name = "sh_ohci", + .id = -1, + .dev = { + .dma_mask = &usb_ohci_dma_mask, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usb_ohci_resources), + .resource = usb_ohci_resources, +}; + +static struct resource usbf_resources[] = { + [0] = { + .start = 0xffec0000, + .end = 0xffec00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = 84, + .end = 84, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usbf_device = { + .name = "sh_udc", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + }, + .num_resources = ARRAY_SIZE(usbf_resources), + .resource = usbf_resources, +}; + +static struct platform_device *sh7763_devices[] __initdata = { + &rtc_device, + &sci_device, + &usb_ohci_device, + &usbf_device, +}; + +static int __init sh7763_devices_setup(void) +{ + return platform_add_devices(sh7763_devices, + ARRAY_SIZE(sh7763_devices)); +} +__initcall(sh7763_devices_setup); + +enum { + UNUSED = 0, + + /* interrupt sources */ + + IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, + IRL_HHLL, IRL_HHLH, IRL_HHHL, + + IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, + RTC_ATI, RTC_PRI, RTC_CUI, + WDT, TMU0, TMU1, TMU2, TMU2_TICPI, + HUDI, LCDC, + DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE, + SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, + DMAC0_DMINT4, DMAC0_DMINT5, + IIC0, IIC1, + CMT, + GEINT0, GEINT1, GEINT2, + HAC, + PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, + PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, + STIF0, STIF1, + SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, + SIOF0, SIOF1, SIOF2, + USBH, USBFI0, USBFI1, + TPU, PCC, + MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY, + SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND, + TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, + SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, + GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3, + + /* interrupt groups */ + + TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5, + SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO, +}; + +static struct intc_vect vectors[] __initdata = { + INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), + INTC_VECT(RTC_CUI, 0x4c0), + INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), + INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), + INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), + INTC_VECT(LCDC, 0x620), + INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), + INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), + INTC_VECT(DMAC0_DMAE, 0x6c0), + INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), + INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), + INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), + INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), + INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920), + INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960), + INTC_VECT(HAC, 0x980), + INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), + INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), + INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), + INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), + INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), + INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), + INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), + INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), + INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), + INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80), + INTC_VECT(USBFI1, 0xca0), + INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), + INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), + INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), + INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0), + INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0), + INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), + INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), + INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), + INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), + INTC_VECT(SCIF1_ERI, 0xf00), INTC_VECT(SCIF1_RXI, 0xf20), + INTC_VECT(SCIF1_BRI, 0xf40), INTC_VECT(SCIF1_TXI, 0xf60), + INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0), + INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0), +}; + +static struct intc_group groups[] __initdata = { + INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), + INTC_GROUP(TMU345, TMU3, TMU4, TMU5), + INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), + INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, + DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), + INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), + INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2), + INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0), + INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), + INTC_GROUP(USBF, USBFI0, USBFI1), + INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY), + INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND), + INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), + INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3), +}; + +static struct intc_prio priorities[] __initdata = { + INTC_PRIO(SCIF0, 3), + INTC_PRIO(SCIF1, 3), + INTC_PRIO(SCIF2, 3), +}; + +static struct intc_mask_reg mask_registers[] __initdata = { + { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ + { 0, 0, 0, 0, 0, 0, GPIO, 0, + SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB, + PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC, + HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, + { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ + { 0, 0, 0, 0, 0, 0, SCIF2, USBF, + 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER, + PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1, + LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } }, +}; + +static struct intc_prio_reg prio_registers[] __initdata = { + { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, + TMU2, TMU2_TICPI } }, + { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, + { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, + { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } }, + { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, + PCISERR, PCIINTA } }, + { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, + PCIINTD, PCIC5 } }, + { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } }, + { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } }, + { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } }, + { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } }, + { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } }, + { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } }, + { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } }, + { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } }, +}; + +static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, priorities, + mask_registers, prio_registers, NULL); + +/* Support for external interrupt pins in IRQ mode */ + +static struct intc_vect irq_vectors[] __initdata = { + INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), + INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), + INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), + INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), +}; + +static struct intc_mask_reg irq_mask_registers[] __initdata = { + { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ + { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static struct intc_prio_reg irq_prio_registers[] __initdata = { + { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static struct intc_sense_reg irq_sense_registers[] __initdata = { + { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, + IRQ4, IRQ5, IRQ6, IRQ7 } }, +}; + +static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors, + NULL, NULL, irq_mask_registers, irq_prio_registers, + irq_sense_registers); + +/* External interrupt pins in IRL mode */ + +static struct intc_vect irl_vectors[] __initdata = { + INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), + INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), + INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), + INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), + INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), + INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), + INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), + INTC_VECT(IRL_HHHL, 0x3c0), +}; + +static struct intc_mask_reg irl3210_mask_registers[] __initdata = { + { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ + { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, + IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, +}; + +static struct intc_mask_reg irl7654_mask_registers[] __initdata = { + { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, + IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, + IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, + IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, +}; + +static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors, + NULL, NULL, irl7654_mask_registers, NULL, NULL); + +static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors, + NULL, NULL, irl3210_mask_registers, NULL, NULL); + +#define INTC_ICR0 0xffd00000 +#define INTC_INTMSK0 0xffd00044 +#define INTC_INTMSK1 0xffd00048 +#define INTC_INTMSK2 0xffd40080 +#define INTC_INTMSKCLR1 0xffd00068 +#define INTC_INTMSKCLR2 0xffd40084 + +void __init plat_irq_setup(void) +{ + /* disable IRQ7-0 */ + ctrl_outl(0xff000000, INTC_INTMSK0); + + /* disable IRL3-0 + IRL7-4 */ + ctrl_outl(0xc0000000, INTC_INTMSK1); + ctrl_outl(0xfffefffe, INTC_INTMSK2); + + register_intc_controller(&intc_desc); +} + +void __init plat_irq_setup_pins(int mode) +{ + switch (mode) { + case IRQ_MODE_IRQ: + /* select IRQ mode for IRL3-0 + IRL7-4 */ + ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); + register_intc_controller(&intc_irq_desc); + break; + case IRQ_MODE_IRL7654: + /* enable IRL7-4 but don't provide any masking */ + ctrl_outl(0x40000000, INTC_INTMSKCLR1); + ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); + break; + case IRQ_MODE_IRL3210: + /* enable IRL0-3 but don't provide any masking */ + ctrl_outl(0x80000000, INTC_INTMSKCLR1); + ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); + break; + case IRQ_MODE_IRL7654_MASK: + /* enable IRL7-4 and mask using cpu intc controller */ + ctrl_outl(0x40000000, INTC_INTMSKCLR1); + register_intc_controller(&intc_irl7654_desc); + break; + case IRQ_MODE_IRL3210_MASK: + /* enable IRL0-3 and mask using cpu intc controller */ + ctrl_outl(0x80000000, INTC_INTMSKCLR1); + register_intc_controller(&intc_irl3210_desc); + break; + default: + BUG(); + } +} diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 48cd576754b5..9cf1d2e998bf 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -319,10 +319,10 @@ static const char *cpu_name[] = { [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760", [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501", - [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780", - [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343", - [CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722", - [CPU_SHX3] = "SH-X3", + [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770", + [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", + [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785", + [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", [CPU_SH_NONE] = "Unknown" }; diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c index 6fbfd140b7e7..ddf639144538 100644 --- a/drivers/serial/sh-sci.c +++ b/drivers/serial/sh-sci.c @@ -395,7 +395,8 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) } else { #ifdef CONFIG_CPU_SUBTYPE_SH7343 /* Nothing */ -#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \ +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) || \ defined(CONFIG_CPU_SUBTYPE_SHX3) ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ @@ -408,6 +409,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) #endif #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ + defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) static inline int scif_txroom(struct uart_port *port) diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 85562040a6d3..f5764ebcfe07 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h @@ -120,6 +120,12 @@ # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ # define SCI_ONLY # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) +# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ +# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ +# define SCIF_ORER 0x0001 /* overrun error bit */ +# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ +# define SCIF_ONLY #elif defined(CONFIG_CPU_SUBTYPE_SH7770) # define SCSPTR0 0xff923020 /* 16 bit SCIF */ # define SCSPTR1 0xff924020 /* 16 bit SCIF */ @@ -419,6 +425,7 @@ SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ + defined(CONFIG_CPU_SUBTYPE_SH7763) || \ defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) @@ -588,6 +595,15 @@ static inline int sci_rxd_in(struct uart_port *port) int ch = (port->mapbase - SMR0) >> 3; return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; } +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) +static inline int sci_rxd_in(struct uart_port *port) +{ + if (port->mapbase == 0xffe00000) + return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ + if (port->mapbase == 0xffe08000) + return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ + return 1; +} #elif defined(CONFIG_CPU_SUBTYPE_SH7770) static inline int sci_rxd_in(struct uart_port *port) { @@ -698,7 +714,8 @@ static inline int sci_rxd_in(struct uart_port *port) * -- Mitch Davis - 15 Jul 2000 */ -#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \ +#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) || \ defined(CONFIG_CPU_SUBTYPE_SH7785) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h index 9ce67fd51190..def8128b8b78 100644 --- a/include/asm-sh/bugs.h +++ b/include/asm-sh/bugs.h @@ -35,7 +35,7 @@ static void __init check_bugs(void) case CPU_SH7750 ... CPU_SH4_501: *p++ = '4'; break; - case CPU_SH7770 ... CPU_SHX3: + case CPU_SH7763 ... CPU_SHX3: *p++ = '4'; *p++ = 'a'; break; diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h index dc1d32a86374..1ac10b9a078f 100644 --- a/include/asm-sh/cpu-sh4/freq.h +++ b/include/asm-sh/cpu-sh4/freq.h @@ -16,7 +16,8 @@ #define SCLKACR 0xa4150008 #define SCLKBCR 0xa415000c #define IrDACLKCR 0xa4150010 -#elif defined(CONFIG_CPU_SUBTYPE_SH7780) +#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ + defined(CONFIG_CPU_SUBTYPE_SH7780) #define FRQCR 0xffc80000 #elif defined(CONFIG_CPU_SUBTYPE_SH7785) #define FRQCR0 0xffc80000 diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h index f4a8da71ba45..c9b14161f73d 100644 --- a/include/asm-sh/processor.h +++ b/include/asm-sh/processor.h @@ -30,7 +30,7 @@ enum cpu_type { CPU_SH7760, CPU_SH4_202, CPU_SH4_501, /* SH-4A types */ - CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3, + CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3, /* SH4AL-DSP types */ CPU_SH7343, CPU_SH7722, -- cgit v1.2.3 From 74ee1a7590b782a6df01d00ae38093cbfbee5ca9 Mon Sep 17 00:00:00 2001 From: Adrian McMenamin Date: Mon, 21 Jan 2008 18:52:48 +0900 Subject: cdrom: Add support for Sega Dreamcast GD-ROM. This patch adds support for the GD-Rom drive, SEGA's proprietary implementation of an IDE CD Rom for the SEGA Dreamcast. This driver implements Sega's Packet Interface (SPI) - at least partially. It will also read disks in SEGA's propreitary GD format. Unlike previous drivers (which were never in mainline) this uses DMA and not PIO to read disks. It is a new driver, not a refactoring of old drivers. Signed-off by: Adrian McMenamin Acked-by: Jens Axboe Signed-off-by: Paul Mundt --- drivers/block/Kconfig | 11 + drivers/cdrom/Makefile | 1 + drivers/cdrom/gdrom.c | 867 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 879 insertions(+) create mode 100644 drivers/cdrom/gdrom.c (limited to 'drivers') diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 4d0119ea9e35..f2122855d4ec 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -105,6 +105,17 @@ config PARIDE "MicroSolutions backpack protocol", "DataStor Commuter protocol" etc.). +config GDROM + tristate "SEGA Dreamcast GD-ROM drive" + depends on SH_DREAMCAST + help + A standard SEGA Dreamcast comes with a modified CD ROM drive called a + "GD-ROM" by SEGA to signify it is capable of reading special disks + with up to 1 GB of data. This drive will also read standard CD ROM + disks. Select this option to access any disks in your GD ROM drive. + Most users will want to say "Y" here. + You can also build this as a module which will be called gdrom.ko + source "drivers/block/paride/Kconfig" config BLK_CPQ_DA diff --git a/drivers/cdrom/Makefile b/drivers/cdrom/Makefile index 774c180a4e11..ecf85fda0fc1 100644 --- a/drivers/cdrom/Makefile +++ b/drivers/cdrom/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PARIDE_PCD) += cdrom.o obj-$(CONFIG_CDROM_PKTCDVD) += cdrom.o obj-$(CONFIG_VIOCD) += viocd.o cdrom.o +obj-$(CONFIG_GDROM) += gdrom.o cdrom.o diff --git a/drivers/cdrom/gdrom.c b/drivers/cdrom/gdrom.c new file mode 100644 index 000000000000..4e2bbcccc064 --- /dev/null +++ b/drivers/cdrom/gdrom.c @@ -0,0 +1,867 @@ +/* GD ROM driver for the SEGA Dreamcast + * copyright Adrian McMenamin, 2007 + * With thanks to Marcus Comstedt and Nathan Keynes + * for work in reversing PIO and DMA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GDROM_DEV_NAME "gdrom" +#define GD_SESSION_OFFSET 150 + +/* GD Rom commands */ +#define GDROM_COM_SOFTRESET 0x08 +#define GDROM_COM_EXECDIAG 0x90 +#define GDROM_COM_PACKET 0xA0 +#define GDROM_COM_IDDEV 0xA1 + +/* GD Rom registers */ +#define GDROM_BASE_REG 0xA05F7000 +#define GDROM_ALTSTATUS_REG (GDROM_BASE_REG + 0x18) +#define GDROM_DATA_REG (GDROM_BASE_REG + 0x80) +#define GDROM_ERROR_REG (GDROM_BASE_REG + 0x84) +#define GDROM_INTSEC_REG (GDROM_BASE_REG + 0x88) +#define GDROM_SECNUM_REG (GDROM_BASE_REG + 0x8C) +#define GDROM_BCL_REG (GDROM_BASE_REG + 0x90) +#define GDROM_BCH_REG (GDROM_BASE_REG + 0x94) +#define GDROM_DSEL_REG (GDROM_BASE_REG + 0x98) +#define GDROM_STATUSCOMMAND_REG (GDROM_BASE_REG + 0x9C) +#define GDROM_RESET_REG (GDROM_BASE_REG + 0x4E4) + +#define GDROM_DMA_STARTADDR_REG (GDROM_BASE_REG + 0x404) +#define GDROM_DMA_LENGTH_REG (GDROM_BASE_REG + 0x408) +#define GDROM_DMA_DIRECTION_REG (GDROM_BASE_REG + 0x40C) +#define GDROM_DMA_ENABLE_REG (GDROM_BASE_REG + 0x414) +#define GDROM_DMA_STATUS_REG (GDROM_BASE_REG + 0x418) +#define GDROM_DMA_WAIT_REG (GDROM_BASE_REG + 0x4A0) +#define GDROM_DMA_ACCESS_CTRL_REG (GDROM_BASE_REG + 0x4B8) + +#define GDROM_HARD_SECTOR 2048 +#define BLOCK_LAYER_SECTOR 512 +#define GD_TO_BLK 4 + +#define GDROM_DEFAULT_TIMEOUT (HZ * 7) + +static const struct { + int sense_key; + const char * const text; +} sense_texts[] = { + {NO_SENSE, "OK"}, + {RECOVERED_ERROR, "Recovered from error"}, + {NOT_READY, "Device not ready"}, + {MEDIUM_ERROR, "Disk not ready"}, + {HARDWARE_ERROR, "Hardware error"}, + {ILLEGAL_REQUEST, "Command has failed"}, + {UNIT_ATTENTION, "Device needs attention - disk may have been changed"}, + {DATA_PROTECT, "Data protection error"}, + {ABORTED_COMMAND, "Command aborted"}, +}; + +static struct platform_device *pd; +static int gdrom_major; +static DECLARE_WAIT_QUEUE_HEAD(command_queue); +static DECLARE_WAIT_QUEUE_HEAD(request_queue); + +static DEFINE_SPINLOCK(gdrom_lock); +static void gdrom_readdisk_dma(struct work_struct *work); +static DECLARE_WORK(work, gdrom_readdisk_dma); +static LIST_HEAD(gdrom_deferred); + +struct gdromtoc { + unsigned int entry[99]; + unsigned int first, last; + unsigned int leadout; +}; + +static struct gdrom_unit { + struct gendisk *disk; + struct cdrom_device_info *cd_info; + int status; + int pending; + int transfer; + char disk_type; + struct gdromtoc *toc; + struct request_queue *gdrom_rq; +} gd; + +struct gdrom_id { + char mid; + char modid; + char verid; + char padA[13]; + char mname[16]; + char modname[16]; + char firmver[16]; + char padB[16]; +}; + +static int gdrom_getsense(short *bufstring); +static int gdrom_packetcommand(struct cdrom_device_info *cd_info, + struct packet_command *command); +static int gdrom_hardreset(struct cdrom_device_info *cd_info); + +static bool gdrom_is_busy(void) +{ + return (ctrl_inb(GDROM_ALTSTATUS_REG) & 0x80) != 0; +} + +static bool gdrom_data_request(void) +{ + return (ctrl_inb(GDROM_ALTSTATUS_REG) & 0x88) == 8; +} + +static bool gdrom_wait_clrbusy(void) +{ + unsigned long timeout = jiffies + GDROM_DEFAULT_TIMEOUT; + while ((ctrl_inb(GDROM_ALTSTATUS_REG) & 0x80) && + (time_before(jiffies, timeout))) + cpu_relax(); + return time_before(jiffies, timeout + 1); +} + +static bool gdrom_wait_busy_sleeps(void) +{ + unsigned long timeout; + /* Wait to get busy first */ + timeout = jiffies + GDROM_DEFAULT_TIMEOUT; + while (!gdrom_is_busy() && time_before(jiffies, timeout)) + cpu_relax(); + /* Now wait for busy to clear */ + return gdrom_wait_clrbusy(); +} + +static void gdrom_identifydevice(void *buf) +{ + int c; + short *data = buf; + /* If the device won't clear it has probably + * been hit by a serious failure - but we'll + * try to return a sense key even so */ + if (!gdrom_wait_clrbusy()) { + gdrom_getsense(NULL); + return; + } + ctrl_outb(GDROM_COM_IDDEV, GDROM_STATUSCOMMAND_REG); + if (!gdrom_wait_busy_sleeps()) { + gdrom_getsense(NULL); + return; + } + /* now read in the data */ + for (c = 0; c < 40; c++) + data[c] = ctrl_inw(GDROM_DATA_REG); +} + +static void gdrom_spicommand(void *spi_string, int buflen) +{ + short *cmd = spi_string; + unsigned long timeout; + + /* ensure IRQ_WAIT is set */ + ctrl_outb(0x08, GDROM_ALTSTATUS_REG); + /* specify how many bytes we expect back */ + ctrl_outb(buflen & 0xFF, GDROM_BCL_REG); + ctrl_outb((buflen >> 8) & 0xFF, GDROM_BCH_REG); + /* other parameters */ + ctrl_outb(0, GDROM_INTSEC_REG); + ctrl_outb(0, GDROM_SECNUM_REG); + ctrl_outb(0, GDROM_ERROR_REG); + /* Wait until we can go */ + if (!gdrom_wait_clrbusy()) { + gdrom_getsense(NULL); + return; + } + timeout = jiffies + GDROM_DEFAULT_TIMEOUT; + ctrl_outb(GDROM_COM_PACKET, GDROM_STATUSCOMMAND_REG); + while (!gdrom_data_request() && time_before(jiffies, timeout)) + cpu_relax(); + if (!time_before(jiffies, timeout + 1)) { + gdrom_getsense(NULL); + return; + } + outsw(PHYSADDR(GDROM_DATA_REG), cmd, 6); +} + + +/* gdrom_command_executediagnostic: + * Used to probe for presence of working GDROM + * Restarts GDROM device and then applies standard ATA 3 + * Execute Diagnostic Command: a return of '1' indicates device 0 + * present and device 1 absent + */ +static char gdrom_execute_diagnostic(void) +{ + gdrom_hardreset(gd.cd_info); + if (!gdrom_wait_clrbusy()) + return 0; + ctrl_outb(GDROM_COM_EXECDIAG, GDROM_STATUSCOMMAND_REG); + if (!gdrom_wait_busy_sleeps()) + return 0; + return ctrl_inb(GDROM_ERROR_REG); +} + +/* + * Prepare disk command + * byte 0 = 0x70 + * byte 1 = 0x1f + */ +static int gdrom_preparedisk_cmd(void) +{ + struct packet_command *spin_command; + spin_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL); + if (!spin_command) + return -ENOMEM; + spin_command->cmd[0] = 0x70; + spin_command->cmd[2] = 0x1f; + spin_command->buflen = 0; + gd.pending = 1; + gdrom_packetcommand(gd.cd_info, spin_command); + /* 60 second timeout */ + wait_event_interruptible_timeout(command_queue, gd.pending == 0, + GDROM_DEFAULT_TIMEOUT); + gd.pending = 0; + kfree(spin_command); + if (gd.status & 0x01) { + /* log an error */ + gdrom_getsense(NULL); + return -EIO; + } + return 0; +} + +/* + * Read TOC command + * byte 0 = 0x14 + * byte 1 = session + * byte 3 = sizeof TOC >> 8 ie upper byte + * byte 4 = sizeof TOC & 0xff ie lower byte + */ +static int gdrom_readtoc_cmd(struct gdromtoc *toc, int session) +{ + int tocsize; + struct packet_command *toc_command; + int err = 0; + + toc_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL); + if (!toc_command) + return -ENOMEM; + tocsize = sizeof(struct gdromtoc); + toc_command->cmd[0] = 0x14; + toc_command->cmd[1] = session; + toc_command->cmd[3] = tocsize >> 8; + toc_command->cmd[4] = tocsize & 0xff; + toc_command->buflen = tocsize; + if (gd.pending) { + err = -EBUSY; + goto cleanup_readtoc_final; + } + gd.pending = 1; + gdrom_packetcommand(gd.cd_info, toc_command); + wait_event_interruptible_timeout(command_queue, gd.pending == 0, + GDROM_DEFAULT_TIMEOUT); + if (gd.pending) { + err = -EINVAL; + goto cleanup_readtoc; + } + insw(PHYSADDR(GDROM_DATA_REG), toc, tocsize/2); + if (gd.status & 0x01) + err = -EINVAL; + +cleanup_readtoc: + gd.pending = 0; +cleanup_readtoc_final: + kfree(toc_command); + return err; +} + +/* TOC helpers */ +static int get_entry_lba(int track) +{ + return (cpu_to_be32(track & 0xffffff00) - GD_SESSION_OFFSET); +} + +static int get_entry_q_ctrl(int track) +{ + return (track & 0x000000f0) >> 4; +} + +static int get_entry_track(int track) +{ + return (track & 0x0000ff00) >> 8; +} + +static int gdrom_get_last_session(struct cdrom_device_info *cd_info, + struct cdrom_multisession *ms_info) +{ + int fentry, lentry, track, data, tocuse, err; + if (!gd.toc) + return -ENOMEM; + tocuse = 1; + /* Check if GD-ROM */ + err = gdrom_readtoc_cmd(gd.toc, 1); + /* Not a GD-ROM so check if standard CD-ROM */ + if (err) { + tocuse = 0; + err = gdrom_readtoc_cmd(gd.toc, 0); + if (err) { + printk(KERN_INFO "GDROM: Could not get CD " + "table of contents\n"); + return -ENXIO; + } + } + + fentry = get_entry_track(gd.toc->first); + lentry = get_entry_track(gd.toc->last); + /* Find the first data track */ + track = get_entry_track(gd.toc->last); + do { + data = gd.toc->entry[track - 1]; + if (get_entry_q_ctrl(data)) + break; /* ie a real data track */ + track--; + } while (track >= fentry); + + if ((track > 100) || (track < get_entry_track(gd.toc->first))) { + printk(KERN_INFO "GDROM: No data on the last " + "session of the CD\n"); + gdrom_getsense(NULL); + return -ENXIO; + } + + ms_info->addr_format = CDROM_LBA; + ms_info->addr.lba = get_entry_lba(data); + ms_info->xa_flag = 1; + return 0; +} + +static int gdrom_open(struct cdrom_device_info *cd_info, int purpose) +{ + /* spin up the disk */ + return gdrom_preparedisk_cmd(); +} + +/* this function is required even if empty */ +static void gdrom_release(struct cdrom_device_info *cd_info) +{ +} + +static int gdrom_drivestatus(struct cdrom_device_info *cd_info, int ignore) +{ + /* read the sense key */ + char sense = ctrl_inb(GDROM_ERROR_REG); + sense &= 0xF0; + if (sense == 0) + return CDS_DISC_OK; + if (sense == 0x20) + return CDS_DRIVE_NOT_READY; + /* default */ + return CDS_NO_INFO; +} + +static int gdrom_mediachanged(struct cdrom_device_info *cd_info, int ignore) +{ + /* check the sense key */ + return (ctrl_inb(GDROM_ERROR_REG) & 0xF0) == 0x60; +} + +/* reset the G1 bus */ +static int gdrom_hardreset(struct cdrom_device_info *cd_info) +{ + int count; + ctrl_outl(0x1fffff, GDROM_RESET_REG); + for (count = 0xa0000000; count < 0xa0200000; count += 4) + ctrl_inl(count); + return 0; +} + +/* keep the function looking like the universal + * CD Rom specification - returning int */ +static int gdrom_packetcommand(struct cdrom_device_info *cd_info, + struct packet_command *command) +{ + gdrom_spicommand(&command->cmd, command->buflen); + return 0; +} + +/* Get Sense SPI command + * From Marcus Comstedt + * cmd = 0x13 + * cmd + 4 = length of returned buffer + * Returns 5 16 bit words + */ +static int gdrom_getsense(short *bufstring) +{ + struct packet_command *sense_command; + short sense[5]; + int sense_key; + int err = -EIO; + + sense_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL); + if (!sense_command) + return -ENOMEM; + sense_command->cmd[0] = 0x13; + sense_command->cmd[4] = 10; + sense_command->buflen = 10; + /* even if something is pending try to get + * the sense key if possible */ + if (gd.pending && !gdrom_wait_clrbusy()) { + err = -EBUSY; + goto cleanup_sense_final; + } + gd.pending = 1; + gdrom_packetcommand(gd.cd_info, sense_command); + wait_event_interruptible_timeout(command_queue, gd.pending == 0, + GDROM_DEFAULT_TIMEOUT); + if (gd.pending) + goto cleanup_sense; + insw(PHYSADDR(GDROM_DATA_REG), &sense, sense_command->buflen/2); + if (sense[1] & 40) { + printk(KERN_INFO "GDROM: Drive not ready - command aborted\n"); + goto cleanup_sense; + } + sense_key = sense[1] & 0x0F; + if (sense_key < ARRAY_SIZE(sense_texts)) + printk(KERN_INFO "GDROM: %s\n", sense_texts[sense_key].text); + else + printk(KERN_ERR "GDROM: Unknown sense key: %d\n", sense_key); + if (bufstring) /* return addional sense data */ + memcpy(bufstring, &sense[4], 2); + if (sense_key < 2) + err = 0; + +cleanup_sense: + gd.pending = 0; +cleanup_sense_final: + kfree(sense_command); + return err; +} + +static struct cdrom_device_ops gdrom_ops = { + .open = gdrom_open, + .release = gdrom_release, + .drive_status = gdrom_drivestatus, + .media_changed = gdrom_mediachanged, + .get_last_session = gdrom_get_last_session, + .reset = gdrom_hardreset, + .capability = CDC_MULTI_SESSION | CDC_MEDIA_CHANGED | + CDC_RESET | CDC_DRIVE_STATUS | CDC_CD_R, + .n_minors = 1, +}; + +static int gdrom_bdops_open(struct inode *inode, struct file *file) +{ + return cdrom_open(gd.cd_info, inode, file); +} + +static int gdrom_bdops_release(struct inode *inode, struct file *file) +{ + return cdrom_release(gd.cd_info, file); +} + +static int gdrom_bdops_mediachanged(struct gendisk *disk) +{ + return cdrom_media_changed(gd.cd_info); +} + +static int gdrom_bdops_ioctl(struct inode *inode, struct file *file, + unsigned cmd, unsigned long arg) +{ + return cdrom_ioctl(file, gd.cd_info, inode, cmd, arg); +} + +static struct block_device_operations gdrom_bdops = { + .owner = THIS_MODULE, + .open = gdrom_bdops_open, + .release = gdrom_bdops_release, + .media_changed = gdrom_bdops_mediachanged, + .ioctl = gdrom_bdops_ioctl, +}; + +static irqreturn_t gdrom_command_interrupt(int irq, void *dev_id) +{ + gd.status = ctrl_inb(GDROM_STATUSCOMMAND_REG); + if (gd.pending != 1) + return IRQ_HANDLED; + gd.pending = 0; + wake_up_interruptible(&command_queue); + return IRQ_HANDLED; +} + +static irqreturn_t gdrom_dma_interrupt(int irq, void *dev_id) +{ + gd.status = ctrl_inb(GDROM_STATUSCOMMAND_REG); + if (gd.transfer != 1) + return IRQ_HANDLED; + gd.transfer = 0; + wake_up_interruptible(&request_queue); + return IRQ_HANDLED; +} + +static int __devinit gdrom_set_interrupt_handlers(void) +{ + int err; + + err = request_irq(HW_EVENT_GDROM_CMD, gdrom_command_interrupt, + IRQF_DISABLED, "gdrom_command", &gd); + if (err) + return err; + err = request_irq(HW_EVENT_GDROM_DMA, gdrom_dma_interrupt, + IRQF_DISABLED, "gdrom_dma", &gd); + if (err) + free_irq(HW_EVENT_GDROM_CMD, &gd); + return err; +} + +/* Implement DMA read using SPI command + * 0 -> 0x30 + * 1 -> mode + * 2 -> block >> 16 + * 3 -> block >> 8 + * 4 -> block + * 8 -> sectors >> 16 + * 9 -> sectors >> 8 + * 10 -> sectors + */ +static void gdrom_readdisk_dma(struct work_struct *work) +{ + int err, block, block_cnt; + struct packet_command *read_command; + struct list_head *elem, *next; + struct request *req; + unsigned long timeout; + + if (list_empty(&gdrom_deferred)) + return; + read_command = kzalloc(sizeof(struct packet_command), GFP_KERNEL); + if (!read_command) + return; /* get more memory later? */ + read_command->cmd[0] = 0x30; + read_command->cmd[1] = 0x20; + spin_lock(&gdrom_lock); + list_for_each_safe(elem, next, &gdrom_deferred) { + req = list_entry(elem, struct request, queuelist); + spin_unlock(&gdrom_lock); + block = req->sector/GD_TO_BLK + GD_SESSION_OFFSET; + block_cnt = req->nr_sectors/GD_TO_BLK; + ctrl_outl(PHYSADDR(req->buffer), GDROM_DMA_STARTADDR_REG); + ctrl_outl(block_cnt * GDROM_HARD_SECTOR, GDROM_DMA_LENGTH_REG); + ctrl_outl(1, GDROM_DMA_DIRECTION_REG); + ctrl_outl(1, GDROM_DMA_ENABLE_REG); + read_command->cmd[2] = (block >> 16) & 0xFF; + read_command->cmd[3] = (block >> 8) & 0xFF; + read_command->cmd[4] = block & 0xFF; + read_command->cmd[8] = (block_cnt >> 16) & 0xFF; + read_command->cmd[9] = (block_cnt >> 8) & 0xFF; + read_command->cmd[10] = block_cnt & 0xFF; + /* set for DMA */ + ctrl_outb(1, GDROM_ERROR_REG); + /* other registers */ + ctrl_outb(0, GDROM_SECNUM_REG); + ctrl_outb(0, GDROM_BCL_REG); + ctrl_outb(0, GDROM_BCH_REG); + ctrl_outb(0, GDROM_DSEL_REG); + ctrl_outb(0, GDROM_INTSEC_REG); + /* Wait for registers to reset after any previous activity */ + timeout = jiffies + HZ / 2; + while (gdrom_is_busy() && time_before(jiffies, timeout)) + cpu_relax(); + ctrl_outb(GDROM_COM_PACKET, GDROM_STATUSCOMMAND_REG); + timeout = jiffies + HZ / 2; + /* Wait for packet command to finish */ + while (gdrom_is_busy() && time_before(jiffies, timeout)) + cpu_relax(); + gd.pending = 1; + gd.transfer = 1; + outsw(PHYSADDR(GDROM_DATA_REG), &read_command->cmd, 6); + timeout = jiffies + HZ / 2; + /* Wait for any pending DMA to finish */ + while (ctrl_inb(GDROM_DMA_STATUS_REG) && + time_before(jiffies, timeout)) + cpu_relax(); + /* start transfer */ + ctrl_outb(1, GDROM_DMA_STATUS_REG); + wait_event_interruptible_timeout(request_queue, + gd.transfer == 0, GDROM_DEFAULT_TIMEOUT); + err = gd.transfer; + gd.transfer = 0; + gd.pending = 0; + /* now seek to take the request spinlock + * before handling ending the request */ + spin_lock(&gdrom_lock); + list_del_init(&req->queuelist); + end_dequeued_request(req, 1 - err); + } + spin_unlock(&gdrom_lock); + kfree(read_command); +} + +static void gdrom_request_handler_dma(struct request *req) +{ + /* dequeue, add to list of deferred work + * and then schedule workqueue */ + blkdev_dequeue_request(req); + list_add_tail(&req->queuelist, &gdrom_deferred); + schedule_work(&work); +} + +static void gdrom_request(struct request_queue *rq) +{ + struct request *req; + + while ((req = elv_next_request(rq)) != NULL) { + if (!blk_fs_request(req)) { + printk(KERN_DEBUG "GDROM: Non-fs request ignored\n"); + end_request(req, 0); + } + if (rq_data_dir(req) != READ) { + printk(KERN_NOTICE "GDROM: Read only device -"); + printk(" write request ignored\n"); + end_request(req, 0); + } + if (req->nr_sectors) + gdrom_request_handler_dma(req); + else + end_request(req, 0); + } +} + +/* Print string identifying GD ROM device */ +static int __devinit gdrom_outputversion(void) +{ + struct gdrom_id *id; + char *model_name, *manuf_name, *firmw_ver; + int err = -ENOMEM; + + /* query device ID */ + id = kzalloc(sizeof(struct gdrom_id), GFP_KERNEL); + if (!id) + return err; + gdrom_identifydevice(id); + model_name = kstrndup(id->modname, 16, GFP_KERNEL); + if (!model_name) + goto free_id; + manuf_name = kstrndup(id->mname, 16, GFP_KERNEL); + if (!manuf_name) + goto free_model_name; + firmw_ver = kstrndup(id->firmver, 16, GFP_KERNEL); + if (!firmw_ver) + goto free_manuf_name; + printk(KERN_INFO "GDROM: %s from %s with firmware %s\n", + model_name, manuf_name, firmw_ver); + err = 0; + kfree(firmw_ver); +free_manuf_name: + kfree(manuf_name); +free_model_name: + kfree(model_name); +free_id: + kfree(id); + return err; +} + +/* set the default mode for DMA transfer */ +static int __devinit gdrom_init_dma_mode(void) +{ + ctrl_outb(0x13, GDROM_ERROR_REG); + ctrl_outb(0x22, GDROM_INTSEC_REG); + if (!gdrom_wait_clrbusy()) + return -EBUSY; + ctrl_outb(0xEF, GDROM_STATUSCOMMAND_REG); + if (!gdrom_wait_busy_sleeps()) + return -EBUSY; + /* Memory protection setting for GDROM DMA + * Bits 31 - 16 security: 0x8843 + * Bits 15 and 7 reserved (0) + * Bits 14 - 8 start of transfer range in 1 MB blocks OR'ed with 0x80 + * Bits 6 - 0 end of transfer range in 1 MB blocks OR'ed with 0x80 + * (0x40 | 0x80) = start range at 0x0C000000 + * (0x7F | 0x80) = end range at 0x0FFFFFFF */ + ctrl_outl(0x8843407F, GDROM_DMA_ACCESS_CTRL_REG); + ctrl_outl(9, GDROM_DMA_WAIT_REG); /* DMA word setting */ + return 0; +} + +static void __devinit probe_gdrom_setupcd(void) +{ + gd.cd_info->ops = &gdrom_ops; + gd.cd_info->capacity = 1; + strcpy(gd.cd_info->name, GDROM_DEV_NAME); + gd.cd_info->mask = CDC_CLOSE_TRAY|CDC_OPEN_TRAY|CDC_LOCK| + CDC_SELECT_DISC; +} + +static void __devinit probe_gdrom_setupdisk(void) +{ + gd.disk->major = gdrom_major; + gd.disk->first_minor = 1; + gd.disk->minors = 1; + strcpy(gd.disk->disk_name, GDROM_DEV_NAME); +} + +static int __devinit probe_gdrom_setupqueue(void) +{ + blk_queue_hardsect_size(gd.gdrom_rq, GDROM_HARD_SECTOR); + /* using DMA so memory will need to be contiguous */ + blk_queue_max_hw_segments(gd.gdrom_rq, 1); + /* set a large max size to get most from DMA */ + blk_queue_max_segment_size(gd.gdrom_rq, 0x40000); + gd.disk->queue = gd.gdrom_rq; + return gdrom_init_dma_mode(); +} + +/* + * register this as a block device and as compliant with the + * universal CD Rom driver interface + */ +static int __devinit probe_gdrom(struct platform_device *devptr) +{ + int err; + /* Start the device */ + if (gdrom_execute_diagnostic() != 1) { + printk(KERN_WARNING "GDROM: ATA Probe for GDROM failed.\n"); + return -ENODEV; + } + /* Print out firmware ID */ + if (gdrom_outputversion()) + return -ENOMEM; + /* Register GDROM */ + gdrom_major = register_blkdev(0, GDROM_DEV_NAME); + if (gdrom_major <= 0) + return gdrom_major; + printk(KERN_INFO "GDROM: Registered with major number %d\n", + gdrom_major); + /* Specify basic properties of drive */ + gd.cd_info = kzalloc(sizeof(struct cdrom_device_info), GFP_KERNEL); + if (!gd.cd_info) { + err = -ENOMEM; + goto probe_fail_no_mem; + } + probe_gdrom_setupcd(); + gd.disk = alloc_disk(1); + if (!gd.disk) { + err = -ENODEV; + goto probe_fail_no_disk; + } + probe_gdrom_setupdisk(); + if (register_cdrom(gd.cd_info)) { + err = -ENODEV; + goto probe_fail_cdrom_register; + } + gd.disk->fops = &gdrom_bdops; + /* latch on to the interrupt */ + err = gdrom_set_interrupt_handlers(); + if (err) + goto probe_fail_cmdirq_register; + gd.gdrom_rq = blk_init_queue(gdrom_request, &gdrom_lock); + if (!gd.gdrom_rq) + goto probe_fail_requestq; + + err = probe_gdrom_setupqueue(); + if (err) + goto probe_fail_toc; + + gd.toc = kzalloc(sizeof(struct gdromtoc), GFP_KERNEL); + if (!gd.toc) + goto probe_fail_toc; + add_disk(gd.disk); + return 0; + +probe_fail_toc: + blk_cleanup_queue(gd.gdrom_rq); +probe_fail_requestq: + free_irq(HW_EVENT_GDROM_DMA, &gd); + free_irq(HW_EVENT_GDROM_CMD, &gd); +probe_fail_cmdirq_register: +probe_fail_cdrom_register: + del_gendisk(gd.disk); +probe_fail_no_disk: + kfree(gd.cd_info); + unregister_blkdev(gdrom_major, GDROM_DEV_NAME); + gdrom_major = 0; +probe_fail_no_mem: + printk(KERN_WARNING "GDROM: Probe failed - error is 0x%X\n", err); + return err; +} + +static int __devexit remove_gdrom(struct platform_device *devptr) +{ + flush_scheduled_work(); + blk_cleanup_queue(gd.gdrom_rq); + free_irq(HW_EVENT_GDROM_CMD, &gd); + free_irq(HW_EVENT_GDROM_DMA, &gd); + del_gendisk(gd.disk); + if (gdrom_major) + unregister_blkdev(gdrom_major, GDROM_DEV_NAME); + return unregister_cdrom(gd.cd_info); +} + +static struct platform_driver gdrom_driver = { + .probe = probe_gdrom, + .remove = __devexit_p(remove_gdrom), + .driver = { + .name = GDROM_DEV_NAME, + }, +}; + +static int __init init_gdrom(void) +{ + int rc; + gd.toc = NULL; + rc = platform_driver_register(&gdrom_driver); + if (rc) + return rc; + pd = platform_device_register_simple(GDROM_DEV_NAME, -1, NULL, 0); + if (IS_ERR(pd)) { + platform_driver_unregister(&gdrom_driver); + return PTR_ERR(pd); + } + return 0; +} + +static void __exit exit_gdrom(void) +{ + platform_device_unregister(pd); + platform_driver_unregister(&gdrom_driver); + kfree(gd.toc); +} + +module_init(init_gdrom); +module_exit(exit_gdrom); +MODULE_AUTHOR("Adrian McMenamin "); +MODULE_DESCRIPTION("SEGA Dreamcast GD-ROM Driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3