From 1b0acbfdb8a8884f18fdb2caa85b4beded2390fb Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Tue, 6 Sep 2016 23:38:45 +0200 Subject: stmmac: introduce get_stmmac_bsp_priv() helper Create a helper to retrieve dwmac private data from a dev pointer. This is useful in PM callbacks and driver remove. Signed-off-by: Joachim Eastwood Tested-by: Martin Blumenstingl Acked-by: David S. Miller Signed-off-by: Kevin Hilman --- drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers') diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h index ffeb8d9e2b2e..64e147f53a9c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.h @@ -30,4 +30,12 @@ int stmmac_get_platform_resources(struct platform_device *pdev, int stmmac_pltfr_remove(struct platform_device *pdev); extern const struct dev_pm_ops stmmac_pltfr_pm_ops; +static inline void *get_stmmac_bsp_priv(struct device *dev) +{ + struct net_device *ndev = dev_get_drvdata(dev); + struct stmmac_priv *priv = netdev_priv(ndev); + + return priv->plat->bsp_priv; +} + #endif /* __STMMAC_PLATFORM_H__ */ -- cgit v1.2.3 From 566e8251625304e291bc1e2e7d57850ccf0502f5 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 6 Sep 2016 23:38:46 +0200 Subject: net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC The Ethernet controller available in Meson8b and GXBB SoCs is a Synopsys DesignWare MAC IP core which is already supported by the stmmac driver. In addition to the standard stmmac driver some Meson8b / GXBB specific registers have to be configured for the PHY clocks. These SoC specific registers are called PRG_ETHERNET_ADDR0 and PRG_ETHERNET_ADDR1 in the datasheet. These registers are not backwards compatible with those on Meson 6b, which is why a new glue driver is introduced. This worked for many boards because the bootloader programs the PRG_ETHERNET registers correctly. Additionally the meson6-dwmac driver only sets bit 1 of PRG_ETHERNET_ADDR0 which (according to the datasheet) is only used during reset. Currently all configuration values can be determined automatically, based on the configured phy-mode (which is mandatory for the stmmac driver). If required the tx-delay and the mux clock (so it supports the MPLL2 clock as well) can be made configurable in the future. Signed-off-by: Martin Blumenstingl Tested-by: Kevin Hilman Acked-by: David S. Miller Signed-off-by: Kevin Hilman --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 6 +- drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +- .../net/ethernet/stmicro/stmmac/dwmac-meson8b.c | 324 +++++++++++++++++++++ 3 files changed, 328 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c (limited to 'drivers') diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 8f06a6621ab1..54de17529c97 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -61,13 +61,13 @@ config DWMAC_LPC18XX config DWMAC_MESON tristate "Amlogic Meson dwmac support" default ARCH_MESON - depends on OF && (ARCH_MESON || COMPILE_TEST) + depends on OF && COMMON_CLK && (ARCH_MESON || COMPILE_TEST) help Support for Ethernet controller on Amlogic Meson SoCs. This selects the Amlogic Meson SoC glue layer support for - the stmmac device driver. This driver is used for Meson6 and - Meson8 SoCs. + the stmmac device driver. This driver is used for Meson6, + Meson8, Meson8b and GXBB SoCs. config DWMAC_ROCKCHIP tristate "Rockchip dwmac support" diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile index 44b630cd1755..f77edb9c2fa9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -9,7 +9,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \ obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o obj-$(CONFIG_DWMAC_IPQ806X) += dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) += dwmac-lpc18xx.o -obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o +obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c new file mode 100644 index 000000000000..250e4ceafc8d --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c @@ -0,0 +1,324 @@ +/* + * Amlogic Meson8b and GXBB DWMAC glue layer + * + * Copyright (C) 2016 Martin Blumenstingl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" + +#define PRG_ETH0 0x0 + +#define PRG_ETH0_RGMII_MODE BIT(0) + +/* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */ +#define PRG_ETH0_CLK_M250_SEL_SHIFT 4 +#define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4) + +#define PRG_ETH0_TXDLY_SHIFT 5 +#define PRG_ETH0_TXDLY_MASK GENMASK(6, 5) +#define PRG_ETH0_TXDLY_OFF (0x0 << PRG_ETH0_TXDLY_SHIFT) +#define PRG_ETH0_TXDLY_QUARTER (0x1 << PRG_ETH0_TXDLY_SHIFT) +#define PRG_ETH0_TXDLY_HALF (0x2 << PRG_ETH0_TXDLY_SHIFT) +#define PRG_ETH0_TXDLY_THREE_QUARTERS (0x3 << PRG_ETH0_TXDLY_SHIFT) + +/* divider for the result of m250_sel */ +#define PRG_ETH0_CLK_M250_DIV_SHIFT 7 +#define PRG_ETH0_CLK_M250_DIV_WIDTH 3 + +/* divides the result of m25_sel by either 5 (bit unset) or 10 (bit set) */ +#define PRG_ETH0_CLK_M25_DIV_SHIFT 10 +#define PRG_ETH0_CLK_M25_DIV_WIDTH 1 + +#define PRG_ETH0_INVERTED_RMII_CLK BIT(11) +#define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12) + +#define MUX_CLK_NUM_PARENTS 2 + +struct meson8b_dwmac { + struct platform_device *pdev; + + void __iomem *regs; + + phy_interface_t phy_mode; + + struct clk_mux m250_mux; + struct clk *m250_mux_clk; + struct clk *m250_mux_parent[MUX_CLK_NUM_PARENTS]; + + struct clk_divider m250_div; + struct clk *m250_div_clk; + + struct clk_divider m25_div; + struct clk *m25_div_clk; +}; + +static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg, + u32 mask, u32 value) +{ + u32 data; + + data = readl(dwmac->regs + reg); + data &= ~mask; + data |= (value & mask); + + writel(data, dwmac->regs + reg); +} + +static int meson8b_init_clk(struct meson8b_dwmac *dwmac) +{ + struct clk_init_data init; + int i, ret; + struct device *dev = &dwmac->pdev->dev; + char clk_name[32]; + const char *clk_div_parents[1]; + const char *mux_parent_names[MUX_CLK_NUM_PARENTS]; + static struct clk_div_table clk_25m_div_table[] = { + { .val = 0, .div = 5 }, + { .val = 1, .div = 10 }, + { /* sentinel */ }, + }; + + /* get the mux parents from DT */ + for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { + char name[16]; + + snprintf(name, sizeof(name), "clkin%d", i); + dwmac->m250_mux_parent[i] = devm_clk_get(dev, name); + if (IS_ERR(dwmac->m250_mux_parent[i])) { + ret = PTR_ERR(dwmac->m250_mux_parent[i]); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Missing clock %s\n", name); + return ret; + } + + mux_parent_names[i] = + __clk_get_name(dwmac->m250_mux_parent[i]); + } + + /* create the m250_mux */ + snprintf(clk_name, sizeof(clk_name), "%s#m250_sel", dev_name(dev)); + init.name = clk_name; + init.ops = &clk_mux_ops; + init.flags = 0; + init.parent_names = mux_parent_names; + init.num_parents = MUX_CLK_NUM_PARENTS; + + dwmac->m250_mux.reg = dwmac->regs + PRG_ETH0; + dwmac->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT; + dwmac->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK; + dwmac->m250_mux.flags = 0; + dwmac->m250_mux.table = NULL; + dwmac->m250_mux.hw.init = &init; + + dwmac->m250_mux_clk = devm_clk_register(dev, &dwmac->m250_mux.hw); + if (WARN_ON(IS_ERR(dwmac->m250_mux_clk))) + return PTR_ERR(dwmac->m250_mux_clk); + + /* create the m250_div */ + snprintf(clk_name, sizeof(clk_name), "%s#m250_div", dev_name(dev)); + init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + clk_div_parents[0] = __clk_get_name(dwmac->m250_mux_clk); + init.parent_names = clk_div_parents; + init.num_parents = ARRAY_SIZE(clk_div_parents); + + dwmac->m250_div.reg = dwmac->regs + PRG_ETH0; + dwmac->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT; + dwmac->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH; + dwmac->m250_div.hw.init = &init; + dwmac->m250_div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; + + dwmac->m250_div_clk = devm_clk_register(dev, &dwmac->m250_div.hw); + if (WARN_ON(IS_ERR(dwmac->m250_div_clk))) + return PTR_ERR(dwmac->m250_div_clk); + + /* create the m25_div */ + snprintf(clk_name, sizeof(clk_name), "%s#m25_div", dev_name(dev)); + init.name = devm_kstrdup(dev, clk_name, GFP_KERNEL); + init.ops = &clk_divider_ops; + init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT; + clk_div_parents[0] = __clk_get_name(dwmac->m250_div_clk); + init.parent_names = clk_div_parents; + init.num_parents = ARRAY_SIZE(clk_div_parents); + + dwmac->m25_div.reg = dwmac->regs + PRG_ETH0; + dwmac->m25_div.shift = PRG_ETH0_CLK_M25_DIV_SHIFT; + dwmac->m25_div.width = PRG_ETH0_CLK_M25_DIV_WIDTH; + dwmac->m25_div.table = clk_25m_div_table; + dwmac->m25_div.hw.init = &init; + dwmac->m25_div.flags = CLK_DIVIDER_ALLOW_ZERO; + + dwmac->m25_div_clk = devm_clk_register(dev, &dwmac->m25_div.hw); + if (WARN_ON(IS_ERR(dwmac->m25_div_clk))) + return PTR_ERR(dwmac->m25_div_clk); + + return 0; +} + +static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) +{ + int ret; + unsigned long clk_rate; + + switch (dwmac->phy_mode) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + /* Generate a 25MHz clock for the PHY */ + clk_rate = 25 * 1000 * 1000; + + /* enable RGMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, + PRG_ETH0_RGMII_MODE); + + /* only relevant for RMII mode -> disable in RGMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_INVERTED_RMII_CLK, 0); + + /* TX clock delay - all known boards use a 1/4 cycle delay */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, + PRG_ETH0_TXDLY_QUARTER); + break; + + case PHY_INTERFACE_MODE_RMII: + /* Use the rate of the mux clock for the internal RMII PHY */ + clk_rate = clk_get_rate(dwmac->m250_mux_clk); + + /* disable RGMII mode -> enables RMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_RGMII_MODE, + 0); + + /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, + PRG_ETH0_INVERTED_RMII_CLK, + PRG_ETH0_INVERTED_RMII_CLK); + + /* TX clock delay cannot be configured in RMII mode */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK, + 0); + + break; + + default: + dev_err(&dwmac->pdev->dev, "unsupported phy-mode %s\n", + phy_modes(dwmac->phy_mode)); + return -EINVAL; + } + + ret = clk_prepare_enable(dwmac->m25_div_clk); + if (ret) { + dev_err(&dwmac->pdev->dev, "failed to enable the PHY clock\n"); + return ret; + } + + ret = clk_set_rate(dwmac->m25_div_clk, clk_rate); + if (ret) { + clk_disable_unprepare(dwmac->m25_div_clk); + + dev_err(&dwmac->pdev->dev, "failed to set PHY clock\n"); + return ret; + } + + /* enable TX_CLK and PHY_REF_CLK generator */ + meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK, + PRG_ETH0_TX_AND_PHY_REF_CLK); + + return 0; +} + +static int meson8b_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct resource *res; + struct meson8b_dwmac *dwmac; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); + if (!dwmac) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dwmac->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(dwmac->regs)) + return PTR_ERR(dwmac->regs); + + dwmac->pdev = pdev; + dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node); + if (dwmac->phy_mode < 0) { + dev_err(&pdev->dev, "missing phy-mode property\n"); + return -EINVAL; + } + + ret = meson8b_init_clk(dwmac); + if (ret) + return ret; + + ret = meson8b_init_prg_eth(dwmac); + if (ret) + return ret; + + plat_dat->bsp_priv = dwmac; + + return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); +} + +static int meson8b_dwmac_remove(struct platform_device *pdev) +{ + struct meson8b_dwmac *dwmac = get_stmmac_bsp_priv(&pdev->dev); + + clk_disable_unprepare(dwmac->m25_div_clk); + + return stmmac_pltfr_remove(pdev); +} + +static const struct of_device_id meson8b_dwmac_match[] = { + { .compatible = "amlogic,meson8b-dwmac" }, + { .compatible = "amlogic,meson-gxbb-dwmac" }, + { } +}; +MODULE_DEVICE_TABLE(of, meson8b_dwmac_match); + +static struct platform_driver meson8b_dwmac_driver = { + .probe = meson8b_dwmac_probe, + .remove = meson8b_dwmac_remove, + .driver = { + .name = "meson8b-dwmac", + .pm = &stmmac_pltfr_pm_ops, + .of_match_table = meson8b_dwmac_match, + }, +}; +module_platform_driver(meson8b_dwmac_driver); + +MODULE_AUTHOR("Martin Blumenstingl "); +MODULE_DESCRIPTION("Amlogic Meson8b and GXBB DWMAC glue layer"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 466fd24b681c734640ebefb1e611df0a5f10d011 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 6 Sep 2016 23:38:48 +0200 Subject: net: stmmac: update the module description of the dwmac-meson driver The dwmac-meson glue driver supports Meson6 and Meson8 SoCs. Newer SoCs are supported by the dwmac-meson8b driver. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c index c1bac1912b37..309d99536a2c 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c @@ -1,5 +1,5 @@ /* - * Amlogic Meson DWMAC glue layer + * Amlogic Meson6 and Meson8 DWMAC glue layer * * Copyright (C) 2014 Beniamino Galvani * @@ -96,5 +96,5 @@ static struct platform_driver meson6_dwmac_driver = { module_platform_driver(meson6_dwmac_driver); MODULE_AUTHOR("Beniamino Galvani "); -MODULE_DESCRIPTION("Amlogic Meson DWMAC glue layer"); +MODULE_DESCRIPTION("Amlogic Meson6 and Meson8 DWMAC glue layer"); MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From f94310ac076ea2cd84ff42c901e7a17382ad75f8 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Sun, 11 Sep 2016 15:41:06 +0200 Subject: usb: dwc2: add support for Meson8b and GXBB SoCs Add compatible strings for amlogic Meson8b and GXBB SoCs with the corresponding configuration parameters. Signed-off-by: Jerome Brunet Signed-off-by: Martin Blumenstingl Acked-by: John Youn Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/usb/dwc2.txt | 2 ++ drivers/usb/dwc2/platform.c | 34 ++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) (limited to 'drivers') diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt index 20a68bf2b4e7..2c30a5479069 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.txt +++ b/Documentation/devicetree/bindings/usb/dwc2.txt @@ -10,6 +10,8 @@ Required properties: - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc; - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs; - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs; + - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs; + - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs; - snps,dwc2: A generic DWC2 USB controller with default parameters. - reg : Should contain 1 register range (address and length) - interrupts : Should contain 1 interrupt diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index fc6f5251de5d..8f7b34c8a5d4 100644 --- a/drivers/usb/dwc2/platform.c +++ b/drivers/usb/dwc2/platform.c @@ -181,6 +181,38 @@ static const struct dwc2_core_params params_ltq = { .hibernation = -1, }; +static const struct dwc2_core_params params_amlogic = { + .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE, + .otg_ver = -1, + .dma_enable = 1, + .dma_desc_enable = 0, + .dma_desc_fs_enable = 0, + .speed = DWC2_SPEED_PARAM_HIGH, + .enable_dynamic_fifo = 1, + .en_multiple_tx_fifo = -1, + .host_rx_fifo_size = 512, + .host_nperio_tx_fifo_size = 500, + .host_perio_tx_fifo_size = 500, + .max_transfer_size = -1, + .max_packet_count = -1, + .host_channels = 16, + .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, + .phy_utmi_width = -1, + .phy_ulpi_ddr = -1, + .phy_ulpi_ext_vbus = -1, + .i2c_enable = -1, + .ulpi_fs_ls = -1, + .host_support_fs_ls_low_power = -1, + .host_ls_low_power_phy_clk = -1, + .ts_dline = -1, + .reload_ctl = 1, + .ahbcfg = GAHBCFG_HBSTLEN_INCR8 << + GAHBCFG_HBSTLEN_SHIFT, + .uframe_sched = 0, + .external_id_pin_ctl = -1, + .hibernation = -1, +}; + /* * Check the dr_mode against the module configuration and hardware * capabilities. @@ -464,6 +496,8 @@ static const struct of_device_id dwc2_of_match_table[] = { { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq }, { .compatible = "snps,dwc2", .data = NULL }, { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, + { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic }, + { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic }, {}, }; MODULE_DEVICE_TABLE(of, dwc2_of_match_table); -- cgit v1.2.3 From ed6f4b518004845f6f830422cc9e3ab4f0284930 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Tue, 6 Sep 2016 23:38:44 +0200 Subject: clk: gxbb: expose MPLL2 clock for use by DT This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl Acked-by: Stephen Boyd Signed-off-by: Kevin Hilman --- drivers/clk/meson/gxbb.h | 2 +- include/dt-bindings/clock/gxbb-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index ae461b16af75..a05b5f62e580 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -183,7 +183,7 @@ /* CLKID_CLK81 */ #define CLKID_MPLL0 13 #define CLKID_MPLL1 14 -#define CLKID_MPLL2 15 +/* CLKID_MPLL2 */ #define CLKID_DDR 16 #define CLKID_DOS 17 #define CLKID_ISA 18 diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index ce4ad637083d..ccef0283173b 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -11,6 +11,7 @@ #define CLKID_FCLK_DIV3 5 #define CLKID_FCLK_DIV4 6 #define CLKID_CLK81 12 +#define CLKID_MPLL2 15 #define CLKID_ETH 36 #define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_B 95 -- cgit v1.2.3 From f2120a8b090676380d9bce4ea23f855dc8e0d71f Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 7 Sep 2016 17:13:39 +0200 Subject: clk: gxbb: expose spifc clock SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet Acked-by: Stephen Boyd Signed-off-by: Kevin Hilman --- drivers/clk/meson/gxbb.h | 2 +- include/dt-bindings/clock/gxbb-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index a05b5f62e580..4e643149cc3e 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -202,7 +202,7 @@ #define CLKID_ABUF 31 #define CLKID_HIU_IFACE 32 #define CLKID_ASSIST_MISC 33 -#define CLKID_SPI 34 +/* CLKID_SPI */ #define CLKID_I2S_SPDIF 35 #define CLKID_ETH 36 #define CLKID_DEMUX 37 diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index ccef0283173b..7955d7c712f6 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -12,6 +12,7 @@ #define CLKID_FCLK_DIV4 6 #define CLKID_CLK81 12 #define CLKID_MPLL2 15 +#define CLKID_SPI 34 #define CLKID_ETH 36 #define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_B 95 -- cgit v1.2.3 From 5dbe7890e6e998b49aac3f0a6455803c956a49c9 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Sep 2016 23:31:46 +0200 Subject: clk: gxbb: expose USB clocks USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet Acked-by: Stephen Boyd Signed-off-by: Kevin Hilman --- drivers/clk/meson/gxbb.h | 10 +++++----- include/dt-bindings/clock/gxbb-clkc.h | 5 +++++ 2 files changed, 10 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 4e643149cc3e..044fc44e9144 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -218,12 +218,12 @@ #define CLKID_AIU 47 #define CLKID_UART1 48 #define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 +/* CLKID_USB0 */ +/* CLKID_USB1 */ #define CLKID_RESET 52 #define CLKID_NAND 53 #define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 +/* CLKID_USB */ #define CLKID_VDIN1 56 #define CLKID_AHB_ARB0 57 #define CLKID_EFUSE 58 @@ -232,8 +232,8 @@ #define CLKID_AHB_CTRL_BUS 61 #define CLKID_HDMI_INTR_SYNC 62 #define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 +/* CLKID_USB1_DDR_BRIDGE */ +/* CLKID_USB0_DDR_BRIDGE */ #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_UART2 68 diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index 7955d7c712f6..743c45b40361 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -14,6 +14,11 @@ #define CLKID_MPLL2 15 #define CLKID_SPI 34 #define CLKID_ETH 36 +#define CLKID_USB0 50 +#define CLKID_USB1 51 +#define CLKID_USB 55 +#define CLKID_USB1_DDR_BRIDGE 64 +#define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_B 95 #define CLKID_SD_EMMC_C 96 -- cgit v1.2.3 From dfdd7d4af6ebee027be7bf2636b2314937948da6 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 14 Sep 2016 12:06:05 +0200 Subject: clk: gxbb: expose i2c clocks I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet Acked-by: Stephen Boyd Signed-off-by: Kevin Hilman --- drivers/clk/meson/gxbb.h | 4 ++-- include/dt-bindings/clock/gxbb-clkc.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index 044fc44e9144..0252939ba58f 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -190,7 +190,7 @@ #define CLKID_PL301 19 #define CLKID_PERIPHS 20 #define CLKID_SPICC 21 -#define CLKID_I2C 22 +/* CLKID_I2C */ #define CLKID_SAR_ADC 23 #define CLKID_SMART_CARD 24 #define CLKID_RNG0 25 @@ -261,7 +261,7 @@ #define CLKID_AO_AHB_SRAM 90 #define CLKID_AO_AHB_BUS 91 #define CLKID_AO_IFACE 92 -#define CLKID_AO_I2C 93 +/* CLKID_AO_I2C */ /* CLKID_SD_EMMC_A */ /* CLKID_SD_EMMC_B */ /* CLKID_SD_EMMC_C */ diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index 743c45b40361..baade6f429d0 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -13,12 +13,14 @@ #define CLKID_CLK81 12 #define CLKID_MPLL2 15 #define CLKID_SPI 34 +#define CLKID_I2C 22 #define CLKID_ETH 36 #define CLKID_USB0 50 #define CLKID_USB1 51 #define CLKID_USB 55 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB0_DDR_BRIDGE 65 +#define CLKID_AO_I2C 93 #define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_B 95 #define CLKID_SD_EMMC_C 96 -- cgit v1.2.3