From 9be83448951a404a6fd5cf43ee0245a9bccc02c1 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 22 Feb 2017 10:59:55 +0800 Subject: clk: rockchip: add pll_wait_lock for pll_enable If pll is power down,when power up pll need wait pll lock. The reference documents section: PLL frequency change and lock check Signed-off-by: Elaine Zhang Signed-off-by: Heiko Stuebner --- drivers/clk/rockchip/clk-pll.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index eec51893a7e6..dd0433d4753e 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -269,6 +269,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw) writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), pll->reg_base + RK3036_PLLCON(1)); + rockchip_pll_wait_lock(pll); return 0; } @@ -501,6 +502,7 @@ static int rockchip_rk3066_pll_enable(struct clk_hw *hw) writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), pll->reg_base + RK3066_PLLCON(3)); + rockchip_pll_wait_lock(pll); return 0; } @@ -746,6 +748,7 @@ static int rockchip_rk3399_pll_enable(struct clk_hw *hw) writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), pll->reg_base + RK3399_PLLCON(3)); + rockchip_rk3399_pll_wait_lock(pll); return 0; } -- cgit v1.2.3