From e3a2b0d97568b3db2117580fe59183ebddc8316e Mon Sep 17 00:00:00 2001 From: R Veera Kumar Date: Mon, 6 Apr 2020 21:11:24 +0530 Subject: staging: rtl8723bs: Correct misspelt symbolic names Correct misspelt symbolic names. Misspelling found using checkpatch.pl. Signed-off-by: R Veera Kumar Link: https://lore.kernel.org/r/abe807c11a5fda479ed6079a11d528989fe7b63e.1586187304.git.vkor@vkten.in Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8723bs/hal/hal_com_phycfg.c | 8 ++++---- drivers/staging/rtl8723bs/include/hal_data.h | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/staging') diff --git a/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c b/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c index 767e2a784f78..10250642d30a 100644 --- a/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c +++ b/drivers/staging/rtl8723bs/hal/hal_com_phycfg.c @@ -1816,7 +1816,7 @@ static void phy_CrossReferenceHTAndVHTTxPowerLimit(struct adapter *padapter) s8 tempPwrLmt = 0; for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { - for (bw = 0; bw < MAX_5G_BANDWITH_NUM; ++bw) { + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { for (channel = 0; channel < CHANNEL_MAX_NUMBER_5G; ++channel) { for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) { tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][ODM_RF_PATH_A]; @@ -1877,7 +1877,7 @@ void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter) phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter); for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { - for (bw = 0; bw < MAX_2_4G_BANDWITH_NUM; ++bw) { + for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) { for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) { tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A]; @@ -1920,7 +1920,7 @@ void PHY_InitTxPowerLimit(struct adapter *Adapter) /* DBG_871X("=====> PHY_InitTxPowerLimit()!\n"); */ for (i = 0; i < MAX_REGULATION_NUM; ++i) { - for (j = 0; j < MAX_2_4G_BANDWITH_NUM; ++j) + for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m) for (l = 0; l < MAX_RF_PATH_NUM; ++l) @@ -1928,7 +1928,7 @@ void PHY_InitTxPowerLimit(struct adapter *Adapter) } for (i = 0; i < MAX_REGULATION_NUM; ++i) { - for (j = 0; j < MAX_5G_BANDWITH_NUM; ++j) + for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) for (m = 0; m < CHANNEL_MAX_NUMBER_5G; ++m) for (l = 0; l < MAX_RF_PATH_NUM; ++l) diff --git a/drivers/staging/rtl8723bs/include/hal_data.h b/drivers/staging/rtl8723bs/include/hal_data.h index e5e667df6154..fa5d70016f05 100644 --- a/drivers/staging/rtl8723bs/include/hal_data.h +++ b/drivers/staging/rtl8723bs/include/hal_data.h @@ -56,9 +56,9 @@ enum RT_AMPDU_BURST { /* Tx Power Limit Table Size */ #define MAX_REGULATION_NUM 4 #define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 -#define MAX_2_4G_BANDWITH_NUM 4 +#define MAX_2_4G_BANDWIDTH_NUM 4 #define MAX_RATE_SECTION_NUM 10 -#define MAX_5G_BANDWITH_NUM 4 +#define MAX_5G_BANDWIDTH_NUM 4 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 /* OFDM:1, HT:4, VHT:4 */ @@ -280,14 +280,14 @@ struct hal_com_data { /* Power Limit Table for 2.4G */ s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] - [MAX_2_4G_BANDWITH_NUM] + [MAX_2_4G_BANDWIDTH_NUM] [MAX_RATE_SECTION_NUM] [CHANNEL_MAX_NUMBER_2G] [MAX_RF_PATH_NUM]; /* Power Limit Table for 5G */ s8 TxPwrLimit_5G[MAX_REGULATION_NUM] - [MAX_5G_BANDWITH_NUM] + [MAX_5G_BANDWIDTH_NUM] [MAX_RATE_SECTION_NUM] [CHANNEL_MAX_NUMBER_5G] [MAX_RF_PATH_NUM]; -- cgit v1.2.3