From ece9ef3b60cbc36237138af456b236d3d1d9b771 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 4 Feb 2020 11:12:04 -0800 Subject: spi: spi-geni-qcom: Let firmware specify irq trigger flags We don't need to force IRQF_TRIGGER_HIGH here as the DT or ACPI tables should take care of this for us. Just use 0 instead so that we use the flags from the firmware. Cc: Girish Mahadevan Cc: Dilip Kota Cc: Alok Chauhan Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20200204191206.97036-2-swboyd@chromium.org Signed-off-by: Mark Brown --- drivers/spi/spi-geni-qcom.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 6f3d64a1a2b3..46e501fc87f3 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -585,8 +585,7 @@ static int spi_geni_probe(struct platform_device *pdev) if (ret) goto spi_geni_probe_runtime_disable; - ret = request_irq(mas->irq, geni_spi_isr, - IRQF_TRIGGER_HIGH, "spi_geni", spi); + ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(&pdev->dev), spi); if (ret) goto spi_geni_probe_runtime_disable; -- cgit v1.2.3 From ea1e5b3354b1610ac16a780535fbdabfda9e6912 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 4 Feb 2020 11:12:05 -0800 Subject: spi: spi-geni-qcom: Grow a dev pointer to simplify code Some lines are long here. Use a struct dev pointer to shorten lines and simplify code. The clk_get() call can fail because of EPROBE_DEFER problems too, so just remove the error print message because it isn't useful. Cc: Girish Mahadevan Cc: Dilip Kota Cc: Alok Chauhan Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20200204191206.97036-3-swboyd@chromium.org Signed-off-by: Mark Brown --- drivers/spi/spi-geni-qcom.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 46e501fc87f3..f0ca7f5ae714 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -536,6 +536,7 @@ static int spi_geni_probe(struct platform_device *pdev) struct spi_geni_master *mas; void __iomem *base; struct clk *clk; + struct device *dev = &pdev->dev; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -545,28 +546,25 @@ static int spi_geni_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - clk = devm_clk_get(&pdev->dev, "se"); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "Err getting SE Core clk %ld\n", - PTR_ERR(clk)); + clk = devm_clk_get(dev, "se"); + if (IS_ERR(clk)) return PTR_ERR(clk); - } - spi = spi_alloc_master(&pdev->dev, sizeof(*mas)); + spi = spi_alloc_master(dev, sizeof(*mas)); if (!spi) return -ENOMEM; platform_set_drvdata(pdev, spi); mas = spi_master_get_devdata(spi); mas->irq = irq; - mas->dev = &pdev->dev; - mas->se.dev = &pdev->dev; - mas->se.wrapper = dev_get_drvdata(pdev->dev.parent); + mas->dev = dev; + mas->se.dev = dev; + mas->se.wrapper = dev_get_drvdata(dev->parent); mas->se.base = base; mas->se.clk = clk; spi->bus_num = -1; - spi->dev.of_node = pdev->dev.of_node; + spi->dev.of_node = dev->of_node; spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); spi->num_chipselect = 4; @@ -579,13 +577,13 @@ static int spi_geni_probe(struct platform_device *pdev) init_completion(&mas->xfer_done); spin_lock_init(&mas->lock); - pm_runtime_enable(&pdev->dev); + pm_runtime_enable(dev); ret = spi_geni_init(mas); if (ret) goto spi_geni_probe_runtime_disable; - ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(&pdev->dev), spi); + ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi); if (ret) goto spi_geni_probe_runtime_disable; @@ -597,7 +595,7 @@ static int spi_geni_probe(struct platform_device *pdev) spi_geni_probe_free_irq: free_irq(mas->irq, spi); spi_geni_probe_runtime_disable: - pm_runtime_disable(&pdev->dev); + pm_runtime_disable(dev); spi_master_put(spi); return ret; } -- cgit v1.2.3 From 8196f7bcc2adf21f83d82691d537fcef7abaa1c7 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Mon, 3 Feb 2020 14:50:47 +0100 Subject: spi: stm32-qspi: defer probe for reset controller Changes stm32 QSPI driver to defer its probe operation when a reset controller device have not yet probed but is registered in the system. Signed-off-by: Etienne Carriere Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20200203135048.1299-2-patrice.chotard@st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-qspi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 4ef569b47aa6..13bb64bf4c8f 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -615,7 +615,11 @@ static int stm32_qspi_probe(struct platform_device *pdev) } rstc = devm_reset_control_get_exclusive(dev, NULL); - if (!IS_ERR(rstc)) { + if (IS_ERR(rstc)) { + ret = PTR_ERR(rstc); + if (ret == -EPROBE_DEFER) + goto err; + } else { reset_control_assert(rstc); udelay(2); reset_control_deassert(rstc); -- cgit v1.2.3 From 875014cb79ea4251e8800994640be1a8012b4133 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 4 Feb 2020 11:12:06 -0800 Subject: spi: spi-geni-qcom: Drop of.h include This driver doesn't call any DT functions like of_get_property(). Remove the of.h include as it isn't used. Cc: Girish Mahadevan Cc: Dilip Kota Cc: Alok Chauhan Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20200204191206.97036-4-swboyd@chromium.org Signed-off-by: Mark Brown --- drivers/spi/spi-geni-qcom.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index f0ca7f5ae714..c3972424af71 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.3 From 4a08d6c8662472121b0ddc29180ab3c94c34f586 Mon Sep 17 00:00:00 2001 From: Lionel Debieve Date: Mon, 3 Feb 2020 14:50:48 +0100 Subject: spi: stm32-qspi: properly manage probe errors Fix resource release issues when driver probe operation fails. Signed-off-by: Lionel Debieve Signed-off-by: Etienne Carriere Signed-off-by: Patrice Chotard Link: https://lore.kernel.org/r/20200203135048.1299-3-patrice.chotard@st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32-qspi.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index 13bb64bf4c8f..d066f5144c3e 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -565,7 +565,7 @@ static int stm32_qspi_probe(struct platform_device *pdev) qspi->io_base = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->io_base)) { ret = PTR_ERR(qspi->io_base); - goto err; + goto err_master_put; } qspi->phys_base = res->start; @@ -574,24 +574,26 @@ static int stm32_qspi_probe(struct platform_device *pdev) qspi->mm_base = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->mm_base)) { ret = PTR_ERR(qspi->mm_base); - goto err; + goto err_master_put; } qspi->mm_size = resource_size(res); if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) { ret = -EINVAL; - goto err; + goto err_master_put; } irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; + if (irq < 0) { + ret = irq; + goto err_master_put; + } ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, dev_name(dev), qspi); if (ret) { dev_err(dev, "failed to request irq\n"); - goto err; + goto err_master_put; } init_completion(&qspi->data_completion); @@ -599,26 +601,26 @@ static int stm32_qspi_probe(struct platform_device *pdev) qspi->clk = devm_clk_get(dev, NULL); if (IS_ERR(qspi->clk)) { ret = PTR_ERR(qspi->clk); - goto err; + goto err_master_put; } qspi->clk_rate = clk_get_rate(qspi->clk); if (!qspi->clk_rate) { ret = -EINVAL; - goto err; + goto err_master_put; } ret = clk_prepare_enable(qspi->clk); if (ret) { dev_err(dev, "can not enable the clock\n"); - goto err; + goto err_master_put; } rstc = devm_reset_control_get_exclusive(dev, NULL); if (IS_ERR(rstc)) { ret = PTR_ERR(rstc); if (ret == -EPROBE_DEFER) - goto err; + goto err_qspi_release; } else { reset_control_assert(rstc); udelay(2); @@ -629,7 +631,7 @@ static int stm32_qspi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, qspi); ret = stm32_qspi_dma_setup(qspi); if (ret) - goto err; + goto err_qspi_release; mutex_init(&qspi->lock); @@ -645,8 +647,9 @@ static int stm32_qspi_probe(struct platform_device *pdev) if (!ret) return 0; -err: +err_qspi_release: stm32_qspi_release(qspi); +err_master_put: spi_master_put(qspi->ctrl); return ret; -- cgit v1.2.3 From 047980c582af665e1581e60ebf3e57977e621c23 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Mon, 10 Feb 2020 11:41:51 +0800 Subject: spi: add driver for ar934x spi controller This patch adds driver for SPI controller found in Qualcomm Atheros AR934x/QCA95xx SoCs. This controller is a superset of the already supported qca,ar7100-spi. Besides the bit-bang mode in spi-ath79.c, this new controller added a new "shift register" mode, allowing faster spi operations. Signed-off-by: Chuanhong Guo Link: https://lore.kernel.org/r/20200210034152.49063-2-gch981213@gmail.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 7 ++ drivers/spi/Makefile | 1 + drivers/spi/spi-ar934x.c | 235 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 243 insertions(+) create mode 100644 drivers/spi/spi-ar934x.c (limited to 'drivers/spi') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d6ed0c355954..0434614d8201 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -62,6 +62,13 @@ config SPI_ALTERA help This is the driver for the Altera SPI Controller. +config SPI_AR934X + tristate "Qualcomm Atheros AR934X/QCA95XX SPI controller driver" + depends on ATH79 || COMPILE_TEST + help + This enables support for the SPI controller present on the + Qualcomm Atheros AR934X/QCA95XX SoCs. + config SPI_ATH79 tristate "Atheros AR71XX/AR724X/AR913X SPI controller driver" depends on ATH79 || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 9b65ec5afc5e..9892bdfab15e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o # SPI master controller drivers (bus) obj-$(CONFIG_SPI_ALTERA) += spi-altera.o +obj-$(CONFIG_SPI_AR934X) += spi-ar934x.o obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o diff --git a/drivers/spi/spi-ar934x.c b/drivers/spi/spi-ar934x.c new file mode 100644 index 000000000000..d08dec09d423 --- /dev/null +++ b/drivers/spi/spi-ar934x.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// SPI controller driver for Qualcomm Atheros AR934x/QCA95xx SoCs +// +// Copyright (C) 2020 Chuanhong Guo +// +// Based on spi-mt7621.c: +// Copyright (C) 2011 Sergiy +// Copyright (C) 2011-2013 Gabor Juhos +// Copyright (C) 2014-2015 Felix Fietkau + +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "spi-ar934x" + +#define AR934X_SPI_REG_FS 0x00 +#define AR934X_SPI_ENABLE BIT(0) + +#define AR934X_SPI_REG_IOC 0x08 +#define AR934X_SPI_IOC_INITVAL 0x70000 + +#define AR934X_SPI_REG_CTRL 0x04 +#define AR934X_SPI_CLK_MASK GENMASK(5, 0) + +#define AR934X_SPI_DATAOUT 0x10 + +#define AR934X_SPI_REG_SHIFT_CTRL 0x14 +#define AR934X_SPI_SHIFT_EN BIT(31) +#define AR934X_SPI_SHIFT_CS(n) BIT(28 + (n)) +#define AR934X_SPI_SHIFT_TERM 26 +#define AR934X_SPI_SHIFT_VAL(cs, term, count) \ + (AR934X_SPI_SHIFT_EN | AR934X_SPI_SHIFT_CS(cs) | \ + (term) << AR934X_SPI_SHIFT_TERM | (count)) + +#define AR934X_SPI_DATAIN 0x18 + +struct ar934x_spi { + struct spi_controller *ctlr; + void __iomem *base; + struct clk *clk; + unsigned int clk_freq; +}; + +static inline int ar934x_spi_clk_div(struct ar934x_spi *sp, unsigned int freq) +{ + int div = DIV_ROUND_UP(sp->clk_freq, freq * 2) - 1; + + if (div < 0) + return 0; + else if (div > AR934X_SPI_CLK_MASK) + return -EINVAL; + else + return div; +} + +static int ar934x_spi_setup(struct spi_device *spi) +{ + struct ar934x_spi *sp = spi_controller_get_devdata(spi->master); + + if ((spi->max_speed_hz == 0) || + (spi->max_speed_hz > (sp->clk_freq / 2))) { + spi->max_speed_hz = sp->clk_freq / 2; + } else if (spi->max_speed_hz < (sp->clk_freq / 128)) { + dev_err(&spi->dev, "spi clock is too low\n"); + return -EINVAL; + } + + return 0; +} + +static int ar934x_spi_transfer_one_message(struct spi_controller *master, + struct spi_message *m) +{ + struct ar934x_spi *sp = spi_controller_get_devdata(master); + struct spi_transfer *t = NULL; + struct spi_device *spi = m->spi; + unsigned long trx_done, trx_cur; + int stat = 0; + u8 term = 0; + int div, i; + u32 reg; + const u8 *tx_buf; + u8 *buf; + + m->actual_length = 0; + list_for_each_entry(t, &m->transfers, transfer_list) { + if (t->speed_hz) + div = ar934x_spi_clk_div(sp, t->speed_hz); + else + div = ar934x_spi_clk_div(sp, spi->max_speed_hz); + if (div < 0) { + stat = -EIO; + goto msg_done; + } + + reg = ioread32(sp->base + AR934X_SPI_REG_CTRL); + reg &= ~AR934X_SPI_CLK_MASK; + reg |= div; + iowrite32(reg, sp->base + AR934X_SPI_REG_CTRL); + iowrite32(0, sp->base + AR934X_SPI_DATAOUT); + + for (trx_done = 0; trx_done < t->len; trx_done += 4) { + trx_cur = t->len - trx_done; + if (trx_cur > 4) + trx_cur = 4; + else if (list_is_last(&t->transfer_list, &m->transfers)) + term = 1; + + if (t->tx_buf) { + tx_buf = t->tx_buf + trx_done; + reg = tx_buf[0]; + for (i = 1; i < trx_cur; i++) + reg = reg << 8 | tx_buf[i]; + iowrite32(reg, sp->base + AR934X_SPI_DATAOUT); + } + + reg = AR934X_SPI_SHIFT_VAL(spi->chip_select, term, + trx_cur * 8); + iowrite32(reg, sp->base + AR934X_SPI_REG_SHIFT_CTRL); + stat = readl_poll_timeout( + sp->base + AR934X_SPI_REG_SHIFT_CTRL, reg, + !(reg & AR934X_SPI_SHIFT_EN), 0, 5); + if (stat < 0) + goto msg_done; + + if (t->rx_buf) { + reg = ioread32(sp->base + AR934X_SPI_DATAIN); + buf = t->rx_buf + trx_done; + for (i = 0; i < trx_cur; i++) { + buf[trx_cur - i - 1] = reg & 0xff; + reg >>= 8; + } + } + } + m->actual_length += t->len; + } + +msg_done: + m->status = stat; + spi_finalize_current_message(master); + + return 0; +} + +static const struct of_device_id ar934x_spi_match[] = { + { .compatible = "qca,ar934x-spi" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ar934x_spi_match); + +static int ar934x_spi_probe(struct platform_device *pdev) +{ + struct spi_controller *ctlr; + struct ar934x_spi *sp; + void __iomem *base; + struct clk *clk; + int ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed to get clock\n"); + return PTR_ERR(clk); + } + + ret = clk_prepare_enable(clk); + if (ret) + return ret; + + ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (!ctlr) { + dev_info(&pdev->dev, "failed to allocate spi controller\n"); + return -ENOMEM; + } + + /* disable flash mapping and expose spi controller registers */ + iowrite32(AR934X_SPI_ENABLE, base + AR934X_SPI_REG_FS); + /* restore pins to default state: CSn=1 DO=CLK=0 */ + iowrite32(AR934X_SPI_IOC_INITVAL, base + AR934X_SPI_REG_IOC); + + ctlr->mode_bits = SPI_LSB_FIRST; + ctlr->setup = ar934x_spi_setup; + ctlr->transfer_one_message = ar934x_spi_transfer_one_message; + ctlr->bits_per_word_mask = SPI_BPW_MASK(8); + ctlr->dev.of_node = pdev->dev.of_node; + ctlr->num_chipselect = 3; + + dev_set_drvdata(&pdev->dev, ctlr); + + sp = spi_controller_get_devdata(ctlr); + sp->base = base; + sp->clk = clk; + sp->clk_freq = clk_get_rate(clk); + sp->ctlr = ctlr; + + return devm_spi_register_controller(&pdev->dev, ctlr); +} + +static int ar934x_spi_remove(struct platform_device *pdev) +{ + struct spi_controller *ctlr; + struct ar934x_spi *sp; + + ctlr = dev_get_drvdata(&pdev->dev); + sp = spi_controller_get_devdata(ctlr); + + clk_disable_unprepare(sp->clk); + + return 0; +} + +static struct platform_driver ar934x_spi_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = ar934x_spi_match, + }, + .probe = ar934x_spi_probe, + .remove = ar934x_spi_remove, +}; + +module_platform_driver(ar934x_spi_driver); + +MODULE_DESCRIPTION("SPI controller driver for Qualcomm Atheros AR934x/QCA95xx"); +MODULE_AUTHOR("Chuanhong Guo "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); -- cgit v1.2.3 From e9e40543ad5b38b848879768359fd13650529961 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Tue, 4 Feb 2020 16:28:38 +1300 Subject: spi: Add generic SPI multiplexer Add a SPI device driver that sits in-band and provides a SPI controller which supports chip selects via a mux-control. This enables extra SPI devices to be connected with limited native chip selects. Signed-off-by: Chris Packham Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200204032838.20739-3-chris.packham@alliedtelesis.co.nz Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 11 +++ drivers/spi/Makefile | 1 + drivers/spi/spi-mux.c | 187 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 199 insertions(+) create mode 100644 drivers/spi/spi-mux.c (limited to 'drivers/spi') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 0434614d8201..887fefe87fd5 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -897,6 +897,17 @@ config SPI_ZYNQMP_GQSPI # Add new SPI master controllers in alphabetical order above this line # +comment "SPI Multiplexer support" + +config SPI_MUX + tristate "SPI multiplexer support" + select MULTIPLEXER + help + This adds support for SPI multiplexers. Each SPI mux will be + accessible as a SPI controller, the devices behind the mux will appear + to be chip selects on this controller. It is still necessary to + select one or more specific mux-controller drivers. + # # There are lots of SPI device types, with sensors and memory # being probably the most widely used ones. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 9892bdfab15e..74db1f2c3299 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -9,6 +9,7 @@ ccflags-$(CONFIG_SPI_DEBUG) := -DDEBUG # config declarations into driver model code obj-$(CONFIG_SPI_MASTER) += spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o +obj-$(CONFIG_SPI_MUX) += spi-mux.o obj-$(CONFIG_SPI_SPIDEV) += spidev.o obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o diff --git a/drivers/spi/spi-mux.c b/drivers/spi/spi-mux.c new file mode 100644 index 000000000000..4f94c9127fc1 --- /dev/null +++ b/drivers/spi/spi-mux.c @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// General Purpose SPI multiplexer + +#include +#include +#include +#include +#include +#include + +#define SPI_MUX_NO_CS ((unsigned int)-1) + +/** + * DOC: Driver description + * + * This driver supports a MUX on an SPI bus. This can be useful when you need + * more chip selects than the hardware peripherals support, or than are + * available in a particular board setup. + * + * The driver will create an additional SPI controller. Devices added under the + * mux will be handled as 'chip selects' on this controller. + */ + +/** + * struct spi_mux_priv - the basic spi_mux structure + * @spi: pointer to the device struct attached to the parent + * spi controller + * @current_cs: The current chip select set in the mux + * @child_msg_complete: The mux replaces the complete callback in the child's + * message to its own callback; this field is used by the + * driver to store the child's callback during a transfer + * @child_msg_context: Used to store the child's context to the callback + * @child_msg_dev: Used to store the spi_device pointer to the child + * @mux: mux_control structure used to provide chip selects for + * downstream spi devices + */ +struct spi_mux_priv { + struct spi_device *spi; + unsigned int current_cs; + + void (*child_msg_complete)(void *context); + void *child_msg_context; + struct spi_device *child_msg_dev; + struct mux_control *mux; +}; + +/* should not get called when the parent controller is doing a transfer */ +static int spi_mux_select(struct spi_device *spi) +{ + struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller); + int ret; + + if (priv->current_cs == spi->chip_select) + return 0; + + dev_dbg(&priv->spi->dev, "setting up the mux for cs %d\n", + spi->chip_select); + + /* copy the child device's settings except for the cs */ + priv->spi->max_speed_hz = spi->max_speed_hz; + priv->spi->mode = spi->mode; + priv->spi->bits_per_word = spi->bits_per_word; + + ret = mux_control_select(priv->mux, spi->chip_select); + if (ret) + return ret; + + priv->current_cs = spi->chip_select; + + return 0; +} + +static int spi_mux_setup(struct spi_device *spi) +{ + struct spi_mux_priv *priv = spi_controller_get_devdata(spi->controller); + + /* + * can be called multiple times, won't do a valid setup now but we will + * change the settings when we do a transfer (necessary because we + * can't predict from which device it will be anyway) + */ + return spi_setup(priv->spi); +} + +static void spi_mux_complete_cb(void *context) +{ + struct spi_mux_priv *priv = (struct spi_mux_priv *)context; + struct spi_controller *ctlr = spi_get_drvdata(priv->spi); + struct spi_message *m = ctlr->cur_msg; + + m->complete = priv->child_msg_complete; + m->context = priv->child_msg_context; + m->spi = priv->child_msg_dev; + spi_finalize_current_message(ctlr); + mux_control_deselect(priv->mux); +} + +static int spi_mux_transfer_one_message(struct spi_controller *ctlr, + struct spi_message *m) +{ + struct spi_mux_priv *priv = spi_controller_get_devdata(ctlr); + struct spi_device *spi = m->spi; + int ret; + + ret = spi_mux_select(spi); + if (ret) + return ret; + + /* + * Replace the complete callback, context and spi_device with our own + * pointers. Save originals + */ + priv->child_msg_complete = m->complete; + priv->child_msg_context = m->context; + priv->child_msg_dev = m->spi; + + m->complete = spi_mux_complete_cb; + m->context = priv; + m->spi = priv->spi; + + /* do the transfer */ + return spi_async(priv->spi, m); +} + +static int spi_mux_probe(struct spi_device *spi) +{ + struct spi_controller *ctlr; + struct spi_mux_priv *priv; + int ret; + + ctlr = spi_alloc_master(&spi->dev, sizeof(*priv)); + if (!ctlr) + return -ENOMEM; + + spi_set_drvdata(spi, ctlr); + priv = spi_controller_get_devdata(ctlr); + priv->spi = spi; + + priv->mux = devm_mux_control_get(&spi->dev, NULL); + if (IS_ERR(priv->mux)) { + ret = PTR_ERR(priv->mux); + if (ret != -EPROBE_DEFER) + dev_err(&spi->dev, "failed to get control-mux\n"); + goto err_put_ctlr; + } + + priv->current_cs = SPI_MUX_NO_CS; + + /* supported modes are the same as our parent's */ + ctlr->mode_bits = spi->controller->mode_bits; + ctlr->flags = spi->controller->flags; + ctlr->transfer_one_message = spi_mux_transfer_one_message; + ctlr->setup = spi_mux_setup; + ctlr->num_chipselect = mux_control_states(priv->mux); + ctlr->bus_num = -1; + ctlr->dev.of_node = spi->dev.of_node; + + ret = devm_spi_register_controller(&spi->dev, ctlr); + if (ret) + goto err_put_ctlr; + + return 0; + +err_put_ctlr: + spi_controller_put(ctlr); + + return ret; +} + +static const struct of_device_id spi_mux_of_match[] = { + { .compatible = "spi-mux" }, + { } +}; + +static struct spi_driver spi_mux_driver = { + .probe = spi_mux_probe, + .driver = { + .name = "spi-mux", + .of_match_table = spi_mux_of_match, + }, +}; + +module_spi_driver(spi_mux_driver); + +MODULE_DESCRIPTION("SPI multiplexer"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 32a9d0545c5da9717395264de9b8e004e4b90893 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Sun, 16 Feb 2020 21:40:17 +0000 Subject: spi: spi-mem: Fix typo, s/fallback/falls back "Fallback" in one word is a noun. "Fall back" is two separate words, a verb and an adverb. Use the latter. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200216214012.1106658-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown --- drivers/spi/spi-mem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index e5a46f0eb93b..3c46747bacb1 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -487,7 +487,7 @@ static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc, * This function is creating a direct mapping descriptor which can then be used * to access the memory using spi_mem_dirmap_read() or spi_mem_dirmap_write(). * If the SPI controller driver does not support direct mapping, this function - * fallback to an implementation using spi_mem_exec_op(), so that the caller + * falls back to an implementation using spi_mem_exec_op(), so that the caller * doesn't have to bother implementing a fallback on his own. * * Return: a valid pointer in case of success, and ERR_PTR() otherwise. -- cgit v1.2.3 From cd982e6c44a7265e1c7e92de4f696c3b3b376e93 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Feb 2020 11:58:08 +0100 Subject: spi: rspi: Factor out handling of common mode bits Basic SPI features like clock phase/polarity and loopback mode are common to all RSPI variants. Factor them out to reduce duplication. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200218105810.902-2-geert+renesas@glider.be Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 85575d45901c..7a1e6d524f34 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -239,7 +239,7 @@ struct spi_ops { int (*set_config_register)(struct rspi_data *rspi, int access_size); int (*transfer_one)(struct spi_controller *ctlr, struct spi_device *spi, struct spi_transfer *xfer); - u16 mode_bits; + u16 extra_mode_bits; u16 flags; u16 fifo_size; u8 num_hw_ss; @@ -1122,7 +1122,6 @@ static int rspi_remove(struct platform_device *pdev) static const struct spi_ops rspi_ops = { .set_config_register = rspi_set_config_register, .transfer_one = rspi_transfer_one, - .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, .flags = SPI_CONTROLLER_MUST_TX, .fifo_size = 8, .num_hw_ss = 2, @@ -1131,7 +1130,6 @@ static const struct spi_ops rspi_ops = { static const struct spi_ops rspi_rz_ops = { .set_config_register = rspi_rz_set_config_register, .transfer_one = rspi_rz_transfer_one, - .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, .fifo_size = 8, /* 8 for TX, 32 for RX */ .num_hw_ss = 1, @@ -1140,8 +1138,7 @@ static const struct spi_ops rspi_rz_ops = { static const struct spi_ops qspi_ops = { .set_config_register = qspi_set_config_register, .transfer_one = qspi_transfer_one, - .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | - SPI_TX_DUAL | SPI_TX_QUAD | + .extra_mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD, .flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX, .fifo_size = 32, @@ -1258,7 +1255,7 @@ static int rspi_probe(struct platform_device *pdev) ctlr->transfer_one = ops->transfer_one; ctlr->prepare_message = rspi_prepare_message; ctlr->unprepare_message = rspi_unprepare_message; - ctlr->mode_bits = ops->mode_bits; + ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | ops->extra_mode_bits; ctlr->flags = ops->flags; ctlr->dev.of_node = pdev->dev.of_node; ctlr->use_gpio_descriptors = true; -- cgit v1.2.3 From c046f8fd83a902866ba3b122e9f57ca1c7de898c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 18 Feb 2020 11:58:09 +0100 Subject: spi: rspi: Add support for LSB-first word order All RSPI variants support selecting the word order. Advertize support for LSB-first order, and act upon the flag being set. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200218105810.902-3-geert+renesas@glider.be Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index 7a1e6d524f34..aef05f2ac749 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -933,6 +933,8 @@ static int rspi_prepare_message(struct spi_controller *ctlr, rspi->spcmd |= SPCMD_CPOL; if (spi->mode & SPI_CPHA) rspi->spcmd |= SPCMD_CPHA; + if (spi->mode & SPI_LSB_FIRST) + rspi->spcmd |= SPCMD_LSBF; /* Configure slave signal to assert */ rspi->spcmd |= SPCMD_SSLA(spi->cs_gpiod ? rspi->ctlr->unused_native_cs @@ -1255,7 +1257,8 @@ static int rspi_probe(struct platform_device *pdev) ctlr->transfer_one = ops->transfer_one; ctlr->prepare_message = rspi_prepare_message; ctlr->unprepare_message = rspi_unprepare_message; - ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | ops->extra_mode_bits; + ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_LOOP | + ops->extra_mode_bits; ctlr->flags = ops->flags; ctlr->dev.of_node = pdev->dev.of_node; ctlr->use_gpio_descriptors = true; -- cgit v1.2.3 From 14af1df3b03309f6204661e12c40cdf71bc8f773 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 24 Feb 2020 17:45:55 +0200 Subject: spi: pxa2xx: Return error codes from pxa2xx_spi_init_pdata() For better understanding what's going on on error path, return distinguished error codes instead of NULL pointer. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200224154556.11627-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-pxa2xx.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 4c7a71f0fb3e..934bfe2c8a90 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1548,18 +1548,18 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev) else if (pcidev_id) type = (enum pxa_ssp_type)pcidev_id->driver_data; else - return NULL; + return ERR_PTR(-EINVAL); pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) - return NULL; + return ERR_PTR(-ENOMEM); ssp = &pdata->ssp; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(ssp->mmio_base)) - return NULL; + return ERR_CAST(ssp->mmio_base); ssp->phys_base = res->start; @@ -1573,11 +1573,11 @@ pxa2xx_spi_init_pdata(struct platform_device *pdev) ssp->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(ssp->clk)) - return NULL; + return ERR_CAST(ssp->clk); ssp->irq = platform_get_irq(pdev, 0); if (ssp->irq < 0) - return NULL; + return ERR_PTR(ssp->irq); ssp->type = type; ssp->dev = &pdev->dev; @@ -1634,9 +1634,9 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) platform_info = dev_get_platdata(dev); if (!platform_info) { platform_info = pxa2xx_spi_init_pdata(pdev); - if (!platform_info) { + if (IS_ERR(platform_info)) { dev_err(&pdev->dev, "missing platform data\n"); - return -ENODEV; + return PTR_ERR(platform_info); } } -- cgit v1.2.3 From 3d24b2a470466aa901ba8354468fc1899259fd84 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 24 Feb 2020 17:45:56 +0200 Subject: spi: pxa2xx: drv_data can't be NULL in ->remove() There is no need for drv_data check against NULL, since it won't happen. Remove useless check. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200224154556.11627-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-pxa2xx.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 934bfe2c8a90..8e8e18023ded 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1884,11 +1884,7 @@ out_error_controller_alloc: static int pxa2xx_spi_remove(struct platform_device *pdev) { struct driver_data *drv_data = platform_get_drvdata(pdev); - struct ssp_device *ssp; - - if (!drv_data) - return 0; - ssp = drv_data->ssp; + struct ssp_device *ssp = drv_data->ssp; pm_runtime_get_sync(&pdev->dev); -- cgit v1.2.3 From ea23578611dce2eeaf31dcfe12cd7130cf3d1411 Mon Sep 17 00:00:00 2001 From: John Garry Date: Fri, 28 Feb 2020 23:18:49 +0800 Subject: spi: Allow SPI controller override device buswidth Currently ACPI firmware description for a SPI device does not have any method to describe the data buswidth on the board. So even through the controller and device may support higher modes than standard SPI, it cannot be assumed that the board does - as such, that device is limited to standard SPI in such a circumstance. As a workaround, allow the controller driver supply buswidth override bits, which are used inform the core code that the controller driver knows the buswidth supported on that board for that device. A host controller driver might know this info from DMI tables, for example. Signed-off-by: John Garry Link: https://lore.kernel.org/r/1582903131-160033-2-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown --- drivers/spi/spi.c | 4 +++- include/linux/spi/spi.h | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 38b4c78df506..292f26807b41 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -510,6 +510,7 @@ struct spi_device *spi_alloc_device(struct spi_controller *ctlr) spi->dev.bus = &spi_bus_type; spi->dev.release = spidev_release; spi->cs_gpio = -ENOENT; + spi->mode = ctlr->buswidth_override_bits; spin_lock_init(&spi->statistics.lock); @@ -2181,9 +2182,10 @@ static acpi_status acpi_register_spi_device(struct spi_controller *ctlr, return AE_NO_MEMORY; } + ACPI_COMPANION_SET(&spi->dev, adev); spi->max_speed_hz = lookup.max_speed_hz; - spi->mode = lookup.mode; + spi->mode |= lookup.mode; spi->irq = lookup.irq; spi->bits_per_word = lookup.bits_per_word; spi->chip_select = lookup.chip_select; diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 6d16ba01ff5a..600e3793303e 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -481,6 +481,9 @@ struct spi_controller { /* spi_device.mode flags understood by this controller driver */ u32 mode_bits; + /* spi_device.mode flags override flags for this controller */ + u32 buswidth_override_bits; + /* bitmask of supported bits_per_word for transfers */ u32 bits_per_word_mask; #define SPI_BPW_MASK(bits) BIT((bits) - 1) -- cgit v1.2.3 From 8fe21d6b347247227c349c9b2f7c462fae362af4 Mon Sep 17 00:00:00 2001 From: John Garry Date: Fri, 28 Feb 2020 23:18:50 +0800 Subject: spi: HiSilicon v3xx: Properly set CMD_CONFIG for Dual/Quad modes The CMD_CONFIG register memory interface type field is not set configured for Dual and Quad modes, so set appropriately. This was not detected previously as we only ever operated in standard SPI mode. Signed-off-by: John Garry Link: https://lore.kernel.org/r/1582903131-160033-3-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown --- drivers/spi/spi-hisi-sfc-v3xx.c | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c index 4cf8fc80a7b7..45d906110ed1 100644 --- a/drivers/spi/spi-hisi-sfc-v3xx.c +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -17,6 +17,12 @@ #define HISI_SFC_V3XX_VERSION (0x1f8) #define HISI_SFC_V3XX_CMD_CFG (0x300) +#define HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT (1 << 17) +#define HISI_SFC_V3XX_CMD_CFG_DUAL_IO (2 << 17) +#define HISI_SFC_V3XX_CMD_CFG_FULL_DIO (3 << 17) +#define HISI_SFC_V3XX_CMD_CFG_QUAD_IN_QUAD_OUT (5 << 17) +#define HISI_SFC_V3XX_CMD_CFG_QUAD_IO (6 << 17) +#define HISI_SFC_V3XX_CMD_CFG_FULL_QIO (7 << 17) #define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9 #define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8) #define HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK BIT(7) @@ -161,6 +167,43 @@ static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host, if (op->addr.nbytes) config |= HISI_SFC_V3XX_CMD_CFG_ADDR_EN_MSK; + switch (op->data.buswidth) { + case 0 ... 1: + break; + case 2: + if (op->addr.buswidth <= 1) { + config |= HISI_SFC_V3XX_CMD_CFG_DUAL_IN_DUAL_OUT; + } else if (op->addr.buswidth == 2) { + if (op->cmd.buswidth <= 1) { + config |= HISI_SFC_V3XX_CMD_CFG_DUAL_IO; + } else if (op->cmd.buswidth == 2) { + config |= HISI_SFC_V3XX_CMD_CFG_FULL_DIO; + } else { + return -EIO; + } + } else { + return -EIO; + } + break; + case 4: + if (op->addr.buswidth <= 1) { + config |= HISI_SFC_V3XX_CMD_CFG_QUAD_IN_QUAD_OUT; + } else if (op->addr.buswidth == 4) { + if (op->cmd.buswidth <= 1) { + config |= HISI_SFC_V3XX_CMD_CFG_QUAD_IO; + } else if (op->cmd.buswidth == 4) { + config |= HISI_SFC_V3XX_CMD_CFG_FULL_QIO; + } else { + return -EIO; + } + } else { + return -EIO; + } + break; + default: + return -EOPNOTSUPP; + } + if (op->data.dir != SPI_MEM_NO_DATA) { config |= (len - 1) << HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF; config |= HISI_SFC_V3XX_CMD_CFG_DATA_EN_MSK; -- cgit v1.2.3 From 34e608b023e96f51b31274435b49c8ae61e2389f Mon Sep 17 00:00:00 2001 From: John Garry Date: Fri, 28 Feb 2020 23:18:51 +0800 Subject: spi: HiSilicon v3xx: Use DMI quirk to set controller buswidth override bits The Huawei D06 board (and variants) can support Quad mode of operation. Since we have no current method in ACPI SPI bus device resource description to describe this information, use DMI to detect the board, and set the controller buswidth override bits. Signed-off-by: John Garry Link: https://lore.kernel.org/r/1582903131-160033-4-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown --- drivers/spi/spi-hisi-sfc-v3xx.c | 56 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c index 45d906110ed1..e3b57252d075 100644 --- a/drivers/spi/spi-hisi-sfc-v3xx.c +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -250,6 +251,44 @@ static const struct spi_controller_mem_ops hisi_sfc_v3xx_mem_ops = { .exec_op = hisi_sfc_v3xx_exec_op, }; +static int hisi_sfc_v3xx_buswidth_override_bits; + +/* + * ACPI FW does not allow us to currently set the device buswidth, so quirk it + * depending on the board. + */ +static int __init hisi_sfc_v3xx_dmi_quirk(const struct dmi_system_id *d) +{ + hisi_sfc_v3xx_buswidth_override_bits = SPI_RX_QUAD | SPI_TX_QUAD; + + return 0; +} + +static const struct dmi_system_id hisi_sfc_v3xx_dmi_quirk_table[] = { + { + .callback = hisi_sfc_v3xx_dmi_quirk, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Huawei"), + DMI_MATCH(DMI_PRODUCT_NAME, "D06"), + }, + }, + { + .callback = hisi_sfc_v3xx_dmi_quirk, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Huawei"), + DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 2280 V2"), + }, + }, + { + .callback = hisi_sfc_v3xx_dmi_quirk, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Huawei"), + DMI_MATCH(DMI_PRODUCT_NAME, "TaiShan 200 (Model 2280)"), + }, + }, + {} +}; + static int hisi_sfc_v3xx_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -265,6 +304,8 @@ static int hisi_sfc_v3xx_probe(struct platform_device *pdev) ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->buswidth_override_bits = hisi_sfc_v3xx_buswidth_override_bits; + host = spi_controller_get_devdata(ctlr); host->dev = dev; @@ -320,7 +361,20 @@ static struct platform_driver hisi_sfc_v3xx_spi_driver = { .probe = hisi_sfc_v3xx_probe, }; -module_platform_driver(hisi_sfc_v3xx_spi_driver); +static int __init hisi_sfc_v3xx_spi_init(void) +{ + dmi_check_system(hisi_sfc_v3xx_dmi_quirk_table); + + return platform_driver_register(&hisi_sfc_v3xx_spi_driver); +} + +static void __exit hisi_sfc_v3xx_spi_exit(void) +{ + platform_driver_unregister(&hisi_sfc_v3xx_spi_driver); +} + +module_init(hisi_sfc_v3xx_spi_init); +module_exit(hisi_sfc_v3xx_spi_exit); MODULE_LICENSE("GPL"); MODULE_AUTHOR("John Garry "); -- cgit v1.2.3 From c0e035ac56680e74b27fc218c07e70f4b9b8b7a5 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 28 Feb 2020 16:07:44 +0000 Subject: spi: spi-mem: Compute length only when needed When adjust_op_size is defined, len is never used. Move the len computation where it's actually used. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200228160735.1565047-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown --- drivers/spi/spi-mem.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 3c46747bacb1..adaa0c49f966 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -418,12 +418,13 @@ int spi_mem_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) struct spi_controller *ctlr = mem->spi->controller; size_t len; - len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; - if (ctlr->mem_ops && ctlr->mem_ops->adjust_op_size) return ctlr->mem_ops->adjust_op_size(mem, op); if (!ctlr->mem_ops || !ctlr->mem_ops->exec_op) { + len = sizeof(op->cmd.opcode) + op->addr.nbytes + + op->dummy.nbytes; + if (len > spi_max_transfer_size(mem->spi)) return -EINVAL; -- cgit v1.2.3 From 41c9884170c54013edd2481978cae917f94d40b4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 27 Feb 2020 18:25:56 +0200 Subject: spi: pxa2xx: Introduce is_mmp2_ssp() helper Introduce is_mmp2_ssp() helper to be consistent with the rest helper function to distinguish SSP type. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200227162556.3152-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown --- drivers/spi/spi-pxa2xx.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 8e8e18023ded..aa93bbf0e1d4 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -185,6 +185,11 @@ static bool is_quark_x1000_ssp(const struct driver_data *drv_data) return drv_data->ssp_type == QUARK_X1000_SSP; } +static bool is_mmp2_ssp(const struct driver_data *drv_data) +{ + return drv_data->ssp_type == MMP2_SSP; +} + static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) { switch (drv_data->ssp_type) { @@ -463,8 +468,8 @@ int pxa2xx_spi_flush(struct driver_data *drv_data) static void pxa2xx_spi_off(struct driver_data *drv_data) { - /* On MMP, disabling SSE seems to corrupt the rx fifo */ - if (drv_data->ssp_type == MMP2_SSP) + /* On MMP, disabling SSE seems to corrupt the Rx FIFO */ + if (is_mmp2_ssp(drv_data)) return; pxa2xx_spi_write(drv_data, SSCR0, @@ -1070,7 +1075,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) != (cr1 & change_mask)) { /* stop the SSP, and update the other bits */ - if (drv_data->ssp_type != MMP2_SSP) + if (!is_mmp2_ssp(drv_data)) pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); if (!pxa25x_ssp_comp(drv_data)) pxa2xx_spi_write(drv_data, SSTO, chip->timeout); @@ -1084,7 +1089,7 @@ static int pxa2xx_spi_transfer_one(struct spi_controller *controller, pxa2xx_spi_write(drv_data, SSTO, chip->timeout); } - if (drv_data->ssp_type == MMP2_SSP) { + if (is_mmp2_ssp(drv_data)) { u8 tx_level = (pxa2xx_spi_read(drv_data, SSSR) & SSSR_TFL_MASK) >> 8; -- cgit v1.2.3 From ea70fb5b3e8b795730ab5716592bb573648434bb Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Sat, 29 Feb 2020 18:18:40 +0200 Subject: spi: spidev: fix a debug message value The debug message in spidev_message() can show wrong xfer speed. It happens if the initial (came from DT) and set with ioctl call spidev speeds are different (spidev->speed_hz != spi->max_speed_hz) and one sends a message with ioctl call and the field of speed is uninitialized (u_tmp->speed_hz == 0). In this case the kernel shows the spi->max_speed_hz value instead of correct spidev->speed_hz. ... set the max speed with an ioctl call: [ 1227.702714] spidev spi0.0: setup mode 0, 32 bits/w, 20000000 Hz max --> 0 (real speed sets to 20000000Hz) send a message with an ioctl call: [ 1227.731801] spidev spi0.0: xfer len 4096 tx 32bits 0 usec 10000000Hz (debug message shows 10000000Hz that is the original max speed of this spidev came from DT) ... Fix the data source for the debug message. Signed-off-by: Oleksandr Suvorov Link: https://lore.kernel.org/r/20200229161841.89144-2-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown --- drivers/spi/spidev.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 2ab6e782f14c..c97e853dbf5c 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -275,14 +275,14 @@ static int spidev_message(struct spidev_data *spidev, #ifdef VERBOSE dev_dbg(&spidev->spi->dev, " xfer len %u %s%s%s%dbits %u usec %u usec %uHz\n", - u_tmp->len, - u_tmp->rx_buf ? "rx " : "", - u_tmp->tx_buf ? "tx " : "", - u_tmp->cs_change ? "cs " : "", - u_tmp->bits_per_word ? : spidev->spi->bits_per_word, - u_tmp->delay_usecs, - u_tmp->word_delay_usecs, - u_tmp->speed_hz ? : spidev->spi->max_speed_hz); + k_tmp->len, + k_tmp->rx_buf ? "rx " : "", + k_tmp->tx_buf ? "tx " : "", + k_tmp->cs_change ? "cs " : "", + k_tmp->bits_per_word ? : spidev->spi->bits_per_word, + k_tmp->delay.value, + k_tmp->word_delay.value, + k_tmp->speed_hz ? : spidev->spi->max_speed_hz); #endif spi_message_add_tail(k_tmp, &msg); } -- cgit v1.2.3 From 4276fc82fc5d1aa24c6ad1a16fbaccf11fa61e02 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Sat, 29 Feb 2020 18:18:41 +0200 Subject: spi: spidev: fix speed setting message The message of max device speed setting is shown when an error in spi_setup() occurs. Instead, it should be shown when the setup call succeeds. Signed-off-by: Oleksandr Suvorov Link: https://lore.kernel.org/r/20200229161841.89144-3-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown --- drivers/spi/spidev.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index c97e853dbf5c..80dd1025b953 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -454,10 +454,11 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) spi->max_speed_hz = tmp; retval = spi_setup(spi); - if (retval >= 0) + if (retval == 0) { spidev->speed_hz = tmp; - else - dev_dbg(&spi->dev, "%d Hz (max)\n", tmp); + dev_dbg(&spi->dev, "%d Hz (max)\n", + spidev->speed_hz); + } spi->max_speed_hz = save; } break; -- cgit v1.2.3 From 2fa98705a9289c758b6154a22174aa8d4041a285 Mon Sep 17 00:00:00 2001 From: Oleksandr Suvorov Date: Thu, 20 Feb 2020 14:11:48 +0000 Subject: spi: fsl-lpspi: remove unneeded array - replace the array with the shift operation - remove the extra comparing operation. Signed-off-by: Oleksandr Suvorov Link: https://lore.kernel.org/r/20200220141143.3902922-2-oleksandr.suvorov@toradex.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-lpspi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index d0b8cc741a24..298329b781d2 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -86,8 +86,6 @@ #define TCR_RXMSK BIT(19) #define TCR_TXMSK BIT(18) -static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128}; - struct lpspi_config { u8 bpw; u8 chip_select; @@ -331,15 +329,14 @@ static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi) } for (prescale = 0; prescale < 8; prescale++) { - scldiv = perclk_rate / - (clkdivs[prescale] * config.speed_hz) - 2; + scldiv = perclk_rate / config.speed_hz / (1 << prescale) - 2; if (scldiv < 256) { fsl_lpspi->config.prescale = prescale; break; } } - if (prescale == 8 && scldiv >= 256) + if (scldiv >= 256) return -EINVAL; writel(scldiv | (scldiv << 8) | ((scldiv >> 1) << 16), -- cgit v1.2.3 From d35054010b571486596f9da159f798fc38628683 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Mon, 2 Mar 2020 02:19:54 +0200 Subject: spi: spi-fsl-dspi: Use specific compatible strings for all SoC instantiations Currently, the device tree bindings submitted in mainline for Layerscape SoCs look like this: LS1021A: compatible = "fsl,ls1021a-v1.0-dspi"; LS1012A: compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; LS2085A: compatible = "fsl,ls2085a-dspi"; LS2088A: compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; LX2160A: compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; LS1043A: compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; LS1046A: compatible = "fsl,ls1021a-v1.0-dspi"; Due to a lack of a more specific compatible string, LS1012A, LS1043A and LS1046A will fall under the LS1021A umbrella, and LS2088A and LX2160A under the LS2085A umbrella. They do work in those modes, but there are slight differences in the hardware instantiations, mostly related to FIFO sizes (with the more specific compatible strings, the FIFO size can be increased properly). Signed-off-by: Vladimir Oltean Message-Id: <20200302001958.11105-3-olteanv@gmail.com> Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 108 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 85 insertions(+), 23 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 6ec2dcb8c57a..021c658886d4 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -133,27 +133,66 @@ struct fsl_dspi_devtype_data { bool xspi_mode; }; -static const struct fsl_dspi_devtype_data vf610_data = { - .trans_mode = DSPI_DMA_MODE, - .max_clock_factor = 2, +enum { + LS1021A, + LS1012A, + LS1043A, + LS1046A, + LS2080A, + LS2085A, + LX2160A, + MCF5441X, + VF610, }; -static const struct fsl_dspi_devtype_data ls1021a_v1_data = { - .trans_mode = DSPI_TCFQ_MODE, - .max_clock_factor = 8, - .ptp_sts_supported = true, - .xspi_mode = true, -}; - -static const struct fsl_dspi_devtype_data ls2085a_data = { - .trans_mode = DSPI_TCFQ_MODE, - .max_clock_factor = 8, - .ptp_sts_supported = true, -}; - -static const struct fsl_dspi_devtype_data coldfire_data = { - .trans_mode = DSPI_EOQ_MODE, - .max_clock_factor = 8, +static const struct fsl_dspi_devtype_data devtype_data[] = { + [VF610] = { + .trans_mode = DSPI_DMA_MODE, + .max_clock_factor = 2, + }, + [LS1021A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS1012A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS1043A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS1046A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + .xspi_mode = true, + }, + [LS2080A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + }, + [LS2085A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + }, + [LX2160A] = { + .trans_mode = DSPI_TCFQ_MODE, + .max_clock_factor = 8, + .ptp_sts_supported = true, + }, + [MCF5441X] = { + .trans_mode = DSPI_EOQ_MODE, + .max_clock_factor = 8, + }, }; struct fsl_dspi_dma { @@ -909,9 +948,31 @@ static void dspi_cleanup(struct spi_device *spi) } static const struct of_device_id fsl_dspi_dt_ids[] = { - { .compatible = "fsl,vf610-dspi", .data = &vf610_data, }, - { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, }, - { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, }, + { + .compatible = "fsl,vf610-dspi", + .data = &devtype_data[VF610], + }, { + .compatible = "fsl,ls1021a-v1.0-dspi", + .data = &devtype_data[LS1021A], + }, { + .compatible = "fsl,ls1012a-dspi", + .data = &devtype_data[LS1012A], + }, { + .compatible = "fsl,ls1043a-dspi", + .data = &devtype_data[LS1043A], + }, { + .compatible = "fsl,ls1046a-dspi", + .data = &devtype_data[LS1046A], + }, { + .compatible = "fsl,ls2080a-dspi", + .data = &devtype_data[LS2080A], + }, { + .compatible = "fsl,ls2085a-dspi", + .data = &devtype_data[LS2085A], + }, { + .compatible = "fsl,lx2160a-dspi", + .data = &devtype_data[LX2160A], + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); @@ -1064,7 +1125,8 @@ static int dspi_probe(struct platform_device *pdev) ctlr->num_chipselect = pdata->cs_num; ctlr->bus_num = pdata->bus_num; - dspi->devtype_data = &coldfire_data; + /* Only Coldfire uses platform data */ + dspi->devtype_data = &devtype_data[MCF5441X]; } else { ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); -- cgit v1.2.3 From 1d8b4c95c37ccccfc18adef7a13b79fbc3e1557e Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Mon, 2 Mar 2020 02:19:55 +0200 Subject: spi: spi-fsl-dspi: Parameterize the FIFO size and DMA buffer size Get rid of the ifdef for Coldfire and make these hardware characteristics part of dspi->devtype_data. Signed-off-by: Vladimir Oltean Message-Id: <20200302001958.11105-4-olteanv@gmail.com> Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 48 +++++++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 20 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 021c658886d4..55ccb3d0f683 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -20,13 +20,6 @@ #define DRIVER_NAME "fsl-dspi" -#ifdef CONFIG_M5441x -#define DSPI_FIFO_SIZE 16 -#else -#define DSPI_FIFO_SIZE 4 -#endif -#define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024) - #define SPI_MCR 0x00 #define SPI_MCR_MASTER BIT(31) #define SPI_MCR_PCSIS (0x3F << 16) @@ -131,6 +124,8 @@ struct fsl_dspi_devtype_data { u8 max_clock_factor; bool ptp_sts_supported; bool xspi_mode; + int fifo_size; + int dma_bufsize; }; enum { @@ -149,54 +144,64 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { [VF610] = { .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 2, + .dma_bufsize = 4096, + .fifo_size = 4, }, [LS1021A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 4, }, [LS1012A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 16, }, [LS1043A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 16, }, [LS1046A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, .xspi_mode = true, + .fifo_size = 16, }, [LS2080A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .fifo_size = 4, }, [LS2085A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .fifo_size = 4, }, [LX2160A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .fifo_size = 4, }, [MCF5441X] = { .trans_mode = DSPI_EOQ_MODE, .max_clock_factor = 8, + .fifo_size = 16, }, }; struct fsl_dspi_dma { - /* Length of transfer in words of DSPI_FIFO_SIZE */ + /* Length of transfer in words of dspi->fifo_size */ u32 curr_xfer_len; u32 *tx_dma_buf; @@ -397,7 +402,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi) int ret = 0; curr_remaining_bytes = dspi->len; - bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE; + bytes_per_buffer = dspi->devtype_data->dma_bufsize / + dspi->devtype_data->fifo_size; while (curr_remaining_bytes) { /* Check if current transfer fits the DMA buffer */ dma->curr_xfer_len = curr_remaining_bytes @@ -449,14 +455,14 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) goto err_tx_channel; } - dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, + dma->tx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, &dma->tx_dma_phys, GFP_KERNEL); if (!dma->tx_dma_buf) { ret = -ENOMEM; goto err_tx_dma_buf; } - dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE, + dma->rx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, &dma->rx_dma_phys, GFP_KERNEL); if (!dma->rx_dma_buf) { ret = -ENOMEM; @@ -493,11 +499,11 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) return 0; err_slave_config: - dma_free_coherent(dev, DSPI_DMA_BUFSIZE, - dma->rx_dma_buf, dma->rx_dma_phys); + dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->rx_dma_buf, dma->rx_dma_phys); err_rx_dma_buf: - dma_free_coherent(dev, DSPI_DMA_BUFSIZE, - dma->tx_dma_buf, dma->tx_dma_phys); + dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->tx_dma_buf, dma->tx_dma_phys); err_tx_dma_buf: dma_release_channel(dma->chan_tx); err_tx_channel: @@ -519,13 +525,15 @@ static void dspi_release_dma(struct fsl_dspi *dspi) if (dma->chan_tx) { dma_unmap_single(dev, dma->tx_dma_phys, - DSPI_DMA_BUFSIZE, DMA_TO_DEVICE); + dspi->devtype_data->dma_bufsize, + DMA_TO_DEVICE); dma_release_channel(dma->chan_tx); } if (dma->chan_rx) { dma_unmap_single(dev, dma->rx_dma_phys, - DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE); + dspi->devtype_data->dma_bufsize, + DMA_FROM_DEVICE); dma_release_channel(dma->chan_rx); } } @@ -657,7 +665,7 @@ static void dspi_tcfq_read(struct fsl_dspi *dspi) static void dspi_eoq_write(struct fsl_dspi *dspi) { - int fifo_size = DSPI_FIFO_SIZE; + int fifo_size = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; /* Fill TX FIFO with as many transfers as possible */ @@ -667,7 +675,7 @@ static void dspi_eoq_write(struct fsl_dspi *dspi) if (dspi->len == dspi->bytes_per_word || fifo_size == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Clear transfer count for first transfer in FIFO */ - if (fifo_size == (DSPI_FIFO_SIZE - 1)) + if (fifo_size == (dspi->devtype_data->fifo_size - 1)) dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; /* Write combined TX FIFO and CMD FIFO entry */ fifo_write(dspi); @@ -676,7 +684,7 @@ static void dspi_eoq_write(struct fsl_dspi *dspi) static void dspi_eoq_read(struct fsl_dspi *dspi) { - int fifo_size = DSPI_FIFO_SIZE; + int fifo_size = dspi->devtype_data->fifo_size; /* Read one FIFO entry and push to rx buffer */ while ((dspi->rx < dspi->rx_end) && fifo_size--) -- cgit v1.2.3 From ca5052c8bfab7a44efd2161ce2a9d67dfc126aa6 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Mon, 2 Mar 2020 02:19:56 +0200 Subject: spi: spi-fsl-dspi: LS2080A and LX2160A support XSPI mode XSPI allows for 2 extra features: - Command cycling (use a single TX command with more than 1 word in the TX FIFO). - Increased word size (from 16 bits to 32 bits) Signed-off-by: Vladimir Oltean Message-Id: <20200302001958.11105-5-olteanv@gmail.com> Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 55ccb3d0f683..d21cc5cdc8a4 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -179,6 +179,7 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { @@ -191,6 +192,7 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .ptp_sts_supported = true, + .xspi_mode = true, .fifo_size = 4, }, [MCF5441X] = { -- cgit v1.2.3 From 63669902f74a6133c209fc03109becf5a2141284 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Mon, 2 Mar 2020 02:19:57 +0200 Subject: spi: spi-fsl-dspi: Support SPI software timestamping in all non-DMA modes There's no reason to keep this .ptp_sts_supported property explicitly in devtype_data, since it can be deduced from the operating mode alone. Signed-off-by: Vladimir Oltean Message-Id: <20200302001958.11105-6-olteanv@gmail.com> Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index d21cc5cdc8a4..c26a42f8ecbc 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -122,7 +122,6 @@ enum dspi_trans_mode { struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; - bool ptp_sts_supported; bool xspi_mode; int fifo_size; int dma_bufsize; @@ -150,48 +149,41 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { [LS1021A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 4, }, [LS1012A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 16, }, [LS1043A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 16, }, [LS1046A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 16, }, [LS2080A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .fifo_size = 4, }, [LX2160A] = { .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, - .ptp_sts_supported = true, .xspi_mode = true, .fifo_size = 4, }, @@ -1246,7 +1238,8 @@ poll_mode: ctlr->max_speed_hz = clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor; - ctlr->ptp_sts_supported = dspi->devtype_data->ptp_sts_supported; + if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE) + ctlr->ptp_sts_supported = true; platform_set_drvdata(pdev, ctlr); -- cgit v1.2.3 From 0feaf8f5afe057c397a440e76865b3d746dc9f7e Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Mon, 2 Mar 2020 02:19:58 +0200 Subject: spi: spi-fsl-dspi: Convert the instantiations that support it to DMA The A-011218 eDMA/DSPI erratum affects most of the older Layerscape SoCs with DSPI, and its workaround is a bit intrusive. After this patch, there are no users of TCFQ mode that don't also support XSPI (previously there was LS2085A). Signed-off-by: Vladimir Oltean Message-Id: <20200302001958.11105-7-olteanv@gmail.com> Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index c26a42f8ecbc..c357c3247232 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -147,42 +147,49 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .fifo_size = 4, }, [LS1021A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 4, }, [LS1012A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 16, }, [LS1043A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 16, }, [LS1046A] = { + /* Has A-011218 DMA erratum */ .trans_mode = DSPI_TCFQ_MODE, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 16, }, [LS2080A] = { - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_DMA_MODE, + .dma_bufsize = 8, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_DMA_MODE, + .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, [LX2160A] = { - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_DMA_MODE, + .dma_bufsize = 8, .max_clock_factor = 8, .xspi_mode = true, .fifo_size = 4, -- cgit v1.2.3 From 53fadb4d90c762b560a9d0983bb5894129057ea1 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:33 +0200 Subject: spi: spi-fsl-dspi: Simplify bytes_per_word gymnastics Reduce the if-then-else-if-then-else sequence to: - a simple division in the case of bytes_per_word calculation - a memcpy command with a variable size. The semantics of larger-than-8 xfer->bits_per_word is that those words are to be interpreted and transmitted in CPU native endianness. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-2-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 21 +++------------------ 1 file changed, 3 insertions(+), 18 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index c357c3247232..896d7a0f45b0 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -252,12 +252,7 @@ static u32 dspi_pop_tx(struct fsl_dspi *dspi) u32 txdata = 0; if (dspi->tx) { - if (dspi->bytes_per_word == 1) - txdata = *(u8 *)dspi->tx; - else if (dspi->bytes_per_word == 2) - txdata = *(u16 *)dspi->tx; - else /* dspi->bytes_per_word == 4 */ - txdata = *(u32 *)dspi->tx; + memcpy(&txdata, dspi->tx, dspi->bytes_per_word); dspi->tx += dspi->bytes_per_word; } dspi->len -= dspi->bytes_per_word; @@ -284,12 +279,7 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) /* Mask off undefined bits */ rxdata &= (1 << dspi->bits_per_word) - 1; - if (dspi->bytes_per_word == 1) - *(u8 *)dspi->rx = rxdata; - else if (dspi->bytes_per_word == 2) - *(u16 *)dspi->rx = rxdata; - else /* dspi->bytes_per_word == 4 */ - *(u32 *)dspi->rx = rxdata; + memcpy(dspi->rx, &rxdata, dspi->bytes_per_word); dspi->rx += dspi->bytes_per_word; } @@ -814,12 +804,7 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->progress = 0; /* Validated transfer specific frame size (defaults applied) */ dspi->bits_per_word = transfer->bits_per_word; - if (transfer->bits_per_word <= 8) - dspi->bytes_per_word = 1; - else if (transfer->bits_per_word <= 16) - dspi->bytes_per_word = 2; - else - dspi->bytes_per_word = 4; + dspi->bytes_per_word = DIV_ROUND_UP(dspi->bits_per_word, 8); regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, -- cgit v1.2.3 From 6d6af5796e5d9a88ae83c9c753023bba61deb18b Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:34 +0200 Subject: spi: spi-fsl-dspi: Remove unused chip->void_write_data This variable has been present since the initial submission of the driver, and held, for some reason, the value of zero, to be sent on the wire in the case there wasn't any TX buffer for the current transfer. Since quite a while now, however, it isn't doing anything at all. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-3-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 6 ------ 1 file changed, 6 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 896d7a0f45b0..63ec1d634d08 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -110,7 +110,6 @@ struct chip_data { u32 ctar_val; - u16 void_write_data; }; enum dspi_trans_mode { @@ -235,7 +234,6 @@ struct fsl_dspi { const void *tx; void *rx; void *rx_end; - u16 void_write_data; u16 tx_cmd; u8 bits_per_word; u8 bytes_per_word; @@ -795,8 +793,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->tx_cmd |= SPI_PUSHR_CMD_CONT; } - dspi->void_write_data = dspi->cur_chip->void_write_data; - dspi->tx = transfer->tx_buf; dspi->rx = transfer->rx_buf; dspi->rx_end = dspi->rx + transfer->len; @@ -897,8 +893,6 @@ static int dspi_setup(struct spi_device *spi) sck_cs_delay = pdata->sck_cs_delay; } - chip->void_write_data = 0; - clkrate = clk_get_rate(dspi->clk); hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate); -- cgit v1.2.3 From 5542bd797190d5d77f1ad3a6df9628f26d117b31 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:35 +0200 Subject: spi: spi-fsl-dspi: Don't mask off undefined bits This is a useless operation, and if the driver needs to do that, there's something deeply wrong going on. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-4-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 63ec1d634d08..b92c2b84a94b 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -274,9 +274,6 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) if (!dspi->rx) return; - /* Mask off undefined bits */ - rxdata &= (1 << dspi->bits_per_word) - 1; - memcpy(dspi->rx, &rxdata, dspi->bytes_per_word); dspi->rx += dspi->bytes_per_word; } -- cgit v1.2.3 From 8f8303ee05857e1b3084c467dde8bb31c58464bd Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:36 +0200 Subject: spi: spi-fsl-dspi: Add comments around dspi_pop_tx and dspi_push_rx functions Their names are confusing, since dspi_pop_tx prepares a word to be written to the PUSHR register, and dspi_push_rx gets a word from the POPR register. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-5-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index b92c2b84a94b..a8077d4903c7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -245,6 +245,10 @@ struct fsl_dspi { struct fsl_dspi_dma *dma; }; +/* + * Pop one word from the TX buffer for pushing into the + * PUSHR register (TX FIFO) + */ static u32 dspi_pop_tx(struct fsl_dspi *dspi) { u32 txdata = 0; @@ -257,6 +261,7 @@ static u32 dspi_pop_tx(struct fsl_dspi *dspi) return txdata; } +/* Prepare one TX FIFO entry (txdata plus cmd) */ static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) { u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi); @@ -269,6 +274,7 @@ static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi) return cmd << 16 | data; } +/* Push one word to the RX buffer from the POPR register (RX FIFO) */ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) { if (!dspi->rx) -- cgit v1.2.3 From 547248fbed23f3cd2f6a5937b44fad60993640c4 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:37 +0200 Subject: spi: spi-fsl-dspi: Rename fifo_{read,write} and {tx,cmd}_fifo_write These function names are very generic and it is easy to get confused. Rename them after the hardware register that they are accessing. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-6-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index a8077d4903c7..f37090ad7ad1 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -601,12 +601,12 @@ static void ns_delay_scale(char *psc, char *sc, int delay_ns, } } -static void fifo_write(struct fsl_dspi *dspi) +static void dspi_pushr_write(struct fsl_dspi *dspi) { regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); } -static void cmd_fifo_write(struct fsl_dspi *dspi) +static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) { u16 cmd = dspi->tx_cmd; @@ -615,7 +615,7 @@ static void cmd_fifo_write(struct fsl_dspi *dspi) regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); } -static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata) +static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) { regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); } @@ -631,18 +631,18 @@ static void dspi_tcfq_write(struct fsl_dspi *dspi) */ u32 data = dspi_pop_tx(dspi); - cmd_fifo_write(dspi); - tx_fifo_write(dspi, data & 0xFFFF); - tx_fifo_write(dspi, data >> 16); + dspi_pushr_cmd_write(dspi); + dspi_pushr_txdata_write(dspi, data & 0xFFFF); + dspi_pushr_txdata_write(dspi, data >> 16); } else { /* Write one entry to both TX FIFO and CMD FIFO * simultaneously. */ - fifo_write(dspi); + dspi_pushr_write(dspi); } } -static u32 fifo_read(struct fsl_dspi *dspi) +static u32 dspi_popr_read(struct fsl_dspi *dspi) { u32 rxdata = 0; @@ -652,7 +652,7 @@ static u32 fifo_read(struct fsl_dspi *dspi) static void dspi_tcfq_read(struct fsl_dspi *dspi) { - dspi_push_rx(dspi, fifo_read(dspi)); + dspi_push_rx(dspi, dspi_popr_read(dspi)); } static void dspi_eoq_write(struct fsl_dspi *dspi) @@ -670,7 +670,7 @@ static void dspi_eoq_write(struct fsl_dspi *dspi) if (fifo_size == (dspi->devtype_data->fifo_size - 1)) dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; /* Write combined TX FIFO and CMD FIFO entry */ - fifo_write(dspi); + dspi_pushr_write(dspi); } } @@ -680,7 +680,7 @@ static void dspi_eoq_read(struct fsl_dspi *dspi) /* Read one FIFO entry and push to rx buffer */ while ((dspi->rx < dspi->rx_end) && fifo_size--) - dspi_push_rx(dspi, fifo_read(dspi)); + dspi_push_rx(dspi, dspi_popr_read(dspi)); } static int dspi_rxtx(struct fsl_dspi *dspi) -- cgit v1.2.3 From a3185c38dc6cd664b2b576eb9d3e5d2f49101a10 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:38 +0200 Subject: spi: spi-fsl-dspi: Implement .max_message_size method for EOQ mode When it gets set, End Of Queue Flag halts the DSPI controller and forces the chip select signal to deassert. This operating mode is not ideal, but it is used for the DSPI instantiations where there is no other notification from the controller that the data in the FIFO has finished transmission. So in practice, it means that transmitting buffers larger than the FIFO size will yield unpredictable results. The only controller that operates in EOQ mode is MCF5441X (Coldfire). I would say that the way EOQ is used (and documented in the reference manual, too) on this chip is incorrect, and I would personally migrate it to TCFQ, but that's notably worse in terms of performance (it can only use 1 entry of the 16-deep FIFO) and if this limitation didn't bother any Coldfire DSPI user so far, it's likely that we just need to throw an error for larger buffers to make sure that callers are aware their transfers are getting truncated/split. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-7-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f37090ad7ad1..158cb48c0f4a 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1084,6 +1084,22 @@ static int dspi_slave_abort(struct spi_master *master) return 0; } +/* + * EOQ mode will inevitably deassert its PCS signal on last word in a queue + * (hardware limitation), so we need to inform the spi_device that larger + * buffers than the FIFO size are going to have the chip select randomly + * toggling, so it has a chance to adapt its message sizes. + */ +static size_t dspi_max_message_size(struct spi_device *spi) +{ + struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller); + + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) + return dspi->devtype_data->fifo_size; + + return SIZE_MAX; +} + static int dspi_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -1105,6 +1121,7 @@ static int dspi_probe(struct platform_device *pdev) ctlr->setup = dspi_setup; ctlr->transfer_one_message = dspi_transfer_one_message; + ctlr->max_message_size = dspi_max_message_size; ctlr->dev.of_node = pdev->dev.of_node; ctlr->cleanup = dspi_cleanup; -- cgit v1.2.3 From 6a726824aaa3adaaf3bcfca3b471408e225f33d6 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:39 +0200 Subject: spi: Do spi_take_timestamp_pre for as many times as necessary When dealing with a SPI controller driver that is sending more than 1 byte at once (or the entire buffer at once), and the SPI peripheral driver has requested timestamping for a byte in the middle of the buffer, we find that spi_take_timestamp_pre never records a "pre" timestamp. This happens because the function currently expects to be called with the "progress" argument >= to what the peripheral has requested to be timestamped. But clearly there are cases when that isn't going to fly. And since we can't change the past when we realize that the opportunity to take a "pre" timestamp has just passed and there isn't going to be another one, the approach taken is to keep recording the "pre" timestamp on each call, overwriting the previously recorded one until the "post" timestamp is also taken. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-8-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi.c | 19 +++++++------------ include/linux/spi/spi.h | 3 +-- 2 files changed, 8 insertions(+), 14 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 292f26807b41..6c223f7d1ddc 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1515,17 +1515,15 @@ void spi_take_timestamp_pre(struct spi_controller *ctlr, if (!xfer->ptp_sts) return; - if (xfer->timestamped_pre) + if (xfer->timestamped) return; - if (progress < xfer->ptp_sts_word_pre) + if (progress > xfer->ptp_sts_word_pre) return; /* Capture the resolution of the timestamp */ xfer->ptp_sts_word_pre = progress; - xfer->timestamped_pre = true; - if (irqs_off) { local_irq_save(ctlr->irq_flags); preempt_disable(); @@ -1554,7 +1552,7 @@ void spi_take_timestamp_post(struct spi_controller *ctlr, if (!xfer->ptp_sts) return; - if (xfer->timestamped_post) + if (xfer->timestamped) return; if (progress < xfer->ptp_sts_word_post) @@ -1570,7 +1568,7 @@ void spi_take_timestamp_post(struct spi_controller *ctlr, /* Capture the resolution of the timestamp */ xfer->ptp_sts_word_post = progress; - xfer->timestamped_post = true; + xfer->timestamped = true; } EXPORT_SYMBOL_GPL(spi_take_timestamp_post); @@ -1675,12 +1673,9 @@ void spi_finalize_current_message(struct spi_controller *ctlr) } } - if (unlikely(ctlr->ptp_sts_supported)) { - list_for_each_entry(xfer, &mesg->transfers, transfer_list) { - WARN_ON_ONCE(xfer->ptp_sts && !xfer->timestamped_pre); - WARN_ON_ONCE(xfer->ptp_sts && !xfer->timestamped_post); - } - } + if (unlikely(ctlr->ptp_sts_supported)) + list_for_each_entry(xfer, &mesg->transfers, transfer_list) + WARN_ON_ONCE(xfer->ptp_sts && !xfer->timestamped); spi_unmap_msg(ctlr, mesg); diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 600e3793303e..87105272879b 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -933,8 +933,7 @@ struct spi_transfer { struct ptp_system_timestamp *ptp_sts; - bool timestamped_pre; - bool timestamped_post; + bool timestamped; struct list_head transfer_list; }; -- cgit v1.2.3 From d59c90a2400ffc4d7127a7653f99da1c4a8fa762 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:40 +0200 Subject: spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode The Transfer Complete Flag (TCF) interrupt gets raised after each write to the TX FIFO (PUSHR) which means that it is not possible to devise a transfer procedure that makes full utilization of the FIFO depth (4 entries on most controllers, 16 entries on some). On the other hand, XSPI mode has a feature called "command cycling", which allows a single TX command to be run for a pre-specified number of TX words. When the command cycle ends, the Command Transfer Complete Flag bit asserts and raises an interrupt. The advantage in this mode is that the TX FIFO can be better utilized (more words can be batched at once). Other changes brought by this patch: - The dspi->rx_end variable has been removed, since now the dspi_fifo_write function sets up dspi->words_in_flight, so dspi_fifo_read knows how much to read without overrunning the RX buffer. - Stop using poll mode unconditionally for TCFQ mode, since XSPI mode is a little less efficient than that, and so, poll mode doesn't bring as many improvements for XSPI. - Stop relying on the hardware transfer counter (SPI_TCR_GET_TCNT) and instead increment the message->actual_length based on the newly introduced dspi->words_in_flight variable. - The CTARE register is now written in the hotpath instead of just at transfer init time, since it contains the DTCP field (transfer preload - the counter indicating how many txdata words will follow), which is a dynamic value. Due to the fact that the Chip Select toggling setting is part of the command written to the TX FIFO, the ending word of each buffer needs to be sent via its own TX command, so that we have a chance to emit a 1-word command with deasserted PCS. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-9-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 189 ++++++++++++++++++++++++--------------------- 1 file changed, 101 insertions(+), 88 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 158cb48c0f4a..298c22def165 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -72,6 +72,7 @@ #define SPI_RSER 0x30 #define SPI_RSER_TCFQE BIT(31) #define SPI_RSER_EOQFE BIT(28) +#define SPI_RSER_CMDTCFE BIT(23) #define SPI_PUSHR 0x34 #define SPI_PUSHR_CMD_CONT BIT(15) @@ -114,14 +115,13 @@ struct chip_data { enum dspi_trans_mode { DSPI_EOQ_MODE = 0, - DSPI_TCFQ_MODE, + DSPI_XSPI_MODE, DSPI_DMA_MODE, }; struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; - bool xspi_mode; int fifo_size; int dma_bufsize; }; @@ -147,37 +147,32 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { }, [LS1021A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 4, }, [LS1012A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 16, }, [LS1043A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 16, }, [LS1046A] = { /* Has A-011218 DMA erratum */ - .trans_mode = DSPI_TCFQ_MODE, + .trans_mode = DSPI_XSPI_MODE, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 16, }, [LS2080A] = { .trans_mode = DSPI_DMA_MODE, .dma_bufsize = 8, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 4, }, [LS2085A] = { @@ -190,7 +185,6 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .trans_mode = DSPI_DMA_MODE, .dma_bufsize = 8, .max_clock_factor = 8, - .xspi_mode = true, .fifo_size = 4, }, [MCF5441X] = { @@ -233,7 +227,6 @@ struct fsl_dspi { size_t len; const void *tx; void *rx; - void *rx_end; u16 tx_cmd; u8 bits_per_word; u8 bytes_per_word; @@ -243,6 +236,8 @@ struct fsl_dspi { u32 waitflags; struct fsl_dspi_dma *dma; + + int words_in_flight; }; /* @@ -610,7 +605,17 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) { u16 cmd = dspi->tx_cmd; - if (dspi->len > 0) + /* + * The only time when the PCS doesn't need continuation after this word + * is when it's last. We need to look ahead, because we actually call + * dspi_pop_tx (the function that decrements dspi->len) _after_ + * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One + * word is enough. If there's more to transmit than that, + * dspi_xspi_write will know to split the FIFO writes in 2, and + * generate a new PUSHR command with the final word that will have PCS + * deasserted (not continued) here. + */ + if (dspi->len > dspi->bytes_per_word) cmd |= SPI_PUSHR_CMD_CONT; regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); } @@ -620,93 +625,115 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); } -static void dspi_tcfq_write(struct fsl_dspi *dspi) +static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) { - /* Clear transfer count */ - dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; + regmap_write(dspi->regmap, SPI_CTARE(0), + SPI_FRAME_EBITS(dspi->bits_per_word) | + SPI_CTARE_DTCP(cnt)); - if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) { - /* Write the CMD FIFO entry first, and then the two - * corresponding TX FIFO entries. - */ + /* + * Write the CMD FIFO entry first, and then the two + * corresponding TX FIFO entries (or one...). + */ + dspi_pushr_cmd_write(dspi); + + /* Fill TX FIFO with as many transfers as possible */ + while (cnt--) { u32 data = dspi_pop_tx(dspi); - dspi_pushr_cmd_write(dspi); dspi_pushr_txdata_write(dspi, data & 0xFFFF); - dspi_pushr_txdata_write(dspi, data >> 16); - } else { - /* Write one entry to both TX FIFO and CMD FIFO - * simultaneously. - */ - dspi_pushr_write(dspi); + if (dspi->bits_per_word > 16) + dspi_pushr_txdata_write(dspi, data >> 16); } } -static u32 dspi_popr_read(struct fsl_dspi *dspi) +static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) { - u32 rxdata = 0; + int num_fifo_entries = dspi->devtype_data->fifo_size; + int bytes_in_flight; - regmap_read(dspi->regmap, SPI_POPR, &rxdata); - return rxdata; -} + /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ + if (dspi->bits_per_word > 16) + num_fifo_entries /= 2; -static void dspi_tcfq_read(struct fsl_dspi *dspi) -{ - dspi_push_rx(dspi, dspi_popr_read(dspi)); + dspi->words_in_flight = dspi->len / dspi->bytes_per_word; + + if (dspi->words_in_flight > num_fifo_entries) + dspi->words_in_flight = num_fifo_entries; + + bytes_in_flight = dspi->words_in_flight * dspi->bytes_per_word; + + /* + * If the PCS needs to de-assert (i.e. we're at the end of the buffer + * and cs_change does not want the PCS to stay on), then we need a new + * PUSHR command, since this one (for the body of the buffer) + * necessarily has the CONT bit set. + * So send one word less during this go, to force a split and a command + * with a single word next time, when CONT will be unset. + */ + if (bytes_in_flight == dspi->len && dspi->words_in_flight > 1 && + !(dspi->tx_cmd & SPI_PUSHR_CMD_CONT)) + dspi->words_in_flight--; + + dspi_xspi_write(dspi, dspi->words_in_flight); } -static void dspi_eoq_write(struct fsl_dspi *dspi) +static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) { - int fifo_size = dspi->devtype_data->fifo_size; + int num_fifo_entries = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; + dspi->words_in_flight = num_fifo_entries; + /* Fill TX FIFO with as many transfers as possible */ - while (dspi->len && fifo_size--) { + while (dspi->len && num_fifo_entries--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (dspi->len == dspi->bytes_per_word || fifo_size == 0) + if (dspi->len == dspi->bytes_per_word || num_fifo_entries == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; - /* Clear transfer count for first transfer in FIFO */ - if (fifo_size == (dspi->devtype_data->fifo_size - 1)) - dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); } } -static void dspi_eoq_read(struct fsl_dspi *dspi) +static u32 dspi_popr_read(struct fsl_dspi *dspi) { - int fifo_size = dspi->devtype_data->fifo_size; + u32 rxdata = 0; + regmap_read(dspi->regmap, SPI_POPR, &rxdata); + return rxdata; +} + +static void dspi_fifo_read(struct fsl_dspi *dspi) +{ /* Read one FIFO entry and push to rx buffer */ - while ((dspi->rx < dspi->rx_end) && fifo_size--) + while (dspi->words_in_flight--) dspi_push_rx(dspi, dspi_popr_read(dspi)); } +static void dspi_fifo_write(struct fsl_dspi *dspi) +{ + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) + dspi_eoq_fifo_write(dspi); + else + dspi_xspi_fifo_write(dspi); +} + static int dspi_rxtx(struct fsl_dspi *dspi) { + struct spi_transfer *xfer = dspi->cur_transfer; struct spi_message *msg = dspi->cur_msg; - enum dspi_trans_mode trans_mode; - u16 spi_tcnt; - u32 spi_tcr; + int bytes_sent; + + /* Update total number of bytes that were transferred */ + bytes_sent = dspi->words_in_flight * dspi->bytes_per_word; + msg->actual_length += bytes_sent; + dspi->progress += bytes_sent / DIV_ROUND_UP(xfer->bits_per_word, 8); spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); - /* Get transfer counter (in number of SPI transfers). It was - * reset to 0 when transfer(s) were started. - */ - regmap_read(dspi->regmap, SPI_TCR, &spi_tcr); - spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr); - /* Update total number of bytes that were transferred */ - msg->actual_length += spi_tcnt * dspi->bytes_per_word; - dspi->progress += spi_tcnt; - - trans_mode = dspi->devtype_data->trans_mode; - if (trans_mode == DSPI_EOQ_MODE) - dspi_eoq_read(dspi); - else if (trans_mode == DSPI_TCFQ_MODE) - dspi_tcfq_read(dspi); + dspi_fifo_read(dspi); if (!dspi->len) /* Success! */ @@ -715,10 +742,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); - if (trans_mode == DSPI_EOQ_MODE) - dspi_eoq_write(dspi); - else if (trans_mode == DSPI_TCFQ_MODE) - dspi_tcfq_write(dspi); + dspi_fifo_write(dspi); return -EINPROGRESS; } @@ -732,7 +756,7 @@ static int dspi_poll(struct fsl_dspi *dspi) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); - if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) + if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)) break; } while (--tries); @@ -750,7 +774,7 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) regmap_read(dspi->regmap, SPI_SR, &spi_sr); regmap_write(dspi->regmap, SPI_SR, spi_sr); - if (!(spi_sr & SPI_SR_EOQF)) + if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))) return IRQ_NONE; if (dspi_rxtx(dspi) == 0) { @@ -798,7 +822,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->tx = transfer->tx_buf; dspi->rx = transfer->rx_buf; - dspi->rx_end = dspi->rx + transfer->len; dspi->len = transfer->len; dspi->progress = 0; /* Validated transfer specific frame size (defaults applied) */ @@ -811,10 +834,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, regmap_write(dspi->regmap, SPI_CTAR(0), dspi->cur_chip->ctar_val | SPI_FRAME_BITS(transfer->bits_per_word)); - if (dspi->devtype_data->xspi_mode) - regmap_write(dspi->regmap, SPI_CTARE(0), - SPI_FRAME_EBITS(transfer->bits_per_word) | - SPI_CTARE_DTCP(1)); spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); @@ -823,11 +842,11 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, switch (trans_mode) { case DSPI_EOQ_MODE: regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); - dspi_eoq_write(dspi); + dspi_fifo_write(dspi); break; - case DSPI_TCFQ_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE); - dspi_tcfq_write(dspi); + case DSPI_XSPI_MODE: + regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); + dspi_fifo_write(dspi); break; case DSPI_DMA_MODE: regmap_write(dspi->regmap, SPI_RSER, @@ -1053,16 +1072,13 @@ static void dspi_init(struct fsl_dspi *dspi) { unsigned int mcr = SPI_MCR_PCSIS; - if (dspi->devtype_data->xspi_mode) + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) mcr |= SPI_MCR_XSPI; if (!spi_controller_is_slave(dspi->ctlr)) mcr |= SPI_MCR_MASTER; regmap_write(dspi->regmap, SPI_MCR, mcr); regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); - if (dspi->devtype_data->xspi_mode) - regmap_write(dspi->regmap, SPI_CTARE(0), - SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1)); } static int dspi_slave_abort(struct spi_master *master) @@ -1162,7 +1178,7 @@ static int dspi_probe(struct platform_device *pdev) } } - if (dspi->devtype_data->xspi_mode) + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); else ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); @@ -1174,7 +1190,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } - if (dspi->devtype_data->xspi_mode) + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) regmap_config = &dspi_xspi_regmap_config[0]; else regmap_config = &dspi_regmap_config; @@ -1186,7 +1202,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_ctlr_put; } - if (dspi->devtype_data->xspi_mode) { + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) { dspi->regmap_pushr = devm_regmap_init_mmio( &pdev->dev, base + SPI_PUSHR, &dspi_xspi_regmap_config[1]); @@ -1211,9 +1227,6 @@ static int dspi_probe(struct platform_device *pdev) dspi_init(dspi); - if (dspi->devtype_data->trans_mode == DSPI_TCFQ_MODE) - goto poll_mode; - dspi->irq = platform_get_irq(pdev, 0); if (dspi->irq <= 0) { dev_info(&pdev->dev, -- cgit v1.2.3 From 6c1c26ecd9a31c24f9ea7dfb174528141dd32361 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:41 +0200 Subject: spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible This patch adds logic in the driver to transmit SPI buffers that use bits_per_word=8 with a higher bits_per_word count (multiple of 8). Currently the following (most common) modes are implemented: - 8 bits_per_word on 32-bit capable controllers - 8 bits_per_word on 16-bit capable controllers - 16 bits_per_word on 32-bit capable controllers Transfers which are not accelerated are transferred with a hardware bits_per_word value equal to the one of the SPI transfer. The difference from just extending bits_per_word=32 at the spi_device driver level is that endianness is different - the SPI core wants to treat bits_per_word=32 buffers as arrays of u32 (i.e. words in host CPU endianness). So to preserve endianness when clumping 8x4 bits into 32-bit words, one must perform conversion between CPU and standard (big) endianness. All appearances (both on the wire as well as in the buffers presented to the peripheral driver) are preserved, just that accesses to the PUSHR and POPR registers are now more efficient, since the same number of reads/writes can now carry more data (2x more data on TX, 4x more data on RX). Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-10-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 160 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 135 insertions(+), 25 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 298c22def165..f5b802070d29 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -228,8 +228,6 @@ struct fsl_dspi { const void *tx; void *rx; u16 tx_cmd; - u8 bits_per_word; - u8 bytes_per_word; const struct fsl_dspi_devtype_data *devtype_data; wait_queue_head_t waitq; @@ -237,9 +235,70 @@ struct fsl_dspi { struct fsl_dspi_dma *dma; + int oper_word_size; + int oper_bits_per_word; + int words_in_flight; + + void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); + void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; +static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + memcpy(txdata, dspi->tx, dspi->oper_word_size); + dspi->tx += dspi->oper_word_size; +} + +static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + memcpy(dspi->rx, &rxdata, dspi->oper_word_size); + dspi->rx += dspi->oper_word_size; +} + +static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + *txdata = cpu_to_be32(*(u32 *)dspi->tx); + dspi->tx += sizeof(u32); +} + +static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + *(u32 *)dspi->rx = be32_to_cpu(rxdata); + dspi->rx += sizeof(u32); +} + +static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + *txdata = cpu_to_be16(*(u16 *)dspi->tx); + dspi->tx += sizeof(u16); +} + +static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + *(u16 *)dspi->rx = be16_to_cpu(rxdata); + dspi->rx += sizeof(u16); +} + +static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata) +{ + u16 hi = *(u16 *)dspi->tx; + u16 lo = *(u16 *)(dspi->tx + 2); + + *txdata = (u32)hi << 16 | lo; + dspi->tx += sizeof(u32); +} + +static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata) +{ + u16 hi = rxdata & 0xffff; + u16 lo = rxdata >> 16; + + *(u16 *)dspi->rx = lo; + *(u16 *)(dspi->rx + 2) = hi; + dspi->rx += sizeof(u32); +} + /* * Pop one word from the TX buffer for pushing into the * PUSHR register (TX FIFO) @@ -248,11 +307,9 @@ static u32 dspi_pop_tx(struct fsl_dspi *dspi) { u32 txdata = 0; - if (dspi->tx) { - memcpy(&txdata, dspi->tx, dspi->bytes_per_word); - dspi->tx += dspi->bytes_per_word; - } - dspi->len -= dspi->bytes_per_word; + if (dspi->tx) + dspi->host_to_dev(dspi, &txdata); + dspi->len -= dspi->oper_word_size; return txdata; } @@ -274,9 +331,7 @@ static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata) { if (!dspi->rx) return; - - memcpy(dspi->rx, &rxdata, dspi->bytes_per_word); - dspi->rx += dspi->bytes_per_word; + dspi->dev_to_host(dspi, rxdata); } static void dspi_tx_dma_callback(void *arg) @@ -393,8 +448,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi) dspi->devtype_data->fifo_size; while (curr_remaining_bytes) { /* Check if current transfer fits the DMA buffer */ - dma->curr_xfer_len = curr_remaining_bytes - / dspi->bytes_per_word; + dma->curr_xfer_len = curr_remaining_bytes / + dspi->oper_word_size; if (dma->curr_xfer_len > bytes_per_buffer) dma->curr_xfer_len = bytes_per_buffer; @@ -404,8 +459,8 @@ static int dspi_dma_xfer(struct fsl_dspi *dspi) goto exit; } else { - const int len = - dma->curr_xfer_len * dspi->bytes_per_word; + const int len = dma->curr_xfer_len * + dspi->oper_word_size; curr_remaining_bytes -= len; message->actual_length += len; if (curr_remaining_bytes < 0) @@ -615,7 +670,7 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) * generate a new PUSHR command with the final word that will have PCS * deasserted (not continued) here. */ - if (dspi->len > dspi->bytes_per_word) + if (dspi->len > dspi->oper_word_size) cmd |= SPI_PUSHR_CMD_CONT; regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); } @@ -627,8 +682,9 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) { + /* Update CTARE */ regmap_write(dspi->regmap, SPI_CTARE(0), - SPI_FRAME_EBITS(dspi->bits_per_word) | + SPI_FRAME_EBITS(dspi->oper_bits_per_word) | SPI_CTARE_DTCP(cnt)); /* @@ -642,7 +698,7 @@ static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) u32 data = dspi_pop_tx(dspi); dspi_pushr_txdata_write(dspi, data & 0xFFFF); - if (dspi->bits_per_word > 16) + if (dspi->oper_bits_per_word > 16) dspi_pushr_txdata_write(dspi, data >> 16); } } @@ -653,15 +709,20 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) int bytes_in_flight; /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ - if (dspi->bits_per_word > 16) + if (dspi->oper_word_size == 4) num_fifo_entries /= 2; - dspi->words_in_flight = dspi->len / dspi->bytes_per_word; + /* + * Integer division intentionally trims off odd (or non-multiple of 4) + * numbers of bytes at the end of the buffer, which will be sent next + * time using a smaller oper_word_size. + */ + dspi->words_in_flight = dspi->len / dspi->oper_word_size; if (dspi->words_in_flight > num_fifo_entries) dspi->words_in_flight = num_fifo_entries; - bytes_in_flight = dspi->words_in_flight * dspi->bytes_per_word; + bytes_in_flight = dspi->words_in_flight * dspi->oper_word_size; /* * If the PCS needs to de-assert (i.e. we're at the end of the buffer @@ -689,7 +750,7 @@ static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) while (dspi->len && num_fifo_entries--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (dspi->len == dspi->bytes_per_word || num_fifo_entries == 0) + if (dspi->len == dspi->oper_word_size || num_fifo_entries == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); @@ -711,8 +772,56 @@ static void dspi_fifo_read(struct fsl_dspi *dspi) dspi_push_rx(dspi, dspi_popr_read(dspi)); } +static void dspi_setup_accel(struct fsl_dspi *dspi) +{ + struct spi_transfer *xfer = dspi->cur_transfer; + + /* Start off with maximum supported by hardware */ + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) + dspi->oper_bits_per_word = 32; + else + dspi->oper_bits_per_word = 16; + + /* And go down only if the buffer can't be sent with words this big */ + do { + if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) + break; + + dspi->oper_bits_per_word /= 2; + } while (dspi->oper_bits_per_word > 8); + + if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) { + dspi->dev_to_host = dspi_8on32_dev_to_host; + dspi->host_to_dev = dspi_8on32_host_to_dev; + } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) { + dspi->dev_to_host = dspi_8on16_dev_to_host; + dspi->host_to_dev = dspi_8on16_host_to_dev; + } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) { + dspi->dev_to_host = dspi_16on32_dev_to_host; + dspi->host_to_dev = dspi_16on32_host_to_dev; + } else { + /* No acceleration needed (8dev_to_host = dspi_native_dev_to_host; + dspi->host_to_dev = dspi_native_host_to_dev; + dspi->oper_bits_per_word = xfer->bits_per_word; + } + + dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8); + + /* + * Update CTAR here (code is common for both EOQ and XSPI modes). + * We will update CTARE in the portion specific to XSPI, when we + * also know the preload value (DTCP). + */ + regmap_write(dspi->regmap, SPI_CTAR(0), + dspi->cur_chip->ctar_val | + SPI_FRAME_BITS(dspi->oper_bits_per_word)); +} + static void dspi_fifo_write(struct fsl_dspi *dspi) { + dspi_setup_accel(dspi); + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) dspi_eoq_fifo_write(dspi); else @@ -726,7 +835,7 @@ static int dspi_rxtx(struct fsl_dspi *dspi) int bytes_sent; /* Update total number of bytes that were transferred */ - bytes_sent = dspi->words_in_flight * dspi->bytes_per_word; + bytes_sent = dspi->words_in_flight * dspi->oper_word_size; msg->actual_length += bytes_sent; dspi->progress += bytes_sent / DIV_ROUND_UP(xfer->bits_per_word, 8); @@ -824,13 +933,14 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, dspi->rx = transfer->rx_buf; dspi->len = transfer->len; dspi->progress = 0; - /* Validated transfer specific frame size (defaults applied) */ - dspi->bits_per_word = transfer->bits_per_word; - dspi->bytes_per_word = DIV_ROUND_UP(dspi->bits_per_word, 8); regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); + /* + * Static CTAR setup for modes that don't dynamically adjust it + * via dspi_setup_accel (aka for DMA) + */ regmap_write(dspi->regmap, SPI_CTAR(0), dspi->cur_chip->ctar_val | SPI_FRAME_BITS(transfer->bits_per_word)); -- cgit v1.2.3 From 6365504d42d90c68555ee40cdf297a1f187cb4a3 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:42 +0200 Subject: spi: spi-fsl-dspi: Optimize dspi_setup_accel for lowest interrupt count Currently, a SPI transfer that is not multiple of the highest supported word width (e.g. 4 bytes) will be transmitted as follows (assume a 30-byte buffer transmitted through a 32-bit wide FIFO that is 32 bytes deep): - First 28 bytes are sent as 7 words of 32 bits each - Last 2 bytes are sent as 1 word of 16 bits size But if the dspi_setup_accel function had decided to use a lower oper_bits_per_word value (16 instead of 32), there would have been enough space in the TX FIFO to fit the entire buffer in one go (15 words of 16 bits each). What we're actually trying to avoid is mixing word sizes within the same run with the TX FIFO, since there is an erratum surrounding this, and invalid data might get transmitted. So this patch adds special cases for when the remaining length of the buffer can be sent in one go as 8-bit or 16-bit words, otherwise it falls back to the standard logic of sending as many bytes as possible at the highest oper_bits_per_word value possible. The benefit is that there will be one less CMDFQ/EOQ interrupt to service when the entire buffer is transmitted during a single go, and that will improve the overall latency of the transfer. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-11-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f5b802070d29..df4944353ed5 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -775,20 +775,34 @@ static void dspi_fifo_read(struct fsl_dspi *dspi) static void dspi_setup_accel(struct fsl_dspi *dspi) { struct spi_transfer *xfer = dspi->cur_transfer; + bool odd = !!(dspi->len & 1); - /* Start off with maximum supported by hardware */ - if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) - dspi->oper_bits_per_word = 32; - else + /* No accel for frames not multiple of 8 bits at the moment */ + if (xfer->bits_per_word % 8) + goto no_accel; + + if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) { dspi->oper_bits_per_word = 16; + } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) { + dspi->oper_bits_per_word = 8; + } else { + /* Start off with maximum supported by hardware */ + if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) + dspi->oper_bits_per_word = 32; + else + dspi->oper_bits_per_word = 16; - /* And go down only if the buffer can't be sent with words this big */ - do { - if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) - break; + /* + * And go down only if the buffer can't be sent with + * words this big + */ + do { + if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8)) + break; - dspi->oper_bits_per_word /= 2; - } while (dspi->oper_bits_per_word > 8); + dspi->oper_bits_per_word /= 2; + } while (dspi->oper_bits_per_word > 8); + } if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) { dspi->dev_to_host = dspi_8on32_dev_to_host; @@ -800,7 +814,7 @@ static void dspi_setup_accel(struct fsl_dspi *dspi) dspi->dev_to_host = dspi_16on32_dev_to_host; dspi->host_to_dev = dspi_16on32_host_to_dev; } else { - /* No acceleration needed (8dev_to_host = dspi_native_dev_to_host; dspi->host_to_dev = dspi_native_host_to_dev; dspi->oper_bits_per_word = xfer->bits_per_word; -- cgit v1.2.3 From ea93ed4c181bd42d27b49b612d56f4ceb23d1d6c Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:43 +0200 Subject: spi: spi-fsl-dspi: Use EOQ for last word in buffer even for XSPI mode The EOQ mode has a hardware limitation in that it stops the transmission (including the deassertion of the chip select signal) once the host CPU requests end-of-queue for a particular word in the TX FIFO. And XSPI mode has a limitation in that we need a separate CMD FIFO entry for the last byte in the buffer, where the chip select signal needs to be deasserted. It's not a functional limitation, but it's rather clunky and the fact that we need to halt the pipeline and write a single entry to the TX FIFO whenever a buffer ends brings the throughput down when transmitting small buffers. So the idea here is to use EOQ's limitation in our favor when using XSPI mode. Stop special-casing that final word in the buffer, and just kill the chip select signal by issuing an EOQ for that last word. Now it can be mixed in with all the other words in the current TX FIFO train. A small trick here is that we still keep using the XSPI-specific signaling via the CMDTCFQ interrupt in RSER, and not enabling the EOQ interrupt, in order to avoid hardware weirdness (potential races with separate interrupts being raised for CMDTCFQ and EOQ for what is in fact the end of the same transmission). That is just theoretical, but it's good to be cautious, and the EOQ interrupt isn't needed. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-12-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index df4944353ed5..d5983be32180 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -656,10 +656,8 @@ static void dspi_pushr_write(struct fsl_dspi *dspi) regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi)); } -static void dspi_pushr_cmd_write(struct fsl_dspi *dspi) +static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) { - u16 cmd = dspi->tx_cmd; - /* * The only time when the PCS doesn't need continuation after this word * is when it's last. We need to look ahead, because we actually call @@ -680,8 +678,13 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); } -static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) +static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) { + u16 tx_cmd = dspi->tx_cmd; + + if (eoq) + tx_cmd |= SPI_PUSHR_CMD_EOQ; + /* Update CTARE */ regmap_write(dspi->regmap, SPI_CTARE(0), SPI_FRAME_EBITS(dspi->oper_bits_per_word) | @@ -691,7 +694,7 @@ static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt) * Write the CMD FIFO entry first, and then the two * corresponding TX FIFO entries (or one...). */ - dspi_pushr_cmd_write(dspi); + dspi_pushr_cmd_write(dspi, tx_cmd); /* Fill TX FIFO with as many transfers as possible */ while (cnt--) { @@ -707,6 +710,7 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) { int num_fifo_entries = dspi->devtype_data->fifo_size; int bytes_in_flight; + bool eoq = false; /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ if (dspi->oper_word_size == 4) @@ -732,11 +736,11 @@ static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) * So send one word less during this go, to force a split and a command * with a single word next time, when CONT will be unset. */ - if (bytes_in_flight == dspi->len && dspi->words_in_flight > 1 && - !(dspi->tx_cmd & SPI_PUSHR_CMD_CONT)) - dspi->words_in_flight--; + if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && + bytes_in_flight == dspi->len) + eoq = true; - dspi_xspi_write(dspi, dspi->words_in_flight); + dspi_xspi_write(dspi, dspi->words_in_flight, eoq); } static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) -- cgit v1.2.3 From e9bac90036d394b01cc7d5297a11d33b8ab92a91 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Thu, 5 Mar 2020 00:00:44 +0200 Subject: spi: spi-fsl-dspi: Take software timestamp in dspi_fifo_write Although the SPI system timestamps are supposed to reflect the moment that the peripheral has received a word rather than the moment when the CPU has enqueued that word to the FIFO, in practice it is easier to just record the latter time than the former (with a smaller error). With the recent migration of TCFQ users from poll back to interrupt mode (this time for XSPI FIFO), it's wiser to keep the interrupt latency outside of the measurement of the PTP system timestamp itself. If there proves to be any constant offset that requires static compensation, that can always be added later. So far that does not appear to be the case at least on the LS1021A-TSN board, where testing shows that the phc2sys offset is able to remain within +/- 200 ns even after 68 hours of testing. Signed-off-by: Vladimir Oltean Link: https://lore.kernel.org/r/20200304220044.11193-13-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index d5983be32180..b5ab0afbfa26 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -838,19 +838,18 @@ no_accel: static void dspi_fifo_write(struct fsl_dspi *dspi) { + struct spi_transfer *xfer = dspi->cur_transfer; + struct spi_message *msg = dspi->cur_msg; + int bytes_sent; + dspi_setup_accel(dspi); + spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq); + if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) dspi_eoq_fifo_write(dspi); else dspi_xspi_fifo_write(dspi); -} - -static int dspi_rxtx(struct fsl_dspi *dspi) -{ - struct spi_transfer *xfer = dspi->cur_transfer; - struct spi_message *msg = dspi->cur_msg; - int bytes_sent; /* Update total number of bytes that were transferred */ bytes_sent = dspi->words_in_flight * dspi->oper_word_size; @@ -859,16 +858,16 @@ static int dspi_rxtx(struct fsl_dspi *dspi) spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); +} +static int dspi_rxtx(struct fsl_dspi *dspi) +{ dspi_fifo_read(dspi); if (!dspi->len) /* Success! */ return 0; - spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, - dspi->progress, !dspi->irq); - dspi_fifo_write(dspi); return -EINPROGRESS; -- cgit v1.2.3 From 941be8a73f783aa0d5972b302b8794f984ed032c Mon Sep 17 00:00:00 2001 From: Han Xu Date: Sun, 26 Jan 2020 08:09:08 -0600 Subject: spi: fspi: enable fspi on imx8qxp and imx8mm Pull in this patch from NXP's upstream repo to enable fspi on imx8qxp and imx8mm Signed-off-by: Adam Ford Signed-off-by: Han Xu Link: https://lore.kernel.org/r/20200126140913.2139260-1-aford173@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-nxp-fspi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 8c5084a3a617..00c7899428a1 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -324,6 +324,22 @@ static const struct nxp_fspi_devtype_data lx2160a_data = { .little_endian = true, /* little-endian */ }; +static const struct nxp_fspi_devtype_data imx8mm_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .little_endian = true, /* little-endian */ +}; + +static const struct nxp_fspi_devtype_data imx8qxp_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .little_endian = true, /* little-endian */ +}; + struct nxp_fspi { void __iomem *iobase; void __iomem *ahb_addr; @@ -1076,6 +1092,8 @@ static int nxp_fspi_resume(struct device *dev) static const struct of_device_id nxp_fspi_dt_ids[] = { { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, }, + { .compatible = "nxp,imx8mm-fspi", .data = (void *)&imx8mm_data, }, + { .compatible = "nxp,imx8qxp-fspi", .data = (void *)&imx8qxp_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids); -- cgit v1.2.3 From d166a73503ef74fb761f1a3103ef7919928d7b52 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Sun, 26 Jan 2020 08:09:09 -0600 Subject: spi: fspi: dynamically alloc AHB memory Apply patch from NXP upstream repo to dynamically allocate AHB memory as needed. Signed-off-by: Adam Ford Signed-off-by: Han Xu Link: https://lore.kernel.org/r/20200126140913.2139260-2-aford173@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-nxp-fspi.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 00c7899428a1..23abf5ae318e 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -307,6 +307,7 @@ #define POLL_TOUT 5000 #define NXP_FSPI_MAX_CHIPSELECT 4 +#define NXP_FSPI_MIN_IOMAP SZ_4M struct nxp_fspi_devtype_data { unsigned int rxfifo; @@ -345,6 +346,8 @@ struct nxp_fspi { void __iomem *ahb_addr; u32 memmap_phy; u32 memmap_phy_size; + u32 memmap_start; + u32 memmap_len; struct clk *clk, *clk_en; struct device *dev; struct completion c; @@ -657,12 +660,35 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi) f->selected = spi->chip_select; } -static void nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) +static int nxp_fspi_read_ahb(struct nxp_fspi *f, const struct spi_mem_op *op) { + u32 start = op->addr.val; u32 len = op->data.nbytes; + /* if necessary, ioremap before AHB read */ + if ((!f->ahb_addr) || start < f->memmap_start || + start + len > f->memmap_start + f->memmap_len) { + if (f->ahb_addr) + iounmap(f->ahb_addr); + + f->memmap_start = start; + f->memmap_len = len > NXP_FSPI_MIN_IOMAP ? + len : NXP_FSPI_MIN_IOMAP; + + f->ahb_addr = ioremap_wc(f->memmap_phy + f->memmap_start, + f->memmap_len); + + if (!f->ahb_addr) { + dev_err(f->dev, "failed to alloc memory\n"); + return -ENOMEM; + } + } + /* Read out the data directly from the AHB buffer. */ - memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len); + memcpy_fromio(op->data.buf.in, + f->ahb_addr + start - f->memmap_start, len); + + return 0; } static void nxp_fspi_fill_txfifo(struct nxp_fspi *f, @@ -822,7 +848,7 @@ static int nxp_fspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) */ if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && op->data.dir == SPI_MEM_DATA_IN) { - nxp_fspi_read_ahb(f, op); + err = nxp_fspi_read_ahb(f, op); } else { if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) nxp_fspi_fill_txfifo(f, op); @@ -992,9 +1018,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) /* find the resources - controller memory mapped space */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_mmap"); - f->ahb_addr = devm_ioremap_resource(dev, res); - if (IS_ERR(f->ahb_addr)) { - ret = PTR_ERR(f->ahb_addr); + if (IS_ERR(res)) { + ret = PTR_ERR(res); goto err_put_ctrl; } @@ -1073,6 +1098,9 @@ static int nxp_fspi_remove(struct platform_device *pdev) mutex_destroy(&f->lock); + if (f->ahb_addr) + iounmap(f->ahb_addr); + return 0; } -- cgit v1.2.3 From b7461fa5be3cca1006c63f92012cee57ceb09ba0 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Sun, 26 Jan 2020 08:09:10 -0600 Subject: spi: spi-nxp-fspi: Enable the Octal Mode in MCR0 Apply patch from NXP upstream repo to Enable the octal combination mode in MCR0 Signed-off-by: Adam Ford Signed-off-by: Han Xu Link: https://lore.kernel.org/r/20200126140913.2139260-3-aford173@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-nxp-fspi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 23abf5ae318e..019f40e2917c 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -913,8 +913,9 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) fspi_writel(f, FSPI_DLLBCR_OVRDEN, base + FSPI_DLLBCR); /* enable module */ - fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | FSPI_MCR0_IP_TIMEOUT(0xFF), - base + FSPI_MCR0); + fspi_writel(f, FSPI_MCR0_AHB_TIMEOUT(0xFF) | + FSPI_MCR0_IP_TIMEOUT(0xFF) | (u32) FSPI_MCR0_OCTCOMB_EN, + base + FSPI_MCR0); /* * Disable same device enable bit and configure all slave devices -- cgit v1.2.3 From 29d2daf2c33ce9b1038f3fcd55e16a788c00fc86 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 5 Mar 2020 12:55:46 +0100 Subject: spi: spi-fsl-dspi: Make bus-num property optional The SPI bus number is completely optional to Linux, so make the corresponding device tree property optional as well. Signed-off-by: Sascha Hauer Link: https://lore.kernel.org/r/20200305115546.31814-1-s.hauer@pengutronix.de Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 2 +- drivers/spi/spi-fsl-dspi.c | 8 ++------ 2 files changed, 3 insertions(+), 7 deletions(-) (limited to 'drivers/spi') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt index 99b94cfe1623..30a79da9c039 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt @@ -19,11 +19,11 @@ Required properties: - pinctrl-0: pin control group to be used for this controller. - pinctrl-names: must contain a "default" entry. - spi-num-chipselects : the number of the chipselect signals. -- bus-num : the slave chip chipselect signal number. Optional property: - big-endian: If present the dspi device's registers are implemented in big endian mode. +- bus-num : the slave chip chipselect signal number. Optional SPI slave node properties: - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index c357c3247232..74dc0df518fa 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1108,7 +1108,7 @@ static int dspi_probe(struct platform_device *pdev) const struct regmap_config *regmap_config; struct fsl_dspi_platform_data *pdata; struct spi_controller *ctlr; - int ret, cs_num, bus_num; + int ret, cs_num, bus_num = -1; struct fsl_dspi *dspi; struct resource *res; void __iomem *base; @@ -1145,11 +1145,7 @@ static int dspi_probe(struct platform_device *pdev) } ctlr->num_chipselect = cs_num; - ret = of_property_read_u32(np, "bus-num", &bus_num); - if (ret < 0) { - dev_err(&pdev->dev, "can't get bus-num\n"); - goto out_ctlr_put; - } + of_property_read_u32(np, "bus-num", &bus_num); ctlr->bus_num = bus_num; if (of_property_read_bool(np, "spi-slave")) -- cgit v1.2.3 From e14572c52546c16e159c4c1814984843a119e823 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Thu, 5 Mar 2020 07:15:53 -0800 Subject: spi: Remove CONFIG_ prefix from Kconfig select commit a2ca53b52e00 ("spi: Add HiSilicon v3xx SPI NOR flash controller driver") likely inadvertently used a select statement with a CONFIG_ prefix, remove the prefix. Reported-by: Randy Dunlap Signed-off-by: Joe Perches Acked-by: John Garry Link: https://lore.kernel.org/r/f8ac6b32a29b9a05b58a7e58ffe8b780642abbf1.camel@perches.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 887fefe87fd5..9c5dadb238dc 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -292,7 +292,7 @@ config SPI_HISI_SFC_V3XX tristate "HiSilicon SPI-NOR Flash Controller for Hi16XX chipsets" depends on (ARM64 && ACPI) || COMPILE_TEST depends on HAS_IOMEM - select CONFIG_MTD_SPI_NOR + select MTD_SPI_NOR help This enables support for HiSilicon v3xx SPI-NOR flash controller found in hi16xx chipsets. -- cgit v1.2.3 From bbb6b2f9865b3ed23eb457131b9ea541a3173a66 Mon Sep 17 00:00:00 2001 From: Eddie James Date: Fri, 6 Mar 2020 13:41:18 -0600 Subject: spi: Add FSI-attached SPI controller driver There exists a set of SPI controllers on some POWER processors that may be accessed through the FSI bus. Add a driver to traverse the FSI CFAM engine that can access and drive the SPI controllers. This driver would typically be used by a baseboard management controller (BMC). The SPI controllers operate by means of programming a sequencing engine which automatically manages the usual SPI protocol buses. The driver programs each transfer into the sequencer as various operations specifying the slave chip and shifting data in and out on the lines. Signed-off-by: Eddie James Link: https://lore.kernel.org/r/20200306194118.18581-3-eajames@linux.ibm.com Signed-off-by: Mark Brown --- MAINTAINERS | 7 + drivers/spi/Kconfig | 7 + drivers/spi/Makefile | 1 + drivers/spi/spi-fsi.c | 558 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 573 insertions(+) create mode 100644 drivers/spi/spi-fsi.c (limited to 'drivers/spi') diff --git a/MAINTAINERS b/MAINTAINERS index 7c1080015943..6f99b4a4ae20 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6861,6 +6861,13 @@ S: Maintained F: drivers/i2c/busses/i2c-fsi.c F: Documentation/devicetree/bindings/i2c/i2c-fsi.txt +FSI-ATTACHED SPI DRIVER +M: Eddie James +L: linux-spi@vger.kernel.org +S: Maintained +F: drivers/spi/spi-fsi.c +F: Documentation/devicetree/bindings/fsi/ibm,fsi2spi.yaml + FSNOTIFY: FILESYSTEM NOTIFICATION INFRASTRUCTURE M: Jan Kara R: Amir Goldstein diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9c5dadb238dc..8ad267cb15cd 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -271,6 +271,13 @@ config SPI_FALCON has only been tested with m25p80 type chips. The hardware has no support for other types of SPI peripherals. +config SPI_FSI + tristate "FSI SPI driver" + depends on FSI + help + This enables support for the driver for FSI bus attached SPI + controllers. + config SPI_FSL_LPSPI tristate "Freescale i.MX LPSPI controller" depends on ARCH_MXC || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 74db1f2c3299..aba824a2c447 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -42,6 +42,7 @@ spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o obj-$(CONFIG_SPI_EFM32) += spi-efm32.o obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o obj-$(CONFIG_SPI_FALCON) += spi-falcon.o +obj-$(CONFIG_SPI_FSI) += spi-fsi.o obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl-dspi.o obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o diff --git a/drivers/spi/spi-fsi.c b/drivers/spi/spi-fsi.c new file mode 100644 index 000000000000..37a3e0f8e752 --- /dev/null +++ b/drivers/spi/spi-fsi.c @@ -0,0 +1,558 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (C) IBM Corporation 2020 + +#include +#include +#include +#include +#include +#include +#include +#include + +#define FSI_ENGID_SPI 0x23 +#define FSI_MBOX_ROOT_CTRL_8 0x2860 + +#define FSI2SPI_DATA0 0x00 +#define FSI2SPI_DATA1 0x04 +#define FSI2SPI_CMD 0x08 +#define FSI2SPI_CMD_WRITE BIT(31) +#define FSI2SPI_RESET 0x18 +#define FSI2SPI_STATUS 0x1c +#define FSI2SPI_STATUS_ANY_ERROR BIT(31) +#define FSI2SPI_IRQ 0x20 + +#define SPI_FSI_BASE 0x70000 +#define SPI_FSI_INIT_TIMEOUT_MS 1000 +#define SPI_FSI_MAX_TRANSFER_SIZE 2048 + +#define SPI_FSI_ERROR 0x0 +#define SPI_FSI_COUNTER_CFG 0x1 +#define SPI_FSI_COUNTER_CFG_LOOPS(x) (((u64)(x) & 0xffULL) << 32) +#define SPI_FSI_CFG1 0x2 +#define SPI_FSI_CLOCK_CFG 0x3 +#define SPI_FSI_CLOCK_CFG_MM_ENABLE BIT_ULL(32) +#define SPI_FSI_CLOCK_CFG_ECC_DISABLE (BIT_ULL(35) | BIT_ULL(33)) +#define SPI_FSI_CLOCK_CFG_RESET1 (BIT_ULL(36) | BIT_ULL(38)) +#define SPI_FSI_CLOCK_CFG_RESET2 (BIT_ULL(37) | BIT_ULL(39)) +#define SPI_FSI_CLOCK_CFG_MODE (BIT_ULL(41) | BIT_ULL(42)) +#define SPI_FSI_CLOCK_CFG_SCK_RECV_DEL GENMASK_ULL(51, 44) +#define SPI_FSI_CLOCK_CFG_SCK_NO_DEL BIT_ULL(51) +#define SPI_FSI_CLOCK_CFG_SCK_DIV GENMASK_ULL(63, 52) +#define SPI_FSI_MMAP 0x4 +#define SPI_FSI_DATA_TX 0x5 +#define SPI_FSI_DATA_RX 0x6 +#define SPI_FSI_SEQUENCE 0x7 +#define SPI_FSI_SEQUENCE_STOP 0x00 +#define SPI_FSI_SEQUENCE_SEL_SLAVE(x) (0x10 | ((x) & 0xf)) +#define SPI_FSI_SEQUENCE_SHIFT_OUT(x) (0x30 | ((x) & 0xf)) +#define SPI_FSI_SEQUENCE_SHIFT_IN(x) (0x40 | ((x) & 0xf)) +#define SPI_FSI_SEQUENCE_COPY_DATA_TX 0xc0 +#define SPI_FSI_SEQUENCE_BRANCH(x) (0xe0 | ((x) & 0xf)) +#define SPI_FSI_STATUS 0x8 +#define SPI_FSI_STATUS_ERROR \ + (GENMASK_ULL(31, 21) | GENMASK_ULL(15, 12)) +#define SPI_FSI_STATUS_SEQ_STATE GENMASK_ULL(55, 48) +#define SPI_FSI_STATUS_SEQ_STATE_IDLE BIT_ULL(48) +#define SPI_FSI_STATUS_TDR_UNDERRUN BIT_ULL(57) +#define SPI_FSI_STATUS_TDR_OVERRUN BIT_ULL(58) +#define SPI_FSI_STATUS_TDR_FULL BIT_ULL(59) +#define SPI_FSI_STATUS_RDR_UNDERRUN BIT_ULL(61) +#define SPI_FSI_STATUS_RDR_OVERRUN BIT_ULL(62) +#define SPI_FSI_STATUS_RDR_FULL BIT_ULL(63) +#define SPI_FSI_STATUS_ANY_ERROR \ + (SPI_FSI_STATUS_ERROR | SPI_FSI_STATUS_TDR_UNDERRUN | \ + SPI_FSI_STATUS_TDR_OVERRUN | SPI_FSI_STATUS_RDR_UNDERRUN | \ + SPI_FSI_STATUS_RDR_OVERRUN) +#define SPI_FSI_PORT_CTRL 0x9 + +struct fsi_spi { + struct device *dev; /* SPI controller device */ + struct fsi_device *fsi; /* FSI2SPI CFAM engine device */ + u32 base; +}; + +struct fsi_spi_sequence { + int bit; + u64 data; +}; + +static int fsi_spi_check_status(struct fsi_spi *ctx) +{ + int rc; + u32 sts; + __be32 sts_be; + + rc = fsi_device_read(ctx->fsi, FSI2SPI_STATUS, &sts_be, + sizeof(sts_be)); + if (rc) + return rc; + + sts = be32_to_cpu(sts_be); + if (sts & FSI2SPI_STATUS_ANY_ERROR) { + dev_err(ctx->dev, "Error with FSI2SPI interface: %08x.\n", sts); + return -EIO; + } + + return 0; +} + +static int fsi_spi_read_reg(struct fsi_spi *ctx, u32 offset, u64 *value) +{ + int rc; + __be32 cmd_be; + __be32 data_be; + u32 cmd = offset + ctx->base; + + *value = 0ULL; + + if (cmd & FSI2SPI_CMD_WRITE) + return -EINVAL; + + cmd_be = cpu_to_be32(cmd); + rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be)); + if (rc) + return rc; + + rc = fsi_spi_check_status(ctx); + if (rc) + return rc; + + rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA0, &data_be, + sizeof(data_be)); + if (rc) + return rc; + + *value |= (u64)be32_to_cpu(data_be) << 32; + + rc = fsi_device_read(ctx->fsi, FSI2SPI_DATA1, &data_be, + sizeof(data_be)); + if (rc) + return rc; + + *value |= (u64)be32_to_cpu(data_be); + dev_dbg(ctx->dev, "Read %02x[%016llx].\n", offset, *value); + + return 0; +} + +static int fsi_spi_write_reg(struct fsi_spi *ctx, u32 offset, u64 value) +{ + int rc; + __be32 cmd_be; + __be32 data_be; + u32 cmd = offset + ctx->base; + + if (cmd & FSI2SPI_CMD_WRITE) + return -EINVAL; + + dev_dbg(ctx->dev, "Write %02x[%016llx].\n", offset, value); + + data_be = cpu_to_be32(upper_32_bits(value)); + rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA0, &data_be, + sizeof(data_be)); + if (rc) + return rc; + + data_be = cpu_to_be32(lower_32_bits(value)); + rc = fsi_device_write(ctx->fsi, FSI2SPI_DATA1, &data_be, + sizeof(data_be)); + if (rc) + return rc; + + cmd_be = cpu_to_be32(cmd | FSI2SPI_CMD_WRITE); + rc = fsi_device_write(ctx->fsi, FSI2SPI_CMD, &cmd_be, sizeof(cmd_be)); + if (rc) + return rc; + + return fsi_spi_check_status(ctx); +} + +static int fsi_spi_data_in(u64 in, u8 *rx, int len) +{ + int i; + int num_bytes = min(len, 8); + + for (i = 0; i < num_bytes; ++i) + rx[i] = (u8)(in >> (8 * ((num_bytes - 1) - i))); + + return num_bytes; +} + +static int fsi_spi_data_out(u64 *out, const u8 *tx, int len) +{ + int i; + int num_bytes = min(len, 8); + u8 *out_bytes = (u8 *)out; + + /* Unused bytes of the tx data should be 0. */ + *out = 0ULL; + + for (i = 0; i < num_bytes; ++i) + out_bytes[8 - (i + 1)] = tx[i]; + + return num_bytes; +} + +static int fsi_spi_reset(struct fsi_spi *ctx) +{ + int rc; + + dev_dbg(ctx->dev, "Resetting SPI controller.\n"); + + rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, + SPI_FSI_CLOCK_CFG_RESET1); + if (rc) + return rc; + + return fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, + SPI_FSI_CLOCK_CFG_RESET2); +} + +static int fsi_spi_sequence_add(struct fsi_spi_sequence *seq, u8 val) +{ + /* + * Add the next byte of instruction to the 8-byte sequence register. + * Then decrement the counter so that the next instruction will go in + * the right place. Return the number of "slots" left in the sequence + * register. + */ + seq->data |= (u64)val << seq->bit; + seq->bit -= 8; + + return ((64 - seq->bit) / 8) - 2; +} + +static void fsi_spi_sequence_init(struct fsi_spi_sequence *seq) +{ + seq->bit = 56; + seq->data = 0ULL; +} + +static int fsi_spi_sequence_transfer(struct fsi_spi *ctx, + struct fsi_spi_sequence *seq, + struct spi_transfer *transfer) +{ + int loops; + int idx; + int rc; + u8 len = min(transfer->len, 8U); + u8 rem = transfer->len % len; + + loops = transfer->len / len; + + if (transfer->tx_buf) { + idx = fsi_spi_sequence_add(seq, + SPI_FSI_SEQUENCE_SHIFT_OUT(len)); + if (rem) + rem = SPI_FSI_SEQUENCE_SHIFT_OUT(rem); + } else if (transfer->rx_buf) { + idx = fsi_spi_sequence_add(seq, + SPI_FSI_SEQUENCE_SHIFT_IN(len)); + if (rem) + rem = SPI_FSI_SEQUENCE_SHIFT_IN(rem); + } else { + return -EINVAL; + } + + if (loops > 1) { + fsi_spi_sequence_add(seq, SPI_FSI_SEQUENCE_BRANCH(idx)); + + if (rem) + fsi_spi_sequence_add(seq, rem); + + rc = fsi_spi_write_reg(ctx, SPI_FSI_COUNTER_CFG, + SPI_FSI_COUNTER_CFG_LOOPS(loops - 1)); + if (rc) + return rc; + } + + return 0; +} + +static int fsi_spi_transfer_data(struct fsi_spi *ctx, + struct spi_transfer *transfer) +{ + int rc = 0; + u64 status = 0ULL; + + if (transfer->tx_buf) { + int nb; + int sent = 0; + u64 out = 0ULL; + const u8 *tx = transfer->tx_buf; + + while (transfer->len > sent) { + nb = fsi_spi_data_out(&out, &tx[sent], + (int)transfer->len - sent); + + rc = fsi_spi_write_reg(ctx, SPI_FSI_DATA_TX, out); + if (rc) + return rc; + + do { + rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, + &status); + if (rc) + return rc; + + if (status & SPI_FSI_STATUS_ANY_ERROR) { + rc = fsi_spi_reset(ctx); + if (rc) + return rc; + + return -EREMOTEIO; + } + } while (status & SPI_FSI_STATUS_TDR_FULL); + + sent += nb; + } + } else if (transfer->rx_buf) { + int recv = 0; + u64 in = 0ULL; + u8 *rx = transfer->rx_buf; + + while (transfer->len > recv) { + do { + rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, + &status); + if (rc) + return rc; + + if (status & SPI_FSI_STATUS_ANY_ERROR) { + rc = fsi_spi_reset(ctx); + if (rc) + return rc; + + return -EREMOTEIO; + } + } while (!(status & SPI_FSI_STATUS_RDR_FULL)); + + rc = fsi_spi_read_reg(ctx, SPI_FSI_DATA_RX, &in); + if (rc) + return rc; + + recv += fsi_spi_data_in(in, &rx[recv], + (int)transfer->len - recv); + } + } + + return 0; +} + +static int fsi_spi_transfer_init(struct fsi_spi *ctx) +{ + int rc; + bool reset = false; + unsigned long end; + u64 seq_state; + u64 clock_cfg = 0ULL; + u64 status = 0ULL; + u64 wanted_clock_cfg = SPI_FSI_CLOCK_CFG_ECC_DISABLE | + SPI_FSI_CLOCK_CFG_SCK_NO_DEL | + FIELD_PREP(SPI_FSI_CLOCK_CFG_SCK_DIV, 4); + + end = jiffies + msecs_to_jiffies(SPI_FSI_INIT_TIMEOUT_MS); + do { + if (time_after(jiffies, end)) + return -ETIMEDOUT; + + rc = fsi_spi_read_reg(ctx, SPI_FSI_STATUS, &status); + if (rc) + return rc; + + seq_state = status & SPI_FSI_STATUS_SEQ_STATE; + + if (status & (SPI_FSI_STATUS_ANY_ERROR | + SPI_FSI_STATUS_TDR_FULL | + SPI_FSI_STATUS_RDR_FULL)) { + if (reset) + return -EIO; + + rc = fsi_spi_reset(ctx); + if (rc) + return rc; + + reset = true; + continue; + } + } while (seq_state && (seq_state != SPI_FSI_STATUS_SEQ_STATE_IDLE)); + + rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg); + if (rc) + return rc; + + if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE | + SPI_FSI_CLOCK_CFG_ECC_DISABLE | + SPI_FSI_CLOCK_CFG_MODE | + SPI_FSI_CLOCK_CFG_SCK_RECV_DEL | + SPI_FSI_CLOCK_CFG_SCK_DIV)) != wanted_clock_cfg) + rc = fsi_spi_write_reg(ctx, SPI_FSI_CLOCK_CFG, + wanted_clock_cfg); + + return rc; +} + +static int fsi_spi_transfer_one_message(struct spi_controller *ctlr, + struct spi_message *mesg) +{ + int rc = 0; + u8 seq_slave = SPI_FSI_SEQUENCE_SEL_SLAVE(mesg->spi->chip_select + 1); + struct spi_transfer *transfer; + struct fsi_spi *ctx = spi_controller_get_devdata(ctlr); + + list_for_each_entry(transfer, &mesg->transfers, transfer_list) { + struct fsi_spi_sequence seq; + struct spi_transfer *next = NULL; + + /* Sequencer must do shift out (tx) first. */ + if (!transfer->tx_buf || + transfer->len > SPI_FSI_MAX_TRANSFER_SIZE) { + rc = -EINVAL; + goto error; + } + + dev_dbg(ctx->dev, "Start tx of %d bytes.\n", transfer->len); + + rc = fsi_spi_transfer_init(ctx); + if (rc < 0) + goto error; + + fsi_spi_sequence_init(&seq); + fsi_spi_sequence_add(&seq, seq_slave); + + rc = fsi_spi_sequence_transfer(ctx, &seq, transfer); + if (rc) + goto error; + + if (!list_is_last(&transfer->transfer_list, + &mesg->transfers)) { + next = list_next_entry(transfer, transfer_list); + + /* Sequencer can only do shift in (rx) after tx. */ + if (next->rx_buf) { + if (next->len > SPI_FSI_MAX_TRANSFER_SIZE) { + rc = -EINVAL; + goto error; + } + + dev_dbg(ctx->dev, "Sequence rx of %d bytes.\n", + next->len); + + rc = fsi_spi_sequence_transfer(ctx, &seq, + next); + if (rc) + goto error; + } else { + next = NULL; + } + } + + fsi_spi_sequence_add(&seq, SPI_FSI_SEQUENCE_SEL_SLAVE(0)); + + rc = fsi_spi_write_reg(ctx, SPI_FSI_SEQUENCE, seq.data); + if (rc) + goto error; + + rc = fsi_spi_transfer_data(ctx, transfer); + if (rc) + goto error; + + if (next) { + rc = fsi_spi_transfer_data(ctx, next); + if (rc) + goto error; + + transfer = next; + } + } + +error: + mesg->status = rc; + spi_finalize_current_message(ctlr); + + return rc; +} + +static size_t fsi_spi_max_transfer_size(struct spi_device *spi) +{ + return SPI_FSI_MAX_TRANSFER_SIZE; +} + +static int fsi_spi_probe(struct device *dev) +{ + int rc; + u32 root_ctrl_8; + struct device_node *np; + int num_controllers_registered = 0; + struct fsi_device *fsi = to_fsi_dev(dev); + + /* + * Check the SPI mux before attempting to probe. If the mux isn't set + * then the SPI controllers can't access their slave devices. + */ + rc = fsi_slave_read(fsi->slave, FSI_MBOX_ROOT_CTRL_8, &root_ctrl_8, + sizeof(root_ctrl_8)); + if (rc) + return rc; + + if (!root_ctrl_8) { + dev_dbg(dev, "SPI mux not set, aborting probe.\n"); + return -ENODEV; + } + + for_each_available_child_of_node(dev->of_node, np) { + u32 base; + struct fsi_spi *ctx; + struct spi_controller *ctlr; + + if (of_property_read_u32(np, "reg", &base)) + continue; + + ctlr = spi_alloc_master(dev, sizeof(*ctx)); + if (!ctlr) + break; + + ctlr->dev.of_node = np; + ctlr->num_chipselect = of_get_available_child_count(np) ?: 1; + ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX; + ctlr->max_transfer_size = fsi_spi_max_transfer_size; + ctlr->transfer_one_message = fsi_spi_transfer_one_message; + + ctx = spi_controller_get_devdata(ctlr); + ctx->dev = &ctlr->dev; + ctx->fsi = fsi; + ctx->base = base + SPI_FSI_BASE; + + rc = devm_spi_register_controller(dev, ctlr); + if (rc) + spi_controller_put(ctlr); + else + num_controllers_registered++; + } + + if (!num_controllers_registered) + return -ENODEV; + + return 0; +} + +static const struct fsi_device_id fsi_spi_ids[] = { + { FSI_ENGID_SPI, FSI_VERSION_ANY }, + { } +}; +MODULE_DEVICE_TABLE(fsi, fsi_spi_ids); + +static struct fsi_driver fsi_spi_driver = { + .id_table = fsi_spi_ids, + .drv = { + .name = "spi-fsi", + .bus = &fsi_bus_type, + .probe = fsi_spi_probe, + }, +}; +module_fsi_driver(fsi_spi_driver); + +MODULE_AUTHOR("Eddie James "); +MODULE_DESCRIPTION("FSI attached SPI controller"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From c6486eadb4feae730b68dda95fe2cc8dbe210fae Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Mon, 9 Mar 2020 16:10:03 +0100 Subject: spi: rockchip: add compatible string for px30 rk3308 rk3328 The Rockchip spi binding is updated to yaml and new models were added. The spi on px30,rk3308 and rk3328 are the same as other Rockchip based SoCs, so add compatible string for it. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200309151004.7780-1-jbx6244@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-rockchip.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c index 2cc6d9951b52..70ef63e0b6b8 100644 --- a/drivers/spi/spi-rockchip.c +++ b/drivers/spi/spi-rockchip.c @@ -843,14 +843,17 @@ static const struct dev_pm_ops rockchip_spi_pm = { }; static const struct of_device_id rockchip_spi_dt_match[] = { - { .compatible = "rockchip,rv1108-spi", }, + { .compatible = "rockchip,px30-spi", }, { .compatible = "rockchip,rk3036-spi", }, { .compatible = "rockchip,rk3066-spi", }, { .compatible = "rockchip,rk3188-spi", }, { .compatible = "rockchip,rk3228-spi", }, { .compatible = "rockchip,rk3288-spi", }, + { .compatible = "rockchip,rk3308-spi", }, + { .compatible = "rockchip,rk3328-spi", }, { .compatible = "rockchip,rk3368-spi", }, { .compatible = "rockchip,rk3399-spi", }, + { .compatible = "rockchip,rv1108-spi", }, { }, }; MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); -- cgit v1.2.3 From f3a14a3a4d9a54c665e979b1dedbbab1f7503a43 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 9 Mar 2020 18:15:37 +0100 Subject: spi: rspi: Add support for active-high chip selects All RSPI variants support setting the polarity of the SSL signal. Advertize support for active-high chip selects, and configure polarity according to the state of the flag. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200309171537.21551-1-geert+renesas@glider.be Signed-off-by: Mark Brown --- drivers/spi/spi-rspi.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c index aef05f2ac749..06192c9ea813 100644 --- a/drivers/spi/spi-rspi.c +++ b/drivers/spi/spi-rspi.c @@ -24,6 +24,7 @@ #include #include #include +#include #define RSPI_SPCR 0x00 /* Control Register */ #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ @@ -79,8 +80,7 @@ #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ /* SSLP - Slave Select Polarity Register */ -#define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ -#define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ +#define SSLP_SSLP(i) BIT(i) /* SSLi Signal Polarity Setting */ /* SPPCR - Pin Control Register */ #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ @@ -181,7 +181,9 @@ struct rspi_data { void __iomem *addr; u32 max_speed_hz; struct spi_controller *ctlr; + struct platform_device *pdev; wait_queue_head_t wait; + spinlock_t lock; /* Protects RMW-access to RSPI_SSLP */ struct clk *clk; u16 spcmd; u8 spsr; @@ -919,6 +921,29 @@ static int qspi_setup_sequencer(struct rspi_data *rspi, return 0; } +static int rspi_setup(struct spi_device *spi) +{ + struct rspi_data *rspi = spi_controller_get_devdata(spi->controller); + u8 sslp; + + if (spi->cs_gpiod) + return 0; + + pm_runtime_get_sync(&rspi->pdev->dev); + spin_lock_irq(&rspi->lock); + + sslp = rspi_read8(rspi, RSPI_SSLP); + if (spi->mode & SPI_CS_HIGH) + sslp |= SSLP_SSLP(spi->chip_select); + else + sslp &= ~SSLP_SSLP(spi->chip_select); + rspi_write8(rspi, sslp, RSPI_SSLP); + + spin_unlock_irq(&rspi->lock); + pm_runtime_put(&rspi->pdev->dev); + return 0; +} + static int rspi_prepare_message(struct spi_controller *ctlr, struct spi_message *msg) { @@ -1248,17 +1273,20 @@ static int rspi_probe(struct platform_device *pdev) goto error1; } + rspi->pdev = pdev; pm_runtime_enable(&pdev->dev); init_waitqueue_head(&rspi->wait); + spin_lock_init(&rspi->lock); ctlr->bus_num = pdev->id; + ctlr->setup = rspi_setup; ctlr->auto_runtime_pm = true; ctlr->transfer_one = ops->transfer_one; ctlr->prepare_message = rspi_prepare_message; ctlr->unprepare_message = rspi_unprepare_message; - ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST | SPI_LOOP | - ops->extra_mode_bits; + ctlr->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | + SPI_LOOP | ops->extra_mode_bits; ctlr->flags = ops->flags; ctlr->dev.of_node = pdev->dev.of_node; ctlr->use_gpio_descriptors = true; -- cgit v1.2.3 From 22ee9de1ecfb4459a9b3a959994f6ccb4a3827a4 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 10 Mar 2020 08:33:13 +0100 Subject: spi: spi-fsl-dspi: fix DMA mapping Use the correct device to request the DMA mapping. Otherwise the IOMMU doesn't get the mapping and it will generate a page fault. The error messages look like: [ 3.008452] arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xf9800000, fsynr=0x3f0022, cbfrsynra=0x828, cb=8 [ 3.020123] arm-smmu 5000000.iommu: Unhandled context fault: fsr=0x402, iova=0xf9800000, fsynr=0x3f0022, cbfrsynra=0x828, cb=8 This was tested on a custom board with a LS1028A SoC. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20200310073313.21277-1-michael@walle.cc Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 0683a3fbd48c..50e3382f0c50 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -497,14 +497,16 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) goto err_tx_channel; } - dma->tx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev, + dspi->devtype_data->dma_bufsize, &dma->tx_dma_phys, GFP_KERNEL); if (!dma->tx_dma_buf) { ret = -ENOMEM; goto err_tx_dma_buf; } - dma->rx_dma_buf = dma_alloc_coherent(dev, dspi->devtype_data->dma_bufsize, + dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev, + dspi->devtype_data->dma_bufsize, &dma->rx_dma_phys, GFP_KERNEL); if (!dma->rx_dma_buf) { ret = -ENOMEM; @@ -541,10 +543,12 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) return 0; err_slave_config: - dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma_free_coherent(dma->chan_rx->device->dev, + dspi->devtype_data->dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys); err_rx_dma_buf: - dma_free_coherent(dev, dspi->devtype_data->dma_bufsize, + dma_free_coherent(dma->chan_tx->device->dev, + dspi->devtype_data->dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys); err_tx_dma_buf: dma_release_channel(dma->chan_tx); @@ -560,20 +564,19 @@ err_tx_channel: static void dspi_release_dma(struct fsl_dspi *dspi) { struct fsl_dspi_dma *dma = dspi->dma; - struct device *dev = &dspi->pdev->dev; if (!dma) return; if (dma->chan_tx) { - dma_unmap_single(dev, dma->tx_dma_phys, + dma_unmap_single(dma->chan_tx->device->dev, dma->tx_dma_phys, dspi->devtype_data->dma_bufsize, DMA_TO_DEVICE); dma_release_channel(dma->chan_tx); } if (dma->chan_rx) { - dma_unmap_single(dev, dma->rx_dma_phys, + dma_unmap_single(dma->chan_rx->device->dev, dma->rx_dma_phys, dspi->devtype_data->dma_bufsize, DMA_FROM_DEVICE); dma_release_channel(dma->chan_rx); -- cgit v1.2.3 From caef2df1137adcea48b0902f310f4639b846e3a1 Mon Sep 17 00:00:00 2001 From: John Garry Date: Thu, 12 Mar 2020 01:35:15 +0800 Subject: spi: Stop selecting MTD_SPI_NOR for SPI_HISI_SFC_V3XX By selecting MTD_SPI_NOR for SPI_HISI_SFC_V3XX, we may introduce unmet dependencies: WARNING: unmet direct dependencies detected for MTD_SPI_NOR Depends on [m]: MTD [=m] && SPI_MASTER [=y] Selected by [y]: - SPI_HISI_SFC_V3XX [=y] && SPI [=y] && SPI_MASTER [=y] && (ARM64 && ACPI [=y] || COMPILE_TEST [=y]) && HAS_IOMEM [=y] Since MTD_SPI_NOR is only selected by SPI_HISI_SFC_V3XX for practical reasons - slave devices use the spi-nor driver, enabled by MTD_SPI_NOR - just drop it. Signed-off-by: John Garry Link: https://lore.kernel.org/r/1583948115-239907-1-git-send-email-john.garry@huawei.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8ad267cb15cd..ad79454d8584 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -299,7 +299,6 @@ config SPI_HISI_SFC_V3XX tristate "HiSilicon SPI-NOR Flash Controller for Hi16XX chipsets" depends on (ARM64 && ACPI) || COMPILE_TEST depends on HAS_IOMEM - select MTD_SPI_NOR help This enables support for HiSilicon v3xx SPI-NOR flash controller found in hi16xx chipsets. -- cgit v1.2.3 From 671c3bf50ae498dc12aef6c70abe5cfa066b1348 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Fri, 6 Mar 2020 16:50:49 +0800 Subject: spi: make spi-max-frequency optional We only need a spi-max-frequency when we specifically request a spi frequency lower than the max speed of spi host. This property is already documented as optional property and current host drivers are implemented to operate at highest speed possible when spi->max_speed_hz is 0. This patch makes spi-max-frequency an optional property so that we could just omit it to use max controller speed. Signed-off-by: Chuanhong Guo Link: https://lore.kernel.org/r/20200306085052.28258-2-gch981213@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 38b4c78df506..c0c55dc79972 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -1955,13 +1955,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, spi->mode |= SPI_CS_HIGH; /* Device speed */ - rc = of_property_read_u32(nc, "spi-max-frequency", &value); - if (rc) { - dev_err(&ctlr->dev, - "%pOF has no valid 'spi-max-frequency' property (%d)\n", nc, rc); - return rc; - } - spi->max_speed_hz = value; + if (!of_property_read_u32(nc, "spi-max-frequency", &value)) + spi->max_speed_hz = value; return 0; } -- cgit v1.2.3 From 881d1ee9fe81ff2be1b90809a07621be97404a57 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Fri, 6 Mar 2020 16:50:50 +0800 Subject: spi: add support for mediatek spi-nor controller This is a driver for mtk spi-nor controller using spi-mem interface. The same controller already has limited support provided by mtk-quadspi driver under spi-nor framework and this new driver is a replacement for the old one. Comparing to the old driver, this driver has following advantages: 1. It can handle any full-duplex spi transfer up to 6 bytes, and this is implemented using generic spi interface. 2. It take account into command opcode properly. The reading routine in this controller can only use 0x03 or 0x0b as opcode on 1-1-1 transfers, but old driver doesn't implement this properly. This driver checks supported opcode explicitly and use (1) to perform unmatched operations. 3. It properly handles SFDP reading. Old driver can't read SFDP due to the bug mentioned in (2). 4. It can do 1-2-2 and 1-4-4 fast reading on spi-nor. These two ops requires parsing SFDP, which isn't possible in old driver. And the old driver is only flagged to support 1-1-2 mode. 5. It takes advantage of the DMA feature in this controller for long reads and supports IRQ on DMA requests to free cpu cycles from polling status registers on long DMA reading. It achieves up to 17.5MB/s reading speed (1-4-4 mode) which is way faster than the old one. IRQ is implemented as optional to maintain backward compatibility. Signed-off-by: Chuanhong Guo Link: https://lore.kernel.org/r/20200306085052.28258-3-gch981213@gmail.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 10 + drivers/spi/Makefile | 1 + drivers/spi/spi-mtk-nor.c | 689 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 700 insertions(+) create mode 100644 drivers/spi/spi-mtk-nor.c (limited to 'drivers/spi') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index d6ed0c355954..8a4616de9a6d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -443,6 +443,16 @@ config SPI_MT7621 help This selects a driver for the MediaTek MT7621 SPI Controller. +config SPI_MTK_NOR + tristate "MediaTek SPI NOR controller" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + This enables support for SPI NOR controller found on MediaTek + ARM SoCs. This is a controller specifically for SPI-NOR flash. + It can perform generic SPI transfers up to 6 bytes via generic + SPI interface as well as several SPI-NOR specific instructions + via SPI MEM interface. + config SPI_NPCM_FIU tristate "Nuvoton NPCM FLASH Interface Unit" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 9b65ec5afc5e..d0aab3b777c8 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC) += spi-mpc52xx-psc.o obj-$(CONFIG_SPI_MPC52xx) += spi-mpc52xx.o obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o +obj-$(CONFIG_SPI_MTK_NOR) += spi-mtk-nor.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c new file mode 100644 index 000000000000..c15a9910549f --- /dev/null +++ b/drivers/spi/spi-mtk-nor.c @@ -0,0 +1,689 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Mediatek SPI NOR controller driver +// +// Copyright (C) 2020 Chuanhong Guo + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "mtk-spi-nor" + +#define MTK_NOR_REG_CMD 0x00 +#define MTK_NOR_CMD_WRITE BIT(4) +#define MTK_NOR_CMD_PROGRAM BIT(2) +#define MTK_NOR_CMD_READ BIT(0) +#define MTK_NOR_CMD_MASK GENMASK(5, 0) + +#define MTK_NOR_REG_PRG_CNT 0x04 +#define MTK_NOR_REG_RDATA 0x0c + +#define MTK_NOR_REG_RADR0 0x10 +#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n)) +#define MTK_NOR_REG_RADR3 0xc8 + +#define MTK_NOR_REG_WDATA 0x1c + +#define MTK_NOR_REG_PRGDATA0 0x20 +#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n)) +#define MTK_NOR_REG_PRGDATA_MAX 5 + +#define MTK_NOR_REG_SHIFT0 0x38 +#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n)) +#define MTK_NOR_REG_SHIFT_MAX 9 + +#define MTK_NOR_REG_CFG1 0x60 +#define MTK_NOR_FAST_READ BIT(0) + +#define MTK_NOR_REG_CFG2 0x64 +#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4) +#define MTK_NOR_WR_BUF_EN BIT(0) + +#define MTK_NOR_REG_PP_DATA 0x98 + +#define MTK_NOR_REG_IRQ_STAT 0xa8 +#define MTK_NOR_REG_IRQ_EN 0xac +#define MTK_NOR_IRQ_DMA BIT(7) +#define MTK_NOR_IRQ_MASK GENMASK(7, 0) + +#define MTK_NOR_REG_CFG3 0xb4 +#define MTK_NOR_DISABLE_WREN BIT(7) +#define MTK_NOR_DISABLE_SR_POLL BIT(5) + +#define MTK_NOR_REG_WP 0xc4 +#define MTK_NOR_ENABLE_SF_CMD 0x30 + +#define MTK_NOR_REG_BUSCFG 0xcc +#define MTK_NOR_4B_ADDR BIT(4) +#define MTK_NOR_QUAD_ADDR BIT(3) +#define MTK_NOR_QUAD_READ BIT(2) +#define MTK_NOR_DUAL_ADDR BIT(1) +#define MTK_NOR_DUAL_READ BIT(0) +#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0) + +#define MTK_NOR_REG_DMA_CTL 0x718 +#define MTK_NOR_DMA_START BIT(0) + +#define MTK_NOR_REG_DMA_FADR 0x71c +#define MTK_NOR_REG_DMA_DADR 0x720 +#define MTK_NOR_REG_DMA_END_DADR 0x724 + +#define MTK_NOR_PRG_MAX_SIZE 6 +// Reading DMA src/dst addresses have to be 16-byte aligned +#define MTK_NOR_DMA_ALIGN 16 +#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1) +// and we allocate a bounce buffer if destination address isn't aligned. +#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE + +// Buffered page program can do one 128-byte transfer +#define MTK_NOR_PP_SIZE 128 + +#define CLK_TO_US(sp, clkcnt) ((clkcnt) * 1000000 / sp->spi_freq) + +struct mtk_nor { + struct spi_controller *ctlr; + struct device *dev; + void __iomem *base; + u8 *buffer; + struct clk *spi_clk; + struct clk *ctlr_clk; + unsigned int spi_freq; + bool wbuf_en; + bool has_irq; + struct completion op_done; +}; + +static inline void mtk_nor_rmw(struct mtk_nor *sp, u32 reg, u32 set, u32 clr) +{ + u32 val = readl(sp->base + reg); + + val &= ~clr; + val |= set; + writel(val, sp->base + reg); +} + +static inline int mtk_nor_cmd_exec(struct mtk_nor *sp, u32 cmd, ulong clk) +{ + ulong delay = CLK_TO_US(sp, clk); + u32 reg; + int ret; + + writel(cmd, sp->base + MTK_NOR_REG_CMD); + ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CMD, reg, !(reg & cmd), + delay / 3, (delay + 1) * 200); + if (ret < 0) + dev_err(sp->dev, "command %u timeout.\n", cmd); + return ret; +} + +static void mtk_nor_set_addr(struct mtk_nor *sp, const struct spi_mem_op *op) +{ + u32 addr = op->addr.val; + int i; + + for (i = 0; i < 3; i++) { + writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR(i)); + addr >>= 8; + } + if (op->addr.nbytes == 4) { + writeb(addr & 0xff, sp->base + MTK_NOR_REG_RADR3); + mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0); + } else { + mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR); + } +} + +static bool mtk_nor_match_read(const struct spi_mem_op *op) +{ + int dummy = 0; + + if (op->dummy.buswidth) + dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth; + + if ((op->data.buswidth == 2) || (op->data.buswidth == 4)) { + if (op->addr.buswidth == 1) + return dummy == 8; + else if (op->addr.buswidth == 2) + return dummy == 4; + else if (op->addr.buswidth == 4) + return dummy == 6; + } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) { + if (op->cmd.opcode == 0x03) + return dummy == 0; + else if (op->cmd.opcode == 0x0b) + return dummy == 8; + } + return false; +} + +static int mtk_nor_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) +{ + size_t len; + + if (!op->data.nbytes) + return 0; + + if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { + if ((op->data.dir == SPI_MEM_DATA_IN) && + mtk_nor_match_read(op)) { + if ((op->addr.val & MTK_NOR_DMA_ALIGN_MASK) || + (op->data.nbytes < MTK_NOR_DMA_ALIGN)) + op->data.nbytes = 1; + else if (!((ulong)(op->data.buf.in) & + MTK_NOR_DMA_ALIGN_MASK)) + op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK; + else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE) + op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE; + return 0; + } else if (op->data.dir == SPI_MEM_DATA_OUT) { + if (op->data.nbytes >= MTK_NOR_PP_SIZE) + op->data.nbytes = MTK_NOR_PP_SIZE; + else + op->data.nbytes = 1; + return 0; + } + } + + len = MTK_NOR_PRG_MAX_SIZE - sizeof(op->cmd.opcode) - op->addr.nbytes - + op->dummy.nbytes; + if (op->data.nbytes > len) + op->data.nbytes = len; + + return 0; +} + +static bool mtk_nor_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + size_t len; + + if (op->cmd.buswidth != 1) + return false; + + if ((op->addr.nbytes == 3) || (op->addr.nbytes == 4)) { + if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) + return true; + else if (op->data.dir == SPI_MEM_DATA_OUT) + return (op->addr.buswidth == 1) && + (op->dummy.buswidth == 0) && + (op->data.buswidth == 1); + } + len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + if ((len > MTK_NOR_PRG_MAX_SIZE) || + ((op->data.nbytes) && (len == MTK_NOR_PRG_MAX_SIZE))) + return false; + return true; +} + +static void mtk_nor_setup_bus(struct mtk_nor *sp, const struct spi_mem_op *op) +{ + u32 reg = 0; + + if (op->addr.nbytes == 4) + reg |= MTK_NOR_4B_ADDR; + + if (op->data.buswidth == 4) { + reg |= MTK_NOR_QUAD_READ; + writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(4)); + if (op->addr.buswidth == 4) + reg |= MTK_NOR_QUAD_ADDR; + } else if (op->data.buswidth == 2) { + reg |= MTK_NOR_DUAL_READ; + writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA(3)); + if (op->addr.buswidth == 2) + reg |= MTK_NOR_DUAL_ADDR; + } else { + if (op->cmd.opcode == 0x0b) + mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, MTK_NOR_FAST_READ, 0); + else + mtk_nor_rmw(sp, MTK_NOR_REG_CFG1, 0, MTK_NOR_FAST_READ); + } + mtk_nor_rmw(sp, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK); +} + +static int mtk_nor_read_dma(struct mtk_nor *sp, u32 from, unsigned int length, + u8 *buffer) +{ + int ret = 0; + ulong delay; + u32 reg; + dma_addr_t dma_addr; + + dma_addr = dma_map_single(sp->dev, buffer, length, DMA_FROM_DEVICE); + if (dma_mapping_error(sp->dev, dma_addr)) { + dev_err(sp->dev, "failed to map dma buffer.\n"); + return -EINVAL; + } + + writel(from, sp->base + MTK_NOR_REG_DMA_FADR); + writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR); + writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR); + + if (sp->has_irq) { + reinit_completion(&sp->op_done); + mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0); + } + + mtk_nor_rmw(sp, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0); + + delay = CLK_TO_US(sp, (length + 5) * BITS_PER_BYTE); + + if (sp->has_irq) { + if (!wait_for_completion_timeout(&sp->op_done, + (delay + 1) * 100)) + ret = -ETIMEDOUT; + } else { + ret = readl_poll_timeout(sp->base + MTK_NOR_REG_DMA_CTL, reg, + !(reg & MTK_NOR_DMA_START), delay / 3, + (delay + 1) * 100); + } + + dma_unmap_single(sp->dev, dma_addr, length, DMA_FROM_DEVICE); + if (ret < 0) + dev_err(sp->dev, "dma read timeout.\n"); + + return ret; +} + +static int mtk_nor_read_bounce(struct mtk_nor *sp, u32 from, + unsigned int length, u8 *buffer) +{ + unsigned int rdlen; + int ret; + + if (length & MTK_NOR_DMA_ALIGN_MASK) + rdlen = (length + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK; + else + rdlen = length; + + ret = mtk_nor_read_dma(sp, from, rdlen, sp->buffer); + if (ret) + return ret; + + memcpy(buffer, sp->buffer, length); + return 0; +} + +static int mtk_nor_read_pio(struct mtk_nor *sp, const struct spi_mem_op *op) +{ + u8 *buf = op->data.buf.in; + int ret; + + ret = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE); + if (!ret) + buf[0] = readb(sp->base + MTK_NOR_REG_RDATA); + return ret; +} + +static int mtk_nor_write_buffer_enable(struct mtk_nor *sp) +{ + int ret; + u32 val; + + if (sp->wbuf_en) + return 0; + + val = readl(sp->base + MTK_NOR_REG_CFG2); + writel(val | MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2); + ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val, + val & MTK_NOR_WR_BUF_EN, 0, 10000); + if (!ret) + sp->wbuf_en = true; + return ret; +} + +static int mtk_nor_write_buffer_disable(struct mtk_nor *sp) +{ + int ret; + u32 val; + + if (!sp->wbuf_en) + return 0; + val = readl(sp->base + MTK_NOR_REG_CFG2); + writel(val & ~MTK_NOR_WR_BUF_EN, sp->base + MTK_NOR_REG_CFG2); + ret = readl_poll_timeout(sp->base + MTK_NOR_REG_CFG2, val, + !(val & MTK_NOR_WR_BUF_EN), 0, 10000); + if (!ret) + sp->wbuf_en = false; + return ret; +} + +static int mtk_nor_pp_buffered(struct mtk_nor *sp, const struct spi_mem_op *op) +{ + const u8 *buf = op->data.buf.out; + u32 val; + int ret, i; + + ret = mtk_nor_write_buffer_enable(sp); + if (ret < 0) + return ret; + + for (i = 0; i < op->data.nbytes; i += 4) { + val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 | + buf[i]; + writel(val, sp->base + MTK_NOR_REG_PP_DATA); + } + return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE, + (op->data.nbytes + 5) * BITS_PER_BYTE); +} + +static int mtk_nor_pp_unbuffered(struct mtk_nor *sp, + const struct spi_mem_op *op) +{ + const u8 *buf = op->data.buf.out; + int ret; + + ret = mtk_nor_write_buffer_disable(sp); + if (ret < 0) + return ret; + writeb(buf[0], sp->base + MTK_NOR_REG_WDATA); + return mtk_nor_cmd_exec(sp, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE); +} + +int mtk_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct mtk_nor *sp = spi_controller_get_devdata(mem->spi->master); + int ret; + + if ((op->data.nbytes == 0) || + ((op->addr.nbytes != 3) && (op->addr.nbytes != 4))) + return -ENOTSUPP; + + if (op->data.dir == SPI_MEM_DATA_OUT) { + mtk_nor_set_addr(sp, op); + writeb(op->cmd.opcode, sp->base + MTK_NOR_REG_PRGDATA0); + if (op->data.nbytes == MTK_NOR_PP_SIZE) + return mtk_nor_pp_buffered(sp, op); + return mtk_nor_pp_unbuffered(sp, op); + } + + if ((op->data.dir == SPI_MEM_DATA_IN) && mtk_nor_match_read(op)) { + ret = mtk_nor_write_buffer_disable(sp); + if (ret < 0) + return ret; + mtk_nor_setup_bus(sp, op); + if (op->data.nbytes == 1) { + mtk_nor_set_addr(sp, op); + return mtk_nor_read_pio(sp, op); + } else if (((ulong)(op->data.buf.in) & + MTK_NOR_DMA_ALIGN_MASK)) { + return mtk_nor_read_bounce(sp, op->addr.val, + op->data.nbytes, + op->data.buf.in); + } else { + return mtk_nor_read_dma(sp, op->addr.val, + op->data.nbytes, + op->data.buf.in); + } + } + + return -ENOTSUPP; +} + +static int mtk_nor_setup(struct spi_device *spi) +{ + struct mtk_nor *sp = spi_controller_get_devdata(spi->master); + + if (spi->max_speed_hz && (spi->max_speed_hz < sp->spi_freq)) { + dev_err(&spi->dev, "spi clock should be %u Hz.\n", + sp->spi_freq); + return -EINVAL; + } + spi->max_speed_hz = sp->spi_freq; + + return 0; +} + +static int mtk_nor_transfer_one_message(struct spi_controller *master, + struct spi_message *m) +{ + struct mtk_nor *sp = spi_controller_get_devdata(master); + struct spi_transfer *t = NULL; + unsigned long trx_len = 0; + int stat = 0; + int reg_offset = MTK_NOR_REG_PRGDATA_MAX; + void __iomem *reg; + const u8 *txbuf; + u8 *rxbuf; + int i; + + list_for_each_entry(t, &m->transfers, transfer_list) { + txbuf = t->tx_buf; + for (i = 0; i < t->len; i++, reg_offset--) { + reg = sp->base + MTK_NOR_REG_PRGDATA(reg_offset); + if (txbuf) + writeb(txbuf[i], reg); + else + writeb(0, reg); + } + trx_len += t->len; + } + + writel(trx_len * BITS_PER_BYTE, sp->base + MTK_NOR_REG_PRG_CNT); + + stat = mtk_nor_cmd_exec(sp, MTK_NOR_CMD_PROGRAM, + trx_len * BITS_PER_BYTE); + if (stat < 0) + goto msg_done; + + reg_offset = trx_len - 1; + list_for_each_entry(t, &m->transfers, transfer_list) { + rxbuf = t->rx_buf; + for (i = 0; i < t->len; i++, reg_offset--) { + reg = sp->base + MTK_NOR_REG_SHIFT(reg_offset); + if (rxbuf) + rxbuf[i] = readb(reg); + } + } + + m->actual_length = trx_len; +msg_done: + m->status = stat; + spi_finalize_current_message(master); + + return 0; +} + +static void mtk_nor_disable_clk(struct mtk_nor *sp) +{ + clk_disable_unprepare(sp->spi_clk); + clk_disable_unprepare(sp->ctlr_clk); +} + +static int mtk_nor_enable_clk(struct mtk_nor *sp) +{ + int ret; + + ret = clk_prepare_enable(sp->spi_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(sp->ctlr_clk); + if (ret) { + clk_disable_unprepare(sp->spi_clk); + return ret; + } + + return 0; +} + +static int mtk_nor_init(struct mtk_nor *sp) +{ + int ret; + + ret = mtk_nor_enable_clk(sp); + if (ret) + return ret; + + sp->spi_freq = clk_get_rate(sp->spi_clk); + + writel(MTK_NOR_ENABLE_SF_CMD, sp->base + MTK_NOR_REG_WP); + mtk_nor_rmw(sp, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0); + mtk_nor_rmw(sp, MTK_NOR_REG_CFG3, + MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0); + + return ret; +} + +static irqreturn_t mtk_nor_irq_handler(int irq, void *data) +{ + struct mtk_nor *sp = data; + u32 irq_status, irq_enabled; + + irq_status = readl(sp->base + MTK_NOR_REG_IRQ_STAT); + irq_enabled = readl(sp->base + MTK_NOR_REG_IRQ_EN); + // write status back to clear interrupt + writel(irq_status, sp->base + MTK_NOR_REG_IRQ_STAT); + + if (!(irq_status & irq_enabled)) + return IRQ_NONE; + + if (irq_status & MTK_NOR_IRQ_DMA) { + complete(&sp->op_done); + writel(0, sp->base + MTK_NOR_REG_IRQ_EN); + } + + return IRQ_HANDLED; +} + +static size_t mtk_max_msg_size(struct spi_device *spi) +{ + return MTK_NOR_PRG_MAX_SIZE; +} + +static const struct spi_controller_mem_ops mtk_nor_mem_ops = { + .adjust_op_size = mtk_nor_adjust_op_size, + .supports_op = mtk_nor_supports_op, + .exec_op = mtk_nor_exec_op +}; + +static const struct of_device_id mtk_nor_match[] = { + { .compatible = "mediatek,mt8173-nor" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_nor_match); + +static int mtk_nor_probe(struct platform_device *pdev) +{ + struct spi_controller *ctlr; + struct mtk_nor *sp; + void __iomem *base; + u8 *buffer; + struct clk *spi_clk, *ctlr_clk; + int ret, irq; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + spi_clk = devm_clk_get(&pdev->dev, "spi"); + if (IS_ERR(spi_clk)) + return PTR_ERR(spi_clk); + + ctlr_clk = devm_clk_get(&pdev->dev, "sf"); + if (IS_ERR(ctlr_clk)) + return PTR_ERR(ctlr_clk); + + buffer = devm_kmalloc(&pdev->dev, + MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN, + GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK) + buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) & + ~MTK_NOR_DMA_ALIGN_MASK); + + ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp)); + if (!ctlr) { + dev_err(&pdev->dev, "failed to allocate spi controller\n"); + return -ENOMEM; + } + + ctlr->bits_per_word_mask = SPI_BPW_MASK(8); + ctlr->dev.of_node = pdev->dev.of_node; + ctlr->max_message_size = mtk_max_msg_size; + ctlr->mem_ops = &mtk_nor_mem_ops; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->num_chipselect = 1; + ctlr->setup = mtk_nor_setup; + ctlr->transfer_one_message = mtk_nor_transfer_one_message; + + dev_set_drvdata(&pdev->dev, ctlr); + + sp = spi_controller_get_devdata(ctlr); + sp->base = base; + sp->buffer = buffer; + sp->has_irq = false; + sp->wbuf_en = false; + sp->ctlr = ctlr; + sp->dev = &pdev->dev; + sp->spi_clk = spi_clk; + sp->ctlr_clk = ctlr_clk; + + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0) { + dev_warn(sp->dev, "IRQ not available."); + } else { + writel(MTK_NOR_IRQ_MASK, base + MTK_NOR_REG_IRQ_STAT); + writel(0, base + MTK_NOR_REG_IRQ_EN); + ret = devm_request_irq(sp->dev, irq, mtk_nor_irq_handler, 0, + pdev->name, sp); + if (ret < 0) { + dev_warn(sp->dev, "failed to request IRQ."); + } else { + init_completion(&sp->op_done); + sp->has_irq = true; + } + } + + ret = mtk_nor_init(sp); + if (ret < 0) { + kfree(ctlr); + return ret; + } + + dev_info(&pdev->dev, "spi frequency: %d Hz\n", sp->spi_freq); + + return devm_spi_register_controller(&pdev->dev, ctlr); +} + +static int mtk_nor_remove(struct platform_device *pdev) +{ + struct spi_controller *ctlr; + struct mtk_nor *sp; + + ctlr = dev_get_drvdata(&pdev->dev); + sp = spi_controller_get_devdata(ctlr); + + mtk_nor_disable_clk(sp); + + return 0; +} + +static struct platform_driver mtk_nor_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = mtk_nor_match, + }, + .probe = mtk_nor_probe, + .remove = mtk_nor_remove, +}; + +module_platform_driver(mtk_nor_driver); + +MODULE_DESCRIPTION("Mediatek SPI NOR controller driver"); +MODULE_AUTHOR("Chuanhong Guo "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); -- cgit v1.2.3 From 1a421ebab6bb5bf65001743ba9fef48e94fb345a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 12 Mar 2020 14:31:54 +0300 Subject: spi: spi-nxp-fspi: Fix a NULL vs IS_ERR() check in probe The platform_get_resource_byname() function returns NULL on error, it doesn't return error pointers. Fixes: d166a73503ef ("spi: fspi: dynamically alloc AHB memory") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20200312113154.GC20562@mwanda Signed-off-by: Mark Brown --- drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 019f40e2917c..1ccda82da206 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -1019,8 +1019,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) /* find the resources - controller memory mapped space */ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fspi_mmap"); - if (IS_ERR(res)) { - ret = PTR_ERR(res); + if (!res) { + ret = -ENODEV; goto err_put_ctrl; } -- cgit v1.2.3 From b9dfb20eed5c7dab37d6267a985dbe16df9e4293 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 12 Mar 2020 14:31:23 +0100 Subject: spi: meson-spicc: remove unused variables Remove unused variables from spicc data struct. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20200312133131.26430-2-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 7f5680fe2568..8425e5ae1273 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -130,9 +130,7 @@ struct meson_spicc_device { u8 *rx_buf; unsigned int bytes_per_word; unsigned long tx_remain; - unsigned long txb_remain; unsigned long rx_remain; - unsigned long rxb_remain; unsigned long xfer_remain; bool is_burst_end; bool is_last_burst; -- cgit v1.2.3 From a6cda1f905b4a5442eecce94bda1e136f7e1e539 Mon Sep 17 00:00:00 2001 From: Sunny Luo Date: Thu, 12 Mar 2020 14:31:24 +0100 Subject: spi: meson-spicc: enhance output enable feature The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS signal lines through the idle state (between two transmission operation), which avoid the signals floating in unexpected state. Signed-off-by: Neil Armstrong Signed-off-by: Yixun Lan Signed-off-by: Sunny Luo Link: https://lore.kernel.org/r/20200312133131.26430-3-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 53 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 8425e5ae1273..ba70ef94a82a 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -9,11 +9,13 @@ #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -113,12 +115,23 @@ #define SPICC_DWADDR 0x24 /* Write Address of DMA */ +#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ +#define SPICC_ENH_MOSI_OEN BIT(25) +#define SPICC_ENH_CLK_OEN BIT(26) +#define SPICC_ENH_CS_OEN BIT(27) +#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28) +#define SPICC_ENH_MAIN_CLK_AO BIT(29) + #define writel_bits_relaxed(mask, val, addr) \ writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) #define SPICC_BURST_MAX 16 #define SPICC_FIFO_HALF 10 +struct meson_spicc_data { + bool has_oen; +}; + struct meson_spicc_device { struct spi_master *master; struct platform_device *pdev; @@ -126,6 +139,7 @@ struct meson_spicc_device { struct clk *core; struct spi_message *message; struct spi_transfer *xfer; + const struct meson_spicc_data *data; u8 *tx_buf; u8 *rx_buf; unsigned int bytes_per_word; @@ -136,6 +150,19 @@ struct meson_spicc_device { bool is_last_burst; }; +static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) +{ + u32 conf; + + if (!spicc->data->has_oen) + return; + + conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) | + SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; + + writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0); +} + static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) { return !!FIELD_GET(SPICC_TF, @@ -489,6 +516,13 @@ static int meson_spicc_probe(struct platform_device *pdev) spicc = spi_master_get_devdata(master); spicc->master = master; + spicc->data = of_device_get_match_data(&pdev->dev); + if (!spicc->data) { + dev_err(&pdev->dev, "failed to get match data\n"); + ret = -EINVAL; + goto out_master; + } + spicc->pdev = pdev; platform_set_drvdata(pdev, spicc); @@ -548,6 +582,8 @@ static int meson_spicc_probe(struct platform_device *pdev) else master->max_speed_hz = rate >> 2; + meson_spicc_oen_enable(spicc); + ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "spi master registration failed\n"); @@ -577,9 +613,22 @@ static int meson_spicc_remove(struct platform_device *pdev) return 0; } +static const struct meson_spicc_data meson_spicc_gx_data = { +}; + +static const struct meson_spicc_data meson_spicc_axg_data = { + .has_oen = true, +}; + static const struct of_device_id meson_spicc_of_match[] = { - { .compatible = "amlogic,meson-gx-spicc", }, - { .compatible = "amlogic,meson-axg-spicc", }, + { + .compatible = "amlogic,meson-gx-spicc", + .data = &meson_spicc_gx_data, + }, + { + .compatible = "amlogic,meson-axg-spicc", + .data = &meson_spicc_axg_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_spicc_of_match); -- cgit v1.2.3 From 3e0cf4d3fc2985beee011e9a1bbb8374fc02c0a0 Mon Sep 17 00:00:00 2001 From: Sunny Luo Date: Thu, 12 Mar 2020 14:31:25 +0100 Subject: spi: meson-spicc: add a linear clock divider support The SPICC controller in Meson-AXG SoC is capable of using a linear clock divider to reach a much fine tuned range of clocks, while the old controller only use a power of two clock divider, result at a more coarse clock range. Also convert the clock registration into Common Clock Framework. Signed-off-by: Neil Armstrong Signed-off-by: Yixun Lan Signed-off-by: Sunny Luo Link: https://lore.kernel.org/r/20200312133131.26430-4-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 1 + drivers/spi/spi-meson-spicc.c | 204 +++++++++++++++++++++++++++++++++--------- 2 files changed, 165 insertions(+), 40 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index c33ca96b44de..efce98e9844e 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -428,6 +428,7 @@ config SPI_FSL_ESPI config SPI_MESON_SPICC tristate "Amlogic Meson SPICC controller" + depends on COMMON_CLK depends on ARCH_MESON || COMPILE_TEST help This enables master mode support for the SPICC (SPI communication diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index ba70ef94a82a..bd434d9055d9 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -116,6 +116,9 @@ #define SPICC_DWADDR 0x24 /* Write Address of DMA */ #define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */ +#define SPICC_ENH_CLK_CS_DELAY_MASK GENMASK(15, 0) +#define SPICC_ENH_DATARATE_MASK GENMASK(23, 16) +#define SPICC_ENH_DATARATE_EN BIT(24) #define SPICC_ENH_MOSI_OEN BIT(25) #define SPICC_ENH_CLK_OEN BIT(26) #define SPICC_ENH_CS_OEN BIT(27) @@ -130,6 +133,7 @@ struct meson_spicc_data { bool has_oen; + bool has_enhance_clk_div; }; struct meson_spicc_device { @@ -137,6 +141,7 @@ struct meson_spicc_device { struct platform_device *pdev; void __iomem *base; struct clk *core; + struct clk *clk; struct spi_message *message; struct spi_transfer *xfer; const struct meson_spicc_data *data; @@ -322,40 +327,6 @@ static irqreturn_t meson_spicc_irq(int irq, void *data) return IRQ_HANDLED; } -static u32 meson_spicc_setup_speed(struct meson_spicc_device *spicc, u32 conf, - u32 speed) -{ - unsigned long parent, value; - unsigned int i, div; - - parent = clk_get_rate(spicc->core); - - /* Find closest inferior/equal possible speed */ - for (i = 0 ; i < 7 ; ++i) { - /* 2^(data_rate+2) */ - value = parent >> (i + 2); - - if (value <= speed) - break; - } - - /* If provided speed it lower than max divider, use max divider */ - if (i > 7) { - div = 7; - dev_warn_once(&spicc->pdev->dev, "unable to get close to speed %u\n", - speed); - } else - div = i; - - dev_dbg(&spicc->pdev->dev, "parent %lu, speed %u -> %lu (%u)\n", - parent, speed, value, div); - - conf &= ~SPICC_DATARATE_MASK; - conf |= FIELD_PREP(SPICC_DATARATE_MASK, div); - - return conf; -} - static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, struct spi_transfer *xfer) { @@ -364,9 +335,6 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, /* Read original configuration */ conf = conf_orig = readl_relaxed(spicc->base + SPICC_CONREG); - /* Select closest divider */ - conf = meson_spicc_setup_speed(spicc, conf, xfer->speed_hz); - /* Setup word width */ conf &= ~SPICC_BITLENGTH_MASK; conf |= FIELD_PREP(SPICC_BITLENGTH_MASK, @@ -375,6 +343,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, /* Ignore if unchanged */ if (conf != conf_orig) writel_relaxed(conf, spicc->base + SPICC_CONREG); + + clk_set_rate(spicc->clk, xfer->speed_hz); } static int meson_spicc_transfer_one(struct spi_master *master, @@ -481,9 +451,6 @@ static int meson_spicc_unprepare_transfer(struct spi_master *master) /* Disable all IRQs */ writel(0, spicc->base + SPICC_INTREG); - /* Disable controller */ - writel_bits_relaxed(SPICC_ENABLE, 0, spicc->base + SPICC_CONREG); - device_reset_optional(&spicc->pdev->dev); return 0; @@ -502,6 +469,152 @@ static void meson_spicc_cleanup(struct spi_device *spi) spi->controller_state = NULL; } +/* + * The Clock Mux + * x-----------------x x------------x x------\ + * |---| pow2 fixed div |---| pow2 div |----| | + * | x-----------------x x------------x | | + * src ---| | mux |-- out + * | x-----------------x x------------x | | + * |---| enh fixed div |---| enh div |0---| | + * x-----------------x x------------x x------/ + * + * Clk path for GX series: + * src -> pow2 fixed div -> pow2 div -> out + * + * Clk path for AXG series: + * src -> pow2 fixed div -> pow2 div -> mux -> out + * src -> enh fixed div -> enh div -> mux -> out + */ + +static int meson_spicc_clk_init(struct meson_spicc_device *spicc) +{ + struct device *dev = &spicc->pdev->dev; + struct clk_fixed_factor *pow2_fixed_div, *enh_fixed_div; + struct clk_divider *pow2_div, *enh_div; + struct clk_mux *mux; + struct clk_init_data init; + struct clk *clk; + struct clk_parent_data parent_data[2]; + char name[64]; + + memset(&init, 0, sizeof(init)); + memset(&parent_data, 0, sizeof(parent_data)); + + init.parent_data = parent_data; + + /* algorithm for pow2 div: rate = freq / 4 / (2 ^ N) */ + + pow2_fixed_div = devm_kzalloc(dev, sizeof(*pow2_fixed_div), GFP_KERNEL); + if (!pow2_fixed_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#pow2_fixed_div", dev_name(dev)); + init.name = name; + init.ops = &clk_fixed_factor_ops; + init.flags = 0; + parent_data[0].hw = __clk_get_hw(spicc->core); + init.num_parents = 1; + + pow2_fixed_div->mult = 1, + pow2_fixed_div->div = 4, + pow2_fixed_div->hw.init = &init; + + clk = devm_clk_register(dev, &pow2_fixed_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + pow2_div = devm_kzalloc(dev, sizeof(*pow2_div), GFP_KERNEL); + if (!pow2_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#pow2_div", dev_name(dev)); + init.name = name; + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + parent_data[0].hw = &pow2_fixed_div->hw; + init.num_parents = 1; + + pow2_div->shift = 16, + pow2_div->width = 3, + pow2_div->flags = CLK_DIVIDER_POWER_OF_TWO, + pow2_div->reg = spicc->base + SPICC_CONREG; + pow2_div->hw.init = &init; + + clk = devm_clk_register(dev, &pow2_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + if (!spicc->data->has_enhance_clk_div) { + spicc->clk = clk; + return 0; + } + + /* algorithm for enh div: rate = freq / 2 / (N + 1) */ + + enh_fixed_div = devm_kzalloc(dev, sizeof(*enh_fixed_div), GFP_KERNEL); + if (!enh_fixed_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#enh_fixed_div", dev_name(dev)); + init.name = name; + init.ops = &clk_fixed_factor_ops; + init.flags = 0; + parent_data[0].hw = __clk_get_hw(spicc->core); + init.num_parents = 1; + + enh_fixed_div->mult = 1, + enh_fixed_div->div = 2, + enh_fixed_div->hw.init = &init; + + clk = devm_clk_register(dev, &enh_fixed_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + enh_div = devm_kzalloc(dev, sizeof(*enh_div), GFP_KERNEL); + if (!enh_div) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#enh_div", dev_name(dev)); + init.name = name; + init.ops = &clk_divider_ops; + init.flags = CLK_SET_RATE_PARENT; + parent_data[0].hw = &enh_fixed_div->hw; + init.num_parents = 1; + + enh_div->shift = 16, + enh_div->width = 8, + enh_div->reg = spicc->base + SPICC_ENH_CTL0; + enh_div->hw.init = &init; + + clk = devm_clk_register(dev, &enh_div->hw); + if (WARN_ON(IS_ERR(clk))) + return PTR_ERR(clk); + + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; + + snprintf(name, sizeof(name), "%s#sel", dev_name(dev)); + init.name = name; + init.ops = &clk_mux_ops; + parent_data[0].hw = &pow2_div->hw; + parent_data[1].hw = &enh_div->hw; + init.num_parents = 2; + init.flags = CLK_SET_RATE_PARENT; + + mux->mask = 0x1, + mux->shift = 24, + mux->reg = spicc->base + SPICC_ENH_CTL0; + mux->hw.init = &init; + + spicc->clk = devm_clk_register(dev, &mux->hw); + if (WARN_ON(IS_ERR(spicc->clk))) + return PTR_ERR(spicc->clk); + + return 0; +} + static int meson_spicc_probe(struct platform_device *pdev) { struct spi_master *master; @@ -533,6 +646,10 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_master; } + /* Set master mode and enable controller */ + writel_relaxed(SPICC_ENABLE | SPICC_MODE_MASTER, + spicc->base + SPICC_CONREG); + /* Disable all IRQs */ writel_relaxed(0, spicc->base + SPICC_INTREG); @@ -584,6 +701,12 @@ static int meson_spicc_probe(struct platform_device *pdev) meson_spicc_oen_enable(spicc); + ret = meson_spicc_clk_init(spicc); + if (ret) { + dev_err(&pdev->dev, "clock registration failed\n"); + goto out_master; + } + ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "spi master registration failed\n"); @@ -618,6 +741,7 @@ static const struct meson_spicc_data meson_spicc_gx_data = { static const struct meson_spicc_data meson_spicc_axg_data = { .has_oen = true, + .has_enhance_clk_div = true, }; static const struct of_device_id meson_spicc_of_match[] = { -- cgit v1.2.3 From 3196816ff64bb3a21fbda89e7355b6b87c3f50a0 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 12 Mar 2020 14:31:26 +0100 Subject: spi: meson-spicc: support max 80MHz clock The SPICC controller in Meson-AXG is capable of running at 80M clock. The ASIC IP is improved and the clock is actually running higher than previous old SoCs. Signed-off-by: Neil Armstrong Signed-off-by: Yixun Lan Signed-off-by: Sunny Luo Link: https://lore.kernel.org/r/20200312133131.26430-5-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index bd434d9055d9..710b4e780daa 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -35,7 +35,6 @@ * to have a CS go down over the full transfer */ -#define SPICC_MAX_FREQ 30000000 #define SPICC_MAX_BURST 128 /* Register Map */ @@ -132,6 +131,7 @@ #define SPICC_FIFO_HALF 10 struct meson_spicc_data { + unsigned int max_speed_hz; bool has_oen; bool has_enhance_clk_div; }; @@ -693,11 +693,9 @@ static int meson_spicc_probe(struct platform_device *pdev) master->transfer_one = meson_spicc_transfer_one; master->use_gpio_descriptors = true; - /* Setup max rate according to the Meson GX datasheet */ - if ((rate >> 2) > SPICC_MAX_FREQ) - master->max_speed_hz = SPICC_MAX_FREQ; - else - master->max_speed_hz = rate >> 2; + /* Setup max rate according to the Meson datasheet */ + master->max_speed_hz = min_t(unsigned int, rate >> 1, + spicc->data->max_speed_hz); meson_spicc_oen_enable(spicc); @@ -737,9 +735,11 @@ static int meson_spicc_remove(struct platform_device *pdev) } static const struct meson_spicc_data meson_spicc_gx_data = { + .max_speed_hz = 30000000, }; static const struct meson_spicc_data meson_spicc_axg_data = { + .max_speed_hz = 80000000, .has_oen = true, .has_enhance_clk_div = true, }; -- cgit v1.2.3 From 8791068dab979819e01f41736953b9b2e462867b Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 12 Mar 2020 14:31:27 +0100 Subject: spi: meson-spicc: add min sclk for each compatible The G12A SPICC controller variant takes the source clock from a specific clock instead of the bus clock. The minimal clock calculus won't work with the G12A support, thus add the minimal supported clock for each variant and pass this to the SPI core. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20200312133131.26430-6-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 710b4e780daa..b5bd3a897e8f 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -132,6 +132,7 @@ struct meson_spicc_data { unsigned int max_speed_hz; + unsigned int min_speed_hz; bool has_oen; bool has_enhance_clk_div; }; @@ -685,7 +686,7 @@ static int meson_spicc_probe(struct platform_device *pdev) SPI_BPW_MASK(16) | SPI_BPW_MASK(8); master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); - master->min_speed_hz = rate >> 9; + master->min_speed_hz = spicc->data->min_speed_hz; master->setup = meson_spicc_setup; master->cleanup = meson_spicc_cleanup; master->prepare_message = meson_spicc_prepare_message; @@ -736,10 +737,12 @@ static int meson_spicc_remove(struct platform_device *pdev) static const struct meson_spicc_data meson_spicc_gx_data = { .max_speed_hz = 30000000, + .min_speed_hz = 325000, }; static const struct meson_spicc_data meson_spicc_axg_data = { .max_speed_hz = 80000000, + .min_speed_hz = 325000, .has_oen = true, .has_enhance_clk_div = true, }; -- cgit v1.2.3 From f27bff479ea3de9ca325d4f8e8c8b49a87d6b0c5 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 12 Mar 2020 14:31:28 +0100 Subject: spi: meson-spicc: setup IO line delay Now the controller can support frequencies higher than 30MHz, we need the setup the I/O line delays in regard of the SPI clock frequency. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20200312133131.26430-7-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 61 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index b5bd3a897e8f..4494a791f4a7 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -106,7 +106,21 @@ #define SPICC_SWAP_RO BIT(14) /* RX FIFO Data Swap Read-Only */ #define SPICC_SWAP_W1 BIT(15) /* RX FIFO Data Swap Write-Only */ #define SPICC_DLYCTL_RO_MASK GENMASK(20, 15) /* Delay Control Read-Only */ -#define SPICC_DLYCTL_W1_MASK GENMASK(21, 16) /* Delay Control Write-Only */ +#define SPICC_MO_DELAY_MASK GENMASK(17, 16) /* Master Output Delay */ +#define SPICC_MO_NO_DELAY 0 +#define SPICC_MO_DELAY_1_CYCLE 1 +#define SPICC_MO_DELAY_2_CYCLE 2 +#define SPICC_MO_DELAY_3_CYCLE 3 +#define SPICC_MI_DELAY_MASK GENMASK(19, 18) /* Master Input Delay */ +#define SPICC_MI_NO_DELAY 0 +#define SPICC_MI_DELAY_1_CYCLE 1 +#define SPICC_MI_DELAY_2_CYCLE 2 +#define SPICC_MI_DELAY_3_CYCLE 3 +#define SPICC_MI_CAP_DELAY_MASK GENMASK(21, 20) /* Master Capture Delay */ +#define SPICC_CAP_AHEAD_2_CYCLE 0 +#define SPICC_CAP_AHEAD_1_CYCLE 1 +#define SPICC_CAP_NO_DELAY 2 +#define SPICC_CAP_DELAY_1_CYCLE 3 #define SPICC_FIFORST_RO_MASK GENMASK(22, 21) /* FIFO Softreset Read-Only */ #define SPICC_FIFORST_W1_MASK GENMASK(23, 22) /* FIFO Softreset Write-Only */ @@ -328,6 +342,49 @@ static irqreturn_t meson_spicc_irq(int irq, void *data) return IRQ_HANDLED; } +static void meson_spicc_auto_io_delay(struct meson_spicc_device *spicc) +{ + u32 div, hz; + u32 mi_delay, cap_delay; + u32 conf; + + if (spicc->data->has_enhance_clk_div) { + div = FIELD_GET(SPICC_ENH_DATARATE_MASK, + readl_relaxed(spicc->base + SPICC_ENH_CTL0)); + div++; + div <<= 1; + } else { + div = FIELD_GET(SPICC_DATARATE_MASK, + readl_relaxed(spicc->base + SPICC_CONREG)); + div += 2; + div = 1 << div; + } + + mi_delay = SPICC_MI_NO_DELAY; + cap_delay = SPICC_CAP_AHEAD_2_CYCLE; + hz = clk_get_rate(spicc->clk); + + if (hz >= 100000000) + cap_delay = SPICC_CAP_DELAY_1_CYCLE; + else if (hz >= 80000000) + cap_delay = SPICC_CAP_NO_DELAY; + else if (hz >= 40000000) + cap_delay = SPICC_CAP_AHEAD_1_CYCLE; + else if (div >= 16) + mi_delay = SPICC_MI_DELAY_3_CYCLE; + else if (div >= 8) + mi_delay = SPICC_MI_DELAY_2_CYCLE; + else if (div >= 6) + mi_delay = SPICC_MI_DELAY_1_CYCLE; + + conf = readl_relaxed(spicc->base + SPICC_TESTREG); + conf &= ~(SPICC_MO_DELAY_MASK | SPICC_MI_DELAY_MASK + | SPICC_MI_CAP_DELAY_MASK); + conf |= FIELD_PREP(SPICC_MI_DELAY_MASK, mi_delay); + conf |= FIELD_PREP(SPICC_MI_CAP_DELAY_MASK, cap_delay); + writel_relaxed(conf, spicc->base + SPICC_TESTREG); +} + static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, struct spi_transfer *xfer) { @@ -346,6 +403,8 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, writel_relaxed(conf, spicc->base + SPICC_CONREG); clk_set_rate(spicc->clk, xfer->speed_hz); + + meson_spicc_auto_io_delay(spicc); } static int meson_spicc_transfer_one(struct spi_master *master, -- cgit v1.2.3 From 0eb707ac7dd7a4329d93d47feada6c9bb5ea8ee9 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 12 Mar 2020 14:31:29 +0100 Subject: spi: meson-spicc: adapt burst handling for G12A support The G12A SPICC controller variant has a different FIFO size and doesn't handle the RX Half interrupt the same way as GXL & AXG variants. Thus simplify the burst management and take in account a variable FIFO size. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20200312133131.26430-8-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 129 ++++++++++++++++-------------------------- 1 file changed, 50 insertions(+), 79 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 4494a791f4a7..351ccd8dd2c2 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -141,12 +141,10 @@ #define writel_bits_relaxed(mask, val, addr) \ writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) -#define SPICC_BURST_MAX 16 -#define SPICC_FIFO_HALF 10 - struct meson_spicc_data { unsigned int max_speed_hz; unsigned int min_speed_hz; + unsigned int fifo_size; bool has_oen; bool has_enhance_clk_div; }; @@ -166,8 +164,6 @@ struct meson_spicc_device { unsigned long tx_remain; unsigned long rx_remain; unsigned long xfer_remain; - bool is_burst_end; - bool is_last_burst; }; static void meson_spicc_oen_enable(struct meson_spicc_device *spicc) @@ -191,7 +187,7 @@ static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc) static inline bool meson_spicc_rxready(struct meson_spicc_device *spicc) { - return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF_EN, + return FIELD_GET(SPICC_RH | SPICC_RR | SPICC_RF, readl_relaxed(spicc->base + SPICC_STATREG)); } @@ -246,34 +242,22 @@ static inline void meson_spicc_tx(struct meson_spicc_device *spicc) spicc->base + SPICC_TXDATA); } -static inline u32 meson_spicc_setup_rx_irq(struct meson_spicc_device *spicc, - u32 irq_ctrl) +static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc) { - if (spicc->rx_remain > SPICC_FIFO_HALF) - irq_ctrl |= SPICC_RH_EN; - else - irq_ctrl |= SPICC_RR_EN; - - return irq_ctrl; -} -static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc, - unsigned int burst_len) -{ + unsigned int burst_len = min_t(unsigned int, + spicc->xfer_remain / + spicc->bytes_per_word, + spicc->data->fifo_size); /* Setup Xfer variables */ spicc->tx_remain = burst_len; spicc->rx_remain = burst_len; spicc->xfer_remain -= burst_len * spicc->bytes_per_word; - spicc->is_burst_end = false; - if (burst_len < SPICC_BURST_MAX || !spicc->xfer_remain) - spicc->is_last_burst = true; - else - spicc->is_last_burst = false; /* Setup burst length */ writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, FIELD_PREP(SPICC_BURSTLENGTH_MASK, - burst_len), + burst_len - 1), spicc->base + SPICC_CONREG); /* Fill TX FIFO */ @@ -283,61 +267,26 @@ static inline void meson_spicc_setup_burst(struct meson_spicc_device *spicc, static irqreturn_t meson_spicc_irq(int irq, void *data) { struct meson_spicc_device *spicc = (void *) data; - u32 ctrl = readl_relaxed(spicc->base + SPICC_INTREG); - u32 stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl; - ctrl &= ~(SPICC_RH_EN | SPICC_RR_EN); + writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); /* Empty RX FIFO */ meson_spicc_rx(spicc); - /* Enable TC interrupt since we transferred everything */ - if (!spicc->tx_remain && !spicc->rx_remain) { - spicc->is_burst_end = true; - - /* Enable TC interrupt */ - ctrl |= SPICC_TC_EN; - - /* Reload IRQ status */ - stat = readl_relaxed(spicc->base + SPICC_STATREG) & ctrl; - } - - /* Check transfer complete */ - if ((stat & SPICC_TC) && spicc->is_burst_end) { - unsigned int burst_len; - - /* Clear TC bit */ - writel_relaxed(SPICC_TC, spicc->base + SPICC_STATREG); - - /* Disable TC interrupt */ - ctrl &= ~SPICC_TC_EN; - - if (spicc->is_last_burst) { - /* Disable all IRQs */ - writel(0, spicc->base + SPICC_INTREG); - - spi_finalize_current_transfer(spicc->master); + if (!spicc->xfer_remain) { + /* Disable all IRQs */ + writel(0, spicc->base + SPICC_INTREG); - return IRQ_HANDLED; - } + spi_finalize_current_transfer(spicc->master); - burst_len = min_t(unsigned int, - spicc->xfer_remain / spicc->bytes_per_word, - SPICC_BURST_MAX); - - /* Setup burst */ - meson_spicc_setup_burst(spicc, burst_len); - - /* Restart burst */ - writel_bits_relaxed(SPICC_XCH, SPICC_XCH, - spicc->base + SPICC_CONREG); + return IRQ_HANDLED; } - /* Setup RX interrupt trigger */ - ctrl = meson_spicc_setup_rx_irq(spicc, ctrl); + /* Setup burst */ + meson_spicc_setup_burst(spicc); - /* Reconfigure interrupts */ - writel(ctrl, spicc->base + SPICC_INTREG); + /* Start burst */ + writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); return IRQ_HANDLED; } @@ -405,6 +354,28 @@ static void meson_spicc_setup_xfer(struct meson_spicc_device *spicc, clk_set_rate(spicc->clk, xfer->speed_hz); meson_spicc_auto_io_delay(spicc); + + writel_relaxed(0, spicc->base + SPICC_DMAREG); +} + +static void meson_spicc_reset_fifo(struct meson_spicc_device *spicc) +{ + u32 data; + + if (spicc->data->has_oen) + writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, + SPICC_ENH_MAIN_CLK_AO, + spicc->base + SPICC_ENH_CTL0); + + writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, + spicc->base + SPICC_TESTREG); + + while (meson_spicc_rxready(spicc)) + data = readl_relaxed(spicc->base + SPICC_RXDATA); + + if (spicc->data->has_oen) + writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, + spicc->base + SPICC_ENH_CTL0); } static int meson_spicc_transfer_one(struct spi_master *master, @@ -412,8 +383,6 @@ static int meson_spicc_transfer_one(struct spi_master *master, struct spi_transfer *xfer) { struct meson_spicc_device *spicc = spi_master_get_devdata(master); - unsigned int burst_len; - u32 irq = 0; /* Store current transfer */ spicc->xfer = xfer; @@ -427,22 +396,22 @@ static int meson_spicc_transfer_one(struct spi_master *master, spicc->bytes_per_word = DIV_ROUND_UP(spicc->xfer->bits_per_word, 8); + if (xfer->len % spicc->bytes_per_word) + return -EINVAL; + /* Setup transfer parameters */ meson_spicc_setup_xfer(spicc, xfer); - burst_len = min_t(unsigned int, - spicc->xfer_remain / spicc->bytes_per_word, - SPICC_BURST_MAX); - - meson_spicc_setup_burst(spicc, burst_len); + meson_spicc_reset_fifo(spicc); - irq = meson_spicc_setup_rx_irq(spicc, irq); + /* Setup burst */ + meson_spicc_setup_burst(spicc); /* Start burst */ writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); /* Enable interrupts */ - writel_relaxed(irq, spicc->base + SPICC_INTREG); + writel_relaxed(SPICC_TC_EN, spicc->base + SPICC_INTREG); return 1; } @@ -499,7 +468,7 @@ static int meson_spicc_prepare_message(struct spi_master *master, /* Setup no wait cycles by default */ writel_relaxed(0, spicc->base + SPICC_PERIODREG); - writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG); + writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); return 0; } @@ -797,11 +766,13 @@ static int meson_spicc_remove(struct platform_device *pdev) static const struct meson_spicc_data meson_spicc_gx_data = { .max_speed_hz = 30000000, .min_speed_hz = 325000, + .fifo_size = 16, }; static const struct meson_spicc_data meson_spicc_axg_data = { .max_speed_hz = 80000000, .min_speed_hz = 325000, + .fifo_size = 16, .has_oen = true, .has_enhance_clk_div = true, }; -- cgit v1.2.3 From 4e3d322058a5e5afda100005a94ec7f0bf509d43 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Thu, 12 Mar 2020 14:31:31 +0100 Subject: spi: meson-spicc: add support for Amlogic G12A Add support for the SPICC controllers on the Amlogic G12A SoCs family. The G12A SPICC controllers inherit from the AXG enhanced registers but takes an external pclk for the baud rate generator and can achieve up to 166MHz SCLK. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20200312133131.26430-10-narmstrong@baylibre.com Signed-off-by: Mark Brown --- drivers/spi/spi-meson-spicc.c | 54 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 8 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index 351ccd8dd2c2..77f7d0e0e46a 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -147,6 +147,7 @@ struct meson_spicc_data { unsigned int fifo_size; bool has_oen; bool has_enhance_clk_div; + bool has_pclk; }; struct meson_spicc_device { @@ -154,6 +155,7 @@ struct meson_spicc_device { struct platform_device *pdev; void __iomem *base; struct clk *core; + struct clk *pclk; struct clk *clk; struct spi_message *message; struct spi_transfer *xfer; @@ -514,6 +516,10 @@ static void meson_spicc_cleanup(struct spi_device *spi) * Clk path for AXG series: * src -> pow2 fixed div -> pow2 div -> mux -> out * src -> enh fixed div -> enh div -> mux -> out + * + * Clk path for G12A series: + * pclk -> pow2 fixed div -> pow2 div -> mux -> out + * pclk -> enh fixed div -> enh div -> mux -> out */ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) @@ -542,7 +548,10 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) init.name = name; init.ops = &clk_fixed_factor_ops; init.flags = 0; - parent_data[0].hw = __clk_get_hw(spicc->core); + if (spicc->data->has_pclk) + parent_data[0].hw = __clk_get_hw(spicc->pclk); + else + parent_data[0].hw = __clk_get_hw(spicc->core); init.num_parents = 1; pow2_fixed_div->mult = 1, @@ -589,7 +598,10 @@ static int meson_spicc_clk_init(struct meson_spicc_device *spicc) init.name = name; init.ops = &clk_fixed_factor_ops; init.flags = 0; - parent_data[0].hw = __clk_get_hw(spicc->core); + if (spicc->data->has_pclk) + parent_data[0].hw = __clk_get_hw(spicc->pclk); + else + parent_data[0].hw = __clk_get_hw(spicc->core); init.num_parents = 1; enh_fixed_div->mult = 1, @@ -648,7 +660,7 @@ static int meson_spicc_probe(struct platform_device *pdev) { struct spi_master *master; struct meson_spicc_device *spicc; - int ret, irq, rate; + int ret, irq; master = spi_alloc_master(&pdev->dev, sizeof(*spicc)); if (!master) { @@ -697,12 +709,26 @@ static int meson_spicc_probe(struct platform_device *pdev) goto out_master; } + if (spicc->data->has_pclk) { + spicc->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(spicc->pclk)) { + dev_err(&pdev->dev, "pclk clock request failed\n"); + ret = PTR_ERR(spicc->pclk); + goto out_master; + } + } + ret = clk_prepare_enable(spicc->core); if (ret) { dev_err(&pdev->dev, "core clock enable failed\n"); goto out_master; } - rate = clk_get_rate(spicc->core); + + ret = clk_prepare_enable(spicc->pclk); + if (ret) { + dev_err(&pdev->dev, "pclk clock enable failed\n"); + goto out_master; + } device_reset_optional(&pdev->dev); @@ -715,6 +741,7 @@ static int meson_spicc_probe(struct platform_device *pdev) SPI_BPW_MASK(8); master->flags = (SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX); master->min_speed_hz = spicc->data->min_speed_hz; + master->max_speed_hz = spicc->data->max_speed_hz; master->setup = meson_spicc_setup; master->cleanup = meson_spicc_cleanup; master->prepare_message = meson_spicc_prepare_message; @@ -722,10 +749,6 @@ static int meson_spicc_probe(struct platform_device *pdev) master->transfer_one = meson_spicc_transfer_one; master->use_gpio_descriptors = true; - /* Setup max rate according to the Meson datasheet */ - master->max_speed_hz = min_t(unsigned int, rate >> 1, - spicc->data->max_speed_hz); - meson_spicc_oen_enable(spicc); ret = meson_spicc_clk_init(spicc); @@ -744,6 +767,7 @@ static int meson_spicc_probe(struct platform_device *pdev) out_clk: clk_disable_unprepare(spicc->core); + clk_disable_unprepare(spicc->pclk); out_master: spi_master_put(master); @@ -759,6 +783,7 @@ static int meson_spicc_remove(struct platform_device *pdev) writel(0, spicc->base + SPICC_CONREG); clk_disable_unprepare(spicc->core); + clk_disable_unprepare(spicc->pclk); return 0; } @@ -777,6 +802,15 @@ static const struct meson_spicc_data meson_spicc_axg_data = { .has_enhance_clk_div = true, }; +static const struct meson_spicc_data meson_spicc_g12a_data = { + .max_speed_hz = 166666666, + .min_speed_hz = 50000, + .fifo_size = 15, + .has_oen = true, + .has_enhance_clk_div = true, + .has_pclk = true, +}; + static const struct of_device_id meson_spicc_of_match[] = { { .compatible = "amlogic,meson-gx-spicc", @@ -786,6 +820,10 @@ static const struct of_device_id meson_spicc_of_match[] = { .compatible = "amlogic,meson-axg-spicc", .data = &meson_spicc_axg_data, }, + { + .compatible = "amlogic,meson-g12a-spicc", + .data = &meson_spicc_g12a_data, + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, meson_spicc_of_match); -- cgit v1.2.3 From 5b16668e638c61a9cd4dffaa41d8b3b6f53f6b3a Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 12 Mar 2020 14:45:07 +0100 Subject: spi: acpi: remove superfluous parameter check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit to_spi_device() already checks 'dev'. No need to do it before calling it. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20200312134507.10000-1-wsa@the-dreams.de Signed-off-by: Mark Brown --- drivers/spi/spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index f6f6b2a0c81c..0996d238f61e 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -4028,7 +4028,7 @@ static struct spi_device *acpi_spi_find_device_by_adev(struct acpi_device *adev) struct device *dev; dev = bus_find_device_by_acpi_dev(&spi_bus_type, adev); - return dev ? to_spi_device(dev) : NULL; + return to_spi_device(dev); } static int acpi_spi_notify(struct notifier_block *nb, unsigned long value, -- cgit v1.2.3 From 85dadb718cc23492ef6edbc9af6c765a0c0aca66 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 17 Mar 2020 10:24:57 +0100 Subject: spi: mxs: Drop GPIO includes This driver is not using any symbols from the GPIO .h files so drop them. It was however implicitly using so include that instead. Cc: Fabio Estevam Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20200317092457.264055-1-linus.walleij@linaro.org Signed-off-by: Mark Brown --- drivers/spi/spi-mxs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-mxs.c b/drivers/spi/spi-mxs.c index dce85ee07cd0..918918a9e049 100644 --- a/drivers/spi/spi-mxs.c +++ b/drivers/spi/spi-mxs.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -32,7 +31,7 @@ #include #include #include -#include +#include #include #include #include -- cgit v1.2.3 From 4fcc7c2292def2fcb21a9644969583771c52724e Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:52 +0200 Subject: spi: spi-fsl-dspi: Don't access reserved fields in SPI_MCR The SPI_MCR_PCSIS macro assumes that the controller has a number of chip select signals equal to 6. That is not always the case, but actually is described through the driver-specific "spi-num-chipselects" device tree binding. LS1028A for example only has 4 chip selects. Don't write to the upper bits of the PCSIS field, which are reserved in the reference manual. Fixes: 349ad66c0ab0 ("spi:Add Freescale DSPI driver for Vybrid VF610 platform") Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-2-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 50e3382f0c50..6ca35881881b 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -22,7 +22,7 @@ #define SPI_MCR 0x00 #define SPI_MCR_MASTER BIT(31) -#define SPI_MCR_PCSIS (0x3F << 16) +#define SPI_MCR_PCSIS(x) ((x) << 16) #define SPI_MCR_CLR_TXF BIT(11) #define SPI_MCR_CLR_RXF BIT(10) #define SPI_MCR_XSPI BIT(3) @@ -1200,7 +1200,10 @@ static const struct regmap_config dspi_xspi_regmap_config[] = { static void dspi_init(struct fsl_dspi *dspi) { - unsigned int mcr = SPI_MCR_PCSIS; + unsigned int mcr; + + /* Set idle states for all chip select signals to high */ + mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0)); if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) mcr |= SPI_MCR_XSPI; -- cgit v1.2.3 From 671ffde1752f594c60ccdfd75378defacfaf7c83 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:53 +0200 Subject: spi: spi-fsl-dspi: Fix little endian access to PUSHR CMD and TXDATA In XSPI mode, the 32-bit PUSHR register can be written to separately: the higher 16 bits are for commands and the lower 16 bits are for data. This has nicely been hacked around, by defining a second regmap with a width of 16 bits, and effectively splitting a 32-bit register into 2 16-bit ones, from the perspective of this regmap_pushr. The problem is the assumption about the controller's endianness. If the controller is little endian (such as anything post-LS1046A), then the first 2 bytes, in the order imposed by memory layout, will actually hold the TXDATA, and the last 2 bytes will hold the CMD. So take the controller's endianness into account when performing split writes to PUSHR. The obvious and simple solution would have been to call regmap_get_val_endian(), but that is an internal regmap function and we don't want to change regmap just for this. Therefore, we just re-read the "big-endian" device tree property. Fixes: 58ba07ec79e6 ("spi: spi-fsl-dspi: Add support for XSPI mode registers") Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-3-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 6ca35881881b..be717776dd98 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -103,10 +103,6 @@ #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4) -/* Register offsets for regmap_pushr */ -#define PUSHR_CMD 0x0 -#define PUSHR_TX 0x2 - #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000) struct chip_data { @@ -240,6 +236,13 @@ struct fsl_dspi { int words_in_flight; + /* + * Offsets for CMD and TXDATA within SPI_PUSHR when accessed + * individually (in XSPI mode) + */ + int pushr_cmd; + int pushr_tx; + void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata); void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata); }; @@ -673,12 +676,12 @@ static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd) */ if (dspi->len > dspi->oper_word_size) cmd |= SPI_PUSHR_CMD_CONT; - regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); + regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd); } static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) { - regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); + regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); } static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) @@ -1259,6 +1262,7 @@ static int dspi_probe(struct platform_device *pdev) struct fsl_dspi *dspi; struct resource *res; void __iomem *base; + bool big_endian; ctlr = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); if (!ctlr) @@ -1284,6 +1288,7 @@ static int dspi_probe(struct platform_device *pdev) /* Only Coldfire uses platform data */ dspi->devtype_data = &devtype_data[MCF5441X]; + big_endian = true; } else { ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); @@ -1305,6 +1310,15 @@ static int dspi_probe(struct platform_device *pdev) ret = -EFAULT; goto out_ctlr_put; } + + big_endian = of_device_is_big_endian(np); + } + if (big_endian) { + dspi->pushr_cmd = 0; + dspi->pushr_tx = 2; + } else { + dspi->pushr_cmd = 2; + dspi->pushr_tx = 0; } if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) -- cgit v1.2.3 From a957499bd437720d082d92657b7eb5cf5a62e893 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:54 +0200 Subject: spi: spi-fsl-dspi: Fix bits-per-word acceleration in DMA mode In DMA mode, dspi_setup_accel does not get called, which results in the dspi->oper_word_size variable (which is used by dspi_dma_xfer) to not be initialized properly. Because oper_word_size is zero, a few calculations end up being incorrect, and the DMA transfer eventually times out instead of sending anything on the wire. Set up native transfers (or 8-on-16 acceleration) using dspi_setup_accel for DMA mode too. Also take the opportunity and simplify the DMA buffer handling a little bit. Fixes: 6c1c26ecd9a3 ("spi: spi-fsl-dspi: Accelerate transfers using larger word size if possible") Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-4-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 86 +++++++++++++++++----------------------------- 1 file changed, 32 insertions(+), 54 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index be717776dd98..8f2b73cc6ed7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -119,7 +119,6 @@ struct fsl_dspi_devtype_data { enum dspi_trans_mode trans_mode; u8 max_clock_factor; int fifo_size; - int dma_bufsize; }; enum { @@ -138,7 +137,6 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { [VF610] = { .trans_mode = DSPI_DMA_MODE, .max_clock_factor = 2, - .dma_bufsize = 4096, .fifo_size = 4, }, [LS1021A] = { @@ -167,19 +165,16 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { }, [LS2080A] = { .trans_mode = DSPI_DMA_MODE, - .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, [LS2085A] = { .trans_mode = DSPI_DMA_MODE, - .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, [LX2160A] = { .trans_mode = DSPI_DMA_MODE, - .dma_bufsize = 8, .max_clock_factor = 8, .fifo_size = 4, }, @@ -191,9 +186,6 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { }; struct fsl_dspi_dma { - /* Length of transfer in words of dspi->fifo_size */ - u32 curr_xfer_len; - u32 *tx_dma_buf; struct dma_chan *chan_tx; dma_addr_t tx_dma_phys; @@ -352,7 +344,7 @@ static void dspi_rx_dma_callback(void *arg) int i; if (dspi->rx) { - for (i = 0; i < dma->curr_xfer_len; i++) + for (i = 0; i < dspi->words_in_flight; i++) dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]); } @@ -366,12 +358,12 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) int time_left; int i; - for (i = 0; i < dma->curr_xfer_len; i++) + for (i = 0; i < dspi->words_in_flight; i++) dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi); dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx, dma->tx_dma_phys, - dma->curr_xfer_len * + dspi->words_in_flight * DMA_SLAVE_BUSWIDTH_4_BYTES, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -389,7 +381,7 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx, dma->rx_dma_phys, - dma->curr_xfer_len * + dspi->words_in_flight * DMA_SLAVE_BUSWIDTH_4_BYTES, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); @@ -437,46 +429,42 @@ static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi) return 0; } +static void dspi_setup_accel(struct fsl_dspi *dspi); + static int dspi_dma_xfer(struct fsl_dspi *dspi) { struct spi_message *message = dspi->cur_msg; struct device *dev = &dspi->pdev->dev; - struct fsl_dspi_dma *dma = dspi->dma; - int curr_remaining_bytes; - int bytes_per_buffer; int ret = 0; - curr_remaining_bytes = dspi->len; - bytes_per_buffer = dspi->devtype_data->dma_bufsize / - dspi->devtype_data->fifo_size; - while (curr_remaining_bytes) { - /* Check if current transfer fits the DMA buffer */ - dma->curr_xfer_len = curr_remaining_bytes / - dspi->oper_word_size; - if (dma->curr_xfer_len > bytes_per_buffer) - dma->curr_xfer_len = bytes_per_buffer; + /* + * dspi->len gets decremented by dspi_pop_tx_pushr in + * dspi_next_xfer_dma_submit + */ + while (dspi->len) { + /* Figure out operational bits-per-word for this chunk */ + dspi_setup_accel(dspi); + + dspi->words_in_flight = dspi->len / dspi->oper_word_size; + if (dspi->words_in_flight > dspi->devtype_data->fifo_size) + dspi->words_in_flight = dspi->devtype_data->fifo_size; + + message->actual_length += dspi->words_in_flight * + dspi->oper_word_size; ret = dspi_next_xfer_dma_submit(dspi); if (ret) { dev_err(dev, "DMA transfer failed\n"); - goto exit; - - } else { - const int len = dma->curr_xfer_len * - dspi->oper_word_size; - curr_remaining_bytes -= len; - message->actual_length += len; - if (curr_remaining_bytes < 0) - curr_remaining_bytes = 0; + break; } } -exit: return ret; } static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) { + int dma_bufsize = dspi->devtype_data->fifo_size * 2; struct device *dev = &dspi->pdev->dev; struct dma_slave_config cfg; struct fsl_dspi_dma *dma; @@ -501,16 +489,16 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) } dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev, - dspi->devtype_data->dma_bufsize, - &dma->tx_dma_phys, GFP_KERNEL); + dma_bufsize, &dma->tx_dma_phys, + GFP_KERNEL); if (!dma->tx_dma_buf) { ret = -ENOMEM; goto err_tx_dma_buf; } dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev, - dspi->devtype_data->dma_bufsize, - &dma->rx_dma_phys, GFP_KERNEL); + dma_bufsize, &dma->rx_dma_phys, + GFP_KERNEL); if (!dma->rx_dma_buf) { ret = -ENOMEM; goto err_rx_dma_buf; @@ -547,12 +535,10 @@ static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr) err_slave_config: dma_free_coherent(dma->chan_rx->device->dev, - dspi->devtype_data->dma_bufsize, - dma->rx_dma_buf, dma->rx_dma_phys); + dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys); err_rx_dma_buf: dma_free_coherent(dma->chan_tx->device->dev, - dspi->devtype_data->dma_bufsize, - dma->tx_dma_buf, dma->tx_dma_phys); + dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys); err_tx_dma_buf: dma_release_channel(dma->chan_tx); err_tx_channel: @@ -566,6 +552,7 @@ err_tx_channel: static void dspi_release_dma(struct fsl_dspi *dspi) { + int dma_bufsize = dspi->devtype_data->fifo_size * 2; struct fsl_dspi_dma *dma = dspi->dma; if (!dma) @@ -573,15 +560,13 @@ static void dspi_release_dma(struct fsl_dspi *dspi) if (dma->chan_tx) { dma_unmap_single(dma->chan_tx->device->dev, dma->tx_dma_phys, - dspi->devtype_data->dma_bufsize, - DMA_TO_DEVICE); + dma_bufsize, DMA_TO_DEVICE); dma_release_channel(dma->chan_tx); } if (dma->chan_rx) { dma_unmap_single(dma->chan_rx->device->dev, dma->rx_dma_phys, - dspi->devtype_data->dma_bufsize, - DMA_FROM_DEVICE); + dma_bufsize, DMA_FROM_DEVICE); dma_release_channel(dma->chan_rx); } } @@ -833,7 +818,7 @@ no_accel: dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8); /* - * Update CTAR here (code is common for both EOQ and XSPI modes). + * Update CTAR here (code is common for EOQ, XSPI and DMA modes). * We will update CTARE in the portion specific to XSPI, when we * also know the preload value (DTCP). */ @@ -960,13 +945,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF, SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF); - /* - * Static CTAR setup for modes that don't dynamically adjust it - * via dspi_setup_accel (aka for DMA) - */ - regmap_write(dspi->regmap, SPI_CTAR(0), - dspi->cur_chip->ctar_val | - SPI_FRAME_BITS(transfer->bits_per_word)); spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); -- cgit v1.2.3 From c6c1e30a789b08de2e075cbd9705e81af3d2c7cc Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:55 +0200 Subject: spi: spi-fsl-dspi: Avoid reading more data than written in EOQ mode If dspi->words_in_flight is populated with the hardware FIFO size, then in dspi_fifo_read it will attempt to read more data at the end of a buffer that is not a multiple of 16 bytes in length. It will probably time out attempting to do so. So limit the num_fifo_entries variable to the actual number of FIFO entries that is going to be used. Fixes: d59c90a2400f ("spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode") Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-5-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 8f2b73cc6ed7..51224b772680 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -739,13 +739,16 @@ static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) int num_fifo_entries = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; + if (num_fifo_entries * dspi->oper_word_size > dspi->len) + num_fifo_entries = dspi->len / dspi->oper_word_size; + dspi->words_in_flight = num_fifo_entries; /* Fill TX FIFO with as many transfers as possible */ - while (dspi->len && num_fifo_entries--) { + while (num_fifo_entries--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (dspi->len == dspi->oper_word_size || num_fifo_entries == 0) + if (num_fifo_entries == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); -- cgit v1.2.3 From 0dedf901078074d6c5b41c297fac12c02c6dc41f Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:56 +0200 Subject: spi: spi-fsl-dspi: Protect against races on dspi->words_in_flight dspi->words_in_flight is a variable populated in the *_write functions and used in the dspi_fifo_read function. It is also used in dspi_fifo_write, immediately after transmission, to update the message->actual_length variable used by higher layers such as spi-mem for integrity checking. But it may happen that the IRQ which calls dspi_fifo_read to be triggered before the updating of message->actual_length takes place. In that case, dspi_fifo_read will decrement dspi->words_in_flight to -1, and that will cause an invalid modification of message->actual_length. For that, we make the simplest fix possible: to not decrement the actual shared variable in dspi->words_in_flight from dspi_fifo_read, but actually a copy of it which is on stack. But even if dspi_fifo_read from the next IRQ does not interfere with the dspi_fifo_write of the current chunk, the *next* dspi_fifo_write still can. So we must assume that everything after the last write to the TX FIFO can be preempted by the "TX complete" IRQ, and the dspi_fifo_write function must be safe against that. This means refactoring the 2 flavours of FIFO writes (for EOQ and XSPI) such that the calculation of the number of words to be written is common and happens a priori. This way, the code for updating the message->actual_length variable works with a copy and not with the volatile dspi->words_in_flight. After some interior debate, the dspi->progress variable used for software timestamping was *not* backed up against preemption in a copy on stack. Because if preemption does occur between spi_take_timestamp_pre and spi_take_timestamp_post, there's really no point in trying to save anything. The first-in-time spi_take_timestamp_post call with a dspi->progress higher than the requested xfer->ptp_sts_word_post will trigger xfer->timestamped = true anyway and will close the deal. To understand the above a bit better, consider a transfer with xfer->ptp_sts_word_pre = xfer->ptp_sts_word_post = 3, and xfer->bits_per_words = 8 (so byte 3 needs to be timestamped). The DSPI controller timestamps in chunks of 4 bytes at a time, and preemption occurs in the middle of timestamping the first chunk: spi_take_timestamp_pre(0) . . (preemption) . . spi_take_timestamp_pre(4) . . spi_take_timestamp_post(7) . spi_take_timestamp_post(3) So the reason I'm not bothering to back up dspi->progress for that spi_take_timestamp_post(3) is that spi_take_timestamp_post(7) is going to (a) be more honest, (b) provide better accuracy and (c) already render the spi_take_timestamp_post(3) into a noop by setting xfer->timestamped = true anyway. Fixes: d59c90a2400f ("spi: spi-fsl-dspi: Convert TCFQ users to XSPI FIFO mode") Reported-by: Michael Walle Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-6-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 111 +++++++++++++++++++++------------------------ 1 file changed, 52 insertions(+), 59 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 51224b772680..f7e1e7085e31 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -669,17 +669,26 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata); } -static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) +static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words) { + int num_bytes = num_words * dspi->oper_word_size; u16 tx_cmd = dspi->tx_cmd; - if (eoq) + /* + * If the PCS needs to de-assert (i.e. we're at the end of the buffer + * and cs_change does not want the PCS to stay on), then we need a new + * PUSHR command, since this one (for the body of the buffer) + * necessarily has the CONT bit set. + * So send one word less during this go, to force a split and a command + * with a single word next time, when CONT will be unset. + */ + if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len) tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Update CTARE */ regmap_write(dspi->regmap, SPI_CTARE(0), SPI_FRAME_EBITS(dspi->oper_bits_per_word) | - SPI_CTARE_DTCP(cnt)); + SPI_CTARE_DTCP(num_words)); /* * Write the CMD FIFO entry first, and then the two @@ -688,7 +697,7 @@ static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) dspi_pushr_cmd_write(dspi, tx_cmd); /* Fill TX FIFO with as many transfers as possible */ - while (cnt--) { + while (num_words--) { u32 data = dspi_pop_tx(dspi); dspi_pushr_txdata_write(dspi, data & 0xFFFF); @@ -697,58 +706,15 @@ static void dspi_xspi_write(struct fsl_dspi *dspi, int cnt, bool eoq) } } -static void dspi_xspi_fifo_write(struct fsl_dspi *dspi) -{ - int num_fifo_entries = dspi->devtype_data->fifo_size; - int bytes_in_flight; - bool eoq = false; - - /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ - if (dspi->oper_word_size == 4) - num_fifo_entries /= 2; - - /* - * Integer division intentionally trims off odd (or non-multiple of 4) - * numbers of bytes at the end of the buffer, which will be sent next - * time using a smaller oper_word_size. - */ - dspi->words_in_flight = dspi->len / dspi->oper_word_size; - - if (dspi->words_in_flight > num_fifo_entries) - dspi->words_in_flight = num_fifo_entries; - - bytes_in_flight = dspi->words_in_flight * dspi->oper_word_size; - - /* - * If the PCS needs to de-assert (i.e. we're at the end of the buffer - * and cs_change does not want the PCS to stay on), then we need a new - * PUSHR command, since this one (for the body of the buffer) - * necessarily has the CONT bit set. - * So send one word less during this go, to force a split and a command - * with a single word next time, when CONT will be unset. - */ - if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && - bytes_in_flight == dspi->len) - eoq = true; - - dspi_xspi_write(dspi, dspi->words_in_flight, eoq); -} - -static void dspi_eoq_fifo_write(struct fsl_dspi *dspi) +static void dspi_eoq_fifo_write(struct fsl_dspi *dspi, int num_words) { - int num_fifo_entries = dspi->devtype_data->fifo_size; u16 xfer_cmd = dspi->tx_cmd; - if (num_fifo_entries * dspi->oper_word_size > dspi->len) - num_fifo_entries = dspi->len / dspi->oper_word_size; - - dspi->words_in_flight = num_fifo_entries; - /* Fill TX FIFO with as many transfers as possible */ - while (num_fifo_entries--) { + while (num_words--) { dspi->tx_cmd = xfer_cmd; /* Request EOQF for last transfer in FIFO */ - if (num_fifo_entries == 0) + if (num_words == 0) dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ; /* Write combined TX FIFO and CMD FIFO entry */ dspi_pushr_write(dspi); @@ -765,8 +731,10 @@ static u32 dspi_popr_read(struct fsl_dspi *dspi) static void dspi_fifo_read(struct fsl_dspi *dspi) { + int num_fifo_entries = dspi->words_in_flight; + /* Read one FIFO entry and push to rx buffer */ - while (dspi->words_in_flight--) + while (num_fifo_entries--) dspi_push_rx(dspi, dspi_popr_read(dspi)); } @@ -832,23 +800,48 @@ no_accel: static void dspi_fifo_write(struct fsl_dspi *dspi) { + int num_fifo_entries = dspi->devtype_data->fifo_size; struct spi_transfer *xfer = dspi->cur_transfer; struct spi_message *msg = dspi->cur_msg; - int bytes_sent; + int num_words, num_bytes; dspi_setup_accel(dspi); + /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */ + if (dspi->oper_word_size == 4) + num_fifo_entries /= 2; + + /* + * Integer division intentionally trims off odd (or non-multiple of 4) + * numbers of bytes at the end of the buffer, which will be sent next + * time using a smaller oper_word_size. + */ + num_words = dspi->len / dspi->oper_word_size; + if (num_words > num_fifo_entries) + num_words = num_fifo_entries; + + /* Update total number of bytes that were transferred */ + num_bytes = num_words * dspi->oper_word_size; + msg->actual_length += num_bytes; + dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8); + + /* + * Update shared variable for use in the next interrupt (both in + * dspi_fifo_read and in dspi_fifo_write). + */ + dspi->words_in_flight = num_words; + spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq); if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE) - dspi_eoq_fifo_write(dspi); + dspi_eoq_fifo_write(dspi, num_words); else - dspi_xspi_fifo_write(dspi); - - /* Update total number of bytes that were transferred */ - bytes_sent = dspi->words_in_flight * dspi->oper_word_size; - msg->actual_length += bytes_sent; - dspi->progress += bytes_sent / DIV_ROUND_UP(xfer->bits_per_word, 8); + dspi_xspi_fifo_write(dspi, num_words); + /* + * Everything after this point is in a potential race with the next + * interrupt, so we must never use dspi->words_in_flight again since it + * might already be modified by the next dspi_fifo_write. + */ spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); -- cgit v1.2.3 From 4f5ee75ea1718a09149460b3df993f389a67b56a Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:57 +0200 Subject: spi: spi-fsl-dspi: Replace interruptible wait queue with a simple completion Currently the driver puts the process in interruptible sleep waiting for the interrupt train to finish transfer to/from the tx_buf and rx_buf. But exiting the process with ctrl-c may make the kernel panic: the wait_event_interruptible call will return -ERESTARTSYS, which a proper driver implementation is perhaps supposed to handle, but nonetheless this one doesn't, and aborts the transfer altogether. Actually when the task is interrupted, there is still a high chance that the dspi_interrupt is still triggering. And if dspi_transfer_one_message returns execution all the way to the spi_device driver, that can free the spi_message and spi_transfer structures, leaving the interrupts to access a freed tx_buf and rx_buf. hexdump -C /dev/mtd0 00000000 00 75 68 75 0a ff ff ff ff ff ff ff ff ff ff ff |.uhu............| 00000010 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................| * ^C[ 38.495955] fsl-dspi 2120000.spi: Waiting for transfer to complete failed! [ 38.503097] spi_master spi2: failed to transfer one message from queue [ 38.509729] Unable to handle kernel paging request at virtual address ffff800095ab3377 [ 38.517676] Mem abort info: [ 38.520474] ESR = 0x96000045 [ 38.523533] EC = 0x25: DABT (current EL), IL = 32 bits [ 38.528861] SET = 0, FnV = 0 [ 38.531921] EA = 0, S1PTW = 0 [ 38.535067] Data abort info: [ 38.537952] ISV = 0, ISS = 0x00000045 [ 38.541797] CM = 0, WnR = 1 [ 38.544771] swapper pgtable: 4k pages, 48-bit VAs, pgdp=0000000082621000 [ 38.551494] [ffff800095ab3377] pgd=00000020fffff003, p4d=00000020fffff003, pud=0000000000000000 [ 38.560229] Internal error: Oops: 96000045 [#1] PREEMPT SMP [ 38.565819] Modules linked in: [ 38.568882] CPU: 0 PID: 2729 Comm: hexdump Not tainted 5.6.0-rc4-next-20200306-00052-gd8730cdc8a0b-dirty #193 [ 38.578834] Hardware name: Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier (DT) [ 38.587129] pstate: 20000085 (nzCv daIf -PAN -UAO) [ 38.591941] pc : ktime_get_real_ts64+0x3c/0x110 [ 38.596487] lr : spi_take_timestamp_pre+0x40/0x90 [ 38.601203] sp : ffff800010003d90 [ 38.604525] x29: ffff800010003d90 x28: ffff80001200e000 [ 38.609854] x27: ffff800011da9000 x26: ffff002079c40400 [ 38.615184] x25: ffff8000117fe018 x24: ffff800011daa1a0 [ 38.620513] x23: ffff800015ab3860 x22: ffff800095ab3377 [ 38.625841] x21: 000000000000146e x20: ffff8000120c3000 [ 38.631170] x19: ffff0020795f6e80 x18: ffff800011da9948 [ 38.636498] x17: 0000000000000000 x16: 0000000000000000 [ 38.641826] x15: ffff800095ab3377 x14: 0720072007200720 [ 38.647155] x13: 0720072007200765 x12: 0775076507750771 [ 38.652483] x11: 0720076d076f0772 x10: 0000000000000040 [ 38.657812] x9 : ffff8000108e2100 x8 : ffff800011dcabe8 [ 38.663139] x7 : 0000000000000000 x6 : ffff800015ab3a60 [ 38.668468] x5 : 0000000007200720 x4 : ffff800095ab3377 [ 38.673796] x3 : 0000000000000000 x2 : 0000000000000ab0 [ 38.679125] x1 : ffff800011daa000 x0 : 0000000000000026 [ 38.684454] Call trace: [ 38.686905] ktime_get_real_ts64+0x3c/0x110 [ 38.691100] spi_take_timestamp_pre+0x40/0x90 [ 38.695470] dspi_fifo_write+0x58/0x2c0 [ 38.699315] dspi_interrupt+0xbc/0xd0 [ 38.702987] __handle_irq_event_percpu+0x78/0x2c0 [ 38.707706] handle_irq_event_percpu+0x3c/0x90 [ 38.712161] handle_irq_event+0x4c/0xd0 [ 38.716008] handle_fasteoi_irq+0xbc/0x170 [ 38.720115] generic_handle_irq+0x2c/0x40 [ 38.724135] __handle_domain_irq+0x68/0xc0 [ 38.728243] gic_handle_irq+0xc8/0x160 [ 38.732000] el1_irq+0xb8/0x180 [ 38.735149] spi_nor_spimem_read_data+0xe0/0x140 [ 38.739779] spi_nor_read+0xc4/0x120 [ 38.743364] mtd_read_oob+0xa8/0xc0 [ 38.746860] mtd_read+0x4c/0x80 [ 38.750007] mtdchar_read+0x108/0x2a0 [ 38.753679] __vfs_read+0x20/0x50 [ 38.757002] vfs_read+0xa4/0x190 [ 38.760237] ksys_read+0x6c/0xf0 [ 38.763471] __arm64_sys_read+0x20/0x30 [ 38.767319] el0_svc_common.constprop.3+0x90/0x160 [ 38.772125] do_el0_svc+0x28/0x90 [ 38.775449] el0_sync_handler+0x118/0x190 [ 38.779468] el0_sync+0x140/0x180 [ 38.782793] Code: 91000294 1400000f d50339bf f9405e80 (f90002c0) [ 38.788910] ---[ end trace 55da560db4d6bef7 ]--- [ 38.793540] Kernel panic - not syncing: Fatal exception in interrupt [ 38.799914] SMP: stopping secondary CPUs [ 38.803849] Kernel Offset: disabled [ 38.807344] CPU features: 0x10002,20006008 [ 38.811451] Memory Limit: none [ 38.814513] ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- So it is clear that the "interruptible" part isn't handled correctly. When the process receives a signal, one could either attempt a clean abort (which appears to be difficult with this hardware) or just keep restarting the sleep until the wait queue really completes. But checking in a loop for -ERESTARTSYS is a bit too complicated for this driver, so just make the sleep uninterruptible, to avoid all that nonsense. The wait queue was actually restructured as a completion, after polling other drivers for the most "popular" approach. Fixes: 349ad66c0ab0 ("spi:Add Freescale DSPI driver for Vybrid VF610 platform") Reported-by: Michael Walle Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-7-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index f7e1e7085e31..b65c21d048f9 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -218,8 +218,7 @@ struct fsl_dspi { u16 tx_cmd; const struct fsl_dspi_devtype_data *devtype_data; - wait_queue_head_t waitq; - u32 waitflags; + struct completion xfer_done; struct fsl_dspi_dma *dma; @@ -890,10 +889,8 @@ static irqreturn_t dspi_interrupt(int irq, void *dev_id) if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))) return IRQ_NONE; - if (dspi_rxtx(dspi) == 0) { - dspi->waitflags = 1; - wake_up_interruptible(&dspi->waitq); - } + if (dspi_rxtx(dspi) == 0) + complete(&dspi->xfer_done); return IRQ_HANDLED; } @@ -973,13 +970,9 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, status = dspi_poll(dspi); } while (status == -EINPROGRESS); } else if (trans_mode != DSPI_DMA_MODE) { - status = wait_event_interruptible(dspi->waitq, - dspi->waitflags); - dspi->waitflags = 0; + wait_for_completion(&dspi->xfer_done); + reinit_completion(&dspi->xfer_done); } - if (status) - dev_err(&dspi->pdev->dev, - "Waiting for transfer to complete failed!\n"); spi_transfer_delay_exec(transfer); } @@ -1359,7 +1352,7 @@ static int dspi_probe(struct platform_device *pdev) goto out_clk_put; } - init_waitqueue_head(&dspi->waitq); + init_completion(&dspi->xfer_done); poll_mode: -- cgit v1.2.3 From 3d6224e63be39ff26cf416492cb3923cd3d07dd0 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:58 +0200 Subject: spi: spi-fsl-dspi: Avoid NULL pointer in dspi_slave_abort for non-DMA mode The driver does not create the dspi->dma structure unless operating in DSPI_DMA_MODE, so it makes sense to check for that. Fixes: f4b323905d8b ("spi: Introduce dspi_slave_abort() function for NXP's dspi SPI driver") Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-8-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index b65c21d048f9..81e22b6eadc7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -1192,8 +1192,10 @@ static int dspi_slave_abort(struct spi_master *master) * Terminate all pending DMA transactions for the SPI working * in SLAVE mode. */ - dmaengine_terminate_sync(dspi->dma->chan_rx); - dmaengine_terminate_sync(dspi->dma->chan_tx); + if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { + dmaengine_terminate_sync(dspi->dma->chan_rx); + dmaengine_terminate_sync(dspi->dma->chan_tx); + } /* Clear the internal DSPI RX and TX FIFO buffers */ regmap_update_bits(dspi->regmap, SPI_MCR, -- cgit v1.2.3 From 826b3a6a34619b934cdc33eeb961fcb99ce92c09 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:15:59 +0200 Subject: spi: spi-fsl-dspi: Fix interrupt-less DMA mode taking an XSPI code path Interrupts are not necessary for DMA functionality, since the completion event is provided by the DMA driver. But if the driver fails to request the IRQ defined in the device tree, it will call dspi_poll which would make the driver hang waiting for data to become available in the RX FIFO. Fixes: c55be3059159 ("spi: spi-fsl-dspi: Use poll mode in case the platform IRQ is missing") Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-9-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 81e22b6eadc7..fcc6f20b6631 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -965,13 +965,15 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, goto out; } - if (!dspi->irq) { - do { - status = dspi_poll(dspi); - } while (status == -EINPROGRESS); - } else if (trans_mode != DSPI_DMA_MODE) { - wait_for_completion(&dspi->xfer_done); - reinit_completion(&dspi->xfer_done); + if (trans_mode != DSPI_DMA_MODE) { + if (dspi->irq) { + wait_for_completion(&dspi->xfer_done); + reinit_completion(&dspi->xfer_done); + } else { + do { + status = dspi_poll(dspi); + } while (status == -EINPROGRESS); + } } spi_transfer_delay_exec(transfer); -- cgit v1.2.3 From 5b342c5ab7cde6c543faf46e30bb501feaa2e435 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:16:00 +0200 Subject: spi: spi-fsl-dspi: Move invariant configs out of dspi_transfer_one_message The operating mode (DMA, XSPI, EOQ) is not going to change across the lifetime of the device. So it makes no sense to keep writing to SPI_RSER on each message. Move this configuration to dspi_init instead. Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-10-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 55 ++++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 26 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index fcc6f20b6631..5873752a091e 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -900,7 +900,6 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, { struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr); struct spi_device *spi = message->spi; - enum dspi_trans_mode trans_mode; struct spi_transfer *transfer; int status = 0; @@ -942,30 +941,11 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer, dspi->progress, !dspi->irq); - trans_mode = dspi->devtype_data->trans_mode; - switch (trans_mode) { - case DSPI_EOQ_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); - dspi_fifo_write(dspi); - break; - case DSPI_XSPI_MODE: - regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); - dspi_fifo_write(dspi); - break; - case DSPI_DMA_MODE: - regmap_write(dspi->regmap, SPI_RSER, - SPI_RSER_TFFFE | SPI_RSER_TFFFD | - SPI_RSER_RFDFE | SPI_RSER_RFDFD); + if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) { status = dspi_dma_xfer(dspi); - break; - default: - dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", - trans_mode); - status = -EINVAL; - goto out; - } + } else { + dspi_fifo_write(dspi); - if (trans_mode != DSPI_DMA_MODE) { if (dspi->irq) { wait_for_completion(&dspi->xfer_done); reinit_completion(&dspi->xfer_done); @@ -975,11 +955,12 @@ static int dspi_transfer_one_message(struct spi_controller *ctlr, } while (status == -EINPROGRESS); } } + if (status) + break; spi_transfer_delay_exec(transfer); } -out: message->status = status; spi_finalize_current_message(ctlr); @@ -1170,7 +1151,7 @@ static const struct regmap_config dspi_xspi_regmap_config[] = { }, }; -static void dspi_init(struct fsl_dspi *dspi) +static int dspi_init(struct fsl_dspi *dspi) { unsigned int mcr; @@ -1184,6 +1165,26 @@ static void dspi_init(struct fsl_dspi *dspi) regmap_write(dspi->regmap, SPI_MCR, mcr); regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR); + + switch (dspi->devtype_data->trans_mode) { + case DSPI_EOQ_MODE: + regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE); + break; + case DSPI_XSPI_MODE: + regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE); + break; + case DSPI_DMA_MODE: + regmap_write(dspi->regmap, SPI_RSER, + SPI_RSER_TFFFE | SPI_RSER_TFFFD | + SPI_RSER_RFDFE | SPI_RSER_RFDFD); + break; + default: + dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n", + dspi->devtype_data->trans_mode); + return -EINVAL; + } + + return 0; } static int dspi_slave_abort(struct spi_master *master) @@ -1339,7 +1340,9 @@ static int dspi_probe(struct platform_device *pdev) if (ret) goto out_ctlr_put; - dspi_init(dspi); + ret = dspi_init(dspi); + if (ret) + goto out_clk_put; dspi->irq = platform_get_irq(pdev, 0); if (dspi->irq <= 0) { -- cgit v1.2.3 From 138f56ef914b30087c560492e5997f17d494d043 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 18 Mar 2020 02:16:01 +0200 Subject: spi: spi-fsl-dspi: Add support for LS1028A This is similar to the DSPI instantiation on LS1028A, except that: - The A-011218 erratum has been fixed, so DMA works - The endianness is different, which has implications on XSPI mode Some benchmarking with the following command: spidev_test --device /dev/spidev2.0 --bpw 8 --size 256 --cpha --iter 10000000 --speed 20000000 shows that in DMA mode, it can achieve around 2400 kbps, and in XSPI mode, the same command goes up to 4700 kbps. This is somewhat to be expected, since the DMA buffer size is extremely small at 8 bytes, the winner becomes whomever can prepare the buffers for transmission quicker, and DMA mode has higher overhead there. So XSPI FIFO mode has been chosen as the operating mode for this chip. Signed-off-by: Vladimir Oltean Tested-by: Michael Walle Link: https://lore.kernel.org/r/20200318001603.9650-11-olteanv@gmail.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-dspi.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 5873752a091e..50e41f66a2d7 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -124,6 +124,7 @@ struct fsl_dspi_devtype_data { enum { LS1021A, LS1012A, + LS1028A, LS1043A, LS1046A, LS2080A, @@ -151,6 +152,11 @@ static const struct fsl_dspi_devtype_data devtype_data[] = { .max_clock_factor = 8, .fifo_size = 16, }, + [LS1028A] = { + .trans_mode = DSPI_XSPI_MODE, + .max_clock_factor = 8, + .fifo_size = 4, + }, [LS1043A] = { /* Has A-011218 DMA erratum */ .trans_mode = DSPI_XSPI_MODE, @@ -1050,6 +1056,9 @@ static const struct of_device_id fsl_dspi_dt_ids[] = { }, { .compatible = "fsl,ls1012a-dspi", .data = &devtype_data[LS1012A], + }, { + .compatible = "fsl,ls1028a-dspi", + .data = &devtype_data[LS1028A], }, { .compatible = "fsl,ls1043a-dspi", .data = &devtype_data[LS1043A], -- cgit v1.2.3 From c528ecfbef040ba0d6672d843e7502cb326bcb4d Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 20 Mar 2020 06:51:01 +0000 Subject: spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses This feature should not be enabled in release but can be useful for developers who need to monitor register accesses at some specific places. Helped me identify a bug in u-boot, by comparing the register accesses from the linux driver with the ones from its u-boot variant. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200320065058.891221-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown --- drivers/spi/atmel-quadspi.c | 119 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 97 insertions(+), 22 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index 13def7f78b9e..cb44d1e169aa 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -173,6 +173,81 @@ static const struct atmel_qspi_mode atmel_qspi_modes[] = { { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, }; +#ifdef VERBOSE_DEBUG +static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) +{ + switch (offset) { + case QSPI_CR: + return "CR"; + case QSPI_MR: + return "MR"; + case QSPI_RD: + return "MR"; + case QSPI_TD: + return "TD"; + case QSPI_SR: + return "SR"; + case QSPI_IER: + return "IER"; + case QSPI_IDR: + return "IDR"; + case QSPI_IMR: + return "IMR"; + case QSPI_SCR: + return "SCR"; + case QSPI_IAR: + return "IAR"; + case QSPI_ICR: + return "ICR/WICR"; + case QSPI_IFR: + return "IFR"; + case QSPI_RICR: + return "RICR"; + case QSPI_SMR: + return "SMR"; + case QSPI_SKR: + return "SKR"; + case QSPI_WPMR: + return "WPMR"; + case QSPI_WPSR: + return "WPSR"; + case QSPI_VERSION: + return "VERSION"; + default: + snprintf(tmp, sz, "0x%02x", offset); + break; + } + + return tmp; +} +#endif /* VERBOSE_DEBUG */ + +static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset) +{ + u32 value = readl_relaxed(aq->regs + offset); + +#ifdef VERBOSE_DEBUG + char tmp[8]; + + dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value, + atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); +#endif /* VERBOSE_DEBUG */ + + return value; +} + +static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) +{ +#ifdef VERBOSE_DEBUG + char tmp[8]; + + dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value, + atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); +#endif /* VERBOSE_DEBUG */ + + writel_relaxed(value, aq->regs + offset); +} + static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, const struct atmel_qspi_mode *mode) { @@ -293,32 +368,32 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, * Serial Memory Mode (SMM). */ if (aq->mr != QSPI_MR_SMM) { - writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR); + atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); aq->mr = QSPI_MR_SMM; } /* Clear pending interrupts */ - (void)readl_relaxed(aq->regs + QSPI_SR); + (void)atmel_qspi_read(aq, QSPI_SR); if (aq->caps->has_ricr) { if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN) ifr |= QSPI_IFR_APBTFRTYP_READ; /* Set QSPI Instruction Frame registers */ - writel_relaxed(iar, aq->regs + QSPI_IAR); + atmel_qspi_write(iar, aq, QSPI_IAR); if (op->data.dir == SPI_MEM_DATA_IN) - writel_relaxed(icr, aq->regs + QSPI_RICR); + atmel_qspi_write(icr, aq, QSPI_RICR); else - writel_relaxed(icr, aq->regs + QSPI_WICR); - writel_relaxed(ifr, aq->regs + QSPI_IFR); + atmel_qspi_write(icr, aq, QSPI_WICR); + atmel_qspi_write(ifr, aq, QSPI_IFR); } else { if (op->data.dir == SPI_MEM_DATA_OUT) ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; /* Set QSPI Instruction Frame registers */ - writel_relaxed(iar, aq->regs + QSPI_IAR); - writel_relaxed(icr, aq->regs + QSPI_ICR); - writel_relaxed(ifr, aq->regs + QSPI_IFR); + atmel_qspi_write(iar, aq, QSPI_IAR); + atmel_qspi_write(icr, aq, QSPI_ICR); + atmel_qspi_write(ifr, aq, QSPI_IFR); } return 0; @@ -345,7 +420,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) /* Skip to the final steps if there is no data */ if (op->data.nbytes) { /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ - (void)readl_relaxed(aq->regs + QSPI_IFR); + (void)atmel_qspi_read(aq, QSPI_IFR); /* Send/Receive data */ if (op->data.dir == SPI_MEM_DATA_IN) @@ -356,22 +431,22 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) op->data.nbytes); /* Release the chip-select */ - writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); } /* Poll INSTRuction End status */ - sr = readl_relaxed(aq->regs + QSPI_SR); + sr = atmel_qspi_read(aq, QSPI_SR); if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED) return err; /* Wait for INSTRuction End interrupt */ reinit_completion(&aq->cmd_completion); aq->pending = sr & QSPI_SR_CMD_COMPLETED; - writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER); + atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER); if (!wait_for_completion_timeout(&aq->cmd_completion, msecs_to_jiffies(1000))) err = -ETIMEDOUT; - writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR); + atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR); return err; } @@ -410,7 +485,7 @@ static int atmel_qspi_setup(struct spi_device *spi) scbr--; aq->scr = QSPI_SCR_SCBR(scbr); - writel_relaxed(aq->scr, aq->regs + QSPI_SCR); + atmel_qspi_write(aq->scr, aq, QSPI_SCR); return 0; } @@ -418,14 +493,14 @@ static int atmel_qspi_setup(struct spi_device *spi) static void atmel_qspi_init(struct atmel_qspi *aq) { /* Reset the QSPI controller */ - writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); /* Set the QSPI controller by default in Serial Memory Mode */ - writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR); + atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); aq->mr = QSPI_MR_SMM; /* Enable the QSPI controller */ - writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); } static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) @@ -433,8 +508,8 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) struct atmel_qspi *aq = dev_id; u32 status, mask, pending; - status = readl_relaxed(aq->regs + QSPI_SR); - mask = readl_relaxed(aq->regs + QSPI_IMR); + status = atmel_qspi_read(aq, QSPI_SR); + mask = atmel_qspi_read(aq, QSPI_IMR); pending = status & mask; if (!pending) @@ -569,7 +644,7 @@ static int atmel_qspi_remove(struct platform_device *pdev) struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); spi_unregister_controller(ctrl); - writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); clk_disable_unprepare(aq->qspick); clk_disable_unprepare(aq->pclk); return 0; @@ -596,7 +671,7 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev) atmel_qspi_init(aq); - writel_relaxed(aq->scr, aq->regs + QSPI_SCR); + atmel_qspi_write(aq->scr, aq, QSPI_SCR); return 0; } -- cgit v1.2.3 From 1c52be8bed83e1a67b47295177b355d0f58c1372 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 20 Mar 2020 14:44:17 +0100 Subject: spi: stm32: Fix comments compilation warnings Fix all functions and structure descriptions to have the driver warning free when built with W=1. Signed-off-by: Alain Volmat Reviewed-by: Amelie Delaunay Link: https://lore.kernel.org/r/1584711857-9162-1-git-send-email-alain.volmat@st.com Signed-off-by: Mark Brown --- drivers/spi/spi-stm32.c | 62 +++++++++++++++++++++++++++++++++++-------------- 1 file changed, 45 insertions(+), 17 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c index e041f9c4ec47..44ac6eb3298d 100644 --- a/drivers/spi/spi-stm32.c +++ b/drivers/spi/spi-stm32.c @@ -175,7 +175,7 @@ #define SPI_DMA_MIN_BYTES 16 /** - * stm32_spi_reg - stm32 SPI register & bitfield desc + * struct stm32_spi_reg - stm32 SPI register & bitfield desc * @reg: register offset * @mask: bitfield mask * @shift: left shift @@ -187,16 +187,16 @@ struct stm32_spi_reg { }; /** - * stm32_spi_regspec - stm32 registers definition, compatible dependent data - * en: enable register and SPI enable bit - * dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit - * dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit - * cpol: clock polarity register and polarity bit - * cpha: clock phase register and phase bit - * lsb_first: LSB transmitted first register and bit - * br: baud rate register and bitfields - * rx: SPI RX data register - * tx: SPI TX data register + * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data + * @en: enable register and SPI enable bit + * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit + * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit + * @cpol: clock polarity register and polarity bit + * @cpha: clock phase register and phase bit + * @lsb_first: LSB transmitted first register and bit + * @br: baud rate register and bitfields + * @rx: SPI RX data register + * @tx: SPI TX data register */ struct stm32_spi_regspec { const struct stm32_spi_reg en; @@ -213,7 +213,7 @@ struct stm32_spi_regspec { struct stm32_spi; /** - * stm32_spi_cfg - stm32 compatible configuration data + * struct stm32_spi_cfg - stm32 compatible configuration data * @regs: registers descriptions * @get_fifo_size: routine to get fifo size * @get_bpw_mask: routine to get bits per word mask @@ -223,13 +223,13 @@ struct stm32_spi; * @set_mode: routine to configure registers to desired mode * @set_data_idleness: optional routine to configure registers to desired idle * time between frames (if driver has this functionality) - * set_number_of_data: optional routine to configure registers to desired + * @set_number_of_data: optional routine to configure registers to desired * number of data (if driver has this functionality) * @can_dma: routine to determine if the transfer is eligible for DMA use * @transfer_one_dma_start: routine to start transfer a single spi_transfer * using DMA - * @dma_rx cb: routine to call after DMA RX channel operation is complete - * @dma_tx cb: routine to call after DMA TX channel operation is complete + * @dma_rx_cb: routine to call after DMA RX channel operation is complete + * @dma_tx_cb: routine to call after DMA TX channel operation is complete * @transfer_one_irq: routine to configure interrupts for driver * @irq_handler_event: Interrupt handler for SPI controller events * @irq_handler_thread: thread of interrupt handler for SPI controller @@ -587,6 +587,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi) /** * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register * @spi: pointer to the spi controller data structure + * @flush: boolean indicating that FIFO should be flushed * * Write in rx_buf depends on remaining bytes to avoid to write beyond * rx_buf end. @@ -756,6 +757,9 @@ static void stm32h7_spi_disable(struct stm32_spi *spi) /** * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use + * @master: controller master interface + * @spi_dev: pointer to the spi device + * @transfer: pointer to spi transfer * * If driver has fifo and the current transfer size is greater than fifo size, * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes. @@ -974,6 +978,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) /** * stm32_spi_prepare_msg - set up the controller to transfer a single message + * @master: controller master interface + * @msg: pointer to spi message */ static int stm32_spi_prepare_msg(struct spi_master *master, struct spi_message *msg) @@ -1026,6 +1032,7 @@ static int stm32_spi_prepare_msg(struct spi_master *master, /** * stm32f4_spi_dma_tx_cb - dma callback + * @data: pointer to the spi controller data structure * * DMA callback is called when the transfer is complete for DMA TX channel. */ @@ -1041,6 +1048,7 @@ static void stm32f4_spi_dma_tx_cb(void *data) /** * stm32f4_spi_dma_rx_cb - dma callback + * @data: pointer to the spi controller data structure * * DMA callback is called when the transfer is complete for DMA RX channel. */ @@ -1054,6 +1062,7 @@ static void stm32f4_spi_dma_rx_cb(void *data) /** * stm32h7_spi_dma_cb - dma callback + * @data: pointer to the spi controller data structure * * DMA callback is called when the transfer is complete or when an error * occurs. If the transfer is complete, EOT flag is raised. @@ -1079,6 +1088,9 @@ static void stm32h7_spi_dma_cb(void *data) /** * stm32_spi_dma_config - configure dma slave channel depending on current * transfer bits_per_word. + * @spi: pointer to the spi controller data structure + * @dma_conf: pointer to the dma_slave_config structure + * @dir: direction of the dma transfer */ static void stm32_spi_dma_config(struct stm32_spi *spi, struct dma_slave_config *dma_conf, @@ -1126,6 +1138,7 @@ static void stm32_spi_dma_config(struct stm32_spi *spi, /** * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using * interrupts + * @spi: pointer to the spi controller data structure * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. @@ -1166,6 +1179,7 @@ static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) /** * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using * interrupts + * @spi: pointer to the spi controller data structure * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. @@ -1207,6 +1221,7 @@ static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) /** * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start * transfer using DMA + * @spi: pointer to the spi controller data structure */ static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) { @@ -1227,6 +1242,7 @@ static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) /** * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start * transfer using DMA + * @spi: pointer to the spi controller data structure */ static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) { @@ -1243,6 +1259,8 @@ static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) /** * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA + * @spi: pointer to the spi controller data structure + * @xfer: pointer to the spi_transfer structure * * It must returns 0 if the transfer is finished or 1 if the transfer is still * in progress. @@ -1405,7 +1423,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) /** * stm32_spi_communication_type - return transfer communication type * @spi_dev: pointer to the spi device - * transfer: pointer to spi transfer + * @transfer: pointer to spi transfer */ static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev, struct spi_transfer *transfer) @@ -1522,7 +1540,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) /** * stm32h7_spi_number_of_data - configure number of data at current transfer * @spi: pointer to the spi controller data structure - * @len: transfer length + * @nb_words: transfer length (in words) */ static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) { @@ -1546,6 +1564,9 @@ static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) * stm32_spi_transfer_one_setup - common setup to transfer a single * spi_transfer either using DMA or * interrupts. + * @spi: pointer to the spi controller data structure + * @spi_dev: pointer to the spi device + * @transfer: pointer to spi transfer */ static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, struct spi_device *spi_dev, @@ -1625,6 +1646,9 @@ out: /** * stm32_spi_transfer_one - transfer a single spi_transfer + * @master: controller master interface + * @spi_dev: pointer to the spi device + * @transfer: pointer to spi transfer * * It must return 0 if the transfer is finished or 1 if the transfer is still * in progress. @@ -1658,6 +1682,8 @@ static int stm32_spi_transfer_one(struct spi_master *master, /** * stm32_spi_unprepare_msg - relax the hardware + * @master: controller master interface + * @msg: pointer to the spi message */ static int stm32_spi_unprepare_msg(struct spi_master *master, struct spi_message *msg) @@ -1671,6 +1697,7 @@ static int stm32_spi_unprepare_msg(struct spi_master *master, /** * stm32f4_spi_config - Configure SPI controller as SPI master + * @spi: pointer to the spi controller data structure */ static int stm32f4_spi_config(struct stm32_spi *spi) { @@ -1701,6 +1728,7 @@ static int stm32f4_spi_config(struct stm32_spi *spi) /** * stm32h7_spi_config - Configure SPI controller as SPI master + * @spi: pointer to the spi controller data structure */ static int stm32h7_spi_config(struct stm32_spi *spi) { -- cgit v1.2.3 From 2d4ccc2ac61b1a407a1c75633a3bf2f878ff44b5 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 20 Mar 2020 18:25:56 -0500 Subject: spi: spi-s3c24xx: Replace zero-length array with flexible-array member The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva Reviewed-by: Andi Shyti Link: https://lore.kernel.org/r/20200320232556.GA24989@embeddedor.com Signed-off-by: Mark Brown --- drivers/spi/spi-s3c24xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-s3c24xx.c b/drivers/spi/spi-s3c24xx.c index 2d6e37f25e2d..2cb3b611c294 100644 --- a/drivers/spi/spi-s3c24xx.c +++ b/drivers/spi/spi-s3c24xx.c @@ -227,7 +227,7 @@ static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) struct spi_fiq_code { u32 length; u32 ack_offset; - u8 data[0]; + u8 data[]; }; extern struct spi_fiq_code s3c24xx_spi_fiq_txrx; -- cgit v1.2.3 From 6960b0332c75efbade990f047da073e5f3ef1af4 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 20 Mar 2020 18:25:15 -0500 Subject: spi: spi-fsl-lpspi: Replace zero-length array with flexible-array member The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva Link: https://lore.kernel.org/r/20200320232515.GA24800@embeddedor.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-lpspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index 298329b781d2..8b41b70f6f5c 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -123,7 +123,7 @@ struct fsl_lpspi_data { struct completion dma_rx_completion; struct completion dma_tx_completion; - int chipselect[0]; + int chipselect[]; }; static const struct of_device_id fsl_lpspi_dt_ids[] = { -- cgit v1.2.3 From ebb3b9a92ba98efa8d0525367e653d5ee6630c1b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 17 Mar 2020 10:49:14 +0100 Subject: spi: efm32: Convert to use GPIO descriptors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This switches the EFM32 driver over to use the GPIO descriptor handling in the core. The GPIO handling in this driver is pretty simplistic so this should just work. Drop the GPIO headers and insert the implicitly included header. Signed-off-by: Linus Walleij Cc: Uwe Kleine-König Link: https://lore.kernel.org/r/20200317094914.331932-1-linus.walleij@linaro.org Signed-off-by: Mark Brown --- drivers/spi/spi-efm32.c | 44 +++----------------------------------------- 1 file changed, 3 insertions(+), 41 deletions(-) (limited to 'drivers/spi') diff --git a/drivers/spi/spi-efm32.c b/drivers/spi/spi-efm32.c index 64d4c441b641..ea6e4a7b3feb 100644 --- a/drivers/spi/spi-efm32.c +++ b/drivers/spi/spi-efm32.c @@ -6,14 +6,13 @@ #include #include #include -#include #include #include #include #include #include -#include #include +#include #define DRIVER_NAME "efm32-spi" @@ -82,9 +81,6 @@ struct efm32_spi_ddata { const u8 *tx_buf; u8 *rx_buf; unsigned tx_len, rx_len; - - /* chip selects */ - unsigned csgpio[]; }; #define ddata_to_dev(ddata) (&(ddata->bitbang.master->dev)) @@ -102,14 +98,6 @@ static u32 efm32_spi_read32(struct efm32_spi_ddata *ddata, unsigned offset) return readl_relaxed(ddata->base + offset); } -static void efm32_spi_chipselect(struct spi_device *spi, int is_on) -{ - struct efm32_spi_ddata *ddata = spi_master_get_devdata(spi->master); - int value = !(spi->mode & SPI_CS_HIGH) == !(is_on == BITBANG_CS_ACTIVE); - - gpio_set_value(ddata->csgpio[spi->chip_select], value); -} - static int efm32_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { @@ -320,17 +308,11 @@ static int efm32_spi_probe(struct platform_device *pdev) int ret; struct spi_master *master; struct device_node *np = pdev->dev.of_node; - int num_cs, i; if (!np) return -EINVAL; - num_cs = of_gpio_named_count(np, "cs-gpios"); - if (num_cs < 0) - return num_cs; - - master = spi_alloc_master(&pdev->dev, - sizeof(*ddata) + num_cs * sizeof(unsigned)); + master = spi_alloc_master(&pdev->dev, sizeof(*ddata)); if (!master) { dev_dbg(&pdev->dev, "failed to allocate spi master controller\n"); @@ -340,14 +322,13 @@ static int efm32_spi_probe(struct platform_device *pdev) master->dev.of_node = pdev->dev.of_node; - master->num_chipselect = num_cs; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); + master->use_gpio_descriptors = true; ddata = spi_master_get_devdata(master); ddata->bitbang.master = master; - ddata->bitbang.chipselect = efm32_spi_chipselect; ddata->bitbang.setup_transfer = efm32_spi_setup_transfer; ddata->bitbang.txrx_bufs = efm32_spi_txrx_bufs; @@ -361,25 +342,6 @@ static int efm32_spi_probe(struct platform_device *pdev) goto err; } - for (i = 0; i < num_cs; ++i) { - ret = of_get_named_gpio(np, "cs-gpios", i); - if (ret < 0) { - dev_err(&pdev->dev, "failed to get csgpio#%u (%d)\n", - i, ret); - goto err; - } - ddata->csgpio[i] = ret; - dev_dbg(&pdev->dev, "csgpio#%u = %u\n", i, ddata->csgpio[i]); - ret = devm_gpio_request_one(&pdev->dev, ddata->csgpio[i], - GPIOF_OUT_INIT_LOW, DRIVER_NAME); - if (ret < 0) { - dev_err(&pdev->dev, - "failed to configure csgpio#%u (%d)\n", - i, ret); - goto err; - } - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { ret = -ENODEV; -- cgit v1.2.3