From 1f3753a5f042fea6539986f9caf2552877527d8a Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:17:15 +0800 Subject: soc: sunxi_sram: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20210908071716.772-1-caihuoqing@baidu.com --- drivers/soc/sunxi/sunxi_sram.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 42833e33a96c..a8f3876963a0 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -331,7 +331,6 @@ static struct regmap_config sunxi_sram_emac_clock_regmap = { static int sunxi_sram_probe(struct platform_device *pdev) { - struct resource *res; struct dentry *d; struct regmap *emac_clock; const struct sunxi_sramc_variant *variant; @@ -342,8 +341,7 @@ static int sunxi_sram_probe(struct platform_device *pdev) if (!variant) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); -- cgit v1.2.3 From ca8d1fda5b7d2f81ba9c5649462a7c0b64ae9dcd Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Fri, 20 Aug 2021 01:27:18 +0000 Subject: soc: amlogic: meson-gx-socinfo: Add S905Y2 ID for Radxa Zero Add the SOC ID for the S905Y2 used in the Radxa Zero. Before/After: [ 0.321650] soc soc0: Amlogic Meson G12A (Unknown) Revision 28:b (30:2) Detected [ 0.318533] soc soc0: Amlogic Meson G12A (S905Y2) Revision 28:b (30:2) Detected Signed-off-by: Christian Hewitt Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210820012718.10761-1-christianshewitt@gmail.com --- drivers/soc/amlogic/meson-gx-socinfo.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c index 6f54bd832c8b..165f7548401b 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c @@ -65,6 +65,7 @@ static const struct meson_gx_package_id { { "A113X", 0x25, 0x37, 0xff }, { "A113D", 0x25, 0x22, 0xff }, { "S905D2", 0x28, 0x10, 0xf0 }, + { "S905Y2", 0x28, 0x30, 0xf0 }, { "S905X2", 0x28, 0x40, 0xf0 }, { "A311D", 0x29, 0x10, 0xf0 }, { "S922X", 0x29, 0x40, 0xf0 }, -- cgit v1.2.3 From 97a4a24087ce354ce0318449e6bd9e660f5c573b Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:15:42 +0800 Subject: soc: amlogic: canvas: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210908071544.603-1-caihuoqing@baidu.com --- drivers/soc/amlogic/meson-canvas.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-canvas.c b/drivers/soc/amlogic/meson-canvas.c index d0329ad170d1..383b0cfc584e 100644 --- a/drivers/soc/amlogic/meson-canvas.c +++ b/drivers/soc/amlogic/meson-canvas.c @@ -168,7 +168,6 @@ EXPORT_SYMBOL_GPL(meson_canvas_free); static int meson_canvas_probe(struct platform_device *pdev) { - struct resource *res; struct meson_canvas *canvas; struct device *dev = &pdev->dev; @@ -176,8 +175,7 @@ static int meson_canvas_probe(struct platform_device *pdev) if (!canvas) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - canvas->reg_base = devm_ioremap_resource(dev, res); + canvas->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(canvas->reg_base)) return PTR_ERR(canvas->reg_base); -- cgit v1.2.3 From d54dbe9f0ec05935e10d6a38d81e54e2ec8b8a68 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:15:43 +0800 Subject: soc: amlogic: meson-clk-measure: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210908071544.603-2-caihuoqing@baidu.com --- drivers/soc/amlogic/meson-clk-measure.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index 6dd190270123..3f3039600357 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -606,7 +606,6 @@ static int meson_msr_probe(struct platform_device *pdev) { const struct meson_msr_id *match_data; struct meson_msr *priv; - struct resource *res; struct dentry *root, *clks; void __iomem *base; int i; @@ -624,8 +623,7 @@ static int meson_msr_probe(struct platform_device *pdev) memcpy(priv->msr_table, match_data, sizeof(priv->msr_table)); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); -- cgit v1.2.3 From d687e056a18f71d06e3cb4b10b01815397e30782 Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Mon, 2 Aug 2021 16:59:33 +0800 Subject: soc: mediatek: mmsys: Add mt8192 mmsys routing table mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu Link: https://lore.kernel.org/r/1627894773-23872-3-git-send-email-yongqiang.niu@mediatek.com [mb: take mask into account] Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8192-mmsys.h | 76 +++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++++ 2 files changed, 87 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 000000000000..6f0a57044a7b --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H + +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c + +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 + +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + MT8192_OVL0_MOUT_EN_DISP_RDMA0 + }, { + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, + MT8192_OVL2_2L_MOUT_EN_RDMA4 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, + MT8192_DITHER0_MOUT_IN_DSI0 + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L, + MT8192_RDMA0_SEL_IN_OVL0_2L + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, + MT8192_AAL0_SEL_IN_CCORR0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, + MT8192_RDMA0_SOUT_COLOR0 + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0, + MT8192_CCORR0_SOUT_AAL0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + MT8192_DISP_OVL0_GO_BG + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + MT8192_DISP_OVL0_2L_GO_BLEND + } +}; + +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a78e88f27b62..5ecfe09a5751 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -13,6 +13,7 @@ #include "mtk-mmsys.h" #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" +#include "mt8192-mmsys.h" #include "mt8365-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { @@ -53,6 +54,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .routes = mmsys_mt8192_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), +}; + static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .clk_driver = "clk-mt8365-mm", .routes = mt8365_mmsys_routing_table, @@ -167,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, -- cgit v1.2.3 From 2ed1e4815922a3b22561b6e0e6f6d3d15a4e1007 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 12 Aug 2021 13:23:52 +0200 Subject: soc: renesas: Identify more R-Car Gen3e SoCs Add support for identifying the remaining R-Car Gen3e SoCs: R-Car H3e (R8A779M0), M3e (R8A779M2), M3Ne (R8A779M4), M3Ne-2G (R8A779M5), E3e (R8A779M6), D3e (R8A779M7), and H3Ne (R8A779M8). As these are different gradings of the already supported R-Car Gen3 SoCs, support for them is enabled through the existing ARCH_R8A779* configuration symbols. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ccf2206b24147b3d977e4119bbdefaedceb28644.1628766192.git.geert+renesas@glider.be --- drivers/soc/renesas/Kconfig | 7 +++++-- drivers/soc/renesas/renesas-soc.c | 7 +++++++ 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 07e0ecd64319..ce16ef5c939c 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -186,6 +186,7 @@ config ARCH_R8A77995 select SYSC_R8A77995 help This enables support for the Renesas R-Car D3 SoC. + This includes different gradings like R-Car D3e. config ARCH_R8A77990 bool "ARM64 Platform support for R-Car E3" @@ -193,6 +194,7 @@ config ARCH_R8A77990 select SYSC_R8A77990 help This enables support for the Renesas R-Car E3 SoC. + This includes different gradings like R-Car E3e. config ARCH_R8A77950 bool "ARM64 Platform support for R-Car H3 ES1.x" @@ -208,7 +210,7 @@ config ARCH_R8A77951 help This enables support for the Renesas R-Car H3 SoC (revisions 2.0 and later). - This includes different gradings like R-Car H3e-2G. + This includes different gradings like R-Car H3e, H3e-2G, and H3Ne. config ARCH_R8A77965 bool "ARM64 Platform support for R-Car M3-N" @@ -216,6 +218,7 @@ config ARCH_R8A77965 select SYSC_R8A77965 help This enables support for the Renesas R-Car M3-N SoC. + This includes different gradings like R-Car M3Ne and M3Ne-2G. config ARCH_R8A77960 bool "ARM64 Platform support for R-Car M3-W" @@ -230,7 +233,7 @@ config ARCH_R8A77961 select SYSC_R8A77961 help This enables support for the Renesas R-Car M3-W+ SoC. - This includes different gradings like R-Car M3e-2G. + This includes different gradings like R-Car M3e and M3e-2G. config ARCH_R8A77980 bool "ARM64 Platform support for R-Car V3H" diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c index dab9f5a0aad0..7961b0be1850 100644 --- a/drivers/soc/renesas/renesas-soc.c +++ b/drivers/soc/renesas/renesas-soc.c @@ -285,17 +285,22 @@ static const struct of_device_id renesas_socs[] __initconst = { { .compatible = "renesas,r8a7795", .data = &soc_rcar_h3 }, #endif #ifdef CONFIG_ARCH_R8A77951 + { .compatible = "renesas,r8a779m0", .data = &soc_rcar_h3 }, { .compatible = "renesas,r8a779m1", .data = &soc_rcar_h3 }, + { .compatible = "renesas,r8a779m8", .data = &soc_rcar_h3 }, #endif #ifdef CONFIG_ARCH_R8A77960 { .compatible = "renesas,r8a7796", .data = &soc_rcar_m3_w }, #endif #ifdef CONFIG_ARCH_R8A77961 { .compatible = "renesas,r8a77961", .data = &soc_rcar_m3_w }, + { .compatible = "renesas,r8a779m2", .data = &soc_rcar_m3_w }, { .compatible = "renesas,r8a779m3", .data = &soc_rcar_m3_w }, #endif #ifdef CONFIG_ARCH_R8A77965 { .compatible = "renesas,r8a77965", .data = &soc_rcar_m3_n }, + { .compatible = "renesas,r8a779m4", .data = &soc_rcar_m3_n }, + { .compatible = "renesas,r8a779m5", .data = &soc_rcar_m3_n }, #endif #ifdef CONFIG_ARCH_R8A77970 { .compatible = "renesas,r8a77970", .data = &soc_rcar_v3m }, @@ -305,9 +310,11 @@ static const struct of_device_id renesas_socs[] __initconst = { #endif #ifdef CONFIG_ARCH_R8A77990 { .compatible = "renesas,r8a77990", .data = &soc_rcar_e3 }, + { .compatible = "renesas,r8a779m6", .data = &soc_rcar_e3 }, #endif #ifdef CONFIG_ARCH_R8A77995 { .compatible = "renesas,r8a77995", .data = &soc_rcar_d3 }, + { .compatible = "renesas,r8a779m7", .data = &soc_rcar_d3 }, #endif #ifdef CONFIG_ARCH_R8A779A0 { .compatible = "renesas,r8a779a0", .data = &soc_rcar_v3u }, -- cgit v1.2.3 From dc3401c83f950bfecb7cdffff2b78ac3e09ef505 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:14:15 +0800 Subject: soc: bcm: bcm-pmb: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Florian Fainelli --- drivers/soc/bcm/bcm63xx/bcm-pmb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/bcm63xx/bcm-pmb.c b/drivers/soc/bcm/bcm63xx/bcm-pmb.c index 774465c119be..7bbe46ea5f94 100644 --- a/drivers/soc/bcm/bcm63xx/bcm-pmb.c +++ b/drivers/soc/bcm/bcm63xx/bcm-pmb.c @@ -276,7 +276,6 @@ static int bcm_pmb_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; const struct bcm_pmb_pd_data *table; const struct bcm_pmb_pd_data *e; - struct resource *res; struct bcm_pmb *pmb; int max_id; int err; @@ -287,8 +286,7 @@ static int bcm_pmb_probe(struct platform_device *pdev) pmb->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pmb->base = devm_ioremap_resource(&pdev->dev, res); + pmb->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pmb->base)) return PTR_ERR(pmb->base); -- cgit v1.2.3 From 9787ab5833054500201b980a58ababa3a3ae193c Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:14:16 +0800 Subject: soc: bcm63xx-power: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Florian Fainelli --- drivers/soc/bcm/bcm63xx/bcm63xx-power.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/bcm63xx/bcm63xx-power.c b/drivers/soc/bcm/bcm63xx/bcm63xx-power.c index 515fe182dc34..aa72e13d5d0e 100644 --- a/drivers/soc/bcm/bcm63xx/bcm63xx-power.c +++ b/drivers/soc/bcm/bcm63xx/bcm63xx-power.c @@ -91,7 +91,6 @@ static int bcm63xx_power_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - struct resource *res; const struct bcm63xx_power_data *entry, *table; struct bcm63xx_power *power; unsigned int ndom; @@ -102,8 +101,7 @@ static int bcm63xx_power_probe(struct platform_device *pdev) if (!power) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - power->base = devm_ioremap_resource(&pdev->dev, res); + power->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(power->base)) return PTR_ERR(power->base); -- cgit v1.2.3 From e37ef6dcdb1f4738b01cec7fb7be46af07816af9 Mon Sep 17 00:00:00 2001 From: David Virag Date: Fri, 10 Sep 2021 00:28:12 +0200 Subject: soc: samsung: exynos-pmu: Fix compilation when nothing selects CONFIG_MFD_CORE Commit 93618e344a5e ("soc: samsung: exynos-pmu: instantiate clkout driver as MFD") adds a "devm_mfd_add_devices" call in the exynos-pmu driver which depends on CONFIG_MFD_CORE. If no driver selects that config, the build will fail if CONFIG_EXYNOS_PMU is enabled with the following error: drivers/soc/samsung/exynos-pmu.c:137: undefined reference to `devm_mfd_add_devices' Fix this by making CONFIG_EXYNOS_PMU select CONFIG_MFD_CORE. Fixes: 93618e344a5e ("soc: samsung: exynos-pmu: instantiate clkout driver as MFD") Cc: Signed-off-by: David Virag Link: https://lore.kernel.org/r/20210909222812.108614-1-virag.david003@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index 5745d7e5908e..1f643c0f5c93 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -25,6 +25,7 @@ config EXYNOS_PMU bool "Exynos PMU controller driver" if COMPILE_TEST depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST) select EXYNOS_PMU_ARM_DRIVERS if ARM && ARCH_EXYNOS + select MFD_CORE # There is no need to enable these drivers for ARMv8 config EXYNOS_PMU_ARM_DRIVERS -- cgit v1.2.3 From e8377f497dec2f48bf7599cc9a047941740ecbd3 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 14 Sep 2021 15:21:45 -0700 Subject: soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72113 72113 uses a dual core Cortex-A72 CPU complex which requires tuning of its bus interface unit the same way that the existing Cortex-A72 based systems are tuned. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index 7f8dc302ae6e..e6579fc82b9e 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -136,6 +136,7 @@ static int __init mcp_write_pairing_set(void) static const u32 a72_b53_mach_compat[] = { 0x7211, + 0x72113, 0x7216, 0x72164, 0x72165, -- cgit v1.2.3 From 6e42e16a42c4669d2eb23d6ba3714e03c4c1e387 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 14 Sep 2021 15:21:46 -0700 Subject: soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72116 72116 uses a quad core Brahma-B53 CPU complex which uses the same tuning as done for previous chips, add that chip to the list. Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/biuctrl.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c index e6579fc82b9e..2c975d79fe8e 100644 --- a/drivers/soc/bcm/brcmstb/biuctrl.c +++ b/drivers/soc/bcm/brcmstb/biuctrl.c @@ -137,6 +137,7 @@ static int __init mcp_write_pairing_set(void) static const u32 a72_b53_mach_compat[] = { 0x7211, 0x72113, + 0x72116, 0x7216, 0x72164, 0x72165, -- cgit v1.2.3 From 8c75d585b931ac874fbe4ee5a8f1811d20c2817f Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Tue, 31 Aug 2021 20:00:27 +0530 Subject: soc: qcom: aoss: Expose send for generic usecase Not all upcoming usecases will have an interface to allow the aoss driver to hook onto. Expose the send api and create a get function to enable drivers to send their own messages to aoss. Signed-off-by: Chris Lew Signed-off-by: Deepak Kumar Singh Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1630420228-31075-2-git-send-email-deesin@codeaurora.org --- drivers/soc/qcom/qcom_aoss.c | 54 +++++++++++++++++++++++++++++++++++++- include/linux/soc/qcom/qcom_aoss.h | 38 +++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 include/linux/soc/qcom/qcom_aoss.h (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 536c3e4114fb..bb336cc8df6f 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -8,10 +8,12 @@ #include #include #include +#include #include #include #include #include +#include #define QMP_DESC_MAGIC 0x0 #define QMP_DESC_VERSION 0x4 @@ -223,11 +225,14 @@ static bool qmp_message_empty(struct qmp *qmp) * * Return: 0 on success, negative errno on failure */ -static int qmp_send(struct qmp *qmp, const void *data, size_t len) +int qmp_send(struct qmp *qmp, const void *data, size_t len) { long time_left; int ret; + if (WARN_ON(IS_ERR_OR_NULL(qmp) || !data)) + return -EINVAL; + if (WARN_ON(len + sizeof(u32) > qmp->size)) return -EINVAL; @@ -261,6 +266,7 @@ static int qmp_send(struct qmp *qmp, const void *data, size_t len) return ret; } +EXPORT_SYMBOL(qmp_send); static int qmp_qdss_clk_prepare(struct clk_hw *hw) { @@ -519,6 +525,51 @@ static void qmp_cooling_devices_remove(struct qmp *qmp) thermal_cooling_device_unregister(qmp->cooling_devs[i].cdev); } +/** + * qmp_get() - get a qmp handle from a device + * @dev: client device pointer + * + * Return: handle to qmp device on success, ERR_PTR() on failure + */ +struct qmp *qmp_get(struct device *dev) +{ + struct platform_device *pdev; + struct device_node *np; + struct qmp *qmp; + + if (!dev || !dev->of_node) + return ERR_PTR(-EINVAL); + + np = of_parse_phandle(dev->of_node, "qcom,qmp", 0); + if (!np) + return ERR_PTR(-ENODEV); + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return ERR_PTR(-EINVAL); + + qmp = platform_get_drvdata(pdev); + + return qmp ? qmp : ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL(qmp_get); + +/** + * qmp_put() - release a qmp handle + * @qmp: qmp handle obtained from qmp_get() + */ +void qmp_put(struct qmp *qmp) +{ + /* + * Match get_device() inside of_find_device_by_node() in + * qmp_get() + */ + if (!IS_ERR_OR_NULL(qmp)) + put_device(qmp->dev); +} +EXPORT_SYMBOL(qmp_put); + static int qmp_probe(struct platform_device *pdev) { struct resource *res; @@ -615,6 +666,7 @@ static struct platform_driver qmp_driver = { .driver = { .name = "qcom_aoss_qmp", .of_match_table = qmp_dt_match, + .suppress_bind_attrs = true, }, .probe = qmp_probe, .remove = qmp_remove, diff --git a/include/linux/soc/qcom/qcom_aoss.h b/include/linux/soc/qcom/qcom_aoss.h new file mode 100644 index 000000000000..3c2a82e606f8 --- /dev/null +++ b/include/linux/soc/qcom/qcom_aoss.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __QCOM_AOSS_H__ +#define __QCOM_AOSS_H__ + +#include +#include + +struct qmp; + +#if IS_ENABLED(CONFIG_QCOM_AOSS_QMP) + +int qmp_send(struct qmp *qmp, const void *data, size_t len); +struct qmp *qmp_get(struct device *dev); +void qmp_put(struct qmp *qmp); + +#else + +static inline int qmp_send(struct qmp *qmp, const void *data, size_t len) +{ + return -ENODEV; +} + +static inline struct qmp *qmp_get(struct device *dev) +{ + return ERR_PTR(-ENODEV); +} + +static inline void qmp_put(struct qmp *qmp) +{ +} + +#endif + +#endif -- cgit v1.2.3 From c2b854b03adf325056f57f1aa239440c4e9c7c56 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 20 Aug 2021 22:31:02 +0200 Subject: soc: qcom: rpmhpd: Add SM6350 Add the power domains exposed by RPMH in the Qualcomm SM6350 platform. Acked-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210820203105.229764-4-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index fa209b479ab3..e280a8194725 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -147,6 +147,21 @@ static const struct rpmhpd_desc sdx55_desc = { .num_pds = ARRAY_SIZE(sdx55_rpmhpds), }; +/* SM6350 RPMH powerdomains */ +static struct rpmhpd *sm6350_rpmhpds[] = { + [SM6350_CX] = &sdm845_cx, + [SM6350_GFX] = &sdm845_gfx, + [SM6350_LCX] = &sdm845_lcx, + [SM6350_LMX] = &sdm845_lmx, + [SM6350_MSS] = &sdm845_mss, + [SM6350_MX] = &sdm845_mx, +}; + +static const struct rpmhpd_desc sm6350_desc = { + .rpmhpds = sm6350_rpmhpds, + .num_pds = ARRAY_SIZE(sm6350_rpmhpds), +}; + /* SM8150 RPMH powerdomains */ static struct rpmhpd sm8150_mmcx_ao; @@ -297,6 +312,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, + { .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc }, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, { .compatible = "qcom,sm8350-rpmhpd", .data = &sm8350_desc }, -- cgit v1.2.3 From 1f7b2b6327ffd16d8704bfbf0c28b6bdb6ece39f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Fri, 20 Aug 2021 22:31:04 +0200 Subject: soc: qcom: llcc: Add configuration data for SM6350 Add LLCC configuration data for SM6350 SoC. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20210820203105.229764-6-konrad.dybcio@somainline.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/llcc-qcom.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 15a36dcab990..fb471cc4066b 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -142,6 +142,16 @@ static const struct llcc_slice_config sdm845_data[] = { { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, }; +static const struct llcc_slice_config sm6350_data[] = { + { LLCC_CPUSS, 1, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 1 }, + { LLCC_MDM, 8, 512, 2, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW, 11, 256, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 512, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_MDMPNG, 21, 768, 0, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_NPU, 23, 768, 1, 0, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_MODPE, 29, 64, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1, 0 }, +}; + static const struct llcc_slice_config sm8150_data[] = { { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, @@ -203,6 +213,11 @@ static const struct qcom_llcc_config sdm845_cfg = { .need_llcc_cfg = false, }; +static const struct qcom_llcc_config sm6350_cfg = { + .sct_data = sm6350_data, + .size = ARRAY_SIZE(sm6350_data), +}; + static const struct qcom_llcc_config sm8150_cfg = { .sct_data = sm8150_data, .size = ARRAY_SIZE(sm8150_data), @@ -626,6 +641,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, + { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, { .compatible = "qcom,sm8250-llcc", .data = &sm8250_cfg }, { } -- cgit v1.2.3 From 60f3692b5f0b3e1df3ccc07c28758379052d0ab6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 17:56:05 +0200 Subject: cpuidle: qcom_spm: Detach state machine from main SPM handling In commit a871be6b8eee ("cpuidle: Convert Qualcomm SPM driver to a generic CPUidle driver") the SPM driver has been converted to a generic CPUidle driver: that was mainly made to simplify the driver and that was a great accomplishment; Though, at that time, this driver was only applicable to ARM 32-bit SoCs, lacking logic about the handling of newer generation SAW. In preparation for the enablement of SPM features on AArch64/ARM64, split the cpuidle-qcom-spm driver in two: the CPUIdle related state machine (currently used only on ARM SoCs) stays there, while the SPM communication handling lands back in soc/qcom/spm.c and also making sure to not discard the simplifications that were introduced in the aforementioned commit. Since now the "two drivers" are split, the SCM dependency in the main SPM handling is gone and for this reason it was also possible to move the SPM initialization early: this will also make sure that whenever the SAW CPUIdle driver is getting initialized, the SPM driver will be ready to do the job. Please note that the anticipation of the SPM initialization was also done to optimize the boot times on platforms that have their CPU/L2 idle states managed by other means (such as PSCI), while needing SAW initialization for other purposes, like AVS control. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Stephan Gerhold Tested-by: Stephan Gerhold Acked-by: Daniel Lezcano Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210729155609.608159-2-angelogioacchino.delregno@somainline.org --- drivers/cpuidle/Kconfig.arm | 1 + drivers/cpuidle/cpuidle-qcom-spm.c | 318 ++++++++----------------------------- drivers/soc/qcom/Kconfig | 9 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/spm.c | 216 +++++++++++++++++++++++++ include/soc/qcom/spm.h | 41 +++++ 6 files changed, 336 insertions(+), 250 deletions(-) create mode 100644 drivers/soc/qcom/spm.c create mode 100644 include/soc/qcom/spm.h (limited to 'drivers/soc') diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 334f83e56120..8a02213c8391 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -112,6 +112,7 @@ config ARM_QCOM_SPM_CPUIDLE select CPU_IDLE_MULTIPLE_DRIVERS select DT_IDLE_STATES select QCOM_SCM + select QCOM_SPM help Select this to enable cpuidle for Qualcomm processors. The Subsystem Power Manager (SPM) controls low power modes for the diff --git a/drivers/cpuidle/cpuidle-qcom-spm.c b/drivers/cpuidle/cpuidle-qcom-spm.c index c0e7971da2da..01e77913a414 100644 --- a/drivers/cpuidle/cpuidle-qcom-spm.c +++ b/drivers/cpuidle/cpuidle-qcom-spm.c @@ -18,158 +18,18 @@ #include #include #include +#include #include #include #include "dt_idle_states.h" -#define MAX_PMIC_DATA 2 -#define MAX_SEQ_DATA 64 -#define SPM_CTL_INDEX 0x7f -#define SPM_CTL_INDEX_SHIFT 4 -#define SPM_CTL_EN BIT(0) - -enum pm_sleep_mode { - PM_SLEEP_MODE_STBY, - PM_SLEEP_MODE_RET, - PM_SLEEP_MODE_SPC, - PM_SLEEP_MODE_PC, - PM_SLEEP_MODE_NR, -}; - -enum spm_reg { - SPM_REG_CFG, - SPM_REG_SPM_CTL, - SPM_REG_DLY, - SPM_REG_PMIC_DLY, - SPM_REG_PMIC_DATA_0, - SPM_REG_PMIC_DATA_1, - SPM_REG_VCTL, - SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, - SPM_REG_PMIC_STS, - SPM_REG_NR, -}; - -struct spm_reg_data { - const u8 *reg_offset; - u32 spm_cfg; - u32 spm_dly; - u32 pmic_dly; - u32 pmic_data[MAX_PMIC_DATA]; - u8 seq[MAX_SEQ_DATA]; - u8 start_index[PM_SLEEP_MODE_NR]; -}; - -struct spm_driver_data { +struct cpuidle_qcom_spm_data { struct cpuidle_driver cpuidle_driver; - void __iomem *reg_base; - const struct spm_reg_data *reg_data; -}; - -static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { - [SPM_REG_CFG] = 0x08, - [SPM_REG_SPM_CTL] = 0x30, - [SPM_REG_DLY] = 0x34, - [SPM_REG_SEQ_ENTRY] = 0x80, -}; - -/* SPM register data for 8974, 8084 */ -static const struct spm_reg_data spm_reg_8974_8084_cpu = { - .reg_offset = spm_reg_offset_v2_1, - .spm_cfg = 0x1, - .spm_dly = 0x3C102800, - .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03, - 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30, - 0x0F }, - .start_index[PM_SLEEP_MODE_STBY] = 0, - .start_index[PM_SLEEP_MODE_SPC] = 3, + struct spm_driver_data *spm; }; -/* SPM register data for 8226 */ -static const struct spm_reg_data spm_reg_8226_cpu = { - .reg_offset = spm_reg_offset_v2_1, - .spm_cfg = 0x0, - .spm_dly = 0x3C102800, - .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, - 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, - 0x80, 0x10, 0x26, 0x30, 0x0F }, - .start_index[PM_SLEEP_MODE_STBY] = 0, - .start_index[PM_SLEEP_MODE_SPC] = 5, -}; - -static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { - [SPM_REG_CFG] = 0x08, - [SPM_REG_SPM_CTL] = 0x20, - [SPM_REG_PMIC_DLY] = 0x24, - [SPM_REG_PMIC_DATA_0] = 0x28, - [SPM_REG_PMIC_DATA_1] = 0x2C, - [SPM_REG_SEQ_ENTRY] = 0x80, -}; - -/* SPM register data for 8064 */ -static const struct spm_reg_data spm_reg_8064_cpu = { - .reg_offset = spm_reg_offset_v1_1, - .spm_cfg = 0x1F, - .pmic_dly = 0x02020004, - .pmic_data[0] = 0x0084009C, - .pmic_data[1] = 0x00A4001C, - .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01, - 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, - .start_index[PM_SLEEP_MODE_STBY] = 0, - .start_index[PM_SLEEP_MODE_SPC] = 2, -}; - -static inline void spm_register_write(struct spm_driver_data *drv, - enum spm_reg reg, u32 val) -{ - if (drv->reg_data->reg_offset[reg]) - writel_relaxed(val, drv->reg_base + - drv->reg_data->reg_offset[reg]); -} - -/* Ensure a guaranteed write, before return */ -static inline void spm_register_write_sync(struct spm_driver_data *drv, - enum spm_reg reg, u32 val) -{ - u32 ret; - - if (!drv->reg_data->reg_offset[reg]) - return; - - do { - writel_relaxed(val, drv->reg_base + - drv->reg_data->reg_offset[reg]); - ret = readl_relaxed(drv->reg_base + - drv->reg_data->reg_offset[reg]); - if (ret == val) - break; - cpu_relax(); - } while (1); -} - -static inline u32 spm_register_read(struct spm_driver_data *drv, - enum spm_reg reg) -{ - return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); -} - -static void spm_set_low_power_mode(struct spm_driver_data *drv, - enum pm_sleep_mode mode) -{ - u32 start_index; - u32 ctl_val; - - start_index = drv->reg_data->start_index[mode]; - - ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); - ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); - ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; - ctl_val |= SPM_CTL_EN; - spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); -} - static int qcom_pm_collapse(unsigned long int unused) { qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON); @@ -201,10 +61,10 @@ static int qcom_cpu_spc(struct spm_driver_data *drv) static int spm_enter_idle_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, int idx) { - struct spm_driver_data *data = container_of(drv, struct spm_driver_data, - cpuidle_driver); + struct cpuidle_qcom_spm_data *data = container_of(drv, struct cpuidle_qcom_spm_data, + cpuidle_driver); - return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data); + return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data->spm); } static struct cpuidle_driver qcom_spm_idle_driver = { @@ -225,134 +85,92 @@ static const struct of_device_id qcom_idle_state_match[] = { { }, }; -static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu) +static int spm_cpuidle_register(struct device *cpuidle_dev, int cpu) { + struct platform_device *pdev = NULL; + struct device_node *cpu_node, *saw_node; + struct cpuidle_qcom_spm_data *data = NULL; int ret; - memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv)); - drv->cpumask = (struct cpumask *)cpumask_of(cpu); + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + return -ENODEV; - /* Parse idle states from device tree */ - ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1); - if (ret <= 0) - return ret ? : -ENODEV; + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + if (!saw_node) + return -ENODEV; - /* We have atleast one power down mode */ - return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask); -} + pdev = of_find_device_by_node(saw_node); + of_node_put(saw_node); + of_node_put(cpu_node); + if (!pdev) + return -ENODEV; -static struct spm_driver_data *spm_get_drv(struct platform_device *pdev, - int *spm_cpu) -{ - struct spm_driver_data *drv = NULL; - struct device_node *cpu_node, *saw_node; - int cpu; - bool found = 0; + data = devm_kzalloc(cpuidle_dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; - for_each_possible_cpu(cpu) { - cpu_node = of_cpu_device_node_get(cpu); - if (!cpu_node) - continue; - saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); - found = (saw_node == pdev->dev.of_node); - of_node_put(saw_node); - of_node_put(cpu_node); - if (found) - break; - } + data->spm = dev_get_drvdata(&pdev->dev); + if (!data->spm) + return -EINVAL; - if (found) { - drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); - if (drv) - *spm_cpu = cpu; - } + data->cpuidle_driver = qcom_spm_idle_driver; + data->cpuidle_driver.cpumask = (struct cpumask *)cpumask_of(cpu); - return drv; -} + ret = dt_init_idle_driver(&data->cpuidle_driver, + qcom_idle_state_match, 1); + if (ret <= 0) + return ret ? : -ENODEV; -static const struct of_device_id spm_match_table[] = { - { .compatible = "qcom,msm8226-saw2-v2.1-cpu", - .data = &spm_reg_8226_cpu }, - { .compatible = "qcom,msm8974-saw2-v2.1-cpu", - .data = &spm_reg_8974_8084_cpu }, - { .compatible = "qcom,apq8084-saw2-v2.1-cpu", - .data = &spm_reg_8974_8084_cpu }, - { .compatible = "qcom,apq8064-saw2-v1.1-cpu", - .data = &spm_reg_8064_cpu }, - { }, -}; + ret = qcom_scm_set_warm_boot_addr(cpu_resume_arm, cpumask_of(cpu)); + if (ret) + return ret; + + return cpuidle_register(&data->cpuidle_driver, NULL); +} -static int spm_dev_probe(struct platform_device *pdev) +static int spm_cpuidle_drv_probe(struct platform_device *pdev) { - struct spm_driver_data *drv; - struct resource *res; - const struct of_device_id *match_id; - void __iomem *addr; int cpu, ret; if (!qcom_scm_is_available()) return -EPROBE_DEFER; - drv = spm_get_drv(pdev, &cpu); - if (!drv) - return -EINVAL; - platform_set_drvdata(pdev, drv); + for_each_possible_cpu(cpu) { + ret = spm_cpuidle_register(&pdev->dev, cpu); + if (ret && ret != -ENODEV) { + dev_err(&pdev->dev, + "Cannot register for CPU%d: %d\n", cpu, ret); + } + } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - drv->reg_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(drv->reg_base)) - return PTR_ERR(drv->reg_base); + return 0; +} - match_id = of_match_node(spm_match_table, pdev->dev.of_node); - if (!match_id) - return -ENODEV; +static struct platform_driver spm_cpuidle_driver = { + .probe = spm_cpuidle_drv_probe, + .driver = { + .name = "qcom-spm-cpuidle", + .suppress_bind_attrs = true, + }, +}; - drv->reg_data = match_id->data; +static int __init qcom_spm_cpuidle_init(void) +{ + struct platform_device *pdev; + int ret; - ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu); + ret = platform_driver_register(&spm_cpuidle_driver); if (ret) return ret; - /* Write the SPM sequences first.. */ - addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; - __iowrite32_copy(addr, drv->reg_data->seq, - ARRAY_SIZE(drv->reg_data->seq) / 4); - - /* - * ..and then the control registers. - * On some SoC if the control registers are written first and if the - * CPU was held in reset, the reset signal could trigger the SPM state - * machine, before the sequences are completely written. - */ - spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); - spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); - spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); - spm_register_write(drv, SPM_REG_PMIC_DATA_0, - drv->reg_data->pmic_data[0]); - spm_register_write(drv, SPM_REG_PMIC_DATA_1, - drv->reg_data->pmic_data[1]); - - /* Set up Standby as the default low power mode */ - spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - - return cpuidle_register(&drv->cpuidle_driver, NULL); -} - -static int spm_dev_remove(struct platform_device *pdev) -{ - struct spm_driver_data *drv = platform_get_drvdata(pdev); + pdev = platform_device_register_simple("qcom-spm-cpuidle", + -1, NULL, 0); + if (IS_ERR(pdev)) { + platform_driver_unregister(&spm_cpuidle_driver); + return PTR_ERR(pdev); + } - cpuidle_unregister(&drv->cpuidle_driver); return 0; } - -static struct platform_driver spm_driver = { - .probe = spm_dev_probe, - .remove = spm_dev_remove, - .driver = { - .name = "saw", - .of_match_table = spm_match_table, - }, -}; - -builtin_platform_driver(spm_driver); +device_initcall(qcom_spm_cpuidle_init); diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 79b568f82a1c..fe3c486ae32d 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -190,6 +190,15 @@ config QCOM_SOCINFO Say yes here to support the Qualcomm socinfo driver, providing information about the SoC to user space. +config QCOM_SPM + tristate "Qualcomm Subsystem Power Manager (SPM)" + depends on ARCH_QCOM + select QCOM_SCM + help + Enable the support for the Qualcomm Subsystem Power Manager, used + to manage cores, L2 low power modes and to configure the internal + Adaptive Voltage Scaler parameters, where supported. + config QCOM_WCNSS_CTRL tristate "Qualcomm WCNSS control driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index ad675a6593d0..24514c722832 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o +obj-$(CONFIG_QCOM_SPM) += spm.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c new file mode 100644 index 000000000000..ef20607877de --- /dev/null +++ b/drivers/soc/qcom/spm.c @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2015, Linaro Ltd. + * + * SAW power controller driver + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPM_CTL_INDEX 0x7f +#define SPM_CTL_INDEX_SHIFT 4 +#define SPM_CTL_EN BIT(0) + +enum spm_reg { + SPM_REG_CFG, + SPM_REG_SPM_CTL, + SPM_REG_DLY, + SPM_REG_PMIC_DLY, + SPM_REG_PMIC_DATA_0, + SPM_REG_PMIC_DATA_1, + SPM_REG_VCTL, + SPM_REG_SEQ_ENTRY, + SPM_REG_SPM_STS, + SPM_REG_PMIC_STS, + SPM_REG_NR, +}; + +static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x30, + [SPM_REG_DLY] = 0x34, + [SPM_REG_SEQ_ENTRY] = 0x80, +}; + +/* SPM register data for 8974, 8084 */ +static const struct spm_reg_data spm_reg_8974_8084_cpu = { + .reg_offset = spm_reg_offset_v2_1, + .spm_cfg = 0x1, + .spm_dly = 0x3C102800, + .seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03, + 0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30, + 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 3, +}; + +/* SPM register data for 8226 */ +static const struct spm_reg_data spm_reg_8226_cpu = { + .reg_offset = spm_reg_offset_v2_1, + .spm_cfg = 0x0, + .spm_dly = 0x3C102800, + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, + 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, + 0x80, 0x10, 0x26, 0x30, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 5, +}; + +static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x20, + [SPM_REG_PMIC_DLY] = 0x24, + [SPM_REG_PMIC_DATA_0] = 0x28, + [SPM_REG_PMIC_DATA_1] = 0x2C, + [SPM_REG_SEQ_ENTRY] = 0x80, +}; + +/* SPM register data for 8064 */ +static const struct spm_reg_data spm_reg_8064_cpu = { + .reg_offset = spm_reg_offset_v1_1, + .spm_cfg = 0x1F, + .pmic_dly = 0x02020004, + .pmic_data[0] = 0x0084009C, + .pmic_data[1] = 0x00A4001C, + .seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01, + 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 2, +}; + +static inline void spm_register_write(struct spm_driver_data *drv, + enum spm_reg reg, u32 val) +{ + if (drv->reg_data->reg_offset[reg]) + writel_relaxed(val, drv->reg_base + + drv->reg_data->reg_offset[reg]); +} + +/* Ensure a guaranteed write, before return */ +static inline void spm_register_write_sync(struct spm_driver_data *drv, + enum spm_reg reg, u32 val) +{ + u32 ret; + + if (!drv->reg_data->reg_offset[reg]) + return; + + do { + writel_relaxed(val, drv->reg_base + + drv->reg_data->reg_offset[reg]); + ret = readl_relaxed(drv->reg_base + + drv->reg_data->reg_offset[reg]); + if (ret == val) + break; + cpu_relax(); + } while (1); +} + +static inline u32 spm_register_read(struct spm_driver_data *drv, + enum spm_reg reg) +{ + return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]); +} + +void spm_set_low_power_mode(struct spm_driver_data *drv, + enum pm_sleep_mode mode) +{ + u32 start_index; + u32 ctl_val; + + start_index = drv->reg_data->start_index[mode]; + + ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL); + ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT); + ctl_val |= start_index << SPM_CTL_INDEX_SHIFT; + ctl_val |= SPM_CTL_EN; + spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); +} + +static const struct of_device_id spm_match_table[] = { + { .compatible = "qcom,msm8226-saw2-v2.1-cpu", + .data = &spm_reg_8226_cpu }, + { .compatible = "qcom,msm8974-saw2-v2.1-cpu", + .data = &spm_reg_8974_8084_cpu }, + { .compatible = "qcom,apq8084-saw2-v2.1-cpu", + .data = &spm_reg_8974_8084_cpu }, + { .compatible = "qcom,apq8064-saw2-v1.1-cpu", + .data = &spm_reg_8064_cpu }, + { }, +}; +MODULE_DEVICE_TABLE(of, spm_match_table); + +static int spm_dev_probe(struct platform_device *pdev) +{ + const struct of_device_id *match_id; + struct spm_driver_data *drv; + struct resource *res; + void __iomem *addr; + + drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); + if (!drv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + drv->reg_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(drv->reg_base)) + return PTR_ERR(drv->reg_base); + + match_id = of_match_node(spm_match_table, pdev->dev.of_node); + if (!match_id) + return -ENODEV; + + drv->reg_data = match_id->data; + platform_set_drvdata(pdev, drv); + + /* Write the SPM sequences first.. */ + addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY]; + __iowrite32_copy(addr, drv->reg_data->seq, + ARRAY_SIZE(drv->reg_data->seq) / 4); + + /* + * ..and then the control registers. + * On some SoC if the control registers are written first and if the + * CPU was held in reset, the reset signal could trigger the SPM state + * machine, before the sequences are completely written. + */ + spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); + spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); + spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, + drv->reg_data->pmic_data[0]); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, + drv->reg_data->pmic_data[1]); + + /* Set up Standby as the default low power mode */ + spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); + + return 0; +} + +static struct platform_driver spm_driver = { + .probe = spm_dev_probe, + .driver = { + .name = "qcom_spm", + .of_match_table = spm_match_table, + }, +}; + +static int __init qcom_spm_init(void) +{ + return platform_driver_register(&spm_driver); +} +arch_initcall(qcom_spm_init); + +MODULE_LICENSE("GPL v2"); diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h new file mode 100644 index 000000000000..4c7e5ac2583d --- /dev/null +++ b/include/soc/qcom/spm.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved. + * Copyright (c) 2014,2015, Linaro Ltd. + */ + +#ifndef __SPM_H__ +#define __SPM_H__ + +#include + +#define MAX_PMIC_DATA 2 +#define MAX_SEQ_DATA 64 + +enum pm_sleep_mode { + PM_SLEEP_MODE_STBY, + PM_SLEEP_MODE_RET, + PM_SLEEP_MODE_SPC, + PM_SLEEP_MODE_PC, + PM_SLEEP_MODE_NR, +}; + +struct spm_reg_data { + const u8 *reg_offset; + u32 spm_cfg; + u32 spm_dly; + u32 pmic_dly; + u32 pmic_data[MAX_PMIC_DATA]; + u8 seq[MAX_SEQ_DATA]; + u8 start_index[PM_SLEEP_MODE_NR]; +}; + +struct spm_driver_data { + void __iomem *reg_base; + const struct spm_reg_data *reg_data; +}; + +void spm_set_low_power_mode(struct spm_driver_data *drv, + enum pm_sleep_mode mode); + +#endif /* __SPM_H__ */ -- cgit v1.2.3 From 13e72c3e22611915f9a71a513b640e064a403e78 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 17:56:07 +0200 Subject: soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS Implement the support for SAW v4.1, used in at least MSM8998, SDM630, SDM660 and APQ variants and, while at it, also add the configuration for the SDM630/660 Silver and Gold cluster L2 Adaptive Voltage Scaler: this is also one of the prerequisites to allow the OSM controller to perform DCVS. Please note that despite there are various "versions" of these values downstream, these are the only ones that are perfectly stable on the entire set of tested devices. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210729155609.608159-4-angelogioacchino.delregno@somainline.org --- drivers/soc/qcom/spm.c | 32 +++++++++++++++++++++++++++++--- include/soc/qcom/spm.h | 4 +++- 2 files changed, 32 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index ef20607877de..fb8de9dcfee7 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -33,10 +33,29 @@ enum spm_reg { SPM_REG_SEQ_ENTRY, SPM_REG_SPM_STS, SPM_REG_PMIC_STS, + SPM_REG_AVS_CTL, + SPM_REG_AVS_LIMIT, SPM_REG_NR, }; -static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = { +static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = { + [SPM_REG_AVS_CTL] = 0x904, + [SPM_REG_AVS_LIMIT] = 0x908, +}; + +static const struct spm_reg_data spm_reg_660_gold_l2 = { + .reg_offset = spm_reg_offset_v4_1, + .avs_ctl = 0x1010031, + .avs_limit = 0x4580458, +}; + +static const struct spm_reg_data spm_reg_660_silver_l2 = { + .reg_offset = spm_reg_offset_v4_1, + .avs_ctl = 0x101c031, + .avs_limit = 0x4580458, +}; + +static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, [SPM_REG_DLY] = 0x34, @@ -67,7 +86,7 @@ static const struct spm_reg_data spm_reg_8226_cpu = { .start_index[PM_SLEEP_MODE_SPC] = 5, }; -static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = { +static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, @@ -139,6 +158,10 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, } static const struct of_device_id spm_match_table[] = { + { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", + .data = &spm_reg_660_gold_l2 }, + { .compatible = "qcom,sdm660-silver-saw2-v4.1-l2", + .data = &spm_reg_660_silver_l2 }, { .compatible = "qcom,msm8226-saw2-v2.1-cpu", .data = &spm_reg_8226_cpu }, { .compatible = "qcom,msm8974-saw2-v2.1-cpu", @@ -185,6 +208,8 @@ static int spm_dev_probe(struct platform_device *pdev) * CPU was held in reset, the reset signal could trigger the SPM state * machine, before the sequences are completely written. */ + spm_register_write(drv, SPM_REG_AVS_CTL, drv->reg_data->avs_ctl); + spm_register_write(drv, SPM_REG_AVS_LIMIT, drv->reg_data->avs_limit); spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg); spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly); spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly); @@ -194,7 +219,8 @@ static int spm_dev_probe(struct platform_device *pdev) drv->reg_data->pmic_data[1]); /* Set up Standby as the default low power mode */ - spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); + if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) + spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); return 0; } diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4c7e5ac2583d..4951f9d8b0bd 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -21,11 +21,13 @@ enum pm_sleep_mode { }; struct spm_reg_data { - const u8 *reg_offset; + const u16 *reg_offset; u32 spm_cfg; u32 spm_dly; u32 pmic_dly; u32 pmic_data[MAX_PMIC_DATA]; + u32 avs_ctl; + u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; }; -- cgit v1.2.3 From e48e6fb9ebdf90a290933712621319cf2cfcb777 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 29 Jul 2021 17:56:08 +0200 Subject: soc: qcom: spm: Add compatible for MSM8998 SAWv4.1 L2 Add the SAWv4.1 parameters for MSM8998's Gold and Silver clusters. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210729155609.608159-5-angelogioacchino.delregno@somainline.org --- drivers/soc/qcom/spm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index fb8de9dcfee7..2961a89d929c 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -55,6 +55,18 @@ static const struct spm_reg_data spm_reg_660_silver_l2 = { .avs_limit = 0x4580458, }; +static const struct spm_reg_data spm_reg_8998_gold_l2 = { + .reg_offset = spm_reg_offset_v4_1, + .avs_ctl = 0x1010031, + .avs_limit = 0x4700470, +}; + +static const struct spm_reg_data spm_reg_8998_silver_l2 = { + .reg_offset = spm_reg_offset_v4_1, + .avs_ctl = 0x1010031, + .avs_limit = 0x4200420, +}; + static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, @@ -166,6 +178,10 @@ static const struct of_device_id spm_match_table[] = { .data = &spm_reg_8226_cpu }, { .compatible = "qcom,msm8974-saw2-v2.1-cpu", .data = &spm_reg_8974_8084_cpu }, + { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2", + .data = &spm_reg_8998_gold_l2 }, + { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2", + .data = &spm_reg_8998_silver_l2 }, { .compatible = "qcom,apq8084-saw2-v2.1-cpu", .data = &spm_reg_8974_8084_cpu }, { .compatible = "qcom,apq8064-saw2-v1.1-cpu", -- cgit v1.2.3 From e972a290b03f83eb06c70610eaed7b0984babde7 Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Wed, 25 Aug 2021 22:31:51 +0530 Subject: soc: qcom: smd-rpm: Add compatible for MSM8953 SoC Add a compatible for MSM8953 Signed-off-by: Vladimir Lypak Signed-off-by: Adam Skladowski Signed-off-by: Sireesh Kodali Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210825170151.19698-1-sireeshkodali1@gmail.com --- drivers/soc/qcom/smd-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index dfdd4f20f5fd..fb4896d7a9a7 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -236,6 +236,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-msm8226" }, { .compatible = "qcom,rpm-msm8916" }, { .compatible = "qcom,rpm-msm8936" }, + { .compatible = "qcom,rpm-msm8953" }, { .compatible = "qcom,rpm-msm8974" }, { .compatible = "qcom,rpm-msm8976" }, { .compatible = "qcom,rpm-msm8994" }, -- cgit v1.2.3 From e7ec00eafe944e7a4d02918517aa31c2c3b6c48a Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Wed, 25 Aug 2021 22:32:51 +0530 Subject: soc: qcom: rpmpd: Add power domains for MSM8953 Add support for MSM8953 power domains. Signed-off-by: Vladimir Lypak Signed-off-by: Adam Skladowski Signed-off-by: Sireesh Kodali Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210825170252.20137-1-sireeshkodali1@gmail.com --- drivers/soc/qcom/rpmpd.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index dbf494e92574..4f69fb9b2e0e 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -185,6 +185,29 @@ static const struct rpmpd_desc msm8916_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; +/* msm8953 RPM Power Domains */ +DEFINE_RPMPD_PAIR(msm8953, vddmd, vddmd_ao, SMPA, LEVEL, 1); +DEFINE_RPMPD_PAIR(msm8953, vddcx, vddcx_ao, SMPA, LEVEL, 2); +DEFINE_RPMPD_PAIR(msm8953, vddmx, vddmx_ao, SMPA, LEVEL, 7); + +DEFINE_RPMPD_VFL(msm8953, vddcx_vfl, SMPA, 2); + +static struct rpmpd *msm8953_rpmpds[] = { + [MSM8953_VDDMD] = &msm8953_vddmd, + [MSM8953_VDDMD_AO] = &msm8953_vddmd_ao, + [MSM8953_VDDCX] = &msm8953_vddcx, + [MSM8953_VDDCX_AO] = &msm8953_vddcx_ao, + [MSM8953_VDDCX_VFL] = &msm8953_vddcx_vfl, + [MSM8953_VDDMX] = &msm8953_vddmx, + [MSM8953_VDDMX_AO] = &msm8953_vddmx_ao, +}; + +static const struct rpmpd_desc msm8953_desc = { + .rpmpds = msm8953_rpmpds, + .num_pds = ARRAY_SIZE(msm8953_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO, +}; + /* msm8976 RPM Power Domains */ DEFINE_RPMPD_PAIR(msm8976, vddcx, vddcx_ao, SMPA, LEVEL, 2); DEFINE_RPMPD_PAIR(msm8976, vddmx, vddmx_ao, SMPA, LEVEL, 6); @@ -377,6 +400,7 @@ static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,mdm9607-rpmpd", .data = &mdm9607_desc }, { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, + { .compatible = "qcom,msm8953-rpmpd", .data = &msm8953_desc }, { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, { .compatible = "qcom,msm8994-rpmpd", .data = &msm8994_desc }, { .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc }, -- cgit v1.2.3 From aa88e34f2bfdb7516510b0d154eaa6c0a9b284cb Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 5 Sep 2021 19:11:31 +0200 Subject: soc: qcom: socinfo: Add IPQ8074 family ID-s IPQ8074 family SoC ID-s are missing, so lets add them based on the downstream driver. Signed-off-by: Robert Marko Reviewed-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210905171131.660885-1-robimarko@gmail.com --- drivers/soc/qcom/socinfo.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 9faf48302f4b..288897868435 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -281,19 +281,31 @@ static const struct soc_id soc_id[] = { { 319, "APQ8098" }, { 321, "SDM845" }, { 322, "MDM9206" }, + { 323, "IPQ8074" }, { 324, "SDA660" }, { 325, "SDM658" }, { 326, "SDA658" }, { 327, "SDA630" }, { 338, "SDM450" }, { 341, "SDA845" }, + { 342, "IPQ8072" }, + { 343, "IPQ8076" }, + { 344, "IPQ8078" }, { 345, "SDM636" }, { 346, "SDA636" }, { 349, "SDM632" }, { 350, "SDA632" }, { 351, "SDA450" }, { 356, "SM8250" }, + { 375, "IPQ8070" }, + { 376, "IPQ8071" }, + { 389, "IPQ8072A" }, + { 390, "IPQ8074A" }, + { 391, "IPQ8076A" }, + { 392, "IPQ8078A" }, { 394, "SM6125" }, + { 395, "IPQ8070A" }, + { 396, "IPQ8071A" }, { 402, "IPQ6018" }, { 403, "IPQ6028" }, { 421, "IPQ6000" }, -- cgit v1.2.3 From 0e6fda9c65634e1f6f4a18fd1c48acf0af761deb Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 16:02:11 +0800 Subject: PM: AVS: qcom-cpr: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210908080216.1301-1-caihuoqing@baidu.com --- drivers/soc/qcom/cpr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/cpr.c b/drivers/soc/qcom/cpr.c index 4ce8e816154f..1d818a8ba208 100644 --- a/drivers/soc/qcom/cpr.c +++ b/drivers/soc/qcom/cpr.c @@ -1614,7 +1614,6 @@ static void cpr_debugfs_init(struct cpr_drv *drv) static int cpr_probe(struct platform_device *pdev) { - struct resource *res; struct device *dev = &pdev->dev; struct cpr_drv *drv; int irq, ret; @@ -1648,8 +1647,7 @@ static int cpr_probe(struct platform_device *pdev) if (IS_ERR(drv->tcsr)) return PTR_ERR(drv->tcsr); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - drv->base = devm_ioremap_resource(dev, res); + drv->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(drv->base)) return PTR_ERR(drv->base); -- cgit v1.2.3 From 172037b12be46aee55dae3ae4f8468a2dbd5eaa3 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 16:02:12 +0800 Subject: soc: qcom: ocmem: Make use of the helper function devm_platform_ioremap_resource_byname() Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210908080216.1301-2-caihuoqing@baidu.com --- drivers/soc/qcom/ocmem.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index f1875dc31ae2..d2dacbbaafbd 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -300,7 +300,6 @@ static int ocmem_dev_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; unsigned long reg, region_size; int i, j, ret, num_banks; - struct resource *res; struct ocmem *ocmem; if (!qcom_scm_is_available()) @@ -321,8 +320,7 @@ static int ocmem_dev_probe(struct platform_device *pdev) return ret; } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl"); - ocmem->mmio = devm_ioremap_resource(&pdev->dev, res); + ocmem->mmio = devm_platform_ioremap_resource_byname(pdev, "ctrl"); if (IS_ERR(ocmem->mmio)) { dev_err(&pdev->dev, "Failed to ioremap ocmem_ctrl resource\n"); return PTR_ERR(ocmem->mmio); -- cgit v1.2.3 From d21dc0be36bbe8d424a956f6594c3f2b9f7884a6 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 16:02:13 +0800 Subject: soc: qcom: geni: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210908080216.1301-3-caihuoqing@baidu.com --- drivers/soc/qcom/qcom-geni-se.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 7d649d2cf31e..28a8c0dda66c 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -871,7 +871,6 @@ EXPORT_SYMBOL(geni_icc_disable); static int geni_se_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *res; struct geni_wrapper *wrapper; int ret; @@ -880,8 +879,7 @@ static int geni_se_probe(struct platform_device *pdev) return -ENOMEM; wrapper->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - wrapper->base = devm_ioremap_resource(dev, res); + wrapper->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(wrapper->base)) return PTR_ERR(wrapper->base); -- cgit v1.2.3 From c318dcbcccd35a033e7bd79ba51004d2daeb4acb Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 16:02:14 +0800 Subject: soc: qcom: aoss: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210908080216.1301-4-caihuoqing@baidu.com --- drivers/soc/qcom/qcom_aoss.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 536c3e4114fb..c42b80ee3920 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -521,7 +521,6 @@ static void qmp_cooling_devices_remove(struct qmp *qmp) static int qmp_probe(struct platform_device *pdev) { - struct resource *res; struct qmp *qmp; int irq; int ret; @@ -534,8 +533,7 @@ static int qmp_probe(struct platform_device *pdev) init_waitqueue_head(&qmp->event); mutex_init(&qmp->tx_lock); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - qmp->msgram = devm_ioremap_resource(&pdev->dev, res); + qmp->msgram = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(qmp->msgram)) return PTR_ERR(qmp->msgram); -- cgit v1.2.3 From eb242d57aa6f93b702b15c40682f2775049c467d Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 16:02:15 +0800 Subject: soc: qcom: gsbi: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210908080216.1301-5-caihuoqing@baidu.com --- drivers/soc/qcom/qcom_gsbi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c index 304afc223a58..290bdefbf28a 100644 --- a/drivers/soc/qcom/qcom_gsbi.c +++ b/drivers/soc/qcom/qcom_gsbi.c @@ -127,7 +127,6 @@ static int gsbi_probe(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; struct device_node *tcsr_node; const struct of_device_id *match; - struct resource *res; void __iomem *base; struct gsbi_info *gsbi; int i, ret; @@ -139,8 +138,7 @@ static int gsbi_probe(struct platform_device *pdev) if (!gsbi) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); -- cgit v1.2.3 From f69a91e376695ae6048934c92f6b7eea6c51cd86 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 16:02:16 +0800 Subject: soc: qcom: rpmh-rsc: Make use of the helper function devm_platform_ioremap_resource_byname() Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210908080216.1301-6-caihuoqing@baidu.com --- drivers/soc/qcom/rpmh-rsc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index e749a2b285d8..3a12a482f6b2 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -910,7 +910,6 @@ static int rpmh_rsc_probe(struct platform_device *pdev) { struct device_node *dn = pdev->dev.of_node; struct rsc_drv *drv; - struct resource *res; char drv_id[10] = {0}; int ret, irq; u32 solver_config; @@ -941,8 +940,7 @@ static int rpmh_rsc_probe(struct platform_device *pdev) drv->name = dev_name(&pdev->dev); snprintf(drv_id, ARRAY_SIZE(drv_id), "drv-%d", drv->id); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, drv_id); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource_byname(pdev, drv_id); if (IS_ERR(base)) return PTR_ERR(base); -- cgit v1.2.3 From 26bc7a6a0beed882032aa7c945e44d7e82887073 Mon Sep 17 00:00:00 2001 From: Len Baker Date: Sun, 8 Aug 2021 14:50:10 +0200 Subject: soc: qcom: pdr: Prefer strscpy over strcpy strcpy() performs no bounds checking on the destination buffer. This could result in linear overflows beyond the end of the buffer, leading to all kinds of misbehaviors. The safe replacement is strscpy(). This is a previous step in the path to remove the strcpy() function entirely from the kernel. Signed-off-by: Len Baker Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210808125012.4715-2-len.baker@gmx.com --- drivers/soc/qcom/pdr_interface.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c index 915d5bc3d46e..fc580a3c4336 100644 --- a/drivers/soc/qcom/pdr_interface.c +++ b/drivers/soc/qcom/pdr_interface.c @@ -131,7 +131,7 @@ static int pdr_register_listener(struct pdr_handle *pdr, return ret; req.enable = enable; - strcpy(req.service_path, pds->service_path); + strscpy(req.service_path, pds->service_path, sizeof(req.service_path)); ret = qmi_send_request(&pdr->notifier_hdl, &pds->addr, &txn, SERVREG_REGISTER_LISTENER_REQ, @@ -257,7 +257,7 @@ static int pdr_send_indack_msg(struct pdr_handle *pdr, struct pdr_service *pds, return ret; req.transaction_id = tid; - strcpy(req.service_path, pds->service_path); + strscpy(req.service_path, pds->service_path, sizeof(req.service_path)); ret = qmi_send_request(&pdr->notifier_hdl, &pds->addr, &txn, SERVREG_SET_ACK_REQ, @@ -406,7 +406,7 @@ static int pdr_locate_service(struct pdr_handle *pdr, struct pdr_service *pds) return -ENOMEM; /* Prepare req message */ - strcpy(req.service_name, pds->service_name); + strscpy(req.service_name, pds->service_name, sizeof(req.service_name)); req.domain_offset_valid = true; req.domain_offset = 0; @@ -531,8 +531,8 @@ struct pdr_service *pdr_add_lookup(struct pdr_handle *pdr, return ERR_PTR(-ENOMEM); pds->service = SERVREG_NOTIFIER_SERVICE; - strcpy(pds->service_name, service_name); - strcpy(pds->service_path, service_path); + strscpy(pds->service_name, service_name, sizeof(pds->service_name)); + strscpy(pds->service_path, service_path, sizeof(pds->service_path)); pds->need_locator_lookup = true; mutex_lock(&pdr->list_lock); @@ -587,7 +587,7 @@ int pdr_restart_pd(struct pdr_handle *pdr, struct pdr_service *pds) break; /* Prepare req message */ - strcpy(req.service_path, pds->service_path); + strscpy(req.service_path, pds->service_path, sizeof(req.service_path)); addr = pds->addr; break; } -- cgit v1.2.3 From 3e035cbd445f98760d828154b25f3c55f577d299 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 14 Sep 2021 09:53:49 +0800 Subject: soc: qcom: smd-rpm: Add QCM2290 compatible Add compatible for QCM2290 SoC support. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210914015349.29295-3-shawn.guo@linaro.org --- drivers/soc/qcom/smd-rpm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index fb4896d7a9a7..30dda1af63c8 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -245,6 +245,7 @@ static const struct of_device_id qcom_smd_rpm_of_match[] = { { .compatible = "qcom,rpm-sdm660" }, { .compatible = "qcom,rpm-sm6115" }, { .compatible = "qcom,rpm-sm6125" }, + { .compatible = "qcom,rpm-qcm2290" }, { .compatible = "qcom,rpm-qcs404" }, {} }; -- cgit v1.2.3 From 3a461009e195c3c17f6af73da310b886991309fd Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Tue, 21 Sep 2021 11:29:42 +0530 Subject: soc: qcom: llcc: Disable MMUHWT retention Disable MMUHWT retention for SC7280 as done for other platforms to avoid more power burn. Fixes: f6a07be63301 ("soc: qcom: llcc: Add configuration data for SC7280") Signed-off-by: Naina Mehta Signed-off-by: Sai Prakash Ranjan Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210921055942.30600-1-saiprakash.ranjan@codeaurora.org --- drivers/soc/qcom/llcc-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index fb471cc4066b..6bf2f1d1f2c5 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -115,7 +115,7 @@ static const struct llcc_slice_config sc7280_data[] = { { LLCC_CMPT, 10, 768, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, { LLCC_GPUHTW, 11, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, { LLCC_GPU, 12, 512, 1, 0, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, - { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 1, 0}, + { LLCC_MMUHWT, 13, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 0, 1, 0}, { LLCC_MDMPNG, 21, 768, 0, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, { LLCC_WLHW, 24, 256, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, -- cgit v1.2.3 From 1a561c521ba901ac86acaf698e79ad6ecedbec2b Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Tue, 21 Sep 2021 16:04:27 +0530 Subject: soc: qcom: smp2p: Add wakeup capability to SMP2P IRQ Remote susbsystems notify fatal crash through smp2p interrupt. When remoteproc crashes it can cause soc to come out of low power state and may not allow again to enter in low power state until crash is handled. Mark smp2p interrupt wakeup capable so that interrupt handler is executed and remoteproc crash can be handled in system resume path. This patch marks interrupt wakeup capable but keeps wakeup disabled by default. User space can enable it based on its requirement for wakeup from suspend. Signed-off-by: Deepak Kumar Singh Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632220467-27410-1-git-send-email-deesin@codeaurora.org --- drivers/soc/qcom/smp2p.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 2df488333be9..38585a7edfe7 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -538,9 +539,26 @@ static int qcom_smp2p_probe(struct platform_device *pdev) goto unwind_interfaces; } + /* + * Treat smp2p interrupt as wakeup source, but keep it disabled + * by default. User space can decide enabling it depending on its + * use cases. For example if remoteproc crashes and device wants + * to handle it immediatedly (e.g. to not miss phone calls) it can + * enable wakeup source from user space, while other devices which + * do not have proper autosleep feature may want to handle it with + * other wakeup events (e.g. Power button) instead waking up immediately. + */ + device_set_wakeup_capable(&pdev->dev, true); + + ret = dev_pm_set_wake_irq(&pdev->dev, irq); + if (ret) + goto set_wake_irq_fail; return 0; +set_wake_irq_fail: + dev_pm_clear_wake_irq(&pdev->dev); + unwind_interfaces: list_for_each_entry(entry, &smp2p->inbound, node) irq_domain_remove(entry->domain); @@ -565,6 +583,8 @@ static int qcom_smp2p_remove(struct platform_device *pdev) struct qcom_smp2p *smp2p = platform_get_drvdata(pdev); struct smp2p_entry *entry; + dev_pm_clear_wake_irq(&pdev->dev); + list_for_each_entry(entry, &smp2p->inbound, node) irq_domain_remove(entry->domain); -- cgit v1.2.3 From 99512191f4f1dd4e0ad92e6f61ffe4d8a22aa3ba Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:28 +0530 Subject: soc: qcom: aoss: Drop power domain support Strip out the load state power-domain support from the driver since the low power mode signalling for the co-processors is now accessible through the direct qmp message send interface. Signed-off-by: Sibi Sankar Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-12-git-send-email-sibis@codeaurora.org --- drivers/soc/qcom/qcom_aoss.c | 107 ------------------------------------------- 1 file changed, 107 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index aac36f0b58e4..34acf58bbb0d 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -2,7 +2,6 @@ /* * Copyright (c) 2019, Linaro Ltd */ -#include #include #include #include @@ -10,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -66,7 +64,6 @@ struct qmp_cooling_device { * @event: wait_queue for synchronization with the IRQ * @tx_lock: provides synchronization between multiple callers of qmp_send() * @qdss_clk: QDSS clock hw struct - * @pd_data: genpd data * @cooling_devs: thermal cooling devices */ struct qmp { @@ -84,17 +81,9 @@ struct qmp { struct mutex tx_lock; struct clk_hw qdss_clk; - struct genpd_onecell_data pd_data; struct qmp_cooling_device *cooling_devs; }; -struct qmp_pd { - struct qmp *qmp; - struct generic_pm_domain pd; -}; - -#define to_qmp_pd_resource(res) container_of(res, struct qmp_pd, pd) - static void qmp_kick(struct qmp *qmp) { mbox_send_message(qmp->mbox_chan, NULL); @@ -320,95 +309,6 @@ static void qmp_qdss_clk_remove(struct qmp *qmp) clk_hw_unregister(&qmp->qdss_clk); } -static int qmp_pd_power_toggle(struct qmp_pd *res, bool enable) -{ - char buf[QMP_MSG_LEN] = {}; - - snprintf(buf, sizeof(buf), - "{class: image, res: load_state, name: %s, val: %s}", - res->pd.name, enable ? "on" : "off"); - return qmp_send(res->qmp, buf, sizeof(buf)); -} - -static int qmp_pd_power_on(struct generic_pm_domain *domain) -{ - return qmp_pd_power_toggle(to_qmp_pd_resource(domain), true); -} - -static int qmp_pd_power_off(struct generic_pm_domain *domain) -{ - return qmp_pd_power_toggle(to_qmp_pd_resource(domain), false); -} - -static const char * const sdm845_resources[] = { - [AOSS_QMP_LS_CDSP] = "cdsp", - [AOSS_QMP_LS_LPASS] = "adsp", - [AOSS_QMP_LS_MODEM] = "modem", - [AOSS_QMP_LS_SLPI] = "slpi", - [AOSS_QMP_LS_SPSS] = "spss", - [AOSS_QMP_LS_VENUS] = "venus", -}; - -static int qmp_pd_add(struct qmp *qmp) -{ - struct genpd_onecell_data *data = &qmp->pd_data; - struct device *dev = qmp->dev; - struct qmp_pd *res; - size_t num = ARRAY_SIZE(sdm845_resources); - int ret; - int i; - - res = devm_kcalloc(dev, num, sizeof(*res), GFP_KERNEL); - if (!res) - return -ENOMEM; - - data->domains = devm_kcalloc(dev, num, sizeof(*data->domains), - GFP_KERNEL); - if (!data->domains) - return -ENOMEM; - - for (i = 0; i < num; i++) { - res[i].qmp = qmp; - res[i].pd.name = sdm845_resources[i]; - res[i].pd.power_on = qmp_pd_power_on; - res[i].pd.power_off = qmp_pd_power_off; - - ret = pm_genpd_init(&res[i].pd, NULL, true); - if (ret < 0) { - dev_err(dev, "failed to init genpd\n"); - goto unroll_genpds; - } - - data->domains[i] = &res[i].pd; - } - - data->num_domains = i; - - ret = of_genpd_add_provider_onecell(dev->of_node, data); - if (ret < 0) - goto unroll_genpds; - - return 0; - -unroll_genpds: - for (i--; i >= 0; i--) - pm_genpd_remove(data->domains[i]); - - return ret; -} - -static void qmp_pd_remove(struct qmp *qmp) -{ - struct genpd_onecell_data *data = &qmp->pd_data; - struct device *dev = qmp->dev; - int i; - - of_genpd_del_provider(dev->of_node); - - for (i = 0; i < data->num_domains; i++) - pm_genpd_remove(data->domains[i]); -} - static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev, unsigned long *state) { @@ -612,10 +512,6 @@ static int qmp_probe(struct platform_device *pdev) if (ret) goto err_close_qmp; - ret = qmp_pd_add(qmp); - if (ret) - goto err_remove_qdss_clk; - ret = qmp_cooling_devices_register(qmp); if (ret) dev_err(&pdev->dev, "failed to register aoss cooling devices\n"); @@ -624,8 +520,6 @@ static int qmp_probe(struct platform_device *pdev) return 0; -err_remove_qdss_clk: - qmp_qdss_clk_remove(qmp); err_close_qmp: qmp_close(qmp); err_free_mbox: @@ -639,7 +533,6 @@ static int qmp_remove(struct platform_device *pdev) struct qmp *qmp = platform_get_drvdata(pdev); qmp_qdss_clk_remove(qmp); - qmp_pd_remove(qmp); qmp_cooling_devices_remove(qmp); qmp_close(qmp); -- cgit v1.2.3 From d1141886c8d72ad77920e6e4b617d366e6e3ee8a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 19 Sep 2021 11:31:12 +0200 Subject: soc: samsung: exynos-chipid: avoid soc_device_to_device() soc_device_to_device() seems to be discouraged [1] so remove it in favor of printing info message with platform device. This will only change the prefix in the info message from "soc soc0: " to "exynos-chipid 10000000.chipid:". [1] https://lore.kernel.org/lkml/20191111052741.GB3176397@kroah.com/ Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sylwester Nawrocki Tested-by: Sylwester Nawrocki Reviewed-by: Alim Akhtar Tested-by: Alim Akhtar Link: https://lore.kernel.org/r/20210919093114.35987-2-krzysztof.kozlowski@canonical.com --- drivers/soc/samsung/exynos-chipid.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 5c1d0f97f766..dcd9a08ce706 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -104,8 +104,7 @@ static int exynos_chipid_probe(struct platform_device *pdev) platform_set_drvdata(pdev, soc_dev); - dev_info(soc_device_to_device(soc_dev), - "Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", + dev_info(&pdev->dev, "Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", soc_dev_attr->soc_id, product_id, revision); return 0; -- cgit v1.2.3 From 1e3e559f8d4e5b4c873414078facb35273ecbf4b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 19 Sep 2021 11:31:13 +0200 Subject: soc: samsung: exynos-chipid: convert to a module Exynos ChipID and ASV (Adaptive Supply Voltage) driver is not essential to system boot and it can successfully be built and loaded as module. This makes core kernel image smaller and reduces the memory footprint when multi-platform kernel is booted on non-Exynos board. Usually it is also distro-friendly. Add multiple authors of the driver since its conversion from mach-exynos, ordered alphabetically by first name. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sylwester Nawrocki Tested-by: Sylwester Nawrocki Reviewed-by: Alim Akhtar Tested-by: Alim Akhtar Link: https://lore.kernel.org/r/20210919093114.35987-3-krzysztof.kozlowski@canonical.com --- drivers/soc/samsung/Kconfig | 3 ++- drivers/soc/samsung/Makefile | 3 ++- drivers/soc/samsung/exynos-chipid.c | 11 ++++++++++- drivers/soc/samsung/exynos5422-asv.c | 1 + 4 files changed, 15 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index 1f643c0f5c93..fe139f26d093 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -13,13 +13,14 @@ config EXYNOS_ASV_ARM depends on EXYNOS_CHIPID config EXYNOS_CHIPID - bool "Exynos ChipID controller and ASV driver" if COMPILE_TEST + tristate "Exynos ChipID controller and ASV driver" if COMPILE_TEST depends on ARCH_EXYNOS || COMPILE_TEST select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS select MFD_SYSCON select SOC_BUS help Support for Samsung Exynos SoC ChipID and Adaptive Supply Voltage. + This driver can also be built as module (exynos_chipid). config EXYNOS_PMU bool "Exynos PMU controller driver" if COMPILE_TEST diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 0c523a8de4eb..2ae4bea804cf 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -1,8 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o +obj-$(CONFIG_EXYNOS_CHIPID) += exynos_chipid.o +exynos_chipid-y += exynos-chipid.o exynos-asv.o -obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o exynos-asv.o obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \ diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index dcd9a08ce706..b2627a3a127a 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,7 @@ static const struct of_device_id exynos_chipid_of_device_ids[] = { { .compatible = "samsung,exynos4210-chipid" }, {} }; +MODULE_DEVICE_TABLE(of, exynos_chipid_of_device_ids); static struct platform_driver exynos_chipid_driver = { .driver = { @@ -137,4 +139,11 @@ static struct platform_driver exynos_chipid_driver = { .probe = exynos_chipid_probe, .remove = exynos_chipid_remove, }; -builtin_platform_driver(exynos_chipid_driver); +module_platform_driver(exynos_chipid_driver); + +MODULE_DESCRIPTION("Samsung Exynos ChipID controller and ASV driver"); +MODULE_AUTHOR("Bartlomiej Zolnierkiewicz "); +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_AUTHOR("Pankaj Dubey "); +MODULE_AUTHOR("Sylwester Nawrocki "); +MODULE_LICENSE("GPL"); diff --git a/drivers/soc/samsung/exynos5422-asv.c b/drivers/soc/samsung/exynos5422-asv.c index ca409a976e34..475ae5276529 100644 --- a/drivers/soc/samsung/exynos5422-asv.c +++ b/drivers/soc/samsung/exynos5422-asv.c @@ -503,3 +503,4 @@ int exynos5422_asv_init(struct exynos_asv *asv) return 0; } +EXPORT_SYMBOL_GPL(exynos5422_asv_init); -- cgit v1.2.3 From 140bbfe7cd4be0aa6543f94d3994e4774b325abc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 19 Sep 2021 11:31:14 +0200 Subject: soc: samsung: exynos-chipid: do not enforce built-in After converting the Exynos ChipID and ASV driver to a module, allow to actually choose it to be a module, while being a default built-in. The side effect is that driver could be now entirely disabled even for kernel with ARCH_EXYNOS, but this is not a critical issue because driver is not necessary for the proper platform boot. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sylwester Nawrocki Tested-by: Sylwester Nawrocki Reviewed-by: Alim Akhtar Tested-by: Alim Akhtar Link: https://lore.kernel.org/r/20210919093114.35987-4-krzysztof.kozlowski@canonical.com --- arch/arm/mach-exynos/Kconfig | 1 - drivers/soc/samsung/Kconfig | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 5a48abac6af4..30f930e20599 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -13,7 +13,6 @@ menuconfig ARCH_EXYNOS select ARM_GIC select EXYNOS_IRQ_COMBINER select COMMON_CLK_SAMSUNG - select EXYNOS_CHIPID select EXYNOS_THERMAL select EXYNOS_PMU select EXYNOS_SROM diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index fe139f26d093..e2cedef1e8d1 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -13,8 +13,9 @@ config EXYNOS_ASV_ARM depends on EXYNOS_CHIPID config EXYNOS_CHIPID - tristate "Exynos ChipID controller and ASV driver" if COMPILE_TEST + tristate "Exynos ChipID controller and ASV driver" depends on ARCH_EXYNOS || COMPILE_TEST + default ARCH_EXYNOS select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS select MFD_SYSCON select SOC_BUS -- cgit v1.2.3 From 34a01d9ea7c4981e19c9e926f5e293b011ecd5a3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 7 Sep 2021 04:38:29 +0200 Subject: soc: imx: gpcv2: Turn domain->pgc into bitfield There is currently the MX8MM GPU domain, which is in fact a composite domain for both GPU2D and GPU3D. To correctly configure this domain, it is necessary to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible. Turn the domain->pgc from value into bitfield and use for_each_set_bit() to iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL register array. This way it is possible to configure all GPC_PGC_nCTRL registers required in a particular domain. This is a preparatory patch, no functional change. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut Cc: Frieder Schrempf Cc: Lucas Stach Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 72 ++++++++++++++++++++++++++----------------------- 1 file changed, 38 insertions(+), 34 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 34a9ac1f2b9b..acd8734d960a 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -192,7 +192,7 @@ struct imx_pgc_domain { struct clk_bulk_data *clks; int num_clks; - unsigned int pgc; + unsigned long pgc; const struct { u32 pxx; @@ -220,7 +220,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd) static int imx_pgc_power_up(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); - u32 reg_val; + u32 reg_val, pgc; int ret; ret = pm_runtime_get_sync(domain->dev); @@ -262,8 +262,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } /* disable power control */ - regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR); + for_each_set_bit(pgc, &domain->pgc, 32) { + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR); + } } reset_control_assert(domain->reset); @@ -311,7 +313,7 @@ out_put_pm: static int imx_pgc_power_down(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); - u32 reg_val; + u32 reg_val, pgc; int ret; /* Enable reset clocks for all devices in the domain */ @@ -338,8 +340,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) if (domain->bits.pxx) { /* enable power control */ - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + for_each_set_bit(pgc, &domain->pgc, 32) { + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + } /* request the domain to power down */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, @@ -389,7 +393,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, }, .voltage = 1000000, - .pgc = IMX7_PGC_MIPI, + .pgc = BIT(IMX7_PGC_MIPI), }, [IMX7_POWER_DOMAIN_PCIE_PHY] = { @@ -401,7 +405,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, }, .voltage = 1000000, - .pgc = IMX7_PGC_PCIE, + .pgc = BIT(IMX7_PGC_PCIE), }, [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { @@ -413,7 +417,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, }, .voltage = 1200000, - .pgc = IMX7_PGC_USB_HSIC, + .pgc = BIT(IMX7_PGC_USB_HSIC), }, }; @@ -448,7 +452,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_SW_Pxx_REQ, .map = IMX8M_MIPI_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI, + .pgc = BIT(IMX8M_PGC_MIPI), }, [IMX8M_POWER_DOMAIN_PCIE1] = { @@ -459,7 +463,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_PCIE1_SW_Pxx_REQ, .map = IMX8M_PCIE1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_PCIE1, + .pgc = BIT(IMX8M_PGC_PCIE1), }, [IMX8M_POWER_DOMAIN_USB_OTG1] = { @@ -470,7 +474,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_OTG1_SW_Pxx_REQ, .map = IMX8M_OTG1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_OTG1, + .pgc = BIT(IMX8M_PGC_OTG1), }, [IMX8M_POWER_DOMAIN_USB_OTG2] = { @@ -481,7 +485,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_OTG2_SW_Pxx_REQ, .map = IMX8M_OTG2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_OTG2, + .pgc = BIT(IMX8M_PGC_OTG2), }, [IMX8M_POWER_DOMAIN_DDR1] = { @@ -492,7 +496,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_DDR1_SW_Pxx_REQ, .map = IMX8M_DDR2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_DDR1, + .pgc = BIT(IMX8M_PGC_DDR1), }, [IMX8M_POWER_DOMAIN_GPU] = { @@ -505,7 +509,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_GPU_HSK_PWRDNREQN, .hskack = IMX8M_GPU_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_GPU, + .pgc = BIT(IMX8M_PGC_GPU), }, [IMX8M_POWER_DOMAIN_VPU] = { @@ -518,7 +522,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_VPU_HSK_PWRDNREQN, .hskack = IMX8M_VPU_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_VPU, + .pgc = BIT(IMX8M_PGC_VPU), }, [IMX8M_POWER_DOMAIN_DISP] = { @@ -531,7 +535,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_DISP_HSK_PWRDNREQN, .hskack = IMX8M_DISP_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_DISP, + .pgc = BIT(IMX8M_PGC_DISP), }, [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { @@ -542,7 +546,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, .map = IMX8M_MIPI_CSI1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI_CSI1, + .pgc = BIT(IMX8M_PGC_MIPI_CSI1), }, [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { @@ -553,7 +557,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, .map = IMX8M_MIPI_CSI2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI_CSI2, + .pgc = BIT(IMX8M_PGC_MIPI_CSI2), }, [IMX8M_POWER_DOMAIN_PCIE2] = { @@ -564,7 +568,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_PCIE2_SW_Pxx_REQ, .map = IMX8M_PCIE2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_PCIE2, + .pgc = BIT(IMX8M_PGC_PCIE2), }, }; @@ -627,7 +631,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_PCIE_SW_Pxx_REQ, .map = IMX8MM_PCIE_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_PCIE, + .pgc = BIT(IMX8MM_PGC_PCIE), }, [IMX8MM_POWER_DOMAIN_OTG1] = { @@ -638,7 +642,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_OTG1_SW_Pxx_REQ, .map = IMX8MM_OTG1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_OTG1, + .pgc = BIT(IMX8MM_PGC_OTG1), }, [IMX8MM_POWER_DOMAIN_OTG2] = { @@ -649,7 +653,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_OTG2_SW_Pxx_REQ, .map = IMX8MM_OTG2_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_OTG2, + .pgc = BIT(IMX8MM_PGC_OTG2), }, [IMX8MM_POWER_DOMAIN_GPUMIX] = { @@ -662,7 +666,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_GPUMIX, + .pgc = BIT(IMX8MM_PGC_GPUMIX), }, [IMX8MM_POWER_DOMAIN_GPU] = { @@ -675,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, .hskack = IMX8MM_GPU_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_GPU2D, + .pgc = BIT(IMX8MM_PGC_GPU2D), }, [IMX8MM_POWER_DOMAIN_VPUMIX] = { @@ -688,7 +692,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_VPUMIX, + .pgc = BIT(IMX8MM_PGC_VPUMIX), }, [IMX8MM_POWER_DOMAIN_VPUG1] = { @@ -699,7 +703,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, .map = IMX8MM_VPUG1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUG1, + .pgc = BIT(IMX8MM_PGC_VPUG1), }, [IMX8MM_POWER_DOMAIN_VPUG2] = { @@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, .map = IMX8MM_VPUG2_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUG2, + .pgc = BIT(IMX8MM_PGC_VPUG2), }, [IMX8MM_POWER_DOMAIN_VPUH1] = { @@ -721,7 +725,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, .map = IMX8MM_VPUH1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUH1, + .pgc = BIT(IMX8MM_PGC_VPUH1), }, [IMX8MM_POWER_DOMAIN_DISPMIX] = { @@ -734,7 +738,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_DISPMIX, + .pgc = BIT(IMX8MM_PGC_DISPMIX), }, [IMX8MM_POWER_DOMAIN_MIPI] = { @@ -745,7 +749,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_MIPI_SW_Pxx_REQ, .map = IMX8MM_MIPI_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_MIPI, + .pgc = BIT(IMX8MM_PGC_MIPI), }, }; @@ -812,7 +816,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .pxx = IMX8MN_OTG1_SW_Pxx_REQ, .map = IMX8MN_OTG1_A53_DOMAIN, }, - .pgc = IMX8MN_PGC_OTG1, + .pgc = BIT(IMX8MN_PGC_OTG1), }, [IMX8MN_POWER_DOMAIN_GPUMIX] = { @@ -825,7 +829,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .hskreq = IMX8MN_GPUMIX_HSK_PWRDNREQN, .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MN_PGC_GPUMIX, + .pgc = BIT(IMX8MN_PGC_GPUMIX), }, }; -- cgit v1.2.3 From 19791f518f10b9cbf0a0171166373b4bf3d4be47 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 7 Sep 2021 04:38:30 +0200 Subject: soc: imx: gpcv2: Set both GPC_PGC_nCTRL(GPU_2D|GPU_3D) for MX8MM GPU domain To bring up the MX8MM GPU domain, it is necessary to configure both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers. Without this configuration, the system might hang on boot when bringing up the GPU power domain. This is sporadically observed on multiple disparate systems. Add the GPU3D bit into MX8MM GPU domain pgc bitfield, so that both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) registers are configured when bringing up the GPU domain. This fixes the sporadic hang. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut Cc: Frieder Schrempf Cc: Lucas Stach Cc: NXP Linux Team Cc: Peng Fan Cc: Shawn Guo Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index acd8734d960a..46aac23a35e3 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -679,7 +679,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, .hskack = IMX8MM_GPU_HSK_PWRDNACKN, }, - .pgc = BIT(IMX8MM_PGC_GPU2D), + .pgc = BIT(IMX8MM_PGC_GPU2D) | BIT(IMX8MM_PGC_GPU3D), }, [IMX8MM_POWER_DOMAIN_VPUMIX] = { -- cgit v1.2.3 From 33110589a3f0ed8e2c4c8213bc44858a93cefc01 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Mon, 27 Sep 2021 01:40:26 +0300 Subject: soc/tegra: pmc: Disable PMC state syncing Disable PMC state syncing in order to ensure that we won't break older kernels once device-trees will be updated with the addition of the power domains. This also allows to apply device-tree PM patches independently from the driver patches. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 50091c4ec948..fb8faf7b226a 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -360,6 +360,7 @@ struct tegra_pmc_soc { unsigned int num_pmc_clks; bool has_blink_output; bool has_usb_sleepwalk; + bool supports_core_domain; }; /** @@ -3041,6 +3042,7 @@ static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, } static const struct tegra_pmc_soc tegra20_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra20_powergates), .powergates = tegra20_powergates, .num_cpu_powergates = 0, @@ -3101,6 +3103,7 @@ static const char * const tegra30_reset_sources[] = { }; static const struct tegra_pmc_soc tegra30_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra30_powergates), .powergates = tegra30_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), @@ -3157,6 +3160,7 @@ static const u8 tegra114_cpu_powergates[] = { }; static const struct tegra_pmc_soc tegra114_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra114_powergates), .powergates = tegra114_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), @@ -3273,6 +3277,7 @@ static const struct pinctrl_pin_desc tegra124_pin_descs[] = { }; static const struct tegra_pmc_soc tegra124_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra124_powergates), .powergates = tegra124_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), @@ -3398,6 +3403,7 @@ static const struct tegra_wake_event tegra210_wake_events[] = { }; static const struct tegra_pmc_soc tegra210_pmc_soc = { + .supports_core_domain = false, .num_powergates = ARRAY_SIZE(tegra210_powergates), .powergates = tegra210_powergates, .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), @@ -3555,6 +3561,7 @@ static const struct tegra_wake_event tegra186_wake_events[] = { }; static const struct tegra_pmc_soc tegra186_pmc_soc = { + .supports_core_domain = false, .num_powergates = 0, .powergates = NULL, .num_cpu_powergates = 0, @@ -3689,6 +3696,7 @@ static const struct tegra_wake_event tegra194_wake_events[] = { }; static const struct tegra_pmc_soc tegra194_pmc_soc = { + .supports_core_domain = false, .num_powergates = 0, .powergates = NULL, .num_cpu_powergates = 0, @@ -3757,6 +3765,7 @@ static const char * const tegra234_reset_sources[] = { }; static const struct tegra_pmc_soc tegra234_pmc_soc = { + .supports_core_domain = false, .num_powergates = 0, .powergates = NULL, .num_cpu_powergates = 0, @@ -3803,6 +3812,14 @@ static void tegra_pmc_sync_state(struct device *dev) { int err; + /* + * Newer device-trees have power domains, but we need to prepare all + * device drivers with runtime PM and OPP support first, otherwise + * state syncing is unsafe. + */ + if (!pmc->soc->supports_core_domain) + return; + /* * Older device-trees don't have core PD, and thus, there are * no dependencies that will block the state syncing. We shouldn't -- cgit v1.2.3 From ceba814b37d0f07419068225fe49f0e69f9602f9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Sun, 12 Sep 2021 21:17:14 +0300 Subject: soc/tegra: pmc: Expose USB regmap to all SoCs All Tegra SoCs prior to Tegra186 have USB power controls within the Power Management controller. These controls need to be configured by USB driver. Expose the regmap to these SoCs. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index fb8faf7b226a..2ad7b3bceb80 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3067,7 +3067,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, }; static const char * const tegra30_powergates[] = { @@ -3128,7 +3128,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, }; static const char * const tegra114_powergates[] = { @@ -3185,7 +3185,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, }; static const char * const tegra124_powergates[] = { -- cgit v1.2.3 From f617a8717657e9142de02e54c8e6c885c569692d Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Fri, 24 Sep 2021 11:01:46 -0300 Subject: imx: soc: Select REGMAP_MMIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The imx-gpcv2 driver needs Regmap MMIO. Select it, and fix: drivers/soc/imx/gpcv2.c:420:34: error: array type has incomplete element type ‘struct regmap_range’ 420 | static const struct regmap_range imx7_yes_ranges[] = { | ^~~~~~~~~~~~~~~ drivers/soc/imx/gpcv2.c:421:17: error: implicit declaration of function ‘regmap_reg_range’; did you mean ‘remap_pfn_range’? [-Werror=implicit-function-declaration] 421 | regmap_reg_range(GPC_LPCR_A_CORE_BSC, | ^~~~~~~~~~~~~~~~ | remap_pfn_range Signed-off-by: Ezequiel Garcia Signed-off-by: Shawn Guo --- drivers/soc/imx/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/Kconfig b/drivers/soc/imx/Kconfig index 05812f8ae734..a840494e849a 100644 --- a/drivers/soc/imx/Kconfig +++ b/drivers/soc/imx/Kconfig @@ -6,6 +6,7 @@ config IMX_GPCV2_PM_DOMAINS depends on ARCH_MXC || (COMPILE_TEST && OF) depends on PM select PM_GENERIC_DOMAINS + select REGMAP_MMIO default y if SOC_IMX7D config SOC_IMX8M -- cgit v1.2.3 From 8da8bd5399cfc2ff98514a6b31a3aa2159516fe6 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 14:48:52 +0200 Subject: soc: imx: gpcv2: allow to disable individual power domains Some board designs don't supply power to all of the power domains, as they are not used anyways. In that case we must make sure to not touch those power domains at all, as trying to power up a domain that has no power supplied to it will obviously end in a system crash. Allow to disable those domains via the standard DT status property. Signed-off-by: Lucas Stach Reviewed-By: Tim Harvey Tested-By: Tim Harvey Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 46aac23a35e3..39a581f9b4ac 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -990,6 +990,9 @@ static int imx_gpcv2_probe(struct platform_device *pdev) struct imx_pgc_domain *domain; u32 domain_index; + if (!of_device_is_available(np)) + continue; + ret = of_property_read_u32(np, "reg", &domain_index); if (ret) { dev_err(dev, "Failed to read 'reg' property\n"); -- cgit v1.2.3 From 2b2f106eb55276a60a89ac27a52d0d738b57a546 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:37 +0200 Subject: Revert "soc: imx: gpcv2: move reset assert after requesting domain power up" This reverts commit a77ebdd9f553. It turns out that the VPU domain has no different requirements, even though the downstream ATF implementation seems to suggest otherwise. Powering on the domain with the reset asserted works fine. As the changed sequence has caused sporadic issues with the GPU domains, just revert the change to go back to the working sequence. Cc: # 5.14 Signed-off-by: Lucas Stach Acked-by: Peng Fan Tested-by: Adam Ford #imx8mm-beacon Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 39a581f9b4ac..7fbf1f25b48e 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -244,6 +244,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) goto out_regulator_disable; } + reset_control_assert(domain->reset); + if (domain->bits.pxx) { /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -268,8 +270,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } } - reset_control_assert(domain->reset); - /* delay for reset to propagate */ udelay(5); -- cgit v1.2.3 From fadf79a07b48af66e367b49c3a445a1282148fcf Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:40 +0200 Subject: soc: imx: gpcv2: add lockdep annotation Some of the GPCv2 power domains are nested inside each other without visibility to lockdep at the genpd level, as they are in separate driver instances and don't have a parent/child power-domain relationship. Add a subclass annotation to the nested domains to let lockdep know that it is okay to take the genpd lock in a nested fashion. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 7fbf1f25b48e..fcea95317287 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -898,6 +898,10 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) goto out_domain_unmap; } + if (IS_ENABLED(CONFIG_LOCKDEP) && + of_property_read_bool(domain->dev->of_node, "power-domains")) + lockdep_set_subclass(&domain->genpd.mlock, 1); + ret = of_genpd_add_provider_simple(domain->dev->of_node, &domain->genpd); if (ret) { -- cgit v1.2.3 From 18c98573a4cf2dc183cd884cec23869ba0c9fc1b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:41 +0200 Subject: soc: imx: gpcv2: add domain option to keep domain clocks enabled Some of the MIX domains are using clocks to drive the bus bridges. Those must be enabled at all times, as long as the domain is powered up and they don't have any other consumer than the power domain. Add an option to keep the clocks attached to a domain enabled as long as the domain is power up and only disable them after the domain is powered down. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index fcea95317287..e5a98107ad56 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -202,6 +202,7 @@ struct imx_pgc_domain { } bits; const int voltage; + const bool keep_clocks; struct device *dev; }; @@ -295,7 +296,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } /* Disable reset clocks for all devices in the domain */ - clk_bulk_disable_unprepare(domain->num_clks, domain->clks); + if (!domain->keep_clocks) + clk_bulk_disable_unprepare(domain->num_clks, domain->clks); return 0; @@ -317,10 +319,12 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) int ret; /* Enable reset clocks for all devices in the domain */ - ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); - if (ret) { - dev_err(domain->dev, "failed to enable reset clocks\n"); - return ret; + if (!domain->keep_clocks) { + ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks); + if (ret) { + dev_err(domain->dev, "failed to enable reset clocks\n"); + return ret; + } } /* request the ADB400 to power down */ -- cgit v1.2.3 From 656ade7aa42a2c6d08b3c5ddff074b54d025ccc2 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:42 +0200 Subject: soc: imx: gpcv2: keep i.MX8M* bus clocks enabled Annotate the domains with bus clocks to keep those clocks enabled as long as the domain is active. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index e5a98107ad56..abf840609c56 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -527,6 +527,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskack = IMX8M_VPU_HSK_PWRDNACKN, }, .pgc = BIT(IMX8M_PGC_VPU), + .keep_clocks = true, }, [IMX8M_POWER_DOMAIN_DISP] = { @@ -625,6 +626,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_HSIO_HSK_PWRDNREQN, .hskack = IMX8MM_HSIO_HSK_PWRDNACKN, }, + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_PCIE] = { @@ -671,6 +673,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MM_PGC_GPUMIX), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_GPU] = { @@ -697,6 +700,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MM_PGC_VPUMIX), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_VPUG1] = { @@ -743,6 +747,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, }, .pgc = BIT(IMX8MM_PGC_DISPMIX), + .keep_clocks = true, }, [IMX8MM_POWER_DOMAIN_MIPI] = { @@ -810,6 +815,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { .hskreq = IMX8MN_HSIO_HSK_PWRDNREQN, .hskack = IMX8MN_HSIO_HSK_PWRDNACKN, }, + .keep_clocks = true, }, [IMX8MN_POWER_DOMAIN_OTG1] = { -- cgit v1.2.3 From da4112230f86558f7d3b2cb261e71160e4f88849 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:43 +0200 Subject: soc: imx: gpcv2: support system suspend/resume Our usage of runtime PM to control the hierarchy of power domains is slightly unusual and means that powering up a domain may fail in early system resume, as runtime PM is still disallowed at this stage. However the system suspend/resume path takes care of powering down/up the power domains in the order defined by the device parent/child and power-domain provider/consumer hierarachy. So we can just runtime resume all our power-domain devices to allow the power-up to work properly in the resume path. System suspend will still disable all domains as intended. Signed-off-by: Lucas Stach Acked-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index abf840609c56..b8d52d8d29db 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -948,6 +948,36 @@ static int imx_pgc_domain_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM_SLEEP +static int imx_pgc_domain_suspend(struct device *dev) +{ + int ret; + + /* + * This may look strange, but is done so the generic PM_SLEEP code + * can power down our domain and more importantly power it up again + * after resume, without tripping over our usage of runtime PM to + * power up/down the nested domains. + */ + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + return 0; +} + +static int imx_pgc_domain_resume(struct device *dev) +{ + return pm_runtime_put(dev); +} +#endif + +static const struct dev_pm_ops imx_pgc_domain_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(imx_pgc_domain_suspend, imx_pgc_domain_resume) +}; + static const struct platform_device_id imx_pgc_domain_id[] = { { "imx-pgc-domain", }, { }, @@ -956,6 +986,7 @@ static const struct platform_device_id imx_pgc_domain_id[] = { static struct platform_driver imx_pgc_domain_driver = { .driver = { .name = "imx-pgc", + .pm = &imx_pgc_domain_pm_ops, }, .probe = imx_pgc_domain_probe, .remove = imx_pgc_domain_remove, -- cgit v1.2.3 From 2684ac05a8c4d2d5c49e6c11eb6206b30a284813 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:46 +0200 Subject: soc: imx: add i.MX8M blk-ctrl driver This adds a driver for the blk-ctrl blocks found in the i.MX8M* line of SoCs. The blk-ctrl is a top-level peripheral located in the various *MIX power domains and interacts with the GPC power controller to provide the peripherals in the power domain access to the NoC and ensures that those peripherals are properly reset when their respective power domain is brought back to life. Software needs to do different things to make the bus handshake happen after the GPC *MIX domain is powered up and before it is powered down. As the requirements are quite different between the various blk-ctrls there is a callback function provided to hook in the proper sequence. The peripheral domains are quite uniform, they handle the soft clock enables and resets in the blk-ctrl address space and sequencing with the upstream GPC power domains. Signed-off-by: Lucas Stach Acked-by: Frieder Schrempf Reviewed-by: Philipp Zabel Signed-off-by: Shawn Guo --- drivers/soc/imx/Makefile | 1 + drivers/soc/imx/imx8m-blk-ctrl.c | 453 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 454 insertions(+) create mode 100644 drivers/soc/imx/imx8m-blk-ctrl.c (limited to 'drivers/soc') diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 078dc918f4f3..8a707077914c 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -5,3 +5,4 @@ endif obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o +obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c new file mode 100644 index 000000000000..f8db0ebd02c3 --- /dev/null +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2021 Pengutronix, Lucas Stach + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define BLK_SFT_RSTN 0x0 +#define BLK_CLK_EN 0x4 + +struct imx8m_blk_ctrl_domain; + +struct imx8m_blk_ctrl { + struct device *dev; + struct notifier_block power_nb; + struct device *bus_power_dev; + struct regmap *regmap; + struct imx8m_blk_ctrl_domain *domains; + struct genpd_onecell_data onecell_data; +}; + +struct imx8m_blk_ctrl_domain_data { + const char *name; + const char * const *clk_names; + int num_clks; + const char *gpc_name; + u32 rst_mask; + u32 clk_mask; +}; + +#define DOMAIN_MAX_CLKS 3 + +struct imx8m_blk_ctrl_domain { + struct generic_pm_domain genpd; + const struct imx8m_blk_ctrl_domain_data *data; + struct clk_bulk_data clks[DOMAIN_MAX_CLKS]; + struct device *power_dev; + struct imx8m_blk_ctrl *bc; +}; + +struct imx8m_blk_ctrl_data { + int max_reg; + notifier_fn_t power_notifier_fn; + const struct imx8m_blk_ctrl_domain_data *domains; + int num_domains; +}; + +static inline struct imx8m_blk_ctrl_domain * +to_imx8m_blk_ctrl_domain(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct imx8m_blk_ctrl_domain, genpd); +} + +static int imx8m_blk_ctrl_power_on(struct generic_pm_domain *genpd) +{ + struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); + const struct imx8m_blk_ctrl_domain_data *data = domain->data; + struct imx8m_blk_ctrl *bc = domain->bc; + int ret; + + /* make sure bus domain is awake */ + ret = pm_runtime_get_sync(bc->bus_power_dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->bus_power_dev); + dev_err(bc->dev, "failed to power up bus domain\n"); + return ret; + } + + /* put devices into reset */ + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + + /* enable upstream and blk-ctrl clocks to allow reset to propagate */ + ret = clk_bulk_prepare_enable(data->num_clks, domain->clks); + if (ret) { + dev_err(bc->dev, "failed to enable clocks\n"); + goto bus_put; + } + regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); + + /* power up upstream GPC domain */ + ret = pm_runtime_get_sync(domain->power_dev); + if (ret < 0) { + dev_err(bc->dev, "failed to power up peripheral domain\n"); + goto clk_disable; + } + + /* wait for reset to propagate */ + udelay(5); + + /* release reset */ + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + + /* disable upstream clocks */ + clk_bulk_disable_unprepare(data->num_clks, domain->clks); + + return 0; + +clk_disable: + clk_bulk_disable_unprepare(data->num_clks, domain->clks); +bus_put: + pm_runtime_put(bc->bus_power_dev); + + return ret; +} + +static int imx8m_blk_ctrl_power_off(struct generic_pm_domain *genpd) +{ + struct imx8m_blk_ctrl_domain *domain = to_imx8m_blk_ctrl_domain(genpd); + const struct imx8m_blk_ctrl_domain_data *data = domain->data; + struct imx8m_blk_ctrl *bc = domain->bc; + + /* put devices into reset and disable clocks */ + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); + regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); + + /* power down upstream GPC domain */ + pm_runtime_put(domain->power_dev); + + /* allow bus domain to suspend */ + pm_runtime_put(bc->bus_power_dev); + + return 0; +} + +static struct generic_pm_domain * +imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data) +{ + struct genpd_onecell_data *onecell_data = data; + unsigned int index = args->args[0]; + + if (args->args_count != 1 || + index > onecell_data->num_domains) + return ERR_PTR(-EINVAL); + + return onecell_data->domains[index]; +} + +static struct lock_class_key blk_ctrl_genpd_lock_class; + +static int imx8m_blk_ctrl_probe(struct platform_device *pdev) +{ + const struct imx8m_blk_ctrl_data *bc_data; + struct device *dev = &pdev->dev; + struct imx8m_blk_ctrl *bc; + void __iomem *base; + int i, ret; + + struct regmap_config regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + }; + + bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL); + if (!bc) + return -ENOMEM; + + bc->dev = dev; + + bc_data = of_device_get_match_data(dev); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap_config.max_register = bc_data->max_reg; + bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config); + if (IS_ERR(bc->regmap)) + return dev_err_probe(dev, PTR_ERR(bc->regmap), + "failed to init regmap\n"); + + bc->domains = devm_kcalloc(dev, bc_data->num_domains, + sizeof(struct imx8m_blk_ctrl_domain), + GFP_KERNEL); + if (!bc->domains) + return -ENOMEM; + + bc->onecell_data.num_domains = bc_data->num_domains; + bc->onecell_data.xlate = imx8m_blk_ctrl_xlate; + bc->onecell_data.domains = + devm_kcalloc(dev, bc_data->num_domains, + sizeof(struct generic_pm_domain *), GFP_KERNEL); + if (!bc->onecell_data.domains) + return -ENOMEM; + + bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus"); + if (IS_ERR(bc->bus_power_dev)) + return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev), + "failed to attach power domain\n"); + + for (i = 0; i < bc_data->num_domains; i++) { + const struct imx8m_blk_ctrl_domain_data *data = &bc_data->domains[i]; + struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; + int j; + + domain->data = data; + + for (j = 0; j < data->num_clks; j++) + domain->clks[j].id = data->clk_names[j]; + + ret = devm_clk_bulk_get(dev, data->num_clks, domain->clks); + if (ret) { + dev_err_probe(dev, ret, "failed to get clock\n"); + goto cleanup_pds; + } + + domain->power_dev = + dev_pm_domain_attach_by_name(dev, data->gpc_name); + if (IS_ERR(domain->power_dev)) { + dev_err_probe(dev, PTR_ERR(domain->power_dev), + "failed to attach power domain\n"); + ret = PTR_ERR(domain->power_dev); + goto cleanup_pds; + } + + domain->genpd.name = data->name; + domain->genpd.power_on = imx8m_blk_ctrl_power_on; + domain->genpd.power_off = imx8m_blk_ctrl_power_off; + domain->bc = bc; + + ret = pm_genpd_init(&domain->genpd, NULL, true); + if (ret) { + dev_err_probe(dev, ret, "failed to init power domain\n"); + dev_pm_domain_detach(domain->power_dev, true); + goto cleanup_pds; + } + + /* + * We use runtime PM to trigger power on/off of the upstream GPC + * domain, as a strict hierarchical parent/child power domain + * setup doesn't allow us to meet the sequencing requirements. + * This means we have nested locking of genpd locks, without the + * nesting being visible at the genpd level, so we need a + * separate lock class to make lockdep aware of the fact that + * this are separate domain locks that can be nested without a + * self-deadlock. + */ + lockdep_set_class(&domain->genpd.mlock, + &blk_ctrl_genpd_lock_class); + + bc->onecell_data.domains[i] = &domain->genpd; + } + + ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data); + if (ret) { + dev_err_probe(dev, ret, "failed to add power domain provider\n"); + goto cleanup_pds; + } + + bc->power_nb.notifier_call = bc_data->power_notifier_fn; + ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb); + if (ret) { + dev_err_probe(dev, ret, "failed to add power notifier\n"); + goto cleanup_provider; + } + + dev_set_drvdata(dev, bc); + + return 0; + +cleanup_provider: + of_genpd_del_provider(dev->of_node); +cleanup_pds: + for (i--; i >= 0; i--) { + pm_genpd_remove(&bc->domains[i].genpd); + dev_pm_domain_detach(bc->domains[i].power_dev, true); + } + + dev_pm_domain_detach(bc->bus_power_dev, true); + + return ret; +} + +static int imx8m_blk_ctrl_remove(struct platform_device *pdev) +{ + struct imx8m_blk_ctrl *bc = dev_get_drvdata(&pdev->dev); + int i; + + of_genpd_del_provider(pdev->dev.of_node); + + for (i = 0; bc->onecell_data.num_domains; i++) { + struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; + + pm_genpd_remove(&domain->genpd); + dev_pm_domain_detach(domain->power_dev, true); + } + + dev_pm_genpd_remove_notifier(bc->bus_power_dev); + + dev_pm_domain_detach(bc->bus_power_dev, true); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int imx8m_blk_ctrl_suspend(struct device *dev) +{ + struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); + int ret, i; + + /* + * This may look strange, but is done so the generic PM_SLEEP code + * can power down our domains and more importantly power them up again + * after resume, without tripping over our usage of runtime PM to + * control the upstream GPC domains. Things happen in the right order + * in the system suspend/resume paths due to the device parent/child + * hierarchy. + */ + ret = pm_runtime_get_sync(bc->bus_power_dev); + if (ret < 0) { + pm_runtime_put_noidle(bc->bus_power_dev); + return ret; + } + + for (i = 0; i < bc->onecell_data.num_domains; i++) { + struct imx8m_blk_ctrl_domain *domain = &bc->domains[i]; + + ret = pm_runtime_get_sync(domain->power_dev); + if (ret < 0) { + pm_runtime_put_noidle(domain->power_dev); + goto out_fail; + } + } + + return 0; + +out_fail: + for (i--; i >= 0; i--) + pm_runtime_put(bc->domains[i].power_dev); + + pm_runtime_put(bc->bus_power_dev); + + return ret; +} + +static int imx8m_blk_ctrl_resume(struct device *dev) +{ + struct imx8m_blk_ctrl *bc = dev_get_drvdata(dev); + int i; + + for (i = 0; i < bc->onecell_data.num_domains; i++) + pm_runtime_put(bc->domains[i].power_dev); + + pm_runtime_put(bc->bus_power_dev); + + return 0; +} +#endif + +static const struct dev_pm_ops imx8m_blk_ctrl_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(imx8m_blk_ctrl_suspend, imx8m_blk_ctrl_resume) +}; + +static int imx8mm_vpu_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* + * The ADB in the VPUMIX domain has no separate reset and clock + * enable bits, but is ungated together with the VPU clocks. To + * allow the handshake with the GPC to progress we put the VPUs + * in reset and ungate the clocks. + */ + regmap_clear_bits(bc->regmap, BLK_SFT_RSTN, BIT(0) | BIT(1) | BIT(2)); + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2)); + + if (action == GENPD_NOTIFY_ON) { + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + udelay(5); + + /* set "fuse" bits to enable the VPUs */ + regmap_set_bits(bc->regmap, 0x8, 0xffffffff); + regmap_set_bits(bc->regmap, 0xc, 0xffffffff); + regmap_set_bits(bc->regmap, 0x10, 0xffffffff); + regmap_set_bits(bc->regmap, 0x14, 0xffffffff); + } + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mm_vpu_blk_ctl_domain_data[] = { + [IMX8MM_VPUBLK_PD_G1] = { + .name = "vpublk-g1", + .clk_names = (const char *[]){ "g1", }, + .num_clks = 1, + .gpc_name = "g1", + .rst_mask = BIT(1), + .clk_mask = BIT(1), + }, + [IMX8MM_VPUBLK_PD_G2] = { + .name = "vpublk-g2", + .clk_names = (const char *[]){ "g2", }, + .num_clks = 1, + .gpc_name = "g2", + .rst_mask = BIT(0), + .clk_mask = BIT(0), + }, + [IMX8MM_VPUBLK_PD_H1] = { + .name = "vpublk-h1", + .clk_names = (const char *[]){ "h1", }, + .num_clks = 1, + .gpc_name = "h1", + .rst_mask = BIT(2), + .clk_mask = BIT(2), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = { + .max_reg = 0x18, + .power_notifier_fn = imx8mm_vpu_power_notifier, + .domains = imx8mm_vpu_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data), +}; + +static const struct of_device_id imx8m_blk_ctrl_of_match[] = { + { + .compatible = "fsl,imx8mm-vpu-blk-ctrl", + .data = &imx8mm_vpu_blk_ctl_dev_data + }, { + /* Sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match); + +static struct platform_driver imx8m_blk_ctrl_driver = { + .probe = imx8m_blk_ctrl_probe, + .remove = imx8m_blk_ctrl_remove, + .driver = { + .name = "imx8m-blk-ctrl", + .pm = &imx8m_blk_ctrl_pm_ops, + .of_match_table = imx8m_blk_ctrl_of_match, + }, +}; +module_platform_driver(imx8m_blk_ctrl_driver); -- cgit v1.2.3 From 926e57c065dfcf5a824b206760330f32e786dd8c Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:49 +0200 Subject: soc: imx: imx8m-blk-ctrl: add DISP blk-ctrl This adds the description for the i.MX8MM disp blk-ctrl. Signed-off-by: Lucas Stach Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 70 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index f8db0ebd02c3..e172d295c441 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -431,11 +431,81 @@ static const struct imx8m_blk_ctrl_data imx8mm_vpu_blk_ctl_dev_data = { .num_domains = ARRAY_SIZE(imx8mm_vpu_blk_ctl_domain_data), }; +static int imx8mm_disp_power_notifier(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, + power_nb); + + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) + return NOTIFY_OK; + + /* Enable bus clock and deassert bus reset */ + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12)); + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6)); + + /* + * On power up we have no software backchannel to the GPC to + * wait for the ADB handshake to happen, so we just delay for a + * bit. On power down the GPC driver waits for the handshake. + */ + if (action == GENPD_NOTIFY_ON) + udelay(5); + + + return NOTIFY_OK; +} + +static const struct imx8m_blk_ctrl_domain_data imx8mm_disp_blk_ctl_domain_data[] = { + [IMX8MM_DISPBLK_PD_CSI_BRIDGE] = { + .name = "dispblk-csi-bridge", + .clk_names = (const char *[]){ "csi-bridge-axi", "csi-bridge-apb", + "csi-bridge-core", }, + .num_clks = 3, + .gpc_name = "csi-bridge", + .rst_mask = BIT(0) | BIT(1) | BIT(2), + .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5), + }, + [IMX8MM_DISPBLK_PD_LCDIF] = { + .name = "dispblk-lcdif", + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, + .num_clks = 3, + .gpc_name = "lcdif", + .clk_mask = BIT(6) | BIT(7), + }, + [IMX8MM_DISPBLK_PD_MIPI_DSI] = { + .name = "dispblk-mipi-dsi", + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, + .num_clks = 2, + .gpc_name = "mipi-dsi", + .rst_mask = BIT(5), + .clk_mask = BIT(8) | BIT(9), + }, + [IMX8MM_DISPBLK_PD_MIPI_CSI] = { + .name = "dispblk-mipi-csi", + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, + .num_clks = 2, + .gpc_name = "mipi-csi", + .rst_mask = BIT(3) | BIT(4), + .clk_mask = BIT(10) | BIT(11), + }, +}; + +static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { + .max_reg = 0x2c, + .power_notifier_fn = imx8mm_disp_power_notifier, + .domains = imx8mm_disp_blk_ctl_domain_data, + .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), +}; + static const struct of_device_id imx8m_blk_ctrl_of_match[] = { { .compatible = "fsl,imx8mm-vpu-blk-ctrl", .data = &imx8mm_vpu_blk_ctl_dev_data }, { + .compatible = "fsl,imx8mm-disp-blk-ctrl", + .data = &imx8mm_disp_blk_ctl_dev_data + } ,{ /* Sentinel */ } }; -- cgit v1.2.3 From 986b5094708e508baa452a23ffe809870934a7df Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 27 Jun 2021 17:54:31 +0200 Subject: soc/tegra: Fix an error handling path in tegra_powergate_power_up() If an error occurs after a successful tegra_powergate_enable_clocks() call, it must be undone by a tegra_powergate_disable_clocks() call, as already done in the below and above error handling paths of this function. Update the 'goto' to branch at the correct place of the error handling path. Fixes: a38045121bf4 ("soc/tegra: pmc: Add generic PM domain support") Signed-off-by: Christophe JAILLET Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2ad7b3bceb80..6695935a81f1 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -783,7 +783,7 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, err = reset_control_deassert(pg->reset); if (err) - goto powergate_off; + goto disable_clks; usleep_range(10, 20); -- cgit v1.2.3 From 13d9624da4e10a06446e5b09d962ff42dd10357f Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Thu, 30 Sep 2021 23:52:21 +0800 Subject: soc: mediatek: add mtk mutex support for MT8192 Add mtk mutex support for MT8192 SoC. Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang Reviewed-by: CK Hu Link: https://lore.kernel.org/r/20210930155222.5861-5-yongqiang.niu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mutex.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 2e4bcc300576..2ca55bb5a8be 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -39,6 +39,18 @@ #define MT8167_MUTEX_MOD_DISP_DITHER 15 #define MT8167_MUTEX_MOD_DISP_UFOE 16 +#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + #define MT8183_MUTEX_MOD_DISP_RDMA0 0 #define MT8183_MUTEX_MOD_DISP_RDMA1 1 #define MT8183_MUTEX_MOD_DISP_OVL0 9 @@ -214,6 +226,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; +static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0, + [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L, + [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L, + [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4, +}; + static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, @@ -275,6 +301,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8192_mutex_driver_data = { + .mutex_mod = mt8192_mutex_mod, + .mutex_sof = mt8183_mutex_sof, + .mutex_mod_reg = MT8183_MUTEX0_MOD0, + .mutex_sof_reg = MT8183_MUTEX0_SOF0, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +540,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8192-disp-mutex", + .data = &mt8192_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); -- cgit v1.2.3 From f27ef2856343e2ddc392975d7b15120442e4d7b7 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 30 Sep 2021 10:31:49 +0200 Subject: soc: mediatek: mmsys: Add reset controller support Among other features the mmsys driver should implement a reset controller to be able to reset different bits from their space. Cc: Jitao Shi Suggested-by: Chun-Kuang Hu Signed-off-by: Enric Balletbo i Serra Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/20210930103105.v4.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 68 ++++++++++++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.h | 2 ++ 2 files changed, 70 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 5ecfe09a5751..1e448f1ffefb 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -4,10 +4,12 @@ * Author: James Liao */ +#include #include #include #include #include +#include #include #include "mtk-mmsys.h" @@ -69,6 +71,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; + spinlock_t lock; /* protects mmsys_sw_rst_b reg */ + struct reset_controller_dev rcdev; }; void mtk_mmsys_ddp_connect(struct device *dev, @@ -108,6 +112,58 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id, + bool assert) +{ + struct mtk_mmsys *mmsys = container_of(rcdev, struct mtk_mmsys, rcdev); + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&mmsys->lock, flags); + + reg = readl_relaxed(mmsys->regs + MMSYS_SW0_RST_B); + + if (assert) + reg &= ~BIT(id); + else + reg |= BIT(id); + + writel_relaxed(reg, mmsys->regs + MMSYS_SW0_RST_B); + + spin_unlock_irqrestore(&mmsys->lock, flags); + + return 0; +} + +static int mtk_mmsys_reset_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + return mtk_mmsys_reset_update(rcdev, id, true); +} + +static int mtk_mmsys_reset_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + return mtk_mmsys_reset_update(rcdev, id, false); +} + +static int mtk_mmsys_reset(struct reset_controller_dev *rcdev, unsigned long id) +{ + int ret; + + ret = mtk_mmsys_reset_assert(rcdev, id); + if (ret) + return ret; + + usleep_range(1000, 1100); + + return mtk_mmsys_reset_deassert(rcdev, id); +} + +static const struct reset_control_ops mtk_mmsys_reset_ops = { + .assert = mtk_mmsys_reset_assert, + .deassert = mtk_mmsys_reset_deassert, + .reset = mtk_mmsys_reset, +}; + static int mtk_mmsys_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -127,6 +183,18 @@ static int mtk_mmsys_probe(struct platform_device *pdev) return ret; } + spin_lock_init(&mmsys->lock); + + mmsys->rcdev.owner = THIS_MODULE; + mmsys->rcdev.nr_resets = 32; + mmsys->rcdev.ops = &mtk_mmsys_reset_ops; + mmsys->rcdev.of_node = pdev->dev.of_node; + ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev); + if (ret) { + dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret); + return ret; + } + mmsys->data = of_device_get_match_data(&pdev->dev); platform_set_drvdata(pdev, mmsys); diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h index 9e2b81bd38db..8b0ed05117ea 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -78,6 +78,8 @@ #define DSI_SEL_IN_RDMA 0x1 #define DSI_SEL_IN_MASK 0x1 +#define MMSYS_SW0_RST_B 0x140 + struct mtk_mmsys_routes { u32 from_comp; u32 to_comp; -- cgit v1.2.3 From 29962197e64f9e62d0408dfa361a613003795968 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 17 Jun 2021 15:13:07 +0300 Subject: soc/tegra: Add Tegra186 ARI driver Add a driver to hook into panic notifiers and print machine check status for debugging. Status information is retrieved via SMC. This is supported by upstream ARM Trusted Firmware. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding --- drivers/soc/tegra/Makefile | 1 + drivers/soc/tegra/ari-tegra186.c | 80 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 drivers/soc/tegra/ari-tegra186.c (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/Makefile b/drivers/soc/tegra/Makefile index 9c809c1814bd..054e862b63d8 100644 --- a/drivers/soc/tegra/Makefile +++ b/drivers/soc/tegra/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_SOC_TEGRA_PMC) += pmc.o obj-$(CONFIG_SOC_TEGRA_POWERGATE_BPMP) += powergate-bpmp.o obj-$(CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER) += regulators-tegra20.o obj-$(CONFIG_SOC_TEGRA30_VOLTAGE_COUPLER) += regulators-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_186_SOC) += ari-tegra186.o diff --git a/drivers/soc/tegra/ari-tegra186.c b/drivers/soc/tegra/ari-tegra186.c new file mode 100644 index 000000000000..02577853ec49 --- /dev/null +++ b/drivers/soc/tegra/ari-tegra186.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include + +#define SMC_SIP_INVOKE_MCE 0xc2ffff00 +#define MCE_SMC_READ_MCA 12 + +#define MCA_ARI_CMD_RD_SERR 1 + +#define MCA_ARI_RW_SUBIDX_STAT 1 +#define SERR_STATUS_VAL BIT_ULL(63) + +#define MCA_ARI_RW_SUBIDX_ADDR 2 +#define MCA_ARI_RW_SUBIDX_MSC1 3 +#define MCA_ARI_RW_SUBIDX_MSC2 4 + +static const char * const bank_names[] = { + "SYS:DPMU", "ROC:IOB", "ROC:MCB", "ROC:CCE", "ROC:CQX", "ROC:CTU", +}; + +static void read_uncore_mca(u8 cmd, u8 idx, u8 subidx, u8 inst, u64 *data) +{ + struct arm_smccc_res res; + + arm_smccc_smc(SMC_SIP_INVOKE_MCE | MCE_SMC_READ_MCA, + ((u64)inst << 24) | ((u64)idx << 16) | + ((u64)subidx << 8) | ((u64)cmd << 0), + 0, 0, 0, 0, 0, 0, &res); + + *data = res.a2; +} + +static int tegra186_ari_panic_handler(struct notifier_block *nb, + unsigned long code, void *unused) +{ + u64 status; + int i; + + for (i = 0; i < ARRAY_SIZE(bank_names); i++) { + read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, MCA_ARI_RW_SUBIDX_STAT, + 0, &status); + + if (status & SERR_STATUS_VAL) { + u64 addr, misc1, misc2; + + read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, + MCA_ARI_RW_SUBIDX_ADDR, 0, &addr); + read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, + MCA_ARI_RW_SUBIDX_MSC1, 0, &misc1); + read_uncore_mca(MCA_ARI_CMD_RD_SERR, i, + MCA_ARI_RW_SUBIDX_MSC2, 0, &misc2); + + pr_crit("Machine Check Error in %s\n" + " status=0x%llx addr=0x%llx\n" + " msc1=0x%llx msc2=0x%llx\n", + bank_names[i], status, addr, misc1, misc2); + } + } + + return NOTIFY_DONE; +} + +static struct notifier_block tegra186_ari_panic_nb = { + .notifier_call = tegra186_ari_panic_handler, +}; + +static int __init tegra186_ari_init(void) +{ + if (of_machine_is_compatible("nvidia,tegra186")) + atomic_notifier_chain_register(&panic_notifier_list, &tegra186_ari_panic_nb); + + return 0; +} +early_initcall(tegra186_ari_init); -- cgit v1.2.3 From 76d89474310e05d9c592a8beed2aefe4d3396d2d Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:17:24 +0800 Subject: soc/tegra: pmc: Use devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Cai Huoqing Signed-off-by: Thierry Reding --- drivers/soc/tegra/pmc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 6695935a81f1..575d6d5b4294 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -2816,8 +2816,7 @@ static int tegra_pmc_probe(struct platform_device *pdev) return err; /* take over the memory region from the early initialization */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&pdev->dev, res); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); -- cgit v1.2.3 From 178d6c1b83e5244b866d90071246b3b0135c3f7d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 8 Oct 2021 09:52:53 +0200 Subject: soc: samsung: pm_domains: drop unused is_off field The 'is_off' member of internal state structure 'exynos_pm_domain' is not used anymore. Fixes: 2ed5f236716c ("ARM: EXYNOS: Detect power domain state on registration from DT") Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20211008075253.67961-1-krzysztof.kozlowski@canonical.com --- drivers/soc/samsung/pm_domains.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index 5ec0c13f0aaf..d07f3c9d6903 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -28,7 +28,6 @@ struct exynos_pm_domain_config { */ struct exynos_pm_domain { void __iomem *base; - bool is_off; struct generic_pm_domain pd; u32 local_pwr_cfg; }; -- cgit v1.2.3 From b5af64fceb04dc298c5e69c517b4d83893ff060b Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 30 Sep 2021 11:21:10 -0700 Subject: soc: qcom: smem: Support reserved-memory description Practically all modern Qualcomm platforms has a single reserved-memory region for SMEM. So rather than having to describe SMEM in the form of a node with a reference to a reserved-memory node, allow the SMEM device to be instantiated directly from the reserved-memory node. The current means of falling back to dereferencing the "memory-region" is kept as a fallback, if it's determined that the SMEM node is a reserved-memory node. The "qcom,smem" compatible is added to the reserved_mem_matches list, to allow the reserved-memory device to be probed. In order to retain the readability of the code, the resolution of resources is split from the actual ioremapping. Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Reviewed-by: Vladimir Zapolskiy Link: https://lore.kernel.org/r/20210930182111.57353-4-bjorn.andersson@linaro.org --- drivers/of/platform.c | 1 + drivers/soc/qcom/smem.c | 57 +++++++++++++++++++++++++++++++++---------------- 2 files changed, 40 insertions(+), 18 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/of/platform.c b/drivers/of/platform.c index 74afbb7a4f5e..19ba8e4d4f8d 100644 --- a/drivers/of/platform.c +++ b/drivers/of/platform.c @@ -509,6 +509,7 @@ EXPORT_SYMBOL_GPL(of_platform_default_populate); static const struct of_device_id reserved_mem_matches[] = { { .compatible = "qcom,rmtfs-mem" }, { .compatible = "qcom,cmd-db" }, + { .compatible = "qcom,smem" }, { .compatible = "ramoops" }, { .compatible = "nvmem-rmem" }, {} diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 4fb5aeeb0843..c7e519bfdc8a 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -240,7 +241,7 @@ static const u8 SMEM_INFO_MAGIC[] = { 0x53, 0x49, 0x49, 0x49 }; /* SIII */ * @size: size of the memory region */ struct smem_region { - u32 aux_base; + phys_addr_t aux_base; void __iomem *virt_base; size_t size; }; @@ -499,7 +500,7 @@ static void *qcom_smem_get_global(struct qcom_smem *smem, for (i = 0; i < smem->num_regions; i++) { region = &smem->regions[i]; - if (region->aux_base == aux_base || !aux_base) { + if ((u32)region->aux_base == aux_base || !aux_base) { if (size != NULL) *size = le32_to_cpu(entry->size); return region->virt_base + le32_to_cpu(entry->offset); @@ -664,7 +665,7 @@ phys_addr_t qcom_smem_virt_to_phys(void *p) if (p < region->virt_base + region->size) { u64 offset = p - region->virt_base; - return (phys_addr_t)region->aux_base + offset; + return region->aux_base + offset; } } @@ -863,12 +864,12 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) return 0; } -static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, - const char *name, int i) +static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name, + struct smem_region *region) { + struct device *dev = smem->dev; struct device_node *np; struct resource r; - resource_size_t size; int ret; np = of_parse_phandle(dev->of_node, name, 0); @@ -881,13 +882,9 @@ static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, of_node_put(np); if (ret) return ret; - size = resource_size(&r); - smem->regions[i].virt_base = devm_ioremap_wc(dev, r.start, size); - if (!smem->regions[i].virt_base) - return -ENOMEM; - smem->regions[i].aux_base = (u32)r.start; - smem->regions[i].size = size; + region->aux_base = r.start; + region->size = resource_size(&r); return 0; } @@ -895,12 +892,14 @@ static int qcom_smem_map_memory(struct qcom_smem *smem, struct device *dev, static int qcom_smem_probe(struct platform_device *pdev) { struct smem_header *header; + struct reserved_mem *rmem; struct qcom_smem *smem; size_t array_size; int num_regions; int hwlock_id; u32 version; int ret; + int i; num_regions = 1; if (of_find_property(pdev->dev.of_node, "qcom,rpm-msg-ram", NULL)) @@ -914,13 +913,35 @@ static int qcom_smem_probe(struct platform_device *pdev) smem->dev = &pdev->dev; smem->num_regions = num_regions; - ret = qcom_smem_map_memory(smem, &pdev->dev, "memory-region", 0); - if (ret) - return ret; + rmem = of_reserved_mem_lookup(pdev->dev.of_node); + if (rmem) { + smem->regions[0].aux_base = rmem->base; + smem->regions[0].size = rmem->size; + } else { + /* + * Fall back to the memory-region reference, if we're not a + * reserved-memory node. + */ + ret = qcom_smem_resolve_mem(smem, "memory-region", &smem->regions[0]); + if (ret) + return ret; + } - if (num_regions > 1 && (ret = qcom_smem_map_memory(smem, &pdev->dev, - "qcom,rpm-msg-ram", 1))) - return ret; + if (num_regions > 1) { + ret = qcom_smem_resolve_mem(smem, "qcom,rpm-msg-ram", &smem->regions[1]); + if (ret) + return ret; + } + + for (i = 0; i < num_regions; i++) { + smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev, + smem->regions[i].aux_base, + smem->regions[i].size); + if (!smem->regions[i].virt_base) { + dev_err(&pdev->dev, "failed to remap %pa\n", &smem->regions[i].aux_base); + return -ENOMEM; + } + } header = smem->regions[0].virt_base; if (le32_to_cpu(header->initialized) != 1 || -- cgit v1.2.3 From 72949f76565c9ea9f4231c977774a31d4713c386 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 11 Oct 2021 15:36:38 +0300 Subject: soc: imx: imx8m-blk-ctrl: off by one in imx8m_blk_ctrl_xlate() The > comparison should be >= to prevent reading one element beyond the end of the array. The onecell_data->domains[] array is allocated in imx8m_blk_ctrl_probe() and it has "onecell_data->num_domains" elements. Fixes: 5b340e7813d4 ("soc: imx: add i.MX8M blk-ctrl driver") Signed-off-by: Dan Carpenter Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- drivers/soc/imx/imx8m-blk-ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index e172d295c441..519b3651d1d9 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -139,7 +139,7 @@ imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data) unsigned int index = args->args[0]; if (args->args_count != 1 || - index > onecell_data->num_domains) + index >= onecell_data->num_domains) return ERR_PTR(-EINVAL); return onecell_data->domains[index]; -- cgit v1.2.3 From c072c4ef7ef09e1d6470c48cf52570487589b76a Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 14 Oct 2021 16:35:06 +0300 Subject: soc: samsung: exynos-chipid: Pass revision reg offsets Old Exynos SoCs have both Product ID and Revision ID in one single register, while new SoCs tend to have two separate registers for those IDs. Implement handling of both cases by passing Revision ID register offsets in driver data. Previously existing macros for Exynos4210 (removed in this patch) were incorrect: #define EXYNOS_SUBREV_MASK (0xf << 4) #define EXYNOS_MAINREV_MASK (0xf << 0) Actual format of PRO_ID register in Exynos4210 (offset 0x0): [31:12] Product ID [9:8] Package information [7:4] Main Revision Number [3:0] Sub Revision Number This patch doesn't change the behavior on existing platforms, so '/sys/devices/soc0/revision' will show the same string as before. Signed-off-by: Sam Protsenko Tested-by: Henrik Grimler Link: https://lore.kernel.org/r/20211014133508.1210-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-chipid.c | 69 ++++++++++++++++++++++++++----- include/linux/soc/samsung/exynos-chipid.h | 6 +-- 2 files changed, 60 insertions(+), 15 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index b2627a3a127a..986978e83661 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,17 @@ #include "exynos-asv.h" +struct exynos_chipid_variant { + unsigned int rev_reg; /* revision register offset */ + unsigned int main_rev_shift; /* main revision offset in rev_reg */ + unsigned int sub_rev_shift; /* sub revision offset in rev_reg */ +}; + +struct exynos_chipid_info { + u32 product_id; + u32 revision; +}; + static const struct exynos_soc_id { const char *name; unsigned int id; @@ -50,31 +62,57 @@ static const char *product_id_to_soc_id(unsigned int product_id) int i; for (i = 0; i < ARRAY_SIZE(soc_ids); i++) - if ((product_id & EXYNOS_MASK) == soc_ids[i].id) + if (product_id == soc_ids[i].id) return soc_ids[i].name; return NULL; } +static int exynos_chipid_get_chipid_info(struct regmap *regmap, + const struct exynos_chipid_variant *data, + struct exynos_chipid_info *soc_info) +{ + int ret; + unsigned int val, main_rev, sub_rev; + + ret = regmap_read(regmap, EXYNOS_CHIPID_REG_PRO_ID, &val); + if (ret < 0) + return ret; + soc_info->product_id = val & EXYNOS_MASK; + + if (data->rev_reg != EXYNOS_CHIPID_REG_PRO_ID) { + ret = regmap_read(regmap, data->rev_reg, &val); + if (ret < 0) + return ret; + } + main_rev = (val >> data->main_rev_shift) & EXYNOS_REV_PART_MASK; + sub_rev = (val >> data->sub_rev_shift) & EXYNOS_REV_PART_MASK; + soc_info->revision = (main_rev << EXYNOS_REV_PART_SHIFT) | sub_rev; + + return 0; +} + static int exynos_chipid_probe(struct platform_device *pdev) { + const struct exynos_chipid_variant *drv_data; + struct exynos_chipid_info soc_info; struct soc_device_attribute *soc_dev_attr; struct soc_device *soc_dev; struct device_node *root; struct regmap *regmap; - u32 product_id; - u32 revision; int ret; + drv_data = of_device_get_match_data(&pdev->dev); + if (!drv_data) + return -EINVAL; + regmap = device_node_to_regmap(pdev->dev.of_node); if (IS_ERR(regmap)) return PTR_ERR(regmap); - ret = regmap_read(regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id); + ret = exynos_chipid_get_chipid_info(regmap, drv_data, &soc_info); if (ret < 0) return ret; - revision = product_id & EXYNOS_REV_MASK; - soc_dev_attr = devm_kzalloc(&pdev->dev, sizeof(*soc_dev_attr), GFP_KERNEL); if (!soc_dev_attr) @@ -87,8 +125,8 @@ static int exynos_chipid_probe(struct platform_device *pdev) of_node_put(root); soc_dev_attr->revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, - "%x", revision); - soc_dev_attr->soc_id = product_id_to_soc_id(product_id); + "%x", soc_info.revision); + soc_dev_attr->soc_id = product_id_to_soc_id(soc_info.product_id); if (!soc_dev_attr->soc_id) { pr_err("Unknown SoC\n"); return -ENODEV; @@ -106,7 +144,7 @@ static int exynos_chipid_probe(struct platform_device *pdev) platform_set_drvdata(pdev, soc_dev); dev_info(&pdev->dev, "Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", - soc_dev_attr->soc_id, product_id, revision); + soc_dev_attr->soc_id, soc_info.product_id, soc_info.revision); return 0; @@ -125,9 +163,18 @@ static int exynos_chipid_remove(struct platform_device *pdev) return 0; } +static const struct exynos_chipid_variant exynos4210_chipid_drv_data = { + .rev_reg = 0x0, + .main_rev_shift = 4, + .sub_rev_shift = 0, +}; + static const struct of_device_id exynos_chipid_of_device_ids[] = { - { .compatible = "samsung,exynos4210-chipid" }, - {} + { + .compatible = "samsung,exynos4210-chipid", + .data = &exynos4210_chipid_drv_data, + }, + { } }; MODULE_DEVICE_TABLE(of, exynos_chipid_of_device_ids); diff --git a/include/linux/soc/samsung/exynos-chipid.h b/include/linux/soc/samsung/exynos-chipid.h index 8bca6763f99c..62f0e2531068 100644 --- a/include/linux/soc/samsung/exynos-chipid.h +++ b/include/linux/soc/samsung/exynos-chipid.h @@ -9,10 +9,8 @@ #define __LINUX_SOC_EXYNOS_CHIPID_H #define EXYNOS_CHIPID_REG_PRO_ID 0x00 -#define EXYNOS_SUBREV_MASK (0xf << 4) -#define EXYNOS_MAINREV_MASK (0xf << 0) -#define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | \ - EXYNOS_MAINREV_MASK) +#define EXYNOS_REV_PART_MASK 0xf +#define EXYNOS_REV_PART_SHIFT 4 #define EXYNOS_MASK 0xfffff000 #define EXYNOS_CHIPID_REG_PKG_ID 0x04 -- cgit v1.2.3 From 81a51eb6be3dbb76790b7353ec8dfaadfc751782 Mon Sep 17 00:00:00 2001 From: Sam Protsenko Date: Thu, 14 Oct 2021 16:35:08 +0300 Subject: soc: samsung: exynos-chipid: Add Exynos850 support Add chip-id support for Exynos850 SoC. Despite its "E3830" ID, the actual SoC name is Exynos850 (Exynos3830 name is internal and outdated). Format of Product_ID register in Exynos850 (offset 0x0): [31:0] Product ID (identification) Format of CHIPID_REV register in Exynos850 (offset 0x10): [23:20] Main revision [19:16] Sub revision Signed-off-by: Sam Protsenko Link: https://lore.kernel.org/r/20211014133508.1210-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-chipid.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 986978e83661..0aeb24bcc11a 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -55,6 +55,7 @@ static const struct exynos_soc_id { { "EXYNOS5440", 0xE5440000 }, { "EXYNOS5800", 0xE5422000 }, { "EXYNOS7420", 0xE7420000 }, + { "EXYNOS850", 0xE3830000 }, }; static const char *product_id_to_soc_id(unsigned int product_id) @@ -169,10 +170,19 @@ static const struct exynos_chipid_variant exynos4210_chipid_drv_data = { .sub_rev_shift = 0, }; +static const struct exynos_chipid_variant exynos850_chipid_drv_data = { + .rev_reg = 0x10, + .main_rev_shift = 20, + .sub_rev_shift = 16, +}; + static const struct of_device_id exynos_chipid_of_device_ids[] = { { .compatible = "samsung,exynos4210-chipid", .data = &exynos4210_chipid_drv_data, + }, { + .compatible = "samsung,exynos850-chipid", + .data = &exynos850_chipid_drv_data, }, { } }; -- cgit v1.2.3 From e3e56c050ab6e3f1bd811f0787f50709017543e4 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Oct 2021 20:37:32 -0700 Subject: soc: qcom: rpmhpd: Make power_on actually enable the domain The general expectation is that powering on a power-domain should make the power domain deliver some power, and if a specific performance state is needed further requests has to be made. But in contrast with other power-domain implementations (e.g. rpmpd) the RPMh does not have an interface to enable the power, so the driver has to vote for a particular corner (performance level) in rpmh_power_on(). But the corner is never initialized, so a typical request to simply enable the power domain would not actually turn on the hardware. Further more, when no more clients vote for a performance state (i.e. the aggregated vote is 0) the power domain would be turned off. Fix both of these issues by always voting for a corner with non-zero value, when the power domain is enabled. The tracking of the lowest non-zero corner is performed to handle the corner case if there's ever a domain with a non-zero lowest corner, in which case both rpmh_power_on() and rpmh_rpmhpd_set_performance_state() would be allowed to use this lowest corner. Fixes: 279b7e8a62cc ("soc: qcom: rpmhpd: Add RPMh power domain driver") Signed-off-by: Bjorn Andersson Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20211005033732.2284447-1-bjorn.andersson@linaro.org --- drivers/soc/qcom/rpmhpd.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index e280a8194725..0ca77ed22c6c 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -30,6 +30,7 @@ * @active_only: True if it represents an Active only peer * @corner: current corner * @active_corner: current active corner + * @enable_corner: lowest non-zero corner * @level: An array of level (vlvl) to corner (hlvl) mappings * derived from cmd-db * @level_count: Number of levels supported by the power domain. max @@ -47,6 +48,7 @@ struct rpmhpd { const bool active_only; unsigned int corner; unsigned int active_corner; + unsigned int enable_corner; u32 level[RPMH_ARC_MAX_LEVELS]; size_t level_count; bool enabled; @@ -401,13 +403,13 @@ static int rpmhpd_aggregate_corner(struct rpmhpd *pd, unsigned int corner) static int rpmhpd_power_on(struct generic_pm_domain *domain) { struct rpmhpd *pd = domain_to_rpmhpd(domain); - int ret = 0; + unsigned int corner; + int ret; mutex_lock(&rpmhpd_lock); - if (pd->corner) - ret = rpmhpd_aggregate_corner(pd, pd->corner); - + corner = max(pd->corner, pd->enable_corner); + ret = rpmhpd_aggregate_corner(pd, corner); if (!ret) pd->enabled = true; @@ -452,6 +454,10 @@ static int rpmhpd_set_performance_state(struct generic_pm_domain *domain, i--; if (pd->enabled) { + /* Ensure that the domain isn't turn off */ + if (i < pd->enable_corner) + i = pd->enable_corner; + ret = rpmhpd_aggregate_corner(pd, i); if (ret) goto out; @@ -488,6 +494,10 @@ static int rpmhpd_update_level_mapping(struct rpmhpd *rpmhpd) for (i = 0; i < rpmhpd->level_count; i++) { rpmhpd->level[i] = buf[i]; + /* Remember the first corner with non-zero level */ + if (!rpmhpd->level[rpmhpd->enable_corner] && rpmhpd->level[i]) + rpmhpd->enable_corner = i; + /* * The AUX data may be zero padded. These 0 valued entries at * the end of the map must be ignored. -- cgit v1.2.3 From 2fae3ecc70405b72ea6c923b216d34547559d6a9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 16 Oct 2021 22:06:07 +0300 Subject: soc: qcom: socinfo: add two missing PMIC IDs Add IDs for PMK8001 and PMI8996. They also fall in the list of 'duplicated' IDs, where the same index was used for multiple chips. Fixes: 7fda2b0bfbd9 ("soc: qcom: socinfo: import PMIC IDs from pmic-spmi") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211016190607.49866-1-dmitry.baryshkov@linaro.org --- drivers/soc/qcom/socinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 288897868435..bec6eb910cba 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -87,8 +87,8 @@ static const char *const pmic_models[] = { [15] = "PM8901", [16] = "PM8950/PM8027", [17] = "PMI8950/ISL9519", - [18] = "PM8921", - [19] = "PM8018", + [18] = "PMK8001/PM8921", + [19] = "PMI8996/PM8018", [20] = "PM8998/PM8015", [21] = "PMI8998/PM8014", [22] = "PM8821", -- cgit v1.2.3 From 1d7724690344a264f8a567c9214aa65456d7566d Mon Sep 17 00:00:00 2001 From: Mahesh Sivasubramanian Date: Wed, 13 Oct 2021 12:08:21 +0530 Subject: soc: qcom: Add Sleep stats driver Let's add a driver to read the stats from remote processor and export to debugfs. The driver creates "qcom_sleep_stats" directory in debugfs and adds files for various low power mode available. Below is sample output with command cat /sys/kernel/debug/qcom_sleep_stats/ddr count = 0 Last Entered At = 0 Last Exited At = 0 Accumulated Duration = 0 Signed-off-by: Mahesh Sivasubramanian Signed-off-by: Lina Iyer [mkshah: add subsystem sleep stats, create one file for each stat] Signed-off-by: Maulik Shah Tested-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1634107104-22197-3-git-send-email-mkshah@codeaurora.org --- drivers/soc/qcom/Kconfig | 10 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qcom_stats.c | 277 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 288 insertions(+) create mode 100644 drivers/soc/qcom/qcom_stats.c (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index abfef201b94f..3cf3a6b41182 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -199,6 +199,16 @@ config QCOM_SPM to manage cores, L2 low power modes and to configure the internal Adaptive Voltage Scaler parameters, where supported. +config QCOM_STATS + tristate "Qualcomm Technologies, Inc. (QTI) Sleep stats driver" + depends on (ARCH_QCOM && DEBUG_FS) || COMPILE_TEST + depends on QCOM_SMEM + help + Qualcomm Technologies, Inc. (QTI) Sleep stats driver to read + the shared memory exported by the remote processor related to + various SoC level low power modes statistics and export to debugfs + interface. + config QCOM_WCNSS_CTRL tristate "Qualcomm WCNSS control driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 24514c722832..70d5de69fd7b 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o obj-$(CONFIG_QCOM_SPM) += spm.o +obj-$(CONFIG_QCOM_STATS) += qcom_stats.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c new file mode 100644 index 000000000000..817505bd99b5 --- /dev/null +++ b/drivers/soc/qcom/qcom_stats.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define RPM_DYNAMIC_ADDR 0x14 +#define RPM_DYNAMIC_ADDR_MASK 0xFFFF + +#define STAT_TYPE_OFFSET 0x0 +#define COUNT_OFFSET 0x4 +#define LAST_ENTERED_AT_OFFSET 0x8 +#define LAST_EXITED_AT_OFFSET 0x10 +#define ACCUMULATED_OFFSET 0x18 +#define CLIENT_VOTES_OFFSET 0x1c + +struct subsystem_data { + const char *name; + u32 smem_item; + u32 pid; +}; + +static const struct subsystem_data subsystems[] = { + { "modem", 605, 1 }, + { "wpss", 605, 13 }, + { "adsp", 606, 2 }, + { "cdsp", 607, 5 }, + { "slpi", 608, 3 }, + { "gpu", 609, 0 }, + { "display", 610, 0 }, + { "adsp_island", 613, 2 }, + { "slpi_island", 613, 3 }, +}; + +struct stats_config { + size_t stats_offset; + size_t num_records; + bool appended_stats_avail; + bool dynamic_offset; + bool subsystem_stats_in_smem; +}; + +struct stats_data { + bool appended_stats_avail; + void __iomem *base; +}; + +struct sleep_stats { + u32 stat_type; + u32 count; + u64 last_entered_at; + u64 last_exited_at; + u64 accumulated; +}; + +struct appended_stats { + u32 client_votes; + u32 reserved[3]; +}; + +static void qcom_print_stats(struct seq_file *s, const struct sleep_stats *stat) +{ + u64 accumulated = stat->accumulated; + /* + * If a subsystem is in sleep when reading the sleep stats adjust + * the accumulated sleep duration to show actual sleep time. + */ + if (stat->last_entered_at > stat->last_exited_at) + accumulated += arch_timer_read_counter() - stat->last_entered_at; + + seq_printf(s, "Count: %u\n", stat->count); + seq_printf(s, "Last Entered At: %llu\n", stat->last_entered_at); + seq_printf(s, "Last Exited At: %llu\n", stat->last_exited_at); + seq_printf(s, "Accumulated Duration: %llu\n", accumulated); +} + +static int qcom_subsystem_sleep_stats_show(struct seq_file *s, void *unused) +{ + struct subsystem_data *subsystem = s->private; + struct sleep_stats *stat; + + /* Items are allocated lazily, so lookup pointer each time */ + stat = qcom_smem_get(subsystem->pid, subsystem->smem_item, NULL); + if (IS_ERR(stat)) + return -EIO; + + qcom_print_stats(s, stat); + + return 0; +} + +static int qcom_soc_sleep_stats_show(struct seq_file *s, void *unused) +{ + struct stats_data *d = s->private; + void __iomem *reg = d->base; + struct sleep_stats stat; + + memcpy_fromio(&stat, reg, sizeof(stat)); + qcom_print_stats(s, &stat); + + if (d->appended_stats_avail) { + struct appended_stats votes; + + memcpy_fromio(&votes, reg + CLIENT_VOTES_OFFSET, sizeof(votes)); + seq_printf(s, "Client Votes: %#x\n", votes.client_votes); + } + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(qcom_soc_sleep_stats); +DEFINE_SHOW_ATTRIBUTE(qcom_subsystem_sleep_stats); + +static void qcom_create_soc_sleep_stat_files(struct dentry *root, void __iomem *reg, + struct stats_data *d, + const struct stats_config *config) +{ + char stat_type[sizeof(u32) + 1] = {0}; + size_t stats_offset = config->stats_offset; + u32 offset = 0, type; + int i, j; + + /* + * On RPM targets, stats offset location is dynamic and changes from target + * to target and sometimes from build to build for same target. + * + * In such cases the dynamic address is present at 0x14 offset from base + * address in devicetree. The last 16bits indicates the stats_offset. + */ + if (config->dynamic_offset) { + stats_offset = readl(reg + RPM_DYNAMIC_ADDR); + stats_offset &= RPM_DYNAMIC_ADDR_MASK; + } + + for (i = 0; i < config->num_records; i++) { + d[i].base = reg + offset + stats_offset; + + /* + * Read the low power mode name and create debugfs file for it. + * The names read could be of below, + * (may change depending on low power mode supported). + * For rpmh-sleep-stats: "aosd", "cxsd" and "ddr". + * For rpm-sleep-stats: "vmin" and "vlow". + */ + type = readl(d[i].base); + for (j = 0; j < sizeof(u32); j++) { + stat_type[j] = type & 0xff; + type = type >> 8; + } + strim(stat_type); + debugfs_create_file(stat_type, 0400, root, &d[i], + &qcom_soc_sleep_stats_fops); + + offset += sizeof(struct sleep_stats); + if (d[i].appended_stats_avail) + offset += sizeof(struct appended_stats); + } +} + +static void qcom_create_subsystem_stat_files(struct dentry *root, + const struct stats_config *config) +{ + const struct sleep_stats *stat; + int i; + + if (!config->subsystem_stats_in_smem) + return; + + for (i = 0; i < ARRAY_SIZE(subsystems); i++) { + stat = qcom_smem_get(subsystems[i].pid, subsystems[i].smem_item, NULL); + if (IS_ERR(stat)) + continue; + + debugfs_create_file(subsystems[i].name, 0400, root, (void *)&subsystems[i], + &qcom_subsystem_sleep_stats_fops); + } +} + +static int qcom_stats_probe(struct platform_device *pdev) +{ + void __iomem *reg; + struct dentry *root; + const struct stats_config *config; + struct stats_data *d; + int i; + + config = device_get_match_data(&pdev->dev); + if (!config) + return -ENODEV; + + reg = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(reg)) + return -ENOMEM; + + d = devm_kcalloc(&pdev->dev, config->num_records, + sizeof(*d), GFP_KERNEL); + if (!d) + return -ENOMEM; + + for (i = 0; i < config->num_records; i++) + d[i].appended_stats_avail = config->appended_stats_avail; + + root = debugfs_create_dir("qcom_stats", NULL); + + qcom_create_subsystem_stat_files(root, config); + qcom_create_soc_sleep_stat_files(root, reg, d, config); + + platform_set_drvdata(pdev, root); + + return 0; +} + +static int qcom_stats_remove(struct platform_device *pdev) +{ + struct dentry *root = platform_get_drvdata(pdev); + + debugfs_remove_recursive(root); + + return 0; +} + +static const struct stats_config rpm_data = { + .stats_offset = 0, + .num_records = 2, + .appended_stats_avail = true, + .dynamic_offset = true, + .subsystem_stats_in_smem = false, +}; + +static const struct stats_config rpmh_data = { + .stats_offset = 0x48, + .num_records = 3, + .appended_stats_avail = false, + .dynamic_offset = false, + .subsystem_stats_in_smem = true, +}; + +static const struct of_device_id qcom_stats_table[] = { + { .compatible = "qcom,rpm-stats", .data = &rpm_data }, + { .compatible = "qcom,rpmh-stats", .data = &rpmh_data }, + { } +}; +MODULE_DEVICE_TABLE(of, qcom_stats_table); + +static struct platform_driver qcom_stats = { + .probe = qcom_stats_probe, + .remove = qcom_stats_remove, + .driver = { + .name = "qcom_stats", + .of_match_table = qcom_stats_table, + }, +}; + +static int __init qcom_stats_init(void) +{ + return platform_driver_register(&qcom_stats); +} +late_initcall(qcom_stats_init); + +static void __exit qcom_stats_exit(void) +{ + platform_driver_unregister(&qcom_stats); +} +module_exit(qcom_stats_exit) + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. (QTI) Stats driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 85f755083b23b1ee59c96df80f148e6203bb078f Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 5 Oct 2021 21:43:23 +0530 Subject: soc: qcom: smp2p: add feature negotiation and ssr ack feature support This patch adds feature negotiation and ssr ack feature between local host and remote processor. Local host can negotiate on common features supported with remote processor. When ssr ack feature bit is set, the remote processor will tell local host when it is reinitialized. All clients registered for falling edge interrupts will be notified when the smp2p entries are cleared for ssr. Signed-off-by: Chris Lew Signed-off-by: Deepak Kumar Singh Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1633450403-21281-1-git-send-email-deesin@codeaurora.org --- drivers/soc/qcom/smp2p.c | 121 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 96 insertions(+), 25 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 38585a7edfe7..11b95113e38e 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -41,8 +41,11 @@ #define SMP2P_MAX_ENTRY_NAME 16 #define SMP2P_FEATURE_SSR_ACK 0x1 +#define SMP2P_FLAGS_RESTART_DONE_BIT 0 +#define SMP2P_FLAGS_RESTART_ACK_BIT 1 #define SMP2P_MAGIC 0x504d5324 +#define SMP2P_ALL_FEATURES SMP2P_FEATURE_SSR_ACK /** * struct smp2p_smem_item - in memory communication structure @@ -136,6 +139,10 @@ struct qcom_smp2p { unsigned valid_entries; + bool ssr_ack_enabled; + bool ssr_ack; + bool negotiation_done; + unsigned local_pid; unsigned remote_pid; @@ -163,22 +170,53 @@ static void qcom_smp2p_kick(struct qcom_smp2p *smp2p) } } -/** - * qcom_smp2p_intr() - interrupt handler for incoming notifications - * @irq: unused - * @data: smp2p driver context - * - * Handle notifications from the remote side to handle newly allocated entries - * or any changes to the state bits of existing entries. - */ -static irqreturn_t qcom_smp2p_intr(int irq, void *data) +static bool qcom_smp2p_check_ssr(struct qcom_smp2p *smp2p) +{ + struct smp2p_smem_item *in = smp2p->in; + bool restart; + + if (!smp2p->ssr_ack_enabled) + return false; + + restart = in->flags & BIT(SMP2P_FLAGS_RESTART_DONE_BIT); + + return restart != smp2p->ssr_ack; +} + +static void qcom_smp2p_do_ssr_ack(struct qcom_smp2p *smp2p) +{ + struct smp2p_smem_item *out = smp2p->out; + u32 val; + + smp2p->ssr_ack = !smp2p->ssr_ack; + + val = out->flags & ~BIT(SMP2P_FLAGS_RESTART_ACK_BIT); + if (smp2p->ssr_ack) + val |= BIT(SMP2P_FLAGS_RESTART_ACK_BIT); + out->flags = val; + + qcom_smp2p_kick(smp2p); +} + +static void qcom_smp2p_negotiate(struct qcom_smp2p *smp2p) +{ + struct smp2p_smem_item *out = smp2p->out; + struct smp2p_smem_item *in = smp2p->in; + + if (in->version == out->version) { + out->features &= in->features; + + if (out->features & SMP2P_FEATURE_SSR_ACK) + smp2p->ssr_ack_enabled = true; + + smp2p->negotiation_done = true; + } +} + +static void qcom_smp2p_notify_in(struct qcom_smp2p *smp2p) { struct smp2p_smem_item *in; struct smp2p_entry *entry; - struct qcom_smp2p *smp2p = data; - unsigned smem_id = smp2p->smem_items[SMP2P_INBOUND]; - unsigned pid = smp2p->remote_pid; - size_t size; int irq_pin; u32 status; char buf[SMP2P_MAX_ENTRY_NAME]; @@ -187,18 +225,6 @@ static irqreturn_t qcom_smp2p_intr(int irq, void *data) in = smp2p->in; - /* Acquire smem item, if not already found */ - if (!in) { - in = qcom_smem_get(pid, smem_id, &size); - if (IS_ERR(in)) { - dev_err(smp2p->dev, - "Unable to acquire remote smp2p item\n"); - return IRQ_HANDLED; - } - - smp2p->in = in; - } - /* Match newly created entries */ for (i = smp2p->valid_entries; i < in->valid_entries; i++) { list_for_each_entry(entry, &smp2p->inbound, node) { @@ -237,7 +263,51 @@ static irqreturn_t qcom_smp2p_intr(int irq, void *data) } } } +} + +/** + * qcom_smp2p_intr() - interrupt handler for incoming notifications + * @irq: unused + * @data: smp2p driver context + * + * Handle notifications from the remote side to handle newly allocated entries + * or any changes to the state bits of existing entries. + */ +static irqreturn_t qcom_smp2p_intr(int irq, void *data) +{ + struct smp2p_smem_item *in; + struct qcom_smp2p *smp2p = data; + unsigned int smem_id = smp2p->smem_items[SMP2P_INBOUND]; + unsigned int pid = smp2p->remote_pid; + bool ack_restart; + size_t size; + + in = smp2p->in; + + /* Acquire smem item, if not already found */ + if (!in) { + in = qcom_smem_get(pid, smem_id, &size); + if (IS_ERR(in)) { + dev_err(smp2p->dev, + "Unable to acquire remote smp2p item\n"); + goto out; + } + + smp2p->in = in; + } + + if (!smp2p->negotiation_done) + qcom_smp2p_negotiate(smp2p); + + if (smp2p->negotiation_done) { + ack_restart = qcom_smp2p_check_ssr(smp2p); + qcom_smp2p_notify_in(smp2p); + + if (ack_restart) + qcom_smp2p_do_ssr_ack(smp2p); + } +out: return IRQ_HANDLED; } @@ -393,6 +463,7 @@ static int qcom_smp2p_alloc_outbound_item(struct qcom_smp2p *smp2p) out->remote_pid = smp2p->remote_pid; out->total_entries = SMP2P_MAX_ENTRY; out->valid_entries = 0; + out->features = SMP2P_ALL_FEATURES; /* * Make sure the rest of the header is written before we validate the -- cgit v1.2.3 From e0162129c6763eb02765a1b33fdaac6980fb0c46 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:16:29 +0800 Subject: soc: fsl: guts: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Li Yang --- drivers/soc/fsl/guts.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c index d5e9a5f2c087..072473a16f4d 100644 --- a/drivers/soc/fsl/guts.c +++ b/drivers/soc/fsl/guts.c @@ -140,7 +140,6 @@ static int fsl_guts_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; - struct resource *res; const struct fsl_soc_die_attr *soc_die; const char *machine; u32 svr; @@ -152,8 +151,7 @@ static int fsl_guts_probe(struct platform_device *pdev) guts->little_endian = of_property_read_bool(np, "little-endian"); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - guts->regs = devm_ioremap_resource(dev, res); + guts->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(guts->regs)) return PTR_ERR(guts->regs); -- cgit v1.2.3 From ea41191165fdce7baef9a9ab09523c6d3d0525e1 Mon Sep 17 00:00:00 2001 From: Cai Huoqing Date: Wed, 8 Sep 2021 15:16:30 +0800 Subject: soc: fsl: rcpm: Make use of the helper function devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing Signed-off-by: Li Yang --- drivers/soc/fsl/rcpm.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c index 90d3f4060b0c..3d0cae30c769 100644 --- a/drivers/soc/fsl/rcpm.c +++ b/drivers/soc/fsl/rcpm.c @@ -146,7 +146,6 @@ static const struct dev_pm_ops rcpm_pm_ops = { static int rcpm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct resource *r; struct rcpm *rcpm; int ret; @@ -154,11 +153,7 @@ static int rcpm_probe(struct platform_device *pdev) if (!rcpm) return -ENOMEM; - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) - return -ENODEV; - - rcpm->ippdexpcr_base = devm_ioremap_resource(&pdev->dev, r); + rcpm->ippdexpcr_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rcpm->ippdexpcr_base)) { ret = PTR_ERR(rcpm->ippdexpcr_base); return ret; -- cgit v1.2.3 From a7ff7dcaf4d2dfbfd901e28ab0101ee9a1b8bf98 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Thu, 14 Oct 2021 17:49:22 +0300 Subject: soc: fsl: dpio: use an explicit NULL instead of 0 Use an explicit NULL pointer when calling qbman_swp_enqueue_multiple() instead of a plain integer. Without this fix, we get the following compile time error. drivers/soc/fsl/dpio/dpio-service.c:466:60: warning: Using plain integer as NULL pointer Fixes: 9d98809711ae ("soc: fsl: dpio: Adding QMAN multiple enqueue interface") Signed-off-by: Ioana Ciornei Signed-off-by: Li Yang --- drivers/soc/fsl/dpio/dpio-service.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/fsl/dpio/dpio-service.c b/drivers/soc/fsl/dpio/dpio-service.c index 7351f3030550..23ff027b9986 100644 --- a/drivers/soc/fsl/dpio/dpio-service.c +++ b/drivers/soc/fsl/dpio/dpio-service.c @@ -462,7 +462,7 @@ int dpaa2_io_service_enqueue_multiple_fq(struct dpaa2_io *d, qbman_eq_desc_set_no_orp(&ed, 0); qbman_eq_desc_set_fq(&ed, fqid); - return qbman_swp_enqueue_multiple(d->swp, &ed, fd, 0, nb); + return qbman_swp_enqueue_multiple(d->swp, &ed, fd, NULL, nb); } EXPORT_SYMBOL(dpaa2_io_service_enqueue_multiple_fq); -- cgit v1.2.3 From 54c8b5b6f8a868b9c21a7b0efe92ed2fbcc67080 Mon Sep 17 00:00:00 2001 From: Youri Querry Date: Wed, 21 Apr 2021 09:56:44 -0400 Subject: soc: fsl: dpio: rename the enqueue descriptor variable The struct qbman_eq_desc 'd' variable declaration is covering one of the function parameters. This has no functional impact since this function parameter was not used after the new declaration. Even so, rename the variable so that we make the code more readable. Fixes: 3b2abda7d28c ("soc: fsl: dpio: Replace QMAN array mode with ring mode enqueue") Signed-off-by: Youri Querry Signed-off-by: Ioana Ciornei Signed-off-by: Li Yang --- drivers/soc/fsl/dpio/qbman-portal.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/fsl/dpio/qbman-portal.c b/drivers/soc/fsl/dpio/qbman-portal.c index f13da4d7d1c5..caddcf0dbc60 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.c +++ b/drivers/soc/fsl/dpio/qbman-portal.c @@ -688,9 +688,9 @@ int qbman_swp_enqueue_multiple_direct(struct qbman_swp *s, p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); p[0] = cl[0] | s->eqcr.pi_vb; if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) { - struct qbman_eq_desc *d = (struct qbman_eq_desc *)p; + struct qbman_eq_desc *eq_desc = (struct qbman_eq_desc *)p; - d->dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | + eq_desc->dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK); } eqcr_pi++; @@ -770,9 +770,9 @@ int qbman_swp_enqueue_multiple_mem_back(struct qbman_swp *s, p = (s->addr_cena + QBMAN_CENA_SWP_EQCR(eqcr_pi & half_mask)); p[0] = cl[0] | s->eqcr.pi_vb; if (flags && (flags[i] & QBMAN_ENQUEUE_FLAG_DCA)) { - struct qbman_eq_desc *d = (struct qbman_eq_desc *)p; + struct qbman_eq_desc *eq_desc = (struct qbman_eq_desc *)p; - d->dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | + eq_desc->dca = (1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT) | ((flags[i]) & QBMAN_EQCR_DCA_IDXMASK); } eqcr_pi++; -- cgit v1.2.3 From c6807970c3bc0aa80f4804fc7d38b32f99fc3cf6 Mon Sep 17 00:00:00 2001 From: Chia-Wei Wang Date: Fri, 22 Oct 2021 10:36:16 +1030 Subject: soc: aspeed: Add UART routing support Add driver support for the UART routing control. Users can perform runtime configuration of the RX muxes among the UART controllers and the UART IO pins. The sysfs interface is also exported for the convenience of routing paths check and update. Signed-off-by: Oskar Senft Signed-off-by: Chia-Wei Wang Signed-off-by: Joel Stanley Tested-by: Lei YU Link: https://lore.kernel.org/r/20210927023053.6728-5-chiawei_wang@aspeedtech.com Link: https://lore.kernel.org/r/20211022000616.481772-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann --- .../ABI/testing/sysfs-driver-aspeed-uart-routing | 27 + drivers/soc/aspeed/Kconfig | 10 + drivers/soc/aspeed/Makefile | 9 +- drivers/soc/aspeed/aspeed-uart-routing.c | 603 +++++++++++++++++++++ 4 files changed, 645 insertions(+), 4 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c (limited to 'drivers/soc') diff --git a/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing new file mode 100644 index 000000000000..b363827da437 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing @@ -0,0 +1,27 @@ +What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart* +Date: September 2021 +Contact: Oskar Senft + Chia-Wei Wang +Description: Selects the RX source of the UARTx device. + + When read, each file shows the list of available options with currently + selected option marked by brackets "[]". The list of available options + depends on the selected file. + + e.g. + cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1 + [io1] io2 io3 io4 uart2 uart3 uart4 io6 + + In this case, UART1 gets its input from IO1 (physical serial port 1). + +Users: OpenBMC. Proposed changes should be mailed to + openbmc@lists.ozlabs.org + +What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io* +Date: September 2021 +Contact: Oskar Senft + Chia-Wei Wang +Description: Selects the RX source of IOx serial port. The current selection + will be marked by brackets "[]". +Users: OpenBMC. Proposed changes should be mailed to + openbmc@lists.ozlabs.org diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 243ca196e6ad..f579ee0b5afa 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -24,6 +24,16 @@ config ASPEED_LPC_SNOOP allows the BMC to listen on and save the data written by the host to an arbitrary LPC I/O port. +config ASPEED_UART_ROUTING + tristate "ASPEED uart routing control" + select REGMAP + select MFD_SYSCON + default ARCH_ASPEED + help + Provides a driver to control the UART routing paths, allowing + users to perform runtime configuration of the RX muxes among + the UART controllers and I/O pins. + config ASPEED_P2A_CTRL tristate "ASPEED P2A (VGA MMIO to BMC) bridge control" select REGMAP diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile index fcab7192e1a4..b35d74592964 100644 --- a/drivers/soc/aspeed/Makefile +++ b/drivers/soc/aspeed/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o -obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o -obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o -obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o +obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o +obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o +obj-$(CONFIG_ASPEED_UART_ROUTING) += aspeed-uart-routing.o +obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o +obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o diff --git a/drivers/soc/aspeed/aspeed-uart-routing.c b/drivers/soc/aspeed/aspeed-uart-routing.c new file mode 100644 index 000000000000..ef8b24fd1851 --- /dev/null +++ b/drivers/soc/aspeed/aspeed-uart-routing.c @@ -0,0 +1,603 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 Google LLC + * Copyright (c) 2021 Aspeed Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include + +/* register offsets */ +#define HICR9 0x98 +#define HICRA 0x9c + +/* attributes options */ +#define UART_ROUTING_IO1 "io1" +#define UART_ROUTING_IO2 "io2" +#define UART_ROUTING_IO3 "io3" +#define UART_ROUTING_IO4 "io4" +#define UART_ROUTING_IO5 "io5" +#define UART_ROUTING_IO6 "io6" +#define UART_ROUTING_IO10 "io10" +#define UART_ROUTING_UART1 "uart1" +#define UART_ROUTING_UART2 "uart2" +#define UART_ROUTING_UART3 "uart3" +#define UART_ROUTING_UART4 "uart4" +#define UART_ROUTING_UART5 "uart5" +#define UART_ROUTING_UART6 "uart6" +#define UART_ROUTING_UART10 "uart10" +#define UART_ROUTING_RES "reserved" + +struct aspeed_uart_routing { + struct regmap *map; + struct attribute_group const *attr_grp; +}; + +struct aspeed_uart_routing_selector { + struct device_attribute dev_attr; + uint8_t reg; + uint8_t mask; + uint8_t shift; + const char *const options[]; +}; + +#define to_routing_selector(_dev_attr) \ + container_of(_dev_attr, struct aspeed_uart_routing_selector, dev_attr) + +static ssize_t aspeed_uart_routing_show(struct device *dev, + struct device_attribute *attr, + char *buf); + +static ssize_t aspeed_uart_routing_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +#define ROUTING_ATTR(_name) { \ + .attr = {.name = _name, \ + .mode = VERIFY_OCTAL_PERMISSIONS(0644) }, \ + .show = aspeed_uart_routing_show, \ + .store = aspeed_uart_routing_store, \ +} + +/* routing selector for AST25xx */ +static struct aspeed_uart_routing_selector ast2500_io6_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO6), + .reg = HICR9, + .shift = 8, + .mask = 0xf, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO5, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart5_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART5), + .reg = HICRA, + .shift = 28, + .mask = 0xf, + .options = { + UART_ROUTING_IO5, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4), + .reg = HICRA, + .shift = 25, + .mask = 0x7, + .options = { + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3), + .reg = HICRA, + .shift = 22, + .mask = 0x7, + .options = { + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2), + .reg = HICRA, + .shift = 19, + .mask = 0x7, + .options = { + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_uart1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1), + .reg = HICRA, + .shift = 16, + .mask = 0x7, + .options = { + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io5_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO5), + .reg = HICRA, + .shift = 12, + .mask = 0x7, + .options = { + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO1, + UART_ROUTING_IO3, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4), + .reg = HICRA, + .shift = 9, + .mask = 0x7, + .options = { + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3), + .reg = HICRA, + .shift = 6, + .mask = 0x7, + .options = { + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2), + .reg = HICRA, + .shift = 3, + .mask = 0x7, + .options = { + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_UART1, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2500_io1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1), + .reg = HICRA, + .shift = 0, + .mask = 0x7, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART5, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO6, + NULL, + }, +}; + +static struct attribute *ast2500_uart_routing_attrs[] = { + &ast2500_io6_sel.dev_attr.attr, + &ast2500_uart5_sel.dev_attr.attr, + &ast2500_uart4_sel.dev_attr.attr, + &ast2500_uart3_sel.dev_attr.attr, + &ast2500_uart2_sel.dev_attr.attr, + &ast2500_uart1_sel.dev_attr.attr, + &ast2500_io5_sel.dev_attr.attr, + &ast2500_io4_sel.dev_attr.attr, + &ast2500_io3_sel.dev_attr.attr, + &ast2500_io2_sel.dev_attr.attr, + &ast2500_io1_sel.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ast2500_uart_routing_attr_group = { + .attrs = ast2500_uart_routing_attrs, +}; + +/* routing selector for AST26xx */ +static struct aspeed_uart_routing_selector ast2600_uart10_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART10), + .reg = HICR9, + .shift = 12, + .mask = 0xf, + .options = { + UART_ROUTING_IO10, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_RES, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io10_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO10), + .reg = HICR9, + .shift = 8, + .mask = 0xf, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_RES, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_RES, + UART_ROUTING_UART10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4), + .reg = HICRA, + .shift = 25, + .mask = 0x7, + .options = { + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3), + .reg = HICRA, + .shift = 22, + .mask = 0x7, + .options = { + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2), + .reg = HICRA, + .shift = 19, + .mask = 0x7, + .options = { + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO1, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART1, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_uart1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1), + .reg = HICRA, + .shift = 16, + .mask = 0x7, + .options = { + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io4_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4), + .reg = HICRA, + .shift = 9, + .mask = 0x7, + .options = { + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io3_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3), + .reg = HICRA, + .shift = 6, + .mask = 0x7, + .options = { + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_IO1, + UART_ROUTING_IO2, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io2_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2), + .reg = HICRA, + .shift = 3, + .mask = 0x7, + .options = { + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_UART1, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct aspeed_uart_routing_selector ast2600_io1_sel = { + .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1), + .reg = HICRA, + .shift = 0, + .mask = 0x7, + .options = { + UART_ROUTING_UART1, + UART_ROUTING_UART2, + UART_ROUTING_UART3, + UART_ROUTING_UART4, + UART_ROUTING_UART10, + UART_ROUTING_IO3, + UART_ROUTING_IO4, + UART_ROUTING_IO10, + NULL, + }, +}; + +static struct attribute *ast2600_uart_routing_attrs[] = { + &ast2600_uart10_sel.dev_attr.attr, + &ast2600_io10_sel.dev_attr.attr, + &ast2600_uart4_sel.dev_attr.attr, + &ast2600_uart3_sel.dev_attr.attr, + &ast2600_uart2_sel.dev_attr.attr, + &ast2600_uart1_sel.dev_attr.attr, + &ast2600_io4_sel.dev_attr.attr, + &ast2600_io3_sel.dev_attr.attr, + &ast2600_io2_sel.dev_attr.attr, + &ast2600_io1_sel.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ast2600_uart_routing_attr_group = { + .attrs = ast2600_uart_routing_attrs, +}; + +static ssize_t aspeed_uart_routing_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev); + struct aspeed_uart_routing_selector *sel = to_routing_selector(attr); + int val, pos, len; + + regmap_read(uart_routing->map, sel->reg, &val); + val = (val >> sel->shift) & sel->mask; + + len = 0; + for (pos = 0; sel->options[pos] != NULL; ++pos) { + if (pos == val) + len += sysfs_emit_at(buf, len, "[%s] ", sel->options[pos]); + else + len += sysfs_emit_at(buf, len, "%s ", sel->options[pos]); + } + + if (val >= pos) + len += sysfs_emit_at(buf, len, "[unknown(%d)]", val); + + len += sysfs_emit_at(buf, len, "\n"); + + return len; +} + +static ssize_t aspeed_uart_routing_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev); + struct aspeed_uart_routing_selector *sel = to_routing_selector(attr); + int val; + + val = match_string(sel->options, -1, buf); + if (val < 0) { + dev_err(dev, "invalid value \"%s\"\n", buf); + return -EINVAL; + } + + regmap_update_bits(uart_routing->map, sel->reg, + (sel->mask << sel->shift), + (val & sel->mask) << sel->shift); + + return count; +} + +static int aspeed_uart_routing_probe(struct platform_device *pdev) +{ + int rc; + struct device *dev = &pdev->dev; + struct aspeed_uart_routing *uart_routing; + + uart_routing = devm_kzalloc(&pdev->dev, sizeof(*uart_routing), GFP_KERNEL); + if (!uart_routing) + return -ENOMEM; + + uart_routing->map = syscon_node_to_regmap(dev->parent->of_node); + if (IS_ERR(uart_routing->map)) { + dev_err(dev, "cannot get regmap\n"); + return PTR_ERR(uart_routing->map); + } + + uart_routing->attr_grp = of_device_get_match_data(dev); + + rc = sysfs_create_group(&dev->kobj, uart_routing->attr_grp); + if (rc < 0) + return rc; + + dev_set_drvdata(dev, uart_routing); + + dev_info(dev, "module loaded\n"); + + return 0; +} + +static int aspeed_uart_routing_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct aspeed_uart_routing *uart_routing = platform_get_drvdata(pdev); + + sysfs_remove_group(&dev->kobj, uart_routing->attr_grp); + + return 0; +} + +static const struct of_device_id aspeed_uart_routing_table[] = { + { .compatible = "aspeed,ast2400-uart-routing", + .data = &ast2500_uart_routing_attr_group }, + { .compatible = "aspeed,ast2500-uart-routing", + .data = &ast2500_uart_routing_attr_group }, + { .compatible = "aspeed,ast2600-uart-routing", + .data = &ast2600_uart_routing_attr_group }, + { }, +}; + +static struct platform_driver aspeed_uart_routing_driver = { + .driver = { + .name = "aspeed-uart-routing", + .of_match_table = aspeed_uart_routing_table, + }, + .probe = aspeed_uart_routing_probe, + .remove = aspeed_uart_routing_remove, +}; + +module_platform_driver(aspeed_uart_routing_driver); + +MODULE_AUTHOR("Oskar Senft "); +MODULE_AUTHOR("Chia-Wei Wang "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Driver to configure Aspeed UART routing"); -- cgit v1.2.3 From 87fd343c6e398e3a1d3368a4a8c9833dce0894ff Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 4 Oct 2021 19:40:25 -0700 Subject: soc: qcom: socinfo: Add PM8150C and SMB2351 models Add PM8150C and SMB2351 to the list of known PMIC models. Signed-off-by: Bjorn Andersson Reviewed-by: Bhupesh Sharma Link: https://lore.kernel.org/r/20211005024025.2037810-1-bjorn.andersson@linaro.org --- drivers/soc/qcom/socinfo.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index bec6eb910cba..553554e7116e 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -102,6 +102,8 @@ static const char *const pmic_models[] = { [32] = "PM8150B", [33] = "PMK8002", [36] = "PM8009", + [38] = "PM8150C", + [41] = "SMB2351", }; #endif /* CONFIG_DEBUG_FS */ -- cgit v1.2.3 From 7f8adb19e97339d0b36ea98e61d8c455efd86874 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Mon, 4 Oct 2021 22:49:51 +0200 Subject: soc: qcom: spm: Add 8916 SPM register data Add SPM register information and initialization values for QCOM 8916 SoC. Link: https://lore.kernel.org/linux-arm-msm/1429314549-6730-5-git-send-email-lina.iyer@linaro.org/ Signed-off-by: Lina Iyer [stephan: rebase patch and fix conflicts] Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211004204955.21077-11-stephan@gerhold.net --- drivers/soc/qcom/spm.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2961a89d929c..f831420b7fd4 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -67,6 +67,25 @@ static const struct spm_reg_data spm_reg_8998_silver_l2 = { .avs_limit = 0x4200420, }; +static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = { + [SPM_REG_CFG] = 0x08, + [SPM_REG_SPM_CTL] = 0x30, + [SPM_REG_DLY] = 0x34, + [SPM_REG_SEQ_ENTRY] = 0x400, +}; + +/* SPM register data for 8916 */ +static const struct spm_reg_data spm_reg_8916_cpu = { + .reg_offset = spm_reg_offset_v3_0, + .spm_cfg = 0x1, + .spm_dly = 0x3C102800, + .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90, + 0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B, + 0x80, 0x10, 0x26, 0x30, 0x0F }, + .start_index[PM_SLEEP_MODE_STBY] = 0, + .start_index[PM_SLEEP_MODE_SPC] = 5, +}; + static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, [SPM_REG_SPM_CTL] = 0x30, @@ -176,6 +195,8 @@ static const struct of_device_id spm_match_table[] = { .data = &spm_reg_660_silver_l2 }, { .compatible = "qcom,msm8226-saw2-v2.1-cpu", .data = &spm_reg_8226_cpu }, + { .compatible = "qcom,msm8916-saw2-v3.0-cpu", + .data = &spm_reg_8916_cpu }, { .compatible = "qcom,msm8974-saw2-v2.1-cpu", .data = &spm_reg_8974_8084_cpu }, { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2", -- cgit v1.2.3 From 086f52fdc8f7bd273d06a3de2adf65a063eb5392 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 20 Oct 2021 04:26:39 +0300 Subject: soc: qcom: rpmhpd: fix sm8350_mxc's peer domain The sm8350_mxc's domain description incorrectly references sm8150_mmcx_ao as a peer instead of sm8350_mxc_ao. Correct this typo. Fixes: 639c85628757 ("soc: qcom: rpmhpd: Add SM8350 power domains") Cc: Vinod Koul Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211020012639.1183806-1-dmitry.baryshkov@linaro.org --- drivers/soc/qcom/rpmhpd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 0ca77ed22c6c..1118345d8824 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -221,7 +221,7 @@ static const struct rpmhpd_desc sm8250_desc = { static struct rpmhpd sm8350_mxc_ao; static struct rpmhpd sm8350_mxc = { .pd = { .name = "mxc", }, - .peer = &sm8150_mmcx_ao, + .peer = &sm8350_mxc_ao, .res_name = "mxc.lvl", }; -- cgit v1.2.3 From 62563bd99c7d7be269982b88173ad8938420d648 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 20 Oct 2021 14:19:13 +0530 Subject: soc: qcom: qcom_stats: Fix client votes offset Client votes starts at 0x20 offset. Correct the offset. Reported-and-suggested-by: Shawn Guo Fixes: 1d7724690344 ("soc: qcom: Add Sleep stats driver") Signed-off-by: Maulik Shah Reviewed-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1634719753-26064-1-git-send-email-mkshah@codeaurora.org --- drivers/soc/qcom/qcom_stats.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/qcom_stats.c b/drivers/soc/qcom/qcom_stats.c index 817505bd99b5..131d24caabf8 100644 --- a/drivers/soc/qcom/qcom_stats.c +++ b/drivers/soc/qcom/qcom_stats.c @@ -22,7 +22,7 @@ #define LAST_ENTERED_AT_OFFSET 0x8 #define LAST_EXITED_AT_OFFSET 0x10 #define ACCUMULATED_OFFSET 0x18 -#define CLIENT_VOTES_OFFSET 0x1c +#define CLIENT_VOTES_OFFSET 0x20 struct subsystem_data { const char *name; -- cgit v1.2.3 From 72f1aa6205d84337b90b065f602a8fe190821781 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Thu, 14 Oct 2021 04:30:17 -0400 Subject: soc: qcom: apr: Add of_node_put() before return Fix following coccicheck warning: ./drivers/soc/qcom/apr.c:485:1-23: WARNING: Function for_each_child_of_node should have of_node_put() before return Early exits from for_each_child_of_node should decrement the node reference counter. Fixes: 834735662602 ("soc: qcom: apr: Add avs/audio tracking functionality") Signed-off-by: Wan Jiabing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211014083017.19714-1-wanjiabing@vivo.com --- drivers/soc/qcom/apr.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index 8a9bfbcd4bb9..82ca12c9328a 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -492,12 +492,14 @@ static int of_apr_add_pd_lookups(struct device *dev) 1, &service_path); if (ret < 0) { dev_err(dev, "pdr service path missing: %d\n", ret); + of_node_put(node); return ret; } pds = pdr_add_lookup(apr->pdr, service_name, service_path); if (IS_ERR(pds) && PTR_ERR(pds) != -EALREADY) { dev_err(dev, "pdr add lookup failed: %ld\n", PTR_ERR(pds)); + of_node_put(node); return PTR_ERR(pds); } } -- cgit v1.2.3 From e1b391e9712db4880394e727ae623b96ee18d618 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Thu, 14 Oct 2021 02:23:49 -0400 Subject: soc: qcom: smp2p: Add of_node_put() before goto Fix following coccicheck warning: ./drivers/soc/qcom/smp2p.c:501:1-33: WARNING: Function for_each_available_child_of_node should have of_node_put() before goto Early exits from for_each_available_child_of_node should decrement the node reference counter. Signed-off-by: Wan Jiabing Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211014062350.8942-1-wanjiabing@vivo.com --- drivers/soc/qcom/smp2p.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 11b95113e38e..4a157240f419 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -573,6 +573,7 @@ static int qcom_smp2p_probe(struct platform_device *pdev) entry = devm_kzalloc(&pdev->dev, sizeof(*entry), GFP_KERNEL); if (!entry) { ret = -ENOMEM; + of_node_put(node); goto unwind_interfaces; } @@ -580,19 +581,25 @@ static int qcom_smp2p_probe(struct platform_device *pdev) spin_lock_init(&entry->lock); ret = of_property_read_string(node, "qcom,entry-name", &entry->name); - if (ret < 0) + if (ret < 0) { + of_node_put(node); goto unwind_interfaces; + } if (of_property_read_bool(node, "interrupt-controller")) { ret = qcom_smp2p_inbound_entry(smp2p, entry, node); - if (ret < 0) + if (ret < 0) { + of_node_put(node); goto unwind_interfaces; + } list_add(&entry->node, &smp2p->inbound); } else { ret = qcom_smp2p_outbound_entry(smp2p, entry, node); - if (ret < 0) + if (ret < 0) { + of_node_put(node); goto unwind_interfaces; + } list_add(&entry->node, &smp2p->outbound); } -- cgit v1.2.3 From b417d1e88f32645ed62a00d43c347b4386a0a021 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Thu, 21 Oct 2021 10:20:16 +0900 Subject: soc: samsung: exynos-chipid: add exynosautov9 SoC support The product id of Exynos Auto v9 is "0xAAA8_0000". Add this id and its name. Cc: Sam Protsenko Signed-off-by: Chanho Park Link: https://lore.kernel.org/r/20211021012017.158919-2-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-chipid.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/soc') diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 0aeb24bcc11a..a28053ec7e6a 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -56,6 +56,7 @@ static const struct exynos_soc_id { { "EXYNOS5800", 0xE5422000 }, { "EXYNOS7420", 0xE7420000 }, { "EXYNOS850", 0xE3830000 }, + { "EXYNOSAUTOV9", 0xAAA80000 }, }; static const char *product_id_to_soc_id(unsigned int product_id) -- cgit v1.2.3 From 4f22aa4569e55131d69dae87e76869070d62c392 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 19 Oct 2021 17:42:02 +0200 Subject: qcom: spm: allow compile-testing ARM_QCOM_SPM_CPUIDLE can be selected when compile-testing on other architectures, but this causes a Kconfig warning for QCOM_SPM: WARNING: unmet direct dependencies detected for QCOM_SPM Depends on [n]: ARCH_QCOM [=n] Selected by [y]: - ARM_QCOM_SPM_CPUIDLE [=y] && CPU_IDLE [=y] && (ARM [=y] || ARM64) && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && !ARM64 && MMU [=y] Make it possible to also compile-test this one, which can be done now that v5.15-rc5 lets you select QCOM_SCM everywhere. Fixes: a871be6b8eee ("cpuidle: Convert Qualcomm SPM driver to a generic CPUidle driver") Fixes: 498ba2a8a275 ("cpuidle: Fix ARM_QCOM_SPM_CPUIDLE configuration") Reviewed-by: Stephen Boyd Signed-off-by: Arnd Bergmann --- drivers/soc/qcom/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 3cf3a6b41182..e718b8735444 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -192,7 +192,7 @@ config QCOM_SOCINFO config QCOM_SPM tristate "Qualcomm Subsystem Power Manager (SPM)" - depends on ARCH_QCOM + depends on ARCH_QCOM || COMPILE_TEST select QCOM_SCM help Enable the support for the Qualcomm Subsystem Power Manager, used -- cgit v1.2.3