From efb448d0a3fca01bb987dd70963da6185b81751e Mon Sep 17 00:00:00 2001 From: Imran Khan Date: Wed, 24 Jul 2019 04:05:13 +0530 Subject: soc: qcom: Add socinfo driver The Qualcomm socinfo driver exposes information about the SoC, its version and its serial number to user space. Tested-by: Vinod Koul Reviewed-by: Vinod Koul Signed-off-by: Imran Khan [Bjorn: Extract code to platform_driver, split patch in multiple] Signed-off-by: Bjorn Andersson [Vaishali: Simplify declarations, introduce qcom_socinfo struct, Fix memory leak, Remove extra code and Misc code refactoring] Signed-off-by: Vaishali Thakkar Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/Kconfig | 8 ++ drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/smem.c | 9 +++ drivers/soc/qcom/socinfo.c | 194 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 212 insertions(+) create mode 100644 drivers/soc/qcom/socinfo.c (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a6d1bfb17279..661e47acc354 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -175,6 +175,14 @@ config QCOM_SMSM Say yes here to support the Qualcomm Shared Memory State Machine. The state machine is represented by bits in shared memory. +config QCOM_SOCINFO + tristate "Qualcomm socinfo driver" + depends on QCOM_SMEM + select SOC_BUS + help + Say yes here to support the Qualcomm socinfo driver, providing + information about the SoC to user space. + config QCOM_WCNSS_CTRL tristate "Qualcomm WCNSS control driver" depends on ARCH_QCOM || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index eeb088beb15f..162788701a77 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_QCOM_SMEM) += smem.o obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o obj-$(CONFIG_QCOM_SMSM) += smsm.o +obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o obj-$(CONFIG_QCOM_APR) += apr.o obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index f27c00d82ae4..0caf67e2f037 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -268,6 +268,7 @@ struct qcom_smem { struct smem_partition_header *partitions[SMEM_HOST_COUNT]; size_t cacheline[SMEM_HOST_COUNT]; u32 item_count; + struct platform_device *socinfo; unsigned num_regions; struct smem_region regions[]; @@ -963,11 +964,19 @@ static int qcom_smem_probe(struct platform_device *pdev) __smem = smem; + smem->socinfo = platform_device_register_data(&pdev->dev, "qcom-socinfo", + PLATFORM_DEVID_NONE, NULL, + 0); + if (IS_ERR(smem->socinfo)) + dev_dbg(&pdev->dev, "failed to register socinfo device\n"); + return 0; } static int qcom_smem_remove(struct platform_device *pdev) { + platform_device_unregister(__smem->socinfo); + hwspin_lock_free(__smem->hwlock); __smem = NULL; diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c new file mode 100644 index 000000000000..1b9eb44df7fe --- /dev/null +++ b/drivers/soc/qcom/socinfo.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * SoC version type with major number in the upper 16 bits and minor + * number in the lower 16 bits. + */ +#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) +#define SOCINFO_MINOR(ver) ((ver) & 0xffff) + +#define SMEM_SOCINFO_BUILD_ID_LENGTH 32 + +/* + * SMEM item id, used to acquire handles to respective + * SMEM region. + */ +#define SMEM_HW_SW_BUILD_ID 137 + +/* Socinfo SMEM item structure */ +struct socinfo { + __le32 fmt; + __le32 id; + __le32 ver; + char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH]; + /* Version 2 */ + __le32 raw_id; + __le32 raw_ver; + /* Version 3 */ + __le32 hw_plat; + /* Version 4 */ + __le32 plat_ver; + /* Version 5 */ + __le32 accessory_chip; + /* Version 6 */ + __le32 hw_plat_subtype; + /* Version 7 */ + __le32 pmic_model; + __le32 pmic_die_rev; + /* Version 8 */ + __le32 pmic_model_1; + __le32 pmic_die_rev_1; + __le32 pmic_model_2; + __le32 pmic_die_rev_2; + /* Version 9 */ + __le32 foundry_id; + /* Version 10 */ + __le32 serial_num; + /* Version 11 */ + __le32 num_pmics; + __le32 pmic_array_offset; + /* Version 12 */ + __le32 chip_family; + __le32 raw_device_family; + __le32 raw_device_num; +}; + +struct qcom_socinfo { + struct soc_device *soc_dev; + struct soc_device_attribute attr; +}; + +struct soc_id { + unsigned int id; + const char *name; +}; + +static const struct soc_id soc_id[] = { + { 87, "MSM8960" }, + { 109, "APQ8064" }, + { 122, "MSM8660A" }, + { 123, "MSM8260A" }, + { 124, "APQ8060A" }, + { 126, "MSM8974" }, + { 130, "MPQ8064" }, + { 138, "MSM8960AB" }, + { 139, "APQ8060AB" }, + { 140, "MSM8260AB" }, + { 141, "MSM8660AB" }, + { 178, "APQ8084" }, + { 184, "APQ8074" }, + { 185, "MSM8274" }, + { 186, "MSM8674" }, + { 194, "MSM8974PRO" }, + { 206, "MSM8916" }, + { 208, "APQ8074-AA" }, + { 209, "APQ8074-AB" }, + { 210, "APQ8074PRO" }, + { 211, "MSM8274-AA" }, + { 212, "MSM8274-AB" }, + { 213, "MSM8274PRO" }, + { 214, "MSM8674-AA" }, + { 215, "MSM8674-AB" }, + { 216, "MSM8674PRO" }, + { 217, "MSM8974-AA" }, + { 218, "MSM8974-AB" }, + { 246, "MSM8996" }, + { 247, "APQ8016" }, + { 248, "MSM8216" }, + { 249, "MSM8116" }, + { 250, "MSM8616" }, + { 291, "APQ8096" }, + { 305, "MSM8996SG" }, + { 310, "MSM8996AU" }, + { 311, "APQ8096AU" }, + { 312, "APQ8096SG" }, +}; + +static const char *socinfo_machine(struct device *dev, unsigned int id) +{ + int idx; + + for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) { + if (soc_id[idx].id == id) + return soc_id[idx].name; + } + + return NULL; +} + +static int qcom_socinfo_probe(struct platform_device *pdev) +{ + struct qcom_socinfo *qs; + struct socinfo *info; + size_t item_size; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, + &item_size); + if (IS_ERR(info)) { + dev_err(&pdev->dev, "Couldn't find socinfo\n"); + return PTR_ERR(info); + } + + qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL); + if (!qs) + return -ENOMEM; + + qs->attr.family = "Snapdragon"; + qs->attr.machine = socinfo_machine(&pdev->dev, + le32_to_cpu(info->id)); + qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u", + SOCINFO_MAJOR(le32_to_cpu(info->ver)), + SOCINFO_MINOR(le32_to_cpu(info->ver))); + if (offsetof(struct socinfo, serial_num) <= item_size) + qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL, + "%u", + le32_to_cpu(info->serial_num)); + + qs->soc_dev = soc_device_register(&qs->attr); + if (IS_ERR(qs->soc_dev)) + return PTR_ERR(qs->soc_dev); + + /* Feed the soc specific unique data into entropy pool */ + add_device_randomness(info, item_size); + + platform_set_drvdata(pdev, qs->soc_dev); + + return 0; +} + +static int qcom_socinfo_remove(struct platform_device *pdev) +{ + struct qcom_socinfo *qs = platform_get_drvdata(pdev); + + soc_device_unregister(qs->soc_dev); + + return 0; +} + +static struct platform_driver qcom_socinfo_driver = { + .probe = qcom_socinfo_probe, + .remove = qcom_socinfo_remove, + .driver = { + .name = "qcom-socinfo", + }, +}; + +module_platform_driver(qcom_socinfo_driver); + +MODULE_DESCRIPTION("Qualcomm SoCinfo driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:qcom-socinfo"); -- cgit v1.2.3 From 9c84c1e78634bd7f93541ad9ad88e99b21495da7 Mon Sep 17 00:00:00 2001 From: Vaishali Thakkar Date: Wed, 24 Jul 2019 04:05:14 +0530 Subject: soc: qcom: socinfo: Expose custom attributes The Qualcomm socinfo provides a number of additional attributes, add these to the socinfo driver and expose them via debugfs functionality. Tested-by: Vinod Koul Reviewed-by: Vinod Koul Signed-off-by: Vaishali Thakkar Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 190 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 1b9eb44df7fe..6a4795433d57 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -4,6 +4,7 @@ * Copyright (c) 2017-2019, Linaro Ltd. */ +#include #include #include #include @@ -20,6 +21,7 @@ */ #define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) #define SOCINFO_MINOR(ver) ((ver) & 0xffff) +#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) #define SMEM_SOCINFO_BUILD_ID_LENGTH 32 @@ -29,6 +31,27 @@ */ #define SMEM_HW_SW_BUILD_ID 137 +#ifdef CONFIG_DEBUG_FS +static const char *const pmic_models[] = { + [0] = "Unknown PMIC model", + [9] = "PM8994", + [11] = "PM8916", + [13] = "PM8058", + [14] = "PM8028", + [15] = "PM8901", + [16] = "PM8027", + [17] = "ISL9519", + [18] = "PM8921", + [19] = "PM8018", + [20] = "PM8015", + [21] = "PM8014", + [22] = "PM8821", + [23] = "PM8038", + [24] = "PM8922", + [25] = "PM8917", +}; +#endif /* CONFIG_DEBUG_FS */ + /* Socinfo SMEM item structure */ struct socinfo { __le32 fmt; @@ -67,9 +90,28 @@ struct socinfo { __le32 raw_device_num; }; +#ifdef CONFIG_DEBUG_FS +struct socinfo_params { + u32 raw_device_family; + u32 hw_plat_subtype; + u32 accessory_chip; + u32 raw_device_num; + u32 chip_family; + u32 foundry_id; + u32 plat_ver; + u32 raw_ver; + u32 hw_plat; + u32 fmt; +}; +#endif /* CONFIG_DEBUG_FS */ + struct qcom_socinfo { struct soc_device *soc_dev; struct soc_device_attribute attr; +#ifdef CONFIG_DEBUG_FS + struct dentry *dbg_root; + struct socinfo_params info; +#endif /* CONFIG_DEBUG_FS */ }; struct soc_id { @@ -130,6 +172,150 @@ static const char *socinfo_machine(struct device *dev, unsigned int id) return NULL; } +#ifdef CONFIG_DEBUG_FS + +#define QCOM_OPEN(name, _func) \ +static int qcom_open_##name(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, _func, inode->i_private); \ +} \ + \ +static const struct file_operations qcom_ ##name## _ops = { \ + .open = qcom_open_##name, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} + +#define DEBUGFS_ADD(info, name) \ + debugfs_create_file(__stringify(name), 0400, \ + qcom_socinfo->dbg_root, \ + info, &qcom_ ##name## _ops) + + +static int qcom_show_build_id(struct seq_file *seq, void *p) +{ + struct socinfo *socinfo = seq->private; + + seq_printf(seq, "%s\n", socinfo->build_id); + + return 0; +} + +static int qcom_show_pmic_model(struct seq_file *seq, void *p) +{ + struct socinfo *socinfo = seq->private; + int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model)); + + if (model < 0) + return -EINVAL; + + seq_printf(seq, "%s\n", pmic_models[model]); + + return 0; +} + +static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p) +{ + struct socinfo *socinfo = seq->private; + + seq_printf(seq, "%u.%u\n", + SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)), + SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev))); + + return 0; +} + +QCOM_OPEN(build_id, qcom_show_build_id); +QCOM_OPEN(pmic_model, qcom_show_pmic_model); +QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision); + +static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, + struct socinfo *info) +{ + size_t size; + + qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL); + + qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt); + + switch (qcom_socinfo->info.fmt) { + case SOCINFO_VERSION(0, 12): + qcom_socinfo->info.chip_family = + __le32_to_cpu(info->chip_family); + qcom_socinfo->info.raw_device_family = + __le32_to_cpu(info->raw_device_family); + qcom_socinfo->info.raw_device_num = + __le32_to_cpu(info->raw_device_num); + + debugfs_create_x32("chip_family", 0400, qcom_socinfo->dbg_root, + &qcom_socinfo->info.chip_family); + debugfs_create_x32("raw_device_family", 0400, + qcom_socinfo->dbg_root, + &qcom_socinfo->info.raw_device_family); + debugfs_create_x32("raw_device_number", 0400, + qcom_socinfo->dbg_root, + &qcom_socinfo->info.raw_device_num); + case SOCINFO_VERSION(0, 11): + case SOCINFO_VERSION(0, 10): + case SOCINFO_VERSION(0, 9): + qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id); + + debugfs_create_u32("foundry_id", 0400, qcom_socinfo->dbg_root, + &qcom_socinfo->info.foundry_id); + case SOCINFO_VERSION(0, 8): + case SOCINFO_VERSION(0, 7): + DEBUGFS_ADD(info, pmic_model); + DEBUGFS_ADD(info, pmic_die_rev); + case SOCINFO_VERSION(0, 6): + qcom_socinfo->info.hw_plat_subtype = + __le32_to_cpu(info->hw_plat_subtype); + + debugfs_create_u32("hardware_platform_subtype", 0400, + qcom_socinfo->dbg_root, + &qcom_socinfo->info.hw_plat_subtype); + case SOCINFO_VERSION(0, 5): + qcom_socinfo->info.accessory_chip = + __le32_to_cpu(info->accessory_chip); + + debugfs_create_u32("accessory_chip", 0400, + qcom_socinfo->dbg_root, + &qcom_socinfo->info.accessory_chip); + case SOCINFO_VERSION(0, 4): + qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver); + + debugfs_create_u32("platform_version", 0400, + qcom_socinfo->dbg_root, + &qcom_socinfo->info.plat_ver); + case SOCINFO_VERSION(0, 3): + qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat); + + debugfs_create_u32("hardware_platform", 0400, + qcom_socinfo->dbg_root, + &qcom_socinfo->info.hw_plat); + case SOCINFO_VERSION(0, 2): + qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver); + + debugfs_create_u32("raw_version", 0400, qcom_socinfo->dbg_root, + &qcom_socinfo->info.raw_ver); + case SOCINFO_VERSION(0, 1): + DEBUGFS_ADD(info, build_id); + break; + } +} + +static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) +{ + debugfs_remove_recursive(qcom_socinfo->dbg_root); +} +#else +static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, + struct socinfo *info) +{ +} +static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { } +#endif /* CONFIG_DEBUG_FS */ + static int qcom_socinfo_probe(struct platform_device *pdev) { struct qcom_socinfo *qs; @@ -162,6 +348,8 @@ static int qcom_socinfo_probe(struct platform_device *pdev) if (IS_ERR(qs->soc_dev)) return PTR_ERR(qs->soc_dev); + socinfo_debugfs_init(qs, info); + /* Feed the soc specific unique data into entropy pool */ add_device_randomness(info, item_size); @@ -176,6 +364,8 @@ static int qcom_socinfo_remove(struct platform_device *pdev) soc_device_unregister(qs->soc_dev); + socinfo_debugfs_exit(qs); + return 0; } -- cgit v1.2.3 From cd23d1405be666a7c43045abe339bc1acaa3400b Mon Sep 17 00:00:00 2001 From: Vaishali Thakkar Date: Wed, 24 Jul 2019 04:05:15 +0530 Subject: soc: qcom: socinfo: Expose image information The socinfo driver provides information about version of the various images loaded in the system. Expose this to user space for debugging purpose. Tested-by: Vinod Koul Reviewed-by: Vinod Koul Signed-off-by: Vaishali Thakkar Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 6a4795433d57..855353bed19e 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -32,6 +32,39 @@ #define SMEM_HW_SW_BUILD_ID 137 #ifdef CONFIG_DEBUG_FS +#define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32 +#define SMEM_IMAGE_VERSION_SIZE 4096 +#define SMEM_IMAGE_VERSION_NAME_SIZE 75 +#define SMEM_IMAGE_VERSION_VARIANT_SIZE 20 +#define SMEM_IMAGE_VERSION_OEM_SIZE 32 + +/* + * SMEM Image table indices + */ +#define SMEM_IMAGE_TABLE_BOOT_INDEX 0 +#define SMEM_IMAGE_TABLE_TZ_INDEX 1 +#define SMEM_IMAGE_TABLE_RPM_INDEX 3 +#define SMEM_IMAGE_TABLE_APPS_INDEX 10 +#define SMEM_IMAGE_TABLE_MPSS_INDEX 11 +#define SMEM_IMAGE_TABLE_ADSP_INDEX 12 +#define SMEM_IMAGE_TABLE_CNSS_INDEX 13 +#define SMEM_IMAGE_TABLE_VIDEO_INDEX 14 +#define SMEM_IMAGE_VERSION_TABLE 469 + +/* + * SMEM Image table names + */ +static const char *const socinfo_image_names[] = { + [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp", + [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps", + [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot", + [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss", + [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss", + [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm", + [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz", + [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video", +}; + static const char *const pmic_models[] = { [0] = "Unknown PMIC model", [9] = "PM8994", @@ -103,6 +136,13 @@ struct socinfo_params { u32 hw_plat; u32 fmt; }; + +struct smem_image_version { + char name[SMEM_IMAGE_VERSION_NAME_SIZE]; + char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE]; + char pad; + char oem[SMEM_IMAGE_VERSION_OEM_SIZE]; +}; #endif /* CONFIG_DEBUG_FS */ struct qcom_socinfo { @@ -230,10 +270,37 @@ QCOM_OPEN(build_id, qcom_show_build_id); QCOM_OPEN(pmic_model, qcom_show_pmic_model); QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision); +#define DEFINE_IMAGE_OPS(type) \ +static int show_image_##type(struct seq_file *seq, void *p) \ +{ \ + struct smem_image_version *image_version = seq->private; \ + seq_puts(seq, image_version->type); \ + seq_puts(seq, "\n"); \ + return 0; \ +} \ +static int open_image_##type(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, show_image_##type, inode->i_private); \ +} \ + \ +static const struct file_operations qcom_image_##type##_ops = { \ + .open = open_image_##type, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} + +DEFINE_IMAGE_OPS(name); +DEFINE_IMAGE_OPS(variant); +DEFINE_IMAGE_OPS(oem); + static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, struct socinfo *info) { + struct smem_image_version *versions; + struct dentry *dentry; size_t size; + int i; qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL); @@ -302,6 +369,23 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, DEBUGFS_ADD(info, build_id); break; } + + versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE, + &size); + + for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) { + if (!socinfo_image_names[i]) + continue; + + dentry = debugfs_create_dir(socinfo_image_names[i], + qcom_socinfo->dbg_root); + debugfs_create_file("name", 0400, dentry, &versions[i], + &qcom_image_name_ops); + debugfs_create_file("variant", 0400, dentry, &versions[i], + &qcom_image_variant_ops); + debugfs_create_file("oem", 0400, dentry, &versions[i], + &qcom_image_oem_ops); + } } static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) -- cgit v1.2.3 From 05589b30b21ac0273970b61edd50c07d2ba156af Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Tue, 30 Jul 2019 11:24:42 -0400 Subject: soc: qcom: Extend AOSS QMP driver to support resources that are used to wake up the SoC. The AOSS QMP driver is extended to communicate with the additional resources. These resources are then registered as cooling devices with the thermal framework. Signed-off-by: Thara Gopinath Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 131 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 5f885196f4d0..443dab2207de 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include #define QMP_DESC_MAGIC 0x0 #define QMP_DESC_VERSION 0x4 @@ -40,6 +42,17 @@ /* 64 bytes is enough to store the requests and provides padding to 4 bytes */ #define QMP_MSG_LEN 64 +#define QMP_NUM_COOLING_RESOURCES 2 + +static bool qmp_cdev_init_state = 1; + +struct qmp_cooling_device { + struct thermal_cooling_device *cdev; + struct qmp *qmp; + char *name; + bool state; +}; + /** * struct qmp - driver state for QMP implementation * @msgram: iomem referencing the message RAM used for communication @@ -69,6 +82,7 @@ struct qmp { struct clk_hw qdss_clk; struct genpd_onecell_data pd_data; + struct qmp_cooling_device *cooling_devs; }; struct qmp_pd { @@ -385,6 +399,118 @@ static void qmp_pd_remove(struct qmp *qmp) pm_genpd_remove(data->domains[i]); } +static int qmp_cdev_get_max_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + *state = qmp_cdev_init_state; + return 0; +} + +static int qmp_cdev_get_cur_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + struct qmp_cooling_device *qmp_cdev = cdev->devdata; + + *state = qmp_cdev->state; + return 0; +} + +static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev, + unsigned long state) +{ + struct qmp_cooling_device *qmp_cdev = cdev->devdata; + char buf[QMP_MSG_LEN] = {}; + bool cdev_state; + int ret; + + /* Normalize state */ + cdev_state = !!state; + + if (qmp_cdev->state == state) + return 0; + + snprintf(buf, sizeof(buf), + "{class: volt_flr, event:zero_temp, res:%s, value:%s}", + qmp_cdev->name, + cdev_state ? "off" : "on"); + + ret = qmp_send(qmp_cdev->qmp, buf, sizeof(buf)); + + if (!ret) + qmp_cdev->state = cdev_state; + + return ret; +} + +static struct thermal_cooling_device_ops qmp_cooling_device_ops = { + .get_max_state = qmp_cdev_get_max_state, + .get_cur_state = qmp_cdev_get_cur_state, + .set_cur_state = qmp_cdev_set_cur_state, +}; + +static int qmp_cooling_device_add(struct qmp *qmp, + struct qmp_cooling_device *qmp_cdev, + struct device_node *node) +{ + char *cdev_name = (char *)node->name; + + qmp_cdev->qmp = qmp; + qmp_cdev->state = qmp_cdev_init_state; + qmp_cdev->name = cdev_name; + qmp_cdev->cdev = devm_thermal_of_cooling_device_register + (qmp->dev, node, + cdev_name, + qmp_cdev, &qmp_cooling_device_ops); + + if (IS_ERR(qmp_cdev->cdev)) + dev_err(qmp->dev, "unable to register %s cooling device\n", + cdev_name); + + return PTR_ERR_OR_ZERO(qmp_cdev->cdev); +} + +static int qmp_cooling_devices_register(struct qmp *qmp) +{ + struct device_node *np, *child; + int count = QMP_NUM_COOLING_RESOURCES; + int ret; + + np = qmp->dev->of_node; + + qmp->cooling_devs = devm_kcalloc(qmp->dev, count, + sizeof(*qmp->cooling_devs), + GFP_KERNEL); + + if (!qmp->cooling_devs) + return -ENOMEM; + + for_each_available_child_of_node(np, child) { + if (!of_find_property(child, "#cooling-cells", NULL)) + continue; + ret = qmp_cooling_device_add(qmp, &qmp->cooling_devs[count++], + child); + if (ret) + goto unroll; + } + + return 0; + +unroll: + while (--count >= 0) + thermal_cooling_device_unregister + (qmp->cooling_devs[count].cdev); + + return ret; +} + +static void qmp_cooling_devices_remove(struct qmp *qmp) +{ + int i; + + for (i = 0; i < QMP_NUM_COOLING_RESOURCES; i++) + thermal_cooling_device_unregister(qmp->cooling_devs[i].cdev); +} + static int qmp_probe(struct platform_device *pdev) { struct resource *res; @@ -433,6 +559,10 @@ static int qmp_probe(struct platform_device *pdev) if (ret) goto err_remove_qdss_clk; + ret = qmp_cooling_devices_register(qmp); + if (ret) + dev_err(&pdev->dev, "failed to register aoss cooling devices\n"); + platform_set_drvdata(pdev, qmp); return 0; @@ -453,6 +583,7 @@ static int qmp_remove(struct platform_device *pdev) qmp_qdss_clk_remove(qmp); qmp_pd_remove(qmp); + qmp_cooling_devices_remove(qmp); qmp_close(qmp); mbox_free_channel(qmp->mbox_chan); -- cgit v1.2.3 From 7bea41c4a25675a32bc3a63cfbd98099fdfb2695 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 6 Aug 2019 19:23:56 -0700 Subject: soc: qcom: socinfo: Annotate switch cases with fall through Introduce fall through annotations in the switch statements of socinfo_debugfs_init() to silence compiler warnings. Acked-by: Vaishali Thakkar Fixes: 9c84c1e78634 ("soc: qcom: socinfo: Expose custom attributes") Reported-by: Stephen Rothwell Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 855353bed19e..a39ea5061dc5 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -323,6 +323,7 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, debugfs_create_x32("raw_device_number", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.raw_device_num); + /* Fall through */ case SOCINFO_VERSION(0, 11): case SOCINFO_VERSION(0, 10): case SOCINFO_VERSION(0, 9): @@ -330,10 +331,12 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, debugfs_create_u32("foundry_id", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.foundry_id); + /* Fall through */ case SOCINFO_VERSION(0, 8): case SOCINFO_VERSION(0, 7): DEBUGFS_ADD(info, pmic_model); DEBUGFS_ADD(info, pmic_die_rev); + /* Fall through */ case SOCINFO_VERSION(0, 6): qcom_socinfo->info.hw_plat_subtype = __le32_to_cpu(info->hw_plat_subtype); @@ -341,6 +344,7 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, debugfs_create_u32("hardware_platform_subtype", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.hw_plat_subtype); + /* Fall through */ case SOCINFO_VERSION(0, 5): qcom_socinfo->info.accessory_chip = __le32_to_cpu(info->accessory_chip); @@ -348,23 +352,27 @@ static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo, debugfs_create_u32("accessory_chip", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.accessory_chip); + /* Fall through */ case SOCINFO_VERSION(0, 4): qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver); debugfs_create_u32("platform_version", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.plat_ver); + /* Fall through */ case SOCINFO_VERSION(0, 3): qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat); debugfs_create_u32("hardware_platform", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.hw_plat); + /* Fall through */ case SOCINFO_VERSION(0, 2): qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver); debugfs_create_u32("raw_version", 0400, qcom_socinfo->dbg_root, &qcom_socinfo->info.raw_ver); + /* Fall through */ case SOCINFO_VERSION(0, 1): DEBUGFS_ADD(info, build_id); break; -- cgit v1.2.3 From f117249e4b7831248404ff1fb47bfe44c355caea Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 7 Aug 2019 12:39:51 +0530 Subject: soc: qcom: smem: Update max processor count Update max processor count to reflect the number of co-processors on SC7180 SoCs. Reviewed-by: Vinod Koul Tested-by: Vinod Koul Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 0caf67e2f037..28c19bcb2f20 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -84,7 +84,7 @@ #define SMEM_GLOBAL_HOST 0xfffe /* Max number of processors/hosts in a system */ -#define SMEM_HOST_COUNT 10 +#define SMEM_HOST_COUNT 11 /** * struct smem_proc_comm - proc_comm communication struct (legacy) -- cgit v1.2.3 From 1709510221c57fd566479c228434ff9edd6435be Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Wed, 7 Aug 2019 12:39:57 +0530 Subject: soc: qcom: aoss: Add AOSS QMP support Add AOSS QMP support for SM8150 and SC7180 SoCs. Reviewed-by: Vinod Koul Tested-by: Vinod Koul Signed-off-by: Sibi Sankar Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/soc/qcom') diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 443dab2207de..33a27e6c6d67 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -592,7 +592,9 @@ static int qmp_remove(struct platform_device *pdev) } static const struct of_device_id qmp_dt_match[] = { + { .compatible = "qcom,sc7180-aoss-qmp", }, { .compatible = "qcom,sdm845-aoss-qmp", }, + { .compatible = "qcom,sm8150-aoss-qmp", }, {} }; MODULE_DEVICE_TABLE(of, qmp_dt_match); -- cgit v1.2.3