From 1034023606d0e971f4dee6f725e441b785a846b5 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:25:46 -0500 Subject: PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() Rename dw_pcie_valid_config() to dw_pcie_valid_device() and use the result directly as a boolean value instead of testing against 0. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 74da71ea544a..b58f078f480a 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -760,8 +760,8 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, return ret; } -static int dw_pcie_valid_config(struct pcie_port *pp, - struct pci_bus *bus, int dev) +static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, + int dev) { /* If there is no link, then there is no device */ if (bus->number != pp->root_bus_nr) { @@ -781,7 +781,7 @@ static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, { struct pcie_port *pp = bus->sysdata; - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { + if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) { *val = 0xffffffff; return PCIBIOS_DEVICE_NOT_FOUND; } @@ -797,7 +797,7 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, { struct pcie_port *pp = bus->sysdata; - if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) + if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) return PCIBIOS_DEVICE_NOT_FOUND; if (bus->number == pp->root_bus_nr) -- cgit v1.2.3 From a26e0108b61d6e65c151af720f2c4248a38f000d Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Tue, 11 Oct 2016 08:26:21 -0500 Subject: PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() dw_pcie_readl_unroll() and dw_pcie_writel_unroll() duplicate what dw_pcie_readl_rc() and dw_pcie_writel_rc() already do, so call them directly. [bhelgaas: reworked into patch series] Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index b58f078f480a..7ce4f7510bb5 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -161,10 +161,7 @@ static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - if (pp->ops->readl_rc) - return pp->ops->readl_rc(pp, pp->dbi_base + offset + reg); - - return readl(pp->dbi_base + offset + reg); + return dw_pcie_readl_rc(pp, offset + reg); } static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, @@ -172,10 +169,7 @@ static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, pp->dbi_base + offset + reg); - else - writel(val, pp->dbi_base + offset + reg); + dw_pcie_writel_rc(pp, val, offset + reg); } static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, -- cgit v1.2.3 From 7e00dfd0fbbb2fc276592613f76ded0b9a139a04 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:25:46 -0500 Subject: PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers allow a driver to override the default DesignWare register accessors. Make the signature of the override functions the same as the default accessors. This makes the default dw_pcie_readl_rc() and the corresponding override more structurally similar: both will compute the final register address with "pp->dbi_base + reg". Previously dw_pcie_readl_rc() computed the address and passed it to the override. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-exynos.c | 10 ++++------ drivers/pci/host/pcie-designware.c | 4 ++-- drivers/pci/host/pcie-designware.h | 5 ++--- 3 files changed, 8 insertions(+), 11 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 2e2d7f00b9e8..b29e9d64d41b 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -425,22 +425,20 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp) exynos_pcie_msi_init(pp); } -static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, - void __iomem *dbi_base) +static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) { u32 val; exynos_pcie_sideband_dbi_r_mode(pp, true); - val = readl(dbi_base); + val = readl(pp->dbi_base + reg); exynos_pcie_sideband_dbi_r_mode(pp, false); return val; } -static inline void exynos_pcie_writel_rc(struct pcie_port *pp, - u32 val, void __iomem *dbi_base) +static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) { exynos_pcie_sideband_dbi_w_mode(pp, true); - writel(val, dbi_base); + writel(val, pp->dbi_base + reg); exynos_pcie_sideband_dbi_w_mode(pp, false); } diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 7ce4f7510bb5..6a28eb1e2ef9 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -144,7 +144,7 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) { if (pp->ops->readl_rc) - return pp->ops->readl_rc(pp, pp->dbi_base + reg); + return pp->ops->readl_rc(pp, reg); return readl(pp->dbi_base + reg); } @@ -152,7 +152,7 @@ static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) { if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, pp->dbi_base + reg); + pp->ops->writel_rc(pp, val, reg); else writel(val, pp->dbi_base + reg); } diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index c8e5bc647f49..60cbc682618f 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -54,9 +54,8 @@ struct pcie_port { }; struct pcie_host_ops { - u32 (*readl_rc)(struct pcie_port *pp, void __iomem *dbi_base); - void (*writel_rc)(struct pcie_port *pp, - u32 val, void __iomem *dbi_base); + u32 (*readl_rc)(struct pcie_port *pp, u32 reg); + void (*writel_rc)(struct pcie_port *pp, u32 val, u32 reg); int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, -- cgit v1.2.3 From ad8802189426cf7b3a2ad0444f71981fb81312a8 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:25:46 -0500 Subject: PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments Swap order of dw_pcie_writel_rc() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-exynos.c | 2 +- drivers/pci/host/pcie-designware.c | 48 +++++++++++++++++++------------------- drivers/pci/host/pcie-designware.h | 2 +- 3 files changed, 26 insertions(+), 26 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index b29e9d64d41b..f559b494f300 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c @@ -435,7 +435,7 @@ static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg) return val; } -static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) +static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) { exynos_pcie_sideband_dbi_w_mode(pp, true); writel(val, pp->dbi_base + reg); diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 6a28eb1e2ef9..f91c7b305ca2 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -149,10 +149,10 @@ static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) return readl(pp->dbi_base + reg); } -static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) +static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) { if (pp->ops->writel_rc) - pp->ops->writel_rc(pp, val, reg); + pp->ops->writel_rc(pp, reg, val); else writel(val, pp->dbi_base + reg); } @@ -169,7 +169,7 @@ static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); - dw_pcie_writel_rc(pp, val, offset + reg); + dw_pcie_writel_rc(pp, offset + reg, val); } static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, @@ -211,20 +211,20 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, dw_pcie_writel_unroll(pp, index, PCIE_ATU_ENABLE, PCIE_ATU_UNR_REGION_CTRL2); } else { - dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, - PCIE_ATU_VIEWPORT); - dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), - PCIE_ATU_LOWER_BASE); - dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), - PCIE_ATU_UPPER_BASE); - dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), - PCIE_ATU_LIMIT); - dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), - PCIE_ATU_LOWER_TARGET); - dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), - PCIE_ATU_UPPER_TARGET); - dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); + dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, + PCIE_ATU_REGION_OUTBOUND | index); + dw_pcie_writel_rc(pp, PCIE_ATU_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_rc(pp, PCIE_ATU_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_rc(pp, PCIE_ATU_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_rc(pp, PCIE_ATU_LOWER_TARGET, + lower_32_bits(pci_addr)); + dw_pcie_writel_rc(pp, PCIE_ATU_UPPER_TARGET, + upper_32_bits(pci_addr)); + dw_pcie_writel_rc(pp, PCIE_ATU_CR1, type); + dw_pcie_writel_rc(pp, PCIE_ATU_CR2, PCIE_ATU_ENABLE); } /* @@ -829,7 +829,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); return; } - dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); + dw_pcie_writel_rc(pp, PCIE_PORT_LINK_CONTROL, val); /* set link width speed control register */ val = dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL); @@ -848,30 +848,30 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val |= PORT_LOGIC_LINK_WIDTH_8_LANES; break; } - dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); + dw_pcie_writel_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, val); /* setup RC BARs */ - dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); - dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_0, 0x00000004); + dw_pcie_writel_rc(pp, PCI_BASE_ADDRESS_1, 0x00000000); /* setup interrupt pins */ val = dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE); val &= 0xffff00ff; val |= 0x00000100; - dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); + dw_pcie_writel_rc(pp, PCI_INTERRUPT_LINE, val); /* setup bus numbers */ val = dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS); val &= 0xff000000; val |= 0x00010100; - dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); + dw_pcie_writel_rc(pp, PCI_PRIMARY_BUS, val); /* setup command register */ val = dw_pcie_readl_rc(pp, PCI_COMMAND); val &= 0xffff0000; val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - dw_pcie_writel_rc(pp, val, PCI_COMMAND); + dw_pcie_writel_rc(pp, PCI_COMMAND, val); /* * If the platform provides ->rd_other_conf, it means the platform diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 60cbc682618f..c41384832766 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -55,7 +55,7 @@ struct pcie_port { struct pcie_host_ops { u32 (*readl_rc)(struct pcie_port *pp, u32 reg); - void (*writel_rc)(struct pcie_port *pp, u32 val, u32 reg); + void (*writel_rc)(struct pcie_port *pp, u32 reg, u32 val); int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, -- cgit v1.2.3 From 8ad750193430668d1d833dbee94788533b417b9a Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:25:47 -0500 Subject: PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() Export dw_pcie_readl_rc() and dw_pcie_writel_rc(). Many other drivers can use these instead of implementing their own versions. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware.c | 4 ++-- drivers/pci/host/pcie-designware.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index f91c7b305ca2..b8feea41e1e7 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -141,7 +141,7 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) return PCIBIOS_SUCCESSFUL; } -static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) +u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) { if (pp->ops->readl_rc) return pp->ops->readl_rc(pp, reg); @@ -149,7 +149,7 @@ static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) return readl(pp->dbi_base + reg); } -static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) +void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) { if (pp->ops->writel_rc) pp->ops->writel_rc(pp, reg, val); diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index c41384832766..a567ea288ee2 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -72,6 +72,8 @@ struct pcie_host_ops { int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip); }; +u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg); +void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val); int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); -- cgit v1.2.3 From 3d469939bcdf044d9f370be4f6bf21436afea310 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 11 Oct 2016 08:33:33 -0500 Subject: PCI: designware: Uninline register accessors The register accessors are not performance critical and small enough that the compiler can inline them itself if it makes sense. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index b8feea41e1e7..7a3458dcf7b9 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -157,14 +157,14 @@ void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val) writel(val, pp->dbi_base + reg); } -static inline u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) +static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); return dw_pcie_readl_rc(pp, offset + reg); } -static inline void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, +static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, u32 val, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); -- cgit v1.2.3 From f5acb5c51de2c073ee5f80d868354113ce0227ee Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 11 Oct 2016 08:33:00 -0500 Subject: PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 7a3458dcf7b9..035f50c03281 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -164,8 +164,8 @@ static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg) return dw_pcie_readl_rc(pp, offset + reg); } -static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, - u32 val, u32 reg) +static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, u32 reg, + u32 val) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); @@ -196,20 +196,20 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, u32 retries, val; if (pp->iatu_unroll_enabled) { - dw_pcie_writel_unroll(pp, index, - lower_32_bits(cpu_addr), PCIE_ATU_UNR_LOWER_BASE); - dw_pcie_writel_unroll(pp, index, - upper_32_bits(cpu_addr), PCIE_ATU_UNR_UPPER_BASE); - dw_pcie_writel_unroll(pp, index, - lower_32_bits(cpu_addr + size - 1), PCIE_ATU_UNR_LIMIT); - dw_pcie_writel_unroll(pp, index, - lower_32_bits(pci_addr), PCIE_ATU_UNR_LOWER_TARGET); - dw_pcie_writel_unroll(pp, index, - upper_32_bits(pci_addr), PCIE_ATU_UNR_UPPER_TARGET); - dw_pcie_writel_unroll(pp, index, - type, PCIE_ATU_UNR_REGION_CTRL1); - dw_pcie_writel_unroll(pp, index, - PCIE_ATU_ENABLE, PCIE_ATU_UNR_REGION_CTRL2); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE, + lower_32_bits(cpu_addr)); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_BASE, + upper_32_bits(cpu_addr)); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LIMIT, + lower_32_bits(cpu_addr + size - 1)); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_TARGET, + lower_32_bits(pci_addr)); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_TARGET, + upper_32_bits(pci_addr)); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL1, + type); + dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL2, + PCIE_ATU_ENABLE); } else { dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index); -- cgit v1.2.3 From bb8a79477738ee038c9cfd471e8ab60da1e37177 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:32:15 -0500 Subject: PCI: designware-plat: Remove redundant dw_plat_pcie.mem_base Remove the struct dw_plat_pcie.mem_base member, which is only used as a temporary. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware-plat.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c index 17da005497a5..d9d01e7879c9 100644 --- a/drivers/pci/host/pcie-designware-plat.c +++ b/drivers/pci/host/pcie-designware-plat.c @@ -25,8 +25,7 @@ #include "pcie-designware.h" struct dw_plat_pcie { - void __iomem *mem_base; - struct pcie_port pp; + struct pcie_port pp; /* pp.dbi_base is DT 0th resource */ }; static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg) @@ -100,11 +99,9 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) pp->dev = &pdev->dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - dw_plat_pcie->mem_base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(dw_plat_pcie->mem_base)) - return PTR_ERR(dw_plat_pcie->mem_base); - - pp->dbi_base = dw_plat_pcie->mem_base; + pp->dbi_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pp->dbi_base)) + return PTR_ERR(pp->dbi_base); ret = dw_plat_add_pcie_port(pp, pdev); if (ret < 0) -- cgit v1.2.3 From 2d6054b968d4dc5a739f96cb60f7e7b410a0e2fb Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:32:15 -0500 Subject: PCI: designware-plat: Add local struct device pointers Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware-plat.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c index d9d01e7879c9..f0a2a60fbb6d 100644 --- a/drivers/pci/host/pcie-designware-plat.c +++ b/drivers/pci/host/pcie-designware-plat.c @@ -51,6 +51,7 @@ static struct pcie_host_ops dw_plat_pcie_host_ops = { static int dw_plat_add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) { + struct device *dev = pp->dev; int ret; pp->irq = platform_get_irq(pdev, 1); @@ -62,11 +63,11 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, if (pp->msi_irq < 0) return pp->msi_irq; - ret = devm_request_irq(&pdev->dev, pp->msi_irq, + ret = devm_request_irq(dev, pp->msi_irq, dw_plat_pcie_msi_irq_handler, IRQF_SHARED, "dw-plat-pcie-msi", pp); if (ret) { - dev_err(&pdev->dev, "failed to request MSI IRQ\n"); + dev_err(dev, "failed to request MSI IRQ\n"); return ret; } } @@ -76,7 +77,7 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, ret = dw_pcie_host_init(pp); if (ret) { - dev_err(&pdev->dev, "failed to initialize host\n"); + dev_err(dev, "failed to initialize host\n"); return ret; } @@ -85,21 +86,21 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp, static int dw_plat_pcie_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct dw_plat_pcie *dw_plat_pcie; struct pcie_port *pp; struct resource *res; /* Resource from DT */ int ret; - dw_plat_pcie = devm_kzalloc(&pdev->dev, sizeof(*dw_plat_pcie), - GFP_KERNEL); + dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL); if (!dw_plat_pcie) return -ENOMEM; pp = &dw_plat_pcie->pp; - pp->dev = &pdev->dev; + pp->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pp->dbi_base = devm_ioremap_resource(&pdev->dev, res); + pp->dbi_base = devm_ioremap_resource(dev, res); if (IS_ERR(pp->dbi_base)) return PTR_ERR(pp->dbi_base); -- cgit v1.2.3 From 4c9441d1e64c0ce224771d0985fabd75690a6d53 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 6 Oct 2016 13:32:15 -0500 Subject: PCI: designware-plat: Remove unused platform data The designware-plat driver never uses the platform drvdata pointer, so don't bother setting it. No functional change intended. Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pcie-designware-plat.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/pci') diff --git a/drivers/pci/host/pcie-designware-plat.c b/drivers/pci/host/pcie-designware-plat.c index f0a2a60fbb6d..537f58a664fa 100644 --- a/drivers/pci/host/pcie-designware-plat.c +++ b/drivers/pci/host/pcie-designware-plat.c @@ -108,7 +108,6 @@ static int dw_plat_pcie_probe(struct platform_device *pdev) if (ret < 0) return ret; - platform_set_drvdata(pdev, dw_plat_pcie); return 0; } -- cgit v1.2.3