From 7c3a95a15ad2a5278498a72df0463131048926a3 Mon Sep 17 00:00:00 2001 From: Christian Riesch Date: Wed, 22 Feb 2012 22:07:58 +0000 Subject: davinci_mdio: Correct bitmask for clock divider value The CLKDIV bitfield in the MDIO Control Register is a 16 bit field, therefore the CLKDIV value may range from 0 to 0xffff. Signed-off-by: Christian Riesch Signed-off-by: David S. Miller --- drivers/net/ethernet/ti/davinci_mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/net/ethernet/ti/davinci_mdio.c') diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c index af8b8fc39eb2..2757c7d6e633 100644 --- a/drivers/net/ethernet/ti/davinci_mdio.c +++ b/drivers/net/ethernet/ti/davinci_mdio.c @@ -53,7 +53,7 @@ struct davinci_mdio_regs { u32 control; #define CONTROL_IDLE BIT(31) #define CONTROL_ENABLE BIT(30) -#define CONTROL_MAX_DIV (0xff) +#define CONTROL_MAX_DIV (0xffff) u32 alive; u32 link; -- cgit v1.2.3