From 017d6250ad719d3ddab9070446db1e9fd4ba4a65 Mon Sep 17 00:00:00 2001 From: Voon Weifeng Date: Tue, 6 Apr 2021 09:32:50 +0800 Subject: stmmac: intel: Enable SERDES PHY rx clk for PSE EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up sequence and vice versa. Signed-off-by: Voon Weifeng Signed-off-by: David S. Miller --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h') diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index e723096c0b15..542acb8ce467 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -14,6 +14,7 @@ /* SERDES defines */ #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ #define SERDES_RST BIT(2) /* Serdes Reset */ #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ #define SERDES_PWR_ST_SHIFT 4 -- cgit v1.2.3