From a1867f85e06edacd82956d3422caa2b9074f4321 Mon Sep 17 00:00:00 2001 From: Min Li Date: Fri, 18 Jun 2021 12:37:12 -0400 Subject: mfd: Add Renesas Synchronization Management Unit (SMU) support Add support for ClockMatrix(TM) and 82P33xxx families of timing and synchronization devices. The access interface can be either SPI or I2C. Currently, it will create 2 types of MFD devices, which are to be used by the corresponding rsmu character device driver and the PTP hardware clock driver, respectively. Signed-off-by: Min Li Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 28 +++++ drivers/mfd/Makefile | 5 + drivers/mfd/rsmu.h | 16 +++ drivers/mfd/rsmu_core.c | 88 ++++++++++++++++ drivers/mfd/rsmu_i2c.c | 203 +++++++++++++++++++++++++++++++++++ drivers/mfd/rsmu_spi.c | 273 ++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 613 insertions(+) create mode 100644 drivers/mfd/rsmu.h create mode 100644 drivers/mfd/rsmu_core.c create mode 100644 drivers/mfd/rsmu_i2c.c create mode 100644 drivers/mfd/rsmu_spi.c (limited to 'drivers/mfd') diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6a3fd2d75f96..578db280dedf 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2183,5 +2183,33 @@ config MFD_INTEL_M10_BMC additional drivers must be enabled in order to use the functionality of the device. +config MFD_RSMU_I2C + tristate "Renesas Synchronization Management Unit with I2C" + depends on I2C && OF + select MFD_CORE + select REGMAP_I2C + help + Support for the Renesas Synchronization Management Unit, such as + Clockmatrix and 82P33XXX series. This option supports I2C as + the control interface. + + This driver provides common support for accessing the device. + Additional drivers must be enabled in order to use the functionality + of the device. + +config MFD_RSMU_SPI + tristate "Renesas Synchronization Management Unit with SPI" + depends on SPI && OF + select MFD_CORE + select REGMAP_SPI + help + Support for the Renesas Synchronization Management Unit, such as + Clockmatrix and 82P33XXX series. This option supports SPI as + the control interface. + + This driver provides common support for accessing the device. + Additional drivers must be enabled in order to use the functionality + of the device. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 8116c19d5fd4..54e37704f74b 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -272,3 +272,8 @@ obj-$(CONFIG_MFD_INTEL_M10_BMC) += intel-m10-bmc.o obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o + +rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o +rsmu-spi-objs := rsmu_core.o rsmu_spi.o +obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o +obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o diff --git a/drivers/mfd/rsmu.h b/drivers/mfd/rsmu.h new file mode 100644 index 000000000000..bb88597d189f --- /dev/null +++ b/drivers/mfd/rsmu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Renesas Synchronization Management Unit (SMU) devices. + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ + +#ifndef __RSMU_MFD_H +#define __RSMU_MFD_H + +#include + +int rsmu_core_init(struct rsmu_ddata *rsmu); +void rsmu_core_exit(struct rsmu_ddata *rsmu); + +#endif /* __RSMU_MFD_H */ diff --git a/drivers/mfd/rsmu_core.c b/drivers/mfd/rsmu_core.c new file mode 100644 index 000000000000..29437fd0bd5b --- /dev/null +++ b/drivers/mfd/rsmu_core.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Core driver for Renesas Synchronization Management Unit (SMU) devices. + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rsmu.h" + +enum { + RSMU_PHC = 0, + RSMU_CDEV = 1, + RSMU_N_DEVS = 2, +}; + +static struct mfd_cell rsmu_cm_devs[] = { + [RSMU_PHC] = { + .name = "8a3400x-phc", + }, + [RSMU_CDEV] = { + .name = "8a3400x-cdev", + }, +}; + +static struct mfd_cell rsmu_sabre_devs[] = { + [RSMU_PHC] = { + .name = "82p33x1x-phc", + }, + [RSMU_CDEV] = { + .name = "82p33x1x-cdev", + }, +}; + +static struct mfd_cell rsmu_sl_devs[] = { + [RSMU_PHC] = { + .name = "8v19n85x-phc", + }, + [RSMU_CDEV] = { + .name = "8v19n85x-cdev", + }, +}; + +int rsmu_core_init(struct rsmu_ddata *rsmu) +{ + struct mfd_cell *cells; + int ret; + + switch (rsmu->type) { + case RSMU_CM: + cells = rsmu_cm_devs; + break; + case RSMU_SABRE: + cells = rsmu_sabre_devs; + break; + case RSMU_SL: + cells = rsmu_sl_devs; + break; + default: + dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type); + return -ENODEV; + } + + mutex_init(&rsmu->lock); + + ret = devm_mfd_add_devices(rsmu->dev, PLATFORM_DEVID_AUTO, cells, + RSMU_N_DEVS, NULL, 0, NULL); + if (ret < 0) + dev_err(rsmu->dev, "Failed to register sub-devices: %d\n", ret); + + return ret; +} + +void rsmu_core_exit(struct rsmu_ddata *rsmu) +{ + mutex_destroy(&rsmu->lock); +} + +MODULE_DESCRIPTION("Renesas SMU core driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/rsmu_i2c.c b/drivers/mfd/rsmu_i2c.c new file mode 100644 index 000000000000..dc001c9791c1 --- /dev/null +++ b/drivers/mfd/rsmu_i2c.c @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * I2C driver for Renesas Synchronization Management Unit (SMU) devices. + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rsmu.h" + +/* + * 16-bit register address: the lower 8 bits of the register address come + * from the offset addr byte and the upper 8 bits come from the page register. + */ +#define RSMU_CM_PAGE_ADDR 0xFD +#define RSMU_CM_PAGE_WINDOW 256 + +/* + * 15-bit register address: the lower 7 bits of the register address come + * from the offset addr byte and the upper 8 bits come from the page register. + */ +#define RSMU_SABRE_PAGE_ADDR 0x7F +#define RSMU_SABRE_PAGE_WINDOW 128 + +static const struct regmap_range_cfg rsmu_cm_range_cfg[] = { + { + .range_min = 0, + .range_max = 0xD000, + .selector_reg = RSMU_CM_PAGE_ADDR, + .selector_mask = 0xFF, + .selector_shift = 0, + .window_start = 0, + .window_len = RSMU_CM_PAGE_WINDOW, + } +}; + +static const struct regmap_range_cfg rsmu_sabre_range_cfg[] = { + { + .range_min = 0, + .range_max = 0x400, + .selector_reg = RSMU_SABRE_PAGE_ADDR, + .selector_mask = 0xFF, + .selector_shift = 0, + .window_start = 0, + .window_len = RSMU_SABRE_PAGE_WINDOW, + } +}; + +static bool rsmu_cm_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RSMU_CM_PAGE_ADDR: + return false; + default: + return true; + } +} + +static bool rsmu_sabre_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RSMU_SABRE_PAGE_ADDR: + return false; + default: + return true; + } +} + +static const struct regmap_config rsmu_cm_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xD000, + .ranges = rsmu_cm_range_cfg, + .num_ranges = ARRAY_SIZE(rsmu_cm_range_cfg), + .volatile_reg = rsmu_cm_volatile_reg, + .cache_type = REGCACHE_RBTREE, + .can_multi_write = true, +}; + +static const struct regmap_config rsmu_sabre_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0x400, + .ranges = rsmu_sabre_range_cfg, + .num_ranges = ARRAY_SIZE(rsmu_sabre_range_cfg), + .volatile_reg = rsmu_sabre_volatile_reg, + .cache_type = REGCACHE_RBTREE, + .can_multi_write = true, +}; + +static const struct regmap_config rsmu_sl_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .max_register = 0x339, + .cache_type = REGCACHE_NONE, + .can_multi_write = true, +}; + +static int rsmu_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + const struct regmap_config *cfg; + struct rsmu_ddata *rsmu; + int ret; + + rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL); + if (!rsmu) + return -ENOMEM; + + i2c_set_clientdata(client, rsmu); + + rsmu->dev = &client->dev; + rsmu->type = (enum rsmu_type)id->driver_data; + + switch (rsmu->type) { + case RSMU_CM: + cfg = &rsmu_cm_regmap_config; + break; + case RSMU_SABRE: + cfg = &rsmu_sabre_regmap_config; + break; + case RSMU_SL: + cfg = &rsmu_sl_regmap_config; + break; + default: + dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type); + return -ENODEV; + } + rsmu->regmap = devm_regmap_init_i2c(client, cfg); + if (IS_ERR(rsmu->regmap)) { + ret = PTR_ERR(rsmu->regmap); + dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret); + return ret; + } + + return rsmu_core_init(rsmu); +} + +static int rsmu_i2c_remove(struct i2c_client *client) +{ + struct rsmu_ddata *rsmu = i2c_get_clientdata(client); + + rsmu_core_exit(rsmu); + + return 0; +} + +static const struct i2c_device_id rsmu_i2c_id[] = { + { "8a34000", RSMU_CM }, + { "8a34001", RSMU_CM }, + { "82p33810", RSMU_SABRE }, + { "82p33811", RSMU_SABRE }, + { "8v19n850", RSMU_SL }, + { "8v19n851", RSMU_SL }, + {} +}; +MODULE_DEVICE_TABLE(i2c, rsmu_i2c_id); + +static const struct of_device_id rsmu_i2c_of_match[] = { + { .compatible = "idt,8a34000", .data = (void *)RSMU_CM }, + { .compatible = "idt,8a34001", .data = (void *)RSMU_CM }, + { .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE }, + { .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE }, + { .compatible = "idt,8v19n850", .data = (void *)RSMU_SL }, + { .compatible = "idt,8v19n851", .data = (void *)RSMU_SL }, + {} +}; +MODULE_DEVICE_TABLE(of, rsmu_i2c_of_match); + +static struct i2c_driver rsmu_i2c_driver = { + .driver = { + .name = "rsmu-i2c", + .of_match_table = of_match_ptr(rsmu_i2c_of_match), + }, + .probe = rsmu_i2c_probe, + .remove = rsmu_i2c_remove, + .id_table = rsmu_i2c_id, +}; + +static int __init rsmu_i2c_init(void) +{ + return i2c_add_driver(&rsmu_i2c_driver); +} +subsys_initcall(rsmu_i2c_init); + +static void __exit rsmu_i2c_exit(void) +{ + i2c_del_driver(&rsmu_i2c_driver); +} +module_exit(rsmu_i2c_exit); + +MODULE_DESCRIPTION("Renesas SMU I2C driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mfd/rsmu_spi.c b/drivers/mfd/rsmu_spi.c new file mode 100644 index 000000000000..fec2b4ec477c --- /dev/null +++ b/drivers/mfd/rsmu_spi.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * SPI driver for Renesas Synchronization Management Unit (SMU) devices. + * + * Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rsmu.h" + +#define RSMU_CM_PAGE_ADDR 0x7C +#define RSMU_SABRE_PAGE_ADDR 0x7F +#define RSMU_HIGHER_ADDR_MASK 0xFF80 +#define RSMU_HIGHER_ADDR_SHIFT 7 +#define RSMU_LOWER_ADDR_MASK 0x7F + +static int rsmu_read_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes) +{ + struct spi_device *client = to_spi_device(rsmu->dev); + struct spi_transfer xfer = {0}; + struct spi_message msg; + u8 cmd[256] = {0}; + u8 rsp[256] = {0}; + int ret; + + cmd[0] = reg | 0x80; + xfer.rx_buf = rsp; + xfer.len = bytes + 1; + xfer.tx_buf = cmd; + xfer.bits_per_word = client->bits_per_word; + xfer.speed_hz = client->max_speed_hz; + + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + + /* + * 4-wire SPI is a shift register, so for every byte you send, + * you get one back at the same time. Example read from 0xC024, + * which has value of 0x2D + * + * MOSI: + * 7C 00 C0 #Set page register + * A4 00 #MSB is set, so this is read command + * MISO: + * XX 2D #XX is a dummy byte from sending A4 and we + * need to throw it away + */ + ret = spi_sync(client, &msg); + if (ret >= 0) + memcpy(buf, &rsp[1], xfer.len-1); + + return ret; +} + +static int rsmu_write_device(struct rsmu_ddata *rsmu, u8 reg, u8 *buf, u16 bytes) +{ + struct spi_device *client = to_spi_device(rsmu->dev); + struct spi_transfer xfer = {0}; + struct spi_message msg; + u8 cmd[256] = {0}; + + cmd[0] = reg; + memcpy(&cmd[1], buf, bytes); + + xfer.len = bytes + 1; + xfer.tx_buf = cmd; + xfer.bits_per_word = client->bits_per_word; + xfer.speed_hz = client->max_speed_hz; + spi_message_init(&msg); + spi_message_add_tail(&xfer, &msg); + + return spi_sync(client, &msg); +} + +/* + * 1-byte (1B) offset addressing: + * 16-bit register address: the lower 7 bits of the register address come + * from the offset addr byte and the upper 9 bits come from the page register. + */ +static int rsmu_write_page_register(struct rsmu_ddata *rsmu, u16 reg) +{ + u8 page_reg; + u8 buf[2]; + u16 bytes; + u16 page; + int err; + + switch (rsmu->type) { + case RSMU_CM: + page_reg = RSMU_CM_PAGE_ADDR; + page = reg & RSMU_HIGHER_ADDR_MASK; + buf[0] = (u8)(page & 0xff); + buf[1] = (u8)((page >> 8) & 0xff); + bytes = 2; + break; + case RSMU_SABRE: + page_reg = RSMU_SABRE_PAGE_ADDR; + page = reg >> RSMU_HIGHER_ADDR_SHIFT; + buf[0] = (u8)(page & 0xff); + bytes = 1; + break; + default: + dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type); + return -ENODEV; + } + + /* Simply return if we are on the same page */ + if (rsmu->page == page) + return 0; + + err = rsmu_write_device(rsmu, page_reg, buf, bytes); + if (err) + dev_err(rsmu->dev, "Failed to set page offset 0x%x\n", page); + else + /* Remember the last page */ + rsmu->page = page; + + return err; +} + +static int rsmu_reg_read(void *context, unsigned int reg, unsigned int *val) +{ + struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context); + u8 addr = (u8)(reg & RSMU_LOWER_ADDR_MASK); + int err; + + err = rsmu_write_page_register(rsmu, reg); + if (err) + return err; + + err = rsmu_read_device(rsmu, addr, (u8 *)val, 1); + if (err) + dev_err(rsmu->dev, "Failed to read offset address 0x%x\n", addr); + + return err; +} + +static int rsmu_reg_write(void *context, unsigned int reg, unsigned int val) +{ + struct rsmu_ddata *rsmu = spi_get_drvdata((struct spi_device *)context); + u8 addr = (u8)(reg & RSMU_LOWER_ADDR_MASK); + u8 data = (u8)val; + int err; + + err = rsmu_write_page_register(rsmu, reg); + if (err) + return err; + + err = rsmu_write_device(rsmu, addr, &data, 1); + if (err) + dev_err(rsmu->dev, + "Failed to write offset address 0x%x\n", addr); + + return err; +} + +static const struct regmap_config rsmu_cm_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0xD000, + .reg_read = rsmu_reg_read, + .reg_write = rsmu_reg_write, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_config rsmu_sabre_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .max_register = 0x400, + .reg_read = rsmu_reg_read, + .reg_write = rsmu_reg_write, + .cache_type = REGCACHE_NONE, +}; + +static int rsmu_spi_probe(struct spi_device *client) +{ + const struct spi_device_id *id = spi_get_device_id(client); + const struct regmap_config *cfg; + struct rsmu_ddata *rsmu; + int ret; + + rsmu = devm_kzalloc(&client->dev, sizeof(*rsmu), GFP_KERNEL); + if (!rsmu) + return -ENOMEM; + + spi_set_drvdata(client, rsmu); + + rsmu->dev = &client->dev; + rsmu->type = (enum rsmu_type)id->driver_data; + + /* Initialize regmap */ + switch (rsmu->type) { + case RSMU_CM: + cfg = &rsmu_cm_regmap_config; + break; + case RSMU_SABRE: + cfg = &rsmu_sabre_regmap_config; + break; + default: + dev_err(rsmu->dev, "Unsupported RSMU device type: %d\n", rsmu->type); + return -ENODEV; + } + + rsmu->regmap = devm_regmap_init(&client->dev, NULL, client, cfg); + if (IS_ERR(rsmu->regmap)) { + ret = PTR_ERR(rsmu->regmap); + dev_err(rsmu->dev, "Failed to allocate register map: %d\n", ret); + return ret; + } + + return rsmu_core_init(rsmu); +} + +static int rsmu_spi_remove(struct spi_device *client) +{ + struct rsmu_ddata *rsmu = spi_get_drvdata(client); + + rsmu_core_exit(rsmu); + + return 0; +} + +static const struct spi_device_id rsmu_spi_id[] = { + { "8a34000", RSMU_CM }, + { "8a34001", RSMU_CM }, + { "82p33810", RSMU_SABRE }, + { "82p33811", RSMU_SABRE }, + {} +}; +MODULE_DEVICE_TABLE(spi, rsmu_spi_id); + +static const struct of_device_id rsmu_spi_of_match[] = { + { .compatible = "idt,8a34000", .data = (void *)RSMU_CM }, + { .compatible = "idt,8a34001", .data = (void *)RSMU_CM }, + { .compatible = "idt,82p33810", .data = (void *)RSMU_SABRE }, + { .compatible = "idt,82p33811", .data = (void *)RSMU_SABRE }, + {} +}; +MODULE_DEVICE_TABLE(of, rsmu_spi_of_match); + +static struct spi_driver rsmu_spi_driver = { + .driver = { + .name = "rsmu-spi", + .of_match_table = of_match_ptr(rsmu_spi_of_match), + }, + .probe = rsmu_spi_probe, + .remove = rsmu_spi_remove, + .id_table = rsmu_spi_id, +}; + +static int __init rsmu_spi_init(void) +{ + return spi_register_driver(&rsmu_spi_driver); +} +subsys_initcall(rsmu_spi_init); + +static void __exit rsmu_spi_exit(void) +{ + spi_unregister_driver(&rsmu_spi_driver); +} +module_exit(rsmu_spi_exit); + +MODULE_DESCRIPTION("Renesas SMU SPI driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From f949a9ebce7a18005266b859a17f10c891bb13d7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 29 Jun 2021 19:12:39 +0200 Subject: mfd: axp20x: Update AXP288 volatile ranges On Cherry Trail devices with an AXP288 PMIC the external SD-card slot used the AXP's DLDO2 as card-voltage and either DLDO3 or GPIO1LDO (GPIO1 pin in low noise LDO mode) as signal-voltage. These regulators are turned on/off and in case of the signal-voltage also have their output-voltage changed by the _PS0 and _PS3 power- management ACPI methods on the MMC-controllers ACPI fwnode as well as by the _DSM ACPI method for changing the signal voltage. The AML code implementing these methods is directly accessing the PMIC through ACPI I2C OpRegion accesses, instead of using the special PMIC OpRegion handled by drivers/acpi/pmic/intel_pmic_xpower.c . This means that the contents of the involved PMIC registers can change without the change being made through the regmap interface, so regmap should not cache the contents of these registers. Mark the regulator power on/off, the regulator voltage control and the GPIO1 control registers as volatile, to avoid regmap caching them. Specifically this fixes an issue on some models where the i915 driver toggles another LDO using the same on/off register on/off through MIPI sequences (through intel_soc_pmic_exec_mipi_pmic_seq_element()) which then writes back a cached on/off register-value where the card-voltage is off causing the external sdcard slot to stop working when the screen goes blank, or comes back on again. The regulator register-range now marked volatile also includes the buck regulator control registers. This is done on purpose these are normally not touched by the AML code, but they are updated directly by the SoC's PUNIT which means that they may also change without going through regmap. Note the AXP288 PMIC is only used on Bay- and Cherry-Trail platforms, so even though this is an ACPI specific problem there is no need to make the new volatile ranges conditional since these platforms always use ACPI. Fixes: dc91c3b6fe66 ("mfd: axp20x: Mark AXP20X_VBUS_IPSOUT_MGMT as volatile") Fixes: cd53216625a0 ("mfd: axp20x: Fix axp288 volatile ranges") Reported-and-tested-by: Clamshell Signed-off-by: Hans de Goede Reviewed-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- drivers/mfd/axp20x.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 4145a38b3890..d0ac019850d1 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -125,12 +125,13 @@ static const struct regmap_range axp288_writeable_ranges[] = { static const struct regmap_range axp288_volatile_ranges[] = { regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP288_POWER_REASON), + regmap_reg_range(AXP22X_PWR_OUT_CTRL1, AXP22X_ALDO3_V_OUT), regmap_reg_range(AXP288_BC_GLOBAL, AXP288_BC_GLOBAL), regmap_reg_range(AXP288_BC_DET_STAT, AXP20X_VBUS_IPSOUT_MGMT), regmap_reg_range(AXP20X_CHRG_BAK_CTRL, AXP20X_CHRG_BAK_CTRL), regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L), regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL), - regmap_reg_range(AXP22X_GPIO_STATE, AXP22X_GPIO_STATE), + regmap_reg_range(AXP20X_GPIO1_CTRL, AXP22X_GPIO_STATE), regmap_reg_range(AXP288_RT_BATT_V_H, AXP288_RT_BATT_V_L), regmap_reg_range(AXP20X_FG_RES, AXP288_FG_CC_CAP_REG), }; -- cgit v1.2.3 From f4ab169e88d9a512f3d93b315aa04ac1e058991b Mon Sep 17 00:00:00 2001 From: Martin Hundebøll Date: Tue, 29 Jun 2021 14:12:13 +0200 Subject: mfd: intel-m10-bmc: Add N5010 variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The m10-bmc is used on the Silicom N5010 PAC too, so add it to list of m10bmc types. Signed-off-by: Martin Hundebøll Acked-by: Moritz Fischer Reviewed-by: Xu Yilun Reviewed-by: Matthew Gerlach Signed-off-by: Lee Jones --- drivers/mfd/intel-m10-bmc.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/intel-m10-bmc.c b/drivers/mfd/intel-m10-bmc.c index 1a9bfb7f48cd..8db3bcf5fccc 100644 --- a/drivers/mfd/intel-m10-bmc.c +++ b/drivers/mfd/intel-m10-bmc.c @@ -15,7 +15,8 @@ enum m10bmc_type { M10_N3000, - M10_D5005 + M10_D5005, + M10_N5010, }; static struct mfd_cell m10bmc_d5005_subdevs[] = { @@ -28,6 +29,10 @@ static struct mfd_cell m10bmc_pacn3000_subdevs[] = { { .name = "n3000bmc-secure" }, }; +static struct mfd_cell m10bmc_n5010_subdevs[] = { + { .name = "n5010bmc-hwmon" }, +}; + static const struct regmap_range m10bmc_regmap_range[] = { regmap_reg_range(M10BMC_LEGACY_BUILD_VER, M10BMC_LEGACY_BUILD_VER), regmap_reg_range(M10BMC_SYS_BASE, M10BMC_SYS_END), @@ -192,6 +197,10 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) cells = m10bmc_d5005_subdevs; n_cell = ARRAY_SIZE(m10bmc_d5005_subdevs); break; + case M10_N5010: + cells = m10bmc_n5010_subdevs; + n_cell = ARRAY_SIZE(m10bmc_n5010_subdevs); + break; default: return -ENODEV; } @@ -207,6 +216,7 @@ static int intel_m10_bmc_spi_probe(struct spi_device *spi) static const struct spi_device_id m10bmc_spi_id[] = { { "m10-n3000", M10_N3000 }, { "m10-d5005", M10_D5005 }, + { "m10-n5010", M10_N5010 }, { } }; MODULE_DEVICE_TABLE(spi, m10bmc_spi_id); -- cgit v1.2.3 From 84742a98a97237146bdcc5f87c20a7d3d76e02de Mon Sep 17 00:00:00 2001 From: Fei Shao Date: Tue, 29 Jun 2021 17:43:38 +0800 Subject: mfd: mt6360: Sort regulator resources Reorder the regulator resources. Signed-off-by: Fei Shao Signed-off-by: Lee Jones --- drivers/mfd/mt6360-core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c index e628953548ce..6eaa6775b888 100644 --- a/drivers/mfd/mt6360-core.c +++ b/drivers/mfd/mt6360-core.c @@ -319,18 +319,18 @@ static const struct resource mt6360_regulator_resources[] = { DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"), DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"), - DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), - DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), - DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), - DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"), DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), }; static const struct mfd_cell mt6360_devs[] = { -- cgit v1.2.3 From ef0eea5b151aefe1efea78e2fa7c507ff3c56bf0 Mon Sep 17 00:00:00 2001 From: Chris Blake Date: Mon, 7 Jun 2021 18:35:35 -0500 Subject: mfd: lpc_ich: Enable GPIO driver for DH89xxCC Based on the Intel Datasheet for the DH89xxCC PCH, the GPIO driver is the same as ICH_v5_GPIO, minus the fact the DH89xxCC also has blink support. However, blink support isn't supported by the GPIO driver so we should use ICH_v5_GPIO. Tested and working on a Meraki MX100-HW. Signed-off-by: Chris Blake Co-developed-by: Christian Lamparter Signed-off-by: Lee Jones --- drivers/mfd/lpc_ich.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 3bbb29a7e7a5..f10e53187f67 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -489,6 +489,7 @@ static struct lpc_ich_info lpc_chipset_info[] = { [LPC_DH89XXCC] = { .name = "DH89xxCC", .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, }, [LPC_PPT] = { .name = "Panther Point", -- cgit v1.2.3 From 32979fcf5ab5df9359b98796886c5356b9cf4298 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 3 Jun 2021 19:51:28 +0300 Subject: mfd: intel-lpss: Add Intel Cannon Lake ACPI IDs Some of the machines, like Dell Precision 3630, may expose LPSS devices via ACPI. Add their IDs to the list. Signed-off-by: Andy Shevchenko Signed-off-by: Lee Jones --- drivers/mfd/intel-lpss-acpi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c index 1f396039d58f..3f1d976eb67c 100644 --- a/drivers/mfd/intel-lpss-acpi.c +++ b/drivers/mfd/intel-lpss-acpi.c @@ -89,6 +89,11 @@ static const struct intel_lpss_platform_info apl_i2c_info = { .swnode = &apl_i2c_node, }; +static const struct intel_lpss_platform_info cnl_i2c_info = { + .clk_rate = 216000000, + .swnode = &spt_i2c_node, +}; + static const struct acpi_device_id intel_lpss_acpi_ids[] = { /* SPT */ { "INT3440", (kernel_ulong_t)&spt_info }, @@ -102,6 +107,19 @@ static const struct acpi_device_id intel_lpss_acpi_ids[] = { { "INT3448", (kernel_ulong_t)&spt_uart_info }, { "INT3449", (kernel_ulong_t)&spt_uart_info }, { "INT344A", (kernel_ulong_t)&spt_uart_info }, + /* CNL */ + { "INT34B0", (kernel_ulong_t)&spt_info }, + { "INT34B1", (kernel_ulong_t)&spt_info }, + { "INT34B2", (kernel_ulong_t)&cnl_i2c_info }, + { "INT34B3", (kernel_ulong_t)&cnl_i2c_info }, + { "INT34B4", (kernel_ulong_t)&cnl_i2c_info }, + { "INT34B5", (kernel_ulong_t)&cnl_i2c_info }, + { "INT34B6", (kernel_ulong_t)&cnl_i2c_info }, + { "INT34B7", (kernel_ulong_t)&cnl_i2c_info }, + { "INT34B8", (kernel_ulong_t)&spt_uart_info }, + { "INT34B9", (kernel_ulong_t)&spt_uart_info }, + { "INT34BA", (kernel_ulong_t)&spt_uart_info }, + { "INT34BC", (kernel_ulong_t)&spt_info }, /* BXT */ { "80860AAC", (kernel_ulong_t)&bxt_i2c_info }, { "80860ABC", (kernel_ulong_t)&bxt_info }, -- cgit v1.2.3 From ec343111c056ec3847800302f6dbc57281f833fa Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 2 Aug 2021 01:33:13 +0200 Subject: mfd: db8500-prcmu: Adjust map to reality These are the actual frequencies reported by the PLL, so let's report these. The roundoffs are inappropriate, we should round to the frequency that the clock will later report. Drop some whitespace at the same time. Cc: phone-devel@vger.kernel.org Signed-off-by: Linus Walleij Signed-off-by: Lee Jones --- drivers/mfd/db8500-prcmu.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 3bde7fda755f..dea4e4e8bed5 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -1622,22 +1622,20 @@ static long round_clock_rate(u8 clock, unsigned long rate) } static const unsigned long db8500_armss_freqs[] = { - 200000000, - 400000000, - 800000000, + 199680000, + 399360000, + 798720000, 998400000 }; /* The DB8520 has slightly higher ARMSS max frequency */ static const unsigned long db8520_armss_freqs[] = { - 200000000, - 400000000, - 800000000, + 199680000, + 399360000, + 798720000, 1152000000 }; - - static long round_armss_rate(unsigned long rate) { unsigned long freq = 0; -- cgit v1.2.3 From 9ff80e2de36d0554e3a6da18a171719fe8663c17 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Sun, 25 Jul 2021 19:07:54 +0100 Subject: mfd: Don't use irq_create_mapping() to resolve a mapping Although irq_create_mapping() is able to deal with duplicate mappings, it really isn't supposed to be a substitute for irq_find_mapping(), and can result in allocations that take place in atomic context if the mapping didn't exist. Fix the handful of MFD drivers that use irq_create_mapping() in interrupt context by using irq_find_mapping() instead. Cc: Linus Walleij Cc: Lee Jones Cc: Maxime Coquelin Cc: Alexandre Torgue Signed-off-by: Marc Zyngier Signed-off-by: Lee Jones --- drivers/mfd/ab8500-core.c | 2 +- drivers/mfd/stmpe.c | 4 ++-- drivers/mfd/tc3589x.c | 2 +- drivers/mfd/wm8994-irq.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c index 30489670ea52..cca0aac26148 100644 --- a/drivers/mfd/ab8500-core.c +++ b/drivers/mfd/ab8500-core.c @@ -485,7 +485,7 @@ static int ab8500_handle_hierarchical_line(struct ab8500 *ab8500, if (line == AB8540_INT_GPIO43F || line == AB8540_INT_GPIO44F) line += 1; - handle_nested_irq(irq_create_mapping(ab8500->domain, line)); + handle_nested_irq(irq_find_mapping(ab8500->domain, line)); } return 0; diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index 1dd39483e7c1..58d09c615e67 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -1095,7 +1095,7 @@ static irqreturn_t stmpe_irq(int irq, void *data) if (variant->id_val == STMPE801_ID || variant->id_val == STMPE1600_ID) { - int base = irq_create_mapping(stmpe->domain, 0); + int base = irq_find_mapping(stmpe->domain, 0); handle_nested_irq(base); return IRQ_HANDLED; @@ -1123,7 +1123,7 @@ static irqreturn_t stmpe_irq(int irq, void *data) while (status) { int bit = __ffs(status); int line = bank * 8 + bit; - int nestedirq = irq_create_mapping(stmpe->domain, line); + int nestedirq = irq_find_mapping(stmpe->domain, line); handle_nested_irq(nestedirq); status &= ~(1 << bit); diff --git a/drivers/mfd/tc3589x.c b/drivers/mfd/tc3589x.c index 7614f8fe0e91..13583cdb93b6 100644 --- a/drivers/mfd/tc3589x.c +++ b/drivers/mfd/tc3589x.c @@ -187,7 +187,7 @@ again: while (status) { int bit = __ffs(status); - int virq = irq_create_mapping(tc3589x->domain, bit); + int virq = irq_find_mapping(tc3589x->domain, bit); handle_nested_irq(virq); status &= ~(1 << bit); diff --git a/drivers/mfd/wm8994-irq.c b/drivers/mfd/wm8994-irq.c index 6c3a619e2628..651a028bc519 100644 --- a/drivers/mfd/wm8994-irq.c +++ b/drivers/mfd/wm8994-irq.c @@ -154,7 +154,7 @@ static irqreturn_t wm8994_edge_irq(int irq, void *data) struct wm8994 *wm8994 = data; while (gpio_get_value_cansleep(wm8994->pdata.irq_gpio)) - handle_nested_irq(irq_create_mapping(wm8994->edge_irq, 0)); + handle_nested_irq(irq_find_mapping(wm8994->edge_irq, 0)); return IRQ_HANDLED; } -- cgit v1.2.3 From 32679a7a6b69d9307e6d89b45d554873ca625896 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 17 Jul 2021 18:25:28 +0200 Subject: mfd: axp20x: Add supplied-from property to axp288_fuel_gauge cell The power-supply framework has the notion of one power-supply device being supplied by another. A typical example of this is a charger charging a battery. A tablet getting plugged in to charge (or plugged out) only results in events seen by the axp288_charger device / MFD cell. Which means that a change udev-event only gets send for the charger power-supply class device, not for the battery (the axp288_fuel_gauge device). The axp288_fuel_gauge does have an external_power_change'd callback which will generate a change udev-event when called. But before this commit this never got called because the power-supply core only calls this when a power-supply class device's supplier changes and the supplier link from axp288_charger to axp288_fuel_gauge was missing. Add a "supplied-from" property to axp288_fuel_gauge cell, pointing to the "axp288_charger" power-supply class device, so that the axp288_fuel_gauge's external_power_change'd callback gets called on axp288_charger state changes. Signed-off-by: Hans de Goede Reviewed-by: Chen-Yu Tsai Signed-off-by: Lee Jones --- drivers/mfd/axp20x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index d0ac019850d1..8161a5dc68e8 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -700,6 +700,18 @@ static const struct resource axp288_charger_resources[] = { DEFINE_RES_IRQ(AXP288_IRQ_CBTO), }; +static const char * const axp288_fuel_gauge_suppliers[] = { "axp288_charger" }; + +static const struct property_entry axp288_fuel_gauge_properties[] = { + PROPERTY_ENTRY_STRING_ARRAY("supplied-from", axp288_fuel_gauge_suppliers), + { } +}; + +static const struct software_node axp288_fuel_gauge_sw_node = { + .name = "axp288_fuel_gauge", + .properties = axp288_fuel_gauge_properties, +}; + static const struct mfd_cell axp288_cells[] = { { .name = "axp288_adc", @@ -717,6 +729,7 @@ static const struct mfd_cell axp288_cells[] = { .name = "axp288_fuel_gauge", .num_resources = ARRAY_SIZE(axp288_fuel_gauge_resources), .resources = axp288_fuel_gauge_resources, + .swnode = &axp288_fuel_gauge_sw_node, }, { .name = "axp221-pek", .num_resources = ARRAY_SIZE(axp288_power_button_resources), -- cgit v1.2.3 From 8f00b3c41ae772e7393602a1b2e3bda4269ae636 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 2 Aug 2021 10:03:32 +0200 Subject: mfd: db8500-prcmu: Rename register header Drop the ambition to support dbx500, the other SoCs in this series were never deleted and the support for them has been deleted. DB8500 is what we support. Signed-off-by: Linus Walleij Signed-off-by: Lee Jones --- drivers/mfd/db8500-prcmu-regs.h | 226 ++++++++++++++++++++++++++++++++++++++++ drivers/mfd/db8500-prcmu.c | 2 +- drivers/mfd/dbx500-prcmu-regs.h | 226 ---------------------------------------- 3 files changed, 227 insertions(+), 227 deletions(-) create mode 100644 drivers/mfd/db8500-prcmu-regs.h delete mode 100644 drivers/mfd/dbx500-prcmu-regs.h (limited to 'drivers/mfd') diff --git a/drivers/mfd/db8500-prcmu-regs.h b/drivers/mfd/db8500-prcmu-regs.h new file mode 100644 index 000000000000..75fd1069372c --- /dev/null +++ b/drivers/mfd/db8500-prcmu-regs.h @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) STMicroelectronics 2009 + * Copyright (C) ST-Ericsson SA 2010 + * + * Author: Kumar Sanghvi + * Author: Sundar Iyer + * + * PRCM Unit registers + */ + +#ifndef __DB8500_PRCMU_REGS_H +#define __DB8500_PRCMU_REGS_H + +#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) + +#define PRCM_ACLK_MGT (0x004) +#define PRCM_SVAMMCSPCLK_MGT (0x008) +#define PRCM_SIAMMDSPCLK_MGT (0x00C) +#define PRCM_SGACLK_MGT (0x014) +#define PRCM_UARTCLK_MGT (0x018) +#define PRCM_MSP02CLK_MGT (0x01C) +#define PRCM_I2CCLK_MGT (0x020) +#define PRCM_SDMMCCLK_MGT (0x024) +#define PRCM_SLIMCLK_MGT (0x028) +#define PRCM_PER1CLK_MGT (0x02C) +#define PRCM_PER2CLK_MGT (0x030) +#define PRCM_PER3CLK_MGT (0x034) +#define PRCM_PER5CLK_MGT (0x038) +#define PRCM_PER6CLK_MGT (0x03C) +#define PRCM_PER7CLK_MGT (0x040) +#define PRCM_LCDCLK_MGT (0x044) +#define PRCM_BMLCLK_MGT (0x04C) +#define PRCM_HSITXCLK_MGT (0x050) +#define PRCM_HSIRXCLK_MGT (0x054) +#define PRCM_HDMICLK_MGT (0x058) +#define PRCM_APEATCLK_MGT (0x05C) +#define PRCM_APETRACECLK_MGT (0x060) +#define PRCM_MCDECLK_MGT (0x064) +#define PRCM_IPI2CCLK_MGT (0x068) +#define PRCM_DSIALTCLK_MGT (0x06C) +#define PRCM_DMACLK_MGT (0x074) +#define PRCM_B2R2CLK_MGT (0x078) +#define PRCM_TVCLK_MGT (0x07C) +#define PRCM_UNIPROCLK_MGT (0x278) +#define PRCM_SSPCLK_MGT (0x280) +#define PRCM_RNGCLK_MGT (0x284) +#define PRCM_UICCCLK_MGT (0x27C) +#define PRCM_MSP1CLK_MGT (0x288) + +#define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) +#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f +#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf + +#define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) +#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 + +#define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) +#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) +#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) + +#define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) +#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 +#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 + +#define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) +#define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) +#define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) +#define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) +#define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) +#define PRCM_SRAM_A9 (prcmu_base + 0x308) + +#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) +#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) + +/* CPU mailbox registers */ +#define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) +#define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) +#define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) + +#define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) +#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 +#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) +#define ARM_WAKEUP_MODEM 0x1 + +#define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) +#define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) +#define PRCM_HOLD_EVT (prcmu_base + 0x174) + +#define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) +#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) +#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) +#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) + +#define PRCM_ITSTATUS0 (prcmu_base + 0x148) +#define PRCM_ITSTATUS1 (prcmu_base + 0x150) +#define PRCM_ITSTATUS2 (prcmu_base + 0x158) +#define PRCM_ITSTATUS3 (prcmu_base + 0x160) +#define PRCM_ITSTATUS4 (prcmu_base + 0x168) +#define PRCM_ITSTATUS5 (prcmu_base + 0x484) +#define PRCM_ITCLEAR5 (prcmu_base + 0x488) +#define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) + +/* System reset register */ +#define PRCM_APE_SOFTRST (prcmu_base + 0x228) + +/* Level shifter and clamp control registers */ +#define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) +#define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) + +#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) +#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) + +/* PRCMU clock/PLL/reset registers */ +#define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) +#define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) +#define PRCM_PLLARM_FREQ (prcmu_base + 0x088) +#define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) +#define PRCM_PLL_FREQ_D_SHIFT 0 +#define PRCM_PLL_FREQ_D_MASK BITS(0, 7) +#define PRCM_PLL_FREQ_N_SHIFT 8 +#define PRCM_PLL_FREQ_N_MASK BITS(8, 13) +#define PRCM_PLL_FREQ_R_SHIFT 16 +#define PRCM_PLL_FREQ_R_MASK BITS(16, 18) +#define PRCM_PLL_FREQ_SELDIV2 BIT(24) +#define PRCM_PLL_FREQ_DIV2EN BIT(25) + +#define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) +#define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) +#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) +#define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) +#define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) +#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) +#define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) +#define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) + +#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) + +#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) +#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) + +#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0 +#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2) +#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8 +#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10) + +#define PRCM_DSI_PLLOUT_SEL_OFF 0 +#define PRCM_DSI_PLLOUT_SEL_PHI 1 +#define PRCM_DSI_PLLOUT_SEL_PHI_2 2 +#define PRCM_DSI_PLLOUT_SEL_PHI_4 3 + +#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0 +#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7) +#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8 +#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15) +#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16 +#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23) +#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) +#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) +#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) + +#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) + +#define PRCM_CLKOCR (prcmu_base + 0x1CC) +#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) +#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) +#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) +#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) + +/* ePOD and memory power signal control registers */ +#define PRCM_EPOD_C_SET (prcmu_base + 0x410) +#define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) + +/* Debug power control unit registers */ +#define PRCM_POWER_STATE_SET (prcmu_base + 0x254) + +/* Miscellaneous unit registers */ +#define PRCM_DSI_SW_RESET (prcmu_base + 0x324) +#define PRCM_GPIOCR (prcmu_base + 0x138) +#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 +#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 + +/* PRCMU HW semaphore */ +#define PRCM_SEM (prcmu_base + 0x400) +#define PRCM_SEM_PRCM_SEM BIT(0) + +#define PRCM_TCR (prcmu_base + 0x1C8) +#define PRCM_TCR_TENSEL_MASK BITS(0, 7) +#define PRCM_TCR_STOP_TIMERS BIT(16) +#define PRCM_TCR_DOZE_MODE BIT(17) + +#define PRCM_CLKOCR_CLKODIV0_SHIFT 0 +#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5) +#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6 +#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8) +#define PRCM_CLKOCR_CLKODIV1_SHIFT 16 +#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21) +#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22 +#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) +#define PRCM_CLKOCR_CLK1TYPE BIT(28) + +#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) +#define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) +#define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) +#define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) +#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) +#define PRCM_CLK_MGT_CLKEN BIT(8) +#define PRCM_CLK_MGT_CLK38 BIT(9) +#define PRCM_CLK_MGT_CLK38DIV BIT(11) +#define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) + +/* GPIOCR register */ +#define PRCM_GPIOCR_SPI2_SELECT BIT(23) + +#define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) +#define PRCM_CGATING_BYPASS (prcmu_base + 0x134) +#define PRCM_CGATING_BYPASS_ICN2 BIT(6) + +/* Miscellaneous unit registers */ +#define PRCM_RESOUTN_SET (prcmu_base + 0x214) +#define PRCM_RESOUTN_CLR (prcmu_base + 0x218) + +/* System reset register */ +#define PRCM_APE_SOFTRST (prcmu_base + 0x228) + +#endif /* __DB8500_PRCMU_REGS_H */ diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index dea4e4e8bed5..82058d11099f 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -37,7 +37,7 @@ #include #include #include -#include "dbx500-prcmu-regs.h" +#include "db8500-prcmu-regs.h" /* Index of different voltages to be used when accessing AVSData */ #define PRCM_AVS_BASE 0x2FC diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h deleted file mode 100644 index 75fd1069372c..000000000000 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) STMicroelectronics 2009 - * Copyright (C) ST-Ericsson SA 2010 - * - * Author: Kumar Sanghvi - * Author: Sundar Iyer - * - * PRCM Unit registers - */ - -#ifndef __DB8500_PRCMU_REGS_H -#define __DB8500_PRCMU_REGS_H - -#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) - -#define PRCM_ACLK_MGT (0x004) -#define PRCM_SVAMMCSPCLK_MGT (0x008) -#define PRCM_SIAMMDSPCLK_MGT (0x00C) -#define PRCM_SGACLK_MGT (0x014) -#define PRCM_UARTCLK_MGT (0x018) -#define PRCM_MSP02CLK_MGT (0x01C) -#define PRCM_I2CCLK_MGT (0x020) -#define PRCM_SDMMCCLK_MGT (0x024) -#define PRCM_SLIMCLK_MGT (0x028) -#define PRCM_PER1CLK_MGT (0x02C) -#define PRCM_PER2CLK_MGT (0x030) -#define PRCM_PER3CLK_MGT (0x034) -#define PRCM_PER5CLK_MGT (0x038) -#define PRCM_PER6CLK_MGT (0x03C) -#define PRCM_PER7CLK_MGT (0x040) -#define PRCM_LCDCLK_MGT (0x044) -#define PRCM_BMLCLK_MGT (0x04C) -#define PRCM_HSITXCLK_MGT (0x050) -#define PRCM_HSIRXCLK_MGT (0x054) -#define PRCM_HDMICLK_MGT (0x058) -#define PRCM_APEATCLK_MGT (0x05C) -#define PRCM_APETRACECLK_MGT (0x060) -#define PRCM_MCDECLK_MGT (0x064) -#define PRCM_IPI2CCLK_MGT (0x068) -#define PRCM_DSIALTCLK_MGT (0x06C) -#define PRCM_DMACLK_MGT (0x074) -#define PRCM_B2R2CLK_MGT (0x078) -#define PRCM_TVCLK_MGT (0x07C) -#define PRCM_UNIPROCLK_MGT (0x278) -#define PRCM_SSPCLK_MGT (0x280) -#define PRCM_RNGCLK_MGT (0x284) -#define PRCM_UICCCLK_MGT (0x27C) -#define PRCM_MSP1CLK_MGT (0x288) - -#define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) -#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f -#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf - -#define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) -#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2 - -#define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) -#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0) -#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL BIT(16) - -#define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) -#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1 -#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100 - -#define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) -#define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) -#define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) -#define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) -#define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) -#define PRCM_SRAM_A9 (prcmu_base + 0x308) - -#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0) -#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1) - -/* CPU mailbox registers */ -#define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) -#define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) -#define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) - -#define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) -#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1 -#define PRCM_HOSTACCESS_REQ_WAKE_REQ BIT(16) -#define ARM_WAKEUP_MODEM 0x1 - -#define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) -#define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) -#define PRCM_HOLD_EVT (prcmu_base + 0x174) - -#define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) -#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE BIT(0) -#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE BIT(1) -#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO BIT(2) - -#define PRCM_ITSTATUS0 (prcmu_base + 0x148) -#define PRCM_ITSTATUS1 (prcmu_base + 0x150) -#define PRCM_ITSTATUS2 (prcmu_base + 0x158) -#define PRCM_ITSTATUS3 (prcmu_base + 0x160) -#define PRCM_ITSTATUS4 (prcmu_base + 0x168) -#define PRCM_ITSTATUS5 (prcmu_base + 0x484) -#define PRCM_ITCLEAR5 (prcmu_base + 0x488) -#define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) - -/* System reset register */ -#define PRCM_APE_SOFTRST (prcmu_base + 0x228) - -/* Level shifter and clamp control registers */ -#define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) -#define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) - -#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP BIT(11) -#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI BIT(22) - -/* PRCMU clock/PLL/reset registers */ -#define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) -#define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) -#define PRCM_PLLARM_FREQ (prcmu_base + 0x088) -#define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) -#define PRCM_PLL_FREQ_D_SHIFT 0 -#define PRCM_PLL_FREQ_D_MASK BITS(0, 7) -#define PRCM_PLL_FREQ_N_SHIFT 8 -#define PRCM_PLL_FREQ_N_MASK BITS(8, 13) -#define PRCM_PLL_FREQ_R_SHIFT 16 -#define PRCM_PLL_FREQ_R_MASK BITS(16, 18) -#define PRCM_PLL_FREQ_SELDIV2 BIT(24) -#define PRCM_PLL_FREQ_DIV2EN BIT(25) - -#define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) -#define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) -#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) -#define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) -#define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) -#define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) -#define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) -#define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) - -#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0) - -#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 BIT(0) -#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3 BIT(1) - -#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT 0 -#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK BITS(0, 2) -#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT 8 -#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK BITS(8, 10) - -#define PRCM_DSI_PLLOUT_SEL_OFF 0 -#define PRCM_DSI_PLLOUT_SEL_PHI 1 -#define PRCM_DSI_PLLOUT_SEL_PHI_2 2 -#define PRCM_DSI_PLLOUT_SEL_PHI_4 3 - -#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT 0 -#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK BITS(0, 7) -#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT 8 -#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK BITS(8, 15) -#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT 16 -#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK BITS(16, 23) -#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN BIT(24) -#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN BIT(25) -#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN BIT(26) - -#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14) - -#define PRCM_CLKOCR (prcmu_base + 0x1CC) -#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) -#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) -#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) -#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) - -/* ePOD and memory power signal control registers */ -#define PRCM_EPOD_C_SET (prcmu_base + 0x410) -#define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) - -/* Debug power control unit registers */ -#define PRCM_POWER_STATE_SET (prcmu_base + 0x254) - -/* Miscellaneous unit registers */ -#define PRCM_DSI_SW_RESET (prcmu_base + 0x324) -#define PRCM_GPIOCR (prcmu_base + 0x138) -#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800 -#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1 - -/* PRCMU HW semaphore */ -#define PRCM_SEM (prcmu_base + 0x400) -#define PRCM_SEM_PRCM_SEM BIT(0) - -#define PRCM_TCR (prcmu_base + 0x1C8) -#define PRCM_TCR_TENSEL_MASK BITS(0, 7) -#define PRCM_TCR_STOP_TIMERS BIT(16) -#define PRCM_TCR_DOZE_MODE BIT(17) - -#define PRCM_CLKOCR_CLKODIV0_SHIFT 0 -#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5) -#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6 -#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8) -#define PRCM_CLKOCR_CLKODIV1_SHIFT 16 -#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21) -#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22 -#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) -#define PRCM_CLKOCR_CLK1TYPE BIT(28) - -#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) -#define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) -#define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) -#define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) -#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) -#define PRCM_CLK_MGT_CLKEN BIT(8) -#define PRCM_CLK_MGT_CLK38 BIT(9) -#define PRCM_CLK_MGT_CLK38DIV BIT(11) -#define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) - -/* GPIOCR register */ -#define PRCM_GPIOCR_SPI2_SELECT BIT(23) - -#define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) -#define PRCM_CGATING_BYPASS (prcmu_base + 0x134) -#define PRCM_CGATING_BYPASS_ICN2 BIT(6) - -/* Miscellaneous unit registers */ -#define PRCM_RESOUTN_SET (prcmu_base + 0x214) -#define PRCM_RESOUTN_CLR (prcmu_base + 0x218) - -/* System reset register */ -#define PRCM_APE_SOFTRST (prcmu_base + 0x228) - -#endif /* __DB8500_PRCMU_REGS_H */ -- cgit v1.2.3 From 9050ad816f5205c0d069e3e492eb849265ae5167 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 2 Aug 2021 01:33:14 +0200 Subject: mfd: db8500-prcmu: Handle missing FW variant There was an "unknown" firmware variant turning up in the wild causing problems in the clock driver. Add this missing variant and clarify that varian 11 and 15 are Samsung variants, as this is now very well known from released products. Signed-off-by: Linus Walleij Acked-by: Stephen Boyd Signed-off-by: Lee Jones --- drivers/clk/ux500/u8500_of_clk.c | 3 ++- drivers/mfd/db8500-prcmu.c | 6 ++++-- include/linux/mfd/dbx500-prcmu.h | 3 ++- 3 files changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c index 0aedd42fad52..528c5bb397cc 100644 --- a/drivers/clk/ux500/u8500_of_clk.c +++ b/drivers/clk/ux500/u8500_of_clk.c @@ -99,10 +99,11 @@ static void u8500_clk_init(struct device_node *np) if (fw_version != NULL) { switch (fw_version->project) { case PRCMU_FW_PROJECT_U8500_C2: - case PRCMU_FW_PROJECT_U8500_MBL: + case PRCMU_FW_PROJECT_U8500_SSG1: case PRCMU_FW_PROJECT_U8520: case PRCMU_FW_PROJECT_U8420: case PRCMU_FW_PROJECT_U8420_SYSCLK: + case PRCMU_FW_PROJECT_U8500_SSG2: sgaclk_parent = "soc0_pll"; break; default: diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 82058d11099f..75049cf38832 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -2565,14 +2565,16 @@ static char *fw_project_name(u32 project) return "U8500 C4"; case PRCMU_FW_PROJECT_U9500_MBL: return "U9500 MBL"; - case PRCMU_FW_PROJECT_U8500_MBL: - return "U8500 MBL"; + case PRCMU_FW_PROJECT_U8500_SSG1: + return "U8500 Samsung 1"; case PRCMU_FW_PROJECT_U8500_MBL2: return "U8500 MBL2"; case PRCMU_FW_PROJECT_U8520: return "U8520 MBL"; case PRCMU_FW_PROJECT_U8420: return "U8420"; + case PRCMU_FW_PROJECT_U8500_SSG2: + return "U8500 Samsung 2"; case PRCMU_FW_PROJECT_U8420_SYSCLK: return "U8420-sysclk"; case PRCMU_FW_PROJECT_U9540: diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index e6ee2ec35de9..cbf9d7619493 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -186,10 +186,11 @@ enum ddr_pwrst { #define PRCMU_FW_PROJECT_U8500_C3 8 #define PRCMU_FW_PROJECT_U8500_C4 9 #define PRCMU_FW_PROJECT_U9500_MBL 10 -#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */ +#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */ #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */ #define PRCMU_FW_PROJECT_U8520 13 #define PRCMU_FW_PROJECT_U8420 14 +#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */ #define PRCMU_FW_PROJECT_U8420_SYSCLK 17 #define PRCMU_FW_PROJECT_A9420 20 /* [32..63] 9540 and derivatives */ -- cgit v1.2.3 From e06f4abb1b79b31b712dc865f8ffc0e20ef2c416 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 27 Jul 2021 11:25:52 +0200 Subject: mfd: tps65086: Make interrupt line optional The BeagleV Starlight v0.9 board[1] doesn't have the IRQB line routed to the SoC, but it is still useful to be able to reach the PMIC over I2C for the other functionality it provides such as GPIOs and regulator settings. [1] https://github.com/beagleboard/beaglev-starlight Signed-off-by: Emil Renner Berthing Acked-by: Rob Herring Signed-off-by: Lee Jones --- .../devicetree/bindings/mfd/ti,tps65086.yaml | 3 --- drivers/mfd/tps65086.c | 21 +++++++++++---------- 2 files changed, 11 insertions(+), 13 deletions(-) (limited to 'drivers/mfd') diff --git a/Documentation/devicetree/bindings/mfd/ti,tps65086.yaml b/Documentation/devicetree/bindings/mfd/ti,tps65086.yaml index 9f6e1349eadc..6aeedda3be15 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps65086.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps65086.yaml @@ -87,9 +87,6 @@ additionalProperties: false required: - compatible - reg - - interrupts - - interrupt-controller - - '#interrupt-cells' - gpio-controller - '#gpio-cells' - regulators diff --git a/drivers/mfd/tps65086.c b/drivers/mfd/tps65086.c index 341466ef20cc..cc3478ee9a64 100644 --- a/drivers/mfd/tps65086.c +++ b/drivers/mfd/tps65086.c @@ -100,29 +100,30 @@ static int tps65086_probe(struct i2c_client *client, (char)((version & TPS65086_DEVICEID_OTP_MASK) >> 4) + 'A', (version & TPS65086_DEVICEID_REV_MASK) >> 6); - ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0, - &tps65086_irq_chip, &tps->irq_data); - if (ret) { - dev_err(tps->dev, "Failed to register IRQ chip\n"); - return ret; + if (tps->irq > 0) { + ret = regmap_add_irq_chip(tps->regmap, tps->irq, IRQF_ONESHOT, 0, + &tps65086_irq_chip, &tps->irq_data); + if (ret) { + dev_err(tps->dev, "Failed to register IRQ chip\n"); + return ret; + } } ret = mfd_add_devices(tps->dev, PLATFORM_DEVID_AUTO, tps65086_cells, ARRAY_SIZE(tps65086_cells), NULL, 0, regmap_irq_get_domain(tps->irq_data)); - if (ret) { + if (ret && tps->irq > 0) regmap_del_irq_chip(tps->irq, tps->irq_data); - return ret; - } - return 0; + return ret; } static int tps65086_remove(struct i2c_client *client) { struct tps65086 *tps = i2c_get_clientdata(client); - regmap_del_irq_chip(tps->irq, tps->irq_data); + if (tps->irq > 0) + regmap_del_irq_chip(tps->irq, tps->irq_data); return 0; } -- cgit v1.2.3 From 72b89b9ab58fae01f2deea30e0ff4d2349021506 Mon Sep 17 00:00:00 2001 From: Emil Renner Berthing Date: Tue, 27 Jul 2021 11:25:54 +0200 Subject: mfd: tps65086: Add cell entry for reset driver The only way to reset the BeagleV Starlight v0.9 board[1] properly is to tell the PMIC to reset itself which will then assert the external reset lines of the SoC, USB hub and ethernet phy. This adds an mfd cell entry for the reset driver doing just that. [1] https://github.com/beagleboard/beaglev-starlight Signed-off-by: Emil Renner Berthing Signed-off-by: Lee Jones --- drivers/mfd/tps65086.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tps65086.c b/drivers/mfd/tps65086.c index cc3478ee9a64..3bd5728844a0 100644 --- a/drivers/mfd/tps65086.c +++ b/drivers/mfd/tps65086.c @@ -24,6 +24,7 @@ static const struct mfd_cell tps65086_cells[] = { { .name = "tps65086-regulator", }, { .name = "tps65086-gpio", }, + { .name = "tps65086-reset", }, }; static const struct regmap_range tps65086_yes_ranges[] = { -- cgit v1.2.3 From f28fd3b6f73dd908776145143a63393be3522e54 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 6 Aug 2021 11:14:04 +0200 Subject: mfd/cpuidle: ux500: Rename driver symbol The PRCMU driver defines this as a DT node but there are no bindings for it and it needs no data from the device tree. Just spawn the device directly in the same way as the watchdog. Name it "db8500-cpuidle" since there are no ambitions to support any more SoCs than this one. This rids this annoying boot message: [ 0.032610] cpuidle-dbx500: Failed to locate of_node [id: 0] However I think the device still spawns and work just fine, despite not finding a device tree node. Cc: Rafael J. Wysocki Cc: linux-pm@vger.kernel.org Signed-off-by: Linus Walleij Acked-by: Daniel Lezcano Signed-off-by: Lee Jones --- drivers/cpuidle/cpuidle-ux500.c | 2 +- drivers/mfd/db8500-prcmu.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/cpuidle/cpuidle-ux500.c b/drivers/cpuidle/cpuidle-ux500.c index a2d34be17a09..f7d778580e9b 100644 --- a/drivers/cpuidle/cpuidle-ux500.c +++ b/drivers/cpuidle/cpuidle-ux500.c @@ -117,7 +117,7 @@ static int dbx500_cpuidle_probe(struct platform_device *pdev) static struct platform_driver dbx500_cpuidle_plat_driver = { .driver = { - .name = "cpuidle-dbx500", + .name = "db8500-cpuidle", }, .probe = dbx500_cpuidle_probe, }; diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 75049cf38832..2f4ba91c404a 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -2951,14 +2951,13 @@ static const struct mfd_cell common_prcmu_devs[] = { .pdata_size = sizeof(db8500_wdt_pdata), .id = -1, }, + MFD_CELL_NAME("db8500-cpuidle"), }; static const struct mfd_cell db8500_prcmu_devs[] = { MFD_CELL_OF("db8500-prcmu-regulators", NULL, &db8500_regulators, sizeof(db8500_regulators), 0, "stericsson,db8500-prcmu-regulator"), - MFD_CELL_OF("cpuidle-dbx500", - NULL, NULL, 0, 0, "stericsson,cpuidle-dbx500"), MFD_CELL_OF("db8500-thermal", NULL, NULL, 0, 0, "stericsson,db8500-thermal"), }; -- cgit v1.2.3 From c753ea31781aaab2dccc3e6f297cfde3c99f0ba1 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 4 Aug 2021 15:21:59 +0100 Subject: mfd: simple-mfd-i2c: Add support for registering devices via MFD cells More devices are cropping up requiring only Regmap initialisation and child registration functionality. We currently only support that if all required devices are represented by their own Device Tree nodes complete with compatible strings. However, not everyone is happy with adding empty nodes that provide no additional device information into the Device Tree. Rather than have a plethora of mostly empty, function-less drivers in MFD, we'll support those simple cases in here instead via MFD cells. Cc: Mark Brown Tested-by: Michael Walle Reviewed-by: Alistair Francis Tested-by: Alistair Francis Signed-off-by: Lee Jones --- drivers/mfd/simple-mfd-i2c.c | 41 +++++++++++++++++++++++++++++++++-------- drivers/mfd/simple-mfd-i2c.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 8 deletions(-) create mode 100644 drivers/mfd/simple-mfd-i2c.h (limited to 'drivers/mfd') diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c index 87f684cff9a1..51536691ad9d 100644 --- a/drivers/mfd/simple-mfd-i2c.c +++ b/drivers/mfd/simple-mfd-i2c.c @@ -2,39 +2,64 @@ /* * Simple MFD - I2C * + * Author(s): + * Michael Walle + * Lee Jones + * * This driver creates a single register map with the intention for it to be * shared by all sub-devices. Children can use their parent's device structure * (dev.parent) in order to reference it. * * Once the register map has been successfully initialised, any sub-devices - * represented by child nodes in Device Tree will be subsequently registered. + * represented by child nodes in Device Tree or via the MFD cells in this file + * will be subsequently registered. */ #include #include +#include #include #include #include -static const struct regmap_config simple_regmap_config = { +#include "simple-mfd-i2c.h" + +static const struct regmap_config regmap_config_8r_8v = { .reg_bits = 8, .val_bits = 8, }; static int simple_mfd_i2c_probe(struct i2c_client *i2c) { - const struct regmap_config *config; + const struct simple_mfd_data *simple_mfd_data; + const struct regmap_config *regmap_config; struct regmap *regmap; + int ret; + + simple_mfd_data = device_get_match_data(&i2c->dev); - config = device_get_match_data(&i2c->dev); - if (!config) - config = &simple_regmap_config; + /* If no regmap_config is specified, use the default 8reg and 8val bits */ + if (!simple_mfd_data || !simple_mfd_data->regmap_config) + regmap_config = ®map_config_8r_8v; + else + regmap_config = simple_mfd_data->regmap_config; - regmap = devm_regmap_init_i2c(i2c, config); + regmap = devm_regmap_init_i2c(i2c, regmap_config); if (IS_ERR(regmap)) return PTR_ERR(regmap); - return devm_of_platform_populate(&i2c->dev); + /* If no MFD cells are spedified, use register the DT child nodes instead */ + if (!simple_mfd_data || !simple_mfd_data->mfd_cell) + return devm_of_platform_populate(&i2c->dev); + + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, + simple_mfd_data->mfd_cell, + simple_mfd_data->mfd_cell_size, + NULL, 0, NULL); + if (ret) + dev_err(&i2c->dev, "Failed to add child devices\n"); + + return ret; } static const struct of_device_id simple_mfd_i2c_of_match[] = { diff --git a/drivers/mfd/simple-mfd-i2c.h b/drivers/mfd/simple-mfd-i2c.h new file mode 100644 index 000000000000..7cb2bdd347d9 --- /dev/null +++ b/drivers/mfd/simple-mfd-i2c.h @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Simple MFD - I2C + * + * Author: Lee Jones + * + * This driver creates a single register map with the intention for it to be + * shared by all sub-devices. Children can use their parent's device structure + * (dev.parent) in order to reference it. + * + * This driver creates a single register map with the intention for it to be + * shared by all sub-devices. Children can use their parent's device structure + * (dev.parent) in order to reference it. + * + * Once the register map has been successfully initialised, any sub-devices + * represented by child nodes in Device Tree or via the MFD cells in the + * associated C file will be subsequently registered. + */ + +#ifndef __MFD_SIMPLE_MFD_I2C_H +#define __MFD_SIMPLE_MFD_I2C_H + +#include +#include + +struct simple_mfd_data { + const struct regmap_config *regmap_config; + const struct mfd_cell *mfd_cell; + size_t mfd_cell_size; +}; + +#endif /* __MFD_SIMPLE_MFD_I2C_H */ -- cgit v1.2.3 From a946506c48f3bd09363c9d2b0a178e55733bcbb6 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 16 Jul 2021 12:00:48 +0200 Subject: mfd: tqmx86: Clear GPIO IRQ resource when no IRQ is set The driver was registering IRQ 0 when no IRQ was set. This leads to warnings with newer kernels. Clear the resource flags, so no resource is registered at all in this case. Fixes: 2f17dd34ffed ("mfd: tqmx86: IO controller with I2C, Wachdog and GPIO") Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Signed-off-by: Lee Jones --- drivers/mfd/tqmx86.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index ddddf08b6a4c..732013f40e4e 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -209,6 +209,8 @@ static int tqmx86_probe(struct platform_device *pdev) /* Assumes the IRQ resource is first. */ tqmx_gpio_resources[0].start = gpio_irq; + } else { + tqmx_gpio_resources[0].flags = 0; } ocores_platfom_data.clock_khz = tqmx86_board_id_to_clk_rate(board_id); -- cgit v1.2.3 From 16b2ad150f74db0eb91f445061f16140b5aaa650 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 16 Jul 2021 12:00:49 +0200 Subject: mfd: tqmx86: Remove incorrect TQMx90UC board ID No TQMx90UC exists at the moment, and it is undecided whether ID 10 will be used eventually (and if it is, how that SoM will be named). Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Signed-off-by: Lee Jones --- drivers/mfd/tqmx86.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index 732013f40e4e..9b65dbedc1bb 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -35,7 +35,6 @@ #define TQMX86_REG_BOARD_ID_E39x 7 #define TQMX86_REG_BOARD_ID_70EB 8 #define TQMX86_REG_BOARD_ID_80UC 9 -#define TQMX86_REG_BOARD_ID_90UC 10 #define TQMX86_REG_BOARD_REV 0x21 #define TQMX86_REG_IO_EXT_INT 0x26 #define TQMX86_REG_IO_EXT_INT_NONE 0 @@ -128,8 +127,6 @@ static const char *tqmx86_board_id_to_name(u8 board_id) return "TQMx70EB"; case TQMX86_REG_BOARD_ID_80UC: return "TQMx80UC"; - case TQMX86_REG_BOARD_ID_90UC: - return "TQMx90UC"; default: return "Unknown"; } @@ -142,7 +139,6 @@ static int tqmx86_board_id_to_clk_rate(u8 board_id) case TQMX86_REG_BOARD_ID_60EB: case TQMX86_REG_BOARD_ID_70EB: case TQMX86_REG_BOARD_ID_80UC: - case TQMX86_REG_BOARD_ID_90UC: return 24000; case TQMX86_REG_BOARD_ID_E39M: case TQMX86_REG_BOARD_ID_E39C: -- cgit v1.2.3 From 41e9b5e2d88f6452be0f82a5f66b69ff5d26622e Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 16 Jul 2021 12:00:50 +0200 Subject: mfd: tqmx86: Fix typo in "platform" Rename variable from "ocores_platfom_data" to "ocores_platform_data". Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Signed-off-by: Lee Jones --- drivers/mfd/tqmx86.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index 9b65dbedc1bb..ff1bdb742e3f 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -76,7 +76,7 @@ static struct i2c_board_info tqmx86_i2c_devices[] = { }, }; -static struct ocores_i2c_platform_data ocores_platfom_data = { +static struct ocores_i2c_platform_data ocores_platform_data = { .num_devices = ARRAY_SIZE(tqmx86_i2c_devices), .devices = tqmx86_i2c_devices, }; @@ -84,8 +84,8 @@ static struct ocores_i2c_platform_data ocores_platfom_data = { static const struct mfd_cell tqmx86_i2c_soft_dev[] = { { .name = "ocores-i2c", - .platform_data = &ocores_platfom_data, - .pdata_size = sizeof(ocores_platfom_data), + .platform_data = &ocores_platform_data, + .pdata_size = sizeof(ocores_platform_data), .resources = tqmx_i2c_soft_resources, .num_resources = ARRAY_SIZE(tqmx_i2c_soft_resources), }, @@ -209,7 +209,7 @@ static int tqmx86_probe(struct platform_device *pdev) tqmx_gpio_resources[0].flags = 0; } - ocores_platfom_data.clock_khz = tqmx86_board_id_to_clk_rate(board_id); + ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(board_id); if (i2c_det == TQMX86_REG_I2C_DETECT_SOFT) { err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, -- cgit v1.2.3 From 3da48ccb1d0f3b53b1e8c9022edbedc2a6e3f50a Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 16 Jul 2021 12:00:51 +0200 Subject: mfd: tqmx86: Add support for TQMx110EB and TQMxE40x Add the board IDs for the TQMx110EB and the TQMxE40x family. All use a 24MHz LPC clock. Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Signed-off-by: Lee Jones --- drivers/mfd/tqmx86.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index ff1bdb742e3f..9eb05b3ef573 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -35,6 +35,11 @@ #define TQMX86_REG_BOARD_ID_E39x 7 #define TQMX86_REG_BOARD_ID_70EB 8 #define TQMX86_REG_BOARD_ID_80UC 9 +#define TQMX86_REG_BOARD_ID_110EB 11 +#define TQMX86_REG_BOARD_ID_E40M 12 +#define TQMX86_REG_BOARD_ID_E40S 13 +#define TQMX86_REG_BOARD_ID_E40C1 14 +#define TQMX86_REG_BOARD_ID_E40C2 15 #define TQMX86_REG_BOARD_REV 0x21 #define TQMX86_REG_IO_EXT_INT 0x26 #define TQMX86_REG_IO_EXT_INT_NONE 0 @@ -127,6 +132,16 @@ static const char *tqmx86_board_id_to_name(u8 board_id) return "TQMx70EB"; case TQMX86_REG_BOARD_ID_80UC: return "TQMx80UC"; + case TQMX86_REG_BOARD_ID_110EB: + return "TQMx110EB"; + case TQMX86_REG_BOARD_ID_E40M: + return "TQMxE40M"; + case TQMX86_REG_BOARD_ID_E40S: + return "TQMxE40S"; + case TQMX86_REG_BOARD_ID_E40C1: + return "TQMxE40C1"; + case TQMX86_REG_BOARD_ID_E40C2: + return "TQMxE40C2"; default: return "Unknown"; } @@ -139,6 +154,11 @@ static int tqmx86_board_id_to_clk_rate(u8 board_id) case TQMX86_REG_BOARD_ID_60EB: case TQMX86_REG_BOARD_ID_70EB: case TQMX86_REG_BOARD_ID_80UC: + case TQMX86_REG_BOARD_ID_110EB: + case TQMX86_REG_BOARD_ID_E40M: + case TQMX86_REG_BOARD_ID_E40S: + case TQMX86_REG_BOARD_ID_E40C1: + case TQMX86_REG_BOARD_ID_E40C2: return 24000; case TQMX86_REG_BOARD_ID_E39M: case TQMX86_REG_BOARD_ID_E39C: -- cgit v1.2.3 From d5949a35cc29db81f7b50ac0b18a114ffc655ea5 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 16 Jul 2021 12:00:52 +0200 Subject: mfd: tqmx86: Add support for TQ-Systems DMI IDs Newer TQMx86 modules use TQ-Systems instead of TQ-Group as their vendor ID. Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Signed-off-by: Lee Jones --- drivers/mfd/tqmx86.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index 9eb05b3ef573..58f35c8b5a45 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -271,6 +271,14 @@ static const struct dmi_system_id tqmx86_dmi_table[] __initconst = { }, .callback = tqmx86_create_platform_device, }, + { + .ident = "TQMX86", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "TQ-Systems"), + DMI_MATCH(DMI_PRODUCT_NAME, "TQMx"), + }, + .callback = tqmx86_create_platform_device, + }, {} }; MODULE_DEVICE_TABLE(dmi, tqmx86_dmi_table); -- cgit v1.2.3 From 9a8c4bace04a61efbcce4bd44ffa8b86b03ffdfe Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 16 Jul 2021 12:00:53 +0200 Subject: mfd: tqmx86: Assume 24MHz LPC clock for unknown boards All future TQMx86 modules should use a 24MHz LPC clock. Warn about unknown boards, but assume this is the case. Signed-off-by: Matthias Schiffer Reviewed-by: Andrew Lunn Signed-off-by: Lee Jones --- drivers/mfd/tqmx86.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/tqmx86.c b/drivers/mfd/tqmx86.c index 58f35c8b5a45..7ae906ff8e35 100644 --- a/drivers/mfd/tqmx86.c +++ b/drivers/mfd/tqmx86.c @@ -147,7 +147,7 @@ static const char *tqmx86_board_id_to_name(u8 board_id) } } -static int tqmx86_board_id_to_clk_rate(u8 board_id) +static int tqmx86_board_id_to_clk_rate(struct device *dev, u8 board_id) { switch (board_id) { case TQMX86_REG_BOARD_ID_50UC: @@ -168,7 +168,9 @@ static int tqmx86_board_id_to_clk_rate(u8 board_id) case TQMX86_REG_BOARD_ID_E38C: return 33000; default: - return 0; + dev_warn(dev, "unknown board %d, assuming 24MHz LPC clock\n", + board_id); + return 24000; } } @@ -229,7 +231,7 @@ static int tqmx86_probe(struct platform_device *pdev) tqmx_gpio_resources[0].flags = 0; } - ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(board_id); + ocores_platform_data.clock_khz = tqmx86_board_id_to_clk_rate(dev, board_id); if (i2c_det == TQMX86_REG_I2C_DETECT_SOFT) { err = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, -- cgit v1.2.3 From bc239d8d6dd927af1df3fa3984ccf5f531d1be54 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Wed, 11 Aug 2021 20:19:34 +0800 Subject: mfd: ti_am335x_tscadc: Delete superfluous error message In the function ti_tscadc_probe(), when get irq failed, platform_get_irq() logs an error message, so remove redundant message here. Signed-off-by: Tang Bin Signed-off-by: Lee Jones --- drivers/mfd/ti_am335x_tscadc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c index 0e6e25308190..55adc379f94b 100644 --- a/drivers/mfd/ti_am335x_tscadc.c +++ b/drivers/mfd/ti_am335x_tscadc.c @@ -175,10 +175,9 @@ static int ti_tscadc_probe(struct platform_device *pdev) tscadc->dev = &pdev->dev; err = platform_get_irq(pdev, 0); - if (err < 0) { - dev_err(&pdev->dev, "no irq ID is specified.\n"); + if (err < 0) goto ret; - } else + else tscadc->irq = err; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- cgit v1.2.3 From 452d07413954ef38951cfd41507b310c3afccd93 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Mon, 23 Aug 2021 23:31:22 +0900 Subject: mfd: syscon: Use of_iomap() instead of ioremap() This automatically selects between ioremap() and ioremap_np() on platforms that require it, such as Apple SoCs. Signed-off-by: Hector Martin Acked-by: Arnd Bergmann Signed-off-by: Lee Jones --- drivers/mfd/syscon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c index 765c0210cb52..191fdb87c424 100644 --- a/drivers/mfd/syscon.c +++ b/drivers/mfd/syscon.c @@ -60,7 +60,7 @@ static struct syscon *of_syscon_register(struct device_node *np, bool check_clk) goto err_map; } - base = ioremap(res.start, resource_size(&res)); + base = of_iomap(np, 0); if (!base) { ret = -ENOMEM; goto err_map; -- cgit v1.2.3 From cdff1eda69326fb46de10c5454212b3efcf4bb41 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 6 Sep 2021 17:19:49 -0700 Subject: mfd: lpc_sch: Rename GPIOBASE to prevent build error One MIPS platform (mach-rc32434) defines GPIOBASE. This macro conflicts with one of the same name in lpc_sch.c. Rename the latter one to prevent the build error. ../drivers/mfd/lpc_sch.c:25: error: "GPIOBASE" redefined [-Werror] 25 | #define GPIOBASE 0x44 ../arch/mips/include/asm/mach-rc32434/rb.h:32: note: this is the location of the previous definition 32 | #define GPIOBASE 0x050000 Cc: Denis Turischev Fixes: e82c60ae7d3a ("mfd: Introduce lpc_sch for Intel SCH LPC bridge") Signed-off-by: Randy Dunlap Signed-off-by: Lee Jones --- drivers/mfd/lpc_sch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/mfd') diff --git a/drivers/mfd/lpc_sch.c b/drivers/mfd/lpc_sch.c index 428a526cbe86..9ab9adce06fd 100644 --- a/drivers/mfd/lpc_sch.c +++ b/drivers/mfd/lpc_sch.c @@ -22,7 +22,7 @@ #define SMBASE 0x40 #define SMBUS_IO_SIZE 64 -#define GPIOBASE 0x44 +#define GPIO_BASE 0x44 #define GPIO_IO_SIZE 64 #define GPIO_IO_SIZE_CENTERTON 128 @@ -145,7 +145,7 @@ static int lpc_sch_probe(struct pci_dev *dev, const struct pci_device_id *id) if (ret == 0) cells++; - ret = lpc_sch_populate_cell(dev, GPIOBASE, "sch_gpio", + ret = lpc_sch_populate_cell(dev, GPIO_BASE, "sch_gpio", info->io_size_gpio, id->device, &lpc_sch_cells[cells]); if (ret < 0) -- cgit v1.2.3