From 6442241630d1273033ae7f6665c4caec19671633 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 6 Jul 2020 20:35:25 +0200 Subject: media: ti-vpe: cal: Index CSI-2 port starting at 0 The datasheet numbers the CSI-2 PHYs (external to the CAL) starting from 1, but the PPI inputs to the CAL starting from 0. Update the numbering scheme for csi2_port to match the datasheet, which also simplifies the driver by removing the need to constantly subtract 1 from the value. Signed-off-by: Laurent Pinchart Reviewed-by: Tomi Valkeinen Reviewed-by: Benoit Parrot Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/ti-vpe/cal_regs.h | 64 ++++++++++++++++---------------- 1 file changed, 32 insertions(+), 32 deletions(-) (limited to 'drivers/media/platform/ti-vpe/cal_regs.h') diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index ac54a2fe7bb6..56c8ccd0e75f 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -46,7 +46,7 @@ #define CAL_HL_IRQSTATUS(m) (0x24U + ((m-1) * 0x10U)) #define CAL_HL_IRQENABLE_SET(m) (0x28U + ((m-1) * 0x10U)) #define CAL_HL_IRQENABLE_CLR(m) (0x2cU + ((m-1) * 0x10U)) -#define CAL_PIX_PROC(m) (0xc0U + ((m-1) * 0x4U)) +#define CAL_PIX_PROC(m) (0xc0U + (m) * 0x4U) #define CAL_CTRL 0x100 #define CAL_CTRL1 0x104 #define CAL_LINE_NUMBER_EVT 0x108 @@ -62,34 +62,34 @@ #define CAL_RD_DMA_INIT_ADDR 0x154 #define CAL_RD_DMA_INIT_OFST 0x168 #define CAL_RD_DMA_CTRL2 0x16c -#define CAL_WR_DMA_CTRL(m) (0x200U + ((m-1) * 0x10U)) -#define CAL_WR_DMA_ADDR(m) (0x204U + ((m-1) * 0x10U)) -#define CAL_WR_DMA_OFST(m) (0x208U + ((m-1) * 0x10U)) -#define CAL_WR_DMA_XSIZE(m) (0x20cU + ((m-1) * 0x10U)) -#define CAL_CSI2_PPI_CTRL(m) (0x300U + ((m-1) * 0x80U)) -#define CAL_CSI2_COMPLEXIO_CFG(m) (0x304U + ((m-1) * 0x80U)) -#define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) (0x308U + ((m-1) * 0x80U)) -#define CAL_CSI2_SHORT_PACKET(m) (0x30cU + ((m-1) * 0x80U)) -#define CAL_CSI2_COMPLEXIO_IRQENABLE(m) (0x310U + ((m-1) * 0x80U)) -#define CAL_CSI2_TIMING(m) (0x314U + ((m-1) * 0x80U)) -#define CAL_CSI2_VC_IRQENABLE(m) (0x318U + ((m-1) * 0x80U)) -#define CAL_CSI2_VC_IRQSTATUS(m) (0x328U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX0(m) (0x330U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX1(m) (0x334U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX2(m) (0x338U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX3(m) (0x33cU + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX4(m) (0x340U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX5(m) (0x344U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX6(m) (0x348U + ((m-1) * 0x80U)) -#define CAL_CSI2_CTX7(m) (0x34cU + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS0(m) (0x350U + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS1(m) (0x354U + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS2(m) (0x358U + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS3(m) (0x35cU + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS4(m) (0x360U + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS5(m) (0x364U + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS6(m) (0x368U + ((m-1) * 0x80U)) -#define CAL_CSI2_STATUS7(m) (0x36cU + ((m-1) * 0x80U)) +#define CAL_WR_DMA_CTRL(m) (0x200U + (m) * 0x10U) +#define CAL_WR_DMA_ADDR(m) (0x204U + (m) * 0x10U) +#define CAL_WR_DMA_OFST(m) (0x208U + (m) * 0x10U) +#define CAL_WR_DMA_XSIZE(m) (0x20cU + (m) * 0x10U) +#define CAL_CSI2_PPI_CTRL(m) (0x300U + (m) * 0x80U) +#define CAL_CSI2_COMPLEXIO_CFG(m) (0x304U + (m) * 0x80U) +#define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) (0x308U + (m) * 0x80U) +#define CAL_CSI2_SHORT_PACKET(m) (0x30cU + (m) * 0x80U) +#define CAL_CSI2_COMPLEXIO_IRQENABLE(m) (0x310U + (m) * 0x80U) +#define CAL_CSI2_TIMING(m) (0x314U + (m) * 0x80U) +#define CAL_CSI2_VC_IRQENABLE(m) (0x318U + (m) * 0x80U) +#define CAL_CSI2_VC_IRQSTATUS(m) (0x328U + (m) * 0x80U) +#define CAL_CSI2_CTX0(m) (0x330U + (m) * 0x80U) +#define CAL_CSI2_CTX1(m) (0x334U + (m) * 0x80U) +#define CAL_CSI2_CTX2(m) (0x338U + (m) * 0x80U) +#define CAL_CSI2_CTX3(m) (0x33cU + (m) * 0x80U) +#define CAL_CSI2_CTX4(m) (0x340U + (m) * 0x80U) +#define CAL_CSI2_CTX5(m) (0x344U + (m) * 0x80U) +#define CAL_CSI2_CTX6(m) (0x348U + (m) * 0x80U) +#define CAL_CSI2_CTX7(m) (0x34cU + (m) * 0x80U) +#define CAL_CSI2_STATUS0(m) (0x350U + (m) * 0x80U) +#define CAL_CSI2_STATUS1(m) (0x354U + (m) * 0x80U) +#define CAL_CSI2_STATUS2(m) (0x358U + (m) * 0x80U) +#define CAL_CSI2_STATUS3(m) (0x35cU + (m) * 0x80U) +#define CAL_CSI2_STATUS4(m) (0x360U + (m) * 0x80U) +#define CAL_CSI2_STATUS5(m) (0x364U + (m) * 0x80U) +#define CAL_CSI2_STATUS6(m) (0x368U + (m) * 0x80U) +#define CAL_CSI2_STATUS7(m) (0x36cU + (m) * 0x80U) /* CAL CSI2 PHY register offsets */ #define CAL_CSI2_PHY_REG0 0x000 @@ -141,12 +141,12 @@ #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0 0 #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0 0 -#define CAL_HL_IRQ_MASK(m) BIT((m) - 1) +#define CAL_HL_IRQ_MASK(m) BIT(m) #define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6) -#define CAL_HL_IRQ_CIO_MASK(i) BIT(16 + ((i) - 1) * 8) -#define CAL_HL_IRQ_VC_MASK(i) BIT(17 + ((i) - 1) * 8) +#define CAL_HL_IRQ_CIO_MASK(i) BIT(16 + (i) * 8) +#define CAL_HL_IRQ_VC_MASK(i) BIT(17 + (i) * 8) #define CAL_PIX_PROC_EN_MASK BIT(0) #define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1) -- cgit v1.2.3 From 255502a723b5fecf01e7f02d19ba49d507c673d5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 6 Jul 2020 20:35:26 +0200 Subject: media: ti-vpe: cal: Index IRQ registersstarting at 0 The datasheet numbers the IRQ registers starting from 0. Update the numbering scheme to match the datasheet. Signed-off-by: Laurent Pinchart Reviewed-by: Tomi Valkeinen Reviewed-by: Benoit Parrot Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/ti-vpe/cal.c | 38 ++++++++++++++++---------------- drivers/media/platform/ti-vpe/cal_regs.h | 8 +++---- 2 files changed, 23 insertions(+), 23 deletions(-) (limited to 'drivers/media/platform/ti-vpe/cal_regs.h') diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index 799c25f5aafd..b04d8cb86977 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -695,22 +695,22 @@ static void enable_irqs(struct cal_ctx *ctx) CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK; /* Enable CIO error irqs */ - reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1), + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_CIO_MASK(ctx->csi2_port)); reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_IRQENABLE(ctx->csi2_port), cio_err_mask); /* Always enable OCPO error */ - reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1), CAL_HL_IRQ_OCPO_ERR_MASK); + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(0), CAL_HL_IRQ_OCPO_ERR_MASK); /* Enable IRQ_WDMA_END 0/1 */ val = 0; set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); - reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(2), val); + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1), val); /* Enable IRQ_WDMA_START 0/1 */ val = 0; set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); - reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(3), val); + reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(2), val); /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(0), 0xFF000000); } @@ -720,7 +720,7 @@ static void disable_irqs(struct cal_ctx *ctx) u32 val; /* Disable CIO error irqs */ - reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(1), + reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(0), CAL_HL_IRQ_CIO_MASK(ctx->csi2_port)); reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_IRQENABLE(ctx->csi2_port), 0); @@ -728,11 +728,11 @@ static void disable_irqs(struct cal_ctx *ctx) /* Disable IRQ_WDMA_END 0/1 */ val = 0; set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); - reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(2), val); + reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(1), val); /* Disable IRQ_WDMA_START 0/1 */ val = 0; set_field(&val, 1, CAL_HL_IRQ_MASK(ctx->csi2_port)); - reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(3), val); + reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(2), val); /* Todo: Add VC_IRQ and CSI2_COMPLEXIO_IRQ handling */ reg_write(ctx->dev, CAL_CSI2_VC_IRQENABLE(0), 0); } @@ -1206,13 +1206,13 @@ static irqreturn_t cal_irq(int irq_cal, void *data) struct cal_dev *dev = (struct cal_dev *)data; struct cal_ctx *ctx; struct cal_dmaqueue *dma_q; - u32 irqst1, irqst2, irqst3; + u32 irqst0, irqst1, irqst2; - irqst1 = reg_read(dev, CAL_HL_IRQSTATUS(1)); - if (irqst1) { + irqst0 = reg_read(dev, CAL_HL_IRQSTATUS(0)); + if (irqst0) { int i; - reg_write(dev, CAL_HL_IRQSTATUS(1), irqst1); + reg_write(dev, CAL_HL_IRQSTATUS(0), irqst0); if (irqst1 & CAL_HL_IRQ_OCPO_ERR_MASK) dev_err_ratelimited(&dev->pdev->dev, "OCPO ERROR\n"); @@ -1232,15 +1232,15 @@ static irqreturn_t cal_irq(int irq_cal, void *data) } /* Check which DMA just finished */ - irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2)); - if (irqst2) { + irqst1 = reg_read(dev, CAL_HL_IRQSTATUS(1)); + if (irqst1) { int i; /* Clear Interrupt status */ - reg_write(dev, CAL_HL_IRQSTATUS(2), irqst2); + reg_write(dev, CAL_HL_IRQSTATUS(1), irqst1); for (i = 0; i < 2; ++i) { - if (isportirqset(irqst2, i)) { + if (isportirqset(irqst1, i)) { ctx = dev->ctx[i]; spin_lock(&ctx->slock); @@ -1255,15 +1255,15 @@ static irqreturn_t cal_irq(int irq_cal, void *data) } /* Check which DMA just started */ - irqst3 = reg_read(dev, CAL_HL_IRQSTATUS(3)); - if (irqst3) { + irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2)); + if (irqst2) { int i; /* Clear Interrupt status */ - reg_write(dev, CAL_HL_IRQSTATUS(3), irqst3); + reg_write(dev, CAL_HL_IRQSTATUS(2), irqst2); for (i = 0; i < 2; ++i) { - if (isportirqset(irqst3, i)) { + if (isportirqset(irqst2, i)) { ctx = dev->ctx[i]; dma_q = &ctx->vidq; diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index 56c8ccd0e75f..b551e67d5d41 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -42,10 +42,10 @@ #define CAL_HL_HWINFO 0x0004 #define CAL_HL_SYSCONFIG 0x0010 #define CAL_HL_IRQ_EOI 0x001c -#define CAL_HL_IRQSTATUS_RAW(m) (0x20U + ((m-1) * 0x10U)) -#define CAL_HL_IRQSTATUS(m) (0x24U + ((m-1) * 0x10U)) -#define CAL_HL_IRQENABLE_SET(m) (0x28U + ((m-1) * 0x10U)) -#define CAL_HL_IRQENABLE_CLR(m) (0x2cU + ((m-1) * 0x10U)) +#define CAL_HL_IRQSTATUS_RAW(m) (0x20U + (m) * 0x10U) +#define CAL_HL_IRQSTATUS(m) (0x24U + (m) * 0x10U) +#define CAL_HL_IRQENABLE_SET(m) (0x28U + (m) * 0x10U) +#define CAL_HL_IRQENABLE_CLR(m) (0x2cU + (m) * 0x10U) #define CAL_PIX_PROC(m) (0xc0U + (m) * 0x4U) #define CAL_CTRL 0x100 #define CAL_CTRL1 0x104 -- cgit v1.2.3 From 4c0ed7ba65d1c2e9476c083ba83c23fe68ef6ebc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Mon, 6 Jul 2020 20:36:27 +0200 Subject: media: ti-vpe: cal: Move CAL_NUM_CSI2_PORTS from cal_regs.h to cal.c The CAL_NUM_CSI2_PORTS macro isn't a register definition. Move it to cal.c, and fix indentation of the other macros while at it. Signed-off-by: Laurent Pinchart Reviewed-by: Benoit Parrot Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab --- drivers/media/platform/ti-vpe/cal.c | 7 ++++--- drivers/media/platform/ti-vpe/cal_regs.h | 2 -- 2 files changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/media/platform/ti-vpe/cal_regs.h') diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index e4d8cadf7bef..67b87d33639d 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -75,10 +75,11 @@ MODULE_PARM_DESC(debug, "activates debug info"); #define phy_err(phy, fmt, arg...) \ cal_err((phy)->cal, "phy%u: " fmt, (phy)->instance, ##arg) -#define CAL_NUM_CONTEXT 2 +#define CAL_NUM_CONTEXT 2 +#define CAL_NUM_CSI2_PORTS 2 -#define MAX_WIDTH_BYTES (8192 * 8) -#define MAX_HEIGHT_LINES 16383 +#define MAX_WIDTH_BYTES (8192 * 8) +#define MAX_HEIGHT_LINES 16383 /* ------------------------------------------------------------------ * Format Handling diff --git a/drivers/media/platform/ti-vpe/cal_regs.h b/drivers/media/platform/ti-vpe/cal_regs.h index b551e67d5d41..f752096dcf7f 100644 --- a/drivers/media/platform/ti-vpe/cal_regs.h +++ b/drivers/media/platform/ti-vpe/cal_regs.h @@ -34,8 +34,6 @@ */ #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0) -#define CAL_NUM_CSI2_PORTS 2 - /* CAL register offsets */ #define CAL_HL_REVISION 0x0000 -- cgit v1.2.3