From f668f074ff58dea540d83bbed1b2c1171b0dd764 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:21 -0800 Subject: irqchip: bcm7120-l2: Eliminate bad IRQ check This check may be prone to race conditions, e.g. 1) Some external event (e.g. GPIO level) causes an IRQ to become pending 2) Peripheral asserts the L2 IRQ 3) CPU takes an interrupt 4) The event from #1 goes away 5) bcm7120_l2_intc_irq_handle() reads back a 0 status Unlike the hardware supported by brcmstb-l2, the bcm7120-l2 controller does not latch the IRQ status. Bits can change if the inputs to the controller change. Also, do_bad_IRQ() is an ARM-specific macro. So let's just nuke it. Signed-off-by: Kevin Cernekee Acked-by: Florian Fainelli Acked-by: Arnd Bergmann Link: https://lkml.kernel.org/r/1415342669-30640-7-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- drivers/irqchip/irq-bcm7120-l2.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index b9f4fb808e49..7086fe0adae0 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -27,8 +27,6 @@ #include "irqchip.h" -#include - /* Register offset in the L2 interrupt controller */ #define IRQEN 0x00 #define IRQSTAT 0x04 @@ -51,19 +49,12 @@ static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc) chained_irq_enter(chip, desc); status = __raw_readl(b->base + IRQSTAT); - - if (status == 0) { - do_bad_IRQ(irq, desc); - goto out; - } - - do { + while (status) { irq = ffs(status) - 1; status &= ~(1 << irq); generic_handle_irq(irq_find_mapping(b->domain, irq)); - } while (status); + } -out: chained_irq_exit(chip, desc); } -- cgit v1.2.3 From 38e3a6e819b64b257a28df6db25a2d008831a2a3 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:23 -0800 Subject: irqchip: bcm7120-l2: Make sure all register accesses use base+offset A couple of accesses to IRQEN (base+0x00) just used "base" directly, so they would break if IRQEN ever became nonzero. Make sure that all reads/writes specify the register offset constant. Signed-off-by: Kevin Cernekee Acked-by: Florian Fainelli Acked-by: Arnd Bergmann Link: https://lkml.kernel.org/r/1415342669-30640-9-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- drivers/irqchip/irq-bcm7120-l2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index 7086fe0adae0..22d3fa1815c7 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -66,10 +66,10 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d) irq_gc_lock(gc); /* Save the current mask and the interrupt forward mask */ - b->saved_mask = __raw_readl(b->base) | b->irq_fwd_mask; + b->saved_mask = __raw_readl(b->base + IRQEN) | b->irq_fwd_mask; if (b->can_wake) { reg = b->saved_mask | gc->wake_active; - __raw_writel(reg, b->base); + __raw_writel(reg, b->base + IRQEN); } irq_gc_unlock(gc); } @@ -81,7 +81,7 @@ static void bcm7120_l2_intc_resume(struct irq_data *d) /* Restore the saved mask */ irq_gc_lock(gc); - __raw_writel(b->saved_mask, b->base); + __raw_writel(b->saved_mask, b->base + IRQEN); irq_gc_unlock(gc); } -- cgit v1.2.3 From 0b5cb32ca5aea14bfcfda380e5da67b0abf35b4b Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:24 -0800 Subject: irqchip: bcm7120-l2: Fix missing nibble in gc->unused mask This mask should have been 0xffff_ffff, not 0x0fff_ffff. The change should not have an effect on current users (STB) because bits 31:27 are unused. Signed-off-by: Kevin Cernekee Acked-by: Arnd Bergmann Acked-by: Florian Fainelli Link: https://lkml.kernel.org/r/1415342669-30640-10-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- drivers/irqchip/irq-bcm7120-l2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index 22d3fa1815c7..b70679f8bb65 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -171,7 +171,7 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, } gc = irq_get_domain_generic_chip(data->domain, 0); - gc->unused = 0xfffffff & ~data->irq_map_mask; + gc->unused = 0xffffffff & ~data->irq_map_mask; gc->reg_base = data->base; gc->private = data; ct = gc->chip_types; -- cgit v1.2.3 From 05b8ce8260b069b0d59516711e2795758f203556 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:25 -0800 Subject: irqchip: bcm7120-l2: Use gc->mask_cache to simplify suspend/resume functions The cached value already incorporates irq_fwd_mask, and was saved the last time an IRQ was enabled/disabled. Signed-off-by: Kevin Cernekee Acked-by: Florian Fainelli Acked-by: Arnd Bergmann Link: https://lkml.kernel.org/r/1415342669-30640-11-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- drivers/irqchip/irq-bcm7120-l2.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index b70679f8bb65..984112112042 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -37,7 +37,6 @@ struct bcm7120_l2_intc_data { bool can_wake; u32 irq_fwd_mask; u32 irq_map_mask; - u32 saved_mask; }; static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc) @@ -62,14 +61,11 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); struct bcm7120_l2_intc_data *b = gc->private; - u32 reg; irq_gc_lock(gc); - /* Save the current mask and the interrupt forward mask */ - b->saved_mask = __raw_readl(b->base + IRQEN) | b->irq_fwd_mask; if (b->can_wake) { - reg = b->saved_mask | gc->wake_active; - __raw_writel(reg, b->base + IRQEN); + __raw_writel(gc->mask_cache | gc->wake_active, + b->base + IRQEN); } irq_gc_unlock(gc); } @@ -77,11 +73,10 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d) static void bcm7120_l2_intc_resume(struct irq_data *d) { struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); - struct bcm7120_l2_intc_data *b = gc->private; /* Restore the saved mask */ irq_gc_lock(gc); - __raw_writel(b->saved_mask, b->base + IRQEN); + __raw_writel(gc->mask_cache, b->base + IRQEN); irq_gc_unlock(gc); } -- cgit v1.2.3 From c76acf4dffa3232711b5364d7a29746df590f3db Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:26 -0800 Subject: irqchip: bcm7120-l2: Extend driver to support 64+ bit controllers Most implementations of the bcm7120-l2 controller only have a single 32-bit enable word + 32-bit status word. But some instances have added more enable/status pairs in order to support 64+ IRQs (which are all ORed into one parent IRQ input). Make the following changes to allow the driver to support this: - Extend DT bindings so that multiple words can be specified for the reg property, various masks, etc. - Add loops to the probe/handle functions to deal with each word separately - Allocate 1 generic-chip for every 32 IRQs, so we can still use the clr/set helper functions - Update the documentation This uses one domain per bcm7120-l2 DT node. If the DT node defines multiple enable/status pairs (i.e. >=64 IRQs) then the driver will create a single IRQ domain with 2+ generic chips. Multiple generic chips are required because the generic-chip code can only handle one enable/status register pair per instance. Signed-off-by: Kevin Cernekee Acked-by: Arnd Bergmann Link: https://lkml.kernel.org/r/1415342669-30640-12-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- .../interrupt-controller/brcm,bcm7120-l2-intc.txt | 26 ++-- drivers/irqchip/irq-bcm7120-l2.c | 144 ++++++++++++++------- 2 files changed, 113 insertions(+), 57 deletions(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt index ff812a8a82bc..bae1f2187226 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt @@ -13,7 +13,12 @@ Such an interrupt controller has the following hardware design: or if they will output an interrupt signal at this 2nd level interrupt controller, in particular for UARTs -- not all 32-bits within the interrupt controller actually map to an interrupt +- typically has one 32-bit enable word and one 32-bit status word, but on + some hardware may have more than one enable/status pair + +- no atomic set/clear operations + +- not all bits within the interrupt controller actually map to an interrupt The typical hardware layout for this controller is represented below: @@ -48,7 +53,9 @@ The typical hardware layout for this controller is represented below: Required properties: - compatible: should be "brcm,bcm7120-l2-intc" -- reg: specifies the base physical address and size of the registers +- reg: specifies the base physical address and size of the registers; + multiple pairs may be specified, with the first pair handling IRQ offsets + 0..31 and the second pair handling 32..63 - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an interrupt source, should be 1. @@ -59,18 +66,21 @@ Required properties: - brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts are wired to this 2nd level interrupt controller, and how they match their respective interrupt parents. Should match exactly the number of interrupts - specified in the 'interrupts' property. + specified in the 'interrupts' property, multiplied by the number of + enable/status register pairs implemented by this controller. For + multiple parent IRQs with multiple enable/status words, this looks like: + Optional properties: - brcm,irq-can-wake: if present, this means the L2 controller can be used as a wakeup source for system suspend/resume. -- brcm,int-fwd-mask: if present, a 32-bits bit mask to configure for the - interrupts which have a mux gate, typically UARTs. Setting these bits will - make their respective interrupts outputs bypass this 2nd level interrupt - controller completely, it completely transparent for the interrupt controller - parent +- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which + have a mux gate, typically UARTs. Setting these bits will make their + respective interrupt outputs bypass this 2nd level interrupt controller + completely; it is completely transparent for the interrupt controller + parent. This should have one 32-bit word per enable/status pair. Example: diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index 984112112042..ef4d32cf267f 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "irqchip.h" @@ -31,27 +32,42 @@ #define IRQEN 0x00 #define IRQSTAT 0x04 +#define MAX_WORDS 4 +#define IRQS_PER_WORD 32 + struct bcm7120_l2_intc_data { - void __iomem *base; + unsigned int n_words; + void __iomem *base[MAX_WORDS]; struct irq_domain *domain; bool can_wake; - u32 irq_fwd_mask; - u32 irq_map_mask; + u32 irq_fwd_mask[MAX_WORDS]; + u32 irq_map_mask[MAX_WORDS]; }; static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc) { struct bcm7120_l2_intc_data *b = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); - u32 status; + unsigned int idx; chained_irq_enter(chip, desc); - status = __raw_readl(b->base + IRQSTAT); - while (status) { - irq = ffs(status) - 1; - status &= ~(1 << irq); - generic_handle_irq(irq_find_mapping(b->domain, irq)); + for (idx = 0; idx < b->n_words; idx++) { + int base = idx * IRQS_PER_WORD; + struct irq_chip_generic *gc = + irq_get_domain_generic_chip(b->domain, base); + unsigned long pending; + int hwirq; + + irq_gc_lock(gc); + pending = __raw_readl(b->base[idx] + IRQSTAT) & + gc->mask_cache; + irq_gc_unlock(gc); + + for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) { + generic_handle_irq(irq_find_mapping(b->domain, + base + hwirq)); + } } chained_irq_exit(chip, desc); @@ -65,7 +81,7 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d) irq_gc_lock(gc); if (b->can_wake) { __raw_writel(gc->mask_cache | gc->wake_active, - b->base + IRQEN); + gc->reg_base + IRQEN); } irq_gc_unlock(gc); } @@ -76,7 +92,7 @@ static void bcm7120_l2_intc_resume(struct irq_data *d) /* Restore the saved mask */ irq_gc_lock(gc); - __raw_writel(gc->mask_cache, b->base + IRQEN); + __raw_writel(gc->mask_cache, gc->reg_base + IRQEN); irq_gc_unlock(gc); } @@ -85,6 +101,7 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn, int irq, const __be32 *map_mask) { int parent_irq; + unsigned int idx; parent_irq = irq_of_parse_and_map(dn, irq); if (parent_irq < 0) { @@ -92,7 +109,12 @@ static int bcm7120_l2_intc_init_one(struct device_node *dn, return parent_irq; } - data->irq_map_mask |= be32_to_cpup(map_mask + irq); + /* For multiple parent IRQs with multiple words, this looks like: + * + */ + for (idx = 0; idx < data->n_words; idx++) + data->irq_map_mask[idx] |= + be32_to_cpup(map_mask + irq * data->n_words + idx); irq_set_handler_data(parent_irq, data); irq_set_chained_handler(parent_irq, bcm7120_l2_intc_irq_handle); @@ -109,26 +131,41 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, struct irq_chip_type *ct; const __be32 *map_mask; int num_parent_irqs; - int ret = 0, len, irq; + int ret = 0, len; + unsigned int idx, irq; data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - data->base = of_iomap(dn, 0); - if (!data->base) { + for (idx = 0; idx < MAX_WORDS; idx++) { + data->base[idx] = of_iomap(dn, idx); + if (!data->base[idx]) + break; + data->n_words = idx + 1; + } + if (!data->n_words) { pr_err("failed to remap intc L2 registers\n"); ret = -ENOMEM; - goto out_free; + goto out_unmap; } - if (of_property_read_u32(dn, "brcm,int-fwd-mask", &data->irq_fwd_mask)) - data->irq_fwd_mask = 0; - - /* Enable all interrupt specified in the interrupt forward mask and have - * the other disabled + /* Enable all interrupts specified in the interrupt forward mask; + * disable all others. If the property doesn't exist (-EINVAL), + * assume all zeroes. */ - __raw_writel(data->irq_fwd_mask, data->base + IRQEN); + ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask", + data->irq_fwd_mask, data->n_words); + if (ret == 0 || ret == -EINVAL) { + for (idx = 0; idx < data->n_words; idx++) + __raw_writel(data->irq_fwd_mask[idx], + data->base[idx] + IRQEN); + } else { + /* property exists but has the wrong number of words */ + pr_err("invalid int-fwd-mask property\n"); + ret = -EINVAL; + goto out_unmap; + } num_parent_irqs = of_irq_count(dn); if (num_parent_irqs <= 0) { @@ -138,7 +175,8 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, } map_mask = of_get_property(dn, "brcm,int-map-mask", &len); - if (!map_mask || (len != (sizeof(*map_mask) * num_parent_irqs))) { + if (!map_mask || + (len != (sizeof(*map_mask) * num_parent_irqs * data->n_words))) { pr_err("invalid brcm,int-map-mask property\n"); ret = -EINVAL; goto out_unmap; @@ -150,14 +188,14 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, goto out_unmap; } - data->domain = irq_domain_add_linear(dn, 32, - &irq_generic_chip_ops, NULL); + data->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * data->n_words, + &irq_generic_chip_ops, NULL); if (!data->domain) { ret = -ENOMEM; goto out_unmap; } - ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, + ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1, dn->full_name, handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); if (ret) { @@ -165,39 +203,47 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, goto out_free_domain; } - gc = irq_get_domain_generic_chip(data->domain, 0); - gc->unused = 0xffffffff & ~data->irq_map_mask; - gc->reg_base = data->base; - gc->private = data; - ct = gc->chip_types; - - ct->regs.mask = IRQEN; - ct->chip.irq_mask = irq_gc_mask_clr_bit; - ct->chip.irq_unmask = irq_gc_mask_set_bit; - ct->chip.irq_ack = irq_gc_noop; - ct->chip.irq_suspend = bcm7120_l2_intc_suspend; - ct->chip.irq_resume = bcm7120_l2_intc_resume; - - if (of_property_read_bool(dn, "brcm,irq-can-wake")) { + if (of_property_read_bool(dn, "brcm,irq-can-wake")) data->can_wake = true; - /* This IRQ chip can wake the system, set all relevant child - * interupts in wake_enabled mask - */ - gc->wake_enabled = 0xffffffff; - gc->wake_enabled &= ~gc->unused; - ct->chip.irq_set_wake = irq_gc_set_wake; + + for (idx = 0; idx < data->n_words; idx++) { + irq = idx * IRQS_PER_WORD; + gc = irq_get_domain_generic_chip(data->domain, irq); + + gc->unused = 0xffffffff & ~data->irq_map_mask[idx]; + gc->reg_base = data->base[idx]; + gc->private = data; + ct = gc->chip_types; + + ct->regs.mask = IRQEN; + ct->chip.irq_mask = irq_gc_mask_clr_bit; + ct->chip.irq_unmask = irq_gc_mask_set_bit; + ct->chip.irq_ack = irq_gc_noop; + ct->chip.irq_suspend = bcm7120_l2_intc_suspend; + ct->chip.irq_resume = bcm7120_l2_intc_resume; + + if (data->can_wake) { + /* This IRQ chip can wake the system, set all + * relevant child interupts in wake_enabled mask + */ + gc->wake_enabled = 0xffffffff; + gc->wake_enabled &= ~gc->unused; + ct->chip.irq_set_wake = irq_gc_set_wake; + } } pr_info("registered BCM7120 L2 intc (mem: 0x%p, parent IRQ(s): %d)\n", - data->base, num_parent_irqs); + data->base[0], num_parent_irqs); return 0; out_free_domain: irq_domain_remove(data->domain); out_unmap: - iounmap(data->base); -out_free: + for (idx = 0; idx < MAX_WORDS; idx++) { + if (data->base[idx]) + iounmap(data->base[idx]); + } kfree(data); return ret; } -- cgit v1.2.3 From a4fcbb8614010ab93e9865607582337791f9be80 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:27 -0800 Subject: irqchip: bcm7120-l2: Decouple driver from brcmstb-l2 Some chips, such as BCM6328, only require bcm7120-l2. Some BCM7xxx STB configurations only require brcmstb-l2. Treat them as two separate entities, and update the mach-bcm dependencies to reflect the change. Signed-off-by: Kevin Cernekee Acked-by: Arnd Bergmann Acked-by: Florian Fainelli Link: https://lkml.kernel.org/r/1415342669-30640-13-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- arch/arm/mach-bcm/Kconfig | 1 + drivers/irqchip/Kconfig | 5 +++++ drivers/irqchip/Makefile | 4 ++-- drivers/irqchip/irq-bcm7120-l2.c | 2 +- 4 files changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 2abad742516d..bf47eb09ff7d 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -125,6 +125,7 @@ config ARCH_BRCMSTB select HAVE_ARM_ARCH_TIMER select BRCMSTB_GISB_ARB select BRCMSTB_L2_IRQ + select BCM7120_L2_IRQ help Say Y if you intend to run the kernel on a Broadcom ARM-based STB chipset. diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 038b59e55b8a..9efe5f10f97b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -48,6 +48,11 @@ config ATMEL_AIC5_IRQ select MULTI_IRQ_HANDLER select SPARSE_IRQ +config BCM7120_L2_IRQ + bool + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + config BRCMSTB_L2_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 173bb5fa2cc9..f0909d05eae3 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -35,6 +35,6 @@ obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o -obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o \ - irq-bcm7120-l2.o +obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o +obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index ef4d32cf267f..e53a3a629a06 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -247,5 +247,5 @@ out_unmap: kfree(data); return ret; } -IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,bcm7120-l2-intc", +IRQCHIP_DECLARE(bcm7120_l2_intc, "brcm,bcm7120-l2-intc", bcm7120_l2_intc_of_init); -- cgit v1.2.3 From c17261fac3874767bf5478ffb27b843ac66d1f5d Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Thu, 6 Nov 2014 22:44:28 -0800 Subject: irqchip: bcm7120-l2: Convert driver to use irq_reg_{readl,writel} On BE MIPS systems this needs to use the new IRQ_GC_BE_IO gc_flag. In all other cases it will use the standard readl/writel accessors. The initial irq_fwd_mask setup runs before "gc" is initialized, so it is unchanged for now. This could potentially be a problem on an ARM system that boots in LE mode but runs a BE kernel, but currently none of the supported ARM platforms are ever expected to run BE. Signed-off-by: Kevin Cernekee Acked-by: Arnd Bergmann Link: https://lkml.kernel.org/r/1415342669-30640-14-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper --- drivers/irqchip/irq-bcm7120-l2.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'drivers/irqchip/irq-bcm7120-l2.c') diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index e53a3a629a06..e7c6155b23b8 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -60,8 +61,7 @@ static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc) int hwirq; irq_gc_lock(gc); - pending = __raw_readl(b->base[idx] + IRQSTAT) & - gc->mask_cache; + pending = irq_reg_readl(gc, IRQSTAT) & gc->mask_cache; irq_gc_unlock(gc); for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) { @@ -79,10 +79,8 @@ static void bcm7120_l2_intc_suspend(struct irq_data *d) struct bcm7120_l2_intc_data *b = gc->private; irq_gc_lock(gc); - if (b->can_wake) { - __raw_writel(gc->mask_cache | gc->wake_active, - gc->reg_base + IRQEN); - } + if (b->can_wake) + irq_reg_writel(gc, gc->mask_cache | gc->wake_active, IRQEN); irq_gc_unlock(gc); } @@ -92,7 +90,7 @@ static void bcm7120_l2_intc_resume(struct irq_data *d) /* Restore the saved mask */ irq_gc_lock(gc); - __raw_writel(gc->mask_cache, gc->reg_base + IRQEN); + irq_reg_writel(gc, gc->mask_cache, IRQEN); irq_gc_unlock(gc); } @@ -132,7 +130,7 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, const __be32 *map_mask; int num_parent_irqs; int ret = 0, len; - unsigned int idx, irq; + unsigned int idx, irq, flags; data = kzalloc(sizeof(*data), GFP_KERNEL); if (!data) @@ -195,9 +193,15 @@ int __init bcm7120_l2_intc_of_init(struct device_node *dn, goto out_unmap; } + /* MIPS chips strapped for BE will automagically configure the + * peripheral registers for CPU-native byte order. + */ + flags = IRQ_GC_INIT_MASK_CACHE; + if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + flags |= IRQ_GC_BE_IO; + ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1, - dn->full_name, handle_level_irq, clr, 0, - IRQ_GC_INIT_MASK_CACHE); + dn->full_name, handle_level_irq, clr, 0, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; -- cgit v1.2.3