From 45c1da501fc5051fb04f579692f5f0a7d3b0ffbe Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 15 Oct 2015 09:36:34 +0200 Subject: drm/radeon: Use rdev->gem.mutex to protect hyperz/cmask owners MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This removes the last depency of radeon for dev->struct_mutex! Also the locking scheme for hyperz/cmask owners seems a bit unsound, there's no protection in the preclose handler (and that never did hold dev->struct_mutex while being called). So grab the same lock there, too. There's also all the checks in the cs checker, but since the overall design seems to never stall for the previous owner I figured it's ok if I leave this racy. It was racy even before I touched it after all too. Reviewed-by: Christian König Signed-off-by: Daniel Vetter Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/radeon_kms.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 977f1a5e11a5..0a68e8d711a1 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -181,7 +181,9 @@ static void radeon_set_filp_rights(struct drm_device *dev, struct drm_file *applier, uint32_t *value) { - mutex_lock(&dev->struct_mutex); + struct radeon_device *rdev = dev->dev_private; + + mutex_lock(&rdev->gem.mutex); if (*value == 1) { /* wants rights */ if (!*owner) @@ -192,7 +194,7 @@ static void radeon_set_filp_rights(struct drm_device *dev, *owner = NULL; } *value = *owner == applier ? 1 : 0; - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&rdev->gem.mutex); } /* @@ -724,10 +726,14 @@ void radeon_driver_preclose_kms(struct drm_device *dev, struct drm_file *file_priv) { struct radeon_device *rdev = dev->dev_private; + + mutex_lock(&rdev->gem.mutex); if (rdev->hyperz_filp == file_priv) rdev->hyperz_filp = NULL; if (rdev->cmask_filp == file_priv) rdev->cmask_filp = NULL; + mutex_unlock(&rdev->gem.mutex); + radeon_uvd_free_handles(rdev, file_priv); radeon_vce_free_handles(rdev, file_priv); } -- cgit v1.2.3 From a3d5aaa836ed993747af7b53cfca1b3cd3c9fc46 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Oct 2015 18:20:45 -0400 Subject: drm/amdgpu/gfx8: set TC_WB_ACTION_EN in RELEASE_MEM packet MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is the recommended setting from the hw team for newer versions of the firmware. Reviewed-by: Christian König Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 718250ae9856..7dd7651b0ba7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4114,6 +4114,7 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | + EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5))); amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); -- cgit v1.2.3 From f9fff064bb83c55b3fc6291e3b59e3bc78fedddf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Oct 2015 16:53:27 -0400 Subject: drm/amdgpu/dce: simplify suspend/resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We were basically opencoding the same thing in both hw_init and resume and hw_fini and suspend. Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 15 ++++----------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 17 +++++------------ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 15 +++++---------- 3 files changed, 14 insertions(+), 33 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 37073930e2c9..a6ea2d8e85df 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -3086,22 +3086,18 @@ static int dce_v10_0_suspend(void *handle) amdgpu_atombios_scratch_regs_save(adev); - dce_v10_0_hpd_fini(adev); - - return 0; + return dce_v10_0_hw_fini(handle); } static int dce_v10_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; - dce_v10_0_init_golden_registers(adev); + ret = dce_v10_0_hw_init(handle); amdgpu_atombios_scratch_regs_restore(adev); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); /* turn on the BL */ if (adev->mode_info.bl_encoder) { u8 bl_level = amdgpu_display_backlight_get_level(adev, @@ -3110,10 +3106,7 @@ static int dce_v10_0_resume(void *handle) bl_level); } - /* initialize hpd */ - dce_v10_0_hpd_init(adev); - - return 0; + return ret; } static bool dce_v10_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index c1147ecff1ee..bdafeb282a59 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3028,6 +3028,7 @@ static int dce_v11_0_hw_init(void *handle) dce_v11_0_init_golden_registers(adev); /* init dig PHYs, disp eng pll */ + amdgpu_atombios_crtc_powergate_init(adev); amdgpu_atombios_encoder_init_dig(adev); amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); @@ -3061,23 +3062,18 @@ static int dce_v11_0_suspend(void *handle) amdgpu_atombios_scratch_regs_save(adev); - dce_v11_0_hpd_fini(adev); - - return 0; + return dce_v11_0_hw_fini(handle); } static int dce_v11_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; - dce_v11_0_init_golden_registers(adev); + ret = dce_v11_0_hw_init(handle); amdgpu_atombios_scratch_regs_restore(adev); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_crtc_powergate_init(adev); - amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); /* turn on the BL */ if (adev->mode_info.bl_encoder) { u8 bl_level = amdgpu_display_backlight_get_level(adev, @@ -3086,10 +3082,7 @@ static int dce_v11_0_resume(void *handle) bl_level); } - /* initialize hpd */ - dce_v11_0_hpd_init(adev); - - return 0; + return ret; } static bool dce_v11_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index d784fb43efc2..00c34f87ac20 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2994,20 +2994,18 @@ static int dce_v8_0_suspend(void *handle) amdgpu_atombios_scratch_regs_save(adev); - dce_v8_0_hpd_fini(adev); - - return 0; + return dce_v8_0_hw_fini(handle); } static int dce_v8_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + ret = dce_v8_0_hw_init(handle); amdgpu_atombios_scratch_regs_restore(adev); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); /* turn on the BL */ if (adev->mode_info.bl_encoder) { u8 bl_level = amdgpu_display_backlight_get_level(adev, @@ -3016,10 +3014,7 @@ static int dce_v8_0_resume(void *handle) bl_level); } - /* initialize hpd */ - dce_v8_0_hpd_init(adev); - - return 0; + return ret; } static bool dce_v8_0_is_idle(void *handle) -- cgit v1.2.3 From d0be9f4ec1c4ad8a8b6be1efa5bc81e5bce957a3 Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Sun, 18 Oct 2015 23:29:48 +0800 Subject: drm: fix trivial typos s/regsiter/register/ Signed-off-by: Geliang Tang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atombios.h | 2 +- drivers/gpu/drm/radeon/cayman_blit_shaders.c | 2 +- drivers/gpu/drm/radeon/evergreen_blit_shaders.c | 2 +- drivers/gpu/drm/radeon/r600_blit_shaders.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index 44c5d4a4d1bf..552622675ace 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -6784,7 +6784,7 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 ULONG ulMCUcodeRomStartAddr; ULONG ulMCUcodeLength; USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. - USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY regsiter setting + USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting }ATOM_MC_INIT_PARAM_TABLE_V2_1; diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c index 98d009e154bf..9fec4d09f383 100644 --- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c +++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c @@ -32,7 +32,7 @@ * evergreen cards need to use the 3D engine to blit data which requires * quite a bit of hw state setup. Rather than pull the whole 3D driver * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The regsiter state and shaders + * statically generated state tables. The register state and shaders * were hand generated to support blitting functionality. See the 3D * driver or documentation for descriptions of the registers and * shader instructions. diff --git a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c index d43383470cdf..1a96ddb3e5ed 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c @@ -32,7 +32,7 @@ * evergreen cards need to use the 3D engine to blit data which requires * quite a bit of hw state setup. Rather than pull the whole 3D driver * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The regsiter state and shaders + * statically generated state tables. The register state and shaders * were hand generated to support blitting functionality. See the 3D * driver or documentation for descriptions of the registers and * shader instructions. diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c index 34c8b2340f33..443cbe59b274 100644 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c @@ -32,7 +32,7 @@ * R6xx+ cards need to use the 3D engine to blit data which requires * quite a bit of hw state setup. Rather than pull the whole 3D driver * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The regsiter state and shaders + * statically generated state tables. The register state and shaders * were hand generated to support blitting functionality. See the 3D * driver or documentation for descriptions of the registers and * shader instructions. -- cgit v1.2.3 From b7e4dad3e1fc5d3909737fb72e57aedeb0072c7f Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 1 Sep 2015 10:50:26 +0200 Subject: drm/amdgpu: remove old lockup detection infrastructure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It didn't worked to well anyway. Signed-off-by: Christian König Reviewed-by: Chunming Zhou Reviewed-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 20 +------------- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 43 ------------------------------ drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 19 ------------- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 20 -------------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 11 -------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 19 ------------- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 19 ------------- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 - drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 - drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 - 15 files changed, 1 insertion(+), 169 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 736eb4560fd5..911d67032d57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -345,7 +345,6 @@ struct amdgpu_ring_funcs { /* testing functions */ int (*test_ring)(struct amdgpu_ring *ring); int (*test_ib)(struct amdgpu_ring *ring); - bool (*is_lockup)(struct amdgpu_ring *ring); /* insert NOP packets */ void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); }; @@ -907,8 +906,6 @@ struct amdgpu_ring { unsigned ring_size; unsigned ring_free_dw; int count_dw; - atomic_t last_rptr; - atomic64_t last_activity; uint64_t gpu_addr; uint32_t align_mask; uint32_t ptr_mask; @@ -1230,8 +1227,6 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring); void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); -void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); -bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, uint32_t **data); int amdgpu_ring_restore(struct amdgpu_ring *ring, @@ -1974,7 +1969,6 @@ struct amdgpu_device { bool suspend; bool need_dma32; bool accel_working; - bool needs_reset; struct work_struct reset_work; struct notifier_block acpi_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; @@ -2253,7 +2247,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) -#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 901a460b2c55..28c9ee334dd7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1816,12 +1816,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) down_write(&adev->exclusive_lock); - if (!adev->needs_reset) { - up_write(&adev->exclusive_lock); - return 0; - } - - adev->needs_reset = false; atomic_inc(&adev->gpu_reset_counter); /* block TTM */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index fcad7e060938..4010aa6b4e53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -269,17 +269,6 @@ static void amdgpu_fence_check_lockup(struct work_struct *work) if (amdgpu_fence_activity(ring)) { wake_up_all(&ring->fence_drv.fence_queue); } - else if (amdgpu_ring_is_lockup(ring)) { - /* good news we believe it's a lockup */ - dev_warn(ring->adev->dev, "GPU lockup (current fence id " - "0x%016llx last fence id 0x%016llx on ring %d)\n", - (uint64_t)atomic64_read(&fence_drv->last_seq), - fence_drv->sync_seq[ring->idx], ring->idx); - - /* remember that we need an reset */ - ring->adev->needs_reset = true; - wake_up_all(&ring->fence_drv.fence_queue); - } up_read(&ring->adev->exclusive_lock); } @@ -380,7 +369,6 @@ static bool amdgpu_fence_enable_signaling(struct fence *f) */ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) { - struct amdgpu_device *adev = ring->adev; bool signaled = false; BUG_ON(!ring); @@ -391,8 +379,7 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) return 0; wait_event(ring->fence_drv.fence_queue, ( - (signaled = amdgpu_fence_seq_signaled(ring, seq)) - || adev->needs_reset)); + (signaled = amdgpu_fence_seq_signaled(ring, seq)))); if (signaled) return 0; @@ -939,11 +926,6 @@ signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, if (amdgpu_test_signaled_any(array, count)) break; - if (adev->needs_reset) { - t = -EDEADLK; - break; - } - t = schedule_timeout(t); if (t > 0 && intr && signal_pending(current)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index c439735ee670..aad4c1c69448 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -298,7 +298,6 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev) r = amdgpu_ring_test_ib(ring); if (r) { ring->ready = false; - adev->needs_reset = false; if (ring == &adev->gfx.gfx_ring[0]) { /* oh, oh, that's really bad */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index b13a74b273a6..b2df348aa223 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -67,8 +67,6 @@ void amdgpu_ring_free_size(struct amdgpu_ring *ring) if (!ring->ring_free_dw) { /* this is an empty ring */ ring->ring_free_dw = ring->ring_size / 4; - /* update lockup info to avoid false positive */ - amdgpu_ring_lockup_update(ring); } } @@ -208,46 +206,6 @@ void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring) mutex_unlock(ring->ring_lock); } -/** - * amdgpu_ring_lockup_update - update lockup variables - * - * @ring: amdgpu_ring structure holding ring information - * - * Update the last rptr value and timestamp (all asics). - */ -void amdgpu_ring_lockup_update(struct amdgpu_ring *ring) -{ - atomic_set(&ring->last_rptr, amdgpu_ring_get_rptr(ring)); - atomic64_set(&ring->last_activity, jiffies_64); -} - -/** - * amdgpu_ring_test_lockup() - check if ring is lockedup by recording information - * @ring: amdgpu_ring structure holding ring information - * - */ -bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring) -{ - uint32_t rptr = amdgpu_ring_get_rptr(ring); - uint64_t last = atomic64_read(&ring->last_activity); - uint64_t elapsed; - - if (rptr != atomic_read(&ring->last_rptr)) { - /* ring is still working, no lockup */ - amdgpu_ring_lockup_update(ring); - return false; - } - - elapsed = jiffies_to_msecs(jiffies_64 - last); - if (amdgpu_lockup_timeout && elapsed >= amdgpu_lockup_timeout) { - dev_err(ring->adev->dev, "ring %d stalled for more than %llumsec\n", - ring->idx, elapsed); - return true; - } - /* give a chance to the GPU ... */ - return false; -} - /** * amdgpu_ring_backup - Back up the content of a ring * @@ -436,7 +394,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, if (amdgpu_debugfs_ring_init(adev, ring)) { DRM_ERROR("Failed to register debugfs file for rings !\n"); } - amdgpu_ring_lockup_update(ring); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 814598e76c98..5f712ceddf08 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1290,24 +1290,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { .set_powergating_state = cik_sdma_set_powergating_state, }; -/** - * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up - * - * @ring: amdgpu_ring structure holding ring information - * - * Check if the async DMA engine is locked up (CIK). - * Returns true if the engine appears to be locked up, false if not. - */ -static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring) -{ - - if (cik_sdma_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, @@ -1320,7 +1302,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, .test_ring = cik_sdma_ring_test_ring, .test_ib = cik_sdma_ring_test_ib, - .is_lockup = cik_sdma_ring_is_lockup, .insert_nop = cik_sdma_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index e992bf2ff66c..72793f93e2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -5542,24 +5542,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .set_powergating_state = gfx_v7_0_set_powergating_state, }; -/** - * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up - * - * @adev: amdgpu_device pointer - * @ring: amdgpu_ring structure holding ring information - * - * Check if the 3D engine is locked up (CIK). - * Returns true if the engine is locked, false if not. - */ -static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring) -{ - if (gfx_v7_0_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .get_rptr = gfx_v7_0_ring_get_rptr_gfx, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, @@ -5573,7 +5555,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, .test_ring = gfx_v7_0_ring_test_ring, .test_ib = gfx_v7_0_ring_test_ib, - .is_lockup = gfx_v7_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; @@ -5590,7 +5571,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, .test_ring = gfx_v7_0_ring_test_ring, .test_ib = gfx_v7_0_ring_test_ib, - .is_lockup = gfx_v7_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 7dd7651b0ba7..e0355eaddabe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4075,15 +4075,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, } } -static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring) -{ - if (gfx_v8_0_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->rptr_offs]; @@ -4365,7 +4356,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, .test_ring = gfx_v8_0_ring_test_ring, .test_ib = gfx_v8_0_ring_test_ib, - .is_lockup = gfx_v8_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; @@ -4382,7 +4372,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, .test_ring = gfx_v8_0_ring_test_ring, .test_ib = gfx_v8_0_ring_test_ib, - .is_lockup = gfx_v8_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index f8b868c7c496..2cf50180cc51 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -1295,24 +1295,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { .set_powergating_state = sdma_v2_4_set_powergating_state, }; -/** - * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up - * - * @ring: amdgpu_ring structure holding ring information - * - * Check if the async DMA engine is locked up (VI). - * Returns true if the engine appears to be locked up, false if not. - */ -static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring) -{ - - if (sdma_v2_4_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, @@ -1325,7 +1307,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, .test_ring = sdma_v2_4_ring_test_ring, .test_ib = sdma_v2_4_ring_test_ib, - .is_lockup = sdma_v2_4_ring_is_lockup, .insert_nop = sdma_v2_4_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 670555a45da9..0271bf9c0609 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1428,24 +1428,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { .set_powergating_state = sdma_v3_0_set_powergating_state, }; -/** - * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up - * - * @ring: amdgpu_ring structure holding ring information - * - * Check if the async DMA engine is locked up (VI). - * Returns true if the engine appears to be locked up, false if not. - */ -static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring) -{ - - if (sdma_v3_0_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, @@ -1458,7 +1440,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, .test_ring = sdma_v3_0_ring_test_ring, .test_ib = sdma_v3_0_ring_test_ib, - .is_lockup = sdma_v3_0_ring_is_lockup, .insert_nop = sdma_v3_0_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index ed50dd725788..5e9f73af83a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -885,7 +885,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .emit_semaphore = uvd_v4_2_ring_emit_semaphore, .test_ring = uvd_v4_2_ring_test_ring, .test_ib = uvd_v4_2_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 9ad8b9906c0b..38864f562981 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -824,7 +824,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .emit_semaphore = uvd_v5_0_ring_emit_semaphore, .test_ring = uvd_v5_0_ring_test_ring, .test_ib = uvd_v5_0_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 7e9934fa4193..121915bbc3b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -808,7 +808,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { .emit_semaphore = uvd_v6_0_ring_emit_semaphore, .test_ring = uvd_v6_0_ring_test_ring, .test_ib = uvd_v6_0_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index cd16df543f64..52ac7a8f1e58 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -642,7 +642,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .emit_semaphore = amdgpu_vce_ring_emit_semaphore, .test_ring = amdgpu_vce_ring_test_ring, .test_ib = amdgpu_vce_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index f0656dfb53f3..b1bf27bb8f9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -643,7 +643,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = { .emit_semaphore = amdgpu_vce_ring_emit_semaphore, .test_ring = amdgpu_vce_ring_test_ring, .test_ib = amdgpu_vce_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; -- cgit v1.2.3 From 0c418f10104d4aa1d6b83698790898dc9ef1c12d Mon Sep 17 00:00:00 2001 From: Christian König Date: Tue, 1 Sep 2015 15:13:53 +0200 Subject: drm/amdgpu: remove the exclusive lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Finally getting rid of it. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 ++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 7 +------ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 21 +++++---------------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 ------- 6 files changed, 8 insertions(+), 42 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 911d67032d57..39d96088f7b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1955,7 +1955,6 @@ struct amdgpu_device { struct device *dev; struct drm_device *ddev; struct pci_dev *pdev; - struct rw_semaphore exclusive_lock; /* ASIC */ enum amd_asic_type asic_type; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 25012c790f8f..5fdc0394561e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -831,11 +831,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) bool reserved_buffers = false; int i, r; - down_read(&adev->exclusive_lock); - if (!adev->accel_working) { - up_read(&adev->exclusive_lock); + if (!adev->accel_working) return -EBUSY; - } parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); if (!parser) @@ -843,8 +840,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_init(parser, data); if (r) { DRM_ERROR("Failed to initialize parser !\n"); - kfree(parser); - up_read(&adev->exclusive_lock); + amdgpu_cs_parser_fini(parser, r, false); r = amdgpu_cs_handle_lockup(adev, r); return r; } @@ -915,14 +911,12 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) mutex_unlock(&job->job_lock); amdgpu_cs_parser_fini_late(parser); - up_read(&adev->exclusive_lock); return 0; } cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; out: amdgpu_cs_parser_fini(parser, r, reserved_buffers); - up_read(&adev->exclusive_lock); r = amdgpu_cs_handle_lockup(adev, r); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 28c9ee334dd7..19e185ec3707 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1418,7 +1418,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.gpu_clock_mutex); mutex_init(&adev->srbm_mutex); mutex_init(&adev->grbm_idx_mutex); - init_rwsem(&adev->exclusive_lock); mutex_init(&adev->mn_lock); hash_init(adev->mn_hash); @@ -1814,8 +1813,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) int i, r; int resched; - down_write(&adev->exclusive_lock); - atomic_inc(&adev->gpu_reset_counter); /* block TTM */ @@ -1879,7 +1876,6 @@ retry: dev_info(adev->dev, "GPU reset failed\n"); } - up_write(&adev->exclusive_lock); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 9b34a3410c32..fdf7525cf120 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -47,11 +47,8 @@ static void amdgpu_flip_wait_fence(struct amdgpu_device *adev, fence = to_amdgpu_fence(*f); if (fence) { r = fence_wait(&fence->base, false); - if (r == -EDEADLK) { - up_read(&adev->exclusive_lock); + if (r == -EDEADLK) r = amdgpu_gpu_reset(adev); - down_read(&adev->exclusive_lock); - } } else r = fence_wait(*f, false); @@ -77,7 +74,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work) unsigned long flags; unsigned i; - down_read(&adev->exclusive_lock); amdgpu_flip_wait_fence(adev, &work->excl); for (i = 0; i < work->shared_count; ++i) amdgpu_flip_wait_fence(adev, &work->shared[i]); @@ -93,7 +89,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work) amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - up_read(&adev->exclusive_lock); } /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 4010aa6b4e53..1fadc15e64ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -260,16 +260,8 @@ static void amdgpu_fence_check_lockup(struct work_struct *work) lockup_work.work); ring = fence_drv->ring; - if (!down_read_trylock(&ring->adev->exclusive_lock)) { - /* just reschedule the check if a reset is going on */ - amdgpu_fence_schedule_check(ring); - return; - } - - if (amdgpu_fence_activity(ring)) { + if (amdgpu_fence_activity(ring)) wake_up_all(&ring->fence_drv.fence_queue); - } - up_read(&ring->adev->exclusive_lock); } /** @@ -317,18 +309,15 @@ static bool amdgpu_fence_is_signaled(struct fence *f) { struct amdgpu_fence *fence = to_amdgpu_fence(f); struct amdgpu_ring *ring = fence->ring; - struct amdgpu_device *adev = ring->adev; if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) return true; - if (down_read_trylock(&adev->exclusive_lock)) { - amdgpu_fence_process(ring); - up_read(&adev->exclusive_lock); + amdgpu_fence_process(ring); + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return true; - if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) - return true; - } return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 7297ca3a0ba7..d81ab785368a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -181,7 +181,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, bool kernel = false; int r; - down_read(&adev->exclusive_lock); /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { @@ -214,11 +213,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, memset(args, 0, sizeof(*args)); args->out.handle = handle; - up_read(&adev->exclusive_lock); return 0; error_unlock: - up_read(&adev->exclusive_lock); r = amdgpu_gem_handle_lockup(adev, r); return r; } @@ -250,8 +247,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return -EACCES; } - down_read(&adev->exclusive_lock); - /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 0, @@ -293,14 +288,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto handle_lockup; args->handle = handle; - up_read(&adev->exclusive_lock); return 0; release_object: drm_gem_object_unreference_unlocked(gobj); handle_lockup: - up_read(&adev->exclusive_lock); r = amdgpu_gem_handle_lockup(adev, r); return r; -- cgit v1.2.3 From ce16b0e5a32a157abd6446214e8b91c55064204e Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Sun, 6 Sep 2015 13:55:03 +0800 Subject: drm/amdgpu: remove the unnecessary parameter adev for amdgpu_fence_wait_any() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Junwei Zhang Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 9 ++------- drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c | 2 +- 3 files changed, 4 insertions(+), 10 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 39d96088f7b4..a9c0def6ce31 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -447,8 +447,7 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring); int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); -signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, - struct fence **array, +signed long amdgpu_fence_wait_any(struct fence **array, uint32_t count, bool intr, signed long t); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 1fadc15e64ae..003a219943f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -857,16 +857,12 @@ static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb) static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, signed long t) { - struct amdgpu_fence *fence = to_amdgpu_fence(f); - struct amdgpu_device *adev = fence->ring->adev; - - return amdgpu_fence_wait_any(adev, &f, 1, intr, t); + return amdgpu_fence_wait_any(&f, 1, intr, t); } /** * Wait the fence array with timeout * - * @adev: amdgpu device * @array: the fence array with amdgpu fence pointer * @count: the number of the fence array * @intr: when sleep, set the current task interruptable or not @@ -874,8 +870,7 @@ static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, * * It will return when any fence is signaled or timeout. */ -signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, - struct fence **array, uint32_t count, +signed long amdgpu_fence_wait_any(struct fence **array, uint32_t count, bool intr, signed long t) { struct amdgpu_wait_cb *cb; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index e90712443fe9..5cb27d525e43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -372,7 +372,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries)); spin_unlock(&sa_manager->wq.lock); - t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS, + t = amdgpu_fence_wait_any(fences, AMDGPU_MAX_RINGS, false, MAX_SCHEDULE_TIMEOUT); r = (t > 0) ? 0 : t; spin_lock(&sa_manager->wq.lock); -- cgit v1.2.3 From f48b2659f521301753f9b3b67e308a79c6110346 Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Fri, 16 Oct 2015 14:06:19 +0800 Subject: drm/amdgpu: fix the broken vm->mutex V2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix the vm->mutex and ww_mutex confilcts. vm->mutex is always token first, then ww_mutex. V2: remove unneccessary checking for pt bo. Change-Id: Iea56e183752c02831126d06d2f5b7a474a6e4743 Signed-off-by: Chunming Zhou Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 8 +++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 22 ++++++++++----------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 35 +++------------------------------ 3 files changed, 19 insertions(+), 46 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 5fdc0394561e..8727c3099554 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -608,7 +608,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, } } - mutex_lock(&vm->mutex); r = amdgpu_bo_vm_update_pte(parser, vm); if (r) { goto out; @@ -619,7 +618,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, parser->filp); out: - mutex_unlock(&vm->mutex); return r; } @@ -827,6 +825,8 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; union drm_amdgpu_cs *cs = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_cs_parser *parser; bool reserved_buffers = false; int i, r; @@ -844,7 +844,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_handle_lockup(adev, r); return r; } - + mutex_lock(&vm->mutex); r = amdgpu_cs_parser_relocs(parser); if (r == -ENOMEM) DRM_ERROR("Not enough memory for command submission!\n"); @@ -911,12 +911,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) mutex_unlock(&job->job_lock); amdgpu_cs_parser_fini_late(parser); + mutex_unlock(&vm->mutex); return 0; } cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; out: amdgpu_cs_parser_fini(parser, r, reserved_buffers); + mutex_unlock(&vm->mutex); r = amdgpu_cs_handle_lockup(adev, r); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index d81ab785368a..087332858853 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -115,9 +115,10 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; int r; - + mutex_lock(&vm->mutex); r = amdgpu_bo_reserve(rbo, false); if (r) { + mutex_unlock(&vm->mutex); return r; } @@ -128,7 +129,7 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri ++bo_va->ref_count; } amdgpu_bo_unreserve(rbo); - + mutex_unlock(&vm->mutex); return 0; } @@ -141,9 +142,10 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; int r; - + mutex_lock(&vm->mutex); r = amdgpu_bo_reserve(rbo, true); if (r) { + mutex_unlock(&vm->mutex); dev_err(adev->dev, "leaking bo va because " "we fail to reserve bo (%d)\n", r); return; @@ -155,6 +157,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, } } amdgpu_bo_unreserve(rbo); + mutex_unlock(&vm->mutex); } static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) @@ -481,18 +484,13 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, goto error_unreserve; } - mutex_lock(&bo_va->vm->mutex); r = amdgpu_vm_clear_freed(adev, bo_va->vm); if (r) - goto error_unlock; - + goto error_unreserve; if (operation == AMDGPU_VA_OP_MAP) r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); -error_unlock: - mutex_unlock(&bo_va->vm->mutex); - error_unreserve: ttm_eu_backoff_reservation(&ticket, &list); @@ -549,10 +547,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, gobj = drm_gem_object_lookup(dev, filp, args->handle); if (gobj == NULL) return -ENOENT; - + mutex_lock(&fpriv->vm.mutex); rbo = gem_to_amdgpu_bo(gobj); r = amdgpu_bo_reserve(rbo, false); if (r) { + mutex_unlock(&fpriv->vm.mutex); drm_gem_object_unreference_unlocked(gobj); return r; } @@ -560,6 +559,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); if (!bo_va) { amdgpu_bo_unreserve(rbo); + mutex_unlock(&fpriv->vm.mutex); return -ENOENT; } @@ -584,7 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) amdgpu_gem_va_update_vm(adev, bo_va, args->operation); - + mutex_unlock(&fpriv->vm.mutex); drm_gem_object_unreference_unlocked(gobj); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 0675524eb9de..06e207fd007b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -90,11 +90,9 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, struct amdgpu_bo_list_entry *list; unsigned i, idx; - mutex_lock(&vm->mutex); list = drm_malloc_ab(vm->max_pde_used + 2, sizeof(struct amdgpu_bo_list_entry)); if (!list) { - mutex_unlock(&vm->mutex); return NULL; } @@ -119,7 +117,6 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, list[idx].tv.shared = true; list_add(&list[idx++].tv.head, head); } - mutex_unlock(&vm->mutex); return list; } @@ -970,9 +967,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, INIT_LIST_HEAD(&bo_va->invalids); INIT_LIST_HEAD(&bo_va->vm_status); - mutex_lock(&vm->mutex); list_add_tail(&bo_va->bo_list, &bo->va); - mutex_unlock(&vm->mutex); return bo_va; } @@ -1025,8 +1020,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, return -EINVAL; } - mutex_lock(&vm->mutex); - saddr /= AMDGPU_GPU_PAGE_SIZE; eaddr /= AMDGPU_GPU_PAGE_SIZE; @@ -1040,14 +1033,14 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, tmp->it.start, tmp->it.last + 1); amdgpu_bo_unreserve(bo_va->bo); r = -EINVAL; - goto error_unlock; + goto error; } mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); if (!mapping) { amdgpu_bo_unreserve(bo_va->bo); r = -ENOMEM; - goto error_unlock; + goto error; } INIT_LIST_HEAD(&mapping->list); @@ -1079,9 +1072,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, if (vm->page_tables[pt_idx].bo) continue; - /* drop mutex to allocate and clear page table */ - mutex_unlock(&vm->mutex); - ww_mutex_lock(&resv->lock, NULL); r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, AMDGPU_GPU_PAGE_SIZE, true, @@ -1098,32 +1088,19 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, goto error_free; } - /* aquire mutex again */ - mutex_lock(&vm->mutex); - if (vm->page_tables[pt_idx].bo) { - /* someone else allocated the pt in the meantime */ - mutex_unlock(&vm->mutex); - amdgpu_bo_unref(&pt); - mutex_lock(&vm->mutex); - continue; - } - vm->page_tables[pt_idx].addr = 0; vm->page_tables[pt_idx].bo = pt; } - mutex_unlock(&vm->mutex); return 0; error_free: - mutex_lock(&vm->mutex); list_del(&mapping->list); interval_tree_remove(&mapping->it, &vm->va); trace_amdgpu_vm_bo_unmap(bo_va, mapping); kfree(mapping); -error_unlock: - mutex_unlock(&vm->mutex); +error: return r; } @@ -1168,7 +1145,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, } } - mutex_lock(&vm->mutex); list_del(&mapping->list); interval_tree_remove(&mapping->it, &vm->va); trace_amdgpu_vm_bo_unmap(bo_va, mapping); @@ -1177,7 +1153,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, list_add(&mapping->list, &vm->freed); else kfree(mapping); - mutex_unlock(&vm->mutex); amdgpu_bo_unreserve(bo_va->bo); return 0; @@ -1201,8 +1176,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, list_del(&bo_va->bo_list); - mutex_lock(&vm->mutex); - spin_lock(&vm->status_lock); list_del(&bo_va->vm_status); spin_unlock(&vm->status_lock); @@ -1221,8 +1194,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, fence_put(bo_va->last_pt_update); kfree(bo_va); - - mutex_unlock(&vm->mutex); } /** -- cgit v1.2.3 From 139f491799c303c5269cf6d5600cec9bbf9853e6 Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 14:50:27 -0400 Subject: drm/amdgpu: add Stoney chip family Stoney is based on Carrizo with some IP upgrades. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/include/amd_shared.h | 1 + 2 files changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 19e185ec3707..645690bcb4b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -57,6 +57,7 @@ static const char *amdgpu_asic_name[] = { "TONGA", "FIJI", "CARRIZO", + "STONEY", "LAST", }; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 68a8eaa1b7d0..fe28fb353fab 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -47,6 +47,7 @@ enum amd_asic_type { CHIP_TONGA, CHIP_FIJI, CHIP_CARRIZO, + CHIP_STONEY, CHIP_LAST, }; -- cgit v1.2.3 From aade2f04f94aad4ed68a7a77893b300ef9cf25da Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:26:41 -0400 Subject: drm/amdgpu: add GMC support for Stoney Stoney is GMC 8.x. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 42b5ff827055..72e977b1685d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -93,6 +93,12 @@ static const u32 cz_mgcg_cgcg_init[] = mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 +}; + + static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { @@ -125,6 +131,11 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + break; default: break; } @@ -228,6 +239,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) chip_name = "fiji"; break; case CHIP_CARRIZO: + case CHIP_STONEY: return 0; default: BUG(); } -- cgit v1.2.3 From 7a753c3f3474458fa1d0b8f41617e41995bc4c40 Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:28:41 -0400 Subject: drm/amdgpu: Update SMC/DPM for Stoney Stoney is SMC 8.x. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cz_dpm.c | 21 ++++++++++--- drivers/gpu/drm/amd/amdgpu/cz_smc.c | 60 +++++++++++++++++++++++++++++-------- 2 files changed, 65 insertions(+), 16 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 44fa96ad4709..6f244e94c5f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -1262,6 +1262,7 @@ static void cz_apply_state_adjust_rules(struct amdgpu_device *adev, static int cz_dpm_enable(struct amdgpu_device *adev) { + const char *chip_name; int ret = 0; /* renable will hang up SMU, so check first */ @@ -1270,21 +1271,33 @@ static int cz_dpm_enable(struct amdgpu_device *adev) cz_program_voting_clients(adev); + switch (adev->asic_type) { + case CHIP_CARRIZO: + chip_name = "carrizo"; + break; + case CHIP_STONEY: + chip_name = "stoney"; + break; + default: + BUG(); + } + + ret = cz_start_dpm(adev); if (ret) { - DRM_ERROR("Carrizo DPM enable failed\n"); + DRM_ERROR("%s DPM enable failed\n", chip_name); return -EINVAL; } ret = cz_program_bootup_state(adev); if (ret) { - DRM_ERROR("Carrizo bootup state program failed\n"); + DRM_ERROR("%s bootup state program failed\n", chip_name); return -EINVAL; } ret = cz_enable_didt(adev, true); if (ret) { - DRM_ERROR("Carrizo enable di/dt failed\n"); + DRM_ERROR("%s enable di/dt failed\n", chip_name); return -EINVAL; } @@ -1351,7 +1364,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev) ret = cz_enable_didt(adev, false); if (ret) { - DRM_ERROR("Carrizo disable di/dt failed\n"); + DRM_ERROR("disable di/dt failed\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c index e33180d3314a..ac7fee7b7eca 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_smc.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_smc.c @@ -312,13 +312,16 @@ int cz_smu_start(struct amdgpu_device *adev) UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK; + if (adev->asic_type == CHIP_STONEY) + fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); + cz_smu_request_load_fw(adev); ret = cz_smu_check_fw_load_finish(adev, fw_to_check); if (ret) return ret; /* manually load MEC firmware for CZ */ - if (adev->asic_type == CHIP_CARRIZO) { + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { ret = cz_load_mec_firmware(adev); if (ret) { dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret); @@ -336,6 +339,9 @@ int cz_smu_start(struct amdgpu_device *adev) AMDGPU_CPMEC2_UCODE_LOADED | AMDGPU_CPRLC_UCODE_LOADED; + if (adev->asic_type == CHIP_STONEY) + adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED); + return ret; } @@ -601,8 +607,13 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); - cz_smu_populate_single_ucode_load_task(adev, + if (adev->asic_type == CHIP_STONEY) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); + } else { + cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); + } cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); } @@ -642,8 +653,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) if (adev->firmware.smu_load) { cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); - cz_smu_populate_single_ucode_load_task(adev, + if (adev->asic_type == CHIP_STONEY) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); + } else { + cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); + } cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); cz_smu_populate_single_ucode_load_task(adev, @@ -652,8 +668,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); - cz_smu_populate_single_ucode_load_task(adev, + if (adev->asic_type == CHIP_STONEY) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); + } else { + cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); + } cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); } @@ -888,10 +909,18 @@ int cz_smu_init(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, &priv->driver_buffer[priv->driver_buffer_length++])) goto smu_init_failed; - if (cz_smu_populate_single_firmware_entry(adev, - CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, - &priv->driver_buffer[priv->driver_buffer_length++])) - goto smu_init_failed; + + if (adev->asic_type == CHIP_STONEY) { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } else { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } if (cz_smu_populate_single_firmware_entry(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, &priv->driver_buffer[priv->driver_buffer_length++])) @@ -908,10 +937,17 @@ int cz_smu_init(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, &priv->driver_buffer[priv->driver_buffer_length++])) goto smu_init_failed; - if (cz_smu_populate_single_firmware_entry(adev, - CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, - &priv->driver_buffer[priv->driver_buffer_length++])) - goto smu_init_failed; + if (adev->asic_type == CHIP_STONEY) { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } else { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } if (cz_smu_populate_single_firmware_entry(adev, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, &priv->driver_buffer[priv->driver_buffer_length++])) -- cgit v1.2.3 From fa2f9befbbbe239bbc6aa1dc6284841a8bd15d49 Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:29:06 -0400 Subject: drm/amdgpu: add DCE support for Stoney Stoney is DCE 11.x. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index bdafeb282a59..444d930b3317 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -126,6 +126,13 @@ static const u32 cz_mgcg_cgcg_init[] = mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, }; +static const u32 stoney_golden_settings_a11[] = +{ + mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, + mmFBC_MISC, 0x1f311fff, 0x14302000, +}; + + static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { @@ -137,6 +144,11 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + break; default: break; } @@ -2425,7 +2437,7 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) /* XXX need to determine what plls are available on each DCE11 part */ pll_in_use = amdgpu_pll_get_use_mask(crtc); - if (adev->asic_type == CHIP_CARRIZO) { + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { if (!(pll_in_use & (1 << ATOM_PPLL1))) return ATOM_PPLL1; if (!(pll_in_use & (1 << ATOM_PPLL0))) @@ -2930,6 +2942,11 @@ static int dce_v11_0_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; + case CHIP_STONEY: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; + break; default: /* FIXME: not supported yet */ return -EINVAL; -- cgit v1.2.3 From bb16e3b6c8641bdf4765c373ba41543861959cbb Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 17:17:51 -0400 Subject: drm/amdgpu: add SDMA support for Stoney (v2) Stoney is SDMA 3.x. v2: update to latest golden register settings Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 0271bf9c0609..7253132f04b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -55,6 +55,7 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { @@ -122,6 +123,19 @@ static const u32 cz_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; +static const u32 stoney_golden_settings_a11[] = +{ + mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, + mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, +}; + +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, +}; + /* * sDMA - System DMA * Starting with CIK, the GPU has new asynchronous @@ -166,6 +180,14 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + break; default: break; } @@ -201,6 +223,9 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_CARRIZO: chip_name = "carrizo"; break; + case CHIP_STONEY: + chip_name = "stoney"; + break; default: BUG(); } @@ -1071,6 +1096,9 @@ static int sdma_v3_0_early_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; switch (adev->asic_type) { + case CHIP_STONEY: + adev->sdma.num_instances = 1; + break; default: adev->sdma.num_instances = SDMA_MAX_INSTANCE; break; -- cgit v1.2.3 From e3c7656c22697eeef46ce043e23417241844ab1c Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:29:40 -0400 Subject: drm/amdgpu: add GFX support for Stoney (v2) Stoney is GFX 8.1. v2: update to latest golden settings Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 400 ++++++++++++++++++++++++++++++++-- 1 file changed, 382 insertions(+), 18 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index e0355eaddabe..cbc46a34987c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -73,6 +73,12 @@ MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); +MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); +MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); +MODULE_FIRMWARE("amdgpu/stoney_me.bin"); +MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); +MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); + MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); MODULE_FIRMWARE("amdgpu/tonga_me.bin"); @@ -493,6 +499,42 @@ static const u32 cz_mgcg_cgcg_init[] = mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; +static const u32 stoney_golden_settings_a11[] = +{ + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmGB_GPU_ID, 0x0000000f, 0x00000000, + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, + mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, + mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, +}; + +static const u32 stoney_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, + mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, +}; + +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, + mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, + mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, + mmATC_MISC_CG, 0xffffffff, 0x000c0200, +}; + static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); @@ -545,6 +587,17 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_common_all, (const u32)ARRAY_SIZE(cz_golden_common_all)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + amdgpu_program_register_sequence(adev, + stoney_golden_common_all, + (const u32)ARRAY_SIZE(stoney_golden_common_all)); + break; default: break; } @@ -691,6 +744,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; + case CHIP_STONEY: + chip_name = "stoney"; + break; default: BUG(); } @@ -748,21 +804,23 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - cp_hdr = (const struct gfx_firmware_header_v1_0 *) - adev->gfx.mec2_fw->data; - adev->gfx.mec2_fw_version = le32_to_cpu( - cp_hdr->header.ucode_version); - adev->gfx.mec2_feature_version = le32_to_cpu( - cp_hdr->ucode_feature_version); - } else { - err = 0; - adev->gfx.mec2_fw = NULL; + if (adev->asic_type != CHIP_STONEY) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (!err) { + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw_version = + le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.mec2_feature_version = + le32_to_cpu(cp_hdr->ucode_feature_version); + } else { + err = 0; + adev->gfx.mec2_fw = NULL; + } } if (adev->firmware.smu_load) { @@ -1004,6 +1062,40 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.max_gs_threads = 32; adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_STONEY: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 1; + + switch (adev->pdev->revision) { + case 0xc0: + case 0xc1: + case 0xc2: + case 0xc4: + case 0xc8: + case 0xc9: + adev->gfx.config.max_cu_per_sh = 3; + break; + case 0xd0: + case 0xd1: + case 0xd2: + default: + adev->gfx.config.max_cu_per_sh = 2; + break; + } + + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 16; + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; @@ -1797,6 +1889,273 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); } break; + case CHIP_STONEY: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P2)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 7: + case 12: + case 17: + case 23: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 7: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + break; case CHIP_CARRIZO: default: for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { @@ -2384,7 +2743,7 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) WREG32(mmRLC_CNTL, tmp); /* carrizo do enable cp interrupt after cp inited */ - if (adev->asic_type != CHIP_CARRIZO) + if (!(adev->flags & AMD_IS_APU)) gfx_v8_0_enable_gui_idle_interrupt(adev, true); udelay(50); @@ -2606,6 +2965,10 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, 0x00000002); amdgpu_ring_write(ring, 0x00000000); break; + case CHIP_STONEY: + amdgpu_ring_write(ring, 0x00000000); + amdgpu_ring_write(ring, 0x00000000); + break; default: BUG(); } @@ -3240,7 +3603,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) /* enable the doorbell if requested */ if (use_doorbell) { if ((adev->asic_type == CHIP_CARRIZO) || - (adev->asic_type == CHIP_FIJI)) { + (adev->asic_type == CHIP_FIJI) || + (adev->asic_type == CHIP_STONEY)) { WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, @@ -3312,7 +3676,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) { int r; - if (adev->asic_type != CHIP_CARRIZO) + if (!(adev->flags & AMD_IS_APU)) gfx_v8_0_enable_gui_idle_interrupt(adev, false); if (!adev->firmware.smu_load) { -- cgit v1.2.3 From a39c8cea3512bdf9d002edc9142ff35d314a690e Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:27:21 -0400 Subject: drm/amdgpu: add UVD support for Stoney Stoney is UVD 6.x. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index d0312364d950..53f987aeeacf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -53,6 +53,7 @@ #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" +#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -83,6 +84,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS); MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); +MODULE_FIRMWARE(FIRMWARE_STONEY); static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); @@ -124,6 +126,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_CARRIZO: fw_name = FIRMWARE_CARRIZO; break; + case CHIP_STONEY: + fw_name = FIRMWARE_STONEY; + break; default: return -EINVAL; } -- cgit v1.2.3 From cfaba566035d2f5a977b18d3287fd407bacf34bc Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:27:55 -0400 Subject: drm/amdgpu: add VCE support for Stoney (v2) Stoney is VCE 3.x single. v2: Stoney is single pipe like Fiji Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 74f2038ac747..03f0c3bae516 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -49,6 +49,7 @@ #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin" #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" +#define FIRMWARE_STONEY "amdgpu/stoney_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); @@ -60,6 +61,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS); MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); +MODULE_FIRMWARE(FIRMWARE_STONEY); static void amdgpu_vce_idle_work_handler(struct work_struct *work); @@ -106,6 +108,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_FIJI: fw_name = FIRMWARE_FIJI; break; + case CHIP_STONEY: + fw_name = FIRMWARE_STONEY; + break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index b1bf27bb8f9e..6a52db6ad8d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -205,8 +205,9 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) u32 tmp; unsigned ret; - /* Fiji is single pipe */ - if (adev->asic_type == CHIP_FIJI) { + /* Fiji, Stoney are single pipe */ + if ((adev->asic_type == CHIP_FIJI) || + (adev->asic_type == CHIP_STONEY)){ ret = AMDGPU_VCE_HARVEST_VCE1; return ret; } -- cgit v1.2.3 From 39bb0c92829ad9d7525fa809aa89fc411c85a2c2 Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:31:43 -0400 Subject: drm/amdgpu: update the core VI support for Stoney Add core VI enablement for Stoney. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- drivers/gpu/drm/amd/amdgpu/vi.c | 36 +++++++++++++++++++++++++----- include/uapi/drm/amdgpu_drm.h | 2 +- 3 files changed, 34 insertions(+), 7 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 645690bcb4b3..d5b421330145 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1166,7 +1166,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) case CHIP_TONGA: case CHIP_FIJI: case CHIP_CARRIZO: - if (adev->asic_type == CHIP_CARRIZO) + case CHIP_STONEY: + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) adev->family = AMDGPU_FAMILY_CZ; else adev->family = AMDGPU_FAMILY_VI; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index b55ceb14fdcd..9904761c9c37 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -232,6 +232,13 @@ static const u32 cz_mgcg_cgcg_init[] = mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, }; +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, + mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, + mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, +}; + static void vi_init_golden_registers(struct amdgpu_device *adev) { /* Some of the registers might be dependent on GRBM_GFX_INDEX */ @@ -258,6 +265,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + break; default: break; } @@ -488,6 +500,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, case CHIP_FIJI: case CHIP_TONGA: case CHIP_CARRIZO: + case CHIP_STONEY: asic_register_table = cz_allowed_read_registers; size = ARRAY_SIZE(cz_allowed_read_registers); break; @@ -543,8 +556,10 @@ static void vi_print_gpu_status_regs(struct amdgpu_device *adev) RREG32(mmSRBM_STATUS2)); dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); - dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", - RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); + if (adev->sdma.num_instances > 1) { + dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", + RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); + } dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", RREG32(mmCP_STALLED_STAT1)); @@ -639,9 +654,11 @@ u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev) reset_mask |= AMDGPU_RESET_DMA; /* SDMA1_STATUS_REG */ - tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); - if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) - reset_mask |= AMDGPU_RESET_DMA1; + if (adev->sdma.num_instances > 1) { + tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + reset_mask |= AMDGPU_RESET_DMA1; + } #if 0 /* VCE_STATUS */ if (adev->asic_type != CHIP_TOPAZ) { @@ -1316,6 +1333,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); break; case CHIP_CARRIZO: + case CHIP_STONEY: adev->ip_blocks = cz_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); break; @@ -1327,11 +1345,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) return 0; } +#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 +#define ATI_REV_ID_FUSE_MACRO__SHIFT 9 +#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 + static uint32_t vi_get_rev_id(struct amdgpu_device *adev) { if (adev->asic_type == CHIP_TOPAZ) return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; + else if (adev->flags & AMD_IS_APU) + return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) + >> ATI_REV_ID_FUSE_MACRO__SHIFT; else return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; @@ -1398,6 +1423,7 @@ static int vi_common_early_init(void *handle) adev->firmware.smu_load = true; break; case CHIP_CARRIZO: + case CHIP_STONEY: adev->has_uvd = true; adev->cg_flags = 0; /* Disable UVD pg */ diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index fbdd11851725..e52933a73580 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -640,6 +640,6 @@ struct drm_amdgpu_info_hw_ip { #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ -#define AMDGPU_FAMILY_CZ 135 /* Carrizo */ +#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ #endif -- cgit v1.2.3 From 81b1509aa99b968ac19b0aaa451ecd61a996db10 Mon Sep 17 00:00:00 2001 From: Samuel Li Date: Thu, 8 Oct 2015 16:32:03 -0400 Subject: drm/amdgpu: add Stoney pci ids Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6134b1ece17f..c3216bef8cba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -273,6 +273,8 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, + /* stoney */ + {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, {0, 0, 0} }; -- cgit v1.2.3 From ed885b210752563b5e90dc0933e262f768ea9fa4 Mon Sep 17 00:00:00 2001 From: Christian König Date: Thu, 15 Oct 2015 17:34:20 +0200 Subject: drm/amdgpu: change VM size default to 64GB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That's still small enough to not waste to much memory on PD/PTs. Signed-off-by: Christian König Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c3216bef8cba..8d6668cedf6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -73,7 +73,7 @@ int amdgpu_hard_reset = 0; unsigned amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color = 0; -int amdgpu_vm_size = 8; +int amdgpu_vm_size = 64; int amdgpu_vm_block_size = -1; int amdgpu_vm_fault_stop = 0; int amdgpu_vm_debug = 0; @@ -137,7 +137,7 @@ module_param_named(bapm, amdgpu_bapm, int, 0444); MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); module_param_named(deep_color, amdgpu_deep_color, int, 0444); -MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)"); +MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); module_param_named(vm_size, amdgpu_vm_size, int, 0444); MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); -- cgit v1.2.3