From c618a3a93b5a118fcf4afe5fe85e83c190f4b127 Mon Sep 17 00:00:00 2001 From: Venkateswara Rao Mandela Date: Wed, 24 Jan 2018 16:15:09 +0530 Subject: drm/omap: Implement workaround for DRA7 errata ID:i932 Description of DRA7 Errata i932: In rare circumstances DPLL_VIDEO1 and DPLL_VIDEO2 PLL's may not lock on the first attempt during DSS initialization. When this occurs, a subsequent attempt to relock the PLL will result in PLL successfully locking. This patch does the following as per the errata recommendation: - retries locking the PLL upto 20 times. - The time to wait for a PLL lock set to 1000 REFCLK cycles. We use usleep_range to wait for 1000 REFCLK cycles in the us range. This tight constraint is imposed as a lock later than 1000 REFCLK cycles may have high jitter. - Criteria for PLL lock is extended from check on just the PLL_LOCK bit to check on 6 PLL_STATUS bits. Silicon Versions Impacted: DRA71, DRA72, DRA74, DRA76 - All silicon revisions AM57x - All silicon revisions OMAP4/5 are not impacted by this errata Signed-off-by: Venkateswara Rao Mandela [tomi.valkeinen@ti.com: ported to v4.14] Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dss.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/omapdrm/dss/dss.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 847c78ade024..9f9a700bb6d5 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -180,6 +180,9 @@ struct dss_pll_hw { /* DRA7 errata i886: use high N & M to avoid jitter */ bool errata_i886; + + /* DRA7 errata i932: retry pll lock on failure */ + bool errata_i932; }; struct dss_pll { -- cgit v1.2.3