From 8539b37acef73949861a16808b60cb8b5b9b3bab Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 23 Jun 2015 15:16:01 +0900 Subject: drm/nouveau/gr: use NVIDIA-provided external firmwares NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 31 ++++++++++++++++---------- 1 file changed, 19 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index ca11ddb6ed46..454080339572 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1550,18 +1550,25 @@ gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, { struct nvkm_device *device = nv_device(priv); const struct firmware *fw; - char f[32]; + char f[64]; + char cname[16]; int ret; + int i; + + /* Convert device name to lowercase */ + strncpy(cname, device->cname, sizeof(cname)); + cname[sizeof(cname) - 1] = '\0'; + i = strlen(cname); + while (i) { + --i; + cname[i] = tolower(cname[i]); + } - snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); + snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); ret = request_firmware(&fw, f, nv_device_base(device)); if (ret) { - snprintf(f, sizeof(f), "nouveau/%s", fwname); - ret = request_firmware(&fw, f, nv_device_base(device)); - if (ret) { - nv_error(priv, "failed to load %s\n", fwname); - return ret; - } + nv_error(priv, "failed to load %s\n", fwname); + return ret; } fuc->size = fw->size; @@ -1615,10 +1622,10 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (use_ext_fw) { nv_info(priv, "using external firmware\n"); - if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) || - gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) || - gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || - gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) + if (gf100_gr_ctor_fw(priv, "fecs_inst", &priv->fuc409c) || + gf100_gr_ctor_fw(priv, "fecs_data", &priv->fuc409d) || + gf100_gr_ctor_fw(priv, "gpccs_inst", &priv->fuc41ac) || + gf100_gr_ctor_fw(priv, "gpccs_data", &priv->fuc41ad)) return -ENODEV; priv->firmware = true; } -- cgit v1.2.3 From c4d0f8f6f8c8dc09cd32e7fdb31e3d1a65a0f8f1 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 23 Jun 2015 15:16:02 +0900 Subject: drm/nouveau/gr/gk20a: use same initialization sequence as nvgpu GK20A's initialization was based on GK104, but differences exist in the way the initial context is built and the initialization process itself. This patch follows the same initialization sequence as nvgpu performs to avoid bad surprises. Since the register bundles initialization also differ considerably from GK104, the register packs are now loaded from firmware files, again similarly to what is done with nvgpu. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 65 ++++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 12 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 336 +++++++++++++++++++++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h | 35 +++ 5 files changed, 421 insertions(+), 30 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 2f241f6f0f0a..3fe080e31a86 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,14 +19,56 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ + #include "ctxgf100.h" +#include "gk20a.h" + +#include + +static void +gk20a_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +{ + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int idle_timeout_save; + int i; + + gf100_gr_mmio(priv, priv->fuc_sw_ctx); + + gf100_gr_wait_idle(priv); + + idle_timeout_save = nv_rd32(priv, 0x404154); + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->attrib(info); + + oclass->unkn(priv); + + gf100_grctx_generate_tpcid(priv); + gf100_grctx_generate_r406028(priv); + gk104_grctx_generate_r418bb8(priv); + gf100_grctx_generate_r406800(priv); + + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + + nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + + gk104_grctx_generate_rop_active_fbps(priv); + + nv_mask(priv, 0x5044b0, 0x8000000, 0x8000000); + + gf100_gr_wait_idle(priv); + + nv_wr32(priv, 0x404154, idle_timeout_save); + gf100_gr_wait_idle(priv); + + gf100_gr_mthd(priv, priv->fuc_method); + gf100_gr_wait_idle(priv); -static const struct gf100_gr_pack -gk20a_grctx_pack_mthd[] = { - { gk104_grctx_init_a097_0, 0xa297 }, - { gf100_grctx_init_902d_0, 0x902d }, - {} -}; + gf100_gr_icmd(priv, priv->fuc_bundle); + oclass->pagepool(info); + oclass->bundle(info); +} struct nvkm_oclass * gk20a_grctx_oclass = &(struct gf100_grctx_oclass) { @@ -39,15 +81,8 @@ gk20a_grctx_oclass = &(struct gf100_grctx_oclass) { .rd32 = _nvkm_gr_context_rd32, .wr32 = _nvkm_gr_context_wr32, }, - .main = gk104_grctx_generate_main, + .main = gk20a_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, - .hub = gk104_grctx_pack_hub, - .gpc = gk104_grctx_pack_gpc, - .zcull = gf100_grctx_pack_zcull, - .tpc = gk104_grctx_pack_tpc, - .ppc = gk104_grctx_pack_ppc, - .icmd = gk104_grctx_pack_icmd, - .mthd = gk20a_grctx_pack_mthd, .bundle = gk104_grctx_generate_bundle, .bundle_size = 0x1800, .bundle_min_gpm_fifo_depth = 0x62, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 454080339572..288423b84667 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1537,7 +1537,7 @@ gf100_gr_init(struct nvkm_object *object) return gf100_gr_init_ctxctl(priv); } -static void +void gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) { kfree(fuc->data); @@ -1690,6 +1690,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, break; case 0xd7: case 0xd9: /* 1/0/0/0, 1 */ + case 0xea: /* gk20a */ priv->magic_not_rop_nr = 0x01; break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index c9533fdac4fc..972efd7b7934 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -76,6 +76,15 @@ struct gf100_gr_priv { struct gf100_gr_fuc fuc41ad; bool firmware; + /* + * Used if the register packs are loaded from NVIDIA fw instead of + * using hardcoded arrays. + */ + struct gf100_gr_pack *fuc_sw_nonctx; + struct gf100_gr_pack *fuc_sw_ctx; + struct gf100_gr_pack *fuc_bundle; + struct gf100_gr_pack *fuc_method; + struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT]; struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT]; @@ -116,6 +125,9 @@ void gf100_gr_context_dtor(struct nvkm_object *); void gf100_gr_ctxctl_debug(struct gf100_gr_priv *); +void gf100_gr_dtor_fw(struct gf100_gr_fuc *); +int gf100_gr_ctor_fw(struct gf100_gr_priv *, const char *, + struct gf100_gr_fuc *); u64 gf100_gr_units(struct nvkm_gr *); int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *data, u32 size, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 40ff5eb9180c..d27ef3ea2226 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -19,10 +19,11 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include "gf100.h" +#include "gk20a.h" #include "ctxgf100.h" #include +#include static struct nvkm_oclass gk20a_gr_sclass[] = { @@ -33,17 +34,324 @@ gk20a_gr_sclass[] = { {} }; +static void +gk20a_gr_init_dtor(struct gf100_gr_pack *pack) +{ + vfree(pack); +} + +struct gk20a_fw_av +{ + u32 addr; + u32 data; +}; + +static struct gf100_gr_pack * +gk20a_gr_av_to_init(struct gf100_gr_fuc *fuc) +{ + struct gf100_gr_init *init; + struct gf100_gr_pack *pack; + const int nent = (fuc->size / sizeof(struct gk20a_fw_av)); + int i; + + pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1))); + if (!pack) + return ERR_PTR(-ENOMEM); + + init = (void *)(pack + 2); + + pack[0].init = init; + + for (i = 0; i < nent; i++) { + struct gf100_gr_init *ent = &init[i]; + struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc->data)[i]; + + ent->addr = av->addr; + ent->data = av->data; + ent->count = 1; + ent->pitch = 1; + } + + return pack; +} + +struct gk20a_fw_aiv +{ + u32 addr; + u32 index; + u32 data; +}; + +static struct gf100_gr_pack * +gk20a_gr_aiv_to_init(struct gf100_gr_fuc *fuc) +{ + struct gf100_gr_init *init; + struct gf100_gr_pack *pack; + const int nent = (fuc->size / sizeof(struct gk20a_fw_aiv)); + int i; + + pack = vzalloc((sizeof(*pack) * 2) + (sizeof(*init) * (nent + 1))); + if (!pack) + return ERR_PTR(-ENOMEM); + + init = (void *)(pack + 2); + + pack[0].init = init; + + for (i = 0; i < nent; i++) { + struct gf100_gr_init *ent = &init[i]; + struct gk20a_fw_aiv *av = &((struct gk20a_fw_aiv *)fuc->data)[i]; + + ent->addr = av->addr; + ent->data = av->data; + ent->count = 1; + ent->pitch = 1; + } + + return pack; +} + +static struct gf100_gr_pack * +gk20a_gr_av_to_method(struct gf100_gr_fuc *fuc) +{ + struct gf100_gr_init *init; + struct gf100_gr_pack *pack; + /* We don't suppose we will initialize more than 16 classes here... */ + static const unsigned int max_classes = 16; + const int nent = (fuc->size / sizeof(struct gk20a_fw_av)); + int i, classidx = 0; + u32 prevclass = 0; + + pack = vzalloc((sizeof(*pack) * max_classes) + + (sizeof(*init) * (nent + 1))); + if (!pack) + return ERR_PTR(-ENOMEM); + + init = (void *)(pack + max_classes); + + for (i = 0; i < nent; i++) { + struct gf100_gr_init *ent = &init[i]; + struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc->data)[i]; + u32 class = av->addr & 0xffff; + u32 addr = (av->addr & 0xffff0000) >> 14; + + if (prevclass != class) { + pack[classidx].init = ent; + pack[classidx].type = class; + prevclass = class; + if (++classidx >= max_classes) { + vfree(pack); + return ERR_PTR(-ENOSPC); + } + } + + ent->addr = addr; + ent->data = av->data; + ent->count = 1; + ent->pitch = 1; + } + + return pack; +} + +static int +gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + int err; + struct gf100_gr_priv *priv; + struct gf100_gr_fuc fuc; + + err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject); + if (err) + return err; + + priv = (void *)*pobject; + + err = gf100_gr_ctor_fw(priv, "sw_nonctx", &fuc); + if (err) + return err; + priv->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(priv->fuc_sw_nonctx)) + return PTR_ERR(priv->fuc_sw_nonctx); + + err = gf100_gr_ctor_fw(priv, "sw_ctx", &fuc); + if (err) + return err; + priv->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(priv->fuc_sw_ctx)) + return PTR_ERR(priv->fuc_sw_ctx); + + err = gf100_gr_ctor_fw(priv, "sw_bundle_init", &fuc); + if (err) + return err; + priv->fuc_bundle = gk20a_gr_av_to_init(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(priv->fuc_bundle)) + return PTR_ERR(priv->fuc_bundle); + + err = gf100_gr_ctor_fw(priv, "sw_method_init", &fuc); + if (err) + return err; + priv->fuc_method = gk20a_gr_av_to_method(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(priv->fuc_method)) + return PTR_ERR(priv->fuc_method); + + return 0; +} + +static void +gk20a_gr_dtor(struct nvkm_object *object) +{ + struct gf100_gr_priv *priv = (void *)object; + + gk20a_gr_init_dtor(priv->fuc_method); + gk20a_gr_init_dtor(priv->fuc_bundle); + gk20a_gr_init_dtor(priv->fuc_sw_ctx); + gk20a_gr_init_dtor(priv->fuc_sw_nonctx); + + gf100_gr_dtor(object); +} + +static int +gk20a_gr_wait_mem_scrubbing(struct gf100_gr_priv *priv) +{ + if (!nv_wait(priv, 0x40910c, 0x6, 0x0)) { + nv_error(priv, "FECS mem scrubbing timeout\n"); + return -ETIMEDOUT; + } + + if (!nv_wait(priv, 0x41a10c, 0x6, 0x0)) { + nv_error(priv, "GPCCS mem scrubbing timeout\n"); + return -ETIMEDOUT; + } + + return 0; +} + +static void +gk20a_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) +{ + nv_wr32(priv, 0x419e44, 0x1ffffe); + nv_wr32(priv, 0x419e4c, 0x7f); +} + +static int +gk20a_gr_init(struct nvkm_object *object) +{ + struct gk20a_gr_oclass *oclass = (void *)object->oclass; + struct gf100_gr_priv *priv = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + u32 data[TPC_MAX / 8] = {}; + u8 tpcnr[GPC_MAX]; + int gpc, tpc; + int ret, i; + + ret = nvkm_gr_init(&priv->base); + if (ret) + return ret; + + /* Clear SCC RAM */ + nv_wr32(priv, 0x40802c, 0x1); + + gf100_gr_mmio(priv, priv->fuc_sw_nonctx); + + ret = gk20a_gr_wait_mem_scrubbing(priv); + if (ret) + return ret; + + ret = gf100_gr_wait_idle(priv); + if (ret) + return ret; + + /* MMU debug buffer */ + nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8); + nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8); + + if (oclass->init_gpc_mmu) + oclass->init_gpc_mmu(priv); + + /* Set the PE as stream master */ + nv_mask(priv, 0x503018, 0x1, 0x1); + + /* Zcull init */ + memset(data, 0x00, sizeof(data)); + memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + do { + gpc = (gpc + 1) % priv->gpc_nr; + } while (!tpcnr[gpc]); + tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + + data[i / 8] |= tpc << ((i % 8) * 4); + } + + nv_wr32(priv, GPC_BCAST(0x0980), data[0]); + nv_wr32(priv, GPC_BCAST(0x0984), data[1]); + nv_wr32(priv, GPC_BCAST(0x0988), data[2]); + nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { + nv_wr32(priv, GPC_UNIT(gpc, 0x0914), + priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); + nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | + priv->tpc_total); + nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + } + + nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + + /* Enable FIFO access */ + nv_wr32(priv, 0x400500, 0x00010001); + + /* Enable interrupts */ + nv_wr32(priv, 0x400100, 0xffffffff); + nv_wr32(priv, 0x40013c, 0xffffffff); + + /* Enable FECS error interrupts */ + nv_wr32(priv, 0x409c24, 0x000f0000); + + /* Enable hardware warning exceptions */ + nv_wr32(priv, 0x404000, 0xc0000000); + nv_wr32(priv, 0x404600, 0xc0000000); + + if (oclass->set_hww_esr_report_mask) + oclass->set_hww_esr_report_mask(priv); + + /* Enable TPC exceptions per GPC */ + nv_wr32(priv, 0x419d0c, 0x2); + nv_wr32(priv, 0x41ac94, (((1 << priv->tpc_total) - 1) & 0xff) << 16); + + /* Reset and enable all exceptions */ + nv_wr32(priv, 0x400108, 0xffffffff); + nv_wr32(priv, 0x400138, 0xffffffff); + nv_wr32(priv, 0x400118, 0xffffffff); + nv_wr32(priv, 0x400130, 0xffffffff); + nv_wr32(priv, 0x40011c, 0xffffffff); + nv_wr32(priv, 0x400134, 0xffffffff); + + gf100_gr_zbc_init(priv); + + return gf100_gr_init_ctxctl(priv); +} + struct nvkm_oclass * -gk20a_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gk104_gr_init, - .fini = _nvkm_gr_fini, +gk20a_gr_oclass = &(struct gk20a_gr_oclass) { + .gf100 = { + .base.handle = NV_ENGINE(GR, 0xea), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk20a_gr_ctor, + .dtor = gk20a_gr_dtor, + .init = gk20a_gr_init, + .fini = _nvkm_gr_fini, + }, + .cclass = &gk20a_grctx_oclass, + .sclass = gk20a_gr_sclass, + .ppc_nr = 1, }, - .cclass = &gk20a_grctx_oclass, - .sclass = gk20a_gr_sclass, - .mmio = gk104_gr_pack_mmio, - .ppc_nr = 1, -}.base; + .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, +}.gf100.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h new file mode 100644 index 000000000000..b36958505a81 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __GK20A_GR_H__ +#define __GK20A_GR_H__ + +#include "gf100.h" + +struct gk20a_gr_oclass { + struct gf100_gr_oclass gf100; + + void (*init_gpc_mmu)(struct gf100_gr_priv *); + void (*set_hww_esr_report_mask)(struct gf100_gr_priv *); +}; + +#endif -- cgit v1.2.3 From a032fb9da665ed6e6a36fa6788eff1db43ba2703 Mon Sep 17 00:00:00 2001 From: Alexandre Courbot Date: Tue, 23 Jun 2015 15:16:04 +0900 Subject: drm/nouveau/gr: add GM20B support Add support for GM20B's graphics engine, based on GK20A. Note that this code alone will not allow the engine to initialize on released devices which require PMU-assisted secure boot. Signed-off-by: Alexandre Courbot Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 2 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 7 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 110 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 6 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 84 +++++++++++++++++ 10 files changed, 217 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h index 7cbe20280760..c772497cac3e 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -74,6 +74,7 @@ extern struct nvkm_oclass *gk208_gr_oclass; extern struct nvkm_oclass *gm107_gr_oclass; extern struct nvkm_oclass *gm204_gr_oclass; extern struct nvkm_oclass *gm206_gr_oclass; +extern struct nvkm_oclass *gm20b_gr_oclass; #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild index 2e1b92f71d9e..e91b4dfc0bf3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -14,6 +14,7 @@ nvkm-y += nvkm/engine/gr/ctxgk208.o nvkm-y += nvkm/engine/gr/ctxgm107.o nvkm-y += nvkm/engine/gr/ctxgm204.o nvkm-y += nvkm/engine/gr/ctxgm206.o +nvkm-y += nvkm/engine/gr/ctxgm20b.o nvkm-y += nvkm/engine/gr/nv04.o nvkm-y += nvkm/engine/gr/nv10.o nvkm-y += nvkm/engine/gr/nv20.o @@ -38,3 +39,4 @@ nvkm-y += nvkm/engine/gr/gk208.o nvkm-y += nvkm/engine/gr/gm107.o nvkm-y += nvkm/engine/gr/gm204.o nvkm-y += nvkm/engine/gr/gm206.o +nvkm-y += nvkm/engine/gr/gm20b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index 3676a3342bc5..f89ab3706cf3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -91,6 +91,10 @@ void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *); void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *); +void gm107_grctx_generate_bundle(struct gf100_grctx *); +void gm107_grctx_generate_pagepool(struct gf100_grctx *); +void gm107_grctx_generate_attrib(struct gf100_grctx *); + extern struct nvkm_oclass *gk110_grctx_oclass; extern struct nvkm_oclass *gk110b_grctx_oclass; extern struct nvkm_oclass *gk208_grctx_oclass; @@ -102,8 +106,11 @@ void gm107_grctx_generate_attrib(struct gf100_grctx *); extern struct nvkm_oclass *gm204_grctx_oclass; void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *); +void gm204_grctx_generate_tpcid(struct gf100_gr_priv *); +void gm204_grctx_generate_405b60(struct gf100_gr_priv *); extern struct nvkm_oclass *gm206_grctx_oclass; +extern struct nvkm_oclass *gm20b_grctx_oclass; /* context init value lists */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index fbeaae3ae6ce..6bf2fd1a05ba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -931,7 +931,7 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info) } } -static void +void gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv) { int gpc, tpc, id; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c index ea8e66151aa8..efc76bfae896 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c @@ -918,7 +918,7 @@ gm204_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ -static void +void gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv) { int gpc, tpc, id; @@ -943,7 +943,7 @@ gm204_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv) nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */ } -static void +void gm204_grctx_generate_405b60(struct gf100_gr_priv *priv) { const u32 dist_nr = DIV_ROUND_UP(priv->tpc_total, 4); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c new file mode 100644 index 000000000000..c011bf327276 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "ctxgf100.h" + +static void +gm20b_grctx_generate_r406028(struct gf100_gr_priv *priv) +{ + u32 tpc_per_gpc = 0; + int i; + + for (i = 0; i < priv->gpc_nr; i++) + tpc_per_gpc |= priv->tpc_nr[i] << (4 * i); + + nv_wr32(priv, 0x406028, tpc_per_gpc); + nv_wr32(priv, 0x405870, tpc_per_gpc); +} + +static void +gm20b_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +{ + struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + int idle_timeout_save; + int i, tmp; + + gf100_gr_mmio(priv, priv->fuc_sw_ctx); + + gf100_gr_wait_idle(priv); + + idle_timeout_save = nv_rd32(priv, 0x404154); + nv_wr32(priv, 0x404154, 0x00000000); + + oclass->attrib(info); + + oclass->unkn(priv); + + gm204_grctx_generate_tpcid(priv); + gm20b_grctx_generate_r406028(priv); + gk104_grctx_generate_r418bb8(priv); + + for (i = 0; i < 8; i++) + nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + + nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + + gk104_grctx_generate_rop_active_fbps(priv); + nv_wr32(priv, 0x408908, nv_rd32(priv, 0x410108) | 0x80000000); + + for (tmp = 0, i = 0; i < priv->gpc_nr; i++) + tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4); + nv_wr32(priv, 0x4041c4, tmp); + + gm204_grctx_generate_405b60(priv); + + gf100_gr_wait_idle(priv); + + nv_wr32(priv, 0x404154, idle_timeout_save); + gf100_gr_wait_idle(priv); + + gf100_gr_mthd(priv, priv->fuc_method); + gf100_gr_wait_idle(priv); + + gf100_gr_icmd(priv, priv->fuc_bundle); + oclass->pagepool(info); + oclass->bundle(info); +} + +struct nvkm_oclass * +gm20b_grctx_oclass = &(struct gf100_grctx_oclass) { + .base.handle = NV_ENGCTX(GR, 0x2b), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_gr_context_ctor, + .dtor = gf100_gr_context_dtor, + .init = _nvkm_gr_context_init, + .fini = _nvkm_gr_context_fini, + .rd32 = _nvkm_gr_context_rd32, + .wr32 = _nvkm_gr_context_wr32, + }, + .main = gm20b_grctx_generate_main, + .unkn = gk104_grctx_generate_unkn, + .bundle = gm107_grctx_generate_bundle, + .bundle_size = 0x1800, + .bundle_min_gpm_fifo_depth = 0x182, + .bundle_token_limit = 0x1c0, + .pagepool = gm107_grctx_generate_pagepool, + .pagepool_size = 0x8000, + .attrib = gm107_grctx_generate_attrib, + .attrib_nr_max = 0x600, + .attrib_nr = 0x400, + .alpha_nr_max = 0xc00, + .alpha_nr = 0x800, +}.base; \ No newline at end of file diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 288423b84667..e7c3e9e57385 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1691,6 +1691,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, case 0xd7: case 0xd9: /* 1/0/0/0, 1 */ case 0xea: /* gk20a */ + case 0x12b: /* gm20b */ priv->magic_not_rop_nr = 0x01; break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 972efd7b7934..f185f034d1ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -141,6 +141,12 @@ int gk104_gr_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_object **); int gk104_gr_init(struct nvkm_object *); +int gk20a_gr_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *data, u32 size, + struct nvkm_object **); +void gk20a_gr_dtor(struct nvkm_object *); +int gk20a_gr_init(struct nvkm_object *); + int gm204_gr_init(struct nvkm_object *); extern struct nvkm_ofuncs gf100_fermi_ofuncs; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index d27ef3ea2226..fc4a910b2498 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -154,7 +154,7 @@ gk20a_gr_av_to_method(struct gf100_gr_fuc *fuc) return pack; } -static int +int gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) @@ -204,7 +204,7 @@ gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } -static void +void gk20a_gr_dtor(struct nvkm_object *object) { struct gf100_gr_priv *priv = (void *)object; @@ -240,7 +240,7 @@ gk20a_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) nv_wr32(priv, 0x419e4c, 0x7f); } -static int +int gk20a_gr_init(struct nvkm_object *object) { struct gk20a_gr_oclass *oclass = (void *)object->oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c new file mode 100644 index 000000000000..897628062d58 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "gk20a.h" +#include "ctxgf100.h" + +#include +#include + +static struct nvkm_oclass +gm20b_gr_sclass[] = { + { FERMI_TWOD_A, &nvkm_object_ofuncs }, + { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, + { MAXWELL_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, + { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + {} +}; + +static void +gm20b_gr_init_gpc_mmu(struct gf100_gr_priv *priv) +{ + u32 val; + + /* TODO this needs to be removed once secure boot works */ + if (1) { + nv_wr32(priv, 0x100ce4, 0xffffffff); + } + + /* TODO update once secure boot works */ + val = nv_rd32(priv, 0x100c80); + val &= 0xf000087f; + nv_wr32(priv, 0x418880, val); + nv_wr32(priv, 0x418890, 0); + nv_wr32(priv, 0x418894, 0); + + nv_wr32(priv, 0x4188b0, nv_rd32(priv, 0x100cc4)); + nv_wr32(priv, 0x4188b4, nv_rd32(priv, 0x100cc8)); + nv_wr32(priv, 0x4188b8, nv_rd32(priv, 0x100ccc)); + + nv_wr32(priv, 0x4188ac, nv_rd32(priv, 0x100800)); +} + +static void +gm20b_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) +{ + nv_wr32(priv, 0x419e44, 0xdffffe); + nv_wr32(priv, 0x419e4c, 0x5); +} + +struct nvkm_oclass * +gm20b_gr_oclass = &(struct gk20a_gr_oclass) { + .gf100 = { + .base.handle = NV_ENGINE(GR, 0x2b), + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk20a_gr_ctor, + .dtor = gf100_gr_dtor, + .init = gk20a_gr_init, + .fini = _nvkm_gr_fini, + }, + .cclass = &gm20b_grctx_oclass, + .sclass = gm20b_gr_sclass, + .ppc_nr = 1, + }, + .init_gpc_mmu = gm20b_gr_init_gpc_mmu, + .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, +}.gf100.base; -- cgit v1.2.3 From 9ace404b1098221021b01c2ba0eeea0c257fa4a5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:06 +1000 Subject: drm/nouveau/device: include core/device.h automatically for subdevs/engines Pretty much every subdev/engine is going to need access to nvkm_device shortly to touch registers and/or output messages. The odd placement of the includes is necessary to work around some inter-dependencies that currently exist. This will be fixed later. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 60 +++++++++++++++++++++ drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h | 62 ---------------------- drivers/gpu/drm/nouveau/include/nvkm/core/engine.h | 2 + drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h | 3 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c | 1 - .../gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c | 2 - .../gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c | 1 - .../gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c | 2 - .../gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c | 2 - .../gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c | 1 - .../gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c | 1 - .../gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c | 1 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c | 2 - drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c | 2 - 78 files changed, 65 insertions(+), 159 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index d5811a0212be..4ae876096c7d 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -3,6 +3,66 @@ #include #include +enum nvkm_devidx { + NVDEV_ENGINE_DEVICE, + NVDEV_SUBDEV_VBIOS, + + /* All subdevs from DEVINIT to DEVINIT_LAST will be created before + * *any* of them are initialised. This subdev category is used + * for any subdevs that the VBIOS init table parsing may call out + * to during POST. + */ + NVDEV_SUBDEV_DEVINIT, + NVDEV_SUBDEV_IBUS, + NVDEV_SUBDEV_GPIO, + NVDEV_SUBDEV_I2C, + NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C, + + /* This grouping of subdevs are initialised right after they've + * been created, and are allowed to assume any subdevs in the + * list above them exist and have been initialised. + */ + NVDEV_SUBDEV_FUSE, + NVDEV_SUBDEV_MXM, + NVDEV_SUBDEV_MC, + NVDEV_SUBDEV_BUS, + NVDEV_SUBDEV_TIMER, + NVDEV_SUBDEV_FB, + NVDEV_SUBDEV_LTC, + NVDEV_SUBDEV_INSTMEM, + NVDEV_SUBDEV_MMU, + NVDEV_SUBDEV_BAR, + NVDEV_SUBDEV_PMU, + NVDEV_SUBDEV_VOLT, + NVDEV_SUBDEV_THERM, + NVDEV_SUBDEV_CLK, + + NVDEV_ENGINE_FIRST, + NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, + NVDEV_ENGINE_IFB, + NVDEV_ENGINE_FIFO, + NVDEV_ENGINE_SW, + NVDEV_ENGINE_GR, + NVDEV_ENGINE_MPEG, + NVDEV_ENGINE_ME, + NVDEV_ENGINE_VP, + NVDEV_ENGINE_CIPHER, + NVDEV_ENGINE_BSP, + NVDEV_ENGINE_MSPPP, + NVDEV_ENGINE_CE0, + NVDEV_ENGINE_CE1, + NVDEV_ENGINE_CE2, + NVDEV_ENGINE_VIC, + NVDEV_ENGINE_MSENC, + NVDEV_ENGINE_DISP, + NVDEV_ENGINE_PM, + NVDEV_ENGINE_MSVLD, + NVDEV_ENGINE_SEC, + NVDEV_ENGINE_MSPDEC, + + NVDEV_SUBDEV_NR, +}; + struct nvkm_device { struct nvkm_engine engine; struct list_head head; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h deleted file mode 100644 index 60c5888b5df3..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/devidx.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __NVKM_DEVIDX_H__ -#define __NVKM_DEVIDX_H__ -enum nvkm_devidx { - NVDEV_ENGINE_DEVICE, - NVDEV_SUBDEV_VBIOS, - - /* All subdevs from DEVINIT to DEVINIT_LAST will be created before - * *any* of them are initialised. This subdev category is used - * for any subdevs that the VBIOS init table parsing may call out - * to during POST. - */ - NVDEV_SUBDEV_DEVINIT, - NVDEV_SUBDEV_IBUS, - NVDEV_SUBDEV_GPIO, - NVDEV_SUBDEV_I2C, - NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C, - - /* This grouping of subdevs are initialised right after they've - * been created, and are allowed to assume any subdevs in the - * list above them exist and have been initialised. - */ - NVDEV_SUBDEV_FUSE, - NVDEV_SUBDEV_MXM, - NVDEV_SUBDEV_MC, - NVDEV_SUBDEV_BUS, - NVDEV_SUBDEV_TIMER, - NVDEV_SUBDEV_FB, - NVDEV_SUBDEV_LTC, - NVDEV_SUBDEV_INSTMEM, - NVDEV_SUBDEV_MMU, - NVDEV_SUBDEV_BAR, - NVDEV_SUBDEV_PMU, - NVDEV_SUBDEV_VOLT, - NVDEV_SUBDEV_THERM, - NVDEV_SUBDEV_CLK, - - NVDEV_ENGINE_FIRST, - NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, - NVDEV_ENGINE_IFB, - NVDEV_ENGINE_FIFO, - NVDEV_ENGINE_SW, - NVDEV_ENGINE_GR, - NVDEV_ENGINE_MPEG, - NVDEV_ENGINE_ME, - NVDEV_ENGINE_VP, - NVDEV_ENGINE_CIPHER, - NVDEV_ENGINE_BSP, - NVDEV_ENGINE_MSPPP, - NVDEV_ENGINE_CE0, - NVDEV_ENGINE_CE1, - NVDEV_ENGINE_CE2, - NVDEV_ENGINE_VIC, - NVDEV_ENGINE_MSENC, - NVDEV_ENGINE_DISP, - NVDEV_ENGINE_PM, - NVDEV_ENGINE_MSVLD, - NVDEV_ENGINE_SEC, - NVDEV_ENGINE_MSPDEC, - - NVDEV_SUBDEV_NR, -}; -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index faf0fd2f0638..441f843f2490 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -53,4 +53,6 @@ int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *, #define _nvkm_engine_dtor _nvkm_subdev_dtor #define _nvkm_engine_init _nvkm_subdev_init #define _nvkm_engine_fini _nvkm_subdev_fini + +#include #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h index 8357319f5a14..d2dac06f2b8b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h @@ -1,7 +1,6 @@ #ifndef __NVKM_SUBDEV_H__ #define __NVKM_SUBDEV_H__ #include -#include #define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub)) #define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var)) @@ -119,4 +118,6 @@ nv_mask(void *obj, u32 addr, u32 mask, u32 data) nv_wr32(obj, addr, (temp & ~mask) | data); return temp; } + +#include #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h index fee09ad818e4..53294f42c690 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/vga.h @@ -1,7 +1,6 @@ #ifndef __NOUVEAU_VGA_H__ #define __NOUVEAU_VGA_H__ - -#include +#include /* access to various legacy io ports */ u8 nv_rdport(void *obj, int head, u16 port); @@ -26,5 +25,4 @@ void nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value); bool nv_lockvgac(void *obj, bool lock); u8 nv_rdvgaowner(void *obj); void nv_wrvgaowner(void *obj, u8); - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index d8bb4293bc11..72604d332596 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -27,7 +27,6 @@ #include "fuc/gt215.fuc3.h" #include -#include #include struct gt215_ce_priv { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index ff09b2659c17..b8f9e5c2b3c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -24,7 +24,6 @@ #include "priv.h" #include -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index 8ba808df24ad..25fcabcb1d6c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -26,7 +26,6 @@ #include "outpdp.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c index 22443627a086..0b4ecb837597 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c @@ -24,7 +24,6 @@ #include "nv50.h" #include "outpdp.h" -#include #include static inline u32 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c index c4622c7388d0..c91d73bc9c9b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c @@ -23,8 +23,6 @@ */ #include -#include - u8 nv_rdport(void *obj, int head, u16 port) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c index a2b60d86baba..3adab2ed7c08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c @@ -24,7 +24,6 @@ #include "priv.h" #include -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 30958c19e61d..f6e9ae95c822 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -21,7 +21,6 @@ */ #include -#include #include void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index fa223f88d25e..a85014bb37a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 043e4296084c..d157aaede405 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -24,7 +24,6 @@ #include "nv04.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 5bfc96265f3b..24930d9b6ae4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -24,7 +24,6 @@ #include "nv04.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c index dc31462afe65..a3b0b366f582 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c @@ -111,7 +111,6 @@ #include "ctxnv40.h" #include "nv40.h" -#include /* TODO: * - get vs count from 0x1540 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index 9c9528d2cd90..a9a4e0e3f2cb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -107,7 +107,6 @@ #include "ctxnv40.h" -#include #include #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index e7c3e9e57385..1ca9385f5479 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -26,7 +26,6 @@ #include "fuc/os.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 2614510c28d0..81abe6fb3872 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -25,7 +25,6 @@ #include "regs.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 389904eb603f..62a4d797498a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -25,7 +25,6 @@ #include "regs.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 1713ffb669e8..5d8dbac3cdb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -2,7 +2,6 @@ #include "regs.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index dcc84eb54fb6..207464c3c40e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -1,7 +1,6 @@ #include "nv20.h" #include "regs.h" -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index d852bd6de571..01d9f73a024c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -2,7 +2,6 @@ #define __NV40_GR_H__ #include -#include struct nvkm_gpuobj; /* returns 1 if device is one of the nv4x using the 0x4497 object class, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 270d7cd63fc7..754284feae91 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -24,7 +24,6 @@ #include "nv50.h" #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index 48c1ce6e663c..8741201d4236 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -24,7 +24,6 @@ #include "priv.h" #include -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 401fcd73086b..14d9650f4779 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -23,7 +23,6 @@ */ #include "nv50.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index cea90df533d9..3995d2cf0668 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include -#include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 3502d00122ef..9b6b9ac34ced 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 12a1aebd9a96..4c6d238dd3da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index 8548adb91dcc..36c5c083c1e9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c index 95e9208e47d1..146357171757 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.c @@ -24,8 +24,6 @@ #include #include -#include - u16 dcb_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index 8e5f6ce76232..045b7ddb4d66 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -31,7 +31,6 @@ #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c index 382ae9cdbf58..1e70d0eaed41 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c @@ -25,8 +25,6 @@ #include #include -#include - u16 nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c index ebd402e19dbf..ac48ccc5d2c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.c @@ -27,7 +27,6 @@ #include #include -#include struct pll_mapping { u8 type; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c index 8c2b7cba5cff..6192a9e27bb7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c index f9d0eb5647fa..74604d4a7ff2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c @@ -22,8 +22,6 @@ */ #include "priv.h" -#include - #if defined(CONFIG_ACPI) && defined(CONFIG_X86) int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); bool nouveau_acpi_rom_supported(struct pci_dev *pdev); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c index 4c19a7dba803..4f5cbf4d9666 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c @@ -22,7 +22,6 @@ */ #include "priv.h" -#include #if defined(__powerpc__) struct priv { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c index 1b045483dc87..ae1e229b617f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c @@ -22,8 +22,6 @@ */ #include "priv.h" -#include - struct priv { struct pci_dev *pdev; void __iomem *rom; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c index abe8ae4d3a9f..c2c31ba59868 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.c @@ -22,8 +22,6 @@ */ #include "priv.h" -#include - struct priv { struct nvkm_bios *bios; u32 bar0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c index 6ec3b237925e..cd0b06fbc3c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.c @@ -22,8 +22,6 @@ */ #include "priv.h" -#include - static u32 prom_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c index 249ff6d583df..8fbb8917b0e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.c @@ -25,8 +25,6 @@ #include #include -#include - static u16 therm_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index 77a0ab5ca3b0..cba018d02b4b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -30,7 +30,6 @@ #include #include -#include #include /****************************************************************************** diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c index 3d7330d54b02..e8125b5199a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -24,7 +24,6 @@ #include #include "pll.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c index e9b2310bdfbb..e380d62df232 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c @@ -24,7 +24,6 @@ #include #include "pll.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index 65c532742b08..94d3839fd444 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -25,8 +25,6 @@ #include #include -#include - #ifdef __KERNEL__ #include #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index 065e9f5c8db9..581e3a696fd8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -25,7 +25,6 @@ #include "gt215.h" #include "pll.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index c54417b146c7..d735de2dbd74 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -24,7 +24,6 @@ #include "gt215.h" #include "pll.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c index ed838130c89d..15668d2883f1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c @@ -24,7 +24,6 @@ #include #include "pll.h" -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c index 89c5d886f2ad..b58f4786e407 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c @@ -25,7 +25,6 @@ #include "pll.h" #include "seq.h" -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c index b0d7c5f40db1..5cc7dd24a213 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h index 36684c3f9e9c..4e484c40b5c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h @@ -23,7 +23,6 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include #include #define NV04_PFB_DEBUG_0 0x00100080 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index d51aa0237baf..5a6c2b7a6ef1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -23,8 +23,6 @@ */ #include "gf100.h" -#include - extern const u8 gf100_pte_storage_type_map[256]; bool diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 09ebb9477e00..6c0b82f35d94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -25,8 +25,6 @@ */ #include "nv04.h" -#include - void nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 0480ce52aa06..48fd5a5bcd3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -24,7 +24,6 @@ #include "nv50.h" #include -#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index de9f39569943..dcb175bea84b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -24,7 +24,6 @@ #include "gf100.h" #include "ramfuc.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 1ef15c3e6a81..97060ccfb80c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -24,7 +24,6 @@ #include "ramfuc.h" #include "gf100.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index bc36a4ff15f4..1d604c075a3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -26,7 +26,6 @@ #include "ramfuc.h" #include "nv50.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c index fbae05db4ffd..8bb7e432ad04 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c @@ -23,8 +23,6 @@ */ #include "priv.h" -#include - static int nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 3d31fa45c1a6..a36a90c29ba9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -23,7 +23,6 @@ */ #include "nv40.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 66db0a4e2538..fd0e9cecef62 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -24,7 +24,6 @@ #include "nv50.h" #include "ramseq.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 980822d6d645..f60284f3b8b5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include static int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c index 9200f122c02c..3e2c2882d515 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.c @@ -24,7 +24,6 @@ #include "priv.h" #include "pad.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index dd0994d9ebfc..cd8ab5fcb585 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -40,7 +40,6 @@ #include #include -#include #ifdef __KERNEL__ #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index 5b051a26653e..8699e5b2f497 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include static inline void diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index 40e3019e1fde..9c43ddce9992 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -23,8 +23,6 @@ */ #include "nv04.h" -#include - const struct nvkm_mc_intr nv50_mc_intr[] = { { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c index fe93ea2711c9..861c97adec70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -23,7 +23,6 @@ */ #include "nv04.h" -#include #include #define NV04_PDMA_SIZE (128 * 1024 * 1024) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index 61ee3ab11660..37b943aba114 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -23,7 +23,6 @@ */ #include "nv04.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index b90ded1887aa..87824693f9cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -23,7 +23,6 @@ */ #include "nv04.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c index 0ca9dcabb6d3..7ecacf60f541 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c @@ -23,7 +23,6 @@ */ #include "mxms.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c index b75c5b885980..8e69bc75e571 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c @@ -2,8 +2,6 @@ #define __NVKM_PMU_MEMX_H__ #include "priv.h" -#include - struct nvkm_memx { struct nvkm_pmu *pmu; u32 base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index ec327cb64a0d..eb86c3ed5f56 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -23,8 +23,6 @@ */ #include "priv.h" -#include - static int nvkm_therm_update_trip(struct nvkm_therm *therm) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c index bde5ceaeb70a..3cf4192a33af 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.c @@ -24,7 +24,6 @@ */ #include "priv.h" -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c index 46b7e656a752..0540e6886d7d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf110.c @@ -23,8 +23,6 @@ */ #include "priv.h" -#include - struct gf110_therm_priv { struct nvkm_therm_priv base; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c index 2fd110f09878..c1f3cf361837 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.c @@ -23,8 +23,6 @@ */ #include "priv.h" -#include - struct gm107_therm_priv { struct nvkm_therm_priv base; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c index e99be20332f2..b7fa4716ca9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.c @@ -23,7 +23,6 @@ */ #include "priv.h" -#include #include struct gt215_therm_priv { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c index 8496fffd4688..20f65fd7679a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.c @@ -24,8 +24,6 @@ */ #include "priv.h" -#include - struct nv40_therm_priv { struct nvkm_therm_priv base; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c index 1ef59e8922d4..489dcf355d34 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.c @@ -24,8 +24,6 @@ */ #include "priv.h" -#include - struct nv50_therm_priv { struct nvkm_therm_priv base; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c index 6b7facbe59a2..cf386f9c84c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c @@ -23,8 +23,6 @@ */ #include "nv04.h" -#include - static u64 nv04_timer_read(struct nvkm_timer *ptimer) { -- cgit v1.2.3 From b1e4553cb1f9deddbd8c13d95e9cef81967a3f41 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:06 +1000 Subject: drm/nouveau/fb: cosmetic changes This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 2 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 20 +-- drivers/gpu/drm/nouveau/nouveau_gem.c | 4 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 20 +-- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 10 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c | 64 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 56 ++++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c | 16 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c | 24 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h | 4 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c | 14 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 36 ++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c | 18 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c | 20 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 52 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 18 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 118 +++++++------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 169 ++++++++++---------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 170 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c | 50 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c | 10 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 88 +++++------ drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c | 16 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 125 ++++++++------- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 8 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c | 18 +-- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c | 4 +- 51 files changed, 649 insertions(+), 663 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 16da56cf43b0..344cc99f0dc1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -46,7 +46,7 @@ struct nvkm_fb_tile { }; struct nvkm_fb { - struct nvkm_subdev base; + struct nvkm_subdev subdev; bool (*memtype_valid)(struct nvkm_fb *, u32 memtype); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 6edcce1658b7..37ed3b250ac5 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -48,23 +48,23 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, { struct nouveau_drm *drm = nouveau_drm(dev); int i = reg - drm->tile.reg; - struct nvkm_fb *pfb = nvxx_fb(&drm->device); - struct nvkm_fb_tile *tile = &pfb->tile.region[i]; + struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_fb_tile *tile = &fb->tile.region[i]; struct nvkm_engine *engine; nouveau_fence_unref(®->fence); if (tile->pitch) - pfb->tile.fini(pfb, i, tile); + fb->tile.fini(fb, i, tile); if (pitch) - pfb->tile.init(pfb, i, addr, size, pitch, flags, tile); + fb->tile.init(fb, i, addr, size, pitch, flags, tile); - pfb->tile.prog(pfb, i, tile); + fb->tile.prog(fb, i, tile); - if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_GR))) + if ((engine = nvkm_engine(fb, NVDEV_ENGINE_GR))) engine->tile_prog(engine, i); - if ((engine = nvkm_engine(pfb, NVDEV_ENGINE_MPEG))) + if ((engine = nvkm_engine(fb, NVDEV_ENGINE_MPEG))) engine->tile_prog(engine, i); } @@ -105,18 +105,18 @@ nv10_bo_set_tiling(struct drm_device *dev, u32 addr, u32 size, u32 pitch, u32 flags) { struct nouveau_drm *drm = nouveau_drm(dev); - struct nvkm_fb *pfb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->device); struct nouveau_drm_tile *tile, *found = NULL; int i; - for (i = 0; i < pfb->tile.regions; i++) { + for (i = 0; i < fb->tile.regions; i++) { tile = nv10_bo_get_tile_region(dev, i); if (pitch && !found) { found = tile; continue; - } else if (tile && pfb->tile.region[i].pitch) { + } else if (tile && fb->tile.region[i].pitch) { /* Kill an unused tile region. */ nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); } diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index af1ee517f372..a747eccbc79f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -254,12 +254,12 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data, { struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_cli *cli = nouveau_cli(file_priv); - struct nvkm_fb *pfb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->device); struct drm_nouveau_gem_new *req = data; struct nouveau_bo *nvbo = NULL; int ret = 0; - if (!pfb->memtype_valid(pfb, req->info.tile_flags)) { + if (!fb->memtype_valid(fb, req->info.tile_flags)) { NV_PRINTK(error, cli, "bad page flags: 0x%08x\n", req->info.tile_flags); return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 737e8f976a98..d9c64c2aabc8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -33,8 +33,8 @@ static int nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_fb *pfb = nvxx_fb(&drm->device); - man->priv = pfb; + struct nvkm_fb *fb = nvxx_fb(&drm->device); + man->priv = fb; return 0; } @@ -64,9 +64,9 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_fb *pfb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->device); nvkm_mem_node_cleanup(mem->mm_node); - pfb->ram->put(pfb, (struct nvkm_mem **)&mem->mm_node); + fb->ram->put(fb, (struct nvkm_mem **)&mem->mm_node); } static int @@ -76,7 +76,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_fb *pfb = nvxx_fb(&drm->device); + struct nvkm_fb *fb = nvxx_fb(&drm->device); struct nouveau_bo *nvbo = nouveau_bo(bo); struct nvkm_mem *node; u32 size_nc = 0; @@ -88,7 +88,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) size_nc = 1 << nvbo->page_shift; - ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT, + ret = fb->ram->get(fb, mem->num_pages << PAGE_SHIFT, mem->page_alignment << PAGE_SHIFT, size_nc, (nvbo->tile_flags >> 8) & 0x3ff, &node); if (ret) { @@ -106,12 +106,12 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, static void nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) { - struct nvkm_fb *pfb = man->priv; - struct nvkm_mm *mm = &pfb->vram; + struct nvkm_fb *fb = man->priv; + struct nvkm_mm *mm = &fb->vram; struct nvkm_mm_node *r; u32 total = 0, free = 0; - mutex_lock(&nv_subdev(pfb)->mutex); + mutex_lock(&nv_subdev(fb)->mutex); list_for_each_entry(r, &mm->nodes, nl_entry) { printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n", prefix, r->type, ((u64)r->offset << 12), @@ -121,7 +121,7 @@ nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) if (!r->type) free += r->length; } - mutex_unlock(&nv_subdev(pfb)->mutex); + mutex_unlock(&nv_subdev(fb)->mutex); printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n", prefix, (u64)total << 12, (u64)free << 12); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 28ebe06e87b9..106ec87749a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -80,7 +80,7 @@ static int nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) { struct nvkm_device *device = nv_device(object); - struct nvkm_fb *pfb = nvkm_fb(device); + struct nvkm_fb *fb = nvkm_fb(device); struct nvkm_instmem *imem = nvkm_instmem(device); union { struct nv_device_info_v0 v0; @@ -139,8 +139,8 @@ nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size) args->v0.chipset = device->chipset; args->v0.revision = device->chiprev; - if (pfb && pfb->ram) - args->v0.ram_size = args->v0.ram_user = pfb->ram->size; + if (fb && fb->ram) + args->v0.ram_size = args->v0.ram_user = fb->ram->size; else args->v0.ram_size = args->v0.ram_user = 0; if (imem && args->v0.ram_size > 0) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c index 3adab2ed7c08..b6572f1b6981 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c @@ -64,7 +64,7 @@ nvkm_dmaobj_create_(struct nvkm_object *parent, struct nvkm_instmem *instmem = nvkm_instmem(parent); struct nvkm_client *client = nvkm_client(parent); struct nvkm_device *device = nv_device(parent); - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_dmaobj *dmaobj; void *data = *pdata; u32 size = *psize; @@ -100,7 +100,7 @@ nvkm_dmaobj_create_(struct nvkm_object *parent, break; case NV_DMA_V0_TARGET_VRAM: if (!client->super) { - if (dmaobj->limit >= pfb->ram->size - instmem->reserved) + if (dmaobj->limit >= fb->ram->size - instmem->reserved) return -EACCES; if (device->card_type >= NV_50) return -EACCES; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 24930d9b6ae4..a9bb6a53f9fa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -295,7 +295,7 @@ static int nv40_fifo_init(struct nvkm_object *object) { struct nv04_fifo_priv *priv = (void *)object; - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); int ret; ret = nvkm_fifo_init(&priv->base); @@ -326,7 +326,7 @@ nv40_fifo_init(struct nvkm_object *object) break; default: nv_wr32(priv, 0x002230, 0x00000000); - nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 + + nv_wr32(priv, 0x002220, ((fb->ram->size - 512 * 1024 + priv->ramfc->addr) >> 16) | 0x00030000); break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 62a4d797498a..535f5930c40b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -1249,7 +1249,7 @@ static int nv10_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); struct nv10_gr_priv *priv = (void *)engine; int ret, i; @@ -1279,7 +1279,7 @@ nv10_gr_init(struct nvkm_object *object) } /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) + for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 5d8dbac3cdb8..0aa4cc9f74e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -271,7 +271,7 @@ nv20_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nv20_gr_priv *priv = (void *)engine; - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); u32 tmp, vramsz; int ret, i; @@ -324,7 +324,7 @@ nv20_gr_init(struct nvkm_object *object) } /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) + for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 207464c3c40e..0214e8a91dac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -153,7 +153,7 @@ nv30_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nv20_gr_priv *priv = (void *)engine; - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); int ret, i; ret = nvkm_gr_init(&priv->base); @@ -198,7 +198,7 @@ nv30_gr_init(struct nvkm_object *object) nv_wr32(priv, 0x4000c0, 0x00000016); /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) + for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 7e1937980e3f..ed05c6d7875b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -366,7 +366,7 @@ static int nv40_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); struct nv40_gr_priv *priv = (void *)engine; int ret, i, j; u32 vramsz; @@ -470,7 +470,7 @@ nv40_gr_init(struct nvkm_object *object) } /* Turn all the tiling regions off. */ - for (i = 0; i < pfb->tile.regions; i++) + for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); /* begin RAM config */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index b5bef0718359..891004157ea8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -260,7 +260,7 @@ nv31_mpeg_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nv31_mpeg_priv *priv = (void *)object; - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); int ret, i; ret = nvkm_mpeg_init(&priv->base); @@ -271,7 +271,7 @@ nv31_mpeg_init(struct nvkm_object *object) nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ - for (i = 0; i < pfb->tile.regions; i++) + for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); /* PMPEG init */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index 572fbf1bc72f..a624e9eb0c3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -171,7 +171,7 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) static int nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { - struct nvkm_fb *pfb = nvkm_fb(clk); + struct nvkm_fb *fb = nvkm_fb(clk); struct nvkm_pstate *pstate; int ret, idx = 0; @@ -183,14 +183,14 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) nv_debug(clk, "setting performance state %d\n", pstatei); clk->pstate = pstatei; - if (pfb->ram && pfb->ram->calc) { + if (fb->ram && fb->ram->calc) { int khz = pstate->base.domain[nv_clk_src_mem]; do { - ret = pfb->ram->calc(pfb, khz); + ret = fb->ram->calc(fb, khz); if (ret == 0) - ret = pfb->ram->prog(pfb); + ret = fb->ram->prog(fb); } while (ret > 0); - pfb->ram->tidy(pfb); + fb->ram->tidy(fb); } return nvkm_cstate_prog(clk, pstate, 0); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index 61fde43dab71..8bd560d61bd8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -52,36 +52,36 @@ nvkm_fb_bios_memtype(struct nvkm_bios *bios) int _nvkm_fb_fini(struct nvkm_object *object, bool suspend) { - struct nvkm_fb *pfb = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret; - if (pfb->ram) { - ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); + if (fb->ram) { + ret = nv_ofuncs(fb->ram)->fini(nv_object(fb->ram), suspend); if (ret && suspend) return ret; } - return nvkm_subdev_fini(&pfb->base, suspend); + return nvkm_subdev_fini(&fb->subdev, suspend); } int _nvkm_fb_init(struct nvkm_object *object) { - struct nvkm_fb *pfb = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret, i; - ret = nvkm_subdev_init(&pfb->base); + ret = nvkm_subdev_init(&fb->subdev); if (ret) return ret; - if (pfb->ram) { - ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); + if (fb->ram) { + ret = nv_ofuncs(fb->ram)->init(nv_object(fb->ram)); if (ret) return ret; } - for (i = 0; i < pfb->tile.regions; i++) - pfb->tile.prog(pfb, i, &pfb->tile.region[i]); + for (i = 0; i < fb->tile.regions; i++) + fb->tile.prog(fb, i, &fb->tile.region[i]); return 0; } @@ -89,19 +89,19 @@ _nvkm_fb_init(struct nvkm_object *object) void _nvkm_fb_dtor(struct nvkm_object *object) { - struct nvkm_fb *pfb = (void *)object; + struct nvkm_fb *fb = (void *)object; int i; - for (i = 0; i < pfb->tile.regions; i++) - pfb->tile.fini(pfb, i, &pfb->tile.region[i]); - nvkm_mm_fini(&pfb->tags); + for (i = 0; i < fb->tile.regions; i++) + fb->tile.fini(fb, i, &fb->tile.region[i]); + nvkm_mm_fini(&fb->tags); - if (pfb->ram) { - nvkm_mm_fini(&pfb->vram); - nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram); + if (fb->ram) { + nvkm_mm_fini(&fb->vram); + nvkm_object_ref(NULL, (struct nvkm_object **)&fb->ram); } - nvkm_subdev_destroy(&pfb->base); + nvkm_subdev_destroy(&fb->subdev); } int @@ -123,43 +123,43 @@ nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, [NV_MEM_TYPE_GDDR5 ] = "GDDR5", }; struct nvkm_object *ram; - struct nvkm_fb *pfb; + struct nvkm_fb *fb; int ret; ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", length, pobject); - pfb = *pobject; + fb = *pobject; if (ret) return ret; - pfb->memtype_valid = impl->memtype; + fb->memtype_valid = impl->memtype; if (!impl->ram) return 0; - ret = nvkm_object_ctor(nv_object(pfb), NULL, impl->ram, NULL, 0, &ram); + ret = nvkm_object_ctor(nv_object(fb), NULL, impl->ram, NULL, 0, &ram); if (ret) { - nv_fatal(pfb, "error detecting memory configuration!!\n"); + nv_fatal(fb, "error detecting memory configuration!!\n"); return ret; } - pfb->ram = (void *)ram; + fb->ram = (void *)ram; - if (!nvkm_mm_initialised(&pfb->vram)) { - ret = nvkm_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1); + if (!nvkm_mm_initialised(&fb->vram)) { + ret = nvkm_mm_init(&fb->vram, 0, fb->ram->size >> 12, 1); if (ret) return ret; } - if (!nvkm_mm_initialised(&pfb->tags)) { - ret = nvkm_mm_init(&pfb->tags, 0, pfb->ram->tags ? - ++pfb->ram->tags : 0, 1); + if (!nvkm_mm_initialised(&fb->tags)) { + ret = nvkm_mm_init(&fb->tags, 0, fb->ram->tags ? + ++fb->ram->tags : 0, 1); if (ret) return ret; } - nv_info(pfb, "RAM type: %s\n", name[pfb->ram->type]); - nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram->size >> 20)); - nv_info(pfb, " ZCOMP: %d tags\n", pfb->ram->tags); + nv_info(fb, "RAM type: %s\n", name[fb->ram->type]); + nv_info(fb, "RAM size: %d MiB\n", (int)(fb->ram->size >> 20)); + nv_info(fb, " ZCOMP: %d tags\n", fb->ram->tags); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 5a6c2b7a6ef1..db6bbb439176 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -26,7 +26,7 @@ extern const u8 gf100_pte_storage_type_map[256]; bool -gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) +gf100_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags) { u8 memtype = (tile_flags & 0x0000ff00) >> 8; return likely((gf100_pte_storage_type_map[memtype] != 0xff)); @@ -35,32 +35,28 @@ gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) static void gf100_fb_intr(struct nvkm_subdev *subdev) { - struct gf100_fb_priv *priv = (void *)subdev; - u32 intr = nv_rd32(priv, 0x000100); - if (intr & 0x08000000) { - nv_debug(priv, "PFFB intr\n"); - intr &= ~0x08000000; - } - if (intr & 0x00002000) { - nv_debug(priv, "PBFB intr\n"); - intr &= ~0x00002000; - } + struct gf100_fb *fb = (void *)subdev; + u32 intr = nv_rd32(fb, 0x000100); + if (intr & 0x08000000) + nv_debug(fb, "PFFB intr\n"); + if (intr & 0x00002000) + nv_debug(fb, "PBFB intr\n"); } int gf100_fb_init(struct nvkm_object *object) { - struct gf100_fb_priv *priv = (void *)object; + struct gf100_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(&fb->base); if (ret) return ret; - if (priv->r100c10_page) - nv_wr32(priv, 0x100c10, priv->r100c10 >> 8); + if (fb->r100c10_page) + nv_wr32(fb, 0x100c10, fb->r100c10 >> 8); - nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ + nv_mask(fb, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ return 0; } @@ -68,15 +64,15 @@ void gf100_fb_dtor(struct nvkm_object *object) { struct nvkm_device *device = nv_device(object); - struct gf100_fb_priv *priv = (void *)object; + struct gf100_fb *fb = (void *)object; - if (priv->r100c10_page) { - dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE, + if (fb->r100c10_page) { + dma_unmap_page(nv_device_base(device), fb->r100c10, PAGE_SIZE, DMA_BIDIRECTIONAL); - __free_page(priv->r100c10_page); + __free_page(fb->r100c10_page); } - nvkm_fb_destroy(&priv->base); + nvkm_fb_destroy(&fb->base); } int @@ -85,24 +81,24 @@ gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_device *device = nv_device(parent); - struct gf100_fb_priv *priv; + struct gf100_fb *fb; int ret; - ret = nvkm_fb_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_fb_create(parent, engine, oclass, &fb); + *pobject = nv_object(fb); if (ret) return ret; - priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); - if (priv->r100c10_page) { - priv->r100c10 = dma_map_page(nv_device_base(device), - priv->r100c10_page, 0, PAGE_SIZE, + fb->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); + if (fb->r100c10_page) { + fb->r100c10 = dma_map_page(nv_device_base(device), + fb->r100c10_page, 0, PAGE_SIZE, DMA_BIDIRECTIONAL); - if (dma_mapping_error(nv_device_base(device), priv->r100c10)) + if (dma_mapping_error(nv_device_base(device), fb->r100c10)) return -EFAULT; } - nv_subdev(priv)->intr = gf100_fb_intr; + nv_subdev(fb)->intr = gf100_fb_intr; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h index 0af4da259471..add84641cd81 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -3,7 +3,7 @@ #include "priv.h" #include "nv50.h" -struct gf100_fb_priv { +struct gf100_fb { struct nvkm_fb base; struct page *r100c10_page; dma_addr_t r100c10; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c index a5d7857d3898..91c0409312cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c @@ -21,21 +21,17 @@ */ #include "gf100.h" -struct gk20a_fb_priv { - struct nvkm_fb base; -}; - static int gk20a_fb_init(struct nvkm_object *object) { - struct gk20a_fb_priv *priv = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(fb); if (ret) return ret; - nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ + nv_mask(fb, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ return 0; } @@ -44,11 +40,11 @@ gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct gk20a_fb_priv *priv; + struct nvkm_fb *fb; int ret; - ret = nvkm_fb_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_fb_create(parent, engine, oclass, &fb); + *pobject = nv_object(fb); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index c063dec7d03a..9e55308c9945 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -25,7 +25,7 @@ #include "regsnv04.h" bool -nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) +nv04_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags) { if (!(tile_flags & 0xff00)) return true; @@ -36,10 +36,10 @@ nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) static int nv04_fb_init(struct nvkm_object *object) { - struct nv04_fb_priv *priv = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(fb); if (ret) return ret; @@ -47,7 +47,7 @@ nv04_fb_init(struct nvkm_object *object) * nvidia reading PFB_CFG_0, then writing back its original value. * (which was 0x701114 in this case) */ - nv_wr32(priv, NV04_PFB_CFG0, 0x1114); + nv_wr32(fb, NV04_PFB_CFG0, 0x1114); return 0; } @@ -57,19 +57,19 @@ nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv04_fb_impl *impl = (void *)oclass; - struct nv04_fb_priv *priv; + struct nvkm_fb *fb; int ret; - ret = nvkm_fb_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_fb_create(parent, engine, oclass, &fb); + *pobject = nv_object(fb); if (ret) return ret; - priv->base.tile.regions = impl->tile.regions; - priv->base.tile.init = impl->tile.init; - priv->base.tile.comp = impl->tile.comp; - priv->base.tile.fini = impl->tile.fini; - priv->base.tile.prog = impl->tile.prog; + fb->tile.regions = impl->tile.regions; + fb->tile.init = impl->tile.init; + fb->tile.comp = impl->tile.comp; + fb->tile.fini = impl->tile.fini; + fb->tile.prog = impl->tile.prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h index caa0d03aaacc..b85ef3983539 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h @@ -2,10 +2,6 @@ #define __NVKM_FB_NV04_H__ #include "priv.h" -struct nv04_fb_priv { - struct nvkm_fb base; -}; - int nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index f3530e4a6760..b657ddc1e013 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -26,7 +26,7 @@ #include "nv04.h" void -nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +nv10_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x80000000 | addr; @@ -35,7 +35,7 @@ nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } void -nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) +nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) { tile->addr = 0; tile->limit = 0; @@ -44,12 +44,12 @@ nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) } void -nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) +nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) { - nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); - nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); - nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); - nv_rd32(pfb, 0x100240 + (i * 0x10)); + nv_wr32(fb, 0x100244 + (i * 0x10), tile->limit); + nv_wr32(fb, 0x100248 + (i * 0x10), tile->pitch); + nv_wr32(fb, 0x100240 + (i * 0x10), tile->addr); + nv_rd32(fb, 0x100240 + (i * 0x10)); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index e37084b8d05e..b1b50a41f161 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -26,25 +26,25 @@ #include "nv04.h" void -nv20_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x00000001 | addr; tile->limit = max(1u, addr + size) - 1; tile->pitch = pitch; if (flags & 4) { - pfb->tile.comp(pfb, i, size, flags, tile); + fb->tile.comp(fb, i, size, flags, tile); tile->addr |= 2; } } static void -nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, +nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); - u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + u32 tags = round_up(tiles / fb->ram->parts, 0x40); + if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -56,23 +56,23 @@ nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, } void -nv20_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) +nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) { tile->addr = 0; tile->limit = 0; tile->pitch = 0; tile->zcomp = 0; - nvkm_mm_free(&pfb->tags, &tile->tag); + nvkm_mm_free(&fb->tags, &tile->tag); } void -nv20_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) +nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) { - nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); - nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); - nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); - nv_rd32(pfb, 0x100240 + (i * 0x10)); - nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp); + nv_wr32(fb, 0x100244 + (i * 0x10), tile->limit); + nv_wr32(fb, 0x100248 + (i * 0x10), tile->pitch); + nv_wr32(fb, 0x100240 + (i * 0x10), tile->addr); + nv_rd32(fb, 0x100240 + (i * 0x10)); + nv_wr32(fb, 0x100300 + (i * 0x04), tile->zcomp); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index bc9f54f38fba..90b17004ffb2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -26,12 +26,12 @@ #include "nv04.h" static void -nv25_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, +nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); - u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + u32 tags = round_up(tiles / fb->ram->parts, 0x40); + if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 6c0b82f35d94..40c396284815 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -26,15 +26,15 @@ #include "nv04.h" void -nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) { /* for performance, select alternate bank offset for zeta */ if (!(flags & 4)) { tile->addr = (0 << 4); } else { - if (pfb->tile.comp) /* z compression */ - pfb->tile.comp(pfb, i, size, flags, tile); + if (fb->tile.comp) /* z compression */ + fb->tile.comp(fb, i, size, flags, tile); tile->addr = (1 << 4); } @@ -45,12 +45,12 @@ nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } static void -nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, +nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); - u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + u32 tags = round_up(tiles / fb->ram->parts, 0x40); + if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -62,23 +62,23 @@ nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, } static int -calc_bias(struct nv04_fb_priv *priv, int k, int i, int j) +calc_bias(struct nvkm_fb *fb, int k, int i, int j) { - struct nvkm_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(fb); int b = (device->chipset > 0x30 ? - nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : + nv_rd32(fb, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : 0) & 0xf; return 2 * (b & 0x8 ? b - 0x10 : b); } static int -calc_ref(struct nv04_fb_priv *priv, int l, int k, int i) +calc_ref(struct nvkm_fb *fb, int l, int k, int i) { int j, x = 0; for (j = 0; j < 4; j++) { - int m = (l >> (8 * i) & 0xff) + calc_bias(priv, k, i, j); + int m = (l >> (8 * i) & 0xff) + calc_bias(fb, k, i, j); x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j); } @@ -90,10 +90,10 @@ int nv30_fb_init(struct nvkm_object *object) { struct nvkm_device *device = nv_device(object); - struct nv04_fb_priv *priv = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret, i, j; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(fb); if (ret) return ret; @@ -103,16 +103,16 @@ nv30_fb_init(struct nvkm_object *object) device->chipset == 0x35) { /* Related to ROP count */ int n = (device->chipset == 0x31 ? 2 : 4); - int l = nv_rd32(priv, 0x1003d0); + int l = nv_rd32(fb, 0x1003d0); for (i = 0; i < n; i++) { for (j = 0; j < 3; j++) - nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j, - calc_ref(priv, l, 0, j)); + nv_wr32(fb, 0x10037c + 0xc * i + 0x4 * j, + calc_ref(fb, l, 0, j)); for (j = 0; j < 2; j++) - nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j, - calc_ref(priv, l, 1, j)); + nv_wr32(fb, 0x1003ac + 0x8 * i + 0x4 * j, + calc_ref(fb, l, 1, j)); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index c01dc1839ea4..7de68c6bea74 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -26,12 +26,12 @@ #include "nv04.h" static void -nv35_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, +nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); - u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + u32 tags = round_up(tiles / fb->ram->parts, 0x40); + if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index cad75a1cef22..b78062fd6a3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -26,12 +26,12 @@ #include "nv04.h" static void -nv36_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, +nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); - u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + u32 tags = round_up(tiles / fb->ram->parts, 0x40); + if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index dbe5c1910c2c..fe4ae2d7bfcb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -26,13 +26,13 @@ #include "nv04.h" void -nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, +nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x80); - u32 tags = round_up(tiles / pfb->ram->parts, 0x100); + u32 tags = round_up(tiles / fb->ram->parts, 0x100); if ( (flags & 2) && - !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; @@ -45,14 +45,14 @@ nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, static int nv40_fb_init(struct nvkm_object *object) { - struct nv04_fb_priv *priv = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(fb); if (ret) return ret; - nv_mask(priv, 0x10033c, 0x00008000, 0x00000000); + nv_mask(fb, 0x10033c, 0x00008000, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index d9e1a40a2955..ba0e6e327b6c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -26,26 +26,26 @@ #include "nv04.h" void -nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) +nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) { - nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); - nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); - nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); - nv_rd32(pfb, 0x100600 + (i * 0x10)); - nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp); + nv_wr32(fb, 0x100604 + (i * 0x10), tile->limit); + nv_wr32(fb, 0x100608 + (i * 0x10), tile->pitch); + nv_wr32(fb, 0x100600 + (i * 0x10), tile->addr); + nv_rd32(fb, 0x100600 + (i * 0x10)); + nv_wr32(fb, 0x100700 + (i * 0x04), tile->zcomp); } int nv41_fb_init(struct nvkm_object *object) { - struct nv04_fb_priv *priv = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(fb); if (ret) return ret; - nv_wr32(priv, 0x100800, 0x00000001); + nv_wr32(fb, 0x100800, 0x00000001); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index 20b97c83c4af..d6b917f70910 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -26,7 +26,7 @@ #include "nv04.h" static void -nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +nv44_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x00000001; /* mode = vram */ @@ -36,26 +36,26 @@ nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } void -nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) +nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) { - nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); - nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); - nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); - nv_rd32(pfb, 0x100600 + (i * 0x10)); + nv_wr32(fb, 0x100604 + (i * 0x10), tile->limit); + nv_wr32(fb, 0x100608 + (i * 0x10), tile->pitch); + nv_wr32(fb, 0x100600 + (i * 0x10), tile->addr); + nv_rd32(fb, 0x100600 + (i * 0x10)); } int nv44_fb_init(struct nvkm_object *object) { - struct nv04_fb_priv *priv = (void *)object; + struct nvkm_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(fb); if (ret) return ret; - nv_wr32(priv, 0x100850, 0x80000000); - nv_wr32(priv, 0x100800, 0x00000001); + nv_wr32(fb, 0x100850, 0x80000000); + nv_wr32(fb, 0x100800, 0x00000001); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index 5bfac38cdf24..1f8b69d375f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -26,7 +26,7 @@ #include "nv04.h" void -nv46_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +nv46_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) { /* for performance, select alternate bank offset for zeta */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 48fd5a5bcd3c..093d2a0ae152 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -40,7 +40,7 @@ nv50_fb_memtype[0x80] = { }; bool -nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype) +nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype) { return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0; } @@ -146,23 +146,23 @@ nv50_fb_intr(struct nvkm_subdev *subdev) { struct nvkm_device *device = nv_device(subdev); struct nvkm_engine *engine; - struct nv50_fb_priv *priv = (void *)subdev; + struct nv50_fb *fb = (void *)subdev; const struct nvkm_enum *en, *cl; struct nvkm_object *engctx = NULL; u32 trap[6], idx, chan; u8 st0, st1, st2, st3; int i; - idx = nv_rd32(priv, 0x100c90); + idx = nv_rd32(fb, 0x100c90); if (!(idx & 0x80000000)) return; idx &= 0x00ffffff; for (i = 0; i < 6; i++) { - nv_wr32(priv, 0x100c90, idx | i << 24); - trap[i] = nv_rd32(priv, 0x100c94); + nv_wr32(fb, 0x100c90, idx | i << 24); + trap[i] = nv_rd32(fb, 0x100c94); } - nv_wr32(priv, 0x100c90, idx | 0x80000000); + nv_wr32(fb, 0x100c90, idx | 0x80000000); /* decode status bits into something more useful */ if (device->chipset < 0xa3 || @@ -203,7 +203,7 @@ nv50_fb_intr(struct nvkm_subdev *subdev) en = orig_en; } - nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ", + nv_error(fb, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ", (trap[5] & 0x00000100) ? "read" : "write", trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan, nvkm_client_name(engctx)); @@ -243,26 +243,26 @@ nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_device *device = nv_device(parent); - struct nv50_fb_priv *priv; + struct nv50_fb *fb; int ret; - ret = nvkm_fb_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_fb_create(parent, engine, oclass, &fb); + *pobject = nv_object(fb); if (ret) return ret; - priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); - if (priv->r100c08_page) { - priv->r100c08 = dma_map_page(nv_device_base(device), - priv->r100c08_page, 0, PAGE_SIZE, + fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); + if (fb->r100c08_page) { + fb->r100c08 = dma_map_page(nv_device_base(device), + fb->r100c08_page, 0, PAGE_SIZE, DMA_BIDIRECTIONAL); - if (dma_mapping_error(nv_device_base(device), priv->r100c08)) + if (dma_mapping_error(nv_device_base(device), fb->r100c08)) return -EFAULT; } else { - nv_warn(priv, "failed 0x100c08 page alloc\n"); + nv_warn(fb, "failed 0x100c08 page alloc\n"); } - nv_subdev(priv)->intr = nv50_fb_intr; + nv_subdev(fb)->intr = nv50_fb_intr; return 0; } @@ -270,25 +270,25 @@ void nv50_fb_dtor(struct nvkm_object *object) { struct nvkm_device *device = nv_device(object); - struct nv50_fb_priv *priv = (void *)object; + struct nv50_fb *fb = (void *)object; - if (priv->r100c08_page) { - dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE, + if (fb->r100c08_page) { + dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE, DMA_BIDIRECTIONAL); - __free_page(priv->r100c08_page); + __free_page(fb->r100c08_page); } - nvkm_fb_destroy(&priv->base); + nvkm_fb_destroy(&fb->base); } int nv50_fb_init(struct nvkm_object *object) { struct nv50_fb_impl *impl = (void *)object->oclass; - struct nv50_fb_priv *priv = (void *)object; + struct nv50_fb *fb = (void *)object; int ret; - ret = nvkm_fb_init(&priv->base); + ret = nvkm_fb_init(&fb->base); if (ret) return ret; @@ -296,11 +296,11 @@ nv50_fb_init(struct nvkm_object *object) * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) * cause IOMMU "read from address 0" errors (rh#561267) */ - nv_wr32(priv, 0x100c08, priv->r100c08 >> 8); + nv_wr32(fb, 0x100c08, fb->r100c08 >> 8); /* This is needed to get meaningful information from 100c90 * on traps. No idea what these values mean exactly. */ - nv_wr32(priv, 0x100c90, impl->trap); + nv_wr32(fb, 0x100c90, impl->trap); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index f3cde3f1f511..002b95ae419d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -2,7 +2,7 @@ #define __NVKM_FB_NV50_H__ #include "priv.h" -struct nv50_fb_priv { +struct nv50_fb { struct nvkm_fb base; struct page *r100c08_page; dma_addr_t r100c08; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index 485c4b64819a..74eb9a22705b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -42,16 +42,16 @@ int nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts); #define nvkm_fb_create(p,e,c,d) \ nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d) #define nvkm_fb_destroy(p) ({ \ - struct nvkm_fb *pfb = (p); \ - _nvkm_fb_dtor(nv_object(pfb)); \ + struct nvkm_fb *_fb = (p); \ + _nvkm_fb_dtor(nv_object(_fb)); \ }) #define nvkm_fb_init(p) ({ \ - struct nvkm_fb *pfb = (p); \ - _nvkm_fb_init(nv_object(pfb)); \ + struct nvkm_fb *_fb = (p); \ + _nvkm_fb_init(nv_object(_fb)); \ }) #define nvkm_fb_fini(p,s) ({ \ - struct nvkm_fb *pfb = (p); \ - _nvkm_fb_fini(nv_object(pfb), (s)); \ + struct nvkm_fb *_fb = (p); \ + _nvkm_fb_fini(nv_object(_fb), (s)); \ }) int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h index f343682b1387..72ffb3a4a5d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h @@ -4,7 +4,7 @@ struct ramfuc { struct nvkm_memx *memx; - struct nvkm_fb *pfb; + struct nvkm_fb *fb; int sequence; }; @@ -54,9 +54,9 @@ ramfuc_reg(u32 addr) } static inline int -ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb) +ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb) { - struct nvkm_pmu *pmu = nvkm_pmu(pfb); + struct nvkm_pmu *pmu = nvkm_pmu(fb); int ret; ret = nvkm_memx_init(pmu, &ram->memx); @@ -64,7 +64,7 @@ ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb) return ret; ram->sequence++; - ram->pfb = pfb; + ram->fb = fb; return 0; } @@ -72,9 +72,9 @@ static inline int ramfuc_exec(struct ramfuc *ram, bool exec) { int ret = 0; - if (ram->pfb) { + if (ram->fb) { ret = nvkm_memx_fini(&ram->memx, exec); - ram->pfb = NULL; + ram->fb = NULL; } return ret; } @@ -83,7 +83,7 @@ static inline u32 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) { if (reg->sequence != ram->sequence) - reg->data = nv_rd32(ram->pfb, reg->addr); + reg->data = nv_rd32(ram->fb, reg->addr); return reg->data; } @@ -144,9 +144,9 @@ ramfuc_train(struct ramfuc *ram) } static inline int -ramfuc_train_result(struct nvkm_fb *pfb, u32 *result, u32 rsize) +ramfuc_train_result(struct nvkm_fb *fb, u32 *result, u32 rsize) { - struct nvkm_pmu *pmu = nvkm_pmu(pfb); + struct nvkm_pmu *pmu = nvkm_pmu(fb); return nvkm_memx_train_result(pmu, result, rsize); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index dcb175bea84b..ad1ce222b28f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -107,9 +107,9 @@ static void gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic) { struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nvkm_fb *pfb = nvkm_fb(ram); - u32 part = nv_rd32(pfb, 0x022438), i; - u32 mask = nv_rd32(pfb, 0x022554); + struct nvkm_fb *fb = nvkm_fb(ram); + u32 part = nv_rd32(fb, 0x022438), i; + u32 mask = nv_rd32(fb, 0x022554); u32 addr = 0x110974; ram_wr32(fuc, 0x10f910, magic); @@ -123,11 +123,11 @@ gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic) } static int -gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) +gf100_ram_calc(struct nvkm_fb *fb, u32 freq) { - struct nvkm_clk *clk = nvkm_clk(pfb); - struct nvkm_bios *bios = nvkm_bios(pfb); - struct gf100_ram *ram = (void *)pfb->ram; + struct nvkm_clk *clk = nvkm_clk(fb); + struct nvkm_bios *bios = nvkm_bios(fb); + struct gf100_ram *ram = (void *)fb->ram; struct gf100_ramfuc *fuc = &ram->fuc; struct nvbios_ramcfg cfg; u8 ver, cnt, len, strap; @@ -144,20 +144,20 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, &cnt, &ramcfg.size, &cfg); if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { - nv_error(pfb, "invalid/missing rammap entry\n"); + nv_error(fb, "invalid/missing rammap entry\n"); return -EINVAL; } /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(pfb)); + strap = nvbios_ramcfg_index(nv_subdev(fb)); if (strap >= cnt) { - nv_error(pfb, "invalid ramcfg strap\n"); + nv_error(fb, "invalid ramcfg strap\n"); return -EINVAL; } ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size); if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) { - nv_error(pfb, "invalid/missing ramcfg entry\n"); + nv_error(fb, "invalid/missing ramcfg entry\n"); return -EINVAL; } @@ -167,14 +167,14 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, &cnt, &len); if (!timing.data || ver != 0x10 || timing.size < 0x19) { - nv_error(pfb, "invalid/missing timing entry\n"); + nv_error(fb, "invalid/missing timing entry\n"); return -EINVAL; } } else { timing.data = 0; } - ret = ram_init(fuc, pfb); + ret = ram_init(fuc, fb); if (ret) return ret; @@ -209,10 +209,10 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) if (mode == 1 && from == 0) { /* calculate refpll */ - ret = gt215_pll_calc(nv_subdev(pfb), &ram->refpll, + ret = gt215_pll_calc(nv_subdev(fb), &ram->refpll, ram->mempll.refclk, &N1, NULL, &M1, &P); if (ret <= 0) { - nv_error(pfb, "unable to calc refpll\n"); + nv_error(fb, "unable to calc refpll\n"); return ret ? ret : -ERANGE; } @@ -224,10 +224,10 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); /* calculate mempll */ - ret = gt215_pll_calc(nv_subdev(pfb), &ram->mempll, freq, + ret = gt215_pll_calc(nv_subdev(fb), &ram->mempll, freq, &N1, NULL, &M1, &P); if (ret <= 0) { - nv_error(pfb, "unable to calc refpll\n"); + nv_error(fb, "unable to calc refpll\n"); return ret ? ret : -ERANGE; } @@ -401,19 +401,19 @@ gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) } static int -gf100_ram_prog(struct nvkm_fb *pfb) +gf100_ram_prog(struct nvkm_fb *fb) { - struct nvkm_device *device = nv_device(pfb); - struct gf100_ram *ram = (void *)pfb->ram; + struct nvkm_device *device = nv_device(fb); + struct gf100_ram *ram = (void *)fb->ram; struct gf100_ramfuc *fuc = &ram->fuc; ram_exec(fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -gf100_ram_tidy(struct nvkm_fb *pfb) +gf100_ram_tidy(struct nvkm_fb *fb) { - struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ram *ram = (void *)fb->ram; struct gf100_ramfuc *fuc = &ram->fuc; ram_exec(fuc, false); } @@ -421,29 +421,29 @@ gf100_ram_tidy(struct nvkm_fb *pfb) extern const u8 gf100_pte_storage_type_map[256]; void -gf100_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) +gf100_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) { - struct nvkm_ltc *ltc = nvkm_ltc(pfb); + struct nvkm_ltc *ltc = nvkm_ltc(fb); struct nvkm_mem *mem = *pmem; *pmem = NULL; if (unlikely(mem == NULL)) return; - mutex_lock(&pfb->base.mutex); + mutex_lock(&fb->subdev.mutex); if (mem->tag) ltc->tags_free(ltc, &mem->tag); - __nv50_ram_put(pfb, mem); - mutex_unlock(&pfb->base.mutex); + __nv50_ram_put(fb, mem); + mutex_unlock(&fb->subdev.mutex); kfree(mem); } int -gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, +gf100_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, u32 memtype, struct nvkm_mem **pmem) { - struct nvkm_mm *mm = &pfb->vram; + struct nvkm_mm *mm = &fb->vram; struct nvkm_mm_node *r; struct nvkm_mem *mem; int type = (memtype & 0x0ff); @@ -464,9 +464,9 @@ gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, INIT_LIST_HEAD(&mem->regions); mem->size = size; - mutex_lock(&pfb->base.mutex); + mutex_lock(&fb->subdev.mutex); if (comp) { - struct nvkm_ltc *ltc = nvkm_ltc(pfb); + struct nvkm_ltc *ltc = nvkm_ltc(fb); /* compression only works with lpages */ if (align == (1 << (17 - 12))) { @@ -485,15 +485,15 @@ gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, else ret = nvkm_mm_head(mm, 0, 1, size, ncmin, align, &r); if (ret) { - mutex_unlock(&pfb->base.mutex); - pfb->ram->put(pfb, &mem); + mutex_unlock(&fb->subdev.mutex); + fb->ram->put(fb, &mem); return ret; } list_add_tail(&r->rl_entry, &mem->regions); size -= r->length; } while (size); - mutex_unlock(&pfb->base.mutex); + mutex_unlock(&fb->subdev.mutex); r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); mem->offset = (u64)r->offset << 12; @@ -506,14 +506,14 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 maskaddr, int size, void **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); - struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_fb *fb = nvkm_fb(parent); + struct nvkm_bios *bios = nvkm_bios(fb); struct nvkm_ram *ram; const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ - u32 parts = nv_rd32(pfb, 0x022438); - u32 pmask = nv_rd32(pfb, maskaddr); - u32 bsize = nv_rd32(pfb, 0x10f20c); + u32 parts = nv_rd32(fb, 0x022438); + u32 pmask = nv_rd32(fb, maskaddr); + u32 bsize = nv_rd32(fb, 0x10f20c); u32 offset, length; bool uniform = true; int ret, part; @@ -523,23 +523,23 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800)); - nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask); + nv_debug(fb, "0x100800: 0x%08x\n", nv_rd32(fb, 0x100800)); + nv_debug(fb, "parts 0x%08x mask 0x%08x\n", parts, pmask); ram->type = nvkm_fb_bios_memtype(bios); - ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1; + ram->ranks = (nv_rd32(fb, 0x10f200) & 0x00000004) ? 2 : 1; /* read amount of vram attached to each memory controller */ for (part = 0; part < parts; part++) { if (!(pmask & (1 << part))) { - u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000)); + u32 psize = nv_rd32(fb, 0x11020c + (part * 0x1000)); if (psize != bsize) { if (psize < bsize) bsize = psize; uniform = false; } - nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize); + nv_debug(fb, "%d: mem_amount 0x%08x\n", part, psize); ram->size += (u64)psize << 20; } } @@ -548,10 +548,10 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, if (uniform) { offset = rsvd_head; length = (ram->size >> 12) - rsvd_head - rsvd_tail; - ret = nvkm_mm_init(&pfb->vram, offset, length, 1); + ret = nvkm_mm_init(&fb->vram, offset, length, 1); } else { /* otherwise, address lowest common amount from 0GiB */ - ret = nvkm_mm_init(&pfb->vram, rsvd_head, + ret = nvkm_mm_init(&fb->vram, rsvd_head, (bsize << 8) * parts - rsvd_head, 1); if (ret) return ret; @@ -560,9 +560,9 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, offset = (0x0200000000ULL >> 12) + (bsize << 8); length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail; - ret = nvkm_mm_init(&pfb->vram, offset, length, 1); + ret = nvkm_mm_init(&fb->vram, offset, length, 1); if (ret) - nvkm_mm_fini(&pfb->vram); + nvkm_mm_fini(&fb->vram); } if (ret) @@ -576,7 +576,7 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, static int gf100_ram_init(struct nvkm_object *object) { - struct nvkm_fb *pfb = (void *)object->parent; + struct nvkm_fb *fb = (void *)object->parent; struct gf100_ram *ram = (void *)object; int ret, i; @@ -601,16 +601,16 @@ gf100_ram_init(struct nvkm_object *object) }; for (i = 0; i < 0x30; i++) { - nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8)); - nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8)); - nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]); - nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]); - nv_wr32(pfb, 0x10f918, train1[i % 12]); - nv_wr32(pfb, 0x10f91c, train1[i % 12]); - nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]); - nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]); - nv_wr32(pfb, 0x10f918, train1[i % 12]); - nv_wr32(pfb, 0x10f91c, train1[i % 12]); + nv_wr32(fb, 0x10f968, 0x00000000 | (i << 8)); + nv_wr32(fb, 0x10f96c, 0x00000000 | (i << 8)); + nv_wr32(fb, 0x10f920, 0x00000100 | train0[i % 12]); + nv_wr32(fb, 0x10f924, 0x00000100 | train0[i % 12]); + nv_wr32(fb, 0x10f918, train1[i % 12]); + nv_wr32(fb, 0x10f91c, train1[i % 12]); + nv_wr32(fb, 0x10f920, 0x00000000 | train0[i % 12]); + nv_wr32(fb, 0x10f924, 0x00000000 | train0[i % 12]); + nv_wr32(fb, 0x10f918, train1[i % 12]); + nv_wr32(fb, 0x10f91c, train1[i % 12]); } } break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 97060ccfb80c..e9f3ee344a17 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -228,7 +228,7 @@ static void gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, u32 _mask, u32 _data, u32 _copy) { - struct gk104_fb_priv *priv = (void *)nvkm_fb(ram); + struct gk104_fb *fb = (void *)nvkm_fb(ram); struct ramfuc *fuc = &ram->fuc.base; u32 addr = 0x110000 + (reg->addr & 0xfff); u32 mask = _mask | _copy; @@ -237,7 +237,7 @@ gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, for (i = 0; i < 16; i++, addr += 0x1000) { if (ram->pnuts & (1 << i)) { - u32 prev = nv_rd32(priv, addr); + u32 prev = nv_rd32(fb, addr); u32 next = (prev & ~mask) | data; nvkm_memx_wr32(fuc->memx, addr, next); } @@ -247,9 +247,9 @@ gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) static int -gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq) +gk104_ram_calc_gddr5(struct nvkm_fb *fb, u32 freq) { - struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; struct nvkm_ram_data *next = ram->base.next; int vc = !next->bios.ramcfg_11_02_08; @@ -673,9 +673,9 @@ gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq) ******************************************************************************/ static int -gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq) +gk104_ram_calc_sddr3(struct nvkm_fb *fb, u32 freq) { - struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; @@ -925,9 +925,9 @@ gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq) ******************************************************************************/ static int -gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data) +gk104_ram_calc_data(struct nvkm_fb *fb, u32 khz, struct nvkm_ram_data *data) { - struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ram *ram = (void *)fb->ram; struct nvkm_ram_data *cfg; u32 mhz = khz / 1000; @@ -945,14 +945,14 @@ gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data) } static int -gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) +gk104_ram_calc_xits(struct nvkm_fb *fb, struct nvkm_ram_data *next) { - struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; int refclk, i; int ret; - ret = ram_init(fuc, pfb); + ret = ram_init(fuc, fb); if (ret) return ret; @@ -972,11 +972,11 @@ gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) refclk = fuc->mempll.refclk; /* calculate refpll coefficients */ - ret = gt215_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, + ret = gt215_pll_calc(nv_subdev(fb), &fuc->refpll, refclk, &ram->N1, &ram->fN1, &ram->M1, &ram->P1); fuc->mempll.refclk = ret; if (ret <= 0) { - nv_error(pfb, "unable to calc refpll\n"); + nv_error(fb, "unable to calc refpll\n"); return -EINVAL; } @@ -989,10 +989,10 @@ gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) fuc->mempll.min_p = 1; fuc->mempll.max_p = 2; - ret = gt215_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, + ret = gt215_pll_calc(nv_subdev(fb), &fuc->mempll, next->freq, &ram->N2, NULL, &ram->M2, &ram->P2); if (ret <= 0) { - nv_error(pfb, "unable to calc mempll\n"); + nv_error(fb, "unable to calc mempll\n"); return -EINVAL; } } @@ -1007,12 +1007,12 @@ gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) case NV_MEM_TYPE_DDR3: ret = nvkm_sddr3_calc(&ram->base); if (ret == 0) - ret = gk104_ram_calc_sddr3(pfb, next->freq); + ret = gk104_ram_calc_sddr3(fb, next->freq); break; case NV_MEM_TYPE_GDDR5: ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); if (ret == 0) - ret = gk104_ram_calc_gddr5(pfb, next->freq); + ret = gk104_ram_calc_gddr5(fb, next->freq); break; default: ret = -ENOSYS; @@ -1023,21 +1023,21 @@ gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) } static int -gk104_ram_calc(struct nvkm_fb *pfb, u32 freq) +gk104_ram_calc(struct nvkm_fb *fb, u32 freq) { - struct nvkm_clk *clk = nvkm_clk(pfb); - struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_clk *clk = nvkm_clk(fb); + struct gk104_ram *ram = (void *)fb->ram; struct nvkm_ram_data *xits = &ram->base.xition; struct nvkm_ram_data *copy; int ret; if (ram->base.next == NULL) { - ret = gk104_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), + ret = gk104_ram_calc_data(fb, clk->read(clk, nv_clk_src_mem), &ram->base.former); if (ret) return ret; - ret = gk104_ram_calc_data(pfb, freq, &ram->base.target); + ret = gk104_ram_calc_data(fb, freq, &ram->base.target); if (ret) return ret; @@ -1061,13 +1061,13 @@ gk104_ram_calc(struct nvkm_fb *pfb, u32 freq) ram->base.next = &ram->base.target; } - return gk104_ram_calc_xits(pfb, ram->base.next); + return gk104_ram_calc_xits(fb, ram->base.next); } static void -gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) +gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq) { - struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ram *ram = (void *)fb->ram; struct nvkm_ram_data *cfg; u32 mhz = freq / 1000; u32 mask, data; @@ -1089,31 +1089,31 @@ gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) data |= cfg->bios.rammap_11_09_01ff; mask |= 0x000001ff; } - nv_mask(pfb, 0x10f468, mask, data); + nv_mask(fb, 0x10f468, mask, data); if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { data |= cfg->bios.rammap_11_0a_0400; mask |= 0x00000001; } - nv_mask(pfb, 0x10f420, mask, data); + nv_mask(fb, 0x10f420, mask, data); if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { data |= cfg->bios.rammap_11_0a_0800; mask |= 0x00000001; } - nv_mask(pfb, 0x10f430, mask, data); + nv_mask(fb, 0x10f430, mask, data); if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { data |= cfg->bios.rammap_11_0b_01f0; mask |= 0x0000001f; } - nv_mask(pfb, 0x10f400, mask, data); + nv_mask(fb, 0x10f400, mask, data); if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { data |= cfg->bios.rammap_11_0b_0200 << 9; mask |= 0x00000200; } - nv_mask(pfb, 0x10f410, mask, data); + nv_mask(fb, 0x10f410, mask, data); if (mask = 0, data = 0, ram->diff.rammap_11_0d) { data |= cfg->bios.rammap_11_0d << 16; @@ -1123,7 +1123,7 @@ gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) data |= cfg->bios.rammap_11_0f << 8; mask |= 0x0000ff00; } - nv_mask(pfb, 0x10f440, mask, data); + nv_mask(fb, 0x10f440, mask, data); if (mask = 0, data = 0, ram->diff.rammap_11_0e) { data |= cfg->bios.rammap_11_0e << 8; @@ -1137,14 +1137,14 @@ gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) data |= cfg->bios.rammap_11_0b_0400 << 5; mask |= 0x00000020; } - nv_mask(pfb, 0x10f444, mask, data); + nv_mask(fb, 0x10f444, mask, data); } static int -gk104_ram_prog(struct nvkm_fb *pfb) +gk104_ram_prog(struct nvkm_fb *fb) { - struct nvkm_device *device = nv_device(pfb); - struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_device *device = nv_device(fb); + struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; struct nvkm_ram_data *next = ram->base.next; @@ -1153,17 +1153,17 @@ gk104_ram_prog(struct nvkm_fb *pfb) return (ram->base.next == &ram->base.xition); } - gk104_ram_prog_0(pfb, 1000); + gk104_ram_prog_0(fb, 1000); ram_exec(fuc, true); - gk104_ram_prog_0(pfb, next->freq); + gk104_ram_prog_0(fb, next->freq); return (ram->base.next == &ram->base.xition); } static void -gk104_ram_tidy(struct nvkm_fb *pfb) +gk104_ram_tidy(struct nvkm_fb *fb) { - struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; ram->base.next = NULL; ram_exec(fuc, false); @@ -1182,10 +1182,10 @@ struct gk104_ram_train { }; static int -gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg, +gk104_ram_train_type(struct nvkm_fb *fb, int i, u8 ramcfg, struct gk104_ram_train *train) { - struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(fb); struct nvbios_M0205E M0205E; struct nvbios_M0205S M0205S; struct nvbios_M0209E M0209E; @@ -1243,33 +1243,33 @@ gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg, } static int -gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train) +gk104_ram_train_init_0(struct nvkm_fb *fb, struct gk104_ram_train *train) { int i, j; if ((train->mask & 0x03d3) != 0x03d3) { - nv_warn(pfb, "missing link training data\n"); + nv_warn(fb, "missing link training data\n"); return -EINVAL; } for (i = 0; i < 0x30; i++) { for (j = 0; j < 8; j += 4) { - nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8)); - nv_wr32(pfb, 0x10f920 + j, 0x00000000 | + nv_wr32(fb, 0x10f968 + j, 0x00000000 | (i << 8)); + nv_wr32(fb, 0x10f920 + j, 0x00000000 | train->type08.data[i] << 4 | train->type06.data[i]); - nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]); - nv_wr32(pfb, 0x10f920 + j, 0x00000100 | + nv_wr32(fb, 0x10f918 + j, train->type00.data[i]); + nv_wr32(fb, 0x10f920 + j, 0x00000100 | train->type09.data[i] << 4 | train->type07.data[i]); - nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]); + nv_wr32(fb, 0x10f918 + j, train->type01.data[i]); } } for (j = 0; j < 8; j += 4) { for (i = 0; i < 0x100; i++) { - nv_wr32(pfb, 0x10f968 + j, i); - nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]); + nv_wr32(fb, 0x10f968 + j, i); + nv_wr32(fb, 0x10f900 + j, train->type04.data[i]); } } @@ -1277,23 +1277,24 @@ gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train) } static int -gk104_ram_train_init(struct nvkm_fb *pfb) +gk104_ram_train_init(struct nvkm_fb *fb) { - u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); + u8 ramcfg = nvbios_ramcfg_index(nv_subdev(fb)); struct gk104_ram_train *train; - int ret = -ENOMEM, i; + int ret, i; - if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) { - for (i = 0; i < 0x100; i++) { - ret = gk104_ram_train_type(pfb, i, ramcfg, train); - if (ret && ret != -ENOENT) - break; - } + if (!(train = kzalloc(sizeof(*train), GFP_KERNEL))) + return -ENOMEM; + + for (i = 0; i < 0x100; i++) { + ret = gk104_ram_train_type(fb, i, ramcfg, train); + if (ret && ret != -ENOENT) + break; } - switch (pfb->ram->type) { + switch (fb->ram->type) { case NV_MEM_TYPE_GDDR5: - ret = gk104_ram_train_init_0(pfb, train); + ret = gk104_ram_train_init_0(fb, train); break; default: ret = 0; @@ -1307,9 +1308,9 @@ gk104_ram_train_init(struct nvkm_fb *pfb) int gk104_ram_init(struct nvkm_object *object) { - struct nvkm_fb *pfb = (void *)object->parent; + struct nvkm_fb *fb = (void *)object->parent; struct gk104_ram *ram = (void *)object; - struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(fb); u8 ver, hdr, cnt, len, snr, ssz; u32 data, save; int ret, i; @@ -1335,31 +1336,31 @@ gk104_ram_init(struct nvkm_object *object) cnt = nv_ro08(bios, data + 0x14); /* guess at count */ data = nv_ro32(bios, data + 0x10); /* guess u32... */ - save = nv_rd32(pfb, 0x10f65c) & 0x000000f0; + save = nv_rd32(fb, 0x10f65c) & 0x000000f0; for (i = 0; i < cnt; i++, data += 4) { if (i != save >> 4) { - nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); + nv_mask(fb, 0x10f65c, 0x000000f0, i << 4); nvbios_exec(&(struct nvbios_init) { - .subdev = nv_subdev(pfb), + .subdev = nv_subdev(fb), .bios = bios, .offset = nv_ro32(bios, data), .execute = 1, }); } } - nv_mask(pfb, 0x10f65c, 0x000000f0, save); - nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); - nv_wr32(pfb, 0x10ecc0, 0xffffffff); - nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010); + nv_mask(fb, 0x10f65c, 0x000000f0, save); + nv_mask(fb, 0x10f584, 0x11000000, 0x00000000); + nv_wr32(fb, 0x10ecc0, 0xffffffff); + nv_mask(fb, 0x10f160, 0x00000010, 0x00000010); - return gk104_ram_train_init(pfb); + return gk104_ram_train_init(fb); } static int gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) { - struct nvkm_fb *pfb = (void *)nv_object(ram)->parent; - struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_fb *fb = (void *)nv_object(ram)->parent; + struct nvkm_bios *bios = nvkm_bios(fb); struct nvkm_ram_data *cfg; struct nvbios_ramcfg *d = &ram->diff; struct nvbios_ramcfg *p, *n; @@ -1443,13 +1444,13 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); - struct nvkm_bios *bios = nvkm_bios(pfb); - struct nvkm_gpio *gpio = nvkm_gpio(pfb); + struct nvkm_fb *fb = nvkm_fb(parent); + struct nvkm_bios *bios = nvkm_bios(fb); + struct nvkm_gpio *gpio = nvkm_gpio(fb); struct dcb_gpio_func func; struct gk104_ram *ram; int ret, i; - u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); + u8 ramcfg = nvbios_ramcfg_index(nv_subdev(fb)); u32 tmp; ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); @@ -1467,7 +1468,7 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ram->base.tidy = gk104_ram_tidy; break; default: - nv_warn(pfb, "reclocking of this RAM type is unsupported\n"); + nv_warn(fb, "reclocking of this RAM type is unsupported\n"); break; } @@ -1476,12 +1477,12 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, * already without having to treat some of them differently to * the others.... */ - ram->parts = nv_rd32(pfb, 0x022438); - ram->pmask = nv_rd32(pfb, 0x022554); + ram->parts = nv_rd32(fb, 0x022438); + ram->pmask = nv_rd32(fb, 0x022554); ram->pnuts = 0; for (i = 0, tmp = 0; i < ram->parts; i++) { if (!(ram->pmask & (1 << i))) { - u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); + u32 cfg1 = nv_rd32(fb, 0x110204 + (i * 0x1000)); if (tmp && tmp != cfg1) { ram->pnuts |= (1 << i); continue; @@ -1504,7 +1505,7 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, for (i = 0; !ret; i++) { ret = gk104_ram_ctor_data(ram, ramcfg, i); if (ret && ret != -ENOENT) { - nv_error(pfb, "failed to parse ramcfg data\n"); + nv_error(fb, "failed to parse ramcfg data\n"); return ret; } } @@ -1512,13 +1513,13 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, /* parse bios data for both pll's */ ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); if (ret) { - nv_error(pfb, "mclk refpll data not found\n"); + nv_error(fb, "mclk refpll data not found\n"); return ret; } ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll); if (ret) { - nv_error(pfb, "mclk pll data not found\n"); + nv_error(fb, "mclk pll data not found\n"); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c index a298b39f55c5..40079eb44e70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c @@ -23,16 +23,12 @@ */ #include "gf100.h" -struct gm107_ram { - struct nvkm_ram base; -}; - static int gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct gm107_ram *ram; + struct nvkm_ram *ram; int ret; ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index 1d604c075a3c..2195e4be68eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -153,13 +153,13 @@ gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) * Link training for (at least) DDR3 */ int -gt215_link_train(struct nvkm_fb *pfb) +gt215_link_train(struct nvkm_fb *fb) { - struct nvkm_bios *bios = nvkm_bios(pfb); - struct gt215_ram *ram = (void *)pfb->ram; - struct nvkm_clk *clk = nvkm_clk(pfb); + struct nvkm_bios *bios = nvkm_bios(fb); + struct gt215_ram *ram = (void *)fb->ram; + struct nvkm_clk *clk = nvkm_clk(fb); struct gt215_ltrain *train = &ram->ltrain; - struct nvkm_device *device = nv_device(pfb); + struct nvkm_device *device = nv_device(fb); struct gt215_ramfuc *fuc = &ram->fuc; u32 *result, r1700; int ret, i; @@ -181,8 +181,10 @@ gt215_link_train(struct nvkm_fb *pfb) /* Clock speeds for training and back */ nvbios_M0205Tp(bios, &ver, &hdr, &cnt, &len, &snr, &ssz, &M0205T); - if (M0205T.freq == 0) + if (M0205T.freq == 0) { + kfree(result); return -ENOENT; + } clk_current = clk->read(clk, nv_clk_src_mem); @@ -191,17 +193,17 @@ gt215_link_train(struct nvkm_fb *pfb) goto out; /* First: clock up/down */ - ret = ram->base.calc(pfb, (u32) M0205T.freq * 1000); + ret = ram->base.calc(fb, (u32) M0205T.freq * 1000); if (ret) goto out; /* Do this *after* calc, eliminates write in script */ - nv_wr32(pfb, 0x111400, 0x00000000); + nv_wr32(fb, 0x111400, 0x00000000); /* XXX: Magic writes that improve train reliability? */ - nv_mask(pfb, 0x100674, 0x0000ffff, 0x00000000); - nv_mask(pfb, 0x1005e4, 0x0000ffff, 0x00000000); - nv_mask(pfb, 0x100b0c, 0x000000ff, 0x00000000); - nv_wr32(pfb, 0x100c04, 0x00000400); + nv_mask(fb, 0x100674, 0x0000ffff, 0x00000000); + nv_mask(fb, 0x1005e4, 0x0000ffff, 0x00000000); + nv_mask(fb, 0x100b0c, 0x000000ff, 0x00000000); + nv_wr32(fb, 0x100c04, 0x00000400); /* Now the training script */ r1700 = ram_rd32(fuc, 0x001700); @@ -234,21 +236,21 @@ gt215_link_train(struct nvkm_fb *pfb) ram_exec(fuc, true); - ram->base.calc(pfb, clk_current); + ram->base.calc(fb, clk_current); ram_exec(fuc, true); /* Post-processing, avoids flicker */ - nv_mask(pfb, 0x616308, 0x10, 0x10); - nv_mask(pfb, 0x616b08, 0x10, 0x10); + nv_mask(fb, 0x616308, 0x10, 0x10); + nv_mask(fb, 0x616b08, 0x10, 0x10); gt215_clk_post(clk, f); - ram_train_result(pfb, result, 64); + ram_train_result(fb, result, 64); for (i = 0; i < 64; i++) - nv_debug(pfb, "Train: %08x", result[i]); + nv_debug(fb, "Train: %08x", result[i]); gt215_link_train_calc(result, train); - nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720, + nv_debug(fb, "Train: %08x %08x %08x", train->r_100720, train->r_1111e0, train->r_111400); kfree(result); @@ -264,11 +266,12 @@ out: train->state = NVA3_TRAIN_UNSUPPORTED; gt215_clk_post(clk, f); + kfree(result); return ret; } int -gt215_link_train_init(struct nvkm_fb *pfb) +gt215_link_train_init(struct nvkm_fb *fb) { static const u32 pattern[16] = { 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, @@ -276,8 +279,8 @@ gt215_link_train_init(struct nvkm_fb *pfb) 0x33333333, 0x55555555, 0x77777777, 0x66666666, 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, }; - struct nvkm_bios *bios = nvkm_bios(pfb); - struct gt215_ram *ram = (void *)pfb->ram; + struct nvkm_bios *bios = nvkm_bios(fb); + struct gt215_ram *ram = (void *)fb->ram; struct gt215_ltrain *train = &ram->ltrain; struct nvkm_mem *mem; struct nvbios_M0205E M0205E; @@ -297,48 +300,48 @@ gt215_link_train_init(struct nvkm_fb *pfb) train->state = NVA3_TRAIN_ONCE; - ret = pfb->ram->get(pfb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem); + ret = fb->ram->get(fb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem); if (ret) return ret; mem = ram->ltrain.mem; - nv_wr32(pfb, 0x100538, 0x10000000 | (mem->offset >> 16)); - nv_wr32(pfb, 0x1005a8, 0x0000ffff); - nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001); + nv_wr32(fb, 0x100538, 0x10000000 | (mem->offset >> 16)); + nv_wr32(fb, 0x1005a8, 0x0000ffff); + nv_mask(fb, 0x10f800, 0x00000001, 0x00000001); for (i = 0; i < 0x30; i++) { - nv_wr32(pfb, 0x10f8c0, (i << 8) | i); - nv_wr32(pfb, 0x10f900, pattern[i % 16]); + nv_wr32(fb, 0x10f8c0, (i << 8) | i); + nv_wr32(fb, 0x10f900, pattern[i % 16]); } for (i = 0; i < 0x30; i++) { - nv_wr32(pfb, 0x10f8e0, (i << 8) | i); - nv_wr32(pfb, 0x10f920, pattern[i % 16]); + nv_wr32(fb, 0x10f8e0, (i << 8) | i); + nv_wr32(fb, 0x10f920, pattern[i % 16]); } /* And upload the pattern */ - r001700 = nv_rd32(pfb, 0x1700); - nv_wr32(pfb, 0x1700, mem->offset >> 16); + r001700 = nv_rd32(fb, 0x1700); + nv_wr32(fb, 0x1700, mem->offset >> 16); for (i = 0; i < 16; i++) - nv_wr32(pfb, 0x700000 + (i << 2), pattern[i]); + nv_wr32(fb, 0x700000 + (i << 2), pattern[i]); for (i = 0; i < 16; i++) - nv_wr32(pfb, 0x700100 + (i << 2), pattern[i]); - nv_wr32(pfb, 0x1700, r001700); + nv_wr32(fb, 0x700100 + (i << 2), pattern[i]); + nv_wr32(fb, 0x1700, r001700); - train->r_100720 = nv_rd32(pfb, 0x100720); - train->r_1111e0 = nv_rd32(pfb, 0x1111e0); - train->r_111400 = nv_rd32(pfb, 0x111400); + train->r_100720 = nv_rd32(fb, 0x100720); + train->r_1111e0 = nv_rd32(fb, 0x1111e0); + train->r_111400 = nv_rd32(fb, 0x111400); return 0; } void -gt215_link_train_fini(struct nvkm_fb *pfb) +gt215_link_train_fini(struct nvkm_fb *fb) { - struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)fb->ram; if (ram->ltrain.mem) - pfb->ram->put(pfb, &ram->ltrain.mem); + fb->ram->put(fb, &ram->ltrain.mem); } /* @@ -346,17 +349,17 @@ gt215_link_train_fini(struct nvkm_fb *pfb) */ #define T(t) cfg->timing_10_##t static int -gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) +gt215_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) { - struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)fb->ram; struct nvbios_ramcfg *cfg = &ram->base.target.bios; int tUNK_base, tUNK_40_0, prevCL; u32 cur2, cur3, cur7, cur8; - cur2 = nv_rd32(pfb, 0x100228); - cur3 = nv_rd32(pfb, 0x10022c); - cur7 = nv_rd32(pfb, 0x10023c); - cur8 = nv_rd32(pfb, 0x100240); + cur2 = nv_rd32(fb, 0x100228); + cur3 = nv_rd32(fb, 0x10022c); + cur7 = nv_rd32(fb, 0x10023c); + cur8 = nv_rd32(fb, 0x100240); switch ((!T(CWL)) * ram->base.type) { @@ -411,11 +414,11 @@ gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) break; } - nv_debug(pfb, "Entry: 220: %08x %08x %08x %08x\n", + nv_debug(fb, "Entry: 220: %08x %08x %08x %08x\n", timing[0], timing[1], timing[2], timing[3]); - nv_debug(pfb, " 230: %08x %08x %08x %08x\n", + nv_debug(fb, " 230: %08x %08x %08x %08x\n", timing[4], timing[5], timing[6], timing[7]); - nv_debug(pfb, " 240: %08x\n", timing[8]); + nv_debug(fb, " 240: %08x\n", timing[8]); return 0; } #undef T @@ -465,7 +468,7 @@ gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk) static void gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) { - struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.pfb); + struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.fb); struct dcb_gpio_func func; u32 reg, sh, gpio_val; int ret; @@ -486,10 +489,10 @@ gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) } static int -gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) +gt215_ram_calc(struct nvkm_fb *fb, u32 freq) { - struct nvkm_bios *bios = nvkm_bios(pfb); - struct gt215_ram *ram = (void *)pfb->ram; + struct nvkm_bios *bios = nvkm_bios(fb); + struct gt215_ram *ram = (void *)fb->ram; struct gt215_ramfuc *fuc = &ram->fuc; struct gt215_ltrain *train = &ram->ltrain; struct gt215_clk_info mclk; @@ -507,28 +510,27 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) ram->base.next = next; if (ram->ltrain.state == NVA3_TRAIN_ONCE) - gt215_link_train(pfb); + gt215_link_train(fb); /* lookup memory config data relevant to the target frequency */ - i = 0; data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len, &next->bios); if (!data || ver != 0x10 || hdr < 0x05) { - nv_error(pfb, "invalid/missing rammap entry\n"); + nv_error(fb, "invalid/missing rammap entry\n"); return -EINVAL; } /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(pfb)); + strap = nvbios_ramcfg_index(nv_subdev(fb)); if (strap >= cnt) { - nv_error(pfb, "invalid ramcfg strap\n"); + nv_error(fb, "invalid ramcfg strap\n"); return -EINVAL; } data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap, &ver, &hdr, &next->bios); if (!data || ver != 0x10 || hdr < 0x09) { - nv_error(pfb, "invalid/missing ramcfg entry\n"); + nv_error(fb, "invalid/missing ramcfg entry\n"); return -EINVAL; } @@ -538,20 +540,20 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) &ver, &hdr, &cnt, &len, &next->bios); if (!data || ver != 0x10 || hdr < 0x17) { - nv_error(pfb, "invalid/missing timing entry\n"); + nv_error(fb, "invalid/missing timing entry\n"); return -EINVAL; } } - ret = gt215_pll_info(nvkm_clk(pfb), 0x12, 0x4000, freq, &mclk); + ret = gt215_pll_info(nvkm_clk(fb), 0x12, 0x4000, freq, &mclk); if (ret < 0) { - nv_error(pfb, "failed mclk calculation\n"); + nv_error(fb, "failed mclk calculation\n"); return ret; } - gt215_ram_timing_calc(pfb, timing); + gt215_ram_timing_calc(fb, timing); - ret = ram_init(fuc, pfb); + ret = ram_init(fuc, fb); if (ret) return ret; @@ -649,7 +651,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) ram_wr32(fuc, 0x1002dc, 0x00000001); ram_nsec(fuc, 2000); - if (nv_device(pfb)->chipset == 0xa3 && freq <= 500000) + if (nv_device(fb)->chipset == 0xa3 && freq <= 500000) ram_mask(fuc, 0x100700, 0x00000006, 0x00000006); /* Fiddle with clocks */ @@ -707,7 +709,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) ram_mask(fuc, 0x1007e0, 0x22222222, r100760); } - if (nv_device(pfb)->chipset == 0xa3 && freq > 500000) { + if (nv_device(fb)->chipset == 0xa3 && freq > 500000) { ram_mask(fuc, 0x100700, 0x00000006, 0x00000000); } @@ -752,7 +754,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) if (next->bios.ramcfg_10_02_04) { switch (ram->base.type) { case NV_MEM_TYPE_DDR3: - if (nv_device(pfb)->chipset != 0xa8) + if (nv_device(fb)->chipset != 0xa8) r111100 |= 0x00000004; /* no break */ case NV_MEM_TYPE_DDR2: @@ -768,7 +770,7 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) unk714 |= 0x00000010; break; case NV_MEM_TYPE_DDR3: - if (nv_device(pfb)->chipset == 0xa8) { + if (nv_device(fb)->chipset == 0xa8) { r111100 |= 0x08000000; } else { r111100 &= ~0x00000004; @@ -854,24 +856,24 @@ gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) } static int -gt215_ram_prog(struct nvkm_fb *pfb) +gt215_ram_prog(struct nvkm_fb *fb) { - struct nvkm_device *device = nv_device(pfb); - struct gt215_ram *ram = (void *)pfb->ram; + struct nvkm_device *device = nv_device(fb); + struct gt215_ram *ram = (void *)fb->ram; struct gt215_ramfuc *fuc = &ram->fuc; bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true); if (exec) { - nv_mask(pfb, 0x001534, 0x2, 0x2); + nv_mask(fb, 0x001534, 0x2, 0x2); ram_exec(fuc, true); /* Post-processing, avoids flicker */ - nv_mask(pfb, 0x002504, 0x1, 0x0); - nv_mask(pfb, 0x001534, 0x2, 0x0); + nv_mask(fb, 0x002504, 0x1, 0x0); + nv_mask(fb, 0x001534, 0x2, 0x0); - nv_mask(pfb, 0x616308, 0x10, 0x10); - nv_mask(pfb, 0x616b08, 0x10, 0x10); + nv_mask(fb, 0x616308, 0x10, 0x10); + nv_mask(fb, 0x616b08, 0x10, 0x10); } else { ram_exec(fuc, false); } @@ -879,9 +881,9 @@ gt215_ram_prog(struct nvkm_fb *pfb) } static void -gt215_ram_tidy(struct nvkm_fb *pfb) +gt215_ram_tidy(struct nvkm_fb *fb) { - struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)fb->ram; struct gt215_ramfuc *fuc = &ram->fuc; ram_exec(fuc, false); } @@ -889,7 +891,7 @@ gt215_ram_tidy(struct nvkm_fb *pfb) static int gt215_ram_init(struct nvkm_object *object) { - struct nvkm_fb *pfb = (void *)object->parent; + struct nvkm_fb *fb = (void *)object->parent; struct gt215_ram *ram = (void *)object; int ret; @@ -897,17 +899,17 @@ gt215_ram_init(struct nvkm_object *object) if (ret) return ret; - gt215_link_train_init(pfb); + gt215_link_train_init(fb); return 0; } static int gt215_ram_fini(struct nvkm_object *object, bool suspend) { - struct nvkm_fb *pfb = (void *)object->parent; + struct nvkm_fb *fb = (void *)object->parent; if (!suspend) - gt215_link_train_fini(pfb); + gt215_link_train_fini(fb); return 0; } @@ -917,8 +919,8 @@ gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 datasize, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); - struct nvkm_gpio *gpio = nvkm_gpio(pfb); + struct nvkm_fb *fb = nvkm_fb(parent); + struct nvkm_gpio *gpio = nvkm_gpio(fb); struct dcb_gpio_func func; struct gt215_ram *ram; int ret, i; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c index abc18e89a97c..7f378788d3e5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c @@ -23,7 +23,7 @@ */ #include "nv50.h" -struct mcp77_ram_priv { +struct mcp77_ram { struct nvkm_ram base; u64 poller_base; }; @@ -35,58 +35,58 @@ mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, { u32 rsvd_head = ( 256 * 1024); /* vga memory */ u32 rsvd_tail = (1024 * 1024); /* vbios etc */ - struct nvkm_fb *pfb = nvkm_fb(parent); - struct mcp77_ram_priv *priv; + struct nvkm_fb *fb = nvkm_fb(parent); + struct mcp77_ram *ram; int ret; - ret = nvkm_ram_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_ram_create(parent, engine, oclass, &ram); + *pobject = nv_object(fb); if (ret) return ret; - priv->base.type = NV_MEM_TYPE_STOLEN; - priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; - priv->base.size = (u64)nv_rd32(pfb, 0x100e14) << 12; + ram->base.type = NV_MEM_TYPE_STOLEN; + ram->base.stolen = (u64)nv_rd32(fb, 0x100e10) << 12; + ram->base.size = (u64)nv_rd32(fb, 0x100e14) << 12; rsvd_tail += 0x1000; - priv->poller_base = priv->base.size - rsvd_tail; + ram->poller_base = ram->base.size - rsvd_tail; - ret = nvkm_mm_init(&pfb->vram, rsvd_head >> 12, - (priv->base.size - (rsvd_head + rsvd_tail)) >> 12, + ret = nvkm_mm_init(&fb->vram, rsvd_head >> 12, + (ram->base.size - (rsvd_head + rsvd_tail)) >> 12, 1); if (ret) return ret; - priv->base.get = nv50_ram_get; - priv->base.put = nv50_ram_put; + ram->base.get = nv50_ram_get; + ram->base.put = nv50_ram_put; return 0; } static int mcp77_ram_init(struct nvkm_object *object) { - struct nvkm_fb *pfb = nvkm_fb(object); - struct mcp77_ram_priv *priv = (void *)object; + struct nvkm_fb *fb = nvkm_fb(object); + struct mcp77_ram *ram = (void *)object; int ret; u64 dniso, hostnb, flush; - ret = nvkm_ram_init(&priv->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; - dniso = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1; - hostnb = ((priv->base.size - (priv->poller_base + 0x20)) >> 5) - 1; - flush = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1; + dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; + hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; + flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; /* Enable NISO poller for various clients and set their associated * read address, only for MCP77/78 and MCP79/7A. (fd#25701) */ - nv_wr32(pfb, 0x100c18, dniso); - nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001); - nv_wr32(pfb, 0x100c1c, hostnb); - nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002); - nv_wr32(pfb, 0x100c24, flush); - nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000); + nv_wr32(fb, 0x100c18, dniso); + nv_mask(fb, 0x100c14, 0x00000000, 0x00000001); + nv_wr32(fb, 0x100c1c, hostnb); + nv_mask(fb, 0x100c14, 0x00000000, 0x00000002); + nv_wr32(fb, 0x100c24, flush); + nv_mask(fb, 0x100c14, 0x00000000, 0x00010000); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c index 855de1617229..12311c56c4a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c @@ -29,9 +29,9 @@ nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ram *ram; - u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0); + u32 boot0 = nv_rd32(fb, NV04_PFB_BOOT_0); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c index 3b8a1eda5b64..0999ac2e4771 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c @@ -28,9 +28,9 @@ nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ram *ram; - u32 cfg0 = nv_rd32(pfb, 0x100200); + u32 cfg0 = nv_rd32(fb, 0x100200); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); @@ -43,7 +43,7 @@ nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, else ram->type = NV_MEM_TYPE_SDRAM; - ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; + ram->size = nv_rd32(fb, 0x10020c) & 0xff000000; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c index 8bb7e432ad04..98b14b03d743 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c @@ -28,7 +28,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ram *ram; struct pci_dev *bridge; u32 mem, mib; @@ -36,7 +36,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); if (!bridge) { - nv_fatal(pfb, "no bridge device\n"); + nv_fatal(fb, "no bridge device\n"); return -ENODEV; } @@ -45,7 +45,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - if (nv_device(pfb)->chipset == 0x1a) { + if (nv_device(fb)->chipset == 0x1a) { pci_read_config_dword(bridge, 0x7c, &mem); mib = ((mem >> 6) & 31) + 1; } else { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c index d9e7187bd235..929fa1678444 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c @@ -28,9 +28,9 @@ nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ram *ram; - u32 pbus1218 = nv_rd32(pfb, 0x001218); + u32 pbus1218 = nv_rd32(fb, 0x001218); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); @@ -44,9 +44,9 @@ nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break; case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break; } - ram->size = (nv_rd32(pfb, 0x10020c) & 0xff000000); - ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; - ram->tags = nv_rd32(pfb, 0x100320); + ram->size = (nv_rd32(fb, 0x10020c) & 0xff000000); + ram->parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1; + ram->tags = nv_rd32(fb, 0x100320); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index a36a90c29ba9..bf795846bd8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -31,21 +31,21 @@ #include int -nv40_ram_calc(struct nvkm_fb *pfb, u32 freq) +nv40_ram_calc(struct nvkm_fb *fb, u32 freq) { - struct nvkm_bios *bios = nvkm_bios(pfb); - struct nv40_ram *ram = (void *)pfb->ram; + struct nvkm_bios *bios = nvkm_bios(fb); + struct nv40_ram *ram = (void *)fb->ram; struct nvbios_pll pll; int N1, M1, N2, M2; int log2P, ret; ret = nvbios_pll_parse(bios, 0x04, &pll); if (ret) { - nv_error(pfb, "mclk pll data not found\n"); + nv_error(fb, "mclk pll data not found\n"); return ret; } - ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq, + ret = nv04_pll_calc(nv_subdev(fb), &pll, freq, &N1, &M1, &N2, &M2, &log2P); if (ret < 0) return ret; @@ -64,10 +64,10 @@ nv40_ram_calc(struct nvkm_fb *pfb, u32 freq) } int -nv40_ram_prog(struct nvkm_fb *pfb) +nv40_ram_prog(struct nvkm_fb *fb) { - struct nvkm_bios *bios = nvkm_bios(pfb); - struct nv40_ram *ram = (void *)pfb->ram; + struct nvkm_bios *bios = nvkm_bios(fb); + struct nv40_ram *ram = (void *)fb->ram; struct bit_entry M; u32 crtc_mask = 0; u8 sr1[2]; @@ -75,12 +75,12 @@ nv40_ram_prog(struct nvkm_fb *pfb) /* determine which CRTCs are active, fetch VGA_SR1 for each */ for (i = 0; i < 2; i++) { - u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000)); + u32 vbl = nv_rd32(fb, 0x600808 + (i * 0x2000)); u32 cnt = 0; do { - if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) { - nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01); - sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000)); + if (vbl != nv_rd32(fb, 0x600808 + (i * 0x2000))) { + nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01); + sr1[i] = nv_rd08(fb, 0x0c03c5 + (i * 0x2000)); if (!(sr1[i] & 0x20)) crtc_mask |= (1 << i); break; @@ -93,53 +93,53 @@ nv40_ram_prog(struct nvkm_fb *pfb) for (i = 0; i < 2; i++) { if (!(crtc_mask & (1 << i))) continue; - nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000); - nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); - nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01); - nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); + nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000); + nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); + nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01); + nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); } /* prepare ram for reclocking */ - nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */ - nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */ - nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */ - nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ - nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */ + nv_wr32(fb, 0x1002d4, 0x00000001); /* precharge */ + nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */ + nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */ + nv_mask(fb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ + nv_wr32(fb, 0x1002dc, 0x00000001); /* enable self-refresh */ /* change the PLL of each memory partition */ - nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000); - switch (nv_device(pfb)->chipset) { + nv_mask(fb, 0x00c040, 0x0000c000, 0x00000000); + switch (nv_device(fb)->chipset) { case 0x40: case 0x45: case 0x41: case 0x42: case 0x47: - nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl); - nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl); - nv_wr32(pfb, 0x004048, ram->coef); - nv_wr32(pfb, 0x004030, ram->coef); + nv_mask(fb, 0x004044, 0xc0771100, ram->ctrl); + nv_mask(fb, 0x00402c, 0xc0771100, ram->ctrl); + nv_wr32(fb, 0x004048, ram->coef); + nv_wr32(fb, 0x004030, ram->coef); case 0x43: case 0x49: case 0x4b: - nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl); - nv_wr32(pfb, 0x00403c, ram->coef); + nv_mask(fb, 0x004038, 0xc0771100, ram->ctrl); + nv_wr32(fb, 0x00403c, ram->coef); default: - nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl); - nv_wr32(pfb, 0x004024, ram->coef); + nv_mask(fb, 0x004020, 0xc0771100, ram->ctrl); + nv_wr32(fb, 0x004024, ram->coef); break; } udelay(100); - nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000); + nv_mask(fb, 0x00c040, 0x0000c000, 0x0000c000); /* re-enable normal operation of memory controller */ - nv_wr32(pfb, 0x1002dc, 0x00000000); - nv_mask(pfb, 0x100210, 0x80000000, 0x80000000); + nv_wr32(fb, 0x1002dc, 0x00000000); + nv_mask(fb, 0x100210, 0x80000000, 0x80000000); udelay(100); /* execute memory reset script from vbios */ if (!bit_entry(bios, 'M', &M)) { struct nvbios_init init = { - .subdev = nv_subdev(pfb), + .subdev = nv_subdev(fb), .bios = bios, .offset = nv_ro16(bios, M.offset + 0x00), .execute = 1, @@ -154,16 +154,16 @@ nv40_ram_prog(struct nvkm_fb *pfb) for (i = 0; i < 2; i++) { if (!(crtc_mask & (1 << i))) continue; - nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); - nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01); - nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]); + nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); + nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01); + nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i]); } return 0; } void -nv40_ram_tidy(struct nvkm_fb *pfb) +nv40_ram_tidy(struct nvkm_fb *fb) { } @@ -172,9 +172,9 @@ nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nv40_ram *ram; - u32 pbus1218 = nv_rd32(pfb, 0x001218); + u32 pbus1218 = nv_rd32(fb, 0x001218); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); @@ -189,9 +189,9 @@ nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break; } - ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; - ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; - ram->base.tags = nv_rd32(pfb, 0x100320); + ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000; + ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1; + ram->base.tags = nv_rd32(fb, 0x100320); ram->base.calc = nv40_ram_calc; ram->base.prog = nv40_ram_prog; ram->base.tidy = nv40_ram_tidy; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c index 33c612b1355f..ba0bca729012 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c @@ -28,9 +28,9 @@ nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nv40_ram *ram; - u32 pfb474 = nv_rd32(pfb, 0x100474); + u32 fb474 = nv_rd32(fb, 0x100474); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); @@ -38,16 +38,16 @@ nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - if (pfb474 & 0x00000004) + if (fb474 & 0x00000004) ram->base.type = NV_MEM_TYPE_GDDR3; - if (pfb474 & 0x00000002) + if (fb474 & 0x00000002) ram->base.type = NV_MEM_TYPE_DDR2; - if (pfb474 & 0x00000001) + if (fb474 & 0x00000001) ram->base.type = NV_MEM_TYPE_DDR1; - ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; - ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; - ram->base.tags = nv_rd32(pfb, 0x100320); + ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000; + ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1; + ram->base.tags = nv_rd32(fb, 0x100320); ram->base.calc = nv40_ram_calc; ram->base.prog = nv40_ram_prog; ram->base.tidy = nv40_ram_tidy; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c index f575a7246403..ef84bafad546 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c @@ -28,9 +28,9 @@ nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nv40_ram *ram; - u32 pfb474 = nv_rd32(pfb, 0x100474); + u32 fb474 = nv_rd32(fb, 0x100474); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); @@ -38,14 +38,14 @@ nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - if (pfb474 & 0x00000004) + if (fb474 & 0x00000004) ram->base.type = NV_MEM_TYPE_GDDR3; - if (pfb474 & 0x00000002) + if (fb474 & 0x00000002) ram->base.type = NV_MEM_TYPE_DDR2; - if (pfb474 & 0x00000001) + if (fb474 & 0x00000001) ram->base.type = NV_MEM_TYPE_DDR1; - ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; + ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000; ram->base.calc = nv40_ram_calc; ram->base.prog = nv40_ram_prog; ram->base.tidy = nv40_ram_tidy; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c index 51b44cdb2732..75c62115260e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c @@ -28,9 +28,9 @@ nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nv40_ram *ram; - u32 pfb914 = nv_rd32(pfb, 0x100914); + u32 fb914 = nv_rd32(fb, 0x100914); int ret; ret = nvkm_ram_create(parent, engine, oclass, &ram); @@ -38,16 +38,16 @@ nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - switch (pfb914 & 0x00000003) { + switch (fb914 & 0x00000003) { case 0x00000000: ram->base.type = NV_MEM_TYPE_DDR1; break; case 0x00000001: ram->base.type = NV_MEM_TYPE_DDR2; break; case 0x00000002: ram->base.type = NV_MEM_TYPE_GDDR3; break; case 0x00000003: break; } - ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; - ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; - ram->base.tags = nv_rd32(pfb, 0x100320); + ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000; + ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1; + ram->base.tags = nv_rd32(fb, 0x100320); ram->base.calc = nv40_ram_calc; ram->base.prog = nv40_ram_prog; ram->base.tidy = nv40_ram_tidy; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c index f3ed1c60d730..0eef65933ae7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c @@ -28,7 +28,7 @@ nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ram *ram; int ret; @@ -37,7 +37,7 @@ nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; + ram->size = nv_rd32(fb, 0x10020c) & 0xff000000; ram->type = NV_MEM_TYPE_STOLEN; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index fd0e9cecef62..49e21cf57e22 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -66,18 +66,17 @@ struct nv50_ram { #define T(t) cfg->timing_10_##t static int -nv50_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) +nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) { - struct nv50_ram *ram = (void *)pfb->ram; + struct nv50_ram *ram = (void *)fb->ram; struct nvbios_ramcfg *cfg = &ram->base.target.bios; - u32 cur2, cur3, cur4, cur7, cur8; + u32 cur2, cur4, cur7, cur8; u8 unkt3b; - cur2 = nv_rd32(pfb, 0x100228); - cur3 = nv_rd32(pfb, 0x10022c); - cur4 = nv_rd32(pfb, 0x100230); - cur7 = nv_rd32(pfb, 0x10023c); - cur8 = nv_rd32(pfb, 0x100240); + cur2 = nv_rd32(fb, 0x100228); + cur4 = nv_rd32(fb, 0x100230); + cur7 = nv_rd32(fb, 0x10023c); + cur8 = nv_rd32(fb, 0x100240); switch ((!T(CWL)) * ram->base.type) { case NV_MEM_TYPE_DDR2: @@ -89,7 +88,7 @@ nv50_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) } /* XXX: N=1 is not proper statistics */ - if (nv_device(pfb)->chipset == 0xa0) { + if (nv_device(fb)->chipset == 0xa0) { unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; timing[6] = (0x2d + T(CL) - T(CWL) + ram->base.next->bios.rammap_00_16_40) << 16 | @@ -126,19 +125,19 @@ nv50_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) timing[8] = (cur8 & 0xffffff00); /* XXX: P.version == 1 only has DDR2 and GDDR3? */ - if (pfb->ram->type == NV_MEM_TYPE_DDR2) { + if (fb->ram->type == NV_MEM_TYPE_DDR2) { timing[5] |= (T(CL) + 3) << 8; timing[8] |= (T(CL) - 4); - } else if (pfb->ram->type == NV_MEM_TYPE_GDDR3) { + } else if (fb->ram->type == NV_MEM_TYPE_GDDR3) { timing[5] |= (T(CL) + 2) << 8; timing[8] |= (T(CL) - 2); } - nv_debug(pfb, " 220: %08x %08x %08x %08x\n", + nv_debug(fb, " 220: %08x %08x %08x %08x\n", timing[0], timing[1], timing[2], timing[3]); - nv_debug(pfb, " 230: %08x %08x %08x %08x\n", + nv_debug(fb, " 230: %08x %08x %08x %08x\n", timing[4], timing[5], timing[6], timing[7]); - nv_debug(pfb, " 240: %08x\n", timing[8]); + nv_debug(fb, " 240: %08x\n", timing[8]); return 0; } #undef T @@ -152,10 +151,10 @@ nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) } static int -nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) +nv50_ram_calc(struct nvkm_fb *fb, u32 freq) { - struct nvkm_bios *bios = nvkm_bios(pfb); - struct nv50_ram *ram = (void *)pfb->ram; + struct nvkm_bios *bios = nvkm_bios(fb); + struct nv50_ram *ram = (void *)fb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; struct nvbios_perfE perfE; struct nvbios_pll mpll; @@ -178,7 +177,7 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) &size, &perfE); if (!data || (ver < 0x25 || ver >= 0x40) || (size < 2)) { - nv_error(pfb, "invalid/missing perftab entry\n"); + nv_error(fb, "invalid/missing perftab entry\n"); return -EINVAL; } } while (perfE.memory < freq); @@ -186,16 +185,16 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios); /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(pfb)); + strap = nvbios_ramcfg_index(nv_subdev(fb)); if (strap >= cnt) { - nv_error(pfb, "invalid ramcfg strap\n"); + nv_error(fb, "invalid ramcfg strap\n"); return -EINVAL; } data = nvbios_rammapSp_from_perf(bios, data + hdr, size, strap, &next->bios); if (!data) { - nv_error(pfb, "invalid/missing rammap entry "); + nv_error(fb, "invalid/missing rammap entry "); return -EINVAL; } @@ -204,16 +203,16 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) data = nvbios_timingEp(bios, next->bios.ramcfg_timing, &ver, &hdr, &cnt, &len, &next->bios); if (!data || ver != 0x10 || hdr < 0x12) { - nv_error(pfb, "invalid/missing timing entry " + nv_error(fb, "invalid/missing timing entry " "%02x %04x %02x %02x\n", strap, data, ver, hdr); return -EINVAL; } } - nv50_ram_timing_calc(pfb, timing); + nv50_ram_timing_calc(fb, timing); - ret = ram_init(hwsq, nv_subdev(pfb)); + ret = ram_init(hwsq, nv_subdev(fb)); if (ret) return ret; @@ -254,10 +253,10 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) ret = nvbios_pll_parse(bios, 0x004008, &mpll); mpll.vco2.max_freq = 0; - if (ret == 0) { - ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq, + if (ret >= 0) { + ret = nv04_pll_calc(nv_subdev(fb), &mpll, freq, &N1, &M1, &N2, &M2, &P); - if (ret == 0) + if (ret <= 0) ret = -EINVAL; } @@ -282,7 +281,7 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) next->bios.rammap_00_16_40 << 14); ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); - if (nv_device(pfb)->chipset >= 0x96) + if (nv_device(fb)->chipset >= 0x96) ram_wr32(hwsq, 0x100da0, r100da0); ram_nsec(hwsq, 64000); /*XXX*/ ram_nsec(hwsq, 32000); /*XXX*/ @@ -380,10 +379,10 @@ nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) } static int -nv50_ram_prog(struct nvkm_fb *pfb) +nv50_ram_prog(struct nvkm_fb *fb) { - struct nvkm_device *device = nv_device(pfb); - struct nv50_ram *ram = (void *)pfb->ram; + struct nvkm_device *device = nv_device(fb); + struct nv50_ram *ram = (void *)fb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); @@ -391,15 +390,15 @@ nv50_ram_prog(struct nvkm_fb *pfb) } static void -nv50_ram_tidy(struct nvkm_fb *pfb) +nv50_ram_tidy(struct nvkm_fb *fb) { - struct nv50_ram *ram = (void *)pfb->ram; + struct nv50_ram *ram = (void *)fb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; ram_exec(hwsq, false); } void -__nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem *mem) +__nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem *mem) { struct nvkm_mm_node *this; @@ -407,14 +406,14 @@ __nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem *mem) this = list_first_entry(&mem->regions, typeof(*this), rl_entry); list_del(&this->rl_entry); - nvkm_mm_free(&pfb->vram, &this); + nvkm_mm_free(&fb->vram, &this); } - nvkm_mm_free(&pfb->tags, &mem->tag); + nvkm_mm_free(&fb->tags, &mem->tag); } void -nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) +nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) { struct nvkm_mem *mem = *pmem; @@ -422,19 +421,19 @@ nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) if (unlikely(mem == NULL)) return; - mutex_lock(&pfb->base.mutex); - __nv50_ram_put(pfb, mem); - mutex_unlock(&pfb->base.mutex); + mutex_lock(&fb->subdev.mutex); + __nv50_ram_put(fb, mem); + mutex_unlock(&fb->subdev.mutex); kfree(mem); } int -nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, +nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, u32 memtype, struct nvkm_mem **pmem) { - struct nvkm_mm *heap = &pfb->vram; - struct nvkm_mm *tags = &pfb->tags; + struct nvkm_mm *heap = &fb->vram; + struct nvkm_mm *tags = &fb->tags; struct nvkm_mm_node *r; struct nvkm_mem *mem; int comp = (memtype & 0x300) >> 8; @@ -450,7 +449,7 @@ nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, if (!mem) return -ENOMEM; - mutex_lock(&pfb->base.mutex); + mutex_lock(&fb->subdev.mutex); if (comp) { if (align == 16) { int n = (max >> 4) * comp; @@ -475,15 +474,15 @@ nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, else ret = nvkm_mm_head(heap, 0, type, max, min, align, &r); if (ret) { - mutex_unlock(&pfb->base.mutex); - pfb->ram->put(pfb, &mem); + mutex_unlock(&fb->subdev.mutex); + fb->ram->put(fb, &mem); return ret; } list_add_tail(&r->rl_entry, &mem->regions); max -= r->length; } while (max); - mutex_unlock(&pfb->base.mutex); + mutex_unlock(&fb->subdev.mutex); r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); mem->offset = (u64)r->offset << 12; @@ -492,17 +491,17 @@ nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, } static u32 -nv50_fb_vram_rblock(struct nvkm_fb *pfb, struct nvkm_ram *ram) +nv50_fb_vram_rblock(struct nvkm_fb *fb, struct nvkm_ram *ram) { int colbits, rowbitsa, rowbitsb, banks; u64 rowsize, predicted; u32 r0, r4, rt, rblock_size; - r0 = nv_rd32(pfb, 0x100200); - r4 = nv_rd32(pfb, 0x100204); - rt = nv_rd32(pfb, 0x100250); - nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", - r0, r4, rt, nv_rd32(pfb, 0x001540)); + r0 = nv_rd32(fb, 0x100200); + r4 = nv_rd32(fb, 0x100204); + rt = nv_rd32(fb, 0x100250); + nv_debug(fb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", + r0, r4, rt, nv_rd32(fb, 0x001540)); colbits = (r4 & 0x0000f000) >> 12; rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; @@ -515,7 +514,7 @@ nv50_fb_vram_rblock(struct nvkm_fb *pfb, struct nvkm_ram *ram) predicted += rowsize << rowbitsb; if (predicted != ram->size) { - nv_warn(pfb, "memory controller reports %d MiB VRAM\n", + nv_warn(fb, "memory controller reports %d MiB VRAM\n", (u32)(ram->size >> 20)); } @@ -523,7 +522,7 @@ nv50_fb_vram_rblock(struct nvkm_fb *pfb, struct nvkm_ram *ram) if (rt & 1) rblock_size *= 3; - nv_debug(pfb, "rblock %d bytes\n", rblock_size); + nv_debug(fb, "rblock %d bytes\n", rblock_size); return rblock_size; } @@ -534,7 +533,7 @@ nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ struct nvkm_bios *bios = nvkm_bios(parent); - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ram *ram; int ret; @@ -543,13 +542,13 @@ nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ram->size = nv_rd32(pfb, 0x10020c); + ram->size = nv_rd32(fb, 0x10020c); ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); - ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16; + ram->part_mask = (nv_rd32(fb, 0x001540) & 0x00ff0000) >> 16; ram->parts = hweight8(ram->part_mask); - switch (nv_rd32(pfb, 0x100714) & 0x00000007) { + switch (nv_rd32(fb, 0x100714) & 0x00000007) { case 0: ram->type = NV_MEM_TYPE_DDR1; break; case 1: if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) @@ -564,14 +563,14 @@ nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, break; } - ret = nvkm_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - + ret = nvkm_mm_init(&fb->vram, rsvd_head, (ram->size >> 12) - (rsvd_head + rsvd_tail), - nv50_fb_vram_rblock(pfb, ram) >> 12); + nv50_fb_vram_rblock(fb, ram) >> 12); if (ret) return ret; - ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1; - ram->tags = nv_rd32(pfb, 0x100320); + ram->ranks = (nv_rd32(fb, 0x100200) & 0x4) ? 2 : 1; + ram->tags = nv_rd32(fb, 0x100320); ram->get = nv50_ram_get; ram->put = nv50_ram_put; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 8404143f93ee..b6c5e2d12f20 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -82,8 +82,8 @@ static void nv50_instobj_dtor(struct nvkm_object *object) { struct nv50_instobj_priv *node = (void *)object; - struct nvkm_fb *pfb = nvkm_fb(object); - pfb->ram->put(pfb, &node->mem); + struct nvkm_fb *fb = nvkm_fb(object); + fb->ram->put(fb, &node->mem); nvkm_instobj_destroy(&node->base); } @@ -92,7 +92,7 @@ nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_instobj_args *args = data; struct nv50_instobj_priv *node; int ret; @@ -105,7 +105,7 @@ nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = pfb->ram->get(pfb, args->size, args->align, 0, 0x800, &node->mem); + ret = fb->ram->get(fb, args->size, args->align, 0, 0x800, &node->mem); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index 7fb5ea0314cb..a78ae4ea4008 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -132,12 +132,12 @@ gf100_ltc_init(struct nvkm_object *object) void gf100_ltc_dtor(struct nvkm_object *object) { - struct nvkm_fb *pfb = nvkm_fb(object); + struct nvkm_fb *fb = nvkm_fb(object); struct nvkm_ltc_priv *priv = (void *)object; nvkm_mm_fini(&priv->tags); - if (pfb->ram) - nvkm_mm_free(&pfb->vram, &priv->tag_ram); + if (fb->ram) + nvkm_mm_free(&fb->vram, &priv->tag_ram); nvkm_ltc_destroy(priv); } @@ -145,19 +145,19 @@ gf100_ltc_dtor(struct nvkm_object *object) /* TODO: Figure out tag memory details and drop the over-cautious allocation. */ int -gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv) +gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *priv) { u32 tag_size, tag_margin, tag_align; int ret; /* No VRAM, no tags for now. */ - if (!pfb->ram) { + if (!fb->ram) { priv->num_tags = 0; goto mm_init; } /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ - priv->num_tags = (pfb->ram->size >> 17) / 4; + priv->num_tags = (fb->ram->size >> 17) / 4; if (priv->num_tags > (1 << 17)) priv->num_tags = 1 << 17; /* we have 17 bits in PTE */ priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */ @@ -177,7 +177,7 @@ gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv) tag_size += tag_align; tag_size = (tag_size + 0xfff) >> 12; /* round up */ - ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, + ret = nvkm_mm_tail(&fb->vram, 1, 1, tag_size, tag_size, 1, &priv->tag_ram); if (ret) { priv->num_tags = 0; @@ -200,7 +200,7 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ltc_priv *priv; u32 parts, mask; int ret, i; @@ -218,7 +218,7 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; - ret = gf100_ltc_init_tag_ram(pfb, priv); + ret = gf100_ltc_init_tag_ram(fb, priv); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index 6b3f6f4ce107..477190d27497 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -110,7 +110,7 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_ltc_priv *priv; u32 parts, mask; int ret, i; @@ -128,7 +128,7 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28; - ret = gf100_ltc_init_tag_ram(pfb, priv); + ret = gf100_ltc_init_tag_ram(fb, priv); if (ret) return ret; -- cgit v1.2.3 From cb8bb9cedb6015eafd56ef9e9c5b2c216e8e7960 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:07 +1000 Subject: drm/nouveau/tmr: cosmetic changes This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/dac.c | 8 +- drivers/gpu/drm/nouveau/dispnv04/hw.c | 6 +- .../gpu/drm/nouveau/include/nvkm/subdev/timer.h | 8 +- drivers/gpu/drm/nouveau/nouveau_abi16.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c | 8 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c | 18 +-- drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c | 8 +- drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c | 8 +- drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c | 16 +-- drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c | 147 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h | 2 +- 13 files changed, 121 insertions(+), 122 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c index af7249ca0f4b..2408728942b5 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dac.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c @@ -66,7 +66,7 @@ int nv04_dac_output_offset(struct drm_encoder *encoder) static int sample_load_twice(struct drm_device *dev, bool sense[2]) { struct nvif_device *device = &nouveau_drm(dev)->device; - struct nvkm_timer *ptimer = nvxx_timer(device); + struct nvkm_timer *tmr = nvxx_timer(device); int i; for (i = 0; i < 2; i++) { @@ -80,15 +80,15 @@ static int sample_load_twice(struct drm_device *dev, bool sense[2]) * use a 10ms timeout (guards against crtc being inactive, in * which case blank state would never change) */ - if (!nvkm_timer_wait_eq(ptimer, 10000000, + if (!nvkm_timer_wait_eq(tmr, 10000000, NV_PRMCIO_INP0__COLOR, 0x00000001, 0x00000000)) return -EBUSY; - if (!nvkm_timer_wait_eq(ptimer, 10000000, + if (!nvkm_timer_wait_eq(tmr, 10000000, NV_PRMCIO_INP0__COLOR, 0x00000001, 0x00000001)) return -EBUSY; - if (!nvkm_timer_wait_eq(ptimer, 10000000, + if (!nvkm_timer_wait_eq(tmr, 10000000, NV_PRMCIO_INP0__COLOR, 0x00000001, 0x00000000)) return -EBUSY; diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 42e07afc4c2b..e0d196e67000 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -661,7 +661,7 @@ nv_load_state_ext(struct drm_device *dev, int head, { struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nvkm_timer *ptimer = nvxx_timer(device); + struct nvkm_timer *tmr = nvxx_timer(device); struct nv04_crtc_reg *regp = &state->crtc_reg[head]; uint32_t reg900; int i; @@ -741,8 +741,8 @@ nv_load_state_ext(struct drm_device *dev, int head, if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { /* Not waiting for vertical retrace before modifying CRE_53/CRE_54 causes lockups. */ - nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); - nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); + nvkm_timer_wait_eq(tmr, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); + nvkm_timer_wait_eq(tmr, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); } wr_cio_state(dev, head, regp, NV_CIO_CRE_42); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index 4ad55082ef7a..2c27ce691939 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -31,7 +31,7 @@ void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); nvkm_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d)) struct nvkm_timer { - struct nvkm_subdev base; + struct nvkm_subdev subdev; u64 (*read)(struct nvkm_timer *); void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *); void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *); @@ -47,11 +47,11 @@ nvkm_timer(void *obj) nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \ sizeof(**d), (void **)d) #define nvkm_timer_destroy(p) \ - nvkm_subdev_destroy(&(p)->base) + nvkm_subdev_destroy(&(p)->subdev) #define nvkm_timer_init(p) \ - nvkm_subdev_init(&(p)->base) + nvkm_subdev_init(&(p)->subdev) #define nvkm_timer_fini(p,s) \ - nvkm_subdev_fini(&(p)->base, (s)) + nvkm_subdev_fini(&(p)->subdev, (s)) int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *, struct nvkm_oclass *, int size, void **); diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index d8b0891a141c..1bdde99155a0 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -164,7 +164,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_drm *drm = nouveau_drm(dev); struct nvif_device *device = &drm->device; - struct nvkm_timer *ptimer = nvxx_timer(device); + struct nvkm_timer *tmr = nvxx_timer(device); struct nvkm_gr *gr = nvxx_gr(device); struct drm_nouveau_getparam *getparam = data; @@ -206,7 +206,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) getparam->value = 0; /* deprecated */ break; case NOUVEAU_GETPARAM_PTIMER_TIME: - getparam->value = ptimer->read(ptimer); + getparam->value = tmr->read(tmr); break; case NOUVEAU_GETPARAM_HAS_BO_USAGE: getparam->value = 1; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 754284feae91..f18b75b883ac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -237,7 +237,7 @@ nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r, static int g84_gr_tlb_flush(struct nvkm_engine *engine) { - struct nvkm_timer *ptimer = nvkm_timer(engine); + struct nvkm_timer *tmr = nvkm_timer(engine); struct nv50_gr_priv *priv = (void *)engine; bool idle, timeout = false; unsigned long flags; @@ -247,7 +247,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) spin_lock_irqsave(&priv->lock, flags); nv_mask(priv, 0x400500, 0x00000001, 0x00000000); - start = ptimer->read(ptimer); + start = tmr->read(tmr); do { idle = true; @@ -266,7 +266,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) idle = false; } } while (!idle && - !(timeout = ptimer->read(ptimer) - start > 2000000000)); + !(timeout = tmr->read(tmr) - start > 2000000000)); if (timeout) { nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index abb3fdc18910..87c20d197102 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -83,7 +83,7 @@ static void nvkm_therm_update(struct nvkm_therm *obj, int mode) { struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base); - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); unsigned long flags; bool immd = true; bool poll = true; @@ -96,7 +96,7 @@ nvkm_therm_update(struct nvkm_therm *obj, int mode) switch (mode) { case NVKM_THERM_CTRL_MANUAL: - ptimer->alarm_cancel(ptimer, &therm->alarm); + tmr->alarm_cancel(tmr, &therm->alarm); duty = nvkm_therm_fan_get(&therm->base); if (duty < 0) duty = 100; @@ -120,12 +120,12 @@ nvkm_therm_update(struct nvkm_therm *obj, int mode) break; case NVKM_THERM_CTRL_NONE: default: - ptimer->alarm_cancel(ptimer, &therm->alarm); + tmr->alarm_cancel(tmr, &therm->alarm); poll = false; } if (list_empty(&therm->alarm.head) && poll) - ptimer->alarm(ptimer, 1000000000ULL, &therm->alarm); + tmr->alarm(tmr, 1000000000ULL, &therm->alarm); spin_unlock_irqrestore(&therm->lock, flags); if (duty >= 0) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c index 37b9f47f663c..83ebf366a221 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c @@ -32,7 +32,7 @@ static int nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target) { struct nvkm_therm_priv *therm = (void *)fan->parent; - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); unsigned long flags; int ret = 0; int duty; @@ -94,7 +94,7 @@ nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target) else delay = bump_period; - ptimer->alarm(ptimer, delay * 1000 * 1000, &fan->alarm); + tmr->alarm(tmr, delay * 1000 * 1000, &fan->alarm); } return ret; @@ -125,7 +125,7 @@ int nvkm_therm_fan_sense(struct nvkm_therm *obj) { struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base); - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); struct nvkm_gpio *gpio = nvkm_gpio(therm); u32 cycles, cur, prev; u64 start, end, tach; @@ -137,7 +137,7 @@ nvkm_therm_fan_sense(struct nvkm_therm *obj) * When the fan spins, it changes the value of GPIO FAN_SENSE. * We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation. */ - start = ptimer->read(ptimer); + start = tmr->read(tmr); prev = gpio->get(gpio, 0, therm->fan->tach.func, therm->fan->tach.line); cycles = 0; do { @@ -146,12 +146,12 @@ nvkm_therm_fan_sense(struct nvkm_therm *obj) cur = gpio->get(gpio, 0, therm->fan->tach.func, therm->fan->tach.line); if (prev != cur) { if (!start) - start = ptimer->read(ptimer); + start = tmr->read(tmr); cycles++; prev = cur; } - } while (cycles < 5 && ptimer->read(ptimer) - start < 250000000); - end = ptimer->read(ptimer); + } while (cycles < 5 && tmr->read(tmr) - start < 250000000); + end = tmr->read(tmr); if (cycles == 5) { tach = (u64)60000000000ULL; @@ -217,10 +217,10 @@ int nvkm_therm_fan_fini(struct nvkm_therm *obj, bool suspend) { struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base); - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); if (suspend) - ptimer->alarm_cancel(ptimer, &therm->fan->alarm); + tmr->alarm_cancel(tmr, &therm->fan->alarm); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c index 138ee99ec0ea..88cc190f5a3e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c @@ -39,7 +39,7 @@ static void nvkm_fantog_update(struct nvkm_fantog *fan, int percent) { struct nvkm_therm_priv *therm = (void *)fan->base.parent; - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); struct nvkm_gpio *gpio = nvkm_gpio(therm); unsigned long flags; int duty; @@ -56,7 +56,7 @@ nvkm_fantog_update(struct nvkm_fantog *fan, int percent) u64 next_change = (percent * fan->period_us) / 100; if (!duty) next_change = fan->period_us - next_change; - ptimer->alarm(ptimer, next_change * 1000, &fan->alarm); + tmr->alarm(tmr, next_change * 1000, &fan->alarm); } spin_unlock_irqrestore(&fan->lock, flags); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c index a6f46ed0e2ae..41628de3bf6c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c @@ -169,7 +169,7 @@ alarm_timer_callback(struct nvkm_alarm *alarm) struct nvkm_therm_priv *therm = container_of(alarm, struct nvkm_therm_priv, sensor.therm_poll_alarm); struct nvbios_therm_sensor *sensor = &therm->bios_sensor; - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); unsigned long flags; spin_lock_irqsave(&therm->sensor.alarm_program_lock, flags); @@ -191,7 +191,7 @@ alarm_timer_callback(struct nvkm_alarm *alarm) /* schedule the next poll in one second */ if (therm->base.temp_get(&therm->base) >= 0 && list_empty(&alarm->head)) - ptimer->alarm(ptimer, 1000000000ULL, alarm); + tmr->alarm(tmr, 1000000000ULL, alarm); } void @@ -223,10 +223,10 @@ int nvkm_therm_sensor_fini(struct nvkm_therm *obj, bool suspend) { struct nvkm_therm_priv *therm = container_of(obj, typeof(*therm), base); - struct nvkm_timer *ptimer = nvkm_timer(therm); + struct nvkm_timer *tmr = nvkm_timer(therm); if (suspend) - ptimer->alarm_cancel(ptimer, &therm->sensor.therm_poll_alarm); + tmr->alarm_cancel(tmr, &therm->sensor.therm_poll_alarm); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c index d894061ced52..216f44f9ca7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c @@ -81,13 +81,13 @@ nvkm_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data) void nvkm_timer_alarm(void *obj, u32 nsec, struct nvkm_alarm *alarm) { - struct nvkm_timer *ptimer = nvkm_timer(obj); - ptimer->alarm(ptimer, nsec, alarm); + struct nvkm_timer *tmr = nvkm_timer(obj); + tmr->alarm(tmr, nsec, alarm); } void nvkm_timer_alarm_cancel(void *obj, struct nvkm_alarm *alarm) { - struct nvkm_timer *ptimer = nvkm_timer(obj); - ptimer->alarm_cancel(ptimer, alarm); + struct nvkm_timer *tmr = nvkm_timer(obj); + tmr->alarm_cancel(tmr, alarm); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c index 80e38063dd9b..16965325dbfd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c @@ -26,21 +26,21 @@ static int gk20a_timer_init(struct nvkm_object *object) { - struct nv04_timer_priv *priv = (void *)object; - u32 hi = upper_32_bits(priv->suspend_time); - u32 lo = lower_32_bits(priv->suspend_time); + struct nv04_timer *tmr = (void *)object; + u32 hi = upper_32_bits(tmr->suspend_time); + u32 lo = lower_32_bits(tmr->suspend_time); int ret; - ret = nvkm_timer_init(&priv->base); + ret = nvkm_timer_init(&tmr->base); if (ret) return ret; - nv_debug(priv, "time low : 0x%08x\n", lo); - nv_debug(priv, "time high : 0x%08x\n", hi); + nv_debug(tmr, "time low : 0x%08x\n", lo); + nv_debug(tmr, "time high : 0x%08x\n", hi); /* restore the time before suspend */ - nv_wr32(priv, NV04_PTIMER_TIME_1, hi); - nv_wr32(priv, NV04_PTIMER_TIME_0, lo); + nv_wr32(tmr, NV04_PTIMER_TIME_1, hi); + nv_wr32(tmr, NV04_PTIMER_TIME_0, lo); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c index cf386f9c84c9..c9b3eb8c8e07 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c @@ -24,43 +24,42 @@ #include "nv04.h" static u64 -nv04_timer_read(struct nvkm_timer *ptimer) +nv04_timer_read(struct nvkm_timer *tmr) { - struct nv04_timer_priv *priv = (void *)ptimer; u32 hi, lo; do { - hi = nv_rd32(priv, NV04_PTIMER_TIME_1); - lo = nv_rd32(priv, NV04_PTIMER_TIME_0); - } while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1)); + hi = nv_rd32(tmr, NV04_PTIMER_TIME_1); + lo = nv_rd32(tmr, NV04_PTIMER_TIME_0); + } while (hi != nv_rd32(tmr, NV04_PTIMER_TIME_1)); return ((u64)hi << 32 | lo); } static void -nv04_timer_alarm_trigger(struct nvkm_timer *ptimer) +nv04_timer_alarm_trigger(struct nvkm_timer *obj) { - struct nv04_timer_priv *priv = (void *)ptimer; + struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); struct nvkm_alarm *alarm, *atemp; unsigned long flags; LIST_HEAD(exec); /* move any due alarms off the pending list */ - spin_lock_irqsave(&priv->lock, flags); - list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) { - if (alarm->timestamp <= ptimer->read(ptimer)) + spin_lock_irqsave(&tmr->lock, flags); + list_for_each_entry_safe(alarm, atemp, &tmr->alarms, head) { + if (alarm->timestamp <= tmr->base.read(&tmr->base)) list_move_tail(&alarm->head, &exec); } /* reschedule interrupt for next alarm time */ - if (!list_empty(&priv->alarms)) { - alarm = list_first_entry(&priv->alarms, typeof(*alarm), head); - nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp); - nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001); + if (!list_empty(&tmr->alarms)) { + alarm = list_first_entry(&tmr->alarms, typeof(*alarm), head); + nv_wr32(tmr, NV04_PTIMER_ALARM_0, alarm->timestamp); + nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000001); } else { - nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); + nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000000); } - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&tmr->lock, flags); /* execute any pending alarm handlers */ list_for_each_entry_safe(alarm, atemp, &exec, head) { @@ -70,79 +69,79 @@ nv04_timer_alarm_trigger(struct nvkm_timer *ptimer) } static void -nv04_timer_alarm(struct nvkm_timer *ptimer, u64 time, struct nvkm_alarm *alarm) +nv04_timer_alarm(struct nvkm_timer *obj, u64 time, struct nvkm_alarm *alarm) { - struct nv04_timer_priv *priv = (void *)ptimer; + struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); struct nvkm_alarm *list; unsigned long flags; - alarm->timestamp = ptimer->read(ptimer) + time; + alarm->timestamp = tmr->base.read(&tmr->base) + time; /* append new alarm to list, in soonest-alarm-first order */ - spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&tmr->lock, flags); if (!time) { if (!list_empty(&alarm->head)) list_del(&alarm->head); } else { - list_for_each_entry(list, &priv->alarms, head) { + list_for_each_entry(list, &tmr->alarms, head) { if (list->timestamp > alarm->timestamp) break; } list_add_tail(&alarm->head, &list->head); } - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&tmr->lock, flags); /* process pending alarms */ - nv04_timer_alarm_trigger(ptimer); + nv04_timer_alarm_trigger(&tmr->base); } static void -nv04_timer_alarm_cancel(struct nvkm_timer *ptimer, struct nvkm_alarm *alarm) +nv04_timer_alarm_cancel(struct nvkm_timer *obj, struct nvkm_alarm *alarm) { - struct nv04_timer_priv *priv = (void *)ptimer; + struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); + spin_lock_irqsave(&tmr->lock, flags); list_del_init(&alarm->head); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&tmr->lock, flags); } static void nv04_timer_intr(struct nvkm_subdev *subdev) { - struct nv04_timer_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0); + struct nv04_timer *tmr = (void *)subdev; + u32 stat = nv_rd32(tmr, NV04_PTIMER_INTR_0); if (stat & 0x00000001) { - nv04_timer_alarm_trigger(&priv->base); - nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001); + nv04_timer_alarm_trigger(&tmr->base); + nv_wr32(tmr, NV04_PTIMER_INTR_0, 0x00000001); stat &= ~0x00000001; } if (stat) { - nv_error(priv, "unknown stat 0x%08x\n", stat); - nv_wr32(priv, NV04_PTIMER_INTR_0, stat); + nv_error(tmr, "unknown stat 0x%08x\n", stat); + nv_wr32(tmr, NV04_PTIMER_INTR_0, stat); } } int nv04_timer_fini(struct nvkm_object *object, bool suspend) { - struct nv04_timer_priv *priv = (void *)object; + struct nv04_timer *tmr = (void *)object; if (suspend) - priv->suspend_time = nv04_timer_read(&priv->base); - nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); - return nvkm_timer_fini(&priv->base, suspend); + tmr->suspend_time = nv04_timer_read(&tmr->base); + nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000000); + return nvkm_timer_fini(&tmr->base, suspend); } static int nv04_timer_init(struct nvkm_object *object) { struct nvkm_device *device = nv_device(object); - struct nv04_timer_priv *priv = (void *)object; + struct nv04_timer *tmr = (void *)object; u32 m = 1, f, n, d, lo, hi; int ret; - ret = nvkm_timer_init(&priv->base); + ret = nvkm_timer_init(&tmr->base); if (ret) return ret; @@ -167,15 +166,15 @@ nv04_timer_init(struct nvkm_object *object) m++; } - nv_wr32(priv, 0x009220, m - 1); + nv_wr32(tmr, 0x009220, m - 1); } if (!n) { - nv_warn(priv, "unknown input clock freq\n"); - if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) || - !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) { - nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1); - nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1); + nv_warn(tmr, "unknown input clock freq\n"); + if (!nv_rd32(tmr, NV04_PTIMER_NUMERATOR) || + !nv_rd32(tmr, NV04_PTIMER_DENOMINATOR)) { + nv_wr32(tmr, NV04_PTIMER_NUMERATOR, 1); + nv_wr32(tmr, NV04_PTIMER_DENOMINATOR, 1); } return 0; } @@ -197,31 +196,31 @@ nv04_timer_init(struct nvkm_object *object) } /* restore the time before suspend */ - lo = priv->suspend_time; - hi = (priv->suspend_time >> 32); - - nv_debug(priv, "input frequency : %dHz\n", f); - nv_debug(priv, "input multiplier: %d\n", m); - nv_debug(priv, "numerator : 0x%08x\n", n); - nv_debug(priv, "denominator : 0x%08x\n", d); - nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n); - nv_debug(priv, "time low : 0x%08x\n", lo); - nv_debug(priv, "time high : 0x%08x\n", hi); - - nv_wr32(priv, NV04_PTIMER_NUMERATOR, n); - nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d); - nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff); - nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); - nv_wr32(priv, NV04_PTIMER_TIME_1, hi); - nv_wr32(priv, NV04_PTIMER_TIME_0, lo); + lo = tmr->suspend_time; + hi = (tmr->suspend_time >> 32); + + nv_debug(tmr, "input frequency : %dHz\n", f); + nv_debug(tmr, "input multiplier: %d\n", m); + nv_debug(tmr, "numerator : 0x%08x\n", n); + nv_debug(tmr, "denominator : 0x%08x\n", d); + nv_debug(tmr, "timer frequency : %dHz\n", (f * m) * d / n); + nv_debug(tmr, "time low : 0x%08x\n", lo); + nv_debug(tmr, "time high : 0x%08x\n", hi); + + nv_wr32(tmr, NV04_PTIMER_NUMERATOR, n); + nv_wr32(tmr, NV04_PTIMER_DENOMINATOR, d); + nv_wr32(tmr, NV04_PTIMER_INTR_0, 0xffffffff); + nv_wr32(tmr, NV04_PTIMER_INTR_EN_0, 0x00000000); + nv_wr32(tmr, NV04_PTIMER_TIME_1, hi); + nv_wr32(tmr, NV04_PTIMER_TIME_0, lo); return 0; } void nv04_timer_dtor(struct nvkm_object *object) { - struct nv04_timer_priv *priv = (void *)object; - return nvkm_timer_destroy(&priv->base); + struct nv04_timer *tmr = (void *)object; + return nvkm_timer_destroy(&tmr->base); } int @@ -229,22 +228,22 @@ nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_timer_priv *priv; + struct nv04_timer *tmr; int ret; - ret = nvkm_timer_create(parent, engine, oclass, &priv); - *pobject = nv_object(priv); + ret = nvkm_timer_create(parent, engine, oclass, &tmr); + *pobject = nv_object(tmr); if (ret) return ret; - priv->base.base.intr = nv04_timer_intr; - priv->base.read = nv04_timer_read; - priv->base.alarm = nv04_timer_alarm; - priv->base.alarm_cancel = nv04_timer_alarm_cancel; - priv->suspend_time = 0; + tmr->base.subdev.intr = nv04_timer_intr; + tmr->base.read = nv04_timer_read; + tmr->base.alarm = nv04_timer_alarm; + tmr->base.alarm_cancel = nv04_timer_alarm_cancel; + tmr->suspend_time = 0; - INIT_LIST_HEAD(&priv->alarms); - spin_lock_init(&priv->lock); + INIT_LIST_HEAD(&tmr->alarms); + spin_lock_init(&tmr->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h index 89996a9826b1..1bc0d7c073ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h @@ -10,7 +10,7 @@ #define NV04_PTIMER_TIME_1 0x009410 #define NV04_PTIMER_ALARM_0 0x009420 -struct nv04_timer_priv { +struct nv04_timer { struct nvkm_timer base; struct list_head alarms; spinlock_t lock; -- cgit v1.2.3 From 6189f1b0938dc0621c27494031b83ffae566e318 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:07 +1000 Subject: drm/nouveau/fifo: cosmetic changes This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 6 +- drivers/gpu/drm/nouveau/nv84_fence.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 58 +-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c | 46 +-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 352 +++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 394 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 316 ++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 38 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 68 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 122 +++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 112 +++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 12 +- 25 files changed, 800 insertions(+), 788 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index 9100b800562e..3e77c924434b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -68,7 +68,7 @@ struct nvkm_fifo_base { #include struct nvkm_fifo { - struct nvkm_engine base; + struct nvkm_engine engine; struct nvkm_event cevent; /* channel creation event */ struct nvkm_event uevent; /* async user trigger */ @@ -92,9 +92,9 @@ nvkm_fifo(void *obj) #define nvkm_fifo_create(o,e,c,fc,lc,d) \ nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) #define nvkm_fifo_init(p) \ - nvkm_engine_init(&(p)->base) + nvkm_engine_init(&(p)->engine) #define nvkm_fifo_fini(p,s) \ - nvkm_engine_fini(&(p)->base, (s)) + nvkm_engine_fini(&(p)->engine, (s)) int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, int min, int max, diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index a03db4368696..76098a58e2fa 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -213,7 +213,7 @@ nv84_fence_destroy(struct nouveau_drm *drm) int nv84_fence_create(struct nouveau_drm *drm) { - struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); + struct nvkm_fifo *fifo = nvxx_fifo(&drm->device); struct nv84_fence_priv *priv; u32 domain; int ret; @@ -228,7 +228,7 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_new = nv84_fence_context_new; priv->base.context_del = nv84_fence_context_del; - priv->base.contexts = pfifo->max + 1; + priv->base.contexts = fifo->max + 1; priv->base.context_base = fence_context_alloc(priv->base.contexts); priv->base.uevent = true; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 9addf43e07d4..a8fff0e13e19 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -72,7 +72,7 @@ gt215_ce_isr_error_name[] = { void gt215_ce_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_falcon *falcon = (void *)subdev; struct nvkm_object *engctx; @@ -87,7 +87,7 @@ gt215_ce_intr(struct nvkm_subdev *subdev) int chid; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat & 0x00000040) { nv_error(falcon, "DISPATCH_ERROR ["); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index c1f065d8efa4..442c2a002c63 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -104,7 +104,7 @@ g84_cipher_intr_mask[] = { static void g84_cipher_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_engine *cipher = (void *)subdev; @@ -115,7 +115,7 @@ g84_cipher_intr(struct nvkm_subdev *subdev) int chid; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat) { nv_error(cipher, "%s", ""); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index a85014bb37a7..2b0f497d57a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -58,7 +58,7 @@ nvkm_fifo_channel_create_(struct nvkm_object *parent, u64 engmask, int len, void **ptr) { struct nvkm_device *device = nv_device(engine); - struct nvkm_fifo *priv = (void *)engine; + struct nvkm_fifo *fifo = (void *)engine; struct nvkm_fifo_chan *chan; struct nvkm_dmaeng *dmaeng; unsigned long flags; @@ -90,39 +90,39 @@ nvkm_fifo_channel_create_(struct nvkm_object *parent, return ret; /* find a free fifo channel */ - spin_lock_irqsave(&priv->lock, flags); - for (chan->chid = priv->min; chan->chid < priv->max; chan->chid++) { - if (!priv->channel[chan->chid]) { - priv->channel[chan->chid] = nv_object(chan); + spin_lock_irqsave(&fifo->lock, flags); + for (chan->chid = fifo->min; chan->chid < fifo->max; chan->chid++) { + if (!fifo->channel[chan->chid]) { + fifo->channel[chan->chid] = nv_object(chan); break; } } - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&fifo->lock, flags); - if (chan->chid == priv->max) { - nv_error(priv, "no free channels\n"); + if (chan->chid == fifo->max) { + nv_error(fifo, "no free channels\n"); return -ENOSPC; } chan->addr = nv_device_resource_start(device, bar) + addr + size * chan->chid; chan->size = size; - nvkm_event_send(&priv->cevent, 1, 0, NULL, 0); + nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0); return 0; } void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan) { - struct nvkm_fifo *priv = (void *)nv_object(chan)->engine; + struct nvkm_fifo *fifo = (void *)nv_object(chan)->engine; unsigned long flags; if (chan->user) iounmap(chan->user); - spin_lock_irqsave(&priv->lock, flags); - priv->channel[chan->chid] = NULL; - spin_unlock_irqrestore(&priv->lock, flags); + spin_lock_irqsave(&fifo->lock, flags); + fifo->channel[chan->chid] = NULL; + spin_unlock_irqrestore(&fifo->lock, flags); nvkm_gpuobj_ref(NULL, &chan->pushgpu); nvkm_object_ref(NULL, (struct nvkm_object **)&chan->pushdma); @@ -214,9 +214,9 @@ _nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type, } static int -nvkm_fifo_chid(struct nvkm_fifo *priv, struct nvkm_object *object) +nvkm_fifo_chid(struct nvkm_fifo *fifo, struct nvkm_object *object) { - int engidx = nv_hclass(priv) & 0xff; + int engidx = nv_hclass(fifo) & 0xff; while (object && object->parent) { if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && @@ -243,12 +243,12 @@ nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) } void -nvkm_fifo_destroy(struct nvkm_fifo *priv) +nvkm_fifo_destroy(struct nvkm_fifo *fifo) { - kfree(priv->channel); - nvkm_event_fini(&priv->uevent); - nvkm_event_fini(&priv->cevent); - nvkm_engine_destroy(&priv->base); + kfree(fifo->channel); + nvkm_event_fini(&fifo->uevent); + nvkm_event_fini(&fifo->cevent); + nvkm_engine_destroy(&fifo->engine); } int @@ -256,26 +256,26 @@ nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int min, int max, int length, void **pobject) { - struct nvkm_fifo *priv; + struct nvkm_fifo *fifo; int ret; ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", "fifo", length, pobject); - priv = *pobject; + fifo = *pobject; if (ret) return ret; - priv->min = min; - priv->max = max; - priv->channel = kzalloc(sizeof(*priv->channel) * (max + 1), GFP_KERNEL); - if (!priv->channel) + fifo->min = min; + fifo->max = max; + fifo->channel = kzalloc(sizeof(*fifo->channel) * (max + 1), GFP_KERNEL); + if (!fifo->channel) return -ENOMEM; - ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &priv->cevent); + ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent); if (ret) return ret; - priv->chid = nvkm_fifo_chid; - spin_lock_init(&priv->lock); + fifo->chid = nvkm_fifo_chid; + spin_lock_init(&fifo->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index a04920b3cf84..bff5867e24ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -81,7 +81,7 @@ g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_object *object) { struct nvkm_bar *bar = nvkm_bar(parent); - struct nv50_fifo_priv *priv = (void *)parent->engine; + struct nv50_fifo *fifo = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; u32 addr, save, engn; @@ -103,12 +103,12 @@ g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, return -EINVAL; } - save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn); - nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); - done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff); - nv_wr32(priv, 0x002520, save); + save = nv_mask(fifo, 0x002520, 0x0000003f, 1 << engn); + nv_wr32(fifo, 0x0032fc, nv_gpuobj(base)->addr >> 12); + done = nv_wait_ne(fifo, 0x0032fc, 0xffffffff, 0xffffffff); + nv_wr32(fifo, 0x002520, save); if (!done) { - nv_error(priv, "channel %d [%s] unload timeout\n", + nv_error(fifo, "channel %d [%s] unload timeout\n", chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; @@ -309,7 +309,7 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, static int g84_fifo_chan_init(struct nvkm_object *object) { - struct nv50_fifo_priv *priv = (void *)object->engine; + struct nv50_fifo *fifo = (void *)object->engine; struct nv50_fifo_base *base = (void *)object->parent; struct nv50_fifo_chan *chan = (void *)object; struct nvkm_gpuobj *ramfc = base->ramfc; @@ -320,8 +320,8 @@ g84_fifo_chan_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); - nv50_fifo_playlist_update(priv); + nv_wr32(fifo, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); + nv50_fifo_playlist_update(fifo); return 0; } @@ -444,34 +444,34 @@ g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_fifo_priv *priv; + struct nv50_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[0]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0, + &fifo->playlist[0]); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[1]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0, + &fifo->playlist[1]); if (ret) return ret; - ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent); if (ret) return ret; - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &g84_fifo_cclass; - nv_engine(priv)->sclass = g84_fifo_sclass; - priv->base.pause = nv04_fifo_pause; - priv->base.start = nv04_fifo_start; + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &g84_fifo_cclass; + nv_engine(fifo)->sclass = g84_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index b745252f2261..0a7971a3317c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -35,7 +35,7 @@ #include #include -struct gf100_fifo_priv { +struct gf100_fifo { struct nvkm_fifo base; struct work_struct fault; @@ -74,18 +74,18 @@ struct gf100_fifo_chan { ******************************************************************************/ static void -gf100_fifo_runlist_update(struct gf100_fifo_priv *priv) +gf100_fifo_runlist_update(struct gf100_fifo *fifo) { - struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_bar *bar = nvkm_bar(fifo); struct nvkm_gpuobj *cur; int i, p; - mutex_lock(&nv_subdev(priv)->mutex); - cur = priv->runlist.mem[priv->runlist.active]; - priv->runlist.active = !priv->runlist.active; + mutex_lock(&nv_subdev(fifo)->mutex); + cur = fifo->runlist.mem[fifo->runlist.active]; + fifo->runlist.active = !fifo->runlist.active; for (i = 0, p = 0; i < 128; i++) { - struct gf100_fifo_chan *chan = (void *)priv->base.channel[i]; + struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i]; if (chan && chan->state == RUNNING) { nv_wo32(cur, p + 0, i); nv_wo32(cur, p + 4, 0x00000004); @@ -94,14 +94,14 @@ gf100_fifo_runlist_update(struct gf100_fifo_priv *priv) } bar->flush(bar); - nv_wr32(priv, 0x002270, cur->addr >> 12); - nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); + nv_wr32(fifo, 0x002270, cur->addr >> 12); + nv_wr32(fifo, 0x002274, 0x01f00000 | (p >> 3)); - if (wait_event_timeout(priv->runlist.wait, - !(nv_rd32(priv, 0x00227c) & 0x00100000), + if (wait_event_timeout(fifo->runlist.wait, + !(nv_rd32(fifo, 0x00227c) & 0x00100000), msecs_to_jiffies(2000)) == 0) - nv_error(priv, "runlist update timeout\n"); - mutex_unlock(&nv_subdev(priv)->mutex); + nv_error(fifo, "runlist update timeout\n"); + mutex_unlock(&nv_subdev(fifo)->mutex); } static int @@ -146,7 +146,7 @@ gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_object *object) { struct nvkm_bar *bar = nvkm_bar(parent); - struct gf100_fifo_priv *priv = (void *)parent->engine; + struct gf100_fifo *fifo = (void *)parent->engine; struct gf100_fifo_base *base = (void *)parent->parent; struct gf100_fifo_chan *chan = (void *)parent; u32 addr; @@ -163,9 +163,9 @@ gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, return -EINVAL; } - nv_wr32(priv, 0x002634, chan->base.chid); - if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { - nv_error(priv, "channel %d [%s] kick timeout\n", + nv_wr32(fifo, 0x002634, chan->base.chid); + if (!nv_wait(fifo, 0x002634, 0xffffffff, chan->base.chid)) { + nv_error(fifo, "channel %d [%s] kick timeout\n", chan->base.chid, nvkm_client_name(chan)); if (suspend) return -EBUSY; @@ -186,7 +186,7 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nv50_channel_gpfifo_v0 v0; } *args = data; struct nvkm_bar *bar = nvkm_bar(parent); - struct gf100_fifo_priv *priv = (void *)engine; + struct gf100_fifo *fifo = (void *)engine; struct gf100_fifo_base *base = (void *)parent; struct gf100_fifo_chan *chan; u64 usermem, ioffset, ilength; @@ -202,7 +202,7 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, - priv->user.bar.offset, 0x1000, + fifo->user.bar.offset, 0x1000, args->v0.pushbuf, (1ULL << NVDEV_ENGINE_SW) | (1ULL << NVDEV_ENGINE_GR) | @@ -225,10 +225,10 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ilength = order_base_2(args->v0.ilength / 8); for (i = 0; i < 0x1000; i += 4) - nv_wo32(priv->user.mem, usermem + i, 0x00000000); + nv_wo32(fifo->user.mem, usermem + i, 0x00000000); - nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); - nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); + nv_wo32(base, 0x08, lower_32_bits(fifo->user.mem->addr + usermem)); + nv_wo32(base, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem)); nv_wo32(base, 0x10, 0x0000face); nv_wo32(base, 0x30, 0xfffff902); nv_wo32(base, 0x48, lower_32_bits(ioffset)); @@ -251,7 +251,7 @@ static int gf100_fifo_chan_init(struct nvkm_object *object) { struct nvkm_gpuobj *base = nv_gpuobj(object->parent); - struct gf100_fifo_priv *priv = (void *)object->engine; + struct gf100_fifo *fifo = (void *)object->engine; struct gf100_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; int ret; @@ -260,33 +260,33 @@ gf100_fifo_chan_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); + nv_wr32(fifo, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { - nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); - gf100_fifo_runlist_update(priv); + nv_wr32(fifo, 0x003004 + (chid * 8), 0x001f0001); + gf100_fifo_runlist_update(fifo); } return 0; } -static void gf100_fifo_intr_engine(struct gf100_fifo_priv *priv); +static void gf100_fifo_intr_engine(struct gf100_fifo *fifo); static int gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct gf100_fifo_priv *priv = (void *)object->engine; + struct gf100_fifo *fifo = (void *)object->engine; struct gf100_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { - nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); - gf100_fifo_runlist_update(priv); + nv_mask(fifo, 0x003004 + (chid * 8), 0x00000001, 0x00000000); + gf100_fifo_runlist_update(fifo); } - gf100_fifo_intr_engine(priv); + gf100_fifo_intr_engine(fifo); - nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); + nv_wr32(fifo, 0x003000 + (chid * 8), 0x00000000); return nvkm_fifo_channel_fini(&chan->base, suspend); } @@ -371,7 +371,7 @@ gf100_fifo_cclass = { ******************************************************************************/ static inline int -gf100_fifo_engidx(struct gf100_fifo_priv *priv, u32 engn) +gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) { switch (engn) { case NVDEV_ENGINE_GR : engn = 0; break; @@ -388,7 +388,7 @@ gf100_fifo_engidx(struct gf100_fifo_priv *priv, u32 engn) } static inline struct nvkm_engine * -gf100_fifo_engine(struct gf100_fifo_priv *priv, u32 engn) +gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) { switch (engn) { case 0: engn = NVDEV_ENGINE_GR; break; @@ -401,69 +401,69 @@ gf100_fifo_engine(struct gf100_fifo_priv *priv, u32 engn) return NULL; } - return nvkm_engine(priv, engn); + return nvkm_engine(fifo, engn); } static void gf100_fifo_recover_work(struct work_struct *work) { - struct gf100_fifo_priv *priv = container_of(work, typeof(*priv), fault); + struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); struct nvkm_object *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; - spin_lock_irqsave(&priv->base.lock, flags); - mask = priv->mask; - priv->mask = 0ULL; - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_lock_irqsave(&fifo->base.lock, flags); + mask = fifo->mask; + fifo->mask = 0ULL; + spin_unlock_irqrestore(&fifo->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << gf100_fifo_engidx(priv, engn); - nv_mask(priv, 0x002630, engm, engm); + engm |= 1 << gf100_fifo_engidx(fifo, engn); + nv_mask(fifo, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nvkm_engine(priv, engn))) { + if ((engine = (void *)nvkm_engine(fifo, engn))) { nv_ofuncs(engine)->fini(engine, false); WARN_ON(nv_ofuncs(engine)->init(engine)); } } - gf100_fifo_runlist_update(priv); - nv_wr32(priv, 0x00262c, engm); - nv_mask(priv, 0x002630, engm, 0x00000000); + gf100_fifo_runlist_update(fifo); + nv_wr32(fifo, 0x00262c, engm); + nv_mask(fifo, 0x002630, engm, 0x00000000); } static void -gf100_fifo_recover(struct gf100_fifo_priv *priv, struct nvkm_engine *engine, +gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, struct gf100_fifo_chan *chan) { u32 chid = chan->base.chid; unsigned long flags; - nv_error(priv, "%s engine fault on channel %d, recovering...\n", + nv_error(fifo, "%s engine fault on channel %d, recovering...\n", nv_subdev(engine)->name, chid); - nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); + nv_mask(fifo, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); chan->state = KILLED; - spin_lock_irqsave(&priv->base.lock, flags); - priv->mask |= 1ULL << nv_engidx(engine); - spin_unlock_irqrestore(&priv->base.lock, flags); - schedule_work(&priv->fault); + spin_lock_irqsave(&fifo->base.lock, flags); + fifo->mask |= 1ULL << nv_engidx(engine); + spin_unlock_irqrestore(&fifo->base.lock, flags); + schedule_work(&fifo->fault); } static int -gf100_fifo_swmthd(struct gf100_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data) { struct gf100_fifo_chan *chan = NULL; struct nvkm_handle *bind; unsigned long flags; int ret = -EINVAL; - spin_lock_irqsave(&priv->base.lock, flags); - if (likely(chid >= priv->base.min && chid <= priv->base.max)) - chan = (void *)priv->base.channel[chid]; + spin_lock_irqsave(&fifo->base.lock, flags); + if (likely(chid >= fifo->base.min && chid <= fifo->base.max)) + chan = (void *)fifo->base.channel[chid]; if (unlikely(!chan)) goto out; @@ -475,7 +475,7 @@ gf100_fifo_swmthd(struct gf100_fifo_priv *priv, u32 chid, u32 mthd, u32 data) } out: - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_unlock_irqrestore(&fifo->base.lock, flags); return ret; } @@ -486,14 +486,14 @@ gf100_fifo_sched_reason[] = { }; static void -gf100_fifo_intr_sched_ctxsw(struct gf100_fifo_priv *priv) +gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) { struct nvkm_engine *engine; struct gf100_fifo_chan *chan; u32 engn; for (engn = 0; engn < 6; engn++) { - u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); + u32 stat = nv_rd32(fifo, 0x002640 + (engn * 0x04)); u32 busy = (stat & 0x80000000); u32 save = (stat & 0x00100000); /* maybe? */ u32 unk0 = (stat & 0x00040000); @@ -502,19 +502,19 @@ gf100_fifo_intr_sched_ctxsw(struct gf100_fifo_priv *priv) (void)save; if (busy && unk0 && unk1) { - if (!(chan = (void *)priv->base.channel[chid])) + if (!(chan = (void *)fifo->base.channel[chid])) continue; - if (!(engine = gf100_fifo_engine(priv, engn))) + if (!(engine = gf100_fifo_engine(fifo, engn))) continue; - gf100_fifo_recover(priv, engine, chan); + gf100_fifo_recover(fifo, engine, chan); } } } static void -gf100_fifo_intr_sched(struct gf100_fifo_priv *priv) +gf100_fifo_intr_sched(struct gf100_fifo *fifo) { - u32 intr = nv_rd32(priv, 0x00254c); + u32 intr = nv_rd32(fifo, 0x00254c); u32 code = intr & 0x000000ff; const struct nvkm_enum *en; char enunk[6] = ""; @@ -523,11 +523,11 @@ gf100_fifo_intr_sched(struct gf100_fifo_priv *priv) if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); - nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); + nv_error(fifo, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); switch (code) { case 0x0a: - gf100_fifo_intr_sched_ctxsw(priv); + gf100_fifo_intr_sched_ctxsw(fifo); break; default: break; @@ -594,12 +594,12 @@ gf100_fifo_fault_gpcclient[] = { }; static void -gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit) +gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) { - u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); - u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); - u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); - u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); + u32 inst = nv_rd32(fifo, 0x002800 + (unit * 0x10)); + u32 valo = nv_rd32(fifo, 0x002804 + (unit * 0x10)); + u32 vahi = nv_rd32(fifo, 0x002808 + (unit * 0x10)); + u32 stat = nv_rd32(fifo, 0x00280c + (unit * 0x10)); u32 gpc = (stat & 0x1f000000) >> 24; u32 client = (stat & 0x00001f00) >> 8; u32 write = (stat & 0x00000080); @@ -621,16 +621,16 @@ gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit) if (eu) { switch (eu->data2) { case NVDEV_SUBDEV_BAR: - nv_mask(priv, 0x001704, 0x00000000, 0x00000000); + nv_mask(fifo, 0x001704, 0x00000000, 0x00000000); break; case NVDEV_SUBDEV_INSTMEM: - nv_mask(priv, 0x001714, 0x00000000, 0x00000000); + nv_mask(fifo, 0x001714, 0x00000000, 0x00000000); break; case NVDEV_ENGINE_IFB: - nv_mask(priv, 0x001718, 0x00000000, 0x00000000); + nv_mask(fifo, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_engine(priv, eu->data2); + engine = nvkm_engine(fifo, eu->data2); if (engine) engctx = nvkm_engctx_get(engine, inst); break; @@ -649,7 +649,7 @@ gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit) if (!ec) snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); - nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " + nv_error(fifo, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " "channel 0x%010llx [%s]\n", write ? "write" : "read", (u64)vahi << 32 | valo, er ? er->name : erunk, eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", @@ -660,7 +660,7 @@ gf100_fifo_intr_fault(struct gf100_fifo_priv *priv, int unit) while (object) { switch (nv_mclass(object)) { case FERMI_CHANNEL_GPFIFO: - gf100_fifo_recover(priv, engine, (void *)object); + gf100_fifo_recover(fifo, engine, (void *)object); break; } object = object->parent; @@ -678,82 +678,82 @@ gf100_fifo_pbdma_intr[] = { }; static void -gf100_fifo_intr_pbdma(struct gf100_fifo_priv *priv, int unit) +gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) { - u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); - u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); - u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); - u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; + u32 stat = nv_rd32(fifo, 0x040108 + (unit * 0x2000)); + u32 addr = nv_rd32(fifo, 0x0400c0 + (unit * 0x2000)); + u32 data = nv_rd32(fifo, 0x0400c4 + (unit * 0x2000)); + u32 chid = nv_rd32(fifo, 0x040120 + (unit * 0x2000)) & 0x7f; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00003ffc); u32 show = stat; if (stat & 0x00800000) { - if (!gf100_fifo_swmthd(priv, chid, mthd, data)) + if (!gf100_fifo_swmthd(fifo, chid, mthd, data)) show &= ~0x00800000; } if (show) { - nv_error(priv, "PBDMA%d:", unit); + nv_error(fifo, "PBDMA%d:", unit); nvkm_bitfield_print(gf100_fifo_pbdma_intr, show); pr_cont("\n"); - nv_error(priv, + nv_error(fifo, "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", unit, chid, - nvkm_client_name_for_fifo_chid(&priv->base, chid), + nvkm_client_name_for_fifo_chid(&fifo->base, chid), subc, mthd, data); } - nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); - nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); + nv_wr32(fifo, 0x0400c0 + (unit * 0x2000), 0x80600008); + nv_wr32(fifo, 0x040108 + (unit * 0x2000), stat); } static void -gf100_fifo_intr_runlist(struct gf100_fifo_priv *priv) +gf100_fifo_intr_runlist(struct gf100_fifo *fifo) { - u32 intr = nv_rd32(priv, 0x002a00); + u32 intr = nv_rd32(fifo, 0x002a00); if (intr & 0x10000000) { - wake_up(&priv->runlist.wait); - nv_wr32(priv, 0x002a00, 0x10000000); + wake_up(&fifo->runlist.wait); + nv_wr32(fifo, 0x002a00, 0x10000000); intr &= ~0x10000000; } if (intr) { - nv_error(priv, "RUNLIST 0x%08x\n", intr); - nv_wr32(priv, 0x002a00, intr); + nv_error(fifo, "RUNLIST 0x%08x\n", intr); + nv_wr32(fifo, 0x002a00, intr); } } static void -gf100_fifo_intr_engine_unit(struct gf100_fifo_priv *priv, int engn) +gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) { - u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); - u32 inte = nv_rd32(priv, 0x002628); + u32 intr = nv_rd32(fifo, 0x0025a8 + (engn * 0x04)); + u32 inte = nv_rd32(fifo, 0x002628); u32 unkn; - nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr); + nv_wr32(fifo, 0x0025a8 + (engn * 0x04), intr); for (unkn = 0; unkn < 8; unkn++) { u32 ints = (intr >> (unkn * 0x04)) & inte; if (ints & 0x1) { - nvkm_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&fifo->base); ints &= ~1; } if (ints) { - nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints); - nv_mask(priv, 0x002628, ints, 0); + nv_error(fifo, "ENGINE %d %d %01x", engn, unkn, ints); + nv_mask(fifo, 0x002628, ints, 0); } } } static void -gf100_fifo_intr_engine(struct gf100_fifo_priv *priv) +gf100_fifo_intr_engine(struct gf100_fifo *fifo) { - u32 mask = nv_rd32(priv, 0x0025a4); + u32 mask = nv_rd32(fifo, 0x0025a4); while (mask) { u32 unit = __ffs(mask); - gf100_fifo_intr_engine_unit(priv, unit); + gf100_fifo_intr_engine_unit(fifo, unit); mask &= ~(1 << unit); } } @@ -761,73 +761,73 @@ gf100_fifo_intr_engine(struct gf100_fifo_priv *priv) static void gf100_fifo_intr(struct nvkm_subdev *subdev) { - struct gf100_fifo_priv *priv = (void *)subdev; - u32 mask = nv_rd32(priv, 0x002140); - u32 stat = nv_rd32(priv, 0x002100) & mask; + struct gf100_fifo *fifo = (void *)subdev; + u32 mask = nv_rd32(fifo, 0x002140); + u32 stat = nv_rd32(fifo, 0x002100) & mask; if (stat & 0x00000001) { - u32 intr = nv_rd32(priv, 0x00252c); - nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); - nv_wr32(priv, 0x002100, 0x00000001); + u32 intr = nv_rd32(fifo, 0x00252c); + nv_warn(fifo, "INTR 0x00000001: 0x%08x\n", intr); + nv_wr32(fifo, 0x002100, 0x00000001); stat &= ~0x00000001; } if (stat & 0x00000100) { - gf100_fifo_intr_sched(priv); - nv_wr32(priv, 0x002100, 0x00000100); + gf100_fifo_intr_sched(fifo); + nv_wr32(fifo, 0x002100, 0x00000100); stat &= ~0x00000100; } if (stat & 0x00010000) { - u32 intr = nv_rd32(priv, 0x00256c); - nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); - nv_wr32(priv, 0x002100, 0x00010000); + u32 intr = nv_rd32(fifo, 0x00256c); + nv_warn(fifo, "INTR 0x00010000: 0x%08x\n", intr); + nv_wr32(fifo, 0x002100, 0x00010000); stat &= ~0x00010000; } if (stat & 0x01000000) { - u32 intr = nv_rd32(priv, 0x00258c); - nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); - nv_wr32(priv, 0x002100, 0x01000000); + u32 intr = nv_rd32(fifo, 0x00258c); + nv_warn(fifo, "INTR 0x01000000: 0x%08x\n", intr); + nv_wr32(fifo, 0x002100, 0x01000000); stat &= ~0x01000000; } if (stat & 0x10000000) { - u32 mask = nv_rd32(priv, 0x00259c); + u32 mask = nv_rd32(fifo, 0x00259c); while (mask) { u32 unit = __ffs(mask); - gf100_fifo_intr_fault(priv, unit); - nv_wr32(priv, 0x00259c, (1 << unit)); + gf100_fifo_intr_fault(fifo, unit); + nv_wr32(fifo, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } stat &= ~0x10000000; } if (stat & 0x20000000) { - u32 mask = nv_rd32(priv, 0x0025a0); + u32 mask = nv_rd32(fifo, 0x0025a0); while (mask) { u32 unit = __ffs(mask); - gf100_fifo_intr_pbdma(priv, unit); - nv_wr32(priv, 0x0025a0, (1 << unit)); + gf100_fifo_intr_pbdma(fifo, unit); + nv_wr32(fifo, 0x0025a0, (1 << unit)); mask &= ~(1 << unit); } stat &= ~0x20000000; } if (stat & 0x40000000) { - gf100_fifo_intr_runlist(priv); + gf100_fifo_intr_runlist(fifo); stat &= ~0x40000000; } if (stat & 0x80000000) { - gf100_fifo_intr_engine(priv); + gf100_fifo_intr_engine(fifo); stat &= ~0x80000000; } if (stat) { - nv_error(priv, "INTR 0x%08x\n", stat); - nv_mask(priv, 0x002140, stat, 0x00000000); - nv_wr32(priv, 0x002100, stat); + nv_error(fifo, "INTR 0x%08x\n", stat); + nv_mask(fifo, 0x002140, stat, 0x00000000); + nv_wr32(fifo, 0x002100, stat); } } @@ -857,101 +857,101 @@ gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct gf100_fifo_priv *priv; + struct gf100_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - INIT_WORK(&priv->fault, gf100_fifo_recover_work); + INIT_WORK(&fifo->fault, gf100_fifo_recover_work); - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, - &priv->runlist.mem[0]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, + &fifo->runlist.mem[0]); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, - &priv->runlist.mem[1]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, + &fifo->runlist.mem[1]); if (ret) return ret; - init_waitqueue_head(&priv->runlist.wait); + init_waitqueue_head(&fifo->runlist.wait); - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, - &priv->user.mem); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0, + &fifo->user.mem); if (ret) return ret; - ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, - &priv->user.bar); + ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW, + &fifo->user.bar); if (ret) return ret; - ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent); if (ret) return ret; - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = gf100_fifo_intr; - nv_engine(priv)->cclass = &gf100_fifo_cclass; - nv_engine(priv)->sclass = gf100_fifo_sclass; + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = gf100_fifo_intr; + nv_engine(fifo)->cclass = &gf100_fifo_cclass; + nv_engine(fifo)->sclass = gf100_fifo_sclass; return 0; } static void gf100_fifo_dtor(struct nvkm_object *object) { - struct gf100_fifo_priv *priv = (void *)object; + struct gf100_fifo *fifo = (void *)object; - nvkm_gpuobj_unmap(&priv->user.bar); - nvkm_gpuobj_ref(NULL, &priv->user.mem); - nvkm_gpuobj_ref(NULL, &priv->runlist.mem[0]); - nvkm_gpuobj_ref(NULL, &priv->runlist.mem[1]); + nvkm_gpuobj_unmap(&fifo->user.bar); + nvkm_gpuobj_ref(NULL, &fifo->user.mem); + nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]); + nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]); - nvkm_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&fifo->base); } static int gf100_fifo_init(struct nvkm_object *object) { - struct gf100_fifo_priv *priv = (void *)object; + struct gf100_fifo *fifo = (void *)object; int ret, i; - ret = nvkm_fifo_init(&priv->base); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; - nv_wr32(priv, 0x000204, 0xffffffff); - nv_wr32(priv, 0x002204, 0xffffffff); + nv_wr32(fifo, 0x000204, 0xffffffff); + nv_wr32(fifo, 0x002204, 0xffffffff); - priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204)); - nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); + fifo->spoon_nr = hweight32(nv_rd32(fifo, 0x002204)); + nv_debug(fifo, "%d PBDMA unit(s)\n", fifo->spoon_nr); /* assign engines to PBDMAs */ - if (priv->spoon_nr >= 3) { - nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ - nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ - nv_wr32(priv, 0x002210, ~(1 << 1)); /* PMSPP */ - nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */ - nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ - nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ + if (fifo->spoon_nr >= 3) { + nv_wr32(fifo, 0x002208, ~(1 << 0)); /* PGRAPH */ + nv_wr32(fifo, 0x00220c, ~(1 << 1)); /* PVP */ + nv_wr32(fifo, 0x002210, ~(1 << 1)); /* PMSPP */ + nv_wr32(fifo, 0x002214, ~(1 << 1)); /* PMSVLD */ + nv_wr32(fifo, 0x002218, ~(1 << 2)); /* PCE0 */ + nv_wr32(fifo, 0x00221c, ~(1 << 1)); /* PCE1 */ } /* PBDMA[n] */ - for (i = 0; i < priv->spoon_nr; i++) { - nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); - nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ - nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ + for (i = 0; i < fifo->spoon_nr; i++) { + nv_mask(fifo, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); + nv_wr32(fifo, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ + nv_wr32(fifo, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ } - nv_mask(priv, 0x002200, 0x00000001, 0x00000001); - nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); + nv_mask(fifo, 0x002200, 0x00000001, 0x00000001); + nv_wr32(fifo, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); - nv_wr32(priv, 0x002100, 0xffffffff); - nv_wr32(priv, 0x002140, 0x7fffffff); - nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ + nv_wr32(fifo, 0x002100, 0xffffffff); + nv_wr32(fifo, 0x002140, 0x7fffffff); + nv_wr32(fifo, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index e10f9644140f..ed8d3820a044 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -58,7 +58,7 @@ struct gk104_fifo_engn { wait_queue_head_t wait; }; -struct gk104_fifo_priv { +struct gk104_fifo { struct nvkm_fifo base; struct work_struct fault; @@ -93,19 +93,19 @@ struct gk104_fifo_chan { ******************************************************************************/ static void -gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine) +gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) { - struct nvkm_bar *bar = nvkm_bar(priv); - struct gk104_fifo_engn *engn = &priv->engine[engine]; + struct nvkm_bar *bar = nvkm_bar(fifo); + struct gk104_fifo_engn *engn = &fifo->engine[engine]; struct nvkm_gpuobj *cur; int i, p; - mutex_lock(&nv_subdev(priv)->mutex); + mutex_lock(&nv_subdev(fifo)->mutex); cur = engn->runlist[engn->cur_runlist]; engn->cur_runlist = !engn->cur_runlist; - for (i = 0, p = 0; i < priv->base.max; i++) { - struct gk104_fifo_chan *chan = (void *)priv->base.channel[i]; + for (i = 0, p = 0; i < fifo->base.max; i++) { + struct gk104_fifo_chan *chan = (void *)fifo->base.channel[i]; if (chan && chan->state == RUNNING && chan->engine == engine) { nv_wo32(cur, p + 0, i); nv_wo32(cur, p + 4, 0x00000000); @@ -114,14 +114,14 @@ gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine) } bar->flush(bar); - nv_wr32(priv, 0x002270, cur->addr >> 12); - nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); + nv_wr32(fifo, 0x002270, cur->addr >> 12); + nv_wr32(fifo, 0x002274, (engine << 20) | (p >> 3)); - if (wait_event_timeout(engn->wait, !(nv_rd32(priv, 0x002284 + + if (wait_event_timeout(engn->wait, !(nv_rd32(fifo, 0x002284 + (engine * 0x08)) & 0x00100000), msecs_to_jiffies(2000)) == 0) - nv_error(priv, "runlist %d update timeout\n", engine); - mutex_unlock(&nv_subdev(priv)->mutex); + nv_error(fifo, "runlist %d update timeout\n", engine); + mutex_unlock(&nv_subdev(fifo)->mutex); } static int @@ -165,15 +165,31 @@ gk104_fifo_context_attach(struct nvkm_object *parent, return 0; } +static int +gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) +{ + struct nvkm_object *obj = (void *)chan; + struct gk104_fifo *fifo = (void *)obj->engine; + + nv_wr32(fifo, 0x002634, chan->base.chid); + if (!nv_wait(fifo, 0x002634, 0x100000, 0x000000)) { + nv_error(fifo, "channel %d [%s] kick timeout\n", + chan->base.chid, nvkm_client_name(chan)); + return -EBUSY; + } + + return 0; +} + static int gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_object *object) { struct nvkm_bar *bar = nvkm_bar(parent); - struct gk104_fifo_priv *priv = (void *)parent->engine; struct gk104_fifo_base *base = (void *)parent->parent; struct gk104_fifo_chan *chan = (void *)parent; u32 addr; + int ret; switch (nv_engidx(object->engine)) { case NVDEV_ENGINE_SW : return 0; @@ -188,13 +204,9 @@ gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, return -EINVAL; } - nv_wr32(priv, 0x002634, chan->base.chid); - if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { - nv_error(priv, "channel %d [%s] kick timeout\n", - chan->base.chid, nvkm_client_name(chan)); - if (suspend) - return -EBUSY; - } + ret = gk104_fifo_chan_kick(chan); + if (ret && suspend) + return ret; if (addr) { nv_wo32(base, addr + 0x00, 0x00000000); @@ -214,7 +226,7 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct kepler_channel_gpfifo_a_v0 v0; } *args = data; struct nvkm_bar *bar = nvkm_bar(parent); - struct gk104_fifo_priv *priv = (void *)engine; + struct gk104_fifo *fifo = (void *)engine; struct gk104_fifo_base *base = (void *)parent; struct gk104_fifo_chan *chan; u64 usermem, ioffset, ilength; @@ -239,12 +251,12 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } if (i == FIFO_ENGINE_NR) { - nv_error(priv, "unsupported engines 0x%08x\n", args->v0.engine); + nv_error(fifo, "unsupported engines 0x%08x\n", args->v0.engine); return -ENODEV; } ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, - priv->user.bar.offset, 0x200, + fifo->user.bar.offset, 0x200, args->v0.pushbuf, fifo_engine[i].mask, &chan); *pobject = nv_object(chan); @@ -262,10 +274,10 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ilength = order_base_2(args->v0.ilength / 8); for (i = 0; i < 0x200; i += 4) - nv_wo32(priv->user.mem, usermem + i, 0x00000000); + nv_wo32(fifo->user.mem, usermem + i, 0x00000000); - nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); - nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); + nv_wo32(base, 0x08, lower_32_bits(fifo->user.mem->addr + usermem)); + nv_wo32(base, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem)); nv_wo32(base, 0x10, 0x0000face); nv_wo32(base, 0x30, 0xfffff902); nv_wo32(base, 0x48, lower_32_bits(ioffset)); @@ -286,7 +298,7 @@ static int gk104_fifo_chan_init(struct nvkm_object *object) { struct nvkm_gpuobj *base = nv_gpuobj(object->parent); - struct gk104_fifo_priv *priv = (void *)object->engine; + struct gk104_fifo *fifo = (void *)object->engine; struct gk104_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; int ret; @@ -295,13 +307,13 @@ gk104_fifo_chan_init(struct nvkm_object *object) if (ret) return ret; - nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); - nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); + nv_mask(fifo, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); + nv_wr32(fifo, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { - nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); - gk104_fifo_runlist_update(priv, chan->engine); - nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); + nv_mask(fifo, 0x800004 + (chid * 8), 0x00000400, 0x00000400); + gk104_fifo_runlist_update(fifo, chan->engine); + nv_mask(fifo, 0x800004 + (chid * 8), 0x00000400, 0x00000400); } return 0; @@ -310,16 +322,16 @@ gk104_fifo_chan_init(struct nvkm_object *object) static int gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct gk104_fifo_priv *priv = (void *)object->engine; + struct gk104_fifo *fifo = (void *)object->engine; struct gk104_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { - nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); - gk104_fifo_runlist_update(priv, chan->engine); + nv_mask(fifo, 0x800004 + (chid * 8), 0x00000800, 0x00000800); + gk104_fifo_runlist_update(fifo, chan->engine); } - nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); + nv_wr32(fifo, 0x800000 + (chid * 8), 0x00000000); return nvkm_fifo_channel_fini(&chan->base, suspend); } @@ -403,7 +415,7 @@ gk104_fifo_cclass = { ******************************************************************************/ static inline int -gk104_fifo_engidx(struct gk104_fifo_priv *priv, u32 engn) +gk104_fifo_engidx(struct gk104_fifo *fifo, u32 engn) { switch (engn) { case NVDEV_ENGINE_GR : @@ -422,73 +434,73 @@ gk104_fifo_engidx(struct gk104_fifo_priv *priv, u32 engn) } static inline struct nvkm_engine * -gk104_fifo_engine(struct gk104_fifo_priv *priv, u32 engn) +gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn) { if (engn >= ARRAY_SIZE(fifo_engine)) return NULL; - return nvkm_engine(priv, fifo_engine[engn].subdev); + return nvkm_engine(fifo, fifo_engine[engn].subdev); } static void gk104_fifo_recover_work(struct work_struct *work) { - struct gk104_fifo_priv *priv = container_of(work, typeof(*priv), fault); + struct gk104_fifo *fifo = container_of(work, typeof(*fifo), fault); struct nvkm_object *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; - spin_lock_irqsave(&priv->base.lock, flags); - mask = priv->mask; - priv->mask = 0ULL; - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_lock_irqsave(&fifo->base.lock, flags); + mask = fifo->mask; + fifo->mask = 0ULL; + spin_unlock_irqrestore(&fifo->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << gk104_fifo_engidx(priv, engn); - nv_mask(priv, 0x002630, engm, engm); + engm |= 1 << gk104_fifo_engidx(fifo, engn); + nv_mask(fifo, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nvkm_engine(priv, engn))) { + if ((engine = (void *)nvkm_engine(fifo, engn))) { nv_ofuncs(engine)->fini(engine, false); WARN_ON(nv_ofuncs(engine)->init(engine)); } - gk104_fifo_runlist_update(priv, gk104_fifo_engidx(priv, engn)); + gk104_fifo_runlist_update(fifo, gk104_fifo_engidx(fifo, engn)); } - nv_wr32(priv, 0x00262c, engm); - nv_mask(priv, 0x002630, engm, 0x00000000); + nv_wr32(fifo, 0x00262c, engm); + nv_mask(fifo, 0x002630, engm, 0x00000000); } static void -gk104_fifo_recover(struct gk104_fifo_priv *priv, struct nvkm_engine *engine, +gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, struct gk104_fifo_chan *chan) { u32 chid = chan->base.chid; unsigned long flags; - nv_error(priv, "%s engine fault on channel %d, recovering...\n", + nv_error(fifo, "%s engine fault on channel %d, recovering...\n", nv_subdev(engine)->name, chid); - nv_mask(priv, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); + nv_mask(fifo, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); chan->state = KILLED; - spin_lock_irqsave(&priv->base.lock, flags); - priv->mask |= 1ULL << nv_engidx(engine); - spin_unlock_irqrestore(&priv->base.lock, flags); - schedule_work(&priv->fault); + spin_lock_irqsave(&fifo->base.lock, flags); + fifo->mask |= 1ULL << nv_engidx(engine); + spin_unlock_irqrestore(&fifo->base.lock, flags); + schedule_work(&fifo->fault); } static int -gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +gk104_fifo_swmthd(struct gk104_fifo *fifo, u32 chid, u32 mthd, u32 data) { struct gk104_fifo_chan *chan = NULL; struct nvkm_handle *bind; unsigned long flags; int ret = -EINVAL; - spin_lock_irqsave(&priv->base.lock, flags); - if (likely(chid >= priv->base.min && chid <= priv->base.max)) - chan = (void *)priv->base.channel[chid]; + spin_lock_irqsave(&fifo->base.lock, flags); + if (likely(chid >= fifo->base.min && chid <= fifo->base.max)) + chan = (void *)fifo->base.channel[chid]; if (unlikely(!chan)) goto out; @@ -500,7 +512,7 @@ gk104_fifo_swmthd(struct gk104_fifo_priv *priv, u32 chid, u32 mthd, u32 data) } out: - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_unlock_irqrestore(&fifo->base.lock, flags); return ret; } @@ -516,9 +528,9 @@ gk104_fifo_bind_reason[] = { }; static void -gk104_fifo_intr_bind(struct gk104_fifo_priv *priv) +gk104_fifo_intr_bind(struct gk104_fifo *fifo) { - u32 intr = nv_rd32(priv, 0x00252c); + u32 intr = nv_rd32(fifo, 0x00252c); u32 code = intr & 0x000000ff; const struct nvkm_enum *en; char enunk[6] = ""; @@ -527,7 +539,7 @@ gk104_fifo_intr_bind(struct gk104_fifo_priv *priv) if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); - nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk); + nv_error(fifo, "BIND_ERROR [ %s ]\n", en ? en->name : enunk); } static const struct nvkm_enum @@ -537,14 +549,14 @@ gk104_fifo_sched_reason[] = { }; static void -gk104_fifo_intr_sched_ctxsw(struct gk104_fifo_priv *priv) +gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) { struct nvkm_engine *engine; struct gk104_fifo_chan *chan; u32 engn; for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) { - u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); + u32 stat = nv_rd32(fifo, 0x002640 + (engn * 0x04)); u32 busy = (stat & 0x80000000); u32 next = (stat & 0x07ff0000) >> 16; u32 chsw = (stat & 0x00008000); @@ -555,19 +567,19 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo_priv *priv) (void)save; if (busy && chsw) { - if (!(chan = (void *)priv->base.channel[chid])) + if (!(chan = (void *)fifo->base.channel[chid])) continue; - if (!(engine = gk104_fifo_engine(priv, engn))) + if (!(engine = gk104_fifo_engine(fifo, engn))) continue; - gk104_fifo_recover(priv, engine, chan); + gk104_fifo_recover(fifo, engine, chan); } } } static void -gk104_fifo_intr_sched(struct gk104_fifo_priv *priv) +gk104_fifo_intr_sched(struct gk104_fifo *fifo) { - u32 intr = nv_rd32(priv, 0x00254c); + u32 intr = nv_rd32(fifo, 0x00254c); u32 code = intr & 0x000000ff; const struct nvkm_enum *en; char enunk[6] = ""; @@ -576,11 +588,11 @@ gk104_fifo_intr_sched(struct gk104_fifo_priv *priv) if (!en) snprintf(enunk, sizeof(enunk), "UNK%02x", code); - nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); + nv_error(fifo, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); switch (code) { case 0x0a: - gk104_fifo_intr_sched_ctxsw(priv); + gk104_fifo_intr_sched_ctxsw(fifo); break; default: break; @@ -588,18 +600,18 @@ gk104_fifo_intr_sched(struct gk104_fifo_priv *priv) } static void -gk104_fifo_intr_chsw(struct gk104_fifo_priv *priv) +gk104_fifo_intr_chsw(struct gk104_fifo *fifo) { - u32 stat = nv_rd32(priv, 0x00256c); - nv_error(priv, "CHSW_ERROR 0x%08x\n", stat); - nv_wr32(priv, 0x00256c, stat); + u32 stat = nv_rd32(fifo, 0x00256c); + nv_error(fifo, "CHSW_ERROR 0x%08x\n", stat); + nv_wr32(fifo, 0x00256c, stat); } static void -gk104_fifo_intr_dropped_fault(struct gk104_fifo_priv *priv) +gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) { - u32 stat = nv_rd32(priv, 0x00259c); - nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat); + u32 stat = nv_rd32(fifo, 0x00259c); + nv_error(fifo, "DROPPED_MMU_FAULT 0x%08x\n", stat); } static const struct nvkm_enum @@ -708,12 +720,12 @@ gk104_fifo_fault_gpcclient[] = { }; static void -gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) +gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) { - u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); - u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); - u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); - u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); + u32 inst = nv_rd32(fifo, 0x002800 + (unit * 0x10)); + u32 valo = nv_rd32(fifo, 0x002804 + (unit * 0x10)); + u32 vahi = nv_rd32(fifo, 0x002808 + (unit * 0x10)); + u32 stat = nv_rd32(fifo, 0x00280c + (unit * 0x10)); u32 gpc = (stat & 0x1f000000) >> 24; u32 client = (stat & 0x00001f00) >> 8; u32 write = (stat & 0x00000080); @@ -735,16 +747,16 @@ gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) if (eu) { switch (eu->data2) { case NVDEV_SUBDEV_BAR: - nv_mask(priv, 0x001704, 0x00000000, 0x00000000); + nv_mask(fifo, 0x001704, 0x00000000, 0x00000000); break; case NVDEV_SUBDEV_INSTMEM: - nv_mask(priv, 0x001714, 0x00000000, 0x00000000); + nv_mask(fifo, 0x001714, 0x00000000, 0x00000000); break; case NVDEV_ENGINE_IFB: - nv_mask(priv, 0x001718, 0x00000000, 0x00000000); + nv_mask(fifo, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_engine(priv, eu->data2); + engine = nvkm_engine(fifo, eu->data2); if (engine) engctx = nvkm_engctx_get(engine, inst); break; @@ -763,7 +775,7 @@ gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) if (!ec) snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); - nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " + nv_error(fifo, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " "channel 0x%010llx [%s]\n", write ? "write" : "read", (u64)vahi << 32 | valo, er ? er->name : erunk, eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", @@ -775,7 +787,7 @@ gk104_fifo_intr_fault(struct gk104_fifo_priv *priv, int unit) switch (nv_mclass(object)) { case KEPLER_CHANNEL_GPFIFO_A: case MAXWELL_CHANNEL_GPFIFO_A: - gk104_fifo_recover(priv, engine, (void *)object); + gk104_fifo_recover(fifo, engine, (void *)object); break; } object = object->parent; @@ -819,35 +831,35 @@ static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { }; static void -gk104_fifo_intr_pbdma_0(struct gk104_fifo_priv *priv, int unit) +gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) { - u32 mask = nv_rd32(priv, 0x04010c + (unit * 0x2000)); - u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)) & mask; - u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); - u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); - u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; + u32 mask = nv_rd32(fifo, 0x04010c + (unit * 0x2000)); + u32 stat = nv_rd32(fifo, 0x040108 + (unit * 0x2000)) & mask; + u32 addr = nv_rd32(fifo, 0x0400c0 + (unit * 0x2000)); + u32 data = nv_rd32(fifo, 0x0400c4 + (unit * 0x2000)); + u32 chid = nv_rd32(fifo, 0x040120 + (unit * 0x2000)) & 0xfff; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00003ffc); u32 show = stat; if (stat & 0x00800000) { - if (!gk104_fifo_swmthd(priv, chid, mthd, data)) + if (!gk104_fifo_swmthd(fifo, chid, mthd, data)) show &= ~0x00800000; - nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); + nv_wr32(fifo, 0x0400c0 + (unit * 0x2000), 0x80600008); } if (show) { - nv_error(priv, "PBDMA%d:", unit); + nv_error(fifo, "PBDMA%d:", unit); nvkm_bitfield_print(gk104_fifo_pbdma_intr_0, show); pr_cont("\n"); - nv_error(priv, + nv_error(fifo, "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", unit, chid, - nvkm_client_name_for_fifo_chid(&priv->base, chid), + nvkm_client_name_for_fifo_chid(&fifo->base, chid), subc, mthd, data); } - nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); + nv_wr32(fifo, 0x040108 + (unit * 0x2000), stat); } static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { @@ -860,129 +872,129 @@ static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = { }; static void -gk104_fifo_intr_pbdma_1(struct gk104_fifo_priv *priv, int unit) +gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit) { - u32 mask = nv_rd32(priv, 0x04014c + (unit * 0x2000)); - u32 stat = nv_rd32(priv, 0x040148 + (unit * 0x2000)) & mask; - u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; + u32 mask = nv_rd32(fifo, 0x04014c + (unit * 0x2000)); + u32 stat = nv_rd32(fifo, 0x040148 + (unit * 0x2000)) & mask; + u32 chid = nv_rd32(fifo, 0x040120 + (unit * 0x2000)) & 0xfff; if (stat) { - nv_error(priv, "PBDMA%d:", unit); + nv_error(fifo, "PBDMA%d:", unit); nvkm_bitfield_print(gk104_fifo_pbdma_intr_1, stat); pr_cont("\n"); - nv_error(priv, "PBDMA%d: ch %d %08x %08x\n", unit, chid, - nv_rd32(priv, 0x040150 + (unit * 0x2000)), - nv_rd32(priv, 0x040154 + (unit * 0x2000))); + nv_error(fifo, "PBDMA%d: ch %d %08x %08x\n", unit, chid, + nv_rd32(fifo, 0x040150 + (unit * 0x2000)), + nv_rd32(fifo, 0x040154 + (unit * 0x2000))); } - nv_wr32(priv, 0x040148 + (unit * 0x2000), stat); + nv_wr32(fifo, 0x040148 + (unit * 0x2000), stat); } static void -gk104_fifo_intr_runlist(struct gk104_fifo_priv *priv) +gk104_fifo_intr_runlist(struct gk104_fifo *fifo) { - u32 mask = nv_rd32(priv, 0x002a00); + u32 mask = nv_rd32(fifo, 0x002a00); while (mask) { u32 engn = __ffs(mask); - wake_up(&priv->engine[engn].wait); - nv_wr32(priv, 0x002a00, 1 << engn); + wake_up(&fifo->engine[engn].wait); + nv_wr32(fifo, 0x002a00, 1 << engn); mask &= ~(1 << engn); } } static void -gk104_fifo_intr_engine(struct gk104_fifo_priv *priv) +gk104_fifo_intr_engine(struct gk104_fifo *fifo) { - nvkm_fifo_uevent(&priv->base); + nvkm_fifo_uevent(&fifo->base); } static void gk104_fifo_intr(struct nvkm_subdev *subdev) { - struct gk104_fifo_priv *priv = (void *)subdev; - u32 mask = nv_rd32(priv, 0x002140); - u32 stat = nv_rd32(priv, 0x002100) & mask; + struct gk104_fifo *fifo = (void *)subdev; + u32 mask = nv_rd32(fifo, 0x002140); + u32 stat = nv_rd32(fifo, 0x002100) & mask; if (stat & 0x00000001) { - gk104_fifo_intr_bind(priv); - nv_wr32(priv, 0x002100, 0x00000001); + gk104_fifo_intr_bind(fifo); + nv_wr32(fifo, 0x002100, 0x00000001); stat &= ~0x00000001; } if (stat & 0x00000010) { - nv_error(priv, "PIO_ERROR\n"); - nv_wr32(priv, 0x002100, 0x00000010); + nv_error(fifo, "PIO_ERROR\n"); + nv_wr32(fifo, 0x002100, 0x00000010); stat &= ~0x00000010; } if (stat & 0x00000100) { - gk104_fifo_intr_sched(priv); - nv_wr32(priv, 0x002100, 0x00000100); + gk104_fifo_intr_sched(fifo); + nv_wr32(fifo, 0x002100, 0x00000100); stat &= ~0x00000100; } if (stat & 0x00010000) { - gk104_fifo_intr_chsw(priv); - nv_wr32(priv, 0x002100, 0x00010000); + gk104_fifo_intr_chsw(fifo); + nv_wr32(fifo, 0x002100, 0x00010000); stat &= ~0x00010000; } if (stat & 0x00800000) { - nv_error(priv, "FB_FLUSH_TIMEOUT\n"); - nv_wr32(priv, 0x002100, 0x00800000); + nv_error(fifo, "FB_FLUSH_TIMEOUT\n"); + nv_wr32(fifo, 0x002100, 0x00800000); stat &= ~0x00800000; } if (stat & 0x01000000) { - nv_error(priv, "LB_ERROR\n"); - nv_wr32(priv, 0x002100, 0x01000000); + nv_error(fifo, "LB_ERROR\n"); + nv_wr32(fifo, 0x002100, 0x01000000); stat &= ~0x01000000; } if (stat & 0x08000000) { - gk104_fifo_intr_dropped_fault(priv); - nv_wr32(priv, 0x002100, 0x08000000); + gk104_fifo_intr_dropped_fault(fifo); + nv_wr32(fifo, 0x002100, 0x08000000); stat &= ~0x08000000; } if (stat & 0x10000000) { - u32 mask = nv_rd32(priv, 0x00259c); + u32 mask = nv_rd32(fifo, 0x00259c); while (mask) { u32 unit = __ffs(mask); - gk104_fifo_intr_fault(priv, unit); - nv_wr32(priv, 0x00259c, (1 << unit)); + gk104_fifo_intr_fault(fifo, unit); + nv_wr32(fifo, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } stat &= ~0x10000000; } if (stat & 0x20000000) { - u32 mask = nv_rd32(priv, 0x0025a0); + u32 mask = nv_rd32(fifo, 0x0025a0); while (mask) { u32 unit = __ffs(mask); - gk104_fifo_intr_pbdma_0(priv, unit); - gk104_fifo_intr_pbdma_1(priv, unit); - nv_wr32(priv, 0x0025a0, (1 << unit)); + gk104_fifo_intr_pbdma_0(fifo, unit); + gk104_fifo_intr_pbdma_1(fifo, unit); + nv_wr32(fifo, 0x0025a0, (1 << unit)); mask &= ~(1 << unit); } stat &= ~0x20000000; } if (stat & 0x40000000) { - gk104_fifo_intr_runlist(priv); + gk104_fifo_intr_runlist(fifo); stat &= ~0x40000000; } if (stat & 0x80000000) { - nv_wr32(priv, 0x002100, 0x80000000); - gk104_fifo_intr_engine(priv); + nv_wr32(fifo, 0x002100, 0x80000000); + gk104_fifo_intr_engine(fifo); stat &= ~0x80000000; } if (stat) { - nv_error(priv, "INTR 0x%08x\n", stat); - nv_mask(priv, 0x002140, stat, 0x00000000); - nv_wr32(priv, 0x002100, stat); + nv_error(fifo, "INTR 0x%08x\n", stat); + nv_mask(fifo, 0x002140, stat, 0x00000000); + nv_wr32(fifo, 0x002100, stat); } } @@ -1010,68 +1022,68 @@ gk104_fifo_uevent_func = { int gk104_fifo_fini(struct nvkm_object *object, bool suspend) { - struct gk104_fifo_priv *priv = (void *)object; + struct gk104_fifo *fifo = (void *)object; int ret; - ret = nvkm_fifo_fini(&priv->base, suspend); + ret = nvkm_fifo_fini(&fifo->base, suspend); if (ret) return ret; /* allow mmu fault interrupts, even when we're not using fifo */ - nv_mask(priv, 0x002140, 0x10000000, 0x10000000); + nv_mask(fifo, 0x002140, 0x10000000, 0x10000000); return 0; } int gk104_fifo_init(struct nvkm_object *object) { - struct gk104_fifo_priv *priv = (void *)object; + struct gk104_fifo *fifo = (void *)object; int ret, i; - ret = nvkm_fifo_init(&priv->base); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; /* enable all available PBDMA units */ - nv_wr32(priv, 0x000204, 0xffffffff); - priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204)); - nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); + nv_wr32(fifo, 0x000204, 0xffffffff); + fifo->spoon_nr = hweight32(nv_rd32(fifo, 0x000204)); + nv_debug(fifo, "%d PBDMA unit(s)\n", fifo->spoon_nr); /* PBDMA[n] */ - for (i = 0; i < priv->spoon_nr; i++) { - nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); - nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ - nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ + for (i = 0; i < fifo->spoon_nr; i++) { + nv_mask(fifo, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); + nv_wr32(fifo, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ + nv_wr32(fifo, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ } /* PBDMA[n].HCE */ - for (i = 0; i < priv->spoon_nr; i++) { - nv_wr32(priv, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */ - nv_wr32(priv, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */ + for (i = 0; i < fifo->spoon_nr; i++) { + nv_wr32(fifo, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */ + nv_wr32(fifo, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */ } - nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); + nv_wr32(fifo, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); - nv_wr32(priv, 0x002100, 0xffffffff); - nv_wr32(priv, 0x002140, 0x7fffffff); + nv_wr32(fifo, 0x002100, 0xffffffff); + nv_wr32(fifo, 0x002140, 0x7fffffff); return 0; } void gk104_fifo_dtor(struct nvkm_object *object) { - struct gk104_fifo_priv *priv = (void *)object; + struct gk104_fifo *fifo = (void *)object; int i; - nvkm_gpuobj_unmap(&priv->user.bar); - nvkm_gpuobj_ref(NULL, &priv->user.mem); + nvkm_gpuobj_unmap(&fifo->user.bar); + nvkm_gpuobj_ref(NULL, &fifo->user.mem); for (i = 0; i < FIFO_ENGINE_NR; i++) { - nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); - nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); + nvkm_gpuobj_ref(NULL, &fifo->engine[i].runlist[1]); + nvkm_gpuobj_ref(NULL, &fifo->engine[i].runlist[0]); } - nvkm_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&fifo->base); } int @@ -1080,49 +1092,49 @@ gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct gk104_fifo_impl *impl = (void *)oclass; - struct gk104_fifo_priv *priv; + struct gk104_fifo *fifo; int ret, i; ret = nvkm_fifo_create(parent, engine, oclass, 0, - impl->channels - 1, &priv); - *pobject = nv_object(priv); + impl->channels - 1, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - INIT_WORK(&priv->fault, gk104_fifo_recover_work); + INIT_WORK(&fifo->fault, gk104_fifo_recover_work); for (i = 0; i < FIFO_ENGINE_NR; i++) { - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, - 0, &priv->engine[i].runlist[0]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x8000, 0x1000, + 0, &fifo->engine[i].runlist[0]); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, - 0, &priv->engine[i].runlist[1]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x8000, 0x1000, + 0, &fifo->engine[i].runlist[1]); if (ret) return ret; - init_waitqueue_head(&priv->engine[i].wait); + init_waitqueue_head(&fifo->engine[i].wait); } - ret = nvkm_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, impl->channels * 0x200, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &fifo->user.mem); if (ret) return ret; - ret = nvkm_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, - &priv->user.bar); + ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW, + &fifo->user.bar); if (ret) return ret; - ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &priv->base.uevent); + ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &fifo->base.uevent); if (ret) return ret; - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = gk104_fifo_intr; - nv_engine(priv)->cclass = &gk104_fifo_cclass; - nv_engine(priv)->sclass = gk104_fifo_sclass; + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = gk104_fifo_intr; + nv_engine(fifo)->cclass = &gk104_fifo_cclass; + nv_engine(fifo)->sclass = gk104_fifo_sclass; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c index 7596587b0e7c..6a93b911e8a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c @@ -38,8 +38,8 @@ gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, { int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); if (ret == 0) { - struct gk104_fifo_priv *priv = (void *)*pobject; - nv_engine(priv)->sclass = gm204_fifo_sclass; + struct gk104_fifo *fifo = (void *)*pobject; + nv_engine(fifo)->sclass = gm204_fifo_sclass; } return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index bdf635f9ab5f..91a2080bdaf9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -54,7 +54,7 @@ int nv04_fifo_object_attach(struct nvkm_object *parent, struct nvkm_object *object, u32 handle) { - struct nv04_fifo_priv *priv = (void *)parent->engine; + struct nv04_fifo *fifo = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; u32 context, chid = chan->base.chid; int ret; @@ -82,19 +82,19 @@ nv04_fifo_object_attach(struct nvkm_object *parent, context |= 0x80000000; /* valid */ context |= chid << 24; - mutex_lock(&nv_subdev(priv)->mutex); - ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); - mutex_unlock(&nv_subdev(priv)->mutex); + mutex_lock(&nv_subdev(fifo)->mutex); + ret = nvkm_ramht_insert(fifo->ramht, chid, handle, context); + mutex_unlock(&nv_subdev(fifo)->mutex); return ret; } void nv04_fifo_object_detach(struct nvkm_object *parent, int cookie) { - struct nv04_fifo_priv *priv = (void *)parent->engine; - mutex_lock(&nv_subdev(priv)->mutex); - nvkm_ramht_remove(priv->ramht, cookie); - mutex_unlock(&nv_subdev(priv)->mutex); + struct nv04_fifo *fifo = (void *)parent->engine; + mutex_lock(&nv_subdev(fifo)->mutex); + nvkm_ramht_remove(fifo->ramht, cookie); + mutex_unlock(&nv_subdev(fifo)->mutex); } int @@ -114,7 +114,7 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent, union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo_priv *priv = (void *)engine; + struct nv04_fifo *fifo = (void *)engine; struct nv04_fifo_chan *chan; int ret; @@ -142,10 +142,10 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent, nv_parent(chan)->context_attach = nv04_fifo_context_attach; chan->ramfc = chan->base.chid * 32; - nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); - nv_wo32(priv->ramfc, chan->ramfc + 0x10, + nv_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); + nv_wo32(fifo->ramfc, chan->ramfc + 0x10, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | #ifdef __BIG_ENDIAN @@ -158,12 +158,12 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent, void nv04_fifo_chan_dtor(struct nvkm_object *object) { - struct nv04_fifo_priv *priv = (void *)object->engine; + struct nv04_fifo *fifo = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; - struct ramfc_desc *c = priv->ramfc_desc; + struct ramfc_desc *c = fifo->ramfc_desc; do { - nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); + nv_wo32(fifo->ramfc, chan->ramfc + c->ctxp, 0x00000000); } while ((++c)->bits); nvkm_fifo_channel_destroy(&chan->base); @@ -172,7 +172,7 @@ nv04_fifo_chan_dtor(struct nvkm_object *object) int nv04_fifo_chan_init(struct nvkm_object *object) { - struct nv04_fifo_priv *priv = (void *)object->engine; + struct nv04_fifo *fifo = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; u32 mask = 1 << chan->base.chid; unsigned long flags; @@ -182,59 +182,59 @@ nv04_fifo_chan_init(struct nvkm_object *object) if (ret) return ret; - spin_lock_irqsave(&priv->base.lock, flags); - nv_mask(priv, NV04_PFIFO_MODE, mask, mask); - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_lock_irqsave(&fifo->base.lock, flags); + nv_mask(fifo, NV04_PFIFO_MODE, mask, mask); + spin_unlock_irqrestore(&fifo->base.lock, flags); return 0; } int nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct nv04_fifo_priv *priv = (void *)object->engine; + struct nv04_fifo *fifo = (void *)object->engine; struct nv04_fifo_chan *chan = (void *)object; - struct nvkm_gpuobj *fctx = priv->ramfc; + struct nvkm_gpuobj *fctx = fifo->ramfc; struct ramfc_desc *c; unsigned long flags; u32 data = chan->ramfc; u32 chid; /* prevent fifo context switches */ - spin_lock_irqsave(&priv->base.lock, flags); - nv_wr32(priv, NV03_PFIFO_CACHES, 0); + spin_lock_irqsave(&fifo->base.lock, flags); + nv_wr32(fifo, NV03_PFIFO_CACHES, 0); /* if this channel is active, replace it with a null context */ - chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; + chid = nv_rd32(fifo, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max; if (chid == chan->base.chid) { - nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0); - nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); + nv_mask(fifo, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 0); + nv_mask(fifo, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); - c = priv->ramfc_desc; + c = fifo->ramfc_desc; do { u32 rm = ((1ULL << c->bits) - 1) << c->regs; u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; - u32 rv = (nv_rd32(priv, c->regp) & rm) >> c->regs; + u32 rv = (nv_rd32(fifo, c->regp) & rm) >> c->regs; u32 cv = (nv_ro32(fctx, c->ctxp + data) & ~cm); nv_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); } while ((++c)->bits); - c = priv->ramfc_desc; + c = fifo->ramfc_desc; do { - nv_wr32(priv, c->regp, 0x00000000); + nv_wr32(fifo, c->regp, 0x00000000); } while ((++c)->bits); - nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(fifo, NV03_PFIFO_CACHE1_GET, 0); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUT, 0); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1); } /* restore normal operation, after disabling dma mode */ - nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); - nv_wr32(priv, NV03_PFIFO_CACHES, 1); - spin_unlock_irqrestore(&priv->base.lock, flags); + nv_mask(fifo, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); + nv_wr32(fifo, NV03_PFIFO_CACHES, 1); + spin_unlock_irqrestore(&fifo->base.lock, flags); return nvkm_fifo_channel_fini(&chan->base, suspend); } @@ -297,17 +297,17 @@ nv04_fifo_cclass = { ******************************************************************************/ void -nv04_fifo_pause(struct nvkm_fifo *pfifo, unsigned long *pflags) -__acquires(priv->base.lock) +nv04_fifo_pause(struct nvkm_fifo *obj, unsigned long *pflags) +__acquires(fifo->base.lock) { - struct nv04_fifo_priv *priv = (void *)pfifo; + struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base); unsigned long flags; - spin_lock_irqsave(&priv->base.lock, flags); + spin_lock_irqsave(&fifo->base.lock, flags); *pflags = flags; - nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000); - nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); + nv_wr32(fifo, NV03_PFIFO_CACHES, 0x00000000); + nv_mask(fifo, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); /* in some cases the puller may be left in an inconsistent state * if you try to stop it while it's busy translating handles. @@ -318,28 +318,28 @@ __acquires(priv->base.lock) * to avoid this, we invalidate the most recently calculated * instance. */ - if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0, + if (!nv_wait(fifo, NV04_PFIFO_CACHE1_PULL0, NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0x00000000)) - nv_warn(priv, "timeout idling puller\n"); + nv_warn(fifo, "timeout idling puller\n"); - if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) & + if (nv_rd32(fifo, NV04_PFIFO_CACHE1_PULL0) & NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) - nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); + nv_wr32(fifo, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); - nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0x00000000); + nv_wr32(fifo, NV04_PFIFO_CACHE1_HASH, 0x00000000); } void -nv04_fifo_start(struct nvkm_fifo *pfifo, unsigned long *pflags) -__releases(priv->base.lock) +nv04_fifo_start(struct nvkm_fifo *obj, unsigned long *pflags) +__releases(fifo->base.lock) { - struct nv04_fifo_priv *priv = (void *)pfifo; + struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base); unsigned long flags = *pflags; - nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); - nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000001); + nv_mask(fifo, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); + nv_wr32(fifo, NV03_PFIFO_CACHES, 0x00000001); - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_unlock_irqrestore(&fifo->base.lock, flags); } static const char * @@ -353,7 +353,7 @@ nv_dma_state_err(u32 state) } static bool -nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) +nv04_fifo_swmthd(struct nv04_fifo *fifo, u32 chid, u32 addr, u32 data) { struct nv04_fifo_chan *chan = NULL; struct nvkm_handle *bind; @@ -363,9 +363,9 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) unsigned long flags; u32 engine; - spin_lock_irqsave(&priv->base.lock, flags); - if (likely(chid >= priv->base.min && chid <= priv->base.max)) - chan = (void *)priv->base.channel[chid]; + spin_lock_irqsave(&fifo->base.lock, flags); + if (likely(chid >= fifo->base.min && chid <= fifo->base.max)) + chan = (void *)fifo->base.channel[chid]; if (unlikely(!chan)) goto out; @@ -380,13 +380,13 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) chan->subc[subc] = data; handled = true; - nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); + nv_mask(fifo, NV04_PFIFO_CACHE1_ENGINE, engine, 0); } nvkm_namedb_put(bind); break; default: - engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); + engine = nv_rd32(fifo, NV04_PFIFO_CACHE1_ENGINE); if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) break; @@ -400,13 +400,13 @@ nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) } out: - spin_unlock_irqrestore(&priv->base.lock, flags); + spin_unlock_irqrestore(&fifo->base.lock, flags); return handled; } static void nv04_fifo_cache_error(struct nvkm_device *device, - struct nv04_fifo_priv *priv, u32 chid, u32 get) + struct nv04_fifo *fifo, u32 chid, u32 get) { u32 mthd, data; int ptr; @@ -419,139 +419,139 @@ nv04_fifo_cache_error(struct nvkm_device *device, ptr = (get & 0x7ff) >> 2; if (device->card_type < NV_40) { - mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr)); - data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr)); + mthd = nv_rd32(fifo, NV04_PFIFO_CACHE1_METHOD(ptr)); + data = nv_rd32(fifo, NV04_PFIFO_CACHE1_DATA(ptr)); } else { - mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr)); - data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr)); + mthd = nv_rd32(fifo, NV40_PFIFO_CACHE1_METHOD(ptr)); + data = nv_rd32(fifo, NV40_PFIFO_CACHE1_DATA(ptr)); } - if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { + if (!nv04_fifo_swmthd(fifo, chid, mthd, data)) { const char *client_name = - nvkm_client_name_for_fifo_chid(&priv->base, chid); - nv_error(priv, + nvkm_client_name_for_fifo_chid(&fifo->base, chid); + nv_error(fifo, "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, data); } - nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0); - nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); + nv_wr32(fifo, NV04_PFIFO_CACHE1_DMA_PUSH, 0); + nv_wr32(fifo, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, - nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1); - nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, - nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1); - nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, + nv_rd32(fifo, NV03_PFIFO_CACHE1_PUSH0) & ~1); + nv_wr32(fifo, NV03_PFIFO_CACHE1_GET, get + 4); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, + nv_rd32(fifo, NV03_PFIFO_CACHE1_PUSH0) | 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_HASH, 0); - nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, - nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_DMA_PUSH, + nv_rd32(fifo, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1); } static void nv04_fifo_dma_pusher(struct nvkm_device *device, - struct nv04_fifo_priv *priv, u32 chid) + struct nv04_fifo *fifo, u32 chid) { const char *client_name; - u32 dma_get = nv_rd32(priv, 0x003244); - u32 dma_put = nv_rd32(priv, 0x003240); - u32 push = nv_rd32(priv, 0x003220); - u32 state = nv_rd32(priv, 0x003228); + u32 dma_get = nv_rd32(fifo, 0x003244); + u32 dma_put = nv_rd32(fifo, 0x003240); + u32 push = nv_rd32(fifo, 0x003220); + u32 state = nv_rd32(fifo, 0x003228); - client_name = nvkm_client_name_for_fifo_chid(&priv->base, chid); + client_name = nvkm_client_name_for_fifo_chid(&fifo->base, chid); if (device->card_type == NV_50) { - u32 ho_get = nv_rd32(priv, 0x003328); - u32 ho_put = nv_rd32(priv, 0x003320); - u32 ib_get = nv_rd32(priv, 0x003334); - u32 ib_put = nv_rd32(priv, 0x003330); + u32 ho_get = nv_rd32(fifo, 0x003328); + u32 ho_put = nv_rd32(fifo, 0x003320); + u32 ib_get = nv_rd32(fifo, 0x003334); + u32 ib_put = nv_rd32(fifo, 0x003330); - nv_error(priv, + nv_error(fifo, "DMA_PUSHER - ch %d [%s] get 0x%02x%08x put 0x%02x%08x ib_get 0x%08x ib_put 0x%08x state 0x%08x (err: %s) push 0x%08x\n", chid, client_name, ho_get, dma_get, ho_put, dma_put, ib_get, ib_put, state, nv_dma_state_err(state), push); /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ - nv_wr32(priv, 0x003364, 0x00000000); + nv_wr32(fifo, 0x003364, 0x00000000); if (dma_get != dma_put || ho_get != ho_put) { - nv_wr32(priv, 0x003244, dma_put); - nv_wr32(priv, 0x003328, ho_put); + nv_wr32(fifo, 0x003244, dma_put); + nv_wr32(fifo, 0x003328, ho_put); } else if (ib_get != ib_put) - nv_wr32(priv, 0x003334, ib_put); + nv_wr32(fifo, 0x003334, ib_put); } else { - nv_error(priv, + nv_error(fifo, "DMA_PUSHER - ch %d [%s] get 0x%08x put 0x%08x state 0x%08x (err: %s) push 0x%08x\n", chid, client_name, dma_get, dma_put, state, nv_dma_state_err(state), push); if (dma_get != dma_put) - nv_wr32(priv, 0x003244, dma_put); + nv_wr32(fifo, 0x003244, dma_put); } - nv_wr32(priv, 0x003228, 0x00000000); - nv_wr32(priv, 0x003220, 0x00000001); - nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); + nv_wr32(fifo, 0x003228, 0x00000000); + nv_wr32(fifo, 0x003220, 0x00000001); + nv_wr32(fifo, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); } void nv04_fifo_intr(struct nvkm_subdev *subdev) { struct nvkm_device *device = nv_device(subdev); - struct nv04_fifo_priv *priv = (void *)subdev; - u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0); - u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask; + struct nv04_fifo *fifo = (void *)subdev; + u32 mask = nv_rd32(fifo, NV03_PFIFO_INTR_EN_0); + u32 stat = nv_rd32(fifo, NV03_PFIFO_INTR_0) & mask; u32 reassign, chid, get, sem; - reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; - nv_wr32(priv, NV03_PFIFO_CACHES, 0); + reassign = nv_rd32(fifo, NV03_PFIFO_CACHES) & 1; + nv_wr32(fifo, NV03_PFIFO_CACHES, 0); - chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; - get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); + chid = nv_rd32(fifo, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max; + get = nv_rd32(fifo, NV03_PFIFO_CACHE1_GET); if (stat & NV_PFIFO_INTR_CACHE_ERROR) { - nv04_fifo_cache_error(device, priv, chid, get); + nv04_fifo_cache_error(device, fifo, chid, get); stat &= ~NV_PFIFO_INTR_CACHE_ERROR; } if (stat & NV_PFIFO_INTR_DMA_PUSHER) { - nv04_fifo_dma_pusher(device, priv, chid); + nv04_fifo_dma_pusher(device, fifo, chid); stat &= ~NV_PFIFO_INTR_DMA_PUSHER; } if (stat & NV_PFIFO_INTR_SEMAPHORE) { stat &= ~NV_PFIFO_INTR_SEMAPHORE; - nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); + nv_wr32(fifo, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); - sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); - nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); + sem = nv_rd32(fifo, NV10_PFIFO_CACHE1_SEMAPHORE); + nv_wr32(fifo, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); - nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(fifo, NV03_PFIFO_CACHE1_GET, get + 4); + nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1); } if (device->card_type == NV_50) { if (stat & 0x00000010) { stat &= ~0x00000010; - nv_wr32(priv, 0x002100, 0x00000010); + nv_wr32(fifo, 0x002100, 0x00000010); } if (stat & 0x40000000) { - nv_wr32(priv, 0x002100, 0x40000000); - nvkm_fifo_uevent(&priv->base); + nv_wr32(fifo, 0x002100, 0x40000000); + nvkm_fifo_uevent(&fifo->base); stat &= ~0x40000000; } } if (stat) { - nv_warn(priv, "unknown intr 0x%08x\n", stat); - nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); - nv_wr32(priv, NV03_PFIFO_INTR_0, stat); + nv_warn(fifo, "unknown intr 0x%08x\n", stat); + nv_mask(fifo, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); + nv_wr32(fifo, NV03_PFIFO_INTR_0, stat); } - nv_wr32(priv, NV03_PFIFO_CACHES, reassign); + nv_wr32(fifo, NV03_PFIFO_CACHES, reassign); } static int @@ -560,65 +560,65 @@ nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv04_instmem *imem = nv04_instmem(parent); - struct nv04_fifo_priv *priv; + struct nv04_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - nvkm_ramht_ref(imem->ramht, &priv->ramht); - nvkm_gpuobj_ref(imem->ramro, &priv->ramro); - nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); - - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv04_fifo_cclass; - nv_engine(priv)->sclass = nv04_fifo_sclass; - priv->base.pause = nv04_fifo_pause; - priv->base.start = nv04_fifo_start; - priv->ramfc_desc = nv04_ramfc; + nvkm_ramht_ref(imem->ramht, &fifo->ramht); + nvkm_gpuobj_ref(imem->ramro, &fifo->ramro); + nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc); + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv04_fifo_cclass; + nv_engine(fifo)->sclass = nv04_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv04_ramfc; return 0; } void nv04_fifo_dtor(struct nvkm_object *object) { - struct nv04_fifo_priv *priv = (void *)object; - nvkm_gpuobj_ref(NULL, &priv->ramfc); - nvkm_gpuobj_ref(NULL, &priv->ramro); - nvkm_ramht_ref(NULL, &priv->ramht); - nvkm_fifo_destroy(&priv->base); + struct nv04_fifo *fifo = (void *)object; + nvkm_gpuobj_ref(NULL, &fifo->ramfc); + nvkm_gpuobj_ref(NULL, &fifo->ramro); + nvkm_ramht_ref(NULL, &fifo->ramht); + nvkm_fifo_destroy(&fifo->base); } int nv04_fifo_init(struct nvkm_object *object) { - struct nv04_fifo_priv *priv = (void *)object; + struct nv04_fifo *fifo = (void *)object; int ret; - ret = nvkm_fifo_init(&priv->base); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; - nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); - nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); + nv_wr32(fifo, NV04_PFIFO_DELAY_0, 0x000000ff); + nv_wr32(fifo, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); - nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | - ((priv->ramht->bits - 9) << 16) | - (priv->ramht->gpuobj.addr >> 8)); - nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); - nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8); + nv_wr32(fifo, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | + ((fifo->ramht->bits - 9) << 16) | + (fifo->ramht->gpuobj.addr >> 8)); + nv_wr32(fifo, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8); + nv_wr32(fifo, NV03_PFIFO_RAMFC, fifo->ramfc->addr >> 8); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); - nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); - nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); + nv_wr32(fifo, NV03_PFIFO_INTR_0, 0xffffffff); + nv_wr32(fifo, NV03_PFIFO_INTR_EN_0, 0xffffffff); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); - nv_wr32(priv, NV03_PFIFO_CACHES, 1); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(fifo, NV03_PFIFO_CACHES, 1); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index e0e0c47cb4ca..cb4ec7bd7c51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -139,7 +139,7 @@ struct ramfc_desc { unsigned regp; }; -struct nv04_fifo_priv { +struct nv04_fifo { struct nvkm_fifo base; struct ramfc_desc *ramfc_desc; struct nvkm_ramht *ramht; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index 3537accc927b..7c31c31edd9a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -58,7 +58,7 @@ nv10_fifo_chan_ctor(struct nvkm_object *parent, union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo_priv *priv = (void *)engine; + struct nv04_fifo *fifo = (void *)engine; struct nv04_fifo_chan *chan; int ret; @@ -86,10 +86,10 @@ nv10_fifo_chan_ctor(struct nvkm_object *parent, nv_parent(chan)->context_attach = nv04_fifo_context_attach; chan->ramfc = chan->base.chid * 32; - nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); - nv_wo32(priv->ramfc, chan->ramfc + 0x14, + nv_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nv_wo32(fifo->ramfc, chan->ramfc + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | #ifdef __BIG_ENDIAN @@ -144,25 +144,25 @@ nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv04_instmem *imem = nv04_instmem(parent); - struct nv04_fifo_priv *priv; + struct nv04_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - nvkm_ramht_ref(imem->ramht, &priv->ramht); - nvkm_gpuobj_ref(imem->ramro, &priv->ramro); - nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); - - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv10_fifo_cclass; - nv_engine(priv)->sclass = nv10_fifo_sclass; - priv->base.pause = nv04_fifo_pause; - priv->base.start = nv04_fifo_start; - priv->ramfc_desc = nv10_ramfc; + nvkm_ramht_ref(imem->ramht, &fifo->ramht); + nvkm_gpuobj_ref(imem->ramro, &fifo->ramro); + nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc); + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv10_fifo_cclass; + nv_engine(fifo)->sclass = nv10_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv10_ramfc; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index e9c88da81f10..6f8787fbacc0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -63,7 +63,7 @@ nv17_fifo_chan_ctor(struct nvkm_object *parent, union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo_priv *priv = (void *)engine; + struct nv04_fifo *fifo = (void *)engine; struct nv04_fifo_chan *chan; int ret; @@ -93,10 +93,10 @@ nv17_fifo_chan_ctor(struct nvkm_object *parent, nv_parent(chan)->context_attach = nv04_fifo_context_attach; chan->ramfc = chan->base.chid * 64; - nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); - nv_wo32(priv->ramfc, chan->ramfc + 0x14, + nv_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nv_wo32(fifo->ramfc, chan->ramfc + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | #ifdef __BIG_ENDIAN @@ -151,55 +151,55 @@ nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv04_instmem *imem = nv04_instmem(parent); - struct nv04_fifo_priv *priv; + struct nv04_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - nvkm_ramht_ref(imem->ramht, &priv->ramht); - nvkm_gpuobj_ref(imem->ramro, &priv->ramro); - nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); - - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv17_fifo_cclass; - nv_engine(priv)->sclass = nv17_fifo_sclass; - priv->base.pause = nv04_fifo_pause; - priv->base.start = nv04_fifo_start; - priv->ramfc_desc = nv17_ramfc; + nvkm_ramht_ref(imem->ramht, &fifo->ramht); + nvkm_gpuobj_ref(imem->ramro, &fifo->ramro); + nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc); + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv17_fifo_cclass; + nv_engine(fifo)->sclass = nv17_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv17_ramfc; return 0; } static int nv17_fifo_init(struct nvkm_object *object) { - struct nv04_fifo_priv *priv = (void *)object; + struct nv04_fifo *fifo = (void *)object; int ret; - ret = nvkm_fifo_init(&priv->base); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; - nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); - nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); + nv_wr32(fifo, NV04_PFIFO_DELAY_0, 0x000000ff); + nv_wr32(fifo, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); - nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | - ((priv->ramht->bits - 9) << 16) | - (priv->ramht->gpuobj.addr >> 8)); - nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); - nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); + nv_wr32(fifo, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | + ((fifo->ramht->bits - 9) << 16) | + (fifo->ramht->gpuobj.addr >> 8)); + nv_wr32(fifo, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8); + nv_wr32(fifo, NV03_PFIFO_RAMFC, fifo->ramfc->addr >> 8 | 0x00010000); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); - nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); - nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); + nv_wr32(fifo, NV03_PFIFO_INTR_0, 0xffffffff); + nv_wr32(fifo, NV03_PFIFO_INTR_EN_0, 0xffffffff); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); - nv_wr32(priv, NV03_PFIFO_CACHES, 1); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(fifo, NV03_PFIFO_CACHES, 1); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index f9456a5c762c..4c1ed3f29e6b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -67,7 +67,7 @@ static int nv40_fifo_object_attach(struct nvkm_object *parent, struct nvkm_object *object, u32 handle) { - struct nv04_fifo_priv *priv = (void *)parent->engine; + struct nv04_fifo *fifo = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; u32 context, chid = chan->base.chid; int ret; @@ -94,16 +94,16 @@ nv40_fifo_object_attach(struct nvkm_object *parent, context |= chid << 23; - mutex_lock(&nv_subdev(priv)->mutex); - ret = nvkm_ramht_insert(priv->ramht, chid, handle, context); - mutex_unlock(&nv_subdev(priv)->mutex); + mutex_lock(&nv_subdev(fifo)->mutex); + ret = nvkm_ramht_insert(fifo->ramht, chid, handle, context); + mutex_unlock(&nv_subdev(fifo)->mutex); return ret; } static int nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) { - struct nv04_fifo_priv *priv = (void *)parent->engine; + struct nv04_fifo *fifo = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; unsigned long flags; u32 reg, ctx; @@ -123,16 +123,16 @@ nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) return -EINVAL; } - spin_lock_irqsave(&priv->base.lock, flags); + spin_lock_irqsave(&fifo->base.lock, flags); nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; - nv_mask(priv, 0x002500, 0x00000001, 0x00000000); + nv_mask(fifo, 0x002500, 0x00000001, 0x00000000); - if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) - nv_wr32(priv, reg, nv_engctx(engctx)->addr); - nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); + if ((nv_rd32(fifo, 0x003204) & fifo->base.max) == chan->base.chid) + nv_wr32(fifo, reg, nv_engctx(engctx)->addr); + nv_wo32(fifo->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); - nv_mask(priv, 0x002500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->base.lock, flags); + nv_mask(fifo, 0x002500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&fifo->base.lock, flags); return 0; } @@ -140,7 +140,7 @@ static int nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_object *engctx) { - struct nv04_fifo_priv *priv = (void *)parent->engine; + struct nv04_fifo *fifo = (void *)parent->engine; struct nv04_fifo_chan *chan = (void *)parent; unsigned long flags; u32 reg, ctx; @@ -160,15 +160,15 @@ nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, return -EINVAL; } - spin_lock_irqsave(&priv->base.lock, flags); - nv_mask(priv, 0x002500, 0x00000001, 0x00000000); + spin_lock_irqsave(&fifo->base.lock, flags); + nv_mask(fifo, 0x002500, 0x00000001, 0x00000000); - if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) - nv_wr32(priv, reg, 0x00000000); - nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000); + if ((nv_rd32(fifo, 0x003204) & fifo->base.max) == chan->base.chid) + nv_wr32(fifo, reg, 0x00000000); + nv_wo32(fifo->ramfc, chan->ramfc + ctx, 0x00000000); - nv_mask(priv, 0x002500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->base.lock, flags); + nv_mask(fifo, 0x002500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&fifo->base.lock, flags); return 0; } @@ -180,7 +180,7 @@ nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo_priv *priv = (void *)engine; + struct nv04_fifo *fifo = (void *)engine; struct nv04_fifo_chan *chan; int ret; @@ -210,17 +210,17 @@ nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_parent(chan)->object_detach = nv04_fifo_object_detach; chan->ramfc = chan->base.chid * 128; - nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); - nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); - nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | + nv_wo32(fifo->ramfc, chan->ramfc + 0x00, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x04, args->v0.offset); + nv_wo32(fifo->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nv_wo32(fifo->ramfc, chan->ramfc + 0x18, 0x30000000 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | #ifdef __BIG_ENDIAN NV_PFIFO_CACHE1_BIG_ENDIAN | #endif NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff); + nv_wo32(fifo->ramfc, chan->ramfc + 0x3c, 0x0001ffff); return 0; } @@ -269,77 +269,77 @@ nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv04_instmem *imem = nv04_instmem(parent); - struct nv04_fifo_priv *priv; + struct nv04_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - nvkm_ramht_ref(imem->ramht, &priv->ramht); - nvkm_gpuobj_ref(imem->ramro, &priv->ramro); - nvkm_gpuobj_ref(imem->ramfc, &priv->ramfc); - - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv40_fifo_cclass; - nv_engine(priv)->sclass = nv40_fifo_sclass; - priv->base.pause = nv04_fifo_pause; - priv->base.start = nv04_fifo_start; - priv->ramfc_desc = nv40_ramfc; + nvkm_ramht_ref(imem->ramht, &fifo->ramht); + nvkm_gpuobj_ref(imem->ramro, &fifo->ramro); + nvkm_gpuobj_ref(imem->ramfc, &fifo->ramfc); + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv40_fifo_cclass; + nv_engine(fifo)->sclass = nv40_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv40_ramfc; return 0; } static int nv40_fifo_init(struct nvkm_object *object) { - struct nv04_fifo_priv *priv = (void *)object; + struct nv04_fifo *fifo = (void *)object; struct nvkm_fb *fb = nvkm_fb(object); int ret; - ret = nvkm_fifo_init(&priv->base); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; - nv_wr32(priv, 0x002040, 0x000000ff); - nv_wr32(priv, 0x002044, 0x2101ffff); - nv_wr32(priv, 0x002058, 0x00000001); + nv_wr32(fifo, 0x002040, 0x000000ff); + nv_wr32(fifo, 0x002044, 0x2101ffff); + nv_wr32(fifo, 0x002058, 0x00000001); - nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | - ((priv->ramht->bits - 9) << 16) | - (priv->ramht->gpuobj.addr >> 8)); - nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); + nv_wr32(fifo, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | + ((fifo->ramht->bits - 9) << 16) | + (fifo->ramht->gpuobj.addr >> 8)); + nv_wr32(fifo, NV03_PFIFO_RAMRO, fifo->ramro->addr >> 8); - switch (nv_device(priv)->chipset) { + switch (nv_device(fifo)->chipset) { case 0x47: case 0x49: case 0x4b: - nv_wr32(priv, 0x002230, 0x00000001); + nv_wr32(fifo, 0x002230, 0x00000001); case 0x40: case 0x41: case 0x42: case 0x43: case 0x45: case 0x48: - nv_wr32(priv, 0x002220, 0x00030002); + nv_wr32(fifo, 0x002220, 0x00030002); break; default: - nv_wr32(priv, 0x002230, 0x00000000); - nv_wr32(priv, 0x002220, ((fb->ram->size - 512 * 1024 + - priv->ramfc->addr) >> 16) | + nv_wr32(fifo, 0x002230, 0x00000000); + nv_wr32(fifo, 0x002220, ((fb->ram->size - 512 * 1024 + + fifo->ramfc->addr) >> 16) | 0x00030000); break; } - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); - nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); - nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); + nv_wr32(fifo, NV03_PFIFO_INTR_0, 0xffffffff); + nv_wr32(fifo, NV03_PFIFO_INTR_EN_0, 0xffffffff); - nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); - nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); - nv_wr32(priv, NV03_PFIFO_CACHES, 1); + nv_wr32(fifo, NV03_PFIFO_CACHE1_PUSH0, 1); + nv_wr32(fifo, NV04_PFIFO_CACHE1_PULL0, 1); + nv_wr32(fifo, NV03_PFIFO_CACHES, 1); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index f25f0fd0655d..a36f7efc4658 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -39,33 +39,33 @@ ******************************************************************************/ static void -nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv) +nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo) { - struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_bar *bar = nvkm_bar(fifo); struct nvkm_gpuobj *cur; int i, p; - cur = priv->playlist[priv->cur_playlist]; - priv->cur_playlist = !priv->cur_playlist; + cur = fifo->playlist[fifo->cur_playlist]; + fifo->cur_playlist = !fifo->cur_playlist; - for (i = priv->base.min, p = 0; i < priv->base.max; i++) { - if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000) + for (i = fifo->base.min, p = 0; i < fifo->base.max; i++) { + if (nv_rd32(fifo, 0x002600 + (i * 4)) & 0x80000000) nv_wo32(cur, p++ * 4, i); } bar->flush(bar); - nv_wr32(priv, 0x0032f4, cur->addr >> 12); - nv_wr32(priv, 0x0032ec, p); - nv_wr32(priv, 0x002500, 0x00000101); + nv_wr32(fifo, 0x0032f4, cur->addr >> 12); + nv_wr32(fifo, 0x0032ec, p); + nv_wr32(fifo, 0x002500, 0x00000101); } void -nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) +nv50_fifo_playlist_update(struct nv50_fifo *fifo) { - mutex_lock(&nv_subdev(priv)->mutex); - nv50_fifo_playlist_update_locked(priv); - mutex_unlock(&nv_subdev(priv)->mutex); + mutex_lock(&nv_subdev(fifo)->mutex); + nv50_fifo_playlist_update_locked(fifo); + mutex_unlock(&nv_subdev(fifo)->mutex); } static int @@ -103,7 +103,7 @@ nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_object *object) { struct nvkm_bar *bar = nvkm_bar(parent); - struct nv50_fifo_priv *priv = (void *)parent->engine; + struct nv50_fifo *fifo = (void *)parent->engine; struct nv50_fifo_base *base = (void *)parent->parent; struct nv50_fifo_chan *chan = (void *)parent; u32 addr, me; @@ -129,17 +129,17 @@ nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, * there's also a "ignore these engines" bitmask reg we can use * if we hit the issue there.. */ - me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001); + me = nv_mask(fifo, 0x00b860, 0x00000001, 0x00000001); /* do the kickoff... */ - nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); - if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) { - nv_error(priv, "channel %d [%s] unload timeout\n", + nv_wr32(fifo, 0x0032fc, nv_gpuobj(base)->addr >> 12); + if (!nv_wait_ne(fifo, 0x0032fc, 0xffffffff, 0xffffffff)) { + nv_error(fifo, "channel %d [%s] unload timeout\n", chan->base.chid, nvkm_client_name(chan)); if (suspend) ret = -EBUSY; } - nv_wr32(priv, 0x00b860, me); + nv_wr32(fifo, 0x00b860, me); if (ret == 0) { nv_wo32(base->eng, addr + 0x00, 0x00000000); @@ -320,7 +320,7 @@ nv50_fifo_chan_dtor(struct nvkm_object *object) static int nv50_fifo_chan_init(struct nvkm_object *object) { - struct nv50_fifo_priv *priv = (void *)object->engine; + struct nv50_fifo *fifo = (void *)object->engine; struct nv50_fifo_base *base = (void *)object->parent; struct nv50_fifo_chan *chan = (void *)object; struct nvkm_gpuobj *ramfc = base->ramfc; @@ -331,22 +331,22 @@ nv50_fifo_chan_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); - nv50_fifo_playlist_update(priv); + nv_wr32(fifo, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); + nv50_fifo_playlist_update(fifo); return 0; } int nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) { - struct nv50_fifo_priv *priv = (void *)object->engine; + struct nv50_fifo *fifo = (void *)object->engine; struct nv50_fifo_chan *chan = (void *)object; u32 chid = chan->base.chid; /* remove channel from playlist, fifo will unload context */ - nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000); - nv50_fifo_playlist_update(priv); - nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000); + nv_mask(fifo, 0x002600 + (chid * 4), 0x80000000, 0x00000000); + nv50_fifo_playlist_update(fifo); + nv_wr32(fifo, 0x002600 + (chid * 4), 0x00000000); return nvkm_fifo_channel_fini(&chan->base, suspend); } @@ -456,69 +456,69 @@ nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_fifo_priv *priv; + struct nv50_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); - *pobject = nv_object(priv); + ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); + *pobject = nv_object(fifo); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[0]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0, + &fifo->playlist[0]); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, - &priv->playlist[1]); + ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0, + &fifo->playlist[1]); if (ret) return ret; - nv_subdev(priv)->unit = 0x00000100; - nv_subdev(priv)->intr = nv04_fifo_intr; - nv_engine(priv)->cclass = &nv50_fifo_cclass; - nv_engine(priv)->sclass = nv50_fifo_sclass; - priv->base.pause = nv04_fifo_pause; - priv->base.start = nv04_fifo_start; + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv50_fifo_cclass; + nv_engine(fifo)->sclass = nv50_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; return 0; } void nv50_fifo_dtor(struct nvkm_object *object) { - struct nv50_fifo_priv *priv = (void *)object; + struct nv50_fifo *fifo = (void *)object; - nvkm_gpuobj_ref(NULL, &priv->playlist[1]); - nvkm_gpuobj_ref(NULL, &priv->playlist[0]); + nvkm_gpuobj_ref(NULL, &fifo->playlist[1]); + nvkm_gpuobj_ref(NULL, &fifo->playlist[0]); - nvkm_fifo_destroy(&priv->base); + nvkm_fifo_destroy(&fifo->base); } int nv50_fifo_init(struct nvkm_object *object) { - struct nv50_fifo_priv *priv = (void *)object; + struct nv50_fifo *fifo = (void *)object; int ret, i; - ret = nvkm_fifo_init(&priv->base); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; - nv_mask(priv, 0x000200, 0x00000100, 0x00000000); - nv_mask(priv, 0x000200, 0x00000100, 0x00000100); - nv_wr32(priv, 0x00250c, 0x6f3cfc34); - nv_wr32(priv, 0x002044, 0x01003fff); + nv_mask(fifo, 0x000200, 0x00000100, 0x00000000); + nv_mask(fifo, 0x000200, 0x00000100, 0x00000100); + nv_wr32(fifo, 0x00250c, 0x6f3cfc34); + nv_wr32(fifo, 0x002044, 0x01003fff); - nv_wr32(priv, 0x002100, 0xffffffff); - nv_wr32(priv, 0x002140, 0xbfffffff); + nv_wr32(fifo, 0x002100, 0xffffffff); + nv_wr32(fifo, 0x002140, 0xbfffffff); for (i = 0; i < 128; i++) - nv_wr32(priv, 0x002600 + (i * 4), 0x00000000); - nv50_fifo_playlist_update_locked(priv); + nv_wr32(fifo, 0x002600 + (i * 4), 0x00000000); + nv50_fifo_playlist_update_locked(fifo); - nv_wr32(priv, 0x003200, 0x00000001); - nv_wr32(priv, 0x003250, 0x00000001); - nv_wr32(priv, 0x002500, 0x00000001); + nv_wr32(fifo, 0x003200, 0x00000001); + nv_wr32(fifo, 0x003250, 0x00000001); + nv_wr32(fifo, 0x002500, 0x00000001); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index 09ed93c66567..722fcce7070e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -2,7 +2,7 @@ #define __NV50_FIFO_H__ #include -struct nv50_fifo_priv { +struct nv50_fifo { struct nvkm_fifo base; struct nvkm_gpuobj *playlist[2]; int cur_playlist; @@ -23,7 +23,7 @@ struct nv50_fifo_chan { struct nvkm_ramht *ramht; }; -void nv50_fifo_playlist_update(struct nv50_fifo_priv *); +void nv50_fifo_playlist_update(struct nv50_fifo *); void nv50_fifo_object_detach(struct nvkm_object *, int); void nv50_fifo_chan_dtor(struct nvkm_object *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 1ca9385f5479..b0b5fadfc550 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1121,7 +1121,7 @@ gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv) static void gf100_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle; @@ -1142,7 +1142,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) class = 0x0000; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat & 0x00000001) { /* diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 535f5930c40b..57f05c86a591 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -1119,18 +1119,18 @@ static void nv10_gr_tile_prog(struct nvkm_engine *engine, int i) { struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; - struct nvkm_fifo *pfifo = nvkm_fifo(engine); + struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nv10_gr_priv *priv = (void *)engine; unsigned long flags; - pfifo->pause(pfifo, &flags); + fifo->pause(fifo, &flags); nv04_gr_idle(priv); nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr); - pfifo->start(pfifo, &flags); + fifo->start(fifo, &flags); } const struct nvkm_bitfield nv10_gr_intr_name[] = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 0aa4cc9f74e1..14a83f2a8127 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -157,11 +157,11 @@ void nv20_gr_tile_prog(struct nvkm_engine *engine, int i) { struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; - struct nvkm_fifo *pfifo = nvkm_fifo(engine); + struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nv20_gr_priv *priv = (void *)engine; unsigned long flags; - pfifo->pause(pfifo, &flags); + fifo->pause(fifo, &flags); nv04_gr_idle(priv); nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); @@ -181,7 +181,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); } - pfifo->start(pfifo, &flags); + fifo->start(fifo, &flags); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index ed05c6d7875b..c0a1751a1e88 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -206,11 +206,11 @@ static void nv40_gr_tile_prog(struct nvkm_engine *engine, int i) { struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; - struct nvkm_fifo *pfifo = nvkm_fifo(engine); + struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nv40_gr_priv *priv = (void *)engine; unsigned long flags; - pfifo->pause(pfifo, &flags); + fifo->pause(fifo, &flags); nv04_gr_idle(priv); switch (nv_device(priv)->chipset) { @@ -277,13 +277,13 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) break; } - pfifo->start(pfifo, &flags); + fifo->start(fifo, &flags); } static void nv40_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle = NULL; @@ -301,7 +301,7 @@ nv40_gr_intr(struct nvkm_subdev *subdev) int chid; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat & NV_PGRAPH_INTR_ERROR) { if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index f18b75b883ac..e232cb8e2f9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -782,7 +782,7 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, static void nv50_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle = NULL; @@ -798,7 +798,7 @@ nv50_gr_intr(struct nvkm_subdev *subdev) int chid; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat & 0x00000010) { handle = nvkm_handle_get_class(engctx, class); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 891004157ea8..4199684a4b28 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -194,7 +194,7 @@ void nv31_mpeg_intr(struct nvkm_subdev *subdev) { struct nv31_mpeg_priv *priv = (void *)subdev; - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_handle *handle; struct nvkm_object *engctx; u32 stat = nv_rd32(priv, 0x00b100); @@ -227,7 +227,7 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev) if (show) { nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n", - pfifo->chid(pfifo, engctx), + fifo->chid(fifo, engctx), nvkm_client_name(engctx), stat, type, mthd, data); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index 4720ac884468..aeed7f850f65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -93,7 +93,7 @@ nv44_mpeg_cclass = { static void nv44_mpeg_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle; @@ -107,7 +107,7 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev) int chid; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat & 0x01000000) { /* happens on initial binding of the object */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index 9d5c1b8b1f8c..a598d6dbff46 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -75,7 +75,7 @@ static const struct nvkm_enum g98_sec_isr_error_name[] = { static void g98_sec_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *pfifo = nvkm_fifo(subdev); + struct nvkm_fifo *fifo = nvkm_fifo(subdev); struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct g98_sec_priv *priv = (void *)subdev; @@ -90,7 +90,7 @@ g98_sec_intr(struct nvkm_subdev *subdev) int chid; engctx = nvkm_engctx_get(engine, inst); - chid = pfifo->chid(pfifo, engctx); + chid = fifo->chid(fifo, engctx); if (stat & 0x00000040) { nv_error(priv, "DISPATCH_ERROR ["); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index 5dc637840a65..e17135a1ec83 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -297,7 +297,7 @@ calc_host(struct gt215_clk *clk, struct nvkm_cstate *cstate) int gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) { - struct nvkm_fifo *pfifo = nvkm_fifo(clk); + struct nvkm_fifo *fifo = nvkm_fifo(clk); /* halt and idle execution engines */ nv_mask(clk, 0x020060, 0x00070000, 0x00000000); @@ -306,8 +306,8 @@ gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) return -EBUSY; - if (pfifo) - pfifo->pause(pfifo, flags); + if (fifo) + fifo->pause(fifo, flags); if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) return -EIO; @@ -320,10 +320,10 @@ gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) void gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) { - struct nvkm_fifo *pfifo = nvkm_fifo(clk); + struct nvkm_fifo *fifo = nvkm_fifo(clk); - if (pfifo && flags) - pfifo->start(pfifo, flags); + if (fifo && flags) + fifo->start(fifo, flags); nv_mask(clk, 0x002504, 0x00000001, 0x00000000); nv_mask(clk, 0x020060, 0x00070000, 0x00040000); -- cgit v1.2.3 From bfee3f3d97db88bfb732735eb4955ad3381ac758 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:08 +1000 Subject: drm/nouveau/gr: cosmetic changes This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 35 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 214 ++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 42 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c | 26 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c | 60 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 104 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 42 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 90 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c | 90 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 60 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 928 +++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 162 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 150 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 164 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 170 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 26 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 192 ++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 478 +++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 222 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 114 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 264 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 440 +++++----- 30 files changed, 2092 insertions(+), 2095 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h index c772497cac3e..74bf2fe9a3ca 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -24,7 +24,7 @@ struct nvkm_gr_chan { #include struct nvkm_gr { - struct nvkm_engine base; + struct nvkm_engine engine; /* Returns chipset-specific counts of units packed into an u64. */ @@ -40,11 +40,11 @@ nvkm_gr(void *obj) #define nvkm_gr_create(p,e,c,y,d) \ nvkm_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d)) #define nvkm_gr_destroy(d) \ - nvkm_engine_destroy(&(d)->base) + nvkm_engine_destroy(&(d)->engine) #define nvkm_gr_init(d) \ - nvkm_engine_init(&(d)->base) + nvkm_engine_init(&(d)->engine) #define nvkm_gr_fini(d,s) \ - nvkm_engine_fini(&(d)->base, (s)) + nvkm_engine_fini(&(d)->engine, (s)) #define _nvkm_gr_dtor _nvkm_engine_dtor #define _nvkm_gr_init _nvkm_engine_init diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild index e91b4dfc0bf3..cbdab5a686af 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -1,20 +1,3 @@ -nvkm-y += nvkm/engine/gr/ctxnv40.o -nvkm-y += nvkm/engine/gr/ctxnv50.o -nvkm-y += nvkm/engine/gr/ctxgf100.o -nvkm-y += nvkm/engine/gr/ctxgf108.o -nvkm-y += nvkm/engine/gr/ctxgf104.o -nvkm-y += nvkm/engine/gr/ctxgf110.o -nvkm-y += nvkm/engine/gr/ctxgf117.o -nvkm-y += nvkm/engine/gr/ctxgf119.o -nvkm-y += nvkm/engine/gr/ctxgk104.o -nvkm-y += nvkm/engine/gr/ctxgk20a.o -nvkm-y += nvkm/engine/gr/ctxgk110.o -nvkm-y += nvkm/engine/gr/ctxgk110b.o -nvkm-y += nvkm/engine/gr/ctxgk208.o -nvkm-y += nvkm/engine/gr/ctxgm107.o -nvkm-y += nvkm/engine/gr/ctxgm204.o -nvkm-y += nvkm/engine/gr/ctxgm206.o -nvkm-y += nvkm/engine/gr/ctxgm20b.o nvkm-y += nvkm/engine/gr/nv04.o nvkm-y += nvkm/engine/gr/nv10.o nvkm-y += nvkm/engine/gr/nv20.o @@ -40,3 +23,21 @@ nvkm-y += nvkm/engine/gr/gm107.o nvkm-y += nvkm/engine/gr/gm204.o nvkm-y += nvkm/engine/gr/gm206.o nvkm-y += nvkm/engine/gr/gm20b.o + +nvkm-y += nvkm/engine/gr/ctxnv40.o +nvkm-y += nvkm/engine/gr/ctxnv50.o +nvkm-y += nvkm/engine/gr/ctxgf100.o +nvkm-y += nvkm/engine/gr/ctxgf108.o +nvkm-y += nvkm/engine/gr/ctxgf104.o +nvkm-y += nvkm/engine/gr/ctxgf110.o +nvkm-y += nvkm/engine/gr/ctxgf117.o +nvkm-y += nvkm/engine/gr/ctxgf119.o +nvkm-y += nvkm/engine/gr/ctxgk104.o +nvkm-y += nvkm/engine/gr/ctxgk20a.o +nvkm-y += nvkm/engine/gr/ctxgk110.o +nvkm-y += nvkm/engine/gr/ctxgk110b.o +nvkm-y += nvkm/engine/gr/ctxgk208.o +nvkm-y += nvkm/engine/gr/ctxgm107.o +nvkm-y += nvkm/engine/gr/ctxgm204.o +nvkm-y += nvkm/engine/gr/ctxgm206.o +nvkm-y += nvkm/engine/gr/ctxgm20b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 57e2c5b13123..22bc4dbd46df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1021,13 +1021,13 @@ gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data, return; } - nv_wr32(info->priv, addr, data); + nv_wr32(info->gr, addr, data); } void gf100_grctx_generate_bundle(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); @@ -1040,7 +1040,7 @@ gf100_grctx_generate_bundle(struct gf100_grctx *info) void gf100_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); @@ -1053,13 +1053,13 @@ gf100_grctx_generate_pagepool(struct gf100_grctx *info) void gf100_grctx_generate_attrib(struct gf100_grctx *info) { - struct gf100_gr_priv *priv = info->priv; - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv); + struct gf100_gr *gr = info->gr; + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr); const u32 attrib = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); int gpc, tpc; u32 bo = 0; @@ -1067,8 +1067,8 @@ gf100_grctx_generate_attrib(struct gf100_grctx *info) mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_wr32(info, 0x405830, (attrib << 16)); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { const u32 o = TPC_UNIT(gpc, tpc, 0x0520); mmio_skip(info, o, (attrib << 16) | ++bo); mmio_wr32(info, o, (attrib << 16) | --bo); @@ -1078,67 +1078,67 @@ gf100_grctx_generate_attrib(struct gf100_grctx *info) } void -gf100_grctx_generate_unkn(struct gf100_gr_priv *priv) +gf100_grctx_generate_unkn(struct gf100_gr *gr) { } void -gf100_grctx_generate_tpcid(struct gf100_gr_priv *priv) +gf100_grctx_generate_tpcid(struct gf100_gr *gr) { int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + if (tpc < gr->tpc_nr[gpc]) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x4e8), id); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id); id++; } - nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); } } } void -gf100_grctx_generate_r406028(struct gf100_gr_priv *priv) +gf100_grctx_generate_r406028(struct gf100_gr *gr) { u32 tmp[GPC_MAX / 8] = {}, i = 0; - for (i = 0; i < priv->gpc_nr; i++) - tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4); + for (i = 0; i < gr->gpc_nr; i++) + tmp[i / 8] |= gr->tpc_nr[i] << ((i % 8) * 4); for (i = 0; i < 4; i++) { - nv_wr32(priv, 0x406028 + (i * 4), tmp[i]); - nv_wr32(priv, 0x405870 + (i * 4), tmp[i]); + nv_wr32(gr, 0x406028 + (i * 4), tmp[i]); + nv_wr32(gr, 0x405870 + (i * 4), tmp[i]); } } void -gf100_grctx_generate_r4060a8(struct gf100_gr_priv *priv) +gf100_grctx_generate_r4060a8(struct gf100_gr *gr) { u8 tpcnr[GPC_MAX], data[TPC_MAX]; int gpc, tpc, i; - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); memset(data, 0x1f, sizeof(data)); gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { + for (tpc = 0; tpc < gr->tpc_total; tpc++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); tpcnr[gpc]--; data[tpc] = gpc; } for (i = 0; i < 4; i++) - nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); + nv_wr32(gr, 0x4060a8 + (i * 4), ((u32 *)data)[i]); } void -gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv) +gf100_grctx_generate_r418bb8(struct gf100_gr *gr) { u32 data[6] = {}, data2[2] = {}; u8 tpcnr[GPC_MAX]; @@ -1146,12 +1146,12 @@ gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv) int gpc, tpc, i; /* calculate first set of magics */ - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { + for (tpc = 0; tpc < gr->tpc_total; tpc++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); tpcnr[gpc]--; @@ -1163,7 +1163,7 @@ gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv) /* and the second... */ shift = 0; - ntpcv = priv->tpc_total; + ntpcv = gr->tpc_total; while (!(ntpcv & (1 << 4))) { ntpcv <<= 1; shift++; @@ -1176,95 +1176,95 @@ gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv) data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); /* GPC_BROADCAST */ - nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); + nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) | + gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(priv, 0x418b08 + (i * 4), data[i]); + nv_wr32(gr, 0x418b08 + (i * 4), data[i]); /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) | - priv->magic_not_rop_nr | data2[0]); - nv_wr32(priv, 0x419be4, data2[1]); + nv_wr32(gr, 0x419bd0, (gr->tpc_total << 8) | + gr->magic_not_rop_nr | data2[0]); + nv_wr32(gr, 0x419be4, data2[1]); for (i = 0; i < 6; i++) - nv_wr32(priv, 0x419b00 + (i * 4), data[i]); + nv_wr32(gr, 0x419b00 + (i * 4), data[i]); /* UNK78xx */ - nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); + nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) | + gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(priv, 0x40780c + (i * 4), data[i]); + nv_wr32(gr, 0x40780c + (i * 4), data[i]); } void -gf100_grctx_generate_r406800(struct gf100_gr_priv *priv) +gf100_grctx_generate_r406800(struct gf100_gr *gr) { u64 tpc_mask = 0, tpc_set = 0; u8 tpcnr[GPC_MAX]; int gpc, tpc; int i, a, b; - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) - tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8); + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) + tpc_mask |= ((1ULL << gr->tpc_nr[gpc]) - 1) << (gpc * 8); for (i = 0, gpc = -1, b = -1; i < 32; i++) { - a = (i * (priv->tpc_total - 1)) / 32; + a = (i * (gr->tpc_total - 1)) / 32; if (a != b) { b = a; do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; tpc_set |= 1ULL << ((gpc * 8) + tpc); } - nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); - nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); - if (priv->gpc_nr > 4) { - nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); - nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); + nv_wr32(gr, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); + nv_wr32(gr, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); + if (gr->gpc_nr > 4) { + nv_wr32(gr, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); + nv_wr32(gr, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); } } } void -gf100_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; - nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - gf100_gr_mmio(priv, oclass->hub); - gf100_gr_mmio(priv, oclass->gpc); - gf100_gr_mmio(priv, oclass->zcull); - gf100_gr_mmio(priv, oclass->tpc); - gf100_gr_mmio(priv, oclass->ppc); + gf100_gr_mmio(gr, oclass->hub); + gf100_gr_mmio(gr, oclass->gpc); + gf100_gr_mmio(gr, oclass->zcull); + gf100_gr_mmio(gr, oclass->tpc); + gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(priv, 0x404154, 0x00000000); + nv_wr32(gr, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); oclass->attrib(info); - oclass->unkn(priv); - - gf100_grctx_generate_tpcid(priv); - gf100_grctx_generate_r406028(priv); - gf100_grctx_generate_r4060a8(priv); - gf100_grctx_generate_r418bb8(priv); - gf100_grctx_generate_r406800(priv); - - gf100_gr_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - gf100_gr_mthd(priv, oclass->mthd); - nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); + oclass->unkn(gr); + + gf100_grctx_generate_tpcid(gr); + gf100_grctx_generate_r406028(gr); + gf100_grctx_generate_r4060a8(gr); + gf100_grctx_generate_r418bb8(gr); + gf100_grctx_generate_r406800(gr); + + gf100_gr_icmd(gr, oclass->icmd); + nv_wr32(gr, 0x404154, 0x00000400); + gf100_gr_mthd(gr, oclass->mthd); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); } int -gf100_grctx_generate(struct gf100_gr_priv *priv) +gf100_grctx_generate(struct gf100_gr *gr) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; - struct nvkm_bar *bar = nvkm_bar(priv); + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + struct nvkm_bar *bar = nvkm_bar(gr); struct nvkm_gpuobj *chan; struct gf100_grctx info; int ret, i; @@ -1272,10 +1272,10 @@ gf100_grctx_generate(struct gf100_gr_priv *priv) /* allocate memory to for a "channel", which we'll use to generate * the default context values */ - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); if (ret) { - nv_error(priv, "failed to allocate channel memory, %d\n", ret); + nv_error(gr, "failed to allocate channel memory, %d\n", ret); return ret; } @@ -1302,24 +1302,24 @@ gf100_grctx_generate(struct gf100_gr_priv *priv) bar->flush(bar); - nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); - nv_wr32(priv, 0x100cbc, 0x80000001); - nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); + nv_wr32(gr, 0x100cb8, (chan->addr + 0x1000) >> 8); + nv_wr32(gr, 0x100cbc, 0x80000001); + nv_wait(gr, 0x100c80, 0x00008000, 0x00008000); /* setup default state for mmio list construction */ - info.priv = priv; - info.data = priv->mmio_data; - info.mmio = priv->mmio_list; + info.gr = gr; + info.data = gr->mmio_data; + info.mmio = gr->mmio_list; info.addr = 0x2000 + (i * 8); info.buffer_nr = 0; /* make channel current */ - if (priv->firmware) { - nv_wr32(priv, 0x409840, 0x00000030); - nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(priv, 0x409504, 0x00000003); - if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) - nv_error(priv, "load_ctx timeout\n"); + if (gr->firmware) { + nv_wr32(gr, 0x409840, 0x00000030); + nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12); + nv_wr32(gr, 0x409504, 0x00000003); + if (!nv_wait(gr, 0x409800, 0x00000010, 0x00000010)) + nv_error(gr, "load_ctx timeout\n"); nv_wo32(chan, 0x8001c, 1); nv_wo32(chan, 0x80020, 0); @@ -1327,30 +1327,30 @@ gf100_grctx_generate(struct gf100_gr_priv *priv) nv_wo32(chan, 0x8002c, 0); bar->flush(bar); } else { - nv_wr32(priv, 0x409840, 0x80000000); - nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(priv, 0x409504, 0x00000001); - if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) - nv_error(priv, "HUB_SET_CHAN timeout\n"); + nv_wr32(gr, 0x409840, 0x80000000); + nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12); + nv_wr32(gr, 0x409504, 0x00000001); + if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) + nv_error(gr, "HUB_SET_CHAN timeout\n"); } - oclass->main(priv, &info); + oclass->main(gr, &info); /* trigger a context unload by unsetting the "next channel valid" bit * and faking a context switch interrupt */ - nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); - nv_wr32(priv, 0x409000, 0x00000100); - if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) { - nv_error(priv, "grctx template channel unload timeout\n"); + nv_mask(gr, 0x409b04, 0x80000000, 0x00000000); + nv_wr32(gr, 0x409000, 0x00000100); + if (!nv_wait(gr, 0x409b00, 0x80000000, 0x00000000)) { + nv_error(gr, "grctx template channel unload timeout\n"); ret = -EBUSY; goto done; } - priv->data = kmalloc(priv->size, GFP_KERNEL); - if (priv->data) { - for (i = 0; i < priv->size; i += 4) - priv->data[i / 4] = nv_ro32(chan, 0x80000 + i); + gr->data = kmalloc(gr->size, GFP_KERNEL); + if (gr->data) { + for (i = 0; i < gr->size; i += 4) + gr->data[i / 4] = nv_ro32(chan, 0x80000 + i); ret = 0; } else { ret = -ENOMEM; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index f89ab3706cf3..a555835b5789 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -3,7 +3,7 @@ #include "gf100.h" struct gf100_grctx { - struct gf100_gr_priv *priv; + struct gf100_gr *gr; struct gf100_gr_data *data; struct gf100_gr_mmio *mmio; int buffer_nr; @@ -22,9 +22,9 @@ void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int) struct gf100_grctx_oclass { struct nvkm_oclass base; /* main context generation function */ - void (*main)(struct gf100_gr_priv *, struct gf100_grctx *); + void (*main)(struct gf100_gr *, struct gf100_grctx *); /* context-specific modify-on-first-load list generation function */ - void (*unkn)(struct gf100_gr_priv *); + void (*unkn)(struct gf100_gr *); /* mmio context data */ const struct gf100_gr_pack *hub; const struct gf100_gr_pack *gpc; @@ -51,27 +51,27 @@ struct gf100_grctx_oclass { }; static inline const struct gf100_grctx_oclass * -gf100_grctx_impl(struct gf100_gr_priv *priv) +gf100_grctx_impl(struct gf100_gr *gr) { - return (void *)nv_engine(priv)->cclass; + return (void *)nv_engine(gr)->cclass; } extern struct nvkm_oclass *gf100_grctx_oclass; -int gf100_grctx_generate(struct gf100_gr_priv *); -void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *); +int gf100_grctx_generate(struct gf100_gr *); +void gf100_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); void gf100_grctx_generate_bundle(struct gf100_grctx *); void gf100_grctx_generate_pagepool(struct gf100_grctx *); void gf100_grctx_generate_attrib(struct gf100_grctx *); -void gf100_grctx_generate_unkn(struct gf100_gr_priv *); -void gf100_grctx_generate_tpcid(struct gf100_gr_priv *); -void gf100_grctx_generate_r406028(struct gf100_gr_priv *); -void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *); -void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *); -void gf100_grctx_generate_r406800(struct gf100_gr_priv *); +void gf100_grctx_generate_unkn(struct gf100_gr *); +void gf100_grctx_generate_tpcid(struct gf100_gr *); +void gf100_grctx_generate_r406028(struct gf100_gr *); +void gf100_grctx_generate_r4060a8(struct gf100_gr *); +void gf100_grctx_generate_r418bb8(struct gf100_gr *); +void gf100_grctx_generate_r406800(struct gf100_gr *); extern struct nvkm_oclass *gf108_grctx_oclass; void gf108_grctx_generate_attrib(struct gf100_grctx *); -void gf108_grctx_generate_unkn(struct gf100_gr_priv *); +void gf108_grctx_generate_unkn(struct gf100_gr *); extern struct nvkm_oclass *gf104_grctx_oclass; extern struct nvkm_oclass *gf110_grctx_oclass; @@ -83,12 +83,12 @@ extern struct nvkm_oclass *gf119_grctx_oclass; extern struct nvkm_oclass *gk104_grctx_oclass; extern struct nvkm_oclass *gk20a_grctx_oclass; -void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *); +void gk104_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); void gk104_grctx_generate_bundle(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *); -void gk104_grctx_generate_unkn(struct gf100_gr_priv *); -void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *); -void gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *); +void gk104_grctx_generate_unkn(struct gf100_gr *); +void gk104_grctx_generate_r418bb8(struct gf100_gr *); +void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *); void gm107_grctx_generate_bundle(struct gf100_grctx *); @@ -105,9 +105,9 @@ void gm107_grctx_generate_pagepool(struct gf100_grctx *); void gm107_grctx_generate_attrib(struct gf100_grctx *); extern struct nvkm_oclass *gm204_grctx_oclass; -void gm204_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *); -void gm204_grctx_generate_tpcid(struct gf100_gr_priv *); -void gm204_grctx_generate_405b60(struct gf100_gr_priv *); +void gm204_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); +void gm204_grctx_generate_tpcid(struct gf100_gr *); +void gm204_grctx_generate_405b60(struct gf100_gr *); extern struct nvkm_oclass *gm206_grctx_oclass; extern struct nvkm_oclass *gm20b_grctx_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c index 87c844a5f34b..d810a0b97b76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c @@ -730,18 +730,18 @@ gf108_grctx_pack_tpc[] = { void gf108_grctx_generate_attrib(struct gf100_grctx *info) { - struct gf100_gr_priv *priv = info->priv; - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv); + struct gf100_gr *gr = info->gr; + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr); const u32 alpha = impl->alpha_nr; const u32 beta = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); const int timeslice_mode = 1; const int max_batches = 0xffff; u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; + u32 ao = bo + impl->attrib_nr_max * gr->tpc_total; int gpc, tpc; mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -749,8 +749,8 @@ gf108_grctx_generate_attrib(struct gf100_grctx *info) mmio_wr32(info, 0x405830, (beta << 16) | alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { const u32 a = alpha; const u32 b = beta; const u32 t = timeslice_mode; @@ -765,14 +765,14 @@ gf108_grctx_generate_attrib(struct gf100_grctx *info) } void -gf108_grctx_generate_unkn(struct gf100_gr_priv *priv) +gf108_grctx_generate_unkn(struct gf100_gr *gr) { - nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); - nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); - nv_mask(priv, 0x419814, 0x00000004, 0x00000004); - nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); - nv_mask(priv, 0x405800, 0x08000000, 0x08000000); - nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); + nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(gr, 0x41980c, 0x00000010, 0x00000010); + nv_mask(gr, 0x419814, 0x00000004, 0x00000004); + nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(gr, 0x405800, 0x08000000, 0x08000000); + nv_mask(gr, 0x419c00, 0x00000008, 0x00000008); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c index 9bbe2c97552e..7970b9d4b908 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c @@ -182,18 +182,18 @@ gf117_grctx_pack_ppc[] = { void gf117_grctx_generate_attrib(struct gf100_grctx *info) { - struct gf100_gr_priv *priv = info->priv; - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv); + struct gf100_gr *gr = info->gr; + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr); const u32 alpha = impl->alpha_nr; const u32 beta = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); const int timeslice_mode = 1; const int max_batches = 0xffff; u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; + u32 ao = bo + impl->attrib_nr_max * gr->tpc_total; int gpc, ppc; mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -201,55 +201,55 @@ gf117_grctx_generate_attrib(struct gf100_grctx *info) mmio_wr32(info, 0x405830, (beta << 16) | alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) { - const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc]; - const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc]; + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { + const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; + const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; const u32 t = timeslice_mode; const u32 o = PPC_UNIT(gpc, ppc, 0); mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); - bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, (a << 16) | ao); - ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; } } } void -gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int i; - nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - gf100_gr_mmio(priv, oclass->hub); - gf100_gr_mmio(priv, oclass->gpc); - gf100_gr_mmio(priv, oclass->zcull); - gf100_gr_mmio(priv, oclass->tpc); - gf100_gr_mmio(priv, oclass->ppc); + gf100_gr_mmio(gr, oclass->hub); + gf100_gr_mmio(gr, oclass->gpc); + gf100_gr_mmio(gr, oclass->zcull); + gf100_gr_mmio(gr, oclass->tpc); + gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(priv, 0x404154, 0x00000000); + nv_wr32(gr, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); oclass->attrib(info); - oclass->unkn(priv); + oclass->unkn(gr); - gf100_grctx_generate_tpcid(priv); - gf100_grctx_generate_r406028(priv); - gf100_grctx_generate_r4060a8(priv); - gk104_grctx_generate_r418bb8(priv); - gf100_grctx_generate_r406800(priv); + gf100_grctx_generate_tpcid(gr); + gf100_grctx_generate_r406028(gr); + gf100_grctx_generate_r4060a8(gr); + gk104_grctx_generate_r418bb8(gr); + gf100_grctx_generate_r406800(gr); for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); - gf100_gr_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - gf100_gr_mthd(priv, oclass->mthd); - nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); + gf100_gr_icmd(gr, oclass->icmd); + nv_wr32(gr, 0x404154, 0x00000400); + gf100_gr_mthd(gr, oclass->mthd); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index b12f6a9fd926..7b2a96c6e496 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -843,7 +843,7 @@ gk104_grctx_pack_ppc[] = { void gk104_grctx_generate_bundle(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, impl->bundle_size / 0x20); const u32 token_limit = impl->bundle_token_limit; @@ -860,7 +860,7 @@ gk104_grctx_generate_bundle(struct gf100_grctx *info) void gk104_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); @@ -872,18 +872,18 @@ gk104_grctx_generate_pagepool(struct gf100_grctx *info) } void -gk104_grctx_generate_unkn(struct gf100_gr_priv *priv) +gk104_grctx_generate_unkn(struct gf100_gr *gr) { - nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); - nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); - nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); - nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); - nv_mask(priv, 0x405800, 0x08000000, 0x08000000); - nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); + nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001); + nv_mask(gr, 0x41980c, 0x00000010, 0x00000010); + nv_mask(gr, 0x41be08, 0x00000004, 0x00000004); + nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000); + nv_mask(gr, 0x405800, 0x08000000, 0x08000000); + nv_mask(gr, 0x419c00, 0x00000008, 0x00000008); } void -gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv) +gk104_grctx_generate_r418bb8(struct gf100_gr *gr) { u32 data[6] = {}, data2[2] = {}; u8 tpcnr[GPC_MAX]; @@ -891,12 +891,12 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv) int gpc, tpc, i; /* calculate first set of magics */ - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); gpc = -1; - for (tpc = 0; tpc < priv->tpc_total; tpc++) { + for (tpc = 0; tpc < gr->tpc_total; tpc++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); tpcnr[gpc]--; @@ -908,7 +908,7 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv) /* and the second... */ shift = 0; - ntpcv = priv->tpc_total; + ntpcv = gr->tpc_total; while (!(ntpcv & (1 << 4))) { ntpcv <<= 1; shift++; @@ -921,73 +921,73 @@ gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv) data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); /* GPC_BROADCAST */ - nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); + nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) | + gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(priv, 0x418b08 + (i * 4), data[i]); + nv_wr32(gr, 0x418b08 + (i * 4), data[i]); /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) | - priv->magic_not_rop_nr | data2[0]); - nv_wr32(priv, 0x41bfe4, data2[1]); + nv_wr32(gr, 0x41bfd0, (gr->tpc_total << 8) | + gr->magic_not_rop_nr | data2[0]); + nv_wr32(gr, 0x41bfe4, data2[1]); for (i = 0; i < 6; i++) - nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); + nv_wr32(gr, 0x41bf00 + (i * 4), data[i]); /* UNK78xx */ - nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | - priv->magic_not_rop_nr); + nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) | + gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(priv, 0x40780c + (i * 4), data[i]); + nv_wr32(gr, 0x40780c + (i * 4), data[i]); } void -gk104_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv) +gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr) { - const u32 fbp_count = nv_rd32(priv, 0x120074); - nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */ - nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */ + const u32 fbp_count = nv_rd32(gr, 0x120074); + nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */ + nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */ } void -gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int i; - nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - gf100_gr_mmio(priv, oclass->hub); - gf100_gr_mmio(priv, oclass->gpc); - gf100_gr_mmio(priv, oclass->zcull); - gf100_gr_mmio(priv, oclass->tpc); - gf100_gr_mmio(priv, oclass->ppc); + gf100_gr_mmio(gr, oclass->hub); + gf100_gr_mmio(gr, oclass->gpc); + gf100_gr_mmio(gr, oclass->zcull); + gf100_gr_mmio(gr, oclass->tpc); + gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(priv, 0x404154, 0x00000000); + nv_wr32(gr, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); oclass->attrib(info); - oclass->unkn(priv); + oclass->unkn(gr); - gf100_grctx_generate_tpcid(priv); - gf100_grctx_generate_r406028(priv); - gk104_grctx_generate_r418bb8(priv); - gf100_grctx_generate_r406800(priv); + gf100_grctx_generate_tpcid(gr); + gf100_grctx_generate_r406028(gr); + gk104_grctx_generate_r418bb8(gr); + gf100_grctx_generate_r406800(gr); for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); - gk104_grctx_generate_rop_active_fbps(priv); - nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); + nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); + gk104_grctx_generate_rop_active_fbps(gr); + nv_mask(gr, 0x419f78, 0x00000001, 0x00000000); - gf100_gr_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - gf100_gr_mthd(priv, oclass->mthd); - nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); + gf100_gr_icmd(gr, oclass->icmd); + nv_wr32(gr, 0x404154, 0x00000400); + gf100_gr_mthd(gr, oclass->mthd); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); - nv_mask(priv, 0x418800, 0x00200000, 0x00200000); - nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); + nv_mask(gr, 0x418800, 0x00200000, 0x00200000); + nv_mask(gr, 0x41be10, 0x00800000, 0x00800000); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 3fe080e31a86..91e4aacfdec7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -26,46 +26,46 @@ #include static void -gk20a_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int idle_timeout_save; int i; - gf100_gr_mmio(priv, priv->fuc_sw_ctx); + gf100_gr_mmio(gr, gr->fuc_sw_ctx); - gf100_gr_wait_idle(priv); + gf100_gr_wait_idle(gr); - idle_timeout_save = nv_rd32(priv, 0x404154); - nv_wr32(priv, 0x404154, 0x00000000); + idle_timeout_save = nv_rd32(gr, 0x404154); + nv_wr32(gr, 0x404154, 0x00000000); oclass->attrib(info); - oclass->unkn(priv); + oclass->unkn(gr); - gf100_grctx_generate_tpcid(priv); - gf100_grctx_generate_r406028(priv); - gk104_grctx_generate_r418bb8(priv); - gf100_grctx_generate_r406800(priv); + gf100_grctx_generate_tpcid(gr); + gf100_grctx_generate_r406028(gr); + gk104_grctx_generate_r418bb8(gr); + gf100_grctx_generate_r406800(gr); for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(priv); + gk104_grctx_generate_rop_active_fbps(gr); - nv_mask(priv, 0x5044b0, 0x8000000, 0x8000000); + nv_mask(gr, 0x5044b0, 0x8000000, 0x8000000); - gf100_gr_wait_idle(priv); + gf100_gr_wait_idle(gr); - nv_wr32(priv, 0x404154, idle_timeout_save); - gf100_gr_wait_idle(priv); + nv_wr32(gr, 0x404154, idle_timeout_save); + gf100_gr_wait_idle(gr); - gf100_gr_mthd(priv, priv->fuc_method); - gf100_gr_wait_idle(priv); + gf100_gr_mthd(gr, gr->fuc_method); + gf100_gr_wait_idle(gr); - gf100_gr_icmd(priv, priv->fuc_bundle); + gf100_gr_icmd(gr, gr->fuc_bundle); oclass->pagepool(info); oclass->bundle(info); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 6bf2fd1a05ba..0d908a123170 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -863,7 +863,7 @@ gm107_grctx_pack_ppc[] = { void gm107_grctx_generate_bundle(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, impl->bundle_size / 0x20); const u32 token_limit = impl->bundle_token_limit; @@ -880,7 +880,7 @@ gm107_grctx_generate_bundle(struct gf100_grctx *info) void gm107_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv); + const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); @@ -895,17 +895,17 @@ gm107_grctx_generate_pagepool(struct gf100_grctx *info) void gm107_grctx_generate_attrib(struct gf100_grctx *info) { - struct gf100_gr_priv *priv = info->priv; - const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(priv); + struct gf100_gr *gr = info->gr; + const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(gr); const u32 alpha = impl->alpha_nr; const u32 attrib = impl->attrib_nr; const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; - const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); + const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); const int max_batches = 0xffff; u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; + u32 ao = bo + impl->attrib_nr_max * gr->tpc_total; int gpc, ppc, n = 0; mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -914,84 +914,84 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info) mmio_wr32(info, 0x405830, (attrib << 16) | alpha); mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) { - const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc]; - const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc]; + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { + const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; + const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 u = 0x418ea0 + (n * 0x04); const u32 o = PPC_UNIT(gpc, ppc, 0); mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, o + 0xf4, bo); - bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); - ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; + ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, u, ((bs / 3 /*XXX*/) << 16) | bs); } } } void -gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv) +gm107_grctx_generate_tpcid(struct gf100_gr *gr) { int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + if (tpc < gr->tpc_nr[gpc]) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id); id++; } - nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); } } } static void -gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int i; - gf100_gr_mmio(priv, oclass->hub); - gf100_gr_mmio(priv, oclass->gpc); - gf100_gr_mmio(priv, oclass->zcull); - gf100_gr_mmio(priv, oclass->tpc); - gf100_gr_mmio(priv, oclass->ppc); + gf100_gr_mmio(gr, oclass->hub); + gf100_gr_mmio(gr, oclass->gpc); + gf100_gr_mmio(gr, oclass->zcull); + gf100_gr_mmio(gr, oclass->tpc); + gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(priv, 0x404154, 0x00000000); + nv_wr32(gr, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); oclass->attrib(info); - oclass->unkn(priv); + oclass->unkn(gr); - gm107_grctx_generate_tpcid(priv); - gf100_grctx_generate_r406028(priv); - gk104_grctx_generate_r418bb8(priv); - gf100_grctx_generate_r406800(priv); + gm107_grctx_generate_tpcid(gr); + gf100_grctx_generate_r406028(gr); + gk104_grctx_generate_r418bb8(gr); + gf100_grctx_generate_r406800(gr); - nv_wr32(priv, 0x4064d0, 0x00000001); + nv_wr32(gr, 0x4064d0, 0x00000001); for (i = 1; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(priv, 0x406500, 0x00000001); + nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(gr, 0x406500, 0x00000001); - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(priv); + gk104_grctx_generate_rop_active_fbps(gr); - gf100_gr_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000400); - gf100_gr_mthd(priv, oclass->mthd); + gf100_gr_icmd(gr, oclass->icmd); + nv_wr32(gr, 0x404154, 0x00000400); + gf100_gr_mthd(gr, oclass->mthd); - nv_mask(priv, 0x419e00, 0x00808080, 0x00808080); - nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000); - nv_mask(priv, 0x419f80, 0x80000000, 0x80000000); - nv_mask(priv, 0x419f88, 0x80000000, 0x80000000); + nv_mask(gr, 0x419e00, 0x00808080, 0x00808080); + nv_mask(gr, 0x419ccc, 0x80000000, 0x80000000); + nv_mask(gr, 0x419f80, 0x80000000, 0x80000000); + nv_mask(gr, 0x419f88, 0x80000000, 0x80000000); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c index efc76bfae896..93f38bdfd0cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c @@ -919,16 +919,16 @@ gm204_grctx_pack_ppc[] = { ******************************************************************************/ void -gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv) +gm204_grctx_generate_tpcid(struct gf100_gr *gr) { int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - if (tpc < priv->tpc_nr[gpc]) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + if (tpc < gr->tpc_nr[gpc]) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id); + nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id); id++; } } @@ -936,88 +936,88 @@ gm204_grctx_generate_tpcid(struct gf100_gr_priv *priv) } static void -gm204_grctx_generate_rop_active_fbps(struct gf100_gr_priv *priv) +gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr) { - const u32 fbp_count = nv_rd32(priv, 0x12006c); - nv_mask(priv, 0x408850, 0x0000000f, fbp_count); /* zrop */ - nv_mask(priv, 0x408958, 0x0000000f, fbp_count); /* crop */ + const u32 fbp_count = nv_rd32(gr, 0x12006c); + nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */ + nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */ } void -gm204_grctx_generate_405b60(struct gf100_gr_priv *priv) +gm204_grctx_generate_405b60(struct gf100_gr *gr) { - const u32 dist_nr = DIV_ROUND_UP(priv->tpc_total, 4); - u32 dist[TPC_MAX] = {}; + const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); + u32 dist[TPC_MAX / 4] = {}; u32 gpcs[GPC_MAX] = {}; u8 tpcnr[GPC_MAX]; int tpc, gpc, i; - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); /* won't result in the same distribution as the binary driver where * some of the gpcs have more tpcs than others, but this shall do * for the moment. the code for earlier gpus has this issue too. */ - for (gpc = -1, i = 0; i < priv->tpc_total; i++) { + for (gpc = -1, i = 0; i < gr->tpc_total; i++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while(!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; dist[i / 4] |= ((gpc << 4) | tpc) << ((i % 4) * 8); gpcs[gpc] |= i << (tpc * 8); } for (i = 0; i < dist_nr; i++) - nv_wr32(priv, 0x405b60 + (i * 4), dist[i]); - for (i = 0; i < priv->gpc_nr; i++) - nv_wr32(priv, 0x405ba0 + (i * 4), gpcs[i]); + nv_wr32(gr, 0x405b60 + (i * 4), dist[i]); + for (i = 0; i < gr->gpc_nr; i++) + nv_wr32(gr, 0x405ba0 + (i * 4), gpcs[i]); } void -gm204_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; u32 tmp; int i; - gf100_gr_mmio(priv, oclass->hub); - gf100_gr_mmio(priv, oclass->gpc); - gf100_gr_mmio(priv, oclass->zcull); - gf100_gr_mmio(priv, oclass->tpc); - gf100_gr_mmio(priv, oclass->ppc); + gf100_gr_mmio(gr, oclass->hub); + gf100_gr_mmio(gr, oclass->gpc); + gf100_gr_mmio(gr, oclass->zcull); + gf100_gr_mmio(gr, oclass->tpc); + gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(priv, 0x404154, 0x00000000); + nv_wr32(gr, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); oclass->attrib(info); - oclass->unkn(priv); + oclass->unkn(gr); - gm204_grctx_generate_tpcid(priv); - gf100_grctx_generate_r406028(priv); - gk104_grctx_generate_r418bb8(priv); + gm204_grctx_generate_tpcid(gr); + gf100_grctx_generate_r406028(gr); + gk104_grctx_generate_r418bb8(gr); for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(priv, 0x406500, 0x00000000); + nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(gr, 0x406500, 0x00000000); - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gm204_grctx_generate_rop_active_fbps(priv); + gm204_grctx_generate_rop_active_fbps(gr); - for (tmp = 0, i = 0; i < priv->gpc_nr; i++) - tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4); - nv_wr32(priv, 0x4041c4, tmp); + for (tmp = 0, i = 0; i < gr->gpc_nr; i++) + tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); + nv_wr32(gr, 0x4041c4, tmp); - gm204_grctx_generate_405b60(priv); + gm204_grctx_generate_405b60(gr); - gf100_gr_icmd(priv, oclass->icmd); - nv_wr32(priv, 0x404154, 0x00000800); - gf100_gr_mthd(priv, oclass->mthd); + gf100_gr_icmd(gr, oclass->icmd); + nv_wr32(gr, 0x404154, 0x00000800); + gf100_gr_mthd(gr, oclass->mthd); - nv_mask(priv, 0x418e94, 0xffffffff, 0xc4230000); - nv_mask(priv, 0x418e4c, 0xffffffff, 0x70000000); + nv_mask(gr, 0x418e94, 0xffffffff, 0xc4230000); + nv_mask(gr, 0x418e4c, 0xffffffff, 0x70000000); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c index c011bf327276..c44b2e157ec2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c @@ -22,63 +22,63 @@ #include "ctxgf100.h" static void -gm20b_grctx_generate_r406028(struct gf100_gr_priv *priv) +gm20b_grctx_generate_r406028(struct gf100_gr *gr) { u32 tpc_per_gpc = 0; int i; - for (i = 0; i < priv->gpc_nr; i++) - tpc_per_gpc |= priv->tpc_nr[i] << (4 * i); + for (i = 0; i < gr->gpc_nr; i++) + tpc_per_gpc |= gr->tpc_nr[i] << (4 * i); - nv_wr32(priv, 0x406028, tpc_per_gpc); - nv_wr32(priv, 0x405870, tpc_per_gpc); + nv_wr32(gr, 0x406028, tpc_per_gpc); + nv_wr32(gr, 0x405870, tpc_per_gpc); } static void -gm20b_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info) +gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; + struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int idle_timeout_save; int i, tmp; - gf100_gr_mmio(priv, priv->fuc_sw_ctx); + gf100_gr_mmio(gr, gr->fuc_sw_ctx); - gf100_gr_wait_idle(priv); + gf100_gr_wait_idle(gr); - idle_timeout_save = nv_rd32(priv, 0x404154); - nv_wr32(priv, 0x404154, 0x00000000); + idle_timeout_save = nv_rd32(gr, 0x404154); + nv_wr32(gr, 0x404154, 0x00000000); oclass->attrib(info); - oclass->unkn(priv); + oclass->unkn(gr); - gm204_grctx_generate_tpcid(priv); - gm20b_grctx_generate_r406028(priv); - gk104_grctx_generate_r418bb8(priv); + gm204_grctx_generate_tpcid(gr); + gm20b_grctx_generate_r406028(gr); + gk104_grctx_generate_r418bb8(gr); for (i = 0; i < 8; i++) - nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); + nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); + nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); - gk104_grctx_generate_rop_active_fbps(priv); - nv_wr32(priv, 0x408908, nv_rd32(priv, 0x410108) | 0x80000000); + gk104_grctx_generate_rop_active_fbps(gr); + nv_wr32(gr, 0x408908, nv_rd32(gr, 0x410108) | 0x80000000); - for (tmp = 0, i = 0; i < priv->gpc_nr; i++) - tmp |= ((1 << priv->tpc_nr[i]) - 1) << (i * 4); - nv_wr32(priv, 0x4041c4, tmp); + for (tmp = 0, i = 0; i < gr->gpc_nr; i++) + tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); + nv_wr32(gr, 0x4041c4, tmp); - gm204_grctx_generate_405b60(priv); + gm204_grctx_generate_405b60(gr); - gf100_gr_wait_idle(priv); + gf100_gr_wait_idle(gr); - nv_wr32(priv, 0x404154, idle_timeout_save); - gf100_gr_wait_idle(priv); + nv_wr32(gr, 0x404154, idle_timeout_save); + gf100_gr_wait_idle(gr); - gf100_gr_mthd(priv, priv->fuc_method); - gf100_gr_wait_idle(priv); + gf100_gr_mthd(gr, gr->fuc_method); + gf100_gr_wait_idle(gr); - gf100_gr_icmd(priv, priv->fuc_bundle); + gf100_gr_icmd(gr, gr->fuc_bundle); oclass->pagepool(info); oclass->bundle(info); } @@ -107,4 +107,4 @@ gm20b_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x400, .alpha_nr_max = 0xc00, .alpha_nr = 0x800, -}.base; \ No newline at end of file +}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index b0b5fadfc550..c1b84a687f76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -41,35 +41,35 @@ ******************************************************************************/ static void -gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc) +gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) { - if (priv->zbc_color[zbc].format) { - nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); - nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); - nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); - nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); - } - nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); - nv_wr32(priv, 0x405820, zbc); - nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ + if (gr->zbc_color[zbc].format) { + nv_wr32(gr, 0x405804, gr->zbc_color[zbc].ds[0]); + nv_wr32(gr, 0x405808, gr->zbc_color[zbc].ds[1]); + nv_wr32(gr, 0x40580c, gr->zbc_color[zbc].ds[2]); + nv_wr32(gr, 0x405810, gr->zbc_color[zbc].ds[3]); + } + nv_wr32(gr, 0x405814, gr->zbc_color[zbc].format); + nv_wr32(gr, 0x405820, zbc); + nv_wr32(gr, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ } static int -gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format, +gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, const u32 ds[4], const u32 l2[4]) { - struct nvkm_ltc *ltc = nvkm_ltc(priv); + struct nvkm_ltc *ltc = nvkm_ltc(gr); int zbc = -ENOSPC, i; for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { - if (priv->zbc_color[i].format) { - if (priv->zbc_color[i].format != format) + if (gr->zbc_color[i].format) { + if (gr->zbc_color[i].format != format) continue; - if (memcmp(priv->zbc_color[i].ds, ds, sizeof( - priv->zbc_color[i].ds))) + if (memcmp(gr->zbc_color[i].ds, ds, sizeof( + gr->zbc_color[i].ds))) continue; - if (memcmp(priv->zbc_color[i].l2, l2, sizeof( - priv->zbc_color[i].l2))) { + if (memcmp(gr->zbc_color[i].l2, l2, sizeof( + gr->zbc_color[i].l2))) { WARN_ON(1); return -EINVAL; } @@ -82,38 +82,38 @@ gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format, if (zbc < 0) return zbc; - memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); - memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); - priv->zbc_color[zbc].format = format; + memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); + memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); + gr->zbc_color[zbc].format = format; ltc->zbc_color_get(ltc, zbc, l2); - gf100_gr_zbc_clear_color(priv, zbc); + gf100_gr_zbc_clear_color(gr, zbc); return zbc; } static void -gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc) +gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) { - if (priv->zbc_depth[zbc].format) - nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); - nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); - nv_wr32(priv, 0x405820, zbc); - nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ + if (gr->zbc_depth[zbc].format) + nv_wr32(gr, 0x405818, gr->zbc_depth[zbc].ds); + nv_wr32(gr, 0x40581c, gr->zbc_depth[zbc].format); + nv_wr32(gr, 0x405820, zbc); + nv_wr32(gr, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ } static int -gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, +gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, const u32 ds, const u32 l2) { - struct nvkm_ltc *ltc = nvkm_ltc(priv); + struct nvkm_ltc *ltc = nvkm_ltc(gr); int zbc = -ENOSPC, i; for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { - if (priv->zbc_depth[i].format) { - if (priv->zbc_depth[i].format != format) + if (gr->zbc_depth[i].format) { + if (gr->zbc_depth[i].format != format) continue; - if (priv->zbc_depth[i].ds != ds) + if (gr->zbc_depth[i].ds != ds) continue; - if (priv->zbc_depth[i].l2 != l2) { + if (gr->zbc_depth[i].l2 != l2) { WARN_ON(1); return -EINVAL; } @@ -126,11 +126,11 @@ gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, if (zbc < 0) return zbc; - priv->zbc_depth[zbc].format = format; - priv->zbc_depth[zbc].ds = ds; - priv->zbc_depth[zbc].l2 = l2; + gr->zbc_depth[zbc].format = format; + gr->zbc_depth[zbc].ds = ds; + gr->zbc_depth[zbc].l2 = l2; ltc->zbc_depth_get(ltc, zbc, l2); - gf100_gr_zbc_clear_depth(priv, zbc); + gf100_gr_zbc_clear_depth(gr, zbc); return zbc; } @@ -141,7 +141,7 @@ gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format, static int gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) { - struct gf100_gr_priv *priv = (void *)object->engine; + struct gf100_gr *gr = (void *)object->engine; union { struct fermi_a_zbc_color_v0 v0; } *args = data; @@ -168,7 +168,7 @@ gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: - ret = gf100_gr_zbc_color_get(priv, args->v0.format, + ret = gf100_gr_zbc_color_get(gr, args->v0.format, args->v0.ds, args->v0.l2); if (ret >= 0) { @@ -187,7 +187,7 @@ gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size) static int gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) { - struct gf100_gr_priv *priv = (void *)object->engine; + struct gf100_gr *gr = (void *)object->engine; union { struct fermi_a_zbc_depth_v0 v0; } *args = data; @@ -196,7 +196,7 @@ gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size) if (nvif_unpack(args->v0, 0, 0, false)) { switch (args->v0.format) { case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: - ret = gf100_gr_zbc_depth_get(priv, args->v0.format, + ret = gf100_gr_zbc_depth_get(gr, args->v0.format, args->v0.ds, args->v0.l2); return (ret >= 0) ? 0 : -ENOSPC; @@ -235,11 +235,11 @@ static int gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, void *pdata, u32 size) { - struct gf100_gr_priv *priv = (void *)object->engine; + struct gf100_gr *gr = (void *)object->engine; if (size >= sizeof(u32)) { u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; - nv_wr32(priv, 0x419e44, data); - nv_wr32(priv, 0x419e4c, data); + nv_wr32(gr, 0x419e44, data); + nv_wr32(gr, 0x419e4c, data); return 0; } return -EINVAL; @@ -276,15 +276,15 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_vm *vm = nvkm_client(parent)->vm; - struct gf100_gr_priv *priv = (void *)engine; - struct gf100_gr_data *data = priv->mmio_data; - struct gf100_gr_mmio *mmio = priv->mmio_list; + struct gf100_gr *gr = (void *)engine; + struct gf100_gr_data *data = gr->mmio_data; + struct gf100_gr_mmio *mmio = gr->mmio_list; struct gf100_gr_chan *chan; int ret, i; /* allocate memory for context, and fill with default values */ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, - priv->size, 0x100, + gr->size, 0x100, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) @@ -306,7 +306,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; /* allocate buffers referenced by mmio list */ - for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { + for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, data->align, 0, &chan->data[i].mem); if (ret) @@ -321,7 +321,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } /* finally, fill in the mmio list and point the context at it */ - for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { + for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { u32 addr = mmio->addr; u32 data = mmio->data; @@ -335,10 +335,10 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, mmio++; } - for (i = 0; i < priv->size; i += 4) - nv_wo32(chan, i, priv->data[i / 4]); + for (i = 0; i < gr->size; i += 4) + nv_wo32(chan, i, gr->data[i / 4]); - if (!priv->firmware) { + if (!gr->firmware) { nv_wo32(chan, 0x00, chan->mmio_nr / 2); nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); } else { @@ -634,7 +634,7 @@ gf100_gr_pack_mmio[] = { ******************************************************************************/ void -gf100_gr_zbc_init(struct gf100_gr_priv *priv) +gf100_gr_zbc_init(struct gf100_gr *gr) { const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; @@ -644,22 +644,22 @@ gf100_gr_zbc_init(struct gf100_gr_priv *priv) 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; - struct nvkm_ltc *ltc = nvkm_ltc(priv); + struct nvkm_ltc *ltc = nvkm_ltc(gr); int index; - if (!priv->zbc_color[0].format) { - gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]); - gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]); - gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); - gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); - gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); - gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); + if (!gr->zbc_color[0].format) { + gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); + gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); + gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); + gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); + gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); + gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); } for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) - gf100_gr_zbc_clear_color(priv, index); + gf100_gr_zbc_clear_color(gr, index); for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) - gf100_gr_zbc_clear_depth(priv, index); + gf100_gr_zbc_clear_depth(gr, index); } /** @@ -668,7 +668,7 @@ gf100_gr_zbc_init(struct gf100_gr_priv *priv) * progress. */ int -gf100_gr_wait_idle(struct gf100_gr_priv *priv) +gf100_gr_wait_idle(struct gf100_gr *gr) { unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); bool gr_enabled, ctxsw_active, gr_busy; @@ -678,23 +678,23 @@ gf100_gr_wait_idle(struct gf100_gr_priv *priv) * required to make sure FIFO_ENGINE_STATUS (0x2640) is * up-to-date */ - nv_rd32(priv, 0x400700); + nv_rd32(gr, 0x400700); - gr_enabled = nv_rd32(priv, 0x200) & 0x1000; - ctxsw_active = nv_rd32(priv, 0x2640) & 0x8000; - gr_busy = nv_rd32(priv, 0x40060c) & 0x1; + gr_enabled = nv_rd32(gr, 0x200) & 0x1000; + ctxsw_active = nv_rd32(gr, 0x2640) & 0x8000; + gr_busy = nv_rd32(gr, 0x40060c) & 0x1; if (!gr_enabled || (!gr_busy && !ctxsw_active)) return 0; } while (time_before(jiffies, end_jiffies)); - nv_error(priv, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", + nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", gr_enabled, ctxsw_active, gr_busy); return -EAGAIN; } void -gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) +gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) { const struct gf100_gr_pack *pack; const struct gf100_gr_init *init; @@ -703,48 +703,48 @@ gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) u32 next = init->addr + init->count * init->pitch; u32 addr = init->addr; while (addr < next) { - nv_wr32(priv, addr, init->data); + nv_wr32(gr, addr, init->data); addr += init->pitch; } } } void -gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) +gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) { const struct gf100_gr_pack *pack; const struct gf100_gr_init *init; u32 data = 0; - nv_wr32(priv, 0x400208, 0x80000000); + nv_wr32(gr, 0x400208, 0x80000000); pack_for_each_init(init, pack, p) { u32 next = init->addr + init->count * init->pitch; u32 addr = init->addr; if ((pack == p && init == p->init) || data != init->data) { - nv_wr32(priv, 0x400204, init->data); + nv_wr32(gr, 0x400204, init->data); data = init->data; } while (addr < next) { - nv_wr32(priv, 0x400200, addr); + nv_wr32(gr, 0x400200, addr); /** * Wait for GR to go idle after submitting a * GO_IDLE bundle */ if ((addr & 0xffff) == 0xe100) - gf100_gr_wait_idle(priv); - nv_wait(priv, 0x400700, 0x00000004, 0x00000000); + gf100_gr_wait_idle(gr); + nv_wait(gr, 0x400700, 0x00000004, 0x00000000); addr += init->pitch; } } - nv_wr32(priv, 0x400208, 0x00000000); + nv_wr32(gr, 0x400208, 0x00000000); } void -gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) +gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) { const struct gf100_gr_pack *pack; const struct gf100_gr_init *init; @@ -756,26 +756,26 @@ gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p) u32 addr = init->addr; if ((pack == p && init == p->init) || data != init->data) { - nv_wr32(priv, 0x40448c, init->data); + nv_wr32(gr, 0x40448c, init->data); data = init->data; } while (addr < next) { - nv_wr32(priv, 0x404488, ctrl | (addr << 14)); + nv_wr32(gr, 0x404488, ctrl | (addr << 14)); addr += init->pitch; } } } u64 -gf100_gr_units(struct nvkm_gr *gr) +gf100_gr_units(struct nvkm_gr *obj) { - struct gf100_gr_priv *priv = (void *)gr; + struct gf100_gr *gr = container_of(obj, typeof(*gr), base); u64 cfg; - cfg = (u32)priv->gpc_nr; - cfg |= (u32)priv->tpc_total << 8; - cfg |= (u64)priv->rop_nr << 32; + cfg = (u32)gr->gpc_nr; + cfg |= (u32)gr->tpc_total << 8; + cfg |= (u64)gr->rop_nr << 32; return cfg; } @@ -806,17 +806,17 @@ static const struct nvkm_enum gf100_gpc_rop_error[] = { }; static void -gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc) +gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) { u32 trap[4]; int i; - trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); - trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); - trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); - trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); + trap[0] = nv_rd32(gr, GPC_UNIT(gpc, 0x0420)); + trap[1] = nv_rd32(gr, GPC_UNIT(gpc, 0x0434)); + trap[2] = nv_rd32(gr, GPC_UNIT(gpc, 0x0438)); + trap[3] = nv_rd32(gr, GPC_UNIT(gpc, 0x043c)); - nv_error(priv, "GPC%d/PROP trap:", gpc); + nv_error(gr, "GPC%d/PROP trap:", gpc); for (i = 0; i <= 29; ++i) { if (!(trap[0] & (1 << i))) continue; @@ -825,10 +825,10 @@ gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc) } pr_cont("\n"); - nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", + nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n", trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, trap[3] & 0xff); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); } static const struct nvkm_enum gf100_mp_warp_error[] = { @@ -851,12 +851,12 @@ static const struct nvkm_bitfield gf100_mp_global_error[] = { }; static void -gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc) +gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) { - u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); - u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); + u32 werr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x648)); + u32 gerr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x650)); - nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); + nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc); nvkm_bitfield_print(gf100_mp_global_error, gerr); if (werr) { pr_cont(" "); @@ -864,150 +864,150 @@ gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc) } pr_cont("\n"); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x650), gerr); } static void -gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc) +gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) { - u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); + u32 stat = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0508)); if (stat & 0x00000001) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); - nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); + u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0224)); + nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); stat &= ~0x00000001; } if (stat & 0x00000002) { - gf100_gr_trap_mp(priv, gpc, tpc); + gf100_gr_trap_mp(gr, gpc, tpc); stat &= ~0x00000002; } if (stat & 0x00000004) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); - nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); + u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0084)); + nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); stat &= ~0x00000004; } if (stat & 0x00000008) { - u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); - nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); + u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x048c)); + nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); stat &= ~0x00000008; } if (stat) { - nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); + nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); } } static void -gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc) +gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) { - u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); + u32 stat = nv_rd32(gr, GPC_UNIT(gpc, 0x2c90)); int tpc; if (stat & 0x00000001) { - gf100_gr_trap_gpc_rop(priv, gpc); + gf100_gr_trap_gpc_rop(gr, gpc); stat &= ~0x00000001; } if (stat & 0x00000002) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); - nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); + u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0900)); + nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); + nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); stat &= ~0x00000002; } if (stat & 0x00000004) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); - nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); + u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x1028)); + nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); + nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); stat &= ~0x00000004; } if (stat & 0x00000008) { - u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); - nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); + u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0824)); + nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); + nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); stat &= ~0x00000009; } - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { u32 mask = 0x00010000 << tpc; if (stat & mask) { - gf100_gr_trap_tpc(priv, gpc, tpc); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); + gf100_gr_trap_tpc(gr, gpc, tpc); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), mask); stat &= ~mask; } } if (stat) { - nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); + nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat); } } static void -gf100_gr_trap_intr(struct gf100_gr_priv *priv) +gf100_gr_trap_intr(struct gf100_gr *gr) { - u32 trap = nv_rd32(priv, 0x400108); + u32 trap = nv_rd32(gr, 0x400108); int rop, gpc, i; if (trap & 0x00000001) { - u32 stat = nv_rd32(priv, 0x404000); - nv_error(priv, "DISPATCH 0x%08x\n", stat); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000001); + u32 stat = nv_rd32(gr, 0x404000); + nv_error(gr, "DISPATCH 0x%08x\n", stat); + nv_wr32(gr, 0x404000, 0xc0000000); + nv_wr32(gr, 0x400108, 0x00000001); trap &= ~0x00000001; } if (trap & 0x00000002) { - u32 stat = nv_rd32(priv, 0x404600); - nv_error(priv, "M2MF 0x%08x\n", stat); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000002); + u32 stat = nv_rd32(gr, 0x404600); + nv_error(gr, "M2MF 0x%08x\n", stat); + nv_wr32(gr, 0x404600, 0xc0000000); + nv_wr32(gr, 0x400108, 0x00000002); trap &= ~0x00000002; } if (trap & 0x00000008) { - u32 stat = nv_rd32(priv, 0x408030); - nv_error(priv, "CCACHE 0x%08x\n", stat); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000008); + u32 stat = nv_rd32(gr, 0x408030); + nv_error(gr, "CCACHE 0x%08x\n", stat); + nv_wr32(gr, 0x408030, 0xc0000000); + nv_wr32(gr, 0x400108, 0x00000008); trap &= ~0x00000008; } if (trap & 0x00000010) { - u32 stat = nv_rd32(priv, 0x405840); - nv_error(priv, "SHADER 0x%08x\n", stat); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000010); + u32 stat = nv_rd32(gr, 0x405840); + nv_error(gr, "SHADER 0x%08x\n", stat); + nv_wr32(gr, 0x405840, 0xc0000000); + nv_wr32(gr, 0x400108, 0x00000010); trap &= ~0x00000010; } if (trap & 0x00000040) { - u32 stat = nv_rd32(priv, 0x40601c); - nv_error(priv, "UNK6 0x%08x\n", stat); - nv_wr32(priv, 0x40601c, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000040); + u32 stat = nv_rd32(gr, 0x40601c); + nv_error(gr, "UNK6 0x%08x\n", stat); + nv_wr32(gr, 0x40601c, 0xc0000000); + nv_wr32(gr, 0x400108, 0x00000040); trap &= ~0x00000040; } if (trap & 0x00000080) { - u32 stat = nv_rd32(priv, 0x404490); - nv_error(priv, "MACRO 0x%08x\n", stat); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x400108, 0x00000080); + u32 stat = nv_rd32(gr, 0x404490); + nv_error(gr, "MACRO 0x%08x\n", stat); + nv_wr32(gr, 0x404490, 0xc0000000); + nv_wr32(gr, 0x400108, 0x00000080); trap &= ~0x00000080; } if (trap & 0x00000100) { - u32 stat = nv_rd32(priv, 0x407020); + u32 stat = nv_rd32(gr, 0x407020); - nv_error(priv, "SKED:"); + nv_error(gr, "SKED:"); for (i = 0; i <= 29; ++i) { if (!(stat & (1 << i))) continue; @@ -1017,104 +1017,104 @@ gf100_gr_trap_intr(struct gf100_gr_priv *priv) pr_cont("\n"); if (stat & 0x3fffffff) - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x400108, 0x00000100); + nv_wr32(gr, 0x407020, 0x40000000); + nv_wr32(gr, 0x400108, 0x00000100); trap &= ~0x00000100; } if (trap & 0x01000000) { - u32 stat = nv_rd32(priv, 0x400118); - for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { + u32 stat = nv_rd32(gr, 0x400118); + for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { u32 mask = 0x00000001 << gpc; if (stat & mask) { - gf100_gr_trap_gpc(priv, gpc); - nv_wr32(priv, 0x400118, mask); + gf100_gr_trap_gpc(gr, gpc); + nv_wr32(gr, 0x400118, mask); stat &= ~mask; } } - nv_wr32(priv, 0x400108, 0x01000000); + nv_wr32(gr, 0x400108, 0x01000000); trap &= ~0x01000000; } if (trap & 0x02000000) { - for (rop = 0; rop < priv->rop_nr; rop++) { - u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); - u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); - nv_error(priv, "ROP%d 0x%08x 0x%08x\n", + for (rop = 0; rop < gr->rop_nr; rop++) { + u32 statz = nv_rd32(gr, ROP_UNIT(rop, 0x070)); + u32 statc = nv_rd32(gr, ROP_UNIT(rop, 0x144)); + nv_error(gr, "ROP%d 0x%08x 0x%08x\n", rop, statz, statc); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000); } - nv_wr32(priv, 0x400108, 0x02000000); + nv_wr32(gr, 0x400108, 0x02000000); trap &= ~0x02000000; } if (trap) { - nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); - nv_wr32(priv, 0x400108, trap); + nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap); + nv_wr32(gr, 0x400108, trap); } } static void -gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base) +gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) { - nv_error(priv, "%06x - done 0x%08x\n", base, - nv_rd32(priv, base + 0x400)); - nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), - nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); - nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), - nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); + nv_error(gr, "%06x - done 0x%08x\n", base, + nv_rd32(gr, base + 0x400)); + nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, + nv_rd32(gr, base + 0x800), nv_rd32(gr, base + 0x804), + nv_rd32(gr, base + 0x808), nv_rd32(gr, base + 0x80c)); + nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, + nv_rd32(gr, base + 0x810), nv_rd32(gr, base + 0x814), + nv_rd32(gr, base + 0x818), nv_rd32(gr, base + 0x81c)); } void -gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv) +gf100_gr_ctxctl_debug(struct gf100_gr *gr) { - u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; + u32 gpcnr = nv_rd32(gr, 0x409604) & 0xffff; u32 gpc; - gf100_gr_ctxctl_debug_unit(priv, 0x409000); + gf100_gr_ctxctl_debug_unit(gr, 0x409000); for (gpc = 0; gpc < gpcnr; gpc++) - gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); + gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000)); } static void -gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv) +gf100_gr_ctxctl_isr(struct gf100_gr *gr) { - u32 stat = nv_rd32(priv, 0x409c18); + u32 stat = nv_rd32(gr, 0x409c18); if (stat & 0x00000001) { - u32 code = nv_rd32(priv, 0x409814); + u32 code = nv_rd32(gr, 0x409814); if (code == E_BAD_FWMTHD) { - u32 class = nv_rd32(priv, 0x409808); - u32 addr = nv_rd32(priv, 0x40980c); + u32 class = nv_rd32(gr, 0x409808); + u32 addr = nv_rd32(gr, 0x40980c); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00003ffc); - u32 data = nv_rd32(priv, 0x409810); + u32 data = nv_rd32(gr, 0x409810); - nv_error(priv, "FECS MTHD subc %d class 0x%04x " + nv_error(gr, "FECS MTHD subc %d class 0x%04x " "mthd 0x%04x data 0x%08x\n", subc, class, mthd, data); - nv_wr32(priv, 0x409c20, 0x00000001); + nv_wr32(gr, 0x409c20, 0x00000001); stat &= ~0x00000001; } else { - nv_error(priv, "FECS ucode error %d\n", code); + nv_error(gr, "FECS ucode error %d\n", code); } } if (stat & 0x00080000) { - nv_error(priv, "FECS watchdog timeout\n"); - gf100_gr_ctxctl_debug(priv); - nv_wr32(priv, 0x409c20, 0x00080000); + nv_error(gr, "FECS watchdog timeout\n"); + gf100_gr_ctxctl_debug(gr); + nv_wr32(gr, 0x409c20, 0x00080000); stat &= ~0x00080000; } if (stat) { - nv_error(priv, "FECS 0x%08x\n", stat); - gf100_gr_ctxctl_debug(priv); - nv_wr32(priv, 0x409c20, stat); + nv_error(gr, "FECS 0x%08x\n", stat); + gf100_gr_ctxctl_debug(gr); + nv_wr32(gr, 0x409c20, stat); } } @@ -1125,19 +1125,19 @@ gf100_gr_intr(struct nvkm_subdev *subdev) struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle; - struct gf100_gr_priv *priv = (void *)subdev; - u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; - u32 stat = nv_rd32(priv, 0x400100); - u32 addr = nv_rd32(priv, 0x400704); + struct gf100_gr *gr = (void *)subdev; + u64 inst = nv_rd32(gr, 0x409b00) & 0x0fffffff; + u32 stat = nv_rd32(gr, 0x400100); + u32 addr = nv_rd32(gr, 0x400704); u32 mthd = (addr & 0x00003ffc); u32 subc = (addr & 0x00070000) >> 16; - u32 data = nv_rd32(priv, 0x400708); - u32 code = nv_rd32(priv, 0x400110); + u32 data = nv_rd32(gr, 0x400708); + u32 code = nv_rd32(gr, 0x400110); u32 class; int chid; - if (nv_device(priv)->card_type < NV_E0 || subc < 4) - class = nv_rd32(priv, 0x404200 + (subc * 4)); + if (nv_device(gr)->card_type < NV_E0 || subc < 4) + class = nv_rd32(gr, 0x404200 + (subc * 4)); else class = 0x0000; @@ -1149,89 +1149,89 @@ gf100_gr_intr(struct nvkm_subdev *subdev) * notifier interrupt, only needed for cyclestats * can be safely ignored */ - nv_wr32(priv, 0x400100, 0x00000001); + nv_wr32(gr, 0x400100, 0x00000001); stat &= ~0x00000001; } if (stat & 0x00000010) { handle = nvkm_handle_get_class(engctx, class); if (!handle || nv_call(handle->object, mthd, data)) { - nv_error(priv, + nv_error(gr, "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); } nvkm_handle_put(handle); - nv_wr32(priv, 0x400100, 0x00000010); + nv_wr32(gr, 0x400100, 0x00000010); stat &= ~0x00000010; } if (stat & 0x00000020) { - nv_error(priv, + nv_error(gr, "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); - nv_wr32(priv, 0x400100, 0x00000020); + nv_wr32(gr, 0x400100, 0x00000020); stat &= ~0x00000020; } if (stat & 0x00100000) { - nv_error(priv, "DATA_ERROR ["); + nv_error(gr, "DATA_ERROR ["); nvkm_enum_print(nv50_data_error_names, code); pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); - nv_wr32(priv, 0x400100, 0x00100000); + nv_wr32(gr, 0x400100, 0x00100000); stat &= ~0x00100000; } if (stat & 0x00200000) { - nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, + nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, nvkm_client_name(engctx)); - gf100_gr_trap_intr(priv); - nv_wr32(priv, 0x400100, 0x00200000); + gf100_gr_trap_intr(gr); + nv_wr32(gr, 0x400100, 0x00200000); stat &= ~0x00200000; } if (stat & 0x00080000) { - gf100_gr_ctxctl_isr(priv); - nv_wr32(priv, 0x400100, 0x00080000); + gf100_gr_ctxctl_isr(gr); + nv_wr32(gr, 0x400100, 0x00080000); stat &= ~0x00080000; } if (stat) { - nv_error(priv, "unknown stat 0x%08x\n", stat); - nv_wr32(priv, 0x400100, stat); + nv_error(gr, "unknown stat 0x%08x\n", stat); + nv_wr32(gr, 0x400100, stat); } - nv_wr32(priv, 0x400500, 0x00010001); + nv_wr32(gr, 0x400500, 0x00010001); nvkm_engctx_put(engctx); } void -gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base, +gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) { int i; - nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); + nv_wr32(gr, fuc_base + 0x01c0, 0x01000000); for (i = 0; i < data->size / 4; i++) - nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); + nv_wr32(gr, fuc_base + 0x01c4, data->data[i]); - nv_wr32(priv, fuc_base + 0x0180, 0x01000000); + nv_wr32(gr, fuc_base + 0x0180, 0x01000000); for (i = 0; i < code->size / 4; i++) { if ((i & 0x3f) == 0) - nv_wr32(priv, fuc_base + 0x0188, i >> 6); - nv_wr32(priv, fuc_base + 0x0184, code->data[i]); + nv_wr32(gr, fuc_base + 0x0188, i >> 6); + nv_wr32(gr, fuc_base + 0x0184, code->data[i]); } /* code must be padded to 0x40 words */ for (; i & 0x3f; i++) - nv_wr32(priv, fuc_base + 0x0184, 0); + nv_wr32(gr, fuc_base + 0x0184, 0); } static void -gf100_gr_init_csdata(struct gf100_gr_priv *priv, +gf100_gr_init_csdata(struct gf100_gr *gr, const struct gf100_gr_pack *pack, u32 falcon, u32 starstar, u32 base) { @@ -1240,12 +1240,12 @@ gf100_gr_init_csdata(struct gf100_gr_priv *priv, u32 addr = ~0, prev = ~0, xfer = 0; u32 star, temp; - nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); - star = nv_rd32(priv, falcon + 0x01c4); - temp = nv_rd32(priv, falcon + 0x01c4); + nv_wr32(gr, falcon + 0x01c0, 0x02000000 + starstar); + star = nv_rd32(gr, falcon + 0x01c4); + temp = nv_rd32(gr, falcon + 0x01c4); if (temp > star) star = temp; - nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); + nv_wr32(gr, falcon + 0x01c0, 0x01000000 + star); pack_for_each_init(init, iter, pack) { u32 head = init->addr - base; @@ -1254,7 +1254,7 @@ gf100_gr_init_csdata(struct gf100_gr_priv *priv, if (head != prev + 4 || xfer >= 32) { if (xfer) { u32 data = ((--xfer << 26) | addr); - nv_wr32(priv, falcon + 0x01c4, data); + nv_wr32(gr, falcon + 0x01c4, data); star += 4; } addr = head; @@ -1266,101 +1266,101 @@ gf100_gr_init_csdata(struct gf100_gr_priv *priv, } } - nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); - nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); - nv_wr32(priv, falcon + 0x01c4, star + 4); + nv_wr32(gr, falcon + 0x01c4, (--xfer << 26) | addr); + nv_wr32(gr, falcon + 0x01c0, 0x01000004 + starstar); + nv_wr32(gr, falcon + 0x01c4, star + 4); } int -gf100_gr_init_ctxctl(struct gf100_gr_priv *priv) +gf100_gr_init_ctxctl(struct gf100_gr *gr) { - struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass; - struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; + struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; + struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; int i; - if (priv->firmware) { + if (gr->firmware) { /* load fuc microcode */ - nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); - gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c, - &priv->fuc409d); - gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac, - &priv->fuc41ad); - nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, + &gr->fuc409d); + gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, + &gr->fuc41ad); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); /* start both of them running */ - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x41a10c, 0x00000000); - nv_wr32(priv, 0x40910c, 0x00000000); - nv_wr32(priv, 0x41a100, 0x00000002); - nv_wr32(priv, 0x409100, 0x00000002); - if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) - nv_warn(priv, "0x409800 wait failed\n"); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x7fffffff); - nv_wr32(priv, 0x409504, 0x00000021); - - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000010); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x10 timeout\n"); + nv_wr32(gr, 0x409840, 0xffffffff); + nv_wr32(gr, 0x41a10c, 0x00000000); + nv_wr32(gr, 0x40910c, 0x00000000); + nv_wr32(gr, 0x41a100, 0x00000002); + nv_wr32(gr, 0x409100, 0x00000002); + if (!nv_wait(gr, 0x409800, 0x00000001, 0x00000001)) + nv_warn(gr, "0x409800 wait failed\n"); + + nv_wr32(gr, 0x409840, 0xffffffff); + nv_wr32(gr, 0x409500, 0x7fffffff); + nv_wr32(gr, 0x409504, 0x00000021); + + nv_wr32(gr, 0x409840, 0xffffffff); + nv_wr32(gr, 0x409500, 0x00000000); + nv_wr32(gr, 0x409504, 0x00000010); + if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(gr, "fuc09 req 0x10 timeout\n"); return -EBUSY; } - priv->size = nv_rd32(priv, 0x409800); + gr->size = nv_rd32(gr, 0x409800); - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000016); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x16 timeout\n"); + nv_wr32(gr, 0x409840, 0xffffffff); + nv_wr32(gr, 0x409500, 0x00000000); + nv_wr32(gr, 0x409504, 0x00000016); + if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(gr, "fuc09 req 0x16 timeout\n"); return -EBUSY; } - nv_wr32(priv, 0x409840, 0xffffffff); - nv_wr32(priv, 0x409500, 0x00000000); - nv_wr32(priv, 0x409504, 0x00000025); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x25 timeout\n"); + nv_wr32(gr, 0x409840, 0xffffffff); + nv_wr32(gr, 0x409500, 0x00000000); + nv_wr32(gr, 0x409504, 0x00000025); + if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(gr, "fuc09 req 0x25 timeout\n"); return -EBUSY; } - if (nv_device(priv)->chipset >= 0xe0) { - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000030); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x30 timeout\n"); + if (nv_device(gr)->chipset >= 0xe0) { + nv_wr32(gr, 0x409800, 0x00000000); + nv_wr32(gr, 0x409500, 0x00000001); + nv_wr32(gr, 0x409504, 0x00000030); + if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(gr, "fuc09 req 0x30 timeout\n"); return -EBUSY; } - nv_wr32(priv, 0x409810, 0xb00095c8); - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000031); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x31 timeout\n"); + nv_wr32(gr, 0x409810, 0xb00095c8); + nv_wr32(gr, 0x409800, 0x00000000); + nv_wr32(gr, 0x409500, 0x00000001); + nv_wr32(gr, 0x409504, 0x00000031); + if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(gr, "fuc09 req 0x31 timeout\n"); return -EBUSY; } - nv_wr32(priv, 0x409810, 0x00080420); - nv_wr32(priv, 0x409800, 0x00000000); - nv_wr32(priv, 0x409500, 0x00000001); - nv_wr32(priv, 0x409504, 0x00000032); - if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(priv, "fuc09 req 0x32 timeout\n"); + nv_wr32(gr, 0x409810, 0x00080420); + nv_wr32(gr, 0x409800, 0x00000000); + nv_wr32(gr, 0x409500, 0x00000001); + nv_wr32(gr, 0x409504, 0x00000032); + if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { + nv_error(gr, "fuc09 req 0x32 timeout\n"); return -EBUSY; } - nv_wr32(priv, 0x409614, 0x00000070); - nv_wr32(priv, 0x409614, 0x00000770); - nv_wr32(priv, 0x40802c, 0x00000001); + nv_wr32(gr, 0x409614, 0x00000070); + nv_wr32(gr, 0x409614, 0x00000770); + nv_wr32(gr, 0x40802c, 0x00000001); } - if (priv->data == NULL) { - int ret = gf100_grctx_generate(priv); + if (gr->data == NULL) { + int ret = gf100_grctx_generate(gr); if (ret) { - nv_error(priv, "failed to construct context\n"); + nv_error(gr, "failed to construct context\n"); return ret; } } @@ -1372,51 +1372,51 @@ gf100_gr_init_ctxctl(struct gf100_gr_priv *priv) } /* load HUB microcode */ - nvkm_mc(priv)->unk260(nvkm_mc(priv), 0); - nv_wr32(priv, 0x4091c0, 0x01000000); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + nv_wr32(gr, 0x4091c0, 0x01000000); for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) - nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); + nv_wr32(gr, 0x4091c4, oclass->fecs.ucode->data.data[i]); - nv_wr32(priv, 0x409180, 0x01000000); + nv_wr32(gr, 0x409180, 0x01000000); for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) - nv_wr32(priv, 0x409188, i >> 6); - nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); + nv_wr32(gr, 0x409188, i >> 6); + nv_wr32(gr, 0x409184, oclass->fecs.ucode->code.data[i]); } /* load GPC microcode */ - nv_wr32(priv, 0x41a1c0, 0x01000000); + nv_wr32(gr, 0x41a1c0, 0x01000000); for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) - nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); + nv_wr32(gr, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); - nv_wr32(priv, 0x41a180, 0x01000000); + nv_wr32(gr, 0x41a180, 0x01000000); for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) - nv_wr32(priv, 0x41a188, i >> 6); - nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); + nv_wr32(gr, 0x41a188, i >> 6); + nv_wr32(gr, 0x41a184, oclass->gpccs.ucode->code.data[i]); } - nvkm_mc(priv)->unk260(nvkm_mc(priv), 1); + nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); /* load register lists */ - gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); - gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); - gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); - gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); + gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000); + gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000); + gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800); + gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); /* start HUB ucode running, it'll init the GPCs */ - nv_wr32(priv, 0x40910c, 0x00000000); - nv_wr32(priv, 0x409100, 0x00000002); - if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { - nv_error(priv, "HUB_INIT timed out\n"); - gf100_gr_ctxctl_debug(priv); + nv_wr32(gr, 0x40910c, 0x00000000); + nv_wr32(gr, 0x409100, 0x00000002); + if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) { + nv_error(gr, "HUB_INIT timed out\n"); + gf100_gr_ctxctl_debug(gr); return -EBUSY; } - priv->size = nv_rd32(priv, 0x409804); - if (priv->data == NULL) { - int ret = gf100_grctx_generate(priv); + gr->size = nv_rd32(gr, 0x409804); + if (gr->data == NULL) { + int ret = gf100_grctx_generate(gr); if (ret) { - nv_error(priv, "failed to construct context\n"); + nv_error(gr, "failed to construct context\n"); return ret; } } @@ -1428,112 +1428,112 @@ int gf100_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr_priv *priv = (void *)object; - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + struct gf100_gr *gr = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int ret, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); + nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); - gf100_gr_mmio(priv, oclass->mmio); + gf100_gr_mmio(gr, oclass->mmio); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); + for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); + nv_wr32(gr, GPC_BCAST(0x0980), data[0]); + nv_wr32(gr, GPC_BCAST(0x0984), data[1]); + nv_wr32(gr, GPC_BCAST(0x0988), data[2]); + nv_wr32(gr, GPC_BCAST(0x098c), data[3]); - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); } - if (nv_device(priv)->chipset != 0xd7) - nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); + if (nv_device(gr)->chipset != 0xd7) + nv_wr32(gr, GPC_BCAST(0x1bd4), magicgpc918); else - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - - nv_wr32(priv, 0x400500, 0x00010001); - - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - - nv_wr32(priv, 0x409c24, 0x000f0000); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x40601c, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); + + nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + + nv_wr32(gr, 0x400500, 0x00010001); + + nv_wr32(gr, 0x400100, 0xffffffff); + nv_wr32(gr, 0x40013c, 0xffffffff); + + nv_wr32(gr, 0x409c24, 0x000f0000); + nv_wr32(gr, 0x404000, 0xc0000000); + nv_wr32(gr, 0x404600, 0xc0000000); + nv_wr32(gr, 0x408030, 0xc0000000); + nv_wr32(gr, 0x40601c, 0xc0000000); + nv_wr32(gr, 0x404490, 0xc0000000); + nv_wr32(gr, 0x406018, 0xc0000000); + nv_wr32(gr, 0x405840, 0xc0000000); + nv_wr32(gr, 0x405844, 0x00ffffff); + nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); + nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + for (rop = 0; rop < gr->rop_nr; rop++) { + nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); + nv_wr32(gr, 0x400108, 0xffffffff); + nv_wr32(gr, 0x400138, 0xffffffff); + nv_wr32(gr, 0x400118, 0xffffffff); + nv_wr32(gr, 0x400130, 0xffffffff); + nv_wr32(gr, 0x40011c, 0xffffffff); + nv_wr32(gr, 0x400134, 0xffffffff); - nv_wr32(priv, 0x400054, 0x34ce3464); + nv_wr32(gr, 0x400054, 0x34ce3464); - gf100_gr_zbc_init(priv); + gf100_gr_zbc_init(gr); - return gf100_gr_init_ctxctl(priv); + return gf100_gr_init_ctxctl(gr); } void @@ -1544,10 +1544,10 @@ gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) } int -gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, +gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, struct gf100_gr_fuc *fuc) { - struct nvkm_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(gr); const struct firmware *fw; char f[64]; char cname[16]; @@ -1566,7 +1566,7 @@ gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); ret = request_firmware(&fw, f, nv_device_base(device)); if (ret) { - nv_error(priv, "failed to load %s\n", fwname); + nv_error(gr, "failed to load %s\n", fwname); return ret; } @@ -1579,19 +1579,19 @@ gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, void gf100_gr_dtor(struct nvkm_object *object) { - struct gf100_gr_priv *priv = (void *)object; + struct gf100_gr *gr = (void *)object; - kfree(priv->data); + kfree(gr->data); - gf100_gr_dtor_fw(&priv->fuc409c); - gf100_gr_dtor_fw(&priv->fuc409d); - gf100_gr_dtor_fw(&priv->fuc41ac); - gf100_gr_dtor_fw(&priv->fuc41ad); + gf100_gr_dtor_fw(&gr->fuc409c); + gf100_gr_dtor_fw(&gr->fuc409d); + gf100_gr_dtor_fw(&gr->fuc41ac); + gf100_gr_dtor_fw(&gr->fuc41ad); - nvkm_gpuobj_ref(NULL, &priv->unk4188b8); - nvkm_gpuobj_ref(NULL, &priv->unk4188b4); + nvkm_gpuobj_ref(NULL, &gr->unk4188b8); + nvkm_gpuobj_ref(NULL, &gr->unk4188b4); - nvkm_gr_destroy(&priv->base); + nvkm_gr_destroy(&gr->base); } int @@ -1601,7 +1601,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, { struct gf100_gr_oclass *oclass = (void *)bclass; struct nvkm_device *device = nv_device(parent); - struct gf100_gr_priv *priv; + struct gf100_gr *gr; bool use_ext_fw, enable; int ret, i, j; @@ -1609,94 +1609,94 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, oclass->fecs.ucode == NULL); enable = use_ext_fw || oclass->fecs.ucode != NULL; - ret = nvkm_gr_create(parent, engine, bclass, enable, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); + *pobject = nv_object(gr); if (ret) return ret; - nv_subdev(priv)->unit = 0x08001000; - nv_subdev(priv)->intr = gf100_gr_intr; + nv_subdev(gr)->unit = 0x08001000; + nv_subdev(gr)->intr = gf100_gr_intr; - priv->base.units = gf100_gr_units; + gr->base.units = gf100_gr_units; if (use_ext_fw) { - nv_info(priv, "using external firmware\n"); - if (gf100_gr_ctor_fw(priv, "fecs_inst", &priv->fuc409c) || - gf100_gr_ctor_fw(priv, "fecs_data", &priv->fuc409d) || - gf100_gr_ctor_fw(priv, "gpccs_inst", &priv->fuc41ac) || - gf100_gr_ctor_fw(priv, "gpccs_data", &priv->fuc41ad)) + nv_info(gr, "using external firmware\n"); + if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || + gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || + gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || + gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) return -ENODEV; - priv->firmware = true; + gr->firmware = true; } - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b4); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, + &gr->unk4188b4); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, - &priv->unk4188b8); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, + &gr->unk4188b8); if (ret) return ret; for (i = 0; i < 0x1000; i += 4) { - nv_wo32(priv->unk4188b4, i, 0x00000010); - nv_wo32(priv->unk4188b8, i, 0x00000010); - } - - priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; - priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; - for (i = 0; i < priv->gpc_nr; i++) { - priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); - priv->tpc_total += priv->tpc_nr[i]; - priv->ppc_nr[i] = oclass->ppc_nr; - for (j = 0; j < priv->ppc_nr[i]; j++) { - u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); - priv->ppc_tpc_nr[i][j] = hweight8(mask); + nv_wo32(gr->unk4188b4, i, 0x00000010); + nv_wo32(gr->unk4188b8, i, 0x00000010); + } + + gr->rop_nr = (nv_rd32(gr, 0x409604) & 0x001f0000) >> 16; + gr->gpc_nr = nv_rd32(gr, 0x409604) & 0x0000001f; + for (i = 0; i < gr->gpc_nr; i++) { + gr->tpc_nr[i] = nv_rd32(gr, GPC_UNIT(i, 0x2608)); + gr->tpc_total += gr->tpc_nr[i]; + gr->ppc_nr[i] = oclass->ppc_nr; + for (j = 0; j < gr->ppc_nr[i]; j++) { + u8 mask = nv_rd32(gr, GPC_UNIT(i, 0x0c30 + (j * 4))); + gr->ppc_tpc_nr[i][j] = hweight8(mask); } } /*XXX: these need figuring out... though it might not even matter */ - switch (nv_device(priv)->chipset) { + switch (nv_device(gr)->chipset) { case 0xc0: - if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ - priv->magic_not_rop_nr = 0x07; + if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ + gr->magic_not_rop_nr = 0x07; } else - if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ - priv->magic_not_rop_nr = 0x05; + if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ + gr->magic_not_rop_nr = 0x05; } else - if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ - priv->magic_not_rop_nr = 0x06; + if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ + gr->magic_not_rop_nr = 0x06; } break; case 0xc3: /* 450, 4/0/0/0, 2 */ - priv->magic_not_rop_nr = 0x03; + gr->magic_not_rop_nr = 0x03; break; case 0xc4: /* 460, 3/4/0/0, 4 */ - priv->magic_not_rop_nr = 0x01; + gr->magic_not_rop_nr = 0x01; break; case 0xc1: /* 2/0/0/0, 1 */ - priv->magic_not_rop_nr = 0x01; + gr->magic_not_rop_nr = 0x01; break; case 0xc8: /* 4/4/3/4, 5 */ - priv->magic_not_rop_nr = 0x06; + gr->magic_not_rop_nr = 0x06; break; case 0xce: /* 4/4/0/0, 4 */ - priv->magic_not_rop_nr = 0x03; + gr->magic_not_rop_nr = 0x03; break; case 0xcf: /* 4/0/0/0, 3 */ - priv->magic_not_rop_nr = 0x03; + gr->magic_not_rop_nr = 0x03; break; case 0xd7: case 0xd9: /* 1/0/0/0, 1 */ case 0xea: /* gk20a */ case 0x12b: /* gm20b */ - priv->magic_not_rop_nr = 0x01; + gr->magic_not_rop_nr = 0x01; break; } - nv_engine(priv)->cclass = *oclass->cclass; - nv_engine(priv)->sclass = oclass->sclass; + nv_engine(gr)->cclass = *oclass->cclass; + nv_engine(gr)->sclass = oclass->sclass; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index f185f034d1ea..b23bc32536fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -67,7 +67,7 @@ struct gf100_gr_zbc_depth { u32 l2; }; -struct gf100_gr_priv { +struct gf100_gr { struct nvkm_gr base; struct gf100_gr_fuc fuc409c; @@ -123,10 +123,10 @@ int gf100_gr_context_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_object **); void gf100_gr_context_dtor(struct nvkm_object *); -void gf100_gr_ctxctl_debug(struct gf100_gr_priv *); +void gf100_gr_ctxctl_debug(struct gf100_gr *); void gf100_gr_dtor_fw(struct gf100_gr_fuc *); -int gf100_gr_ctor_fw(struct gf100_gr_priv *, const char *, +int gf100_gr_ctor_fw(struct gf100_gr *, const char *, struct gf100_gr_fuc *); u64 gf100_gr_units(struct nvkm_gr *); int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *, @@ -134,7 +134,7 @@ int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_object **); void gf100_gr_dtor(struct nvkm_object *); int gf100_gr_init(struct nvkm_object *); -void gf100_gr_zbc_init(struct gf100_gr_priv *); +void gf100_gr_zbc_init(struct gf100_gr *); int gk104_gr_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *data, u32 size, @@ -199,11 +199,11 @@ struct gf100_gr_oclass { int ppc_nr; }; -int gf100_gr_wait_idle(struct gf100_gr_priv *); -void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *); -void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *); -void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *); -int gf100_gr_init_ctxctl(struct gf100_gr_priv *); +int gf100_gr_wait_idle(struct gf100_gr *); +void gf100_gr_mmio(struct gf100_gr *, const struct gf100_gr_pack *); +void gf100_gr_icmd(struct gf100_gr *, const struct gf100_gr_pack *); +void gf100_gr_mthd(struct gf100_gr *, const struct gf100_gr_pack *); +int gf100_gr_init_ctxctl(struct gf100_gr *); /* register init value lists */ @@ -279,7 +279,7 @@ extern const struct gf100_gr_init gm107_gr_init_tex_0[]; extern const struct gf100_gr_init gm107_gr_init_l1c_0[]; extern const struct gf100_gr_init gm107_gr_init_wwdx_0[]; extern const struct gf100_gr_init gm107_gr_init_cbm_0[]; -void gm107_gr_init_bios(struct gf100_gr_priv *); +void gm107_gr_init_bios(struct gf100_gr *); extern const struct gf100_gr_pack gm204_gr_pack_mmio[]; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 46f7844eca70..9f83122dc1a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -196,9 +196,9 @@ int gk104_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr_priv *priv = (void *)object; - struct nvkm_pmu *pmu = nvkm_pmu(priv); - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + struct gf100_gr *gr = (void *)object; + struct nvkm_pmu *pmu = nvkm_pmu(gr); + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; @@ -207,107 +207,107 @@ gk104_gr_init(struct nvkm_object *object) if (pmu) pmu->pgob(pmu, false); - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); + nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); - gf100_gr_mmio(priv, oclass->mmio); + gf100_gr_mmio(gr, oclass->mmio); - nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); + nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); + for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x0980), data[0]); + nv_wr32(gr, GPC_BCAST(0x0984), data[1]); + nv_wr32(gr, GPC_BCAST(0x0988), data[2]); + nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - - nv_wr32(priv, 0x400500, 0x00010001); - - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - - nv_wr32(priv, 0x409ffc, 0x00000000); - nv_wr32(priv, 0x409c14, 0x00003e3e); - nv_wr32(priv, 0x409c24, 0x000f0001); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + + nv_wr32(gr, 0x400500, 0x00010001); + + nv_wr32(gr, 0x400100, 0xffffffff); + nv_wr32(gr, 0x40013c, 0xffffffff); + + nv_wr32(gr, 0x409ffc, 0x00000000); + nv_wr32(gr, 0x409c14, 0x00003e3e); + nv_wr32(gr, 0x409c24, 0x000f0001); + nv_wr32(gr, 0x404000, 0xc0000000); + nv_wr32(gr, 0x404600, 0xc0000000); + nv_wr32(gr, 0x408030, 0xc0000000); + nv_wr32(gr, 0x404490, 0xc0000000); + nv_wr32(gr, 0x406018, 0xc0000000); + nv_wr32(gr, 0x407020, 0x40000000); + nv_wr32(gr, 0x405840, 0xc0000000); + nv_wr32(gr, 0x405844, 0x00ffffff); + nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); + nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x3038), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + for (rop = 0; rop < gr->rop_nr; rop++) { + nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000); + nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000); + nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); + nv_wr32(gr, 0x400108, 0xffffffff); + nv_wr32(gr, 0x400138, 0xffffffff); + nv_wr32(gr, 0x400118, 0xffffffff); + nv_wr32(gr, 0x400130, 0xffffffff); + nv_wr32(gr, 0x40011c, 0xffffffff); + nv_wr32(gr, 0x400134, 0xffffffff); - nv_wr32(priv, 0x400054, 0x34ce3464); + nv_wr32(gr, 0x400054, 0x34ce3464); - gf100_gr_zbc_init(priv); + gf100_gr_zbc_init(gr); - return gf100_gr_init_ctxctl(priv); + return gf100_gr_init_ctxctl(gr); } int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index fc4a910b2498..9816303ad716 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -160,46 +160,46 @@ gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { int err; - struct gf100_gr_priv *priv; + struct gf100_gr *gr; struct gf100_gr_fuc fuc; err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject); if (err) return err; - priv = (void *)*pobject; + gr = (void *)*pobject; - err = gf100_gr_ctor_fw(priv, "sw_nonctx", &fuc); + err = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc); if (err) return err; - priv->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc); + gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc); gf100_gr_dtor_fw(&fuc); - if (IS_ERR(priv->fuc_sw_nonctx)) - return PTR_ERR(priv->fuc_sw_nonctx); + if (IS_ERR(gr->fuc_sw_nonctx)) + return PTR_ERR(gr->fuc_sw_nonctx); - err = gf100_gr_ctor_fw(priv, "sw_ctx", &fuc); + err = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc); if (err) return err; - priv->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc); + gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc); gf100_gr_dtor_fw(&fuc); - if (IS_ERR(priv->fuc_sw_ctx)) - return PTR_ERR(priv->fuc_sw_ctx); + if (IS_ERR(gr->fuc_sw_ctx)) + return PTR_ERR(gr->fuc_sw_ctx); - err = gf100_gr_ctor_fw(priv, "sw_bundle_init", &fuc); + err = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc); if (err) return err; - priv->fuc_bundle = gk20a_gr_av_to_init(&fuc); + gr->fuc_bundle = gk20a_gr_av_to_init(&fuc); gf100_gr_dtor_fw(&fuc); - if (IS_ERR(priv->fuc_bundle)) - return PTR_ERR(priv->fuc_bundle); + if (IS_ERR(gr->fuc_bundle)) + return PTR_ERR(gr->fuc_bundle); - err = gf100_gr_ctor_fw(priv, "sw_method_init", &fuc); + err = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc); if (err) return err; - priv->fuc_method = gk20a_gr_av_to_method(&fuc); + gr->fuc_method = gk20a_gr_av_to_method(&fuc); gf100_gr_dtor_fw(&fuc); - if (IS_ERR(priv->fuc_method)) - return PTR_ERR(priv->fuc_method); + if (IS_ERR(gr->fuc_method)) + return PTR_ERR(gr->fuc_method); return 0; } @@ -207,26 +207,26 @@ gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, void gk20a_gr_dtor(struct nvkm_object *object) { - struct gf100_gr_priv *priv = (void *)object; + struct gf100_gr *gr = (void *)object; - gk20a_gr_init_dtor(priv->fuc_method); - gk20a_gr_init_dtor(priv->fuc_bundle); - gk20a_gr_init_dtor(priv->fuc_sw_ctx); - gk20a_gr_init_dtor(priv->fuc_sw_nonctx); + gk20a_gr_init_dtor(gr->fuc_method); + gk20a_gr_init_dtor(gr->fuc_bundle); + gk20a_gr_init_dtor(gr->fuc_sw_ctx); + gk20a_gr_init_dtor(gr->fuc_sw_nonctx); gf100_gr_dtor(object); } static int -gk20a_gr_wait_mem_scrubbing(struct gf100_gr_priv *priv) +gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) { - if (!nv_wait(priv, 0x40910c, 0x6, 0x0)) { - nv_error(priv, "FECS mem scrubbing timeout\n"); + if (!nv_wait(gr, 0x40910c, 0x6, 0x0)) { + nv_error(gr, "FECS mem scrubbing timeout\n"); return -ETIMEDOUT; } - if (!nv_wait(priv, 0x41a10c, 0x6, 0x0)) { - nv_error(priv, "GPCCS mem scrubbing timeout\n"); + if (!nv_wait(gr, 0x41a10c, 0x6, 0x0)) { + nv_error(gr, "GPCCS mem scrubbing timeout\n"); return -ETIMEDOUT; } @@ -234,109 +234,109 @@ gk20a_gr_wait_mem_scrubbing(struct gf100_gr_priv *priv) } static void -gk20a_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) +gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { - nv_wr32(priv, 0x419e44, 0x1ffffe); - nv_wr32(priv, 0x419e4c, 0x7f); + nv_wr32(gr, 0x419e44, 0x1ffffe); + nv_wr32(gr, 0x419e4c, 0x7f); } int gk20a_gr_init(struct nvkm_object *object) { struct gk20a_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr_priv *priv = (void *)object; - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + struct gf100_gr *gr = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc; int ret, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; /* Clear SCC RAM */ - nv_wr32(priv, 0x40802c, 0x1); + nv_wr32(gr, 0x40802c, 0x1); - gf100_gr_mmio(priv, priv->fuc_sw_nonctx); + gf100_gr_mmio(gr, gr->fuc_sw_nonctx); - ret = gk20a_gr_wait_mem_scrubbing(priv); + ret = gk20a_gr_wait_mem_scrubbing(gr); if (ret) return ret; - ret = gf100_gr_wait_idle(priv); + ret = gf100_gr_wait_idle(gr); if (ret) return ret; /* MMU debug buffer */ - nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8); - nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8); + nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8); + nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8); if (oclass->init_gpc_mmu) - oclass->init_gpc_mmu(priv); + oclass->init_gpc_mmu(gr); /* Set the PE as stream master */ - nv_mask(priv, 0x503018, 0x1, 0x1); + nv_mask(gr, 0x503018, 0x1, 0x1); /* Zcull init */ memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); + for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x0980), data[0]); + nv_wr32(gr, GPC_BCAST(0x0984), data[1]); + nv_wr32(gr, GPC_BCAST(0x0988), data[2]); + nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); /* Enable FIFO access */ - nv_wr32(priv, 0x400500, 0x00010001); + nv_wr32(gr, 0x400500, 0x00010001); /* Enable interrupts */ - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); + nv_wr32(gr, 0x400100, 0xffffffff); + nv_wr32(gr, 0x40013c, 0xffffffff); /* Enable FECS error interrupts */ - nv_wr32(priv, 0x409c24, 0x000f0000); + nv_wr32(gr, 0x409c24, 0x000f0000); /* Enable hardware warning exceptions */ - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); + nv_wr32(gr, 0x404000, 0xc0000000); + nv_wr32(gr, 0x404600, 0xc0000000); if (oclass->set_hww_esr_report_mask) - oclass->set_hww_esr_report_mask(priv); + oclass->set_hww_esr_report_mask(gr); /* Enable TPC exceptions per GPC */ - nv_wr32(priv, 0x419d0c, 0x2); - nv_wr32(priv, 0x41ac94, (((1 << priv->tpc_total) - 1) & 0xff) << 16); + nv_wr32(gr, 0x419d0c, 0x2); + nv_wr32(gr, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16); /* Reset and enable all exceptions */ - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); + nv_wr32(gr, 0x400108, 0xffffffff); + nv_wr32(gr, 0x400138, 0xffffffff); + nv_wr32(gr, 0x400118, 0xffffffff); + nv_wr32(gr, 0x400130, 0xffffffff); + nv_wr32(gr, 0x40011c, 0xffffffff); + nv_wr32(gr, 0x400134, 0xffffffff); - gf100_gr_zbc_init(priv); + gf100_gr_zbc_init(gr); - return gf100_gr_init_ctxctl(priv); + return gf100_gr_init_ctxctl(gr); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h index b36958505a81..411099d222d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h @@ -28,8 +28,8 @@ struct gk20a_gr_oclass { struct gf100_gr_oclass gf100; - void (*init_gpc_mmu)(struct gf100_gr_priv *); - void (*set_hww_esr_report_mask)(struct gf100_gr_priv *); + void (*init_gpc_mmu)(struct gf100_gr *); + void (*set_hww_esr_report_mask)(struct gf100_gr *); }; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index a5ebd459bc24..5e9560f6ac0e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -292,7 +292,7 @@ gm107_gr_pack_mmio[] = { ******************************************************************************/ void -gm107_gr_init_bios(struct gf100_gr_priv *priv) +gm107_gr_init_bios(struct gf100_gr *gr) { static const struct { u32 ctrl; @@ -304,7 +304,7 @@ gm107_gr_init_bios(struct gf100_gr_priv *priv) { 0x419af0, 0x419af4 }, { 0x419af8, 0x419afc }, }; - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(gr); struct nvbios_P0260E infoE; struct nvbios_P0260X infoX; int E = -1, X; @@ -312,9 +312,9 @@ gm107_gr_init_bios(struct gf100_gr_priv *priv) while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { if (X = -1, E < ARRAY_SIZE(regs)) { - nv_wr32(priv, regs[E].ctrl, infoE.data); + nv_wr32(gr, regs[E].ctrl, infoE.data); while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) - nv_wr32(priv, regs[E].data, infoX.data); + nv_wr32(gr, regs[E].data, infoX.data); } } } @@ -323,113 +323,113 @@ int gm107_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr_priv *priv = (void *)object; - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + struct gf100_gr *gr = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; int ret, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); - nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); + nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000); + nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); + nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); - gf100_gr_mmio(priv, oclass->mmio); + gf100_gr_mmio(gr, oclass->mmio); - gm107_gr_init_bios(priv); + gm107_gr_init_bios(gr); - nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); + nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); + for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x0980), data[0]); + nv_wr32(gr, GPC_BCAST(0x0984), data[1]); + nv_wr32(gr, GPC_BCAST(0x0988), data[2]); + nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - - nv_wr32(priv, 0x400500, 0x00010001); - - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - nv_wr32(priv, 0x400124, 0x00000002); - nv_wr32(priv, 0x409c24, 0x000e0000); - - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++) - nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); + nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + + nv_wr32(gr, 0x400500, 0x00010001); + + nv_wr32(gr, 0x400100, 0xffffffff); + nv_wr32(gr, 0x40013c, 0xffffffff); + nv_wr32(gr, 0x400124, 0x00000002); + nv_wr32(gr, 0x409c24, 0x000e0000); + + nv_wr32(gr, 0x404000, 0xc0000000); + nv_wr32(gr, 0x404600, 0xc0000000); + nv_wr32(gr, 0x408030, 0xc0000000); + nv_wr32(gr, 0x404490, 0xc0000000); + nv_wr32(gr, 0x406018, 0xc0000000); + nv_wr32(gr, 0x407020, 0x40000000); + nv_wr32(gr, 0x405840, 0xc0000000); + nv_wr32(gr, 0x405844, 0x00ffffff); + nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++) + nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + for (rop = 0; rop < gr->rop_nr; rop++) { + nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000); + nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000); + nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); + nv_wr32(gr, 0x400108, 0xffffffff); + nv_wr32(gr, 0x400138, 0xffffffff); + nv_wr32(gr, 0x400118, 0xffffffff); + nv_wr32(gr, 0x400130, 0xffffffff); + nv_wr32(gr, 0x40011c, 0xffffffff); + nv_wr32(gr, 0x400134, 0xffffffff); - nv_wr32(priv, 0x400054, 0x2c350f63); + nv_wr32(gr, 0x400054, 0x2c350f63); - gf100_gr_zbc_init(priv); + gf100_gr_zbc_init(gr); - return gf100_gr_init_ctxctl(priv); + return gf100_gr_init_ctxctl(gr); } #include "fuc/hubgm107.fuc5.h" diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c index fdb1dcf16a59..4cc60edafaef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c @@ -243,7 +243,7 @@ gm204_gr_data[] = { ******************************************************************************/ static int -gm204_gr_init_ctxctl(struct gf100_gr_priv *priv) +gm204_gr_init_ctxctl(struct gf100_gr *gr) { return 0; } @@ -252,122 +252,122 @@ int gm204_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr_priv *priv = (void *)object; - const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); + struct gf100_gr *gr = (void *)object; + const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; int ret, i; u32 tmp; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - tmp = nv_rd32(priv, 0x100c80); /*XXX: mask? */ - nv_wr32(priv, 0x418880, 0x00001000 | (tmp & 0x00000fff)); - nv_wr32(priv, 0x418890, 0x00000000); - nv_wr32(priv, 0x418894, 0x00000000); - nv_wr32(priv, 0x4188b4, priv->unk4188b4->addr >> 8); - nv_wr32(priv, 0x4188b8, priv->unk4188b8->addr >> 8); - nv_mask(priv, 0x4188b0, 0x00040000, 0x00040000); + tmp = nv_rd32(gr, 0x100c80); /*XXX: mask? */ + nv_wr32(gr, 0x418880, 0x00001000 | (tmp & 0x00000fff)); + nv_wr32(gr, 0x418890, 0x00000000); + nv_wr32(gr, 0x418894, 0x00000000); + nv_wr32(gr, 0x4188b4, gr->unk4188b4->addr >> 8); + nv_wr32(gr, 0x4188b8, gr->unk4188b8->addr >> 8); + nv_mask(gr, 0x4188b0, 0x00040000, 0x00040000); /*XXX: belongs in fb */ - nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8); - nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8); - nv_mask(priv, 0x100cc4, 0x00040000, 0x00040000); + nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8); + nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8); + nv_mask(gr, 0x100cc4, 0x00040000, 0x00040000); - gf100_gr_mmio(priv, oclass->mmio); + gf100_gr_mmio(gr, oclass->mmio); - gm107_gr_init_bios(priv); + gm107_gr_init_bios(gr); - nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); + nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); - memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); - for (i = 0, gpc = -1; i < priv->tpc_total; i++) { + memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); + for (i = 0, gpc = -1; i < gr->tpc_total; i++) { do { - gpc = (gpc + 1) % priv->gpc_nr; + gpc = (gpc + 1) % gr->gpc_nr; } while (!tpcnr[gpc]); - tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; + tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--; data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(priv, GPC_BCAST(0x0980), data[0]); - nv_wr32(priv, GPC_BCAST(0x0984), data[1]); - nv_wr32(priv, GPC_BCAST(0x0988), data[2]); - nv_wr32(priv, GPC_BCAST(0x098c), data[3]); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - nv_wr32(priv, GPC_UNIT(gpc, 0x0914), - priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); - nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | - priv->tpc_total); - nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x0980), data[0]); + nv_wr32(gr, GPC_BCAST(0x0984), data[1]); + nv_wr32(gr, GPC_BCAST(0x0988), data[2]); + nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); - nv_wr32(priv, GPC_BCAST(0x033c), nv_rd32(priv, 0x100804)); - - nv_wr32(priv, 0x400500, 0x00010001); - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - nv_wr32(priv, 0x400124, 0x00000002); - nv_wr32(priv, 0x409c24, 0x000e0000); - nv_wr32(priv, 0x405848, 0xc0000000); - nv_wr32(priv, 0x40584c, 0x00000001); - nv_wr32(priv, 0x404000, 0xc0000000); - nv_wr32(priv, 0x404600, 0xc0000000); - nv_wr32(priv, 0x408030, 0xc0000000); - nv_wr32(priv, 0x404490, 0xc0000000); - nv_wr32(priv, 0x406018, 0xc0000000); - nv_wr32(priv, 0x407020, 0x40000000); - nv_wr32(priv, 0x405840, 0xc0000000); - nv_wr32(priv, 0x405844, 0x00ffffff); - nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); - - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { - for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) - nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); - for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); - nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); + nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); + nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + nv_wr32(gr, GPC_BCAST(0x033c), nv_rd32(gr, 0x100804)); + + nv_wr32(gr, 0x400500, 0x00010001); + nv_wr32(gr, 0x400100, 0xffffffff); + nv_wr32(gr, 0x40013c, 0xffffffff); + nv_wr32(gr, 0x400124, 0x00000002); + nv_wr32(gr, 0x409c24, 0x000e0000); + nv_wr32(gr, 0x405848, 0xc0000000); + nv_wr32(gr, 0x40584c, 0x00000001); + nv_wr32(gr, 0x404000, 0xc0000000); + nv_wr32(gr, 0x404600, 0xc0000000); + nv_wr32(gr, 0x408030, 0xc0000000); + nv_wr32(gr, 0x404490, 0xc0000000); + nv_wr32(gr, 0x406018, 0xc0000000); + nv_wr32(gr, 0x407020, 0x40000000); + nv_wr32(gr, 0x405840, 0xc0000000); + nv_wr32(gr, 0x405844, 0x00ffffff); + nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) + nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); + nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } - nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } - for (rop = 0; rop < priv->rop_nr; rop++) { - nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); - nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); - nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); + for (rop = 0; rop < gr->rop_nr; rop++) { + nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000); + nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000); + nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); + nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400118, 0xffffffff); - nv_wr32(priv, 0x400130, 0xffffffff); - nv_wr32(priv, 0x40011c, 0xffffffff); - nv_wr32(priv, 0x400134, 0xffffffff); + nv_wr32(gr, 0x400108, 0xffffffff); + nv_wr32(gr, 0x400138, 0xffffffff); + nv_wr32(gr, 0x400118, 0xffffffff); + nv_wr32(gr, 0x400130, 0xffffffff); + nv_wr32(gr, 0x40011c, 0xffffffff); + nv_wr32(gr, 0x400134, 0xffffffff); - nv_wr32(priv, 0x400054, 0x2c350f63); + nv_wr32(gr, 0x400054, 0x2c350f63); - gf100_gr_zbc_init(priv); + gf100_gr_zbc_init(gr); - return gm204_gr_init_ctxctl(priv); + return gm204_gr_init_ctxctl(gr); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 897628062d58..6b9c84f8f12d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -35,34 +35,34 @@ gm20b_gr_sclass[] = { }; static void -gm20b_gr_init_gpc_mmu(struct gf100_gr_priv *priv) +gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) { u32 val; /* TODO this needs to be removed once secure boot works */ if (1) { - nv_wr32(priv, 0x100ce4, 0xffffffff); + nv_wr32(gr, 0x100ce4, 0xffffffff); } /* TODO update once secure boot works */ - val = nv_rd32(priv, 0x100c80); + val = nv_rd32(gr, 0x100c80); val &= 0xf000087f; - nv_wr32(priv, 0x418880, val); - nv_wr32(priv, 0x418890, 0); - nv_wr32(priv, 0x418894, 0); + nv_wr32(gr, 0x418880, val); + nv_wr32(gr, 0x418890, 0); + nv_wr32(gr, 0x418894, 0); - nv_wr32(priv, 0x4188b0, nv_rd32(priv, 0x100cc4)); - nv_wr32(priv, 0x4188b4, nv_rd32(priv, 0x100cc8)); - nv_wr32(priv, 0x4188b8, nv_rd32(priv, 0x100ccc)); + nv_wr32(gr, 0x4188b0, nv_rd32(gr, 0x100cc4)); + nv_wr32(gr, 0x4188b4, nv_rd32(gr, 0x100cc8)); + nv_wr32(gr, 0x4188b8, nv_rd32(gr, 0x100ccc)); - nv_wr32(priv, 0x4188ac, nv_rd32(priv, 0x100800)); + nv_wr32(gr, 0x4188ac, nv_rd32(gr, 0x100800)); } static void -gm20b_gr_set_hww_esr_report_mask(struct gf100_gr_priv *priv) +gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { - nv_wr32(priv, 0x419e44, 0xdffffe); - nv_wr32(priv, 0x419e4c, 0x5); + nv_wr32(gr, 0x419e44, 0xdffffe); + nv_wr32(gr, 0x419e4c, 0x5); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 81abe6fb3872..e161abe88fb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -345,7 +345,7 @@ nv04_gr_ctx_regs[] = { NV04_PGRAPH_DEBUG_3 }; -struct nv04_gr_priv { +struct nv04_gr { struct nvkm_gr base; struct nv04_gr_chan *chan[16]; spinlock_t lock; @@ -358,8 +358,8 @@ struct nv04_gr_chan { }; -static inline struct nv04_gr_priv * -nv04_gr_priv(struct nv04_gr_chan *chan) +static inline struct nv04_gr * +nv04_gr(struct nv04_gr_chan *chan) { return (void *)nv_object(chan)->engine; } @@ -445,8 +445,8 @@ nv04_gr_priv(struct nv04_gr_chan *chan) static void nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value) { - struct nv04_gr_priv *priv = (void *)object->engine; - int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; + struct nv04_gr *gr = (void *)object->engine; + int subc = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; u32 tmp; tmp = nv_ro32(object, 0x00); @@ -454,8 +454,8 @@ nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value) tmp |= value; nv_wo32(object, 0x00, tmp); - nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp); - nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); + nv_wr32(gr, NV04_PGRAPH_CTX_SWITCH1, tmp); + nv_wr32(gr, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); } static void @@ -527,7 +527,7 @@ static int nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr *gr = (void *)object->engine; u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; @@ -539,8 +539,8 @@ nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, w |= 0xffff0000; max = min + w; max &= 0x3ffff; - nv_wr32(priv, 0x40053c, min); - nv_wr32(priv, 0x400544, max); + nv_wr32(gr, 0x40053c, min); + nv_wr32(gr, 0x400544, max); return 0; } @@ -548,7 +548,7 @@ static int nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, void *args, u32 size) { - struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr *gr = (void *)object->engine; u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; @@ -560,8 +560,8 @@ nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, w |= 0xffff0000; max = min + w; max &= 0x3ffff; - nv_wr32(priv, 0x400540, min); - nv_wr32(priv, 0x400548, max); + nv_wr32(gr, 0x400540, min); + nv_wr32(gr, 0x400548, max); return 0; } @@ -1031,13 +1031,13 @@ nv04_gr_sclass[] = { ******************************************************************************/ static struct nv04_gr_chan * -nv04_gr_channel(struct nv04_gr_priv *priv) +nv04_gr_channel(struct nv04_gr *gr) { struct nv04_gr_chan *chan = NULL; - if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { - int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; - if (chid < ARRAY_SIZE(priv->chan)) - chan = priv->chan[chid]; + if (nv_rd32(gr, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { + int chid = nv_rd32(gr, NV04_PGRAPH_CTX_USER) >> 24; + if (chid < ARRAY_SIZE(gr->chan)) + chan = gr->chan[chid]; } return chan; } @@ -1045,55 +1045,55 @@ nv04_gr_channel(struct nv04_gr_priv *priv) static int nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) { - struct nv04_gr_priv *priv = nv04_gr_priv(chan); + struct nv04_gr *gr = nv04_gr(chan); int i; for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) - nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]); + nv_wr32(gr, nv04_gr_ctx_regs[i], chan->nv04[i]); - nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100); - nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); - nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); + nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10010100); + nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); + nv_mask(gr, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); return 0; } static int nv04_gr_unload_context(struct nv04_gr_chan *chan) { - struct nv04_gr_priv *priv = nv04_gr_priv(chan); + struct nv04_gr *gr = nv04_gr(chan); int i; for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) - chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]); + chan->nv04[i] = nv_rd32(gr, nv04_gr_ctx_regs[i]); - nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000); - nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10000000); + nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); return 0; } static void -nv04_gr_context_switch(struct nv04_gr_priv *priv) +nv04_gr_context_switch(struct nv04_gr *gr) { struct nv04_gr_chan *prev = NULL; struct nv04_gr_chan *next = NULL; unsigned long flags; int chid; - spin_lock_irqsave(&priv->lock, flags); - nv04_gr_idle(priv); + spin_lock_irqsave(&gr->lock, flags); + nv04_gr_idle(gr); /* If previous context is valid, we need to save it */ - prev = nv04_gr_channel(priv); + prev = nv04_gr_channel(gr); if (prev) nv04_gr_unload_context(prev); /* load context for next channel */ - chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; - next = priv->chan[chid]; + chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; + next = gr->chan[chid]; if (next) nv04_gr_load_context(next, chid); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); } static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) @@ -1115,7 +1115,7 @@ nv04_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object **pobject) { struct nvkm_fifo_chan *fifo = (void *)parent; - struct nv04_gr_priv *priv = (void *)engine; + struct nv04_gr *gr = (void *)engine; struct nv04_gr_chan *chan; unsigned long flags; int ret; @@ -1125,33 +1125,33 @@ nv04_gr_context_ctor(struct nvkm_object *parent, if (ret) return ret; - spin_lock_irqsave(&priv->lock, flags); - if (priv->chan[fifo->chid]) { - *pobject = nv_object(priv->chan[fifo->chid]); + spin_lock_irqsave(&gr->lock, flags); + if (gr->chan[fifo->chid]) { + *pobject = nv_object(gr->chan[fifo->chid]); atomic_inc(&(*pobject)->refcount); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); nvkm_object_destroy(&chan->base); return 1; } *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; - priv->chan[fifo->chid] = chan; + gr->chan[fifo->chid] = chan; chan->chid = fifo->chid; - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); return 0; } static void nv04_gr_context_dtor(struct nvkm_object *object) { - struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr *gr = (void *)object->engine; struct nv04_gr_chan *chan = (void *)object; unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); - priv->chan[chan->chid] = NULL; - spin_unlock_irqrestore(&priv->lock, flags); + spin_lock_irqsave(&gr->lock, flags); + gr->chan[chan->chid] = NULL; + spin_unlock_irqrestore(&gr->lock, flags); nvkm_object_destroy(&chan->base); } @@ -1159,16 +1159,16 @@ nv04_gr_context_dtor(struct nvkm_object *object) static int nv04_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv04_gr_priv *priv = (void *)object->engine; + struct nv04_gr *gr = (void *)object->engine; struct nv04_gr_chan *chan = (void *)object; unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv04_gr_channel(priv) == chan) + spin_lock_irqsave(&gr->lock, flags); + nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + if (nv04_gr_channel(gr) == chan) nv04_gr_unload_context(chan); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->lock, flags); + nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&gr->lock, flags); return nvkm_object_fini(&chan->base, suspend); } @@ -1248,28 +1248,28 @@ nv04_gr_nsource[] = { static void nv04_gr_intr(struct nvkm_subdev *subdev) { - struct nv04_gr_priv *priv = (void *)subdev; + struct nv04_gr *gr = (void *)subdev; struct nv04_gr_chan *chan = NULL; struct nvkm_namedb *namedb = NULL; struct nvkm_handle *handle = NULL; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); + u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); u32 chid = (addr & 0x0f000000) >> 24; u32 subc = (addr & 0x0000e000) >> 13; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff; - u32 inst = (nv_rd32(priv, 0x40016c) & 0xffff) << 4; + u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(gr, 0x400180 + subc * 4) & 0xff; + u32 inst = (nv_rd32(gr, 0x40016c) & 0xffff) << 4; u32 show = stat; unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); - chan = priv->chan[chid]; + spin_lock_irqsave(&gr->lock, flags); + chan = gr->chan[chid]; if (chan) namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); if (stat & NV_PGRAPH_INTR_NOTIFY) { if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { @@ -1280,24 +1280,24 @@ nv04_gr_intr(struct nvkm_subdev *subdev) } if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); + nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - nv04_gr_context_switch(priv); + nv04_gr_context_switch(gr); } - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + nv_wr32(gr, NV03_PGRAPH_INTR, stat); + nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(priv, "%s", ""); + nv_error(gr, "%s", ""); nvkm_bitfield_print(nv04_gr_intr_name, show); pr_cont(" nsource:"); nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); nvkm_bitfield_print(nv04_gr_nstatus, nstatus); pr_cont("\n"); - nv_error(priv, + nv_error(gr, "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, nvkm_client_name(chan), subc, class, mthd, data); @@ -1311,19 +1311,19 @@ nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_gr_priv *priv; + struct nv04_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv04_gr_intr; - nv_engine(priv)->cclass = &nv04_gr_cclass; - nv_engine(priv)->sclass = nv04_gr_sclass; - spin_lock_init(&priv->lock); + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv04_gr_intr; + nv_engine(gr)->cclass = &nv04_gr_cclass; + nv_engine(gr)->sclass = nv04_gr_sclass; + spin_lock_init(&gr->lock); return 0; } @@ -1331,41 +1331,41 @@ static int nv04_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nv04_gr_priv *priv = (void *)engine; + struct nv04_gr *gr = (void *)engine; int ret; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; /* Enable PGRAPH interrupts */ - nv_wr32(priv, NV03_PGRAPH_INTR, 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_VALID1, 0); - nv_wr32(priv, NV04_PGRAPH_VALID2, 0); - /*nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x000001FF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x1231c000); + nv_wr32(gr, NV03_PGRAPH_INTR, 0xFFFFFFFF); + nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(gr, NV04_PGRAPH_VALID1, 0); + nv_wr32(gr, NV04_PGRAPH_VALID2, 0); + /*nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x000001FF); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x1231c000); /*1231C000 blob, 001 haiku*/ /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x72111100); + nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x72111100); /*0x72111100 blob , 01 haiku*/ - /*nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f071); + /*nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ + nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f071); /*haiku same*/ - /*nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); + /*nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ + nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); /*haiku and blob 10d4*/ - nv_wr32(priv, NV04_PGRAPH_STATE , 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL , 0x10000100); - nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + nv_wr32(gr, NV04_PGRAPH_STATE , 0xFFFFFFFF); + nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL , 0x10000100); + nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); /* These don't belong here, they're part of a per-channel context */ - nv_wr32(priv, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); + nv_wr32(gr, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); + nv_wr32(gr, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 57f05c86a591..af33514456a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -385,7 +385,7 @@ static int nv17_gr_ctx_regs[] = { 0x00400a04, }; -struct nv10_gr_priv { +struct nv10_gr { struct nvkm_gr base; struct nv10_gr_chan *chan[32]; spinlock_t lock; @@ -401,8 +401,8 @@ struct nv10_gr_chan { }; -static inline struct nv10_gr_priv * -nv10_gr_priv(struct nv10_gr_chan *chan) +static inline struct nv10_gr * +nv10_gr(struct nv10_gr_chan *chan) { return (void *)nv_object(chan)->engine; } @@ -411,20 +411,20 @@ nv10_gr_priv(struct nv10_gr_chan *chan) * Graphics object classes ******************************************************************************/ -#define PIPE_SAVE(priv, state, addr) \ +#define PIPE_SAVE(gr, state, addr) \ do { \ int __i; \ - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, addr); \ for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ - state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \ + state[__i] = nv_rd32(gr, NV10_PGRAPH_PIPE_DATA); \ } while (0) -#define PIPE_RESTORE(priv, state, addr) \ +#define PIPE_RESTORE(gr, state, addr) \ do { \ int __i; \ - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, addr); \ for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \ + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, state[__i]); \ } while (0) static struct nvkm_oclass @@ -478,7 +478,7 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, void *args, u32 size) { struct nv10_gr_chan *chan = (void *)object->parent; - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe = &chan->pipe_state; u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; u32 xfmode0, xfmode1; @@ -490,62 +490,62 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, if (mthd != 0x1644) return 0; - nv04_gr_idle(priv); + nv04_gr_idle(gr); - PIPE_SAVE(priv, pipe_0x0040, 0x0040); - PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); + PIPE_SAVE(gr, pipe_0x0040, 0x0040); + PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); - PIPE_RESTORE(priv, chan->lma_window, 0x6790); + PIPE_RESTORE(gr, chan->lma_window, 0x6790); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); - xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); + xfmode0 = nv_rd32(gr, NV10_PGRAPH_XFMODE0); + xfmode1 = nv_rd32(gr, NV10_PGRAPH_XFMODE1); - PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); - PIPE_SAVE(priv, pipe_0x64c0, 0x64c0); - PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0); - PIPE_SAVE(priv, pipe_0x6a80, 0x6a80); + PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); + PIPE_SAVE(gr, pipe_0x64c0, 0x64c0); + PIPE_SAVE(gr, pipe_0x6ab0, 0x6ab0); + PIPE_SAVE(gr, pipe_0x6a80, 0x6a80); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + nv_wr32(gr, NV10_PGRAPH_XFMODE0, 0x10000000); + nv_wr32(gr, NV10_PGRAPH_XFMODE1, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000008); - PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); + PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - PIPE_RESTORE(priv, pipe_0x0040, 0x0040); + PIPE_RESTORE(gr, pipe_0x0040, 0x0040); - nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); + nv_wr32(gr, NV10_PGRAPH_XFMODE0, xfmode0); + nv_wr32(gr, NV10_PGRAPH_XFMODE1, xfmode1); - PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0); - PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0); - PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80); - PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); + PIPE_RESTORE(gr, pipe_0x64c0, 0x64c0); + PIPE_RESTORE(gr, pipe_0x6ab0, 0x6ab0); + PIPE_RESTORE(gr, pipe_0x6a80, 0x6a80); + PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv04_gr_idle(priv); + nv04_gr_idle(gr); return 0; } @@ -555,12 +555,12 @@ nv17_gr_mthd_lma_enable(struct nvkm_object *object, u32 mthd, void *args, u32 size) { struct nv10_gr_chan *chan = (void *)object->parent; - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); - nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000); + nv_mask(gr, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); + nv_mask(gr, 0x4006b0, 0x08000000, 0x08000000); return 0; } @@ -602,13 +602,13 @@ nv17_gr_sclass[] = { ******************************************************************************/ static struct nv10_gr_chan * -nv10_gr_channel(struct nv10_gr_priv *priv) +nv10_gr_channel(struct nv10_gr *gr) { struct nv10_gr_chan *chan = NULL; - if (nv_rd32(priv, 0x400144) & 0x00010000) { - int chid = nv_rd32(priv, 0x400148) >> 24; - if (chid < ARRAY_SIZE(priv->chan)) - chan = priv->chan[chid]; + if (nv_rd32(gr, 0x400144) & 0x00010000) { + int chid = nv_rd32(gr, 0x400148) >> 24; + if (chid < ARRAY_SIZE(gr->chan)) + chan = gr->chan[chid]; } return chan; } @@ -616,75 +616,75 @@ nv10_gr_channel(struct nv10_gr_priv *priv) static void nv10_gr_save_pipe(struct nv10_gr_chan *chan) { - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe = &chan->pipe_state; - PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); - PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); - PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400); - PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800); - PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00); - PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000); - PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400); - PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800); - PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040); - PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000); + PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); + PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); + PIPE_SAVE(gr, pipe->pipe_0x6400, 0x6400); + PIPE_SAVE(gr, pipe->pipe_0x6800, 0x6800); + PIPE_SAVE(gr, pipe->pipe_0x6c00, 0x6c00); + PIPE_SAVE(gr, pipe->pipe_0x7000, 0x7000); + PIPE_SAVE(gr, pipe->pipe_0x7400, 0x7400); + PIPE_SAVE(gr, pipe->pipe_0x7800, 0x7800); + PIPE_SAVE(gr, pipe->pipe_0x0040, 0x0040); + PIPE_SAVE(gr, pipe->pipe_0x0000, 0x0000); } static void nv10_gr_load_pipe(struct nv10_gr_chan *chan) { - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe = &chan->pipe_state; u32 xfmode0, xfmode1; int i; - nv04_gr_idle(priv); + nv04_gr_idle(gr); /* XXX check haiku comments */ - xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); - xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); - nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + xfmode0 = nv_rd32(gr, NV10_PGRAPH_XFMODE0); + xfmode1 = nv_rd32(gr, NV10_PGRAPH_XFMODE1); + nv_wr32(gr, NV10_PGRAPH_XFMODE0, 0x10000000); + nv_wr32(gr, NV10_PGRAPH_XFMODE1, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); + nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000008); - PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); - nv04_gr_idle(priv); + PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); + nv04_gr_idle(gr); /* restore XFMODE */ - nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); - nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); - PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400); - PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800); - PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00); - PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000); - PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400); - PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800); - PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); - PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000); - PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040); - nv04_gr_idle(priv); + nv_wr32(gr, NV10_PGRAPH_XFMODE0, xfmode0); + nv_wr32(gr, NV10_PGRAPH_XFMODE1, xfmode1); + PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400); + PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800); + PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00); + PIPE_RESTORE(gr, pipe->pipe_0x7000, 0x7000); + PIPE_RESTORE(gr, pipe->pipe_0x7400, 0x7400); + PIPE_RESTORE(gr, pipe->pipe_0x7800, 0x7800); + PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); + PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000); + PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040); + nv04_gr_idle(gr); } static void nv10_gr_create_pipe(struct nv10_gr_chan *chan) { - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe_state = &chan->pipe_state; u32 *pipe_state_addr; int i; @@ -697,7 +697,7 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan) u32 *__end_addr = pipe_state->pipe_##addr + \ ARRAY_SIZE(pipe_state->pipe_##addr); \ if (pipe_state_addr != __end_addr) \ - nv_error(priv, "incomplete pipe init for 0x%x : %p/%p\n", \ + nv_error(gr, "incomplete pipe init for 0x%x : %p/%p\n", \ addr, pipe_state_addr, __end_addr); \ } while (0) #define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value @@ -837,33 +837,33 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan) } static int -nv10_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg) +nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) { int i; for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) { if (nv10_gr_ctx_regs[i] == reg) return i; } - nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg); + nv_error(gr, "unknow offset nv10_ctx_regs %d\n", reg); return -1; } static int -nv17_gr_ctx_regs_find_offset(struct nv10_gr_priv *priv, int reg) +nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) { int i; for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) { if (nv17_gr_ctx_regs[i] == reg) return i; } - nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg); + nv_error(gr, "unknow offset nv17_ctx_regs %d\n", reg); return -1; } static void nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) { - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; u32 ctx_user, ctx_switch[5]; int i, subchan = -1; @@ -875,7 +875,7 @@ nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) /* Look for a celsius object */ for (i = 0; i < 8; i++) { - int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; + int class = nv_rd32(gr, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; if (class == 0x56 || class == 0x96 || class == 0x99) { subchan = i; @@ -887,131 +887,131 @@ nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) return; /* Save the current ctx object */ - ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER); + ctx_user = nv_rd32(gr, NV10_PGRAPH_CTX_USER); for (i = 0; i < 5; i++) - ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i)); + ctx_switch[i] = nv_rd32(gr, NV10_PGRAPH_CTX_SWITCH(i)); /* Save the FIFO state */ - st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2); - st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL); - st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH); - fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR); + st2 = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2); + st2_dl = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2_DL); + st2_dh = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2_DH); + fifo_ptr = nv_rd32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR); for (i = 0; i < ARRAY_SIZE(fifo); i++) - fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i); + fifo[i] = nv_rd32(gr, 0x4007a0 + 4 * i); /* Switch to the celsius subchannel */ for (i = 0; i < 5; i++) - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), - nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i))); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(i), + nv_rd32(gr, NV10_PGRAPH_CTX_CACHE(subchan, i))); + nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); /* Inject NV10TCL_DMA_VTXBUF */ - nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, + nv_wr32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst); - nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DL, inst); + nv_mask(gr, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); + nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); /* Restore the FIFO state */ for (i = 0; i < ARRAY_SIZE(fifo); i++) - nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]); + nv_wr32(gr, 0x4007a0 + 4 * i, fifo[i]); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, st2); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); /* Restore the current ctx object */ for (i = 0; i < 5; i++) - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); - nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); + nv_wr32(gr, NV10_PGRAPH_CTX_USER, ctx_user); } static int nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) { - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); u32 inst; int i; for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) - nv_wr32(priv, nv10_gr_ctx_regs[i], chan->nv10[i]); + nv_wr32(gr, nv10_gr_ctx_regs[i], chan->nv10[i]); - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { + if (nv_device(gr)->card_type >= NV_11 && + nv_device(gr)->chipset >= 0x17) { for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) - nv_wr32(priv, nv17_gr_ctx_regs[i], chan->nv17[i]); + nv_wr32(gr, nv17_gr_ctx_regs[i], chan->nv17[i]); } nv10_gr_load_pipe(chan); - inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; + inst = nv_rd32(gr, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; nv10_gr_load_dma_vtxbuf(chan, chid, inst); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); - nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10010100); + nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); + nv_mask(gr, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); return 0; } static int nv10_gr_unload_context(struct nv10_gr_chan *chan) { - struct nv10_gr_priv *priv = nv10_gr_priv(chan); + struct nv10_gr *gr = nv10_gr(chan); int i; for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) - chan->nv10[i] = nv_rd32(priv, nv10_gr_ctx_regs[i]); + chan->nv10[i] = nv_rd32(gr, nv10_gr_ctx_regs[i]); - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { + if (nv_device(gr)->card_type >= NV_11 && + nv_device(gr)->chipset >= 0x17) { for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) - chan->nv17[i] = nv_rd32(priv, nv17_gr_ctx_regs[i]); + chan->nv17[i] = nv_rd32(gr, nv17_gr_ctx_regs[i]); } nv10_gr_save_pipe(chan); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); + nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000000); + nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); return 0; } static void -nv10_gr_context_switch(struct nv10_gr_priv *priv) +nv10_gr_context_switch(struct nv10_gr *gr) { struct nv10_gr_chan *prev = NULL; struct nv10_gr_chan *next = NULL; unsigned long flags; int chid; - spin_lock_irqsave(&priv->lock, flags); - nv04_gr_idle(priv); + spin_lock_irqsave(&gr->lock, flags); + nv04_gr_idle(gr); /* If previous context is valid, we need to save it */ - prev = nv10_gr_channel(priv); + prev = nv10_gr_channel(gr); if (prev) nv10_gr_unload_context(prev); /* load context for next channel */ - chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; - next = priv->chan[chid]; + chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; + next = gr->chan[chid]; if (next) nv10_gr_load_context(next, chid); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); } #define NV_WRITE_CTX(reg, val) do { \ - int offset = nv10_gr_ctx_regs_find_offset(priv, reg); \ + int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \ if (offset > 0) \ chan->nv10[offset] = val; \ } while (0) #define NV17_WRITE_CTX(reg, val) do { \ - int offset = nv17_gr_ctx_regs_find_offset(priv, reg); \ + int offset = nv17_gr_ctx_regs_find_offset(gr, reg); \ if (offset > 0) \ chan->nv17[offset] = val; \ } while (0) @@ -1022,7 +1022,7 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_fifo_chan *fifo = (void *)parent; - struct nv10_gr_priv *priv = (void *)engine; + struct nv10_gr *gr = (void *)engine; struct nv10_gr_chan *chan; unsigned long flags; int ret; @@ -1032,11 +1032,11 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - spin_lock_irqsave(&priv->lock, flags); - if (priv->chan[fifo->chid]) { - *pobject = nv_object(priv->chan[fifo->chid]); + spin_lock_irqsave(&gr->lock, flags); + if (gr->chan[fifo->chid]) { + *pobject = nv_object(gr->chan[fifo->chid]); atomic_inc(&(*pobject)->refcount); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); nvkm_object_destroy(&chan->base); return 1; } @@ -1048,12 +1048,12 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, NV_WRITE_CTX(0x00400e14, 0x00001000); NV_WRITE_CTX(0x00400e30, 0x00080008); NV_WRITE_CTX(0x00400e34, 0x00080008); - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { + if (nv_device(gr)->card_type >= NV_11 && + nv_device(gr)->chipset >= 0x17) { /* is it really needed ??? */ NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, - nv_rd32(priv, NV10_PGRAPH_DEBUG_4)); - NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0)); + nv_rd32(gr, NV10_PGRAPH_DEBUG_4)); + NV17_WRITE_CTX(0x004006b0, nv_rd32(gr, 0x004006b0)); NV17_WRITE_CTX(0x00400eac, 0x0fff0000); NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); NV17_WRITE_CTX(0x00400ec0, 0x00000080); @@ -1063,22 +1063,22 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_gr_create_pipe(chan); - priv->chan[fifo->chid] = chan; + gr->chan[fifo->chid] = chan; chan->chid = fifo->chid; - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); return 0; } static void nv10_gr_context_dtor(struct nvkm_object *object) { - struct nv10_gr_priv *priv = (void *)object->engine; + struct nv10_gr *gr = (void *)object->engine; struct nv10_gr_chan *chan = (void *)object; unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); - priv->chan[chan->chid] = NULL; - spin_unlock_irqrestore(&priv->lock, flags); + spin_lock_irqsave(&gr->lock, flags); + gr->chan[chan->chid] = NULL; + spin_unlock_irqrestore(&gr->lock, flags); nvkm_object_destroy(&chan->base); } @@ -1086,16 +1086,16 @@ nv10_gr_context_dtor(struct nvkm_object *object) static int nv10_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv10_gr_priv *priv = (void *)object->engine; + struct nv10_gr *gr = (void *)object->engine; struct nv10_gr_chan *chan = (void *)object; unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv10_gr_channel(priv) == chan) + spin_lock_irqsave(&gr->lock, flags); + nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + if (nv10_gr_channel(gr) == chan) nv10_gr_unload_context(chan); - nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->lock, flags); + nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&gr->lock, flags); return nvkm_object_fini(&chan->base, suspend); } @@ -1120,15 +1120,15 @@ nv10_gr_tile_prog(struct nvkm_engine *engine, int i) { struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; struct nvkm_fifo *fifo = nvkm_fifo(engine); - struct nv10_gr_priv *priv = (void *)engine; + struct nv10_gr *gr = (void *)engine; unsigned long flags; fifo->pause(fifo, &flags); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr); + nv_wr32(gr, NV10_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(gr, NV10_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(gr, NV10_PGRAPH_TILE(i), tile->addr); fifo->start(fifo, &flags); } @@ -1150,27 +1150,27 @@ const struct nvkm_bitfield nv10_gr_nstatus[] = { static void nv10_gr_intr(struct nvkm_subdev *subdev) { - struct nv10_gr_priv *priv = (void *)subdev; + struct nv10_gr *gr = (void *)subdev; struct nv10_gr_chan *chan = NULL; struct nvkm_namedb *namedb = NULL; struct nvkm_handle *handle = NULL; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); + u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); u32 chid = (addr & 0x01f00000) >> 20; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; + u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xfff; u32 show = stat; unsigned long flags; - spin_lock_irqsave(&priv->lock, flags); - chan = priv->chan[chid]; + spin_lock_irqsave(&gr->lock, flags); + chan = gr->chan[chid]; if (chan) namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); - spin_unlock_irqrestore(&priv->lock, flags); + spin_unlock_irqrestore(&gr->lock, flags); if (stat & NV_PGRAPH_INTR_ERROR) { if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { @@ -1181,24 +1181,24 @@ nv10_gr_intr(struct nvkm_subdev *subdev) } if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); + nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - nv10_gr_context_switch(priv); + nv10_gr_context_switch(gr); } - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + nv_wr32(gr, NV03_PGRAPH_INTR, stat); + nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(priv, "%s", ""); + nv_error(gr, "%s", ""); nvkm_bitfield_print(nv10_gr_intr_name, show); pr_cont(" nsource:"); nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); nvkm_bitfield_print(nv10_gr_nstatus, nstatus); pr_cont("\n"); - nv_error(priv, + nv_error(gr, "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, nvkm_client_name(chan), subc, class, mthd, data); @@ -1212,37 +1212,37 @@ nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv10_gr_priv *priv; + struct nv10_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv10_gr_intr; - nv_engine(priv)->cclass = &nv10_gr_cclass; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv10_gr_intr; + nv_engine(gr)->cclass = &nv10_gr_cclass; - if (nv_device(priv)->chipset <= 0x10) - nv_engine(priv)->sclass = nv10_gr_sclass; + if (nv_device(gr)->chipset <= 0x10) + nv_engine(gr)->sclass = nv10_gr_sclass; else - if (nv_device(priv)->chipset < 0x17 || - nv_device(priv)->card_type < NV_11) - nv_engine(priv)->sclass = nv15_gr_sclass; + if (nv_device(gr)->chipset < 0x17 || + nv_device(gr)->card_type < NV_11) + nv_engine(gr)->sclass = nv15_gr_sclass; else - nv_engine(priv)->sclass = nv17_gr_sclass; + nv_engine(gr)->sclass = nv17_gr_sclass; - nv_engine(priv)->tile_prog = nv10_gr_tile_prog; - spin_lock_init(&priv->lock); + nv_engine(gr)->tile_prog = nv10_gr_tile_prog; + spin_lock_init(&gr->lock); return 0; } static void nv10_gr_dtor(struct nvkm_object *object) { - struct nv10_gr_priv *priv = (void *)object; - nvkm_gr_destroy(&priv->base); + struct nv10_gr *gr = (void *)object; + nvkm_gr_destroy(&gr->base); } static int @@ -1250,56 +1250,56 @@ nv10_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nvkm_fb *fb = nvkm_fb(object); - struct nv10_gr_priv *priv = (void *)engine; + struct nv10_gr *gr = (void *)engine; int ret, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); - /* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ - nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); - - if (nv_device(priv)->card_type >= NV_11 && - nv_device(priv)->chipset >= 0x17) { - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000); - nv_wr32(priv, 0x400a10, 0x03ff3fb6); - nv_wr32(priv, 0x400838, 0x002f8684); - nv_wr32(priv, 0x40083c, 0x00115f3f); - nv_wr32(priv, 0x4006b0, 0x40000020); + nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x00118700); + /* nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ + nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); + nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); + + if (nv_device(gr)->card_type >= NV_11 && + nv_device(gr)->chipset >= 0x17) { + nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x1f000000); + nv_wr32(gr, 0x400a10, 0x03ff3fb6); + nv_wr32(gr, 0x400838, 0x002f8684); + nv_wr32(gr, 0x40083c, 0x00115f3f); + nv_wr32(gr, 0x4006b0, 0x40000020); } else { - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00000000); } /* Turn all the tiling regions off. */ for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); - nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); + nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); + nv_wr32(gr, NV10_PGRAPH_STATE, 0xFFFFFFFF); - nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); + nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); + nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); return 0; } static int nv10_gr_fini(struct nvkm_object *object, bool suspend) { - struct nv10_gr_priv *priv = (void *)object; - return nvkm_gr_fini(&priv->base, suspend); + struct nv10_gr *gr = (void *)object; + return nvkm_gr_fini(&gr->base, suspend); } struct nvkm_oclass diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 14a83f2a8127..3e5428552cb2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -101,7 +101,7 @@ nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, int nv20_gr_context_init(struct nvkm_object *object) { - struct nv20_gr_priv *priv = (void *)object->engine; + struct nv20_gr *gr = (void *)object->engine; struct nv20_gr_chan *chan = (void *)object; int ret; @@ -109,30 +109,30 @@ nv20_gr_context_init(struct nvkm_object *object) if (ret) return ret; - nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); + nv_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); return 0; } int nv20_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv20_gr_priv *priv = (void *)object->engine; + struct nv20_gr *gr = (void *)object->engine; struct nv20_gr_chan *chan = (void *)object; int chid = -1; - nv_mask(priv, 0x400720, 0x00000001, 0x00000000); - if (nv_rd32(priv, 0x400144) & 0x00010000) - chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; + nv_mask(gr, 0x400720, 0x00000001, 0x00000000); + if (nv_rd32(gr, 0x400144) & 0x00010000) + chid = (nv_rd32(gr, 0x400148) & 0x1f000000) >> 24; if (chan->chid == chid) { - nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); - nv_wr32(priv, 0x400788, 0x00000002); - nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); - nv_wr32(priv, 0x400144, 0x10000000); - nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); + nv_wr32(gr, 0x400784, nv_gpuobj(chan)->addr >> 4); + nv_wr32(gr, 0x400788, 0x00000002); + nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); + nv_wr32(gr, 0x400144, 0x10000000); + nv_mask(gr, 0x400148, 0xff000000, 0x1f000000); } - nv_mask(priv, 0x400720, 0x00000001, 0x00000001); + nv_mask(gr, 0x400720, 0x00000001, 0x00000001); - nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); + nv_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); return nvkm_gr_context_fini(&chan->base, suspend); } @@ -158,27 +158,27 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) { struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; struct nvkm_fifo *fifo = nvkm_fifo(engine); - struct nv20_gr_priv *priv = (void *)engine; + struct nv20_gr *gr = (void *)engine; unsigned long flags; fifo->pause(fifo, &flags); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); + nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->limit); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->pitch); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->addr); if (nv_device(engine)->chipset != 0x34) { - nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); + nv_wr32(gr, NV20_PGRAPH_ZCOMP(i), tile->zcomp); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->zcomp); } fifo->start(fifo, &flags); @@ -190,16 +190,16 @@ nv20_gr_intr(struct nvkm_subdev *subdev) struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle; - struct nv20_gr_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + struct nv20_gr *gr = (void *)subdev; + u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); + u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); u32 chid = (addr & 0x01f00000) >> 20; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; + u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xfff; u32 show = stat; engctx = nvkm_engctx_get(engine, chid); @@ -212,18 +212,18 @@ nv20_gr_intr(struct nvkm_subdev *subdev) } } - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + nv_wr32(gr, NV03_PGRAPH_INTR, stat); + nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(priv, "%s", ""); + nv_error(gr, "%s", ""); nvkm_bitfield_print(nv10_gr_intr_name, show); pr_cont(" nsource:"); nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); nvkm_bitfield_print(nv10_gr_nstatus, nstatus); pr_cont("\n"); - nv_error(priv, + nv_error(gr, "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, nvkm_client_name(engctx), subc, class, mthd, data); @@ -237,129 +237,129 @@ nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv20_gr_priv *priv; + struct nv20_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_gr_intr; - nv_engine(priv)->cclass = &nv20_gr_cclass; - nv_engine(priv)->sclass = nv20_gr_sclass; - nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv20_gr_intr; + nv_engine(gr)->cclass = &nv20_gr_cclass; + nv_engine(gr)->sclass = nv20_gr_sclass; + nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } void nv20_gr_dtor(struct nvkm_object *object) { - struct nv20_gr_priv *priv = (void *)object; - nvkm_gpuobj_ref(NULL, &priv->ctxtab); - nvkm_gr_destroy(&priv->base); + struct nv20_gr *gr = (void *)object; + nvkm_gpuobj_ref(NULL, &gr->ctxtab); + nvkm_gr_destroy(&gr->base); } int nv20_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nv20_gr_priv *priv = (void *)engine; + struct nv20_gr *gr = (void *)engine; struct nvkm_fb *fb = nvkm_fb(object); u32 tmp, vramsz; int ret, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); + nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); - if (nv_device(priv)->chipset == 0x20) { - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000); + if (nv_device(gr)->chipset == 0x20) { + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x003d0000); for (i = 0; i < 15; i++) - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); - nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, 0x00000000); + nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); } else { - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x02c80000); for (i = 0; i < 32; i++) - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); - nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, 0x00000000); + nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); } - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); - nv_wr32(priv, 0x40009C , 0x00000040); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x00118700); + nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ + nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00000000); + nv_wr32(gr, 0x40009C , 0x00000040); - if (nv_device(priv)->chipset >= 0x25) { - nv_wr32(priv, 0x400890, 0x00a8cfff); - nv_wr32(priv, 0x400610, 0x304B1FB6); - nv_wr32(priv, 0x400B80, 0x1cbd3883); - nv_wr32(priv, 0x400B84, 0x44000000); - nv_wr32(priv, 0x400098, 0x40000080); - nv_wr32(priv, 0x400B88, 0x000000ff); + if (nv_device(gr)->chipset >= 0x25) { + nv_wr32(gr, 0x400890, 0x00a8cfff); + nv_wr32(gr, 0x400610, 0x304B1FB6); + nv_wr32(gr, 0x400B80, 0x1cbd3883); + nv_wr32(gr, 0x400B84, 0x44000000); + nv_wr32(gr, 0x400098, 0x40000080); + nv_wr32(gr, 0x400B88, 0x000000ff); } else { - nv_wr32(priv, 0x400880, 0x0008c7df); - nv_wr32(priv, 0x400094, 0x00000005); - nv_wr32(priv, 0x400B80, 0x45eae20e); - nv_wr32(priv, 0x400B84, 0x24000000); - nv_wr32(priv, 0x400098, 0x00000040); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); + nv_wr32(gr, 0x400880, 0x0008c7df); + nv_wr32(gr, 0x400094, 0x00000005); + nv_wr32(gr, 0x400B80, 0x45eae20e); + nv_wr32(gr, 0x400B84, 0x24000000); + nv_wr32(gr, 0x400098, 0x00000040); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00038); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000030); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E10038); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000030); } /* Turn all the tiling regions off. */ for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); - nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); + nv_wr32(gr, 0x4009a0, nv_rd32(gr, 0x100324)); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA, nv_rd32(gr, 0x100324)); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF); - tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00; - nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); - tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100; - nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); + tmp = nv_rd32(gr, NV10_PGRAPH_SURFACE) & 0x0007ff00; + nv_wr32(gr, NV10_PGRAPH_SURFACE, tmp); + tmp = nv_rd32(gr, NV10_PGRAPH_SURFACE) | 0x00020100; + nv_wr32(gr, NV10_PGRAPH_SURFACE, tmp); /* begin RAM config */ - vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; - nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200)); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x400820, 0); - nv_wr32(priv, 0x400824, 0); - nv_wr32(priv, 0x400864, vramsz - 1); - nv_wr32(priv, 0x400868, vramsz - 1); + vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; + nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204)); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , nv_rd32(gr, 0x100200)); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , nv_rd32(gr, 0x100204)); + nv_wr32(gr, 0x400820, 0); + nv_wr32(gr, 0x400824, 0); + nv_wr32(gr, 0x400864, vramsz - 1); + nv_wr32(gr, 0x400868, vramsz - 1); /* interesting.. the below overwrites some of the tile setup above.. */ - nv_wr32(priv, 0x400B20, 0x00000000); - nv_wr32(priv, 0x400B04, 0xFFFFFFFF); + nv_wr32(gr, 0x400B20, 0x00000000); + nv_wr32(gr, 0x400B04, 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); + nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); + nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); + nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); + nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index ac4dc048fed1..06dfe4bd50b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -2,7 +2,7 @@ #define __NV20_GR_H__ #include -struct nv20_gr_priv { +struct nv20_gr { struct nvkm_gr base; struct nvkm_gpuobj *ctxtab; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index bc362519cebb..50bad48a3eab 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -125,24 +125,24 @@ nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv20_gr_priv *priv; + struct nv20_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_gr_intr; - nv_engine(priv)->cclass = &nv25_gr_cclass; - nv_engine(priv)->sclass = nv25_gr_sclass; - nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv20_gr_intr; + nv_engine(gr)->cclass = &nv25_gr_cclass; + nv_engine(gr)->sclass = nv25_gr_sclass; + nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index 22a5096e283d..5c8ae50ee8e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -92,24 +92,24 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv20_gr_priv *priv; + struct nv20_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_gr_intr; - nv_engine(priv)->cclass = &nv2a_gr_cclass; - nv_engine(priv)->sclass = nv25_gr_sclass; - nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv20_gr_intr; + nv_engine(gr)->cclass = &nv2a_gr_cclass; + nv_engine(gr)->sclass = nv25_gr_sclass; + nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 0214e8a91dac..dea1cb907318 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -127,24 +127,24 @@ nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv20_gr_priv *priv; + struct nv20_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_gr_intr; - nv_engine(priv)->cclass = &nv30_gr_cclass; - nv_engine(priv)->sclass = nv30_gr_sclass; - nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv20_gr_intr; + nv_engine(gr)->cclass = &nv30_gr_cclass; + nv_engine(gr)->sclass = nv30_gr_sclass; + nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } @@ -152,68 +152,68 @@ int nv30_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nv20_gr_priv *priv = (void *)engine; + struct nv20_gr *gr = (void *)engine; struct nvkm_fb *fb = nvkm_fb(object); int ret, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); - - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); - nv_wr32(priv, 0x400890, 0x01b463ff); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475); - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); - nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); - nv_wr32(priv, 0x400B80, 0x1003d888); - nv_wr32(priv, 0x400B84, 0x0c000000); - nv_wr32(priv, 0x400098, 0x00000000); - nv_wr32(priv, 0x40009C, 0x0005ad00); - nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ - nv_wr32(priv, 0x4000a0, 0x00000000); - nv_wr32(priv, 0x4000a4, 0x00000008); - nv_wr32(priv, 0x4008a8, 0xb784a400); - nv_wr32(priv, 0x400ba0, 0x002f8685); - nv_wr32(priv, 0x400ba4, 0x00231f3f); - nv_wr32(priv, 0x4008a4, 0x40000020); - - if (nv_device(priv)->chipset == 0x34) { - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032); - nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004); - nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002); + nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); + + nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0); + nv_wr32(gr, 0x400890, 0x01b463ff); + nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf2de0475); + nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000); + nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); + nv_wr32(gr, 0x400B80, 0x1003d888); + nv_wr32(gr, 0x400B84, 0x0c000000); + nv_wr32(gr, 0x400098, 0x00000000); + nv_wr32(gr, 0x40009C, 0x0005ad00); + nv_wr32(gr, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ + nv_wr32(gr, 0x4000a0, 0x00000000); + nv_wr32(gr, 0x4000a4, 0x00000008); + nv_wr32(gr, 0x4008a8, 0xb784a400); + nv_wr32(gr, 0x400ba0, 0x002f8685); + nv_wr32(gr, 0x400ba4, 0x00231f3f); + nv_wr32(gr, 0x4008a4, 0x40000020); + + if (nv_device(gr)->chipset == 0x34) { + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00200201); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000008); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000032); + nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00004); + nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000002); } - nv_wr32(priv, 0x4000c0, 0x00000016); + nv_wr32(gr, 0x4000c0, 0x00000016); /* Turn all the tiling regions off. */ for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); - nv_wr32(priv, 0x0040075c , 0x00000001); + nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nv_wr32(gr, 0x0040075c , 0x00000001); /* begin RAM config */ - /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */ - nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); - if (nv_device(priv)->chipset != 0x34) { - nv_wr32(priv, 0x400750, 0x00EA0000); - nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x400750, 0x00EA0004); - nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); + /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ + nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204)); + if (nv_device(gr)->chipset != 0x34) { + nv_wr32(gr, 0x400750, 0x00EA0000); + nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x400750, 0x00EA0004); + nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100204)); } return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 985b7f3306ae..e17eb0b13277 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -126,24 +126,24 @@ nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv20_gr_priv *priv; + struct nv20_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_gr_intr; - nv_engine(priv)->cclass = &nv34_gr_cclass; - nv_engine(priv)->sclass = nv34_gr_sclass; - nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv20_gr_intr; + nv_engine(gr)->cclass = &nv34_gr_cclass; + nv_engine(gr)->sclass = nv34_gr_sclass; + nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 707625f19ff5..35ba75130f93 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -126,24 +126,24 @@ nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv20_gr_priv *priv; + struct nv20_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); + ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv20_gr_intr; - nv_engine(priv)->cclass = &nv35_gr_cclass; - nv_engine(priv)->sclass = nv35_gr_sclass; - nv_engine(priv)->tile_prog = nv20_gr_tile_prog; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv20_gr_intr; + nv_engine(gr)->cclass = &nv35_gr_cclass; + nv_engine(gr)->sclass = nv35_gr_sclass; + nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index c0a1751a1e88..3c2df9d29ff3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -30,7 +30,7 @@ #include #include -struct nv40_gr_priv { +struct nv40_gr { struct nvkm_gr base; u32 size; }; @@ -42,9 +42,7 @@ struct nv40_gr_chan { static u64 nv40_gr_units(struct nvkm_gr *gr) { - struct nv40_gr_priv *priv = (void *)gr; - - return nv_rd32(priv, 0x1540); + return nv_rd32(gr, 0x1540); } /******************************************************************************* @@ -137,17 +135,17 @@ nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv40_gr_priv *priv = (void *)engine; + struct nv40_gr *gr = (void *)engine; struct nv40_gr_chan *chan; int ret; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size, 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan)); + nv40_grctx_fill(nv_device(gr), nv_gpuobj(chan)); nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4); return 0; } @@ -155,33 +153,33 @@ nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, static int nv40_gr_context_fini(struct nvkm_object *object, bool suspend) { - struct nv40_gr_priv *priv = (void *)object->engine; + struct nv40_gr *gr = (void *)object->engine; struct nv40_gr_chan *chan = (void *)object; u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; int ret = 0; - nv_mask(priv, 0x400720, 0x00000001, 0x00000000); + nv_mask(gr, 0x400720, 0x00000001, 0x00000000); - if (nv_rd32(priv, 0x40032c) == inst) { + if (nv_rd32(gr, 0x40032c) == inst) { if (suspend) { - nv_wr32(priv, 0x400720, 0x00000000); - nv_wr32(priv, 0x400784, inst); - nv_mask(priv, 0x400310, 0x00000020, 0x00000020); - nv_mask(priv, 0x400304, 0x00000001, 0x00000001); - if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) { - u32 insn = nv_rd32(priv, 0x400308); - nv_warn(priv, "ctxprog timeout 0x%08x\n", insn); + nv_wr32(gr, 0x400720, 0x00000000); + nv_wr32(gr, 0x400784, inst); + nv_mask(gr, 0x400310, 0x00000020, 0x00000020); + nv_mask(gr, 0x400304, 0x00000001, 0x00000001); + if (!nv_wait(gr, 0x400300, 0x00000001, 0x00000000)) { + u32 insn = nv_rd32(gr, 0x400308); + nv_warn(gr, "ctxprog timeout 0x%08x\n", insn); ret = -EBUSY; } } - nv_mask(priv, 0x40032c, 0x01000000, 0x00000000); + nv_mask(gr, 0x40032c, 0x01000000, 0x00000000); } - if (nv_rd32(priv, 0x400330) == inst) - nv_mask(priv, 0x400330, 0x01000000, 0x00000000); + if (nv_rd32(gr, 0x400330) == inst) + nv_mask(gr, 0x400330, 0x01000000, 0x00000000); - nv_mask(priv, 0x400720, 0x00000001, 0x00000001); + nv_mask(gr, 0x400720, 0x00000001, 0x00000001); return ret; } @@ -207,36 +205,36 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) { struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; struct nvkm_fifo *fifo = nvkm_fifo(engine); - struct nv40_gr_priv *priv = (void *)engine; + struct nv40_gr *gr = (void *)engine; unsigned long flags; fifo->pause(fifo, &flags); - nv04_gr_idle(priv); + nv04_gr_idle(gr); - switch (nv_device(priv)->chipset) { + switch (nv_device(gr)->chipset) { case 0x40: case 0x41: case 0x42: case 0x43: case 0x45: case 0x4e: - nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); - nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); - nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); - nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); - switch (nv_device(priv)->chipset) { + nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr); + nv_wr32(gr, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nv_wr32(gr, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nv_wr32(gr, NV40_PGRAPH_TILE1(i), tile->addr); + switch (nv_device(gr)->chipset) { case 0x40: case 0x45: - nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); - nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); + nv_wr32(gr, NV20_PGRAPH_ZCOMP(i), tile->zcomp); + nv_wr32(gr, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); break; case 0x41: case 0x42: case 0x43: - nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); - nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); + nv_wr32(gr, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); + nv_wr32(gr, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); break; default: break; @@ -244,9 +242,9 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) break; case 0x44: case 0x4a: - nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); + nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr); break; case 0x46: case 0x4c: @@ -256,18 +254,18 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) case 0x63: case 0x67: case 0x68: - nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr); - nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); - nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); - nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); - switch (nv_device(priv)->chipset) { + nv_wr32(gr, NV47_PGRAPH_TSIZE(i), tile->pitch); + nv_wr32(gr, NV47_PGRAPH_TLIMIT(i), tile->limit); + nv_wr32(gr, NV47_PGRAPH_TILE(i), tile->addr); + nv_wr32(gr, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nv_wr32(gr, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nv_wr32(gr, NV40_PGRAPH_TILE1(i), tile->addr); + switch (nv_device(gr)->chipset) { case 0x47: case 0x49: case 0x4b: - nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); - nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); + nv_wr32(gr, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); + nv_wr32(gr, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); break; default: break; @@ -287,16 +285,16 @@ nv40_gr_intr(struct nvkm_subdev *subdev) struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle = NULL; - struct nv40_gr_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); - u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff; - u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); + struct nv40_gr *gr = (void *)subdev; + u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); + u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); + u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); + u32 inst = nv_rd32(gr, 0x40032c) & 0x000fffff; + u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff; + u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xffff; u32 show = stat; int chid; @@ -312,22 +310,22 @@ nv40_gr_intr(struct nvkm_subdev *subdev) } if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { - nv_mask(priv, 0x402000, 0, 0); + nv_mask(gr, 0x402000, 0, 0); } } - nv_wr32(priv, NV03_PGRAPH_INTR, stat); - nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); + nv_wr32(gr, NV03_PGRAPH_INTR, stat); + nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(priv, "%s", ""); + nv_error(gr, "%s", ""); nvkm_bitfield_print(nv10_gr_intr_name, show); pr_cont(" nsource:"); nvkm_bitfield_print(nv04_gr_nsource, nsource); pr_cont(" nstatus:"); nvkm_bitfield_print(nv10_gr_nstatus, nstatus); pr_cont("\n"); - nv_error(priv, + nv_error(gr, "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, inst << 4, nvkm_client_name(engctx), subc, class, mthd, data); @@ -341,24 +339,24 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv40_gr_priv *priv; + struct nv40_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - nv_subdev(priv)->unit = 0x00001000; - nv_subdev(priv)->intr = nv40_gr_intr; - nv_engine(priv)->cclass = &nv40_gr_cclass; - if (nv44_gr_class(priv)) - nv_engine(priv)->sclass = nv44_gr_sclass; + nv_subdev(gr)->unit = 0x00001000; + nv_subdev(gr)->intr = nv40_gr_intr; + nv_engine(gr)->cclass = &nv40_gr_cclass; + if (nv44_gr_class(gr)) + nv_engine(gr)->sclass = nv44_gr_sclass; else - nv_engine(priv)->sclass = nv40_gr_sclass; - nv_engine(priv)->tile_prog = nv40_gr_tile_prog; + nv_engine(gr)->sclass = nv40_gr_sclass; + nv_engine(gr)->tile_prog = nv40_gr_tile_prog; - priv->base.units = nv40_gr_units; + gr->base.units = nv40_gr_units; return 0; } @@ -367,103 +365,103 @@ nv40_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nvkm_fb *fb = nvkm_fb(object); - struct nv40_gr_priv *priv = (void *)engine; + struct nv40_gr *gr = (void *)engine; int ret, i, j; u32 vramsz; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; /* generate and upload context program */ - ret = nv40_grctx_init(nv_device(priv), &priv->size); + ret = nv40_grctx_init(nv_device(gr), &gr->size); if (ret) return ret; /* No context present currently */ - nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); + nv_wr32(gr, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); - nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); + nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nv_wr32(gr, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); - nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055); - nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); - nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); + nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0); + nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xe0de8055); + nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000); + nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); - nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); - nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10010100); + nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF); - j = nv_rd32(priv, 0x1540) & 0xff; + j = nv_rd32(gr, 0x1540) & 0xff; if (j) { for (i = 0; !(j & 1); j >>= 1, i++) ; - nv_wr32(priv, 0x405000, i); + nv_wr32(gr, 0x405000, i); } - if (nv_device(priv)->chipset == 0x40) { - nv_wr32(priv, 0x4009b0, 0x83280fff); - nv_wr32(priv, 0x4009b4, 0x000000a0); + if (nv_device(gr)->chipset == 0x40) { + nv_wr32(gr, 0x4009b0, 0x83280fff); + nv_wr32(gr, 0x4009b4, 0x000000a0); } else { - nv_wr32(priv, 0x400820, 0x83280eff); - nv_wr32(priv, 0x400824, 0x000000a0); + nv_wr32(gr, 0x400820, 0x83280eff); + nv_wr32(gr, 0x400824, 0x000000a0); } - switch (nv_device(priv)->chipset) { + switch (nv_device(gr)->chipset) { case 0x40: case 0x45: - nv_wr32(priv, 0x4009b8, 0x0078e366); - nv_wr32(priv, 0x4009bc, 0x0000014c); + nv_wr32(gr, 0x4009b8, 0x0078e366); + nv_wr32(gr, 0x4009bc, 0x0000014c); break; case 0x41: case 0x42: /* pciid also 0x00Cx */ /* case 0x0120: XXX (pciid) */ - nv_wr32(priv, 0x400828, 0x007596ff); - nv_wr32(priv, 0x40082c, 0x00000108); + nv_wr32(gr, 0x400828, 0x007596ff); + nv_wr32(gr, 0x40082c, 0x00000108); break; case 0x43: - nv_wr32(priv, 0x400828, 0x0072cb77); - nv_wr32(priv, 0x40082c, 0x00000108); + nv_wr32(gr, 0x400828, 0x0072cb77); + nv_wr32(gr, 0x40082c, 0x00000108); break; case 0x44: case 0x46: /* G72 */ case 0x4a: case 0x4c: /* G7x-based C51 */ case 0x4e: - nv_wr32(priv, 0x400860, 0); - nv_wr32(priv, 0x400864, 0); + nv_wr32(gr, 0x400860, 0); + nv_wr32(gr, 0x400864, 0); break; case 0x47: /* G70 */ case 0x49: /* G71 */ case 0x4b: /* G73 */ - nv_wr32(priv, 0x400828, 0x07830610); - nv_wr32(priv, 0x40082c, 0x0000016A); + nv_wr32(gr, 0x400828, 0x07830610); + nv_wr32(gr, 0x40082c, 0x0000016A); break; default: break; } - nv_wr32(priv, 0x400b38, 0x2ffff800); - nv_wr32(priv, 0x400b3c, 0x00006000); + nv_wr32(gr, 0x400b38, 0x2ffff800); + nv_wr32(gr, 0x400b3c, 0x00006000); /* Tiling related stuff. */ - switch (nv_device(priv)->chipset) { + switch (nv_device(gr)->chipset) { case 0x44: case 0x4a: - nv_wr32(priv, 0x400bc4, 0x1003d888); - nv_wr32(priv, 0x400bbc, 0xb7a7b500); + nv_wr32(gr, 0x400bc4, 0x1003d888); + nv_wr32(gr, 0x400bbc, 0xb7a7b500); break; case 0x46: - nv_wr32(priv, 0x400bc4, 0x0000e024); - nv_wr32(priv, 0x400bbc, 0xb7a7b520); + nv_wr32(gr, 0x400bc4, 0x0000e024); + nv_wr32(gr, 0x400bbc, 0xb7a7b520); break; case 0x4c: case 0x4e: case 0x67: - nv_wr32(priv, 0x400bc4, 0x1003d888); - nv_wr32(priv, 0x400bbc, 0xb7a7b540); + nv_wr32(gr, 0x400bc4, 0x1003d888); + nv_wr32(gr, 0x400bbc, 0xb7a7b540); break; default: break; @@ -474,20 +472,20 @@ nv40_gr_init(struct nvkm_object *object) engine->tile_prog(engine, i); /* begin RAM config */ - vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; - switch (nv_device(priv)->chipset) { + vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; + switch (nv_device(gr)->chipset) { case 0x40: - nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x400820, 0); - nv_wr32(priv, 0x400824, 0); - nv_wr32(priv, 0x400864, vramsz); - nv_wr32(priv, 0x400868, vramsz); + nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204)); + nv_wr32(gr, 0x4069A4, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x4069A8, nv_rd32(gr, 0x100204)); + nv_wr32(gr, 0x400820, 0); + nv_wr32(gr, 0x400824, 0); + nv_wr32(gr, 0x400864, vramsz); + nv_wr32(gr, 0x400868, vramsz); break; default: - switch (nv_device(priv)->chipset) { + switch (nv_device(gr)->chipset) { case 0x41: case 0x42: case 0x43: @@ -495,20 +493,20 @@ nv40_gr_init(struct nvkm_object *object) case 0x4e: case 0x44: case 0x4a: - nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204)); + nv_wr32(gr, 0x4009F0, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x4009F4, nv_rd32(gr, 0x100204)); break; default: - nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204)); + nv_wr32(gr, 0x400DF0, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x400DF4, nv_rd32(gr, 0x100204)); break; } - nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200)); - nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204)); - nv_wr32(priv, 0x400840, 0); - nv_wr32(priv, 0x400844, 0); - nv_wr32(priv, 0x4008A0, vramsz); - nv_wr32(priv, 0x4008A4, vramsz); + nv_wr32(gr, 0x4069F0, nv_rd32(gr, 0x100200)); + nv_wr32(gr, 0x4069F4, nv_rd32(gr, 0x100204)); + nv_wr32(gr, 0x400840, 0); + nv_wr32(gr, 0x400844, 0); + nv_wr32(gr, 0x4008A0, vramsz); + nv_wr32(gr, 0x4008A4, vramsz); break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index e232cb8e2f9e..70be675b1928 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -28,7 +28,7 @@ #include #include -struct nv50_gr_priv { +struct nv50_gr { struct nvkm_gr base; spinlock_t lock; u32 size; @@ -41,9 +41,7 @@ struct nv50_gr_chan { static u64 nv50_gr_units(struct nvkm_gr *gr) { - struct nv50_gr_priv *priv = (void *)gr; - - return nv_rd32(priv, 0x1540); + return nv_rd32(gr, 0x1540); } /******************************************************************************* @@ -142,17 +140,17 @@ nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_gr_priv *priv = (void *)engine; + struct nv50_gr *gr = (void *)engine; struct nv50_gr_chan *chan; int ret; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, + ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size, 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); *pobject = nv_object(chan); if (ret) return ret; - nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); + nv50_grctx_fill(nv_device(gr), nv_gpuobj(chan)); return 0; } @@ -173,7 +171,7 @@ nv50_gr_cclass = { * PGRAPH engine/subdev functions ******************************************************************************/ -static const struct nvkm_bitfield nv50_pgr_status[] = { +static const struct nvkm_bitfield nv50_gr_status[] = { { 0x00000001, "BUSY" }, /* set when any bit is set */ { 0x00000002, "DISPATCH" }, { 0x00000004, "UNK2" }, @@ -202,27 +200,27 @@ static const struct nvkm_bitfield nv50_pgr_status[] = { {} }; -static const char *const nv50_pgr_vstatus_0[] = { +static const char *const nv50_gr_vstatus_0[] = { "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP", NULL }; -static const char *const nv50_pgr_vstatus_1[] = { +static const char *const nv50_gr_vstatus_1[] = { "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL }; -static const char *const nv50_pgr_vstatus_2[] = { +static const char *const nv50_gr_vstatus_2[] = { "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK", "ROP", NULL }; static void -nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r, +nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, const char *const units[], u32 status) { int i; - nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); + nv_error(gr, "PGRAPH_VSTATUS%d: 0x%08x", r, status); for (i = 0; units[i] && status; i++) { if ((status & 7) == 1) @@ -238,30 +236,30 @@ static int g84_gr_tlb_flush(struct nvkm_engine *engine) { struct nvkm_timer *tmr = nvkm_timer(engine); - struct nv50_gr_priv *priv = (void *)engine; + struct nv50_gr *gr = (void *)engine; bool idle, timeout = false; unsigned long flags; u64 start; u32 tmp; - spin_lock_irqsave(&priv->lock, flags); - nv_mask(priv, 0x400500, 0x00000001, 0x00000000); + spin_lock_irqsave(&gr->lock, flags); + nv_mask(gr, 0x400500, 0x00000001, 0x00000000); start = tmr->read(tmr); do { idle = true; - for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { + for (tmp = nv_rd32(gr, 0x400380); tmp && idle; tmp >>= 3) { if ((tmp & 7) == 1) idle = false; } - for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { + for (tmp = nv_rd32(gr, 0x400384); tmp && idle; tmp >>= 3) { if ((tmp & 7) == 1) idle = false; } - for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { + for (tmp = nv_rd32(gr, 0x400388); tmp && idle; tmp >>= 3) { if ((tmp & 7) == 1) idle = false; } @@ -269,27 +267,27 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) !(timeout = tmr->read(tmr) - start > 2000000000)); if (timeout) { - nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); + nv_error(gr, "PGRAPH TLB flush idle timeout fail\n"); - tmp = nv_rd32(priv, 0x400700); - nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); - nvkm_bitfield_print(nv50_pgr_status, tmp); + tmp = nv_rd32(gr, 0x400700); + nv_error(gr, "PGRAPH_STATUS : 0x%08x", tmp); + nvkm_bitfield_print(nv50_gr_status, tmp); pr_cont("\n"); - nvkm_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0, - nv_rd32(priv, 0x400380)); - nvkm_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1, - nv_rd32(priv, 0x400384)); - nvkm_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2, - nv_rd32(priv, 0x400388)); + nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, + nv_rd32(gr, 0x400380)); + nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1, + nv_rd32(gr, 0x400384)); + nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2, + nv_rd32(gr, 0x400388)); } - nv_wr32(priv, 0x100c80, 0x00000001); - if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) - nv_error(priv, "vm flush timeout\n"); - nv_mask(priv, 0x400500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&priv->lock, flags); + nv_wr32(gr, 0x100c80, 0x00000001); + if (!nv_wait(gr, 0x100c80, 0x00000001, 0x00000000)) + nv_error(gr, "vm flush timeout\n"); + nv_mask(gr, 0x400500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&gr->lock, flags); return timeout ? -EBUSY : 0; } @@ -426,111 +424,111 @@ static const struct nvkm_bitfield nv50_gr_trap_prop[] = { }; static void -nv50_priv_prop_trap(struct nv50_gr_priv *priv, +nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp) { - u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); - u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); - u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); - u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); - u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); - u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); - u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); + u32 e0c = nv_rd32(gr, ustatus_addr + 0x04); + u32 e10 = nv_rd32(gr, ustatus_addr + 0x08); + u32 e14 = nv_rd32(gr, ustatus_addr + 0x0c); + u32 e18 = nv_rd32(gr, ustatus_addr + 0x10); + u32 e1c = nv_rd32(gr, ustatus_addr + 0x14); + u32 e20 = nv_rd32(gr, ustatus_addr + 0x18); + u32 e24 = nv_rd32(gr, ustatus_addr + 0x1c); /* CUDA memory: l[], g[] or stack. */ if (ustatus & 0x00000080) { if (e18 & 0x80000000) { /* g[] read fault? */ - nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", + nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", tp, e14, e10 | ((e18 >> 24) & 0x1f)); e18 &= ~0x1f000000; } else if (e18 & 0xc) { /* g[] write fault? */ - nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", + nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", tp, e14, e10 | ((e18 >> 7) & 0x1f)); e18 &= ~0x00000f80; } else { - nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", + nv_error(gr, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", tp, e14, e10); } ustatus &= ~0x00000080; } if (ustatus) { - nv_error(priv, "TRAP_PROP - TP %d -", tp); + nv_error(gr, "TRAP_PROP - TP %d -", tp); nvkm_bitfield_print(nv50_gr_trap_prop, ustatus); pr_cont(" - Address %02x%08x\n", e14, e10); } - nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", + nv_error(gr, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", tp, e0c, e18, e1c, e20, e24); } static void -nv50_priv_mp_trap(struct nv50_gr_priv *priv, int tpid, int display) +nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) { - u32 units = nv_rd32(priv, 0x1540); + u32 units = nv_rd32(gr, 0x1540); u32 addr, mp10, status, pc, oplow, ophigh; int i; int mps = 0; for (i = 0; i < 4; i++) { if (!(units & 1 << (i+24))) continue; - if (nv_device(priv)->chipset < 0xa0) + if (nv_device(gr)->chipset < 0xa0) addr = 0x408200 + (tpid << 12) + (i << 7); else addr = 0x408100 + (tpid << 11) + (i << 7); - mp10 = nv_rd32(priv, addr + 0x10); - status = nv_rd32(priv, addr + 0x14); + mp10 = nv_rd32(gr, addr + 0x10); + status = nv_rd32(gr, addr + 0x14); if (!status) continue; if (display) { - nv_rd32(priv, addr + 0x20); - pc = nv_rd32(priv, addr + 0x24); - oplow = nv_rd32(priv, addr + 0x70); - ophigh = nv_rd32(priv, addr + 0x74); - nv_error(priv, "TRAP_MP_EXEC - " + nv_rd32(gr, addr + 0x20); + pc = nv_rd32(gr, addr + 0x24); + oplow = nv_rd32(gr, addr + 0x70); + ophigh = nv_rd32(gr, addr + 0x74); + nv_error(gr, "TRAP_MP_EXEC - " "TP %d MP %d:", tpid, i); nvkm_bitfield_print(nv50_mp_exec_errors, status); pr_cont(" at %06x warp %d, opcode %08x %08x\n", pc&0xffffff, pc >> 24, oplow, ophigh); } - nv_wr32(priv, addr + 0x10, mp10); - nv_wr32(priv, addr + 0x14, 0); + nv_wr32(gr, addr + 0x10, mp10); + nv_wr32(gr, addr + 0x14, 0); mps++; } if (!mps && display) - nv_error(priv, "TRAP_MP_EXEC - TP %d: " + nv_error(gr, "TRAP_MP_EXEC - TP %d: " "No MPs claiming errors?\n", tpid); } static void -nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old, +nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, u32 ustatus_new, int display, const char *name) { int tps = 0; - u32 units = nv_rd32(priv, 0x1540); + u32 units = nv_rd32(gr, 0x1540); int i, r; u32 ustatus_addr, ustatus; for (i = 0; i < 16; i++) { if (!(units & (1 << i))) continue; - if (nv_device(priv)->chipset < 0xa0) + if (nv_device(gr)->chipset < 0xa0) ustatus_addr = ustatus_old + (i << 12); else ustatus_addr = ustatus_new + (i << 11); - ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; + ustatus = nv_rd32(gr, ustatus_addr) & 0x7fffffff; if (!ustatus) continue; tps++; switch (type) { case 6: /* texture error... unknown for now */ if (display) { - nv_error(priv, "magic set %d:\n", i); + nv_error(gr, "magic set %d:\n", i); for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) - nv_error(priv, "\t0x%08x: 0x%08x\n", r, - nv_rd32(priv, r)); + nv_error(gr, "\t0x%08x: 0x%08x\n", r, + nv_rd32(gr, r)); if (ustatus) { - nv_error(priv, "%s - TP%d:", name, i); + nv_error(gr, "%s - TP%d:", name, i); nvkm_bitfield_print(nv50_tex_traps, ustatus); pr_cont("\n"); @@ -540,11 +538,11 @@ nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old, break; case 7: /* MP error */ if (ustatus & 0x04030000) { - nv50_priv_mp_trap(priv, i, display); + nv50_gr_mp_trap(gr, i, display); ustatus &= ~0x04030000; } if (ustatus && display) { - nv_error(priv, "%s - TP%d:", name, i); + nv_error(gr, "%s - TP%d:", name, i); nvkm_bitfield_print(nv50_mpc_traps, ustatus); pr_cont("\n"); ustatus = 0; @@ -552,31 +550,31 @@ nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old, break; case 8: /* PROP error */ if (display) - nv50_priv_prop_trap( - priv, ustatus_addr, ustatus, i); + nv50_gr_prop_trap( + gr, ustatus_addr, ustatus, i); ustatus = 0; break; } if (ustatus) { if (display) - nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); + nv_error(gr, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); } - nv_wr32(priv, ustatus_addr, 0xc0000000); + nv_wr32(gr, ustatus_addr, 0xc0000000); } if (!tps && display) - nv_warn(priv, "%s - No TPs claiming errors?\n", name); + nv_warn(gr, "%s - No TPs claiming errors?\n", name); } static int -nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, +nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, int chid, u64 inst, struct nvkm_object *engctx) { - u32 status = nv_rd32(priv, 0x400108); + u32 status = nv_rd32(gr, 0x400108); u32 ustatus; if (!status && display) { - nv_error(priv, "TRAP: no units reporting traps?\n"); + nv_error(gr, "TRAP: no units reporting traps?\n"); return 1; } @@ -584,71 +582,71 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, * COND, QUERY. If you get a trap from it, the command is still stuck * in DISPATCH and you need to do something about it. */ if (status & 0x001) { - ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; + ustatus = nv_rd32(gr, 0x400804) & 0x7fffffff; if (!ustatus && display) { - nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); + nv_error(gr, "TRAP_DISPATCH - no ustatus?\n"); } - nv_wr32(priv, 0x400500, 0x00000000); + nv_wr32(gr, 0x400500, 0x00000000); /* Known to be triggered by screwed up NOTIFY and COND... */ if (ustatus & 0x00000001) { - u32 addr = nv_rd32(priv, 0x400808); + u32 addr = nv_rd32(gr, 0x400808); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 datal = nv_rd32(priv, 0x40080c); - u32 datah = nv_rd32(priv, 0x400810); - u32 class = nv_rd32(priv, 0x400814); - u32 r848 = nv_rd32(priv, 0x400848); + u32 datal = nv_rd32(gr, 0x40080c); + u32 datah = nv_rd32(gr, 0x400810); + u32 class = nv_rd32(gr, 0x400814); + u32 r848 = nv_rd32(gr, 0x400848); - nv_error(priv, "TRAP DISPATCH_FAULT\n"); + nv_error(gr, "TRAP DISPATCH_FAULT\n"); if (display && (addr & 0x80000000)) { - nv_error(priv, + nv_error(gr, "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", chid, inst, nvkm_client_name(engctx), subc, class, mthd, datah, datal, addr, r848); } else if (display) { - nv_error(priv, "no stuck command?\n"); + nv_error(gr, "no stuck command?\n"); } - nv_wr32(priv, 0x400808, 0); - nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); - nv_wr32(priv, 0x400848, 0); + nv_wr32(gr, 0x400808, 0); + nv_wr32(gr, 0x4008e8, nv_rd32(gr, 0x4008e8) & 3); + nv_wr32(gr, 0x400848, 0); ustatus &= ~0x00000001; } if (ustatus & 0x00000002) { - u32 addr = nv_rd32(priv, 0x40084c); + u32 addr = nv_rd32(gr, 0x40084c); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, 0x40085c); - u32 class = nv_rd32(priv, 0x400814); + u32 data = nv_rd32(gr, 0x40085c); + u32 class = nv_rd32(gr, 0x400814); - nv_error(priv, "TRAP DISPATCH_QUERY\n"); + nv_error(gr, "TRAP DISPATCH_QUERY\n"); if (display && (addr & 0x80000000)) { - nv_error(priv, + nv_error(gr, "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", chid, inst, nvkm_client_name(engctx), subc, class, mthd, data, addr); } else if (display) { - nv_error(priv, "no stuck command?\n"); + nv_error(gr, "no stuck command?\n"); } - nv_wr32(priv, 0x40084c, 0); + nv_wr32(gr, 0x40084c, 0); ustatus &= ~0x00000002; } if (ustatus && display) { - nv_error(priv, "TRAP_DISPATCH (unknown " + nv_error(gr, "TRAP_DISPATCH (unknown " "0x%08x)\n", ustatus); } - nv_wr32(priv, 0x400804, 0xc0000000); - nv_wr32(priv, 0x400108, 0x001); + nv_wr32(gr, 0x400804, 0xc0000000); + nv_wr32(gr, 0x400108, 0x001); status &= ~0x001; if (!status) return 0; @@ -656,81 +654,81 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, /* M2MF: Memory to memory copy engine. */ if (status & 0x002) { - u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; + u32 ustatus = nv_rd32(gr, 0x406800) & 0x7fffffff; if (display) { - nv_error(priv, "TRAP_M2MF"); + nv_error(gr, "TRAP_M2MF"); nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus); pr_cont("\n"); - nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", - nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), - nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); + nv_error(gr, "TRAP_M2MF %08x %08x %08x %08x\n", + nv_rd32(gr, 0x406804), nv_rd32(gr, 0x406808), + nv_rd32(gr, 0x40680c), nv_rd32(gr, 0x406810)); } /* No sane way found yet -- just reset the bugger. */ - nv_wr32(priv, 0x400040, 2); - nv_wr32(priv, 0x400040, 0); - nv_wr32(priv, 0x406800, 0xc0000000); - nv_wr32(priv, 0x400108, 0x002); + nv_wr32(gr, 0x400040, 2); + nv_wr32(gr, 0x400040, 0); + nv_wr32(gr, 0x406800, 0xc0000000); + nv_wr32(gr, 0x400108, 0x002); status &= ~0x002; } /* VFETCH: Fetches data from vertex buffers. */ if (status & 0x004) { - u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; + u32 ustatus = nv_rd32(gr, 0x400c04) & 0x7fffffff; if (display) { - nv_error(priv, "TRAP_VFETCH"); + nv_error(gr, "TRAP_VFETCH"); nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus); pr_cont("\n"); - nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", - nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), - nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); + nv_error(gr, "TRAP_VFETCH %08x %08x %08x %08x\n", + nv_rd32(gr, 0x400c00), nv_rd32(gr, 0x400c08), + nv_rd32(gr, 0x400c0c), nv_rd32(gr, 0x400c10)); } - nv_wr32(priv, 0x400c04, 0xc0000000); - nv_wr32(priv, 0x400108, 0x004); + nv_wr32(gr, 0x400c04, 0xc0000000); + nv_wr32(gr, 0x400108, 0x004); status &= ~0x004; } /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ if (status & 0x008) { - ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; + ustatus = nv_rd32(gr, 0x401800) & 0x7fffffff; if (display) { - nv_error(priv, "TRAP_STRMOUT"); + nv_error(gr, "TRAP_STRMOUT"); nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus); pr_cont("\n"); - nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", - nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), - nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); + nv_error(gr, "TRAP_STRMOUT %08x %08x %08x %08x\n", + nv_rd32(gr, 0x401804), nv_rd32(gr, 0x401808), + nv_rd32(gr, 0x40180c), nv_rd32(gr, 0x401810)); } /* No sane way found yet -- just reset the bugger. */ - nv_wr32(priv, 0x400040, 0x80); - nv_wr32(priv, 0x400040, 0); - nv_wr32(priv, 0x401800, 0xc0000000); - nv_wr32(priv, 0x400108, 0x008); + nv_wr32(gr, 0x400040, 0x80); + nv_wr32(gr, 0x400040, 0); + nv_wr32(gr, 0x401800, 0xc0000000); + nv_wr32(gr, 0x400108, 0x008); status &= ~0x008; } /* CCACHE: Handles code and c[] caches and fills them. */ if (status & 0x010) { - ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; + ustatus = nv_rd32(gr, 0x405018) & 0x7fffffff; if (display) { - nv_error(priv, "TRAP_CCACHE"); + nv_error(gr, "TRAP_CCACHE"); nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus); pr_cont("\n"); - nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" + nv_error(gr, "TRAP_CCACHE %08x %08x %08x %08x" " %08x %08x %08x\n", - nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), - nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), - nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), - nv_rd32(priv, 0x40501c)); + nv_rd32(gr, 0x405000), nv_rd32(gr, 0x405004), + nv_rd32(gr, 0x405008), nv_rd32(gr, 0x40500c), + nv_rd32(gr, 0x405010), nv_rd32(gr, 0x405014), + nv_rd32(gr, 0x40501c)); } - nv_wr32(priv, 0x405018, 0xc0000000); - nv_wr32(priv, 0x400108, 0x010); + nv_wr32(gr, 0x405018, 0xc0000000); + nv_wr32(gr, 0x400108, 0x010); status &= ~0x010; } @@ -738,42 +736,42 @@ nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display, * remaining, so try to handle it anyway. Perhaps related to that * unknown DMA slot on tesla? */ if (status & 0x20) { - ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; + ustatus = nv_rd32(gr, 0x402000) & 0x7fffffff; if (display) - nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); - nv_wr32(priv, 0x402000, 0xc0000000); + nv_error(gr, "TRAP_UNKC04 0x%08x\n", ustatus); + nv_wr32(gr, 0x402000, 0xc0000000); /* no status modifiction on purpose */ } /* TEXTURE: CUDA texturing units */ if (status & 0x040) { - nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, + nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display, "TRAP_TEXTURE"); - nv_wr32(priv, 0x400108, 0x040); + nv_wr32(gr, 0x400108, 0x040); status &= ~0x040; } /* MP: CUDA execution engines. */ if (status & 0x080) { - nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, + nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display, "TRAP_MP"); - nv_wr32(priv, 0x400108, 0x080); + nv_wr32(gr, 0x400108, 0x080); status &= ~0x080; } /* PROP: Handles TP-initiated uncached memory accesses: * l[], g[], stack, 2d surfaces, render targets. */ if (status & 0x100) { - nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, + nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display, "TRAP_PROP"); - nv_wr32(priv, 0x400108, 0x100); + nv_wr32(gr, 0x400108, 0x100); status &= ~0x100; } if (status) { if (display) - nv_error(priv, "TRAP: unknown 0x%08x\n", status); - nv_wr32(priv, 0x400108, status); + nv_error(gr, "TRAP: unknown 0x%08x\n", status); + nv_wr32(gr, 0x400108, status); } return 1; @@ -786,14 +784,14 @@ nv50_gr_intr(struct nvkm_subdev *subdev) struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle = NULL; - struct nv50_gr_priv *priv = (void *)subdev; - u32 stat = nv_rd32(priv, 0x400100); - u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; - u32 addr = nv_rd32(priv, 0x400704); + struct nv50_gr *gr = (void *)subdev; + u32 stat = nv_rd32(gr, 0x400100); + u32 inst = nv_rd32(gr, 0x40032c) & 0x0fffffff; + u32 addr = nv_rd32(gr, 0x400704); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(priv, 0x400708); - u32 class = nv_rd32(priv, 0x400814); + u32 data = nv_rd32(gr, 0x400708); + u32 class = nv_rd32(gr, 0x400814); u32 show = stat, show_bitfield = stat; int chid; @@ -808,38 +806,38 @@ nv50_gr_intr(struct nvkm_subdev *subdev) } if (show & 0x00100000) { - u32 ecode = nv_rd32(priv, 0x400110); - nv_error(priv, "DATA_ERROR "); + u32 ecode = nv_rd32(gr, 0x400110); + nv_error(gr, "DATA_ERROR "); nvkm_enum_print(nv50_data_error_names, ecode); pr_cont("\n"); show_bitfield &= ~0x00100000; } if (stat & 0x00200000) { - if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12, + if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, engctx)) show &= ~0x00200000; show_bitfield &= ~0x00200000; } - nv_wr32(priv, 0x400100, stat); - nv_wr32(priv, 0x400500, 0x00010001); + nv_wr32(gr, 0x400100, stat); + nv_wr32(gr, 0x400500, 0x00010001); if (show) { show &= show_bitfield; if (show) { - nv_error(priv, "%s", ""); + nv_error(gr, "%s", ""); nvkm_bitfield_print(nv50_gr_intr_name, show); pr_cont("\n"); } - nv_error(priv, + nv_error(gr, "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, (u64)inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); } - if (nv_rd32(priv, 0x400824) & (1 << 31)) - nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); + if (nv_rd32(gr, 0x400824) & (1 << 31)) + nv_wr32(gr, 0x400824, nv_rd32(gr, 0x400824) & ~(1 << 31)); nvkm_engctx_put(engctx); } @@ -849,23 +847,23 @@ nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_gr_priv *priv; + struct nv50_gr *gr; int ret; - ret = nvkm_gr_create(parent, engine, oclass, true, &priv); - *pobject = nv_object(priv); + ret = nvkm_gr_create(parent, engine, oclass, true, &gr); + *pobject = nv_object(gr); if (ret) return ret; - nv_subdev(priv)->unit = 0x00201000; - nv_subdev(priv)->intr = nv50_gr_intr; - nv_engine(priv)->cclass = &nv50_gr_cclass; + nv_subdev(gr)->unit = 0x00201000; + nv_subdev(gr)->intr = nv50_gr_intr; + nv_engine(gr)->cclass = &nv50_gr_cclass; - priv->base.units = nv50_gr_units; + gr->base.units = nv50_gr_units; - switch (nv_device(priv)->chipset) { + switch (nv_device(gr)->chipset) { case 0x50: - nv_engine(priv)->sclass = nv50_gr_sclass; + nv_engine(gr)->sclass = nv50_gr_sclass; break; case 0x84: case 0x86: @@ -873,104 +871,104 @@ nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, case 0x94: case 0x96: case 0x98: - nv_engine(priv)->sclass = g84_gr_sclass; + nv_engine(gr)->sclass = g84_gr_sclass; break; case 0xa0: case 0xaa: case 0xac: - nv_engine(priv)->sclass = gt200_gr_sclass; + nv_engine(gr)->sclass = gt200_gr_sclass; break; case 0xa3: case 0xa5: case 0xa8: - nv_engine(priv)->sclass = gt215_gr_sclass; + nv_engine(gr)->sclass = gt215_gr_sclass; break; case 0xaf: - nv_engine(priv)->sclass = mcp89_gr_sclass; + nv_engine(gr)->sclass = mcp89_gr_sclass; break; } /* unfortunate hw bug workaround... */ - if (nv_device(priv)->chipset != 0x50 && - nv_device(priv)->chipset != 0xac) - nv_engine(priv)->tlb_flush = g84_gr_tlb_flush; + if (nv_device(gr)->chipset != 0x50 && + nv_device(gr)->chipset != 0xac) + nv_engine(gr)->tlb_flush = g84_gr_tlb_flush; - spin_lock_init(&priv->lock); + spin_lock_init(&gr->lock); return 0; } static int nv50_gr_init(struct nvkm_object *object) { - struct nv50_gr_priv *priv = (void *)object; + struct nv50_gr *gr = (void *)object; int ret, units, i; - ret = nvkm_gr_init(&priv->base); + ret = nvkm_gr_init(&gr->base); if (ret) return ret; /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ - nv_wr32(priv, 0x40008c, 0x00000004); + nv_wr32(gr, 0x40008c, 0x00000004); /* reset/enable traps and interrupts */ - nv_wr32(priv, 0x400804, 0xc0000000); - nv_wr32(priv, 0x406800, 0xc0000000); - nv_wr32(priv, 0x400c04, 0xc0000000); - nv_wr32(priv, 0x401800, 0xc0000000); - nv_wr32(priv, 0x405018, 0xc0000000); - nv_wr32(priv, 0x402000, 0xc0000000); - - units = nv_rd32(priv, 0x001540); + nv_wr32(gr, 0x400804, 0xc0000000); + nv_wr32(gr, 0x406800, 0xc0000000); + nv_wr32(gr, 0x400c04, 0xc0000000); + nv_wr32(gr, 0x401800, 0xc0000000); + nv_wr32(gr, 0x405018, 0xc0000000); + nv_wr32(gr, 0x402000, 0xc0000000); + + units = nv_rd32(gr, 0x001540); for (i = 0; i < 16; i++) { if (!(units & (1 << i))) continue; - if (nv_device(priv)->chipset < 0xa0) { - nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); - nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); - nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); + if (nv_device(gr)->chipset < 0xa0) { + nv_wr32(gr, 0x408900 + (i << 12), 0xc0000000); + nv_wr32(gr, 0x408e08 + (i << 12), 0xc0000000); + nv_wr32(gr, 0x408314 + (i << 12), 0xc0000000); } else { - nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); - nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); - nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); + nv_wr32(gr, 0x408600 + (i << 11), 0xc0000000); + nv_wr32(gr, 0x408708 + (i << 11), 0xc0000000); + nv_wr32(gr, 0x40831c + (i << 11), 0xc0000000); } } - nv_wr32(priv, 0x400108, 0xffffffff); - nv_wr32(priv, 0x400138, 0xffffffff); - nv_wr32(priv, 0x400100, 0xffffffff); - nv_wr32(priv, 0x40013c, 0xffffffff); - nv_wr32(priv, 0x400500, 0x00010001); + nv_wr32(gr, 0x400108, 0xffffffff); + nv_wr32(gr, 0x400138, 0xffffffff); + nv_wr32(gr, 0x400100, 0xffffffff); + nv_wr32(gr, 0x40013c, 0xffffffff); + nv_wr32(gr, 0x400500, 0x00010001); /* upload context program, initialise ctxctl defaults */ - ret = nv50_grctx_init(nv_device(priv), &priv->size); + ret = nv50_grctx_init(nv_device(gr), &gr->size); if (ret) return ret; - nv_wr32(priv, 0x400824, 0x00000000); - nv_wr32(priv, 0x400828, 0x00000000); - nv_wr32(priv, 0x40082c, 0x00000000); - nv_wr32(priv, 0x400830, 0x00000000); - nv_wr32(priv, 0x40032c, 0x00000000); - nv_wr32(priv, 0x400330, 0x00000000); + nv_wr32(gr, 0x400824, 0x00000000); + nv_wr32(gr, 0x400828, 0x00000000); + nv_wr32(gr, 0x40082c, 0x00000000); + nv_wr32(gr, 0x400830, 0x00000000); + nv_wr32(gr, 0x40032c, 0x00000000); + nv_wr32(gr, 0x400330, 0x00000000); /* some unknown zcull magic */ - switch (nv_device(priv)->chipset & 0xf0) { + switch (nv_device(gr)->chipset & 0xf0) { case 0x50: case 0x80: case 0x90: - nv_wr32(priv, 0x402ca8, 0x00000800); + nv_wr32(gr, 0x402ca8, 0x00000800); break; case 0xa0: default: - if (nv_device(priv)->chipset == 0xa0 || - nv_device(priv)->chipset == 0xaa || - nv_device(priv)->chipset == 0xac) { - nv_wr32(priv, 0x402ca8, 0x00000802); + if (nv_device(gr)->chipset == 0xa0 || + nv_device(gr)->chipset == 0xaa || + nv_device(gr)->chipset == 0xac) { + nv_wr32(gr, 0x402ca8, 0x00000802); } else { - nv_wr32(priv, 0x402cc0, 0x00000000); - nv_wr32(priv, 0x402ca8, 0x00000002); + nv_wr32(gr, 0x402cc0, 0x00000000); + nv_wr32(gr, 0x402ca8, 0x00000002); } break; @@ -978,10 +976,10 @@ nv50_gr_init(struct nvkm_object *object) /* zero out zcull regions */ for (i = 0; i < 8; i++) { - nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); - nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); - nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); - nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); + nv_wr32(gr, 0x402c20 + (i * 0x10), 0x00000000); + nv_wr32(gr, 0x402c24 + (i * 0x10), 0x00000000); + nv_wr32(gr, 0x402c28 + (i * 0x10), 0x00000000); + nv_wr32(gr, 0x402c2c + (i * 0x10), 0x00000000); } return 0; } -- cgit v1.2.3 From 276836d46e535c8ca299a1ea8302879dbdd3e93a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:10 +1000 Subject: drm/nouveau/gr: switch to device pri macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 76 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c | 13 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c | 7 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 50 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 13 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 32 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c | 36 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 480 +++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 121 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 62 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 118 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 129 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 24 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 107 ++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 248 +++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 172 ++++---- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 85 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 202 ++++----- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 261 ++++++------ 22 files changed, 1181 insertions(+), 1089 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 22bc4dbd46df..43b393f4cd4d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1005,6 +1005,7 @@ void gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data, int shift, int buffer) { + struct nvkm_device *device = info->gr->base.engine.subdev.device; if (info->data) { if (shift >= 0) { info->mmio->addr = addr; @@ -1021,7 +1022,7 @@ gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data, return; } - nv_wr32(info->gr, addr, data); + nvkm_wr32(device, addr, data); } void @@ -1085,20 +1086,21 @@ gf100_grctx_generate_unkn(struct gf100_gr *gr) void gf100_grctx_generate_tpcid(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) { if (tpc < gr->tpc_nr[gpc]) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x4e8), id); - nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), id); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); id++; } - nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); } } } @@ -1106,18 +1108,20 @@ gf100_grctx_generate_tpcid(struct gf100_gr *gr) void gf100_grctx_generate_r406028(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 tmp[GPC_MAX / 8] = {}, i = 0; for (i = 0; i < gr->gpc_nr; i++) tmp[i / 8] |= gr->tpc_nr[i] << ((i % 8) * 4); for (i = 0; i < 4; i++) { - nv_wr32(gr, 0x406028 + (i * 4), tmp[i]); - nv_wr32(gr, 0x405870 + (i * 4), tmp[i]); + nvkm_wr32(device, 0x406028 + (i * 4), tmp[i]); + nvkm_wr32(device, 0x405870 + (i * 4), tmp[i]); } } void gf100_grctx_generate_r4060a8(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u8 tpcnr[GPC_MAX], data[TPC_MAX]; int gpc, tpc, i; @@ -1134,12 +1138,13 @@ gf100_grctx_generate_r4060a8(struct gf100_gr *gr) } for (i = 0; i < 4; i++) - nv_wr32(gr, 0x4060a8 + (i * 4), ((u32 *)data)[i]); + nvkm_wr32(device, 0x4060a8 + (i * 4), ((u32 *)data)[i]); } void gf100_grctx_generate_r418bb8(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 data[6] = {}, data2[2] = {}; u8 tpcnr[GPC_MAX]; u8 shift, ntpcv; @@ -1176,28 +1181,29 @@ gf100_grctx_generate_r418bb8(struct gf100_gr *gr) data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); /* GPC_BROADCAST */ - nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) | + nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(gr, 0x418b08 + (i * 4), data[i]); + nvkm_wr32(device, 0x418b08 + (i * 4), data[i]); /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(gr, 0x419bd0, (gr->tpc_total << 8) | + nvkm_wr32(device, 0x419bd0, (gr->tpc_total << 8) | gr->magic_not_rop_nr | data2[0]); - nv_wr32(gr, 0x419be4, data2[1]); + nvkm_wr32(device, 0x419be4, data2[1]); for (i = 0; i < 6; i++) - nv_wr32(gr, 0x419b00 + (i * 4), data[i]); + nvkm_wr32(device, 0x419b00 + (i * 4), data[i]); /* UNK78xx */ - nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) | + nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(gr, 0x40780c + (i * 4), data[i]); + nvkm_wr32(device, 0x40780c + (i * 4), data[i]); } void gf100_grctx_generate_r406800(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u64 tpc_mask = 0, tpc_set = 0; u8 tpcnr[GPC_MAX]; int gpc, tpc; @@ -1219,11 +1225,11 @@ gf100_grctx_generate_r406800(struct gf100_gr *gr) tpc_set |= 1ULL << ((gpc * 8) + tpc); } - nv_wr32(gr, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); - nv_wr32(gr, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); + nvkm_wr32(device, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); + nvkm_wr32(device, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); if (gr->gpc_nr > 4) { - nv_wr32(gr, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); - nv_wr32(gr, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); + nvkm_wr32(device, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); + nvkm_wr32(device, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); } } } @@ -1231,6 +1237,7 @@ gf100_grctx_generate_r406800(struct gf100_gr *gr) void gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); @@ -1241,7 +1248,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, oclass->tpc); gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(gr, 0x404154, 0x00000000); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); @@ -1255,7 +1262,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_r406800(gr); gf100_gr_icmd(gr, oclass->icmd); - nv_wr32(gr, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, oclass->mthd); nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); } @@ -1264,7 +1271,8 @@ int gf100_grctx_generate(struct gf100_gr *gr) { struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; - struct nvkm_bar *bar = nvkm_bar(gr); + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_bar *bar = device->bar; struct nvkm_gpuobj *chan; struct gf100_grctx info; int ret, i; @@ -1302,8 +1310,8 @@ gf100_grctx_generate(struct gf100_gr *gr) bar->flush(bar); - nv_wr32(gr, 0x100cb8, (chan->addr + 0x1000) >> 8); - nv_wr32(gr, 0x100cbc, 0x80000001); + nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8); + nvkm_wr32(device, 0x100cbc, 0x80000001); nv_wait(gr, 0x100c80, 0x00008000, 0x00008000); /* setup default state for mmio list construction */ @@ -1315,9 +1323,9 @@ gf100_grctx_generate(struct gf100_gr *gr) /* make channel current */ if (gr->firmware) { - nv_wr32(gr, 0x409840, 0x00000030); - nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(gr, 0x409504, 0x00000003); + nvkm_wr32(device, 0x409840, 0x00000030); + nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); + nvkm_wr32(device, 0x409504, 0x00000003); if (!nv_wait(gr, 0x409800, 0x00000010, 0x00000010)) nv_error(gr, "load_ctx timeout\n"); @@ -1327,9 +1335,9 @@ gf100_grctx_generate(struct gf100_gr *gr) nv_wo32(chan, 0x8002c, 0); bar->flush(bar); } else { - nv_wr32(gr, 0x409840, 0x80000000); - nv_wr32(gr, 0x409500, 0x80000000 | chan->addr >> 12); - nv_wr32(gr, 0x409504, 0x00000001); + nvkm_wr32(device, 0x409840, 0x80000000); + nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); + nvkm_wr32(device, 0x409504, 0x00000001); if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) nv_error(gr, "HUB_SET_CHAN timeout\n"); } @@ -1339,8 +1347,8 @@ gf100_grctx_generate(struct gf100_gr *gr) /* trigger a context unload by unsetting the "next channel valid" bit * and faking a context switch interrupt */ - nv_mask(gr, 0x409b04, 0x80000000, 0x00000000); - nv_wr32(gr, 0x409000, 0x00000100); + nvkm_mask(device, 0x409b04, 0x80000000, 0x00000000); + nvkm_wr32(device, 0x409000, 0x00000100); if (!nv_wait(gr, 0x409b00, 0x80000000, 0x00000000)) { nv_error(gr, "grctx template channel unload timeout\n"); ret = -EBUSY; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c index d810a0b97b76..caccfed4ac7c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c @@ -767,12 +767,13 @@ gf108_grctx_generate_attrib(struct gf100_grctx *info) void gf108_grctx_generate_unkn(struct gf100_gr *gr) { - nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001); - nv_mask(gr, 0x41980c, 0x00000010, 0x00000010); - nv_mask(gr, 0x419814, 0x00000004, 0x00000004); - nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000); - nv_mask(gr, 0x405800, 0x08000000, 0x08000000); - nv_mask(gr, 0x419c00, 0x00000008, 0x00000008); + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001); + nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); + nvkm_mask(device, 0x419814, 0x00000004, 0x00000004); + nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); + nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); + nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c index 7970b9d4b908..78f6be2e92db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c @@ -219,6 +219,7 @@ gf117_grctx_generate_attrib(struct gf100_grctx *info) void gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int i; @@ -230,7 +231,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, oclass->tpc); gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(gr, 0x404154, 0x00000000); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); @@ -244,10 +245,10 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_r406800(gr); for (i = 0; i < 8; i++) - nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); + nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); gf100_gr_icmd(gr, oclass->icmd); - nv_wr32(gr, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, oclass->mthd); nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index 7b2a96c6e496..0365acaf8c70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -874,17 +874,19 @@ gk104_grctx_generate_pagepool(struct gf100_grctx *info) void gk104_grctx_generate_unkn(struct gf100_gr *gr) { - nv_mask(gr, 0x418c6c, 0x00000001, 0x00000001); - nv_mask(gr, 0x41980c, 0x00000010, 0x00000010); - nv_mask(gr, 0x41be08, 0x00000004, 0x00000004); - nv_mask(gr, 0x4064c0, 0x80000000, 0x80000000); - nv_mask(gr, 0x405800, 0x08000000, 0x08000000); - nv_mask(gr, 0x419c00, 0x00000008, 0x00000008); + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_mask(device, 0x418c6c, 0x00000001, 0x00000001); + nvkm_mask(device, 0x41980c, 0x00000010, 0x00000010); + nvkm_mask(device, 0x41be08, 0x00000004, 0x00000004); + nvkm_mask(device, 0x4064c0, 0x80000000, 0x80000000); + nvkm_mask(device, 0x405800, 0x08000000, 0x08000000); + nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); } void gk104_grctx_generate_r418bb8(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 data[6] = {}, data2[2] = {}; u8 tpcnr[GPC_MAX]; u8 shift, ntpcv; @@ -921,36 +923,38 @@ gk104_grctx_generate_r418bb8(struct gf100_gr *gr) data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); /* GPC_BROADCAST */ - nv_wr32(gr, 0x418bb8, (gr->tpc_total << 8) | + nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(gr, 0x418b08 + (i * 4), data[i]); + nvkm_wr32(device, 0x418b08 + (i * 4), data[i]); /* GPC_BROADCAST.TP_BROADCAST */ - nv_wr32(gr, 0x41bfd0, (gr->tpc_total << 8) | + nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | gr->magic_not_rop_nr | data2[0]); - nv_wr32(gr, 0x41bfe4, data2[1]); + nvkm_wr32(device, 0x41bfe4, data2[1]); for (i = 0; i < 6; i++) - nv_wr32(gr, 0x41bf00 + (i * 4), data[i]); + nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]); /* UNK78xx */ - nv_wr32(gr, 0x4078bc, (gr->tpc_total << 8) | + nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | gr->magic_not_rop_nr); for (i = 0; i < 6; i++) - nv_wr32(gr, 0x40780c + (i * 4), data[i]); + nvkm_wr32(device, 0x40780c + (i * 4), data[i]); } void gk104_grctx_generate_rop_active_fbps(struct gf100_gr *gr) { - const u32 fbp_count = nv_rd32(gr, 0x120074); - nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */ - nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */ + struct nvkm_device *device = gr->base.engine.subdev.device; + const u32 fbp_count = nvkm_rd32(device, 0x120074); + nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ + nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ } void gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int i; @@ -962,7 +966,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, oclass->tpc); gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(gr, 0x404154, 0x00000000); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); @@ -975,19 +979,19 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_r406800(gr); for (i = 0; i < 8; i++) - nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); + nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); + nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gk104_grctx_generate_rop_active_fbps(gr); - nv_mask(gr, 0x419f78, 0x00000001, 0x00000000); + nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); gf100_gr_icmd(gr, oclass->icmd); - nv_wr32(gr, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, oclass->mthd); nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); - nv_mask(gr, 0x418800, 0x00200000, 0x00200000); - nv_mask(gr, 0x41be10, 0x00800000, 0x00800000); + nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); + nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 91e4aacfdec7..252bcc331a5a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -28,6 +28,7 @@ static void gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int idle_timeout_save; int i; @@ -36,8 +37,8 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_wait_idle(gr); - idle_timeout_save = nv_rd32(gr, 0x404154); - nv_wr32(gr, 0x404154, 0x00000000); + idle_timeout_save = nvkm_rd32(device, 0x404154); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->attrib(info); @@ -49,17 +50,17 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_r406800(gr); for (i = 0; i < 8; i++) - nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); + nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); + nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gk104_grctx_generate_rop_active_fbps(gr); - nv_mask(gr, 0x5044b0, 0x8000000, 0x8000000); + nvkm_mask(device, 0x5044b0, 0x8000000, 0x8000000); gf100_gr_wait_idle(gr); - nv_wr32(gr, 0x404154, idle_timeout_save); + nvkm_wr32(device, 0x404154, idle_timeout_save); gf100_gr_wait_idle(gr); gf100_gr_mthd(gr, gr->fuc_method); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 0d908a123170..9c361ee21fbf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -934,19 +934,20 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info) void gm107_grctx_generate_tpcid(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) { if (tpc < gr->tpc_nr[gpc]) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); id++; } - nv_wr32(gr, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); } } } @@ -954,6 +955,7 @@ gm107_grctx_generate_tpcid(struct gf100_gr *gr) static void gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int i; @@ -963,7 +965,7 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, oclass->tpc); gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(gr, 0x404154, 0x00000000); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); @@ -975,23 +977,23 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_r418bb8(gr); gf100_grctx_generate_r406800(gr); - nv_wr32(gr, 0x4064d0, 0x00000001); + nvkm_wr32(device, 0x4064d0, 0x00000001); for (i = 1; i < 8; i++) - nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(gr, 0x406500, 0x00000001); + nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); + nvkm_wr32(device, 0x406500, 0x00000001); - nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); + nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gk104_grctx_generate_rop_active_fbps(gr); gf100_gr_icmd(gr, oclass->icmd); - nv_wr32(gr, 0x404154, 0x00000400); + nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, oclass->mthd); - nv_mask(gr, 0x419e00, 0x00808080, 0x00808080); - nv_mask(gr, 0x419ccc, 0x80000000, 0x80000000); - nv_mask(gr, 0x419f80, 0x80000000, 0x80000000); - nv_mask(gr, 0x419f88, 0x80000000, 0x80000000); + nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); + nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); + nvkm_mask(device, 0x419f80, 0x80000000, 0x80000000); + nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c index 93f38bdfd0cc..f8c2432b7d7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c @@ -921,14 +921,15 @@ gm204_grctx_pack_ppc[] = { void gm204_grctx_generate_tpcid(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; int gpc, tpc, id; for (tpc = 0, id = 0; tpc < 4; tpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) { if (tpc < gr->tpc_nr[gpc]) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x698), id); - nv_wr32(gr, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x088), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); id++; } } @@ -938,14 +939,16 @@ gm204_grctx_generate_tpcid(struct gf100_gr *gr) static void gm204_grctx_generate_rop_active_fbps(struct gf100_gr *gr) { - const u32 fbp_count = nv_rd32(gr, 0x12006c); - nv_mask(gr, 0x408850, 0x0000000f, fbp_count); /* zrop */ - nv_mask(gr, 0x408958, 0x0000000f, fbp_count); /* crop */ + struct nvkm_device *device = gr->base.engine.subdev.device; + const u32 fbp_count = nvkm_rd32(device, 0x12006c); + nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ + nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ } void gm204_grctx_generate_405b60(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; const u32 dist_nr = DIV_ROUND_UP(gr->tpc_total, 4); u32 dist[TPC_MAX / 4] = {}; u32 gpcs[GPC_MAX] = {}; @@ -969,14 +972,15 @@ gm204_grctx_generate_405b60(struct gf100_gr *gr) } for (i = 0; i < dist_nr; i++) - nv_wr32(gr, 0x405b60 + (i * 4), dist[i]); + nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]); for (i = 0; i < gr->gpc_nr; i++) - nv_wr32(gr, 0x405ba0 + (i * 4), gpcs[i]); + nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]); } void gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; u32 tmp; int i; @@ -987,7 +991,7 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_mmio(gr, oclass->tpc); gf100_gr_mmio(gr, oclass->ppc); - nv_wr32(gr, 0x404154, 0x00000000); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->bundle(info); oclass->pagepool(info); @@ -999,25 +1003,25 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_r418bb8(gr); for (i = 0; i < 8; i++) - nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(gr, 0x406500, 0x00000000); + nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); + nvkm_wr32(device, 0x406500, 0x00000000); - nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); + nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gm204_grctx_generate_rop_active_fbps(gr); for (tmp = 0, i = 0; i < gr->gpc_nr; i++) tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); - nv_wr32(gr, 0x4041c4, tmp); + nvkm_wr32(device, 0x4041c4, tmp); gm204_grctx_generate_405b60(gr); gf100_gr_icmd(gr, oclass->icmd); - nv_wr32(gr, 0x404154, 0x00000800); + nvkm_wr32(device, 0x404154, 0x00000800); gf100_gr_mthd(gr, oclass->mthd); - nv_mask(gr, 0x418e94, 0xffffffff, 0xc4230000); - nv_mask(gr, 0x418e4c, 0xffffffff, 0x70000000); + nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000); + nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c index c44b2e157ec2..5f5affc55fe0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c @@ -24,19 +24,21 @@ static void gm20b_grctx_generate_r406028(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 tpc_per_gpc = 0; int i; for (i = 0; i < gr->gpc_nr; i++) tpc_per_gpc |= gr->tpc_nr[i] << (4 * i); - nv_wr32(gr, 0x406028, tpc_per_gpc); - nv_wr32(gr, 0x405870, tpc_per_gpc); + nvkm_wr32(device, 0x406028, tpc_per_gpc); + nvkm_wr32(device, 0x405870, tpc_per_gpc); } static void gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; int idle_timeout_save; int i, tmp; @@ -45,8 +47,8 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_wait_idle(gr); - idle_timeout_save = nv_rd32(gr, 0x404154); - nv_wr32(gr, 0x404154, 0x00000000); + idle_timeout_save = nvkm_rd32(device, 0x404154); + nvkm_wr32(device, 0x404154, 0x00000000); oclass->attrib(info); @@ -57,22 +59,22 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_r418bb8(gr); for (i = 0; i < 8; i++) - nv_wr32(gr, 0x4064d0 + (i * 0x04), 0x00000000); + nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); - nv_wr32(gr, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); + nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); gk104_grctx_generate_rop_active_fbps(gr); - nv_wr32(gr, 0x408908, nv_rd32(gr, 0x410108) | 0x80000000); + nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); for (tmp = 0, i = 0; i < gr->gpc_nr; i++) tmp |= ((1 << gr->tpc_nr[i]) - 1) << (i * 4); - nv_wr32(gr, 0x4041c4, tmp); + nvkm_wr32(device, 0x4041c4, tmp); gm204_grctx_generate_405b60(gr); gf100_gr_wait_idle(gr); - nv_wr32(gr, 0x404154, idle_timeout_save); + nvkm_wr32(device, 0x404154, idle_timeout_save); gf100_gr_wait_idle(gr); gf100_gr_mthd(gr, gr->fuc_method); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c index a3b0b366f582..0c717084b44f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c @@ -683,9 +683,9 @@ nv40_grctx_init(struct nvkm_device *device, u32 *size) nv40_grctx_generate(&ctx); - nv_wr32(device, 0x400324, 0); + nvkm_wr32(device, 0x400324, 0); for (i = 0; i < ctx.ctxprog_len; i++) - nv_wr32(device, 0x400328, ctxprog[i]); + nvkm_wr32(device, 0x400328, ctxprog[i]); *size = ctx.ctxvals_pos * 4; kfree(ctxprog); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index a9a4e0e3f2cb..e76bf4a217dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -276,9 +276,9 @@ nv50_grctx_init(struct nvkm_device *device, u32 *size) return -ENOMEM; nv50_grctx_generate(&ctx); - nv_wr32(device, 0x400324, 0); + nvkm_wr32(device, 0x400324, 0); for (i = 0; i < ctx.ctxprog_len; i++) - nv_wr32(device, 0x400328, ctxprog[i]); + nvkm_wr32(device, 0x400328, ctxprog[i]); *size = ctx.ctxvals_pos * 4; kfree(ctxprog); return 0; @@ -298,7 +298,7 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx) struct nvkm_device *device = ctx->device; int i, j; int offset, base; - u32 units = nv_rd32 (ctx->device, 0x1540); + u32 units = nvkm_rd32(device, 0x1540); /* 0800: DISPATCH */ cp_ctx(ctx, 0x400808, 7); @@ -1189,7 +1189,7 @@ nv50_gr_construct_xfer1(struct nvkm_grctx *ctx) int i; int offset; int size = 0; - u32 units = nv_rd32 (ctx->device, 0x1540); + u32 units = nvkm_rd32(device, 0x1540); offset = (ctx->ctxvals_pos+0x3f)&~0x3f; ctx->ctxvals_base = offset; @@ -3272,7 +3272,7 @@ nv50_gr_construct_xfer2(struct nvkm_grctx *ctx) struct nvkm_device *device = ctx->device; int i; u32 offset; - u32 units = nv_rd32 (ctx->device, 0x1540); + u32 units = nvkm_rd32(device, 0x1540); int size = 0; offset = (ctx->ctxvals_pos+0x3f)&~0x3f; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index c1b84a687f76..b692e8e2b982 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -43,15 +43,16 @@ static void gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) { + struct nvkm_device *device = gr->base.engine.subdev.device; if (gr->zbc_color[zbc].format) { - nv_wr32(gr, 0x405804, gr->zbc_color[zbc].ds[0]); - nv_wr32(gr, 0x405808, gr->zbc_color[zbc].ds[1]); - nv_wr32(gr, 0x40580c, gr->zbc_color[zbc].ds[2]); - nv_wr32(gr, 0x405810, gr->zbc_color[zbc].ds[3]); - } - nv_wr32(gr, 0x405814, gr->zbc_color[zbc].format); - nv_wr32(gr, 0x405820, zbc); - nv_wr32(gr, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ + nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); + nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); + nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); + nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); + } + nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); + nvkm_wr32(device, 0x405820, zbc); + nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ } static int @@ -93,11 +94,12 @@ gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, static void gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) { + struct nvkm_device *device = gr->base.engine.subdev.device; if (gr->zbc_depth[zbc].format) - nv_wr32(gr, 0x405818, gr->zbc_depth[zbc].ds); - nv_wr32(gr, 0x40581c, gr->zbc_depth[zbc].format); - nv_wr32(gr, 0x405820, zbc); - nv_wr32(gr, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ + nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); + nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); + nvkm_wr32(device, 0x405820, zbc); + nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ } static int @@ -236,10 +238,11 @@ gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, void *pdata, u32 size) { struct gf100_gr *gr = (void *)object->engine; + struct nvkm_device *device = gr->base.engine.subdev.device; if (size >= sizeof(u32)) { u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; - nv_wr32(gr, 0x419e44, data); - nv_wr32(gr, 0x419e4c, data); + nvkm_wr32(device, 0x419e44, data); + nvkm_wr32(device, 0x419e4c, data); return 0; } return -EINVAL; @@ -670,6 +673,7 @@ gf100_gr_zbc_init(struct gf100_gr *gr) int gf100_gr_wait_idle(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); bool gr_enabled, ctxsw_active, gr_busy; @@ -678,11 +682,11 @@ gf100_gr_wait_idle(struct gf100_gr *gr) * required to make sure FIFO_ENGINE_STATUS (0x2640) is * up-to-date */ - nv_rd32(gr, 0x400700); + nvkm_rd32(device, 0x400700); - gr_enabled = nv_rd32(gr, 0x200) & 0x1000; - ctxsw_active = nv_rd32(gr, 0x2640) & 0x8000; - gr_busy = nv_rd32(gr, 0x40060c) & 0x1; + gr_enabled = nvkm_rd32(device, 0x200) & 0x1000; + ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000; + gr_busy = nvkm_rd32(device, 0x40060c) & 0x1; if (!gr_enabled || (!gr_busy && !ctxsw_active)) return 0; @@ -696,6 +700,7 @@ gf100_gr_wait_idle(struct gf100_gr *gr) void gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) { + struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_gr_pack *pack; const struct gf100_gr_init *init; @@ -703,7 +708,7 @@ gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) u32 next = init->addr + init->count * init->pitch; u32 addr = init->addr; while (addr < next) { - nv_wr32(gr, addr, init->data); + nvkm_wr32(device, addr, init->data); addr += init->pitch; } } @@ -712,23 +717,24 @@ gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p) void gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) { + struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_gr_pack *pack; const struct gf100_gr_init *init; u32 data = 0; - nv_wr32(gr, 0x400208, 0x80000000); + nvkm_wr32(device, 0x400208, 0x80000000); pack_for_each_init(init, pack, p) { u32 next = init->addr + init->count * init->pitch; u32 addr = init->addr; if ((pack == p && init == p->init) || data != init->data) { - nv_wr32(gr, 0x400204, init->data); + nvkm_wr32(device, 0x400204, init->data); data = init->data; } while (addr < next) { - nv_wr32(gr, 0x400200, addr); + nvkm_wr32(device, 0x400200, addr); /** * Wait for GR to go idle after submitting a * GO_IDLE bundle @@ -740,12 +746,13 @@ gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) } } - nv_wr32(gr, 0x400208, 0x00000000); + nvkm_wr32(device, 0x400208, 0x00000000); } void gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) { + struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_gr_pack *pack; const struct gf100_gr_init *init; u32 data = 0; @@ -756,12 +763,12 @@ gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) u32 addr = init->addr; if ((pack == p && init == p->init) || data != init->data) { - nv_wr32(gr, 0x40448c, init->data); + nvkm_wr32(device, 0x40448c, init->data); data = init->data; } while (addr < next) { - nv_wr32(gr, 0x404488, ctrl | (addr << 14)); + nvkm_wr32(device, 0x404488, ctrl | (addr << 14)); addr += init->pitch; } } @@ -808,13 +815,14 @@ static const struct nvkm_enum gf100_gpc_rop_error[] = { static void gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 trap[4]; int i; - trap[0] = nv_rd32(gr, GPC_UNIT(gpc, 0x0420)); - trap[1] = nv_rd32(gr, GPC_UNIT(gpc, 0x0434)); - trap[2] = nv_rd32(gr, GPC_UNIT(gpc, 0x0438)); - trap[3] = nv_rd32(gr, GPC_UNIT(gpc, 0x043c)); + trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)); + trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); + trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); + trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); nv_error(gr, "GPC%d/PROP trap:", gpc); for (i = 0; i <= 29; ++i) { @@ -828,7 +836,7 @@ gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n", trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, trap[3] & 0xff); - nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); } static const struct nvkm_enum gf100_mp_warp_error[] = { @@ -853,8 +861,9 @@ static const struct nvkm_bitfield gf100_mp_global_error[] = { static void gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) { - u32 werr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x648)); - u32 gerr = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x650)); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); + u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc); nvkm_bitfield_print(gf100_mp_global_error, gerr); @@ -864,19 +873,20 @@ gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) } pr_cont("\n"); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x650), gerr); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); } static void gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) { - u32 stat = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0508)); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); if (stat & 0x00000001) { - u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0224)); + u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); stat &= ~0x00000001; } @@ -886,16 +896,16 @@ gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) } if (stat & 0x00000004) { - u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x0084)); + u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); stat &= ~0x00000004; } if (stat & 0x00000008) { - u32 trap = nv_rd32(gr, TPC_UNIT(gpc, tpc, 0x048c)); + u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); stat &= ~0x00000008; } @@ -907,7 +917,8 @@ gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) static void gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) { - u32 stat = nv_rd32(gr, GPC_UNIT(gpc, 0x2c90)); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); int tpc; if (stat & 0x00000001) { @@ -916,23 +927,23 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) } if (stat & 0x00000002) { - u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0900)); + u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); - nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); stat &= ~0x00000002; } if (stat & 0x00000004) { - u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x1028)); + u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); - nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); stat &= ~0x00000004; } if (stat & 0x00000008) { - u32 trap = nv_rd32(gr, GPC_UNIT(gpc, 0x0824)); + u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); - nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); stat &= ~0x00000009; } @@ -940,7 +951,7 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) u32 mask = 0x00010000 << tpc; if (stat & mask) { gf100_gr_trap_tpc(gr, gpc, tpc); - nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), mask); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask); stat &= ~mask; } } @@ -953,59 +964,60 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) static void gf100_gr_trap_intr(struct gf100_gr *gr) { - u32 trap = nv_rd32(gr, 0x400108); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 trap = nvkm_rd32(device, 0x400108); int rop, gpc, i; if (trap & 0x00000001) { - u32 stat = nv_rd32(gr, 0x404000); + u32 stat = nvkm_rd32(device, 0x404000); nv_error(gr, "DISPATCH 0x%08x\n", stat); - nv_wr32(gr, 0x404000, 0xc0000000); - nv_wr32(gr, 0x400108, 0x00000001); + nvkm_wr32(device, 0x404000, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x00000001); trap &= ~0x00000001; } if (trap & 0x00000002) { - u32 stat = nv_rd32(gr, 0x404600); + u32 stat = nvkm_rd32(device, 0x404600); nv_error(gr, "M2MF 0x%08x\n", stat); - nv_wr32(gr, 0x404600, 0xc0000000); - nv_wr32(gr, 0x400108, 0x00000002); + nvkm_wr32(device, 0x404600, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x00000002); trap &= ~0x00000002; } if (trap & 0x00000008) { - u32 stat = nv_rd32(gr, 0x408030); + u32 stat = nvkm_rd32(device, 0x408030); nv_error(gr, "CCACHE 0x%08x\n", stat); - nv_wr32(gr, 0x408030, 0xc0000000); - nv_wr32(gr, 0x400108, 0x00000008); + nvkm_wr32(device, 0x408030, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x00000008); trap &= ~0x00000008; } if (trap & 0x00000010) { - u32 stat = nv_rd32(gr, 0x405840); + u32 stat = nvkm_rd32(device, 0x405840); nv_error(gr, "SHADER 0x%08x\n", stat); - nv_wr32(gr, 0x405840, 0xc0000000); - nv_wr32(gr, 0x400108, 0x00000010); + nvkm_wr32(device, 0x405840, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x00000010); trap &= ~0x00000010; } if (trap & 0x00000040) { - u32 stat = nv_rd32(gr, 0x40601c); + u32 stat = nvkm_rd32(device, 0x40601c); nv_error(gr, "UNK6 0x%08x\n", stat); - nv_wr32(gr, 0x40601c, 0xc0000000); - nv_wr32(gr, 0x400108, 0x00000040); + nvkm_wr32(device, 0x40601c, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x00000040); trap &= ~0x00000040; } if (trap & 0x00000080) { - u32 stat = nv_rd32(gr, 0x404490); + u32 stat = nvkm_rd32(device, 0x404490); nv_error(gr, "MACRO 0x%08x\n", stat); - nv_wr32(gr, 0x404490, 0xc0000000); - nv_wr32(gr, 0x400108, 0x00000080); + nvkm_wr32(device, 0x404490, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x00000080); trap &= ~0x00000080; } if (trap & 0x00000100) { - u32 stat = nv_rd32(gr, 0x407020); + u32 stat = nvkm_rd32(device, 0x407020); nv_error(gr, "SKED:"); for (i = 0; i <= 29; ++i) { @@ -1017,61 +1029,63 @@ gf100_gr_trap_intr(struct gf100_gr *gr) pr_cont("\n"); if (stat & 0x3fffffff) - nv_wr32(gr, 0x407020, 0x40000000); - nv_wr32(gr, 0x400108, 0x00000100); + nvkm_wr32(device, 0x407020, 0x40000000); + nvkm_wr32(device, 0x400108, 0x00000100); trap &= ~0x00000100; } if (trap & 0x01000000) { - u32 stat = nv_rd32(gr, 0x400118); + u32 stat = nvkm_rd32(device, 0x400118); for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) { u32 mask = 0x00000001 << gpc; if (stat & mask) { gf100_gr_trap_gpc(gr, gpc); - nv_wr32(gr, 0x400118, mask); + nvkm_wr32(device, 0x400118, mask); stat &= ~mask; } } - nv_wr32(gr, 0x400108, 0x01000000); + nvkm_wr32(device, 0x400108, 0x01000000); trap &= ~0x01000000; } if (trap & 0x02000000) { for (rop = 0; rop < gr->rop_nr; rop++) { - u32 statz = nv_rd32(gr, ROP_UNIT(rop, 0x070)); - u32 statc = nv_rd32(gr, ROP_UNIT(rop, 0x144)); + u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); + u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); nv_error(gr, "ROP%d 0x%08x 0x%08x\n", rop, statz, statc); - nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); } - nv_wr32(gr, 0x400108, 0x02000000); + nvkm_wr32(device, 0x400108, 0x02000000); trap &= ~0x02000000; } if (trap) { nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap); - nv_wr32(gr, 0x400108, trap); + nvkm_wr32(device, 0x400108, trap); } } static void gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) { + struct nvkm_device *device = gr->base.engine.subdev.device; nv_error(gr, "%06x - done 0x%08x\n", base, - nv_rd32(gr, base + 0x400)); + nvkm_rd32(device, base + 0x400)); nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(gr, base + 0x800), nv_rd32(gr, base + 0x804), - nv_rd32(gr, base + 0x808), nv_rd32(gr, base + 0x80c)); + nvkm_rd32(device, base + 0x800), nvkm_rd32(device, base + 0x804), + nvkm_rd32(device, base + 0x808), nvkm_rd32(device, base + 0x80c)); nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nv_rd32(gr, base + 0x810), nv_rd32(gr, base + 0x814), - nv_rd32(gr, base + 0x818), nv_rd32(gr, base + 0x81c)); + nvkm_rd32(device, base + 0x810), nvkm_rd32(device, base + 0x814), + nvkm_rd32(device, base + 0x818), nvkm_rd32(device, base + 0x81c)); } void gf100_gr_ctxctl_debug(struct gf100_gr *gr) { - u32 gpcnr = nv_rd32(gr, 0x409604) & 0xffff; + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff; u32 gpc; gf100_gr_ctxctl_debug_unit(gr, 0x409000); @@ -1082,22 +1096,23 @@ gf100_gr_ctxctl_debug(struct gf100_gr *gr) static void gf100_gr_ctxctl_isr(struct gf100_gr *gr) { - u32 stat = nv_rd32(gr, 0x409c18); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, 0x409c18); if (stat & 0x00000001) { - u32 code = nv_rd32(gr, 0x409814); + u32 code = nvkm_rd32(device, 0x409814); if (code == E_BAD_FWMTHD) { - u32 class = nv_rd32(gr, 0x409808); - u32 addr = nv_rd32(gr, 0x40980c); + u32 class = nvkm_rd32(device, 0x409808); + u32 addr = nvkm_rd32(device, 0x40980c); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00003ffc); - u32 data = nv_rd32(gr, 0x409810); + u32 data = nvkm_rd32(device, 0x409810); nv_error(gr, "FECS MTHD subc %d class 0x%04x " "mthd 0x%04x data 0x%08x\n", subc, class, mthd, data); - nv_wr32(gr, 0x409c20, 0x00000001); + nvkm_wr32(device, 0x409c20, 0x00000001); stat &= ~0x00000001; } else { nv_error(gr, "FECS ucode error %d\n", code); @@ -1107,37 +1122,38 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr) if (stat & 0x00080000) { nv_error(gr, "FECS watchdog timeout\n"); gf100_gr_ctxctl_debug(gr); - nv_wr32(gr, 0x409c20, 0x00080000); + nvkm_wr32(device, 0x409c20, 0x00080000); stat &= ~0x00080000; } if (stat) { nv_error(gr, "FECS 0x%08x\n", stat); gf100_gr_ctxctl_debug(gr); - nv_wr32(gr, 0x409c20, stat); + nvkm_wr32(device, 0x409c20, stat); } } static void gf100_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *fifo = nvkm_fifo(subdev); + struct gf100_gr *gr = (void *)subdev; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo *fifo = device->fifo; struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle; - struct gf100_gr *gr = (void *)subdev; - u64 inst = nv_rd32(gr, 0x409b00) & 0x0fffffff; - u32 stat = nv_rd32(gr, 0x400100); - u32 addr = nv_rd32(gr, 0x400704); + u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; + u32 stat = nvkm_rd32(device, 0x400100); + u32 addr = nvkm_rd32(device, 0x400704); u32 mthd = (addr & 0x00003ffc); u32 subc = (addr & 0x00070000) >> 16; - u32 data = nv_rd32(gr, 0x400708); - u32 code = nv_rd32(gr, 0x400110); + u32 data = nvkm_rd32(device, 0x400708); + u32 code = nvkm_rd32(device, 0x400110); u32 class; int chid; if (nv_device(gr)->card_type < NV_E0 || subc < 4) - class = nv_rd32(gr, 0x404200 + (subc * 4)); + class = nvkm_rd32(device, 0x404200 + (subc * 4)); else class = 0x0000; @@ -1149,7 +1165,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) * notifier interrupt, only needed for cyclestats * can be safely ignored */ - nv_wr32(gr, 0x400100, 0x00000001); + nvkm_wr32(device, 0x400100, 0x00000001); stat &= ~0x00000001; } @@ -1162,7 +1178,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) subc, class, mthd, data); } nvkm_handle_put(handle); - nv_wr32(gr, 0x400100, 0x00000010); + nvkm_wr32(device, 0x400100, 0x00000010); stat &= ~0x00000010; } @@ -1171,7 +1187,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); - nv_wr32(gr, 0x400100, 0x00000020); + nvkm_wr32(device, 0x400100, 0x00000020); stat &= ~0x00000020; } @@ -1181,7 +1197,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", chid, inst << 12, nvkm_client_name(engctx), subc, class, mthd, data); - nv_wr32(gr, 0x400100, 0x00100000); + nvkm_wr32(device, 0x400100, 0x00100000); stat &= ~0x00100000; } @@ -1189,22 +1205,22 @@ gf100_gr_intr(struct nvkm_subdev *subdev) nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, nvkm_client_name(engctx)); gf100_gr_trap_intr(gr); - nv_wr32(gr, 0x400100, 0x00200000); + nvkm_wr32(device, 0x400100, 0x00200000); stat &= ~0x00200000; } if (stat & 0x00080000) { gf100_gr_ctxctl_isr(gr); - nv_wr32(gr, 0x400100, 0x00080000); + nvkm_wr32(device, 0x400100, 0x00080000); stat &= ~0x00080000; } if (stat) { nv_error(gr, "unknown stat 0x%08x\n", stat); - nv_wr32(gr, 0x400100, stat); + nvkm_wr32(device, 0x400100, stat); } - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400500, 0x00010001); nvkm_engctx_put(engctx); } @@ -1212,22 +1228,23 @@ void gf100_gr_init_fw(struct gf100_gr *gr, u32 fuc_base, struct gf100_gr_fuc *code, struct gf100_gr_fuc *data) { + struct nvkm_device *device = gr->base.engine.subdev.device; int i; - nv_wr32(gr, fuc_base + 0x01c0, 0x01000000); + nvkm_wr32(device, fuc_base + 0x01c0, 0x01000000); for (i = 0; i < data->size / 4; i++) - nv_wr32(gr, fuc_base + 0x01c4, data->data[i]); + nvkm_wr32(device, fuc_base + 0x01c4, data->data[i]); - nv_wr32(gr, fuc_base + 0x0180, 0x01000000); + nvkm_wr32(device, fuc_base + 0x0180, 0x01000000); for (i = 0; i < code->size / 4; i++) { if ((i & 0x3f) == 0) - nv_wr32(gr, fuc_base + 0x0188, i >> 6); - nv_wr32(gr, fuc_base + 0x0184, code->data[i]); + nvkm_wr32(device, fuc_base + 0x0188, i >> 6); + nvkm_wr32(device, fuc_base + 0x0184, code->data[i]); } /* code must be padded to 0x40 words */ for (; i & 0x3f; i++) - nv_wr32(gr, fuc_base + 0x0184, 0); + nvkm_wr32(device, fuc_base + 0x0184, 0); } static void @@ -1235,17 +1252,18 @@ gf100_gr_init_csdata(struct gf100_gr *gr, const struct gf100_gr_pack *pack, u32 falcon, u32 starstar, u32 base) { + struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_gr_pack *iter; const struct gf100_gr_init *init; u32 addr = ~0, prev = ~0, xfer = 0; u32 star, temp; - nv_wr32(gr, falcon + 0x01c0, 0x02000000 + starstar); - star = nv_rd32(gr, falcon + 0x01c4); - temp = nv_rd32(gr, falcon + 0x01c4); + nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar); + star = nvkm_rd32(device, falcon + 0x01c4); + temp = nvkm_rd32(device, falcon + 0x01c4); if (temp > star) star = temp; - nv_wr32(gr, falcon + 0x01c0, 0x01000000 + star); + nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star); pack_for_each_init(init, iter, pack) { u32 head = init->addr - base; @@ -1254,7 +1272,7 @@ gf100_gr_init_csdata(struct gf100_gr *gr, if (head != prev + 4 || xfer >= 32) { if (xfer) { u32 data = ((--xfer << 26) | addr); - nv_wr32(gr, falcon + 0x01c4, data); + nvkm_wr32(device, falcon + 0x01c4, data); star += 4; } addr = head; @@ -1266,14 +1284,15 @@ gf100_gr_init_csdata(struct gf100_gr *gr, } } - nv_wr32(gr, falcon + 0x01c4, (--xfer << 26) | addr); - nv_wr32(gr, falcon + 0x01c0, 0x01000004 + starstar); - nv_wr32(gr, falcon + 0x01c4, star + 4); + nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr); + nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar); + nvkm_wr32(device, falcon + 0x01c4, star + 4); } int gf100_gr_init_ctxctl(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; int i; @@ -1288,73 +1307,73 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); /* start both of them running */ - nv_wr32(gr, 0x409840, 0xffffffff); - nv_wr32(gr, 0x41a10c, 0x00000000); - nv_wr32(gr, 0x40910c, 0x00000000); - nv_wr32(gr, 0x41a100, 0x00000002); - nv_wr32(gr, 0x409100, 0x00000002); + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x41a10c, 0x00000000); + nvkm_wr32(device, 0x40910c, 0x00000000); + nvkm_wr32(device, 0x41a100, 0x00000002); + nvkm_wr32(device, 0x409100, 0x00000002); if (!nv_wait(gr, 0x409800, 0x00000001, 0x00000001)) nv_warn(gr, "0x409800 wait failed\n"); - nv_wr32(gr, 0x409840, 0xffffffff); - nv_wr32(gr, 0x409500, 0x7fffffff); - nv_wr32(gr, 0x409504, 0x00000021); + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x7fffffff); + nvkm_wr32(device, 0x409504, 0x00000021); - nv_wr32(gr, 0x409840, 0xffffffff); - nv_wr32(gr, 0x409500, 0x00000000); - nv_wr32(gr, 0x409504, 0x00000010); + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x00000000); + nvkm_wr32(device, 0x409504, 0x00000010); if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { nv_error(gr, "fuc09 req 0x10 timeout\n"); return -EBUSY; } - gr->size = nv_rd32(gr, 0x409800); + gr->size = nvkm_rd32(device, 0x409800); - nv_wr32(gr, 0x409840, 0xffffffff); - nv_wr32(gr, 0x409500, 0x00000000); - nv_wr32(gr, 0x409504, 0x00000016); + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x00000000); + nvkm_wr32(device, 0x409504, 0x00000016); if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { nv_error(gr, "fuc09 req 0x16 timeout\n"); return -EBUSY; } - nv_wr32(gr, 0x409840, 0xffffffff); - nv_wr32(gr, 0x409500, 0x00000000); - nv_wr32(gr, 0x409504, 0x00000025); + nvkm_wr32(device, 0x409840, 0xffffffff); + nvkm_wr32(device, 0x409500, 0x00000000); + nvkm_wr32(device, 0x409504, 0x00000025); if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { nv_error(gr, "fuc09 req 0x25 timeout\n"); return -EBUSY; } if (nv_device(gr)->chipset >= 0xe0) { - nv_wr32(gr, 0x409800, 0x00000000); - nv_wr32(gr, 0x409500, 0x00000001); - nv_wr32(gr, 0x409504, 0x00000030); + nvkm_wr32(device, 0x409800, 0x00000000); + nvkm_wr32(device, 0x409500, 0x00000001); + nvkm_wr32(device, 0x409504, 0x00000030); if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { nv_error(gr, "fuc09 req 0x30 timeout\n"); return -EBUSY; } - nv_wr32(gr, 0x409810, 0xb00095c8); - nv_wr32(gr, 0x409800, 0x00000000); - nv_wr32(gr, 0x409500, 0x00000001); - nv_wr32(gr, 0x409504, 0x00000031); + nvkm_wr32(device, 0x409810, 0xb00095c8); + nvkm_wr32(device, 0x409800, 0x00000000); + nvkm_wr32(device, 0x409500, 0x00000001); + nvkm_wr32(device, 0x409504, 0x00000031); if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { nv_error(gr, "fuc09 req 0x31 timeout\n"); return -EBUSY; } - nv_wr32(gr, 0x409810, 0x00080420); - nv_wr32(gr, 0x409800, 0x00000000); - nv_wr32(gr, 0x409500, 0x00000001); - nv_wr32(gr, 0x409504, 0x00000032); + nvkm_wr32(device, 0x409810, 0x00080420); + nvkm_wr32(device, 0x409800, 0x00000000); + nvkm_wr32(device, 0x409500, 0x00000001); + nvkm_wr32(device, 0x409504, 0x00000032); if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { nv_error(gr, "fuc09 req 0x32 timeout\n"); return -EBUSY; } - nv_wr32(gr, 0x409614, 0x00000070); - nv_wr32(gr, 0x409614, 0x00000770); - nv_wr32(gr, 0x40802c, 0x00000001); + nvkm_wr32(device, 0x409614, 0x00000070); + nvkm_wr32(device, 0x409614, 0x00000770); + nvkm_wr32(device, 0x40802c, 0x00000001); } if (gr->data == NULL) { @@ -1373,27 +1392,27 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) /* load HUB microcode */ nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - nv_wr32(gr, 0x4091c0, 0x01000000); + nvkm_wr32(device, 0x4091c0, 0x01000000); for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) - nv_wr32(gr, 0x4091c4, oclass->fecs.ucode->data.data[i]); + nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); - nv_wr32(gr, 0x409180, 0x01000000); + nvkm_wr32(device, 0x409180, 0x01000000); for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) - nv_wr32(gr, 0x409188, i >> 6); - nv_wr32(gr, 0x409184, oclass->fecs.ucode->code.data[i]); + nvkm_wr32(device, 0x409188, i >> 6); + nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); } /* load GPC microcode */ - nv_wr32(gr, 0x41a1c0, 0x01000000); + nvkm_wr32(device, 0x41a1c0, 0x01000000); for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) - nv_wr32(gr, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); + nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); - nv_wr32(gr, 0x41a180, 0x01000000); + nvkm_wr32(device, 0x41a180, 0x01000000); for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) - nv_wr32(gr, 0x41a188, i >> 6); - nv_wr32(gr, 0x41a184, oclass->gpccs.ucode->code.data[i]); + nvkm_wr32(device, 0x41a188, i >> 6); + nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); } nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); @@ -1404,15 +1423,15 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); /* start HUB ucode running, it'll init the GPCs */ - nv_wr32(gr, 0x40910c, 0x00000000); - nv_wr32(gr, 0x409100, 0x00000002); + nvkm_wr32(device, 0x40910c, 0x00000000); + nvkm_wr32(device, 0x409100, 0x00000002); if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) { nv_error(gr, "HUB_INIT timed out\n"); gf100_gr_ctxctl_debug(gr); return -EBUSY; } - gr->size = nv_rd32(gr, 0x409804); + gr->size = nvkm_rd32(device, 0x409804); if (gr->data == NULL) { int ret = gf100_grctx_generate(gr); if (ret) { @@ -1427,8 +1446,9 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) int gf100_gr_init(struct nvkm_object *object) { - struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr *gr = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct gf100_gr_oclass *oclass = (void *)object->oclass; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -1439,14 +1459,14 @@ gf100_gr_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); - nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); gf100_gr_mmio(gr, oclass->mmio); @@ -1460,76 +1480,76 @@ gf100_gr_init(struct nvkm_object *object) data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(gr, GPC_BCAST(0x0980), data[0]); - nv_wr32(gr, GPC_BCAST(0x0984), data[1]); - nv_wr32(gr, GPC_BCAST(0x0988), data[2]); - nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); + nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); + nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); + nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); - nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } if (nv_device(gr)->chipset != 0xd7) - nv_wr32(gr, GPC_BCAST(0x1bd4), magicgpc918); + nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); else - nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); + nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400500, 0x00010001); - nv_wr32(gr, 0x400100, 0xffffffff); - nv_wr32(gr, 0x40013c, 0xffffffff); + nvkm_wr32(device, 0x400100, 0xffffffff); + nvkm_wr32(device, 0x40013c, 0xffffffff); - nv_wr32(gr, 0x409c24, 0x000f0000); - nv_wr32(gr, 0x404000, 0xc0000000); - nv_wr32(gr, 0x404600, 0xc0000000); - nv_wr32(gr, 0x408030, 0xc0000000); - nv_wr32(gr, 0x40601c, 0xc0000000); - nv_wr32(gr, 0x404490, 0xc0000000); - nv_wr32(gr, 0x406018, 0xc0000000); - nv_wr32(gr, 0x405840, 0xc0000000); - nv_wr32(gr, 0x405844, 0x00ffffff); - nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000); + nvkm_wr32(device, 0x409c24, 0x000f0000); + nvkm_wr32(device, 0x404000, 0xc0000000); + nvkm_wr32(device, 0x404600, 0xc0000000); + nvkm_wr32(device, 0x408030, 0xc0000000); + nvkm_wr32(device, 0x40601c, 0xc0000000); + nvkm_wr32(device, 0x404490, 0xc0000000); + nvkm_wr32(device, 0x406018, 0xc0000000); + nvkm_wr32(device, 0x405840, 0xc0000000); + nvkm_wr32(device, 0x405844, 0x00ffffff); + nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); + nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); } - nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < gr->rop_nr; rop++) { - nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(gr, 0x400108, 0xffffffff); - nv_wr32(gr, 0x400138, 0xffffffff); - nv_wr32(gr, 0x400118, 0xffffffff); - nv_wr32(gr, 0x400130, 0xffffffff); - nv_wr32(gr, 0x40011c, 0xffffffff); - nv_wr32(gr, 0x400134, 0xffffffff); + nvkm_wr32(device, 0x400108, 0xffffffff); + nvkm_wr32(device, 0x400138, 0xffffffff); + nvkm_wr32(device, 0x400118, 0xffffffff); + nvkm_wr32(device, 0x400130, 0xffffffff); + nvkm_wr32(device, 0x40011c, 0xffffffff); + nvkm_wr32(device, 0x400134, 0xffffffff); - nv_wr32(gr, 0x400054, 0x34ce3464); + nvkm_wr32(device, 0x400054, 0x34ce3464); gf100_gr_zbc_init(gr); @@ -1644,14 +1664,14 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_wo32(gr->unk4188b8, i, 0x00000010); } - gr->rop_nr = (nv_rd32(gr, 0x409604) & 0x001f0000) >> 16; - gr->gpc_nr = nv_rd32(gr, 0x409604) & 0x0000001f; + gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; + gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; for (i = 0; i < gr->gpc_nr; i++) { - gr->tpc_nr[i] = nv_rd32(gr, GPC_UNIT(i, 0x2608)); + gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); gr->tpc_total += gr->tpc_nr[i]; gr->ppc_nr[i] = oclass->ppc_nr; for (j = 0; j < gr->ppc_nr[i]; j++) { - u8 mask = nv_rd32(gr, GPC_UNIT(i, 0x0c30 + (j * 4))); + u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); gr->ppc_tpc_nr[i][j] = hweight8(mask); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 9f83122dc1a8..89bb10161554 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -197,7 +197,8 @@ gk104_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr *gr = (void *)object; - struct nvkm_pmu *pmu = nvkm_pmu(gr); + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_pmu *pmu = device->pmu; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -211,18 +212,18 @@ gk104_gr_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x08a4), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0888), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x088c), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); - nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); gf100_gr_mmio(gr, oclass->mmio); - nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001); + nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); @@ -235,75 +236,75 @@ gk104_gr_init(struct nvkm_object *object) data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(gr, GPC_BCAST(0x0980), data[0]); - nv_wr32(gr, GPC_BCAST(0x0984), data[1]); - nv_wr32(gr, GPC_BCAST(0x0988), data[2]); - nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); + nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); + nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); + nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); - nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); + nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400500, 0x00010001); - nv_wr32(gr, 0x400100, 0xffffffff); - nv_wr32(gr, 0x40013c, 0xffffffff); + nvkm_wr32(device, 0x400100, 0xffffffff); + nvkm_wr32(device, 0x40013c, 0xffffffff); - nv_wr32(gr, 0x409ffc, 0x00000000); - nv_wr32(gr, 0x409c14, 0x00003e3e); - nv_wr32(gr, 0x409c24, 0x000f0001); - nv_wr32(gr, 0x404000, 0xc0000000); - nv_wr32(gr, 0x404600, 0xc0000000); - nv_wr32(gr, 0x408030, 0xc0000000); - nv_wr32(gr, 0x404490, 0xc0000000); - nv_wr32(gr, 0x406018, 0xc0000000); - nv_wr32(gr, 0x407020, 0x40000000); - nv_wr32(gr, 0x405840, 0xc0000000); - nv_wr32(gr, 0x405844, 0x00ffffff); - nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); - nv_mask(gr, 0x419eb4, 0x00001000, 0x00001000); + nvkm_wr32(device, 0x409ffc, 0x00000000); + nvkm_wr32(device, 0x409c14, 0x00003e3e); + nvkm_wr32(device, 0x409c24, 0x000f0001); + nvkm_wr32(device, 0x404000, 0xc0000000); + nvkm_wr32(device, 0x404600, 0xc0000000); + nvkm_wr32(device, 0x408030, 0xc0000000); + nvkm_wr32(device, 0x404490, 0xc0000000); + nvkm_wr32(device, 0x406018, 0xc0000000); + nvkm_wr32(device, 0x407020, 0x40000000); + nvkm_wr32(device, 0x405840, 0xc0000000); + nvkm_wr32(device, 0x405844, 0x00ffffff); + nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); + nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x3038), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x3038), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); } - nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < gr->rop_nr; rop++) { - nv_wr32(gr, ROP_UNIT(rop, 0x144), 0xc0000000); - nv_wr32(gr, ROP_UNIT(rop, 0x070), 0xc0000000); - nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(gr, 0x400108, 0xffffffff); - nv_wr32(gr, 0x400138, 0xffffffff); - nv_wr32(gr, 0x400118, 0xffffffff); - nv_wr32(gr, 0x400130, 0xffffffff); - nv_wr32(gr, 0x40011c, 0xffffffff); - nv_wr32(gr, 0x400134, 0xffffffff); + nvkm_wr32(device, 0x400108, 0xffffffff); + nvkm_wr32(device, 0x400138, 0xffffffff); + nvkm_wr32(device, 0x400118, 0xffffffff); + nvkm_wr32(device, 0x400130, 0xffffffff); + nvkm_wr32(device, 0x40011c, 0xffffffff); + nvkm_wr32(device, 0x400134, 0xffffffff); - nv_wr32(gr, 0x400054, 0x34ce3464); + nvkm_wr32(device, 0x400054, 0x34ce3464); gf100_gr_zbc_init(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 9816303ad716..12b34c7a1477 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -236,8 +236,9 @@ gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) static void gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { - nv_wr32(gr, 0x419e44, 0x1ffffe); - nv_wr32(gr, 0x419e4c, 0x7f); + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_wr32(device, 0x419e44, 0x1ffffe); + nvkm_wr32(device, 0x419e4c, 0x7f); } int @@ -245,6 +246,7 @@ gk20a_gr_init(struct nvkm_object *object) { struct gk20a_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr *gr = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -256,7 +258,7 @@ gk20a_gr_init(struct nvkm_object *object) return ret; /* Clear SCC RAM */ - nv_wr32(gr, 0x40802c, 0x1); + nvkm_wr32(device, 0x40802c, 0x1); gf100_gr_mmio(gr, gr->fuc_sw_nonctx); @@ -269,14 +271,14 @@ gk20a_gr_init(struct nvkm_object *object) return ret; /* MMU debug buffer */ - nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8); - nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8); + nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8); + nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8); if (oclass->init_gpc_mmu) oclass->init_gpc_mmu(gr); /* Set the PE as stream master */ - nv_mask(gr, 0x503018, 0x1, 0x1); + nvkm_mask(device, 0x503018, 0x1, 0x1); /* Zcull init */ memset(data, 0x00, sizeof(data)); @@ -290,49 +292,49 @@ gk20a_gr_init(struct nvkm_object *object) data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(gr, GPC_BCAST(0x0980), data[0]); - nv_wr32(gr, GPC_BCAST(0x0984), data[1]); - nv_wr32(gr, GPC_BCAST(0x0988), data[2]); - nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); + nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); + nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); + nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x0914), - gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | - gr->tpc_total); - nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), + gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); + nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); /* Enable FIFO access */ - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400500, 0x00010001); /* Enable interrupts */ - nv_wr32(gr, 0x400100, 0xffffffff); - nv_wr32(gr, 0x40013c, 0xffffffff); + nvkm_wr32(device, 0x400100, 0xffffffff); + nvkm_wr32(device, 0x40013c, 0xffffffff); /* Enable FECS error interrupts */ - nv_wr32(gr, 0x409c24, 0x000f0000); + nvkm_wr32(device, 0x409c24, 0x000f0000); /* Enable hardware warning exceptions */ - nv_wr32(gr, 0x404000, 0xc0000000); - nv_wr32(gr, 0x404600, 0xc0000000); + nvkm_wr32(device, 0x404000, 0xc0000000); + nvkm_wr32(device, 0x404600, 0xc0000000); if (oclass->set_hww_esr_report_mask) oclass->set_hww_esr_report_mask(gr); /* Enable TPC exceptions per GPC */ - nv_wr32(gr, 0x419d0c, 0x2); - nv_wr32(gr, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16); + nvkm_wr32(device, 0x419d0c, 0x2); + nvkm_wr32(device, 0x41ac94, (((1 << gr->tpc_total) - 1) & 0xff) << 16); /* Reset and enable all exceptions */ - nv_wr32(gr, 0x400108, 0xffffffff); - nv_wr32(gr, 0x400138, 0xffffffff); - nv_wr32(gr, 0x400118, 0xffffffff); - nv_wr32(gr, 0x400130, 0xffffffff); - nv_wr32(gr, 0x40011c, 0xffffffff); - nv_wr32(gr, 0x400134, 0xffffffff); + nvkm_wr32(device, 0x400108, 0xffffffff); + nvkm_wr32(device, 0x400138, 0xffffffff); + nvkm_wr32(device, 0x400118, 0xffffffff); + nvkm_wr32(device, 0x400130, 0xffffffff); + nvkm_wr32(device, 0x40011c, 0xffffffff); + nvkm_wr32(device, 0x400134, 0xffffffff); gf100_gr_zbc_init(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 5e9560f6ac0e..1e451a9e2290 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -304,7 +304,8 @@ gm107_gr_init_bios(struct gf100_gr *gr) { 0x419af0, 0x419af4 }, { 0x419af8, 0x419afc }, }; - struct nvkm_bios *bios = nvkm_bios(gr); + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_bios *bios = device->bios; struct nvbios_P0260E infoE; struct nvbios_P0260X infoX; int E = -1, X; @@ -312,9 +313,9 @@ gm107_gr_init_bios(struct gf100_gr *gr) while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { if (X = -1, E < ARRAY_SIZE(regs)) { - nv_wr32(gr, regs[E].ctrl, infoE.data); + nvkm_wr32(device, regs[E].ctrl, infoE.data); while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) - nv_wr32(gr, regs[E].data, infoX.data); + nvkm_wr32(device, regs[E].data, infoX.data); } } } @@ -324,6 +325,7 @@ gm107_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr *gr = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -334,17 +336,17 @@ gm107_gr_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(gr, GPC_BCAST(0x0880), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0890), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x0894), 0x00000000); - nv_wr32(gr, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); - nv_wr32(gr, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); + nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); gf100_gr_mmio(gr, oclass->mmio); gm107_gr_init_bios(gr); - nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001); + nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); @@ -357,75 +359,75 @@ gm107_gr_init(struct nvkm_object *object) data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(gr, GPC_BCAST(0x0980), data[0]); - nv_wr32(gr, GPC_BCAST(0x0984), data[1]); - nv_wr32(gr, GPC_BCAST(0x0988), data[2]); - nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); + nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); + nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); + nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); - nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); + nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); + nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400500, 0x00010001); - nv_wr32(gr, 0x400100, 0xffffffff); - nv_wr32(gr, 0x40013c, 0xffffffff); - nv_wr32(gr, 0x400124, 0x00000002); - nv_wr32(gr, 0x409c24, 0x000e0000); + nvkm_wr32(device, 0x400100, 0xffffffff); + nvkm_wr32(device, 0x40013c, 0xffffffff); + nvkm_wr32(device, 0x400124, 0x00000002); + nvkm_wr32(device, 0x409c24, 0x000e0000); - nv_wr32(gr, 0x404000, 0xc0000000); - nv_wr32(gr, 0x404600, 0xc0000000); - nv_wr32(gr, 0x408030, 0xc0000000); - nv_wr32(gr, 0x404490, 0xc0000000); - nv_wr32(gr, 0x406018, 0xc0000000); - nv_wr32(gr, 0x407020, 0x40000000); - nv_wr32(gr, 0x405840, 0xc0000000); - nv_wr32(gr, 0x405844, 0x00ffffff); - nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); + nvkm_wr32(device, 0x404000, 0xc0000000); + nvkm_wr32(device, 0x404600, 0xc0000000); + nvkm_wr32(device, 0x408030, 0xc0000000); + nvkm_wr32(device, 0x404490, 0xc0000000); + nvkm_wr32(device, 0x406018, 0xc0000000); + nvkm_wr32(device, 0x407020, 0x40000000); + nvkm_wr32(device, 0x405840, 0xc0000000); + nvkm_wr32(device, 0x405844, 0x00ffffff); + nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < 2 /* gr->ppc_nr[gpc] */; ppc++) - nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } - nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < gr->rop_nr; rop++) { - nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000); - nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000); - nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(gr, 0x400108, 0xffffffff); - nv_wr32(gr, 0x400138, 0xffffffff); - nv_wr32(gr, 0x400118, 0xffffffff); - nv_wr32(gr, 0x400130, 0xffffffff); - nv_wr32(gr, 0x40011c, 0xffffffff); - nv_wr32(gr, 0x400134, 0xffffffff); + nvkm_wr32(device, 0x400108, 0xffffffff); + nvkm_wr32(device, 0x400138, 0xffffffff); + nvkm_wr32(device, 0x400118, 0xffffffff); + nvkm_wr32(device, 0x400130, 0xffffffff); + nvkm_wr32(device, 0x40011c, 0xffffffff); + nvkm_wr32(device, 0x400134, 0xffffffff); - nv_wr32(gr, 0x400054, 0x2c350f63); + nvkm_wr32(device, 0x400054, 0x2c350f63); gf100_gr_zbc_init(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c index 4cc60edafaef..c3d2343d41d3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c @@ -253,6 +253,7 @@ gm204_gr_init(struct nvkm_object *object) { struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr *gr = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; @@ -264,24 +265,24 @@ gm204_gr_init(struct nvkm_object *object) if (ret) return ret; - tmp = nv_rd32(gr, 0x100c80); /*XXX: mask? */ - nv_wr32(gr, 0x418880, 0x00001000 | (tmp & 0x00000fff)); - nv_wr32(gr, 0x418890, 0x00000000); - nv_wr32(gr, 0x418894, 0x00000000); - nv_wr32(gr, 0x4188b4, gr->unk4188b4->addr >> 8); - nv_wr32(gr, 0x4188b8, gr->unk4188b8->addr >> 8); - nv_mask(gr, 0x4188b0, 0x00040000, 0x00040000); + tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */ + nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff)); + nvkm_wr32(device, 0x418890, 0x00000000); + nvkm_wr32(device, 0x418894, 0x00000000); + nvkm_wr32(device, 0x4188b4, gr->unk4188b4->addr >> 8); + nvkm_wr32(device, 0x4188b8, gr->unk4188b8->addr >> 8); + nvkm_mask(device, 0x4188b0, 0x00040000, 0x00040000); /*XXX: belongs in fb */ - nv_wr32(gr, 0x100cc8, gr->unk4188b4->addr >> 8); - nv_wr32(gr, 0x100ccc, gr->unk4188b8->addr >> 8); - nv_mask(gr, 0x100cc4, 0x00040000, 0x00040000); + nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8); + nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8); + nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000); gf100_gr_mmio(gr, oclass->mmio); gm107_gr_init_bios(gr); - nv_wr32(gr, GPC_UNIT(0, 0x3018), 0x00000001); + nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); memset(data, 0x00, sizeof(data)); memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); @@ -294,76 +295,76 @@ gm204_gr_init(struct nvkm_object *object) data[i / 8] |= tpc << ((i % 8) * 4); } - nv_wr32(gr, GPC_BCAST(0x0980), data[0]); - nv_wr32(gr, GPC_BCAST(0x0984), data[1]); - nv_wr32(gr, GPC_BCAST(0x0988), data[2]); - nv_wr32(gr, GPC_BCAST(0x098c), data[3]); + nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); + nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); + nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); + nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { - nv_wr32(gr, GPC_UNIT(gpc, 0x0914), + nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), gr->magic_not_rop_nr << 8 | gr->tpc_nr[gpc]); - nv_wr32(gr, GPC_UNIT(gpc, 0x0910), 0x00040000 | + nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | gr->tpc_total); - nv_wr32(gr, GPC_UNIT(gpc, 0x0918), magicgpc918); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } - nv_wr32(gr, GPC_BCAST(0x3fd4), magicgpc918); - nv_wr32(gr, GPC_BCAST(0x08ac), nv_rd32(gr, 0x100800)); - nv_wr32(gr, GPC_BCAST(0x033c), nv_rd32(gr, 0x100804)); - - nv_wr32(gr, 0x400500, 0x00010001); - nv_wr32(gr, 0x400100, 0xffffffff); - nv_wr32(gr, 0x40013c, 0xffffffff); - nv_wr32(gr, 0x400124, 0x00000002); - nv_wr32(gr, 0x409c24, 0x000e0000); - nv_wr32(gr, 0x405848, 0xc0000000); - nv_wr32(gr, 0x40584c, 0x00000001); - nv_wr32(gr, 0x404000, 0xc0000000); - nv_wr32(gr, 0x404600, 0xc0000000); - nv_wr32(gr, 0x408030, 0xc0000000); - nv_wr32(gr, 0x404490, 0xc0000000); - nv_wr32(gr, 0x406018, 0xc0000000); - nv_wr32(gr, 0x407020, 0x40000000); - nv_wr32(gr, 0x405840, 0xc0000000); - nv_wr32(gr, 0x405844, 0x00ffffff); - nv_mask(gr, 0x419cc0, 0x00000008, 0x00000008); + nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); + nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); + nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); + + nvkm_wr32(device, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400100, 0xffffffff); + nvkm_wr32(device, 0x40013c, 0xffffffff); + nvkm_wr32(device, 0x400124, 0x00000002); + nvkm_wr32(device, 0x409c24, 0x000e0000); + nvkm_wr32(device, 0x405848, 0xc0000000); + nvkm_wr32(device, 0x40584c, 0x00000001); + nvkm_wr32(device, 0x404000, 0xc0000000); + nvkm_wr32(device, 0x404600, 0xc0000000); + nvkm_wr32(device, 0x408030, 0xc0000000); + nvkm_wr32(device, 0x404490, 0xc0000000); + nvkm_wr32(device, 0x406018, 0xc0000000); + nvkm_wr32(device, 0x407020, 0x40000000); + nvkm_wr32(device, 0x405840, 0xc0000000); + nvkm_wr32(device, 0x405844, 0x00ffffff); + nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008); for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) - nv_wr32(gr, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0420), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0900), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x1028), 0xc0000000); - nv_wr32(gr, GPC_UNIT(gpc, 0x0824), 0xc0000000); + nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); + nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); - nv_wr32(gr, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); + nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); } - nv_wr32(gr, GPC_UNIT(gpc, 0x2c90), 0xffffffff); - nv_wr32(gr, GPC_UNIT(gpc, 0x2c94), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff); + nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff); } for (rop = 0; rop < gr->rop_nr; rop++) { - nv_wr32(gr, ROP_UNIT(rop, 0x144), 0x40000000); - nv_wr32(gr, ROP_UNIT(rop, 0x070), 0x40000000); - nv_wr32(gr, ROP_UNIT(rop, 0x204), 0xffffffff); - nv_wr32(gr, ROP_UNIT(rop, 0x208), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000); + nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff); + nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff); } - nv_wr32(gr, 0x400108, 0xffffffff); - nv_wr32(gr, 0x400138, 0xffffffff); - nv_wr32(gr, 0x400118, 0xffffffff); - nv_wr32(gr, 0x400130, 0xffffffff); - nv_wr32(gr, 0x40011c, 0xffffffff); - nv_wr32(gr, 0x400134, 0xffffffff); + nvkm_wr32(device, 0x400108, 0xffffffff); + nvkm_wr32(device, 0x400138, 0xffffffff); + nvkm_wr32(device, 0x400118, 0xffffffff); + nvkm_wr32(device, 0x400130, 0xffffffff); + nvkm_wr32(device, 0x40011c, 0xffffffff); + nvkm_wr32(device, 0x400134, 0xffffffff); - nv_wr32(gr, 0x400054, 0x2c350f63); + nvkm_wr32(device, 0x400054, 0x2c350f63); gf100_gr_zbc_init(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 6b9c84f8f12d..719ebfb6e640 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -37,32 +37,34 @@ gm20b_gr_sclass[] = { static void gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; u32 val; /* TODO this needs to be removed once secure boot works */ if (1) { - nv_wr32(gr, 0x100ce4, 0xffffffff); + nvkm_wr32(device, 0x100ce4, 0xffffffff); } /* TODO update once secure boot works */ - val = nv_rd32(gr, 0x100c80); + val = nvkm_rd32(device, 0x100c80); val &= 0xf000087f; - nv_wr32(gr, 0x418880, val); - nv_wr32(gr, 0x418890, 0); - nv_wr32(gr, 0x418894, 0); + nvkm_wr32(device, 0x418880, val); + nvkm_wr32(device, 0x418890, 0); + nvkm_wr32(device, 0x418894, 0); - nv_wr32(gr, 0x4188b0, nv_rd32(gr, 0x100cc4)); - nv_wr32(gr, 0x4188b4, nv_rd32(gr, 0x100cc8)); - nv_wr32(gr, 0x4188b8, nv_rd32(gr, 0x100ccc)); + nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); + nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); + nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); - nv_wr32(gr, 0x4188ac, nv_rd32(gr, 0x100800)); + nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); } static void gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) { - nv_wr32(gr, 0x419e44, 0xdffffe); - nv_wr32(gr, 0x419e4c, 0x5); + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_wr32(device, 0x419e44, 0xdffffe); + nvkm_wr32(device, 0x419e4c, 0x5); } struct nvkm_oclass * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index e161abe88fb8..d1792ef62712 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -446,7 +446,8 @@ static void nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value) { struct nv04_gr *gr = (void *)object->engine; - int subc = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; + struct nvkm_device *device = gr->base.engine.subdev.device; + int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; u32 tmp; tmp = nv_ro32(object, 0x00); @@ -454,8 +455,8 @@ nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value) tmp |= value; nv_wo32(object, 0x00, tmp); - nv_wr32(gr, NV04_PGRAPH_CTX_SWITCH1, tmp); - nv_wr32(gr, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); + nvkm_wr32(device, NV04_PGRAPH_CTX_SWITCH1, tmp); + nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); } static void @@ -528,6 +529,7 @@ nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, void *args, u32 size) { struct nv04_gr *gr = (void *)object->engine; + struct nvkm_device *device = gr->base.engine.subdev.device; u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; @@ -539,8 +541,8 @@ nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, w |= 0xffff0000; max = min + w; max &= 0x3ffff; - nv_wr32(gr, 0x40053c, min); - nv_wr32(gr, 0x400544, max); + nvkm_wr32(device, 0x40053c, min); + nvkm_wr32(device, 0x400544, max); return 0; } @@ -549,6 +551,7 @@ nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, void *args, u32 size) { struct nv04_gr *gr = (void *)object->engine; + struct nvkm_device *device = gr->base.engine.subdev.device; u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; @@ -560,8 +563,8 @@ nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, w |= 0xffff0000; max = min + w; max &= 0x3ffff; - nv_wr32(gr, 0x400540, min); - nv_wr32(gr, 0x400548, max); + nvkm_wr32(device, 0x400540, min); + nvkm_wr32(device, 0x400548, max); return 0; } @@ -1033,9 +1036,10 @@ nv04_gr_sclass[] = { static struct nv04_gr_chan * nv04_gr_channel(struct nv04_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct nv04_gr_chan *chan = NULL; - if (nv_rd32(gr, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { - int chid = nv_rd32(gr, NV04_PGRAPH_CTX_USER) >> 24; + if (nvkm_rd32(device, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { + int chid = nvkm_rd32(device, NV04_PGRAPH_CTX_USER) >> 24; if (chid < ARRAY_SIZE(gr->chan)) chan = gr->chan[chid]; } @@ -1046,14 +1050,15 @@ static int nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) { struct nv04_gr *gr = nv04_gr(chan); + struct nvkm_device *device = gr->base.engine.subdev.device; int i; for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) - nv_wr32(gr, nv04_gr_ctx_regs[i], chan->nv04[i]); + nvkm_wr32(device, nv04_gr_ctx_regs[i], chan->nv04[i]); - nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10010100); - nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); - nv_mask(gr, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10010100); + nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); + nvkm_mask(device, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); return 0; } @@ -1061,19 +1066,21 @@ static int nv04_gr_unload_context(struct nv04_gr_chan *chan) { struct nv04_gr *gr = nv04_gr(chan); + struct nvkm_device *device = gr->base.engine.subdev.device; int i; for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) - chan->nv04[i] = nv_rd32(gr, nv04_gr_ctx_regs[i]); + chan->nv04[i] = nvkm_rd32(device, nv04_gr_ctx_regs[i]); - nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL, 0x10000000); - nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10000000); + nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); return 0; } static void nv04_gr_context_switch(struct nv04_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct nv04_gr_chan *prev = NULL; struct nv04_gr_chan *next = NULL; unsigned long flags; @@ -1088,7 +1095,7 @@ nv04_gr_context_switch(struct nv04_gr *gr) nv04_gr_unload_context(prev); /* load context for next channel */ - chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; + chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; next = gr->chan[chid]; if (next) nv04_gr_load_context(next, chid); @@ -1161,13 +1168,14 @@ nv04_gr_context_fini(struct nvkm_object *object, bool suspend) { struct nv04_gr *gr = (void *)object->engine; struct nv04_gr_chan *chan = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); - nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); if (nv04_gr_channel(gr) == chan) nv04_gr_unload_context(chan); - nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); return nvkm_object_fini(&chan->base, suspend); @@ -1192,6 +1200,7 @@ bool nv04_gr_idle(void *obj) { struct nvkm_gr *gr = nvkm_gr(obj); + struct nvkm_device *device = gr->engine.subdev.device; u32 mask = 0xffffffff; if (nv_device(obj)->card_type == NV_40) @@ -1199,7 +1208,7 @@ nv04_gr_idle(void *obj) if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) { nv_error(gr, "idle timed out with status 0x%08x\n", - nv_rd32(gr, NV04_PGRAPH_STATUS)); + nvkm_rd32(device, NV04_PGRAPH_STATUS)); return false; } @@ -1252,16 +1261,17 @@ nv04_gr_intr(struct nvkm_subdev *subdev) struct nv04_gr_chan *chan = NULL; struct nvkm_namedb *namedb = NULL; struct nvkm_handle *handle = NULL; - u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); + u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); + u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); + u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); u32 chid = (addr & 0x0f000000) >> 24; u32 subc = (addr & 0x0000e000) >> 13; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(gr, 0x400180 + subc * 4) & 0xff; - u32 inst = (nv_rd32(gr, 0x40016c) & 0xffff) << 4; + u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff; + u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4; u32 show = stat; unsigned long flags; @@ -1280,14 +1290,14 @@ nv04_gr_intr(struct nvkm_subdev *subdev) } if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); + nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; nv04_gr_context_switch(gr); } - nv_wr32(gr, NV03_PGRAPH_INTR, stat); - nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); + nvkm_wr32(device, NV03_PGRAPH_INTR, stat); + nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { nv_error(gr, "%s", ""); @@ -1332,6 +1342,7 @@ nv04_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nv04_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; int ret; ret = nvkm_gr_init(&gr->base); @@ -1339,33 +1350,33 @@ nv04_gr_init(struct nvkm_object *object) return ret; /* Enable PGRAPH interrupts */ - nv_wr32(gr, NV03_PGRAPH_INTR, 0xFFFFFFFF); - nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(gr, NV04_PGRAPH_VALID1, 0); - nv_wr32(gr, NV04_PGRAPH_VALID2, 0); - /*nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x000001FF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x1231c000); + nvkm_wr32(device, NV03_PGRAPH_INTR, 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nvkm_wr32(device, NV04_PGRAPH_VALID1, 0); + nvkm_wr32(device, NV04_PGRAPH_VALID2, 0); + /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x000001FF); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x1231c000); /*1231C000 blob, 001 haiku*/ /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ - nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x72111100); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x72111100); /*0x72111100 blob , 01 haiku*/ - /*nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ - nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x11d5f071); + /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f071); /*haiku same*/ - /*nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ - nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); + /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); /*haiku and blob 10d4*/ - nv_wr32(gr, NV04_PGRAPH_STATE , 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_CTX_CONTROL , 0x10000100); - nv_mask(gr, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + nvkm_wr32(device, NV04_PGRAPH_STATE , 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL , 0x10000100); + nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); /* These don't belong here, they're part of a per-channel context */ - nv_wr32(gr, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - nv_wr32(gr, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index af33514456a4..6b3ee956ced4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -414,17 +414,17 @@ nv10_gr(struct nv10_gr_chan *chan) #define PIPE_SAVE(gr, state, addr) \ do { \ int __i; \ - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, addr); \ + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \ for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ - state[__i] = nv_rd32(gr, NV10_PGRAPH_PIPE_DATA); \ + state[__i] = nvkm_rd32(device, NV10_PGRAPH_PIPE_DATA); \ } while (0) #define PIPE_RESTORE(gr, state, addr) \ do { \ int __i; \ - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, addr); \ + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \ for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, state[__i]); \ + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \ } while (0) static struct nvkm_oclass @@ -480,6 +480,7 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, struct nv10_gr_chan *chan = (void *)object->parent; struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe = &chan->pipe_state; + struct nvkm_device *device = gr->base.engine.subdev.device; u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; u32 xfmode0, xfmode1; u32 data = *(u32 *)args; @@ -499,8 +500,8 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, nv04_gr_idle(gr); - xfmode0 = nv_rd32(gr, NV10_PGRAPH_XFMODE0); - xfmode1 = nv_rd32(gr, NV10_PGRAPH_XFMODE1); + xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); + xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); PIPE_SAVE(gr, pipe_0x64c0, 0x64c0); @@ -509,24 +510,24 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, nv04_gr_idle(gr); - nv_wr32(gr, NV10_PGRAPH_XFMODE0, 0x10000000); - nv_wr32(gr, NV10_PGRAPH_XFMODE1, 0x00000000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); + nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000008); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); @@ -534,16 +535,16 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, PIPE_RESTORE(gr, pipe_0x0040, 0x0040); - nv_wr32(gr, NV10_PGRAPH_XFMODE0, xfmode0); - nv_wr32(gr, NV10_PGRAPH_XFMODE1, xfmode1); + nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0); + nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1); PIPE_RESTORE(gr, pipe_0x64c0, 0x64c0); PIPE_RESTORE(gr, pipe_0x6ab0, 0x6ab0); PIPE_RESTORE(gr, pipe_0x6a80, 0x6a80); PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); nv04_gr_idle(gr); @@ -556,11 +557,12 @@ nv17_gr_mthd_lma_enable(struct nvkm_object *object, u32 mthd, { struct nv10_gr_chan *chan = (void *)object->parent; struct nv10_gr *gr = nv10_gr(chan); + struct nvkm_device *device = gr->base.engine.subdev.device; nv04_gr_idle(gr); - nv_mask(gr, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); - nv_mask(gr, 0x4006b0, 0x08000000, 0x08000000); + nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); + nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000); return 0; } @@ -604,9 +606,10 @@ nv17_gr_sclass[] = { static struct nv10_gr_chan * nv10_gr_channel(struct nv10_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct nv10_gr_chan *chan = NULL; - if (nv_rd32(gr, 0x400144) & 0x00010000) { - int chid = nv_rd32(gr, 0x400148) >> 24; + if (nvkm_rd32(device, 0x400144) & 0x00010000) { + int chid = nvkm_rd32(device, 0x400148) >> 24; if (chid < ARRAY_SIZE(gr->chan)) chan = gr->chan[chid]; } @@ -618,6 +621,7 @@ nv10_gr_save_pipe(struct nv10_gr_chan *chan) { struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe = &chan->pipe_state; + struct nvkm_device *device = gr->base.engine.subdev.device; PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); @@ -636,39 +640,40 @@ nv10_gr_load_pipe(struct nv10_gr_chan *chan) { struct nv10_gr *gr = nv10_gr(chan); struct pipe_state *pipe = &chan->pipe_state; + struct nvkm_device *device = gr->base.engine.subdev.device; u32 xfmode0, xfmode1; int i; nv04_gr_idle(gr); /* XXX check haiku comments */ - xfmode0 = nv_rd32(gr, NV10_PGRAPH_XFMODE0); - xfmode1 = nv_rd32(gr, NV10_PGRAPH_XFMODE1); - nv_wr32(gr, NV10_PGRAPH_XFMODE0, 0x10000000); - nv_wr32(gr, NV10_PGRAPH_XFMODE1, 0x00000000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); + xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); + xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); + nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); + nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); for (i = 0; i < 4; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); for (i = 0; i < 4; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); for (i = 0; i < 3; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x3f800000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); for (i = 0; i < 3; i++) - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); - nv_wr32(gr, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); - nv_wr32(gr, NV10_PGRAPH_PIPE_DATA, 0x00000008); + nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); + nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); nv04_gr_idle(gr); /* restore XFMODE */ - nv_wr32(gr, NV10_PGRAPH_XFMODE0, xfmode0); - nv_wr32(gr, NV10_PGRAPH_XFMODE1, xfmode1); + nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0); + nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1); PIPE_RESTORE(gr, pipe->pipe_0x6400, 0x6400); PIPE_RESTORE(gr, pipe->pipe_0x6800, 0x6800); PIPE_RESTORE(gr, pipe->pipe_0x6c00, 0x6c00); @@ -864,6 +869,7 @@ static void nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) { struct nv10_gr *gr = nv10_gr(chan); + struct nvkm_device *device = gr->base.engine.subdev.device; u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; u32 ctx_user, ctx_switch[5]; int i, subchan = -1; @@ -875,7 +881,7 @@ nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) /* Look for a celsius object */ for (i = 0; i < 8; i++) { - int class = nv_rd32(gr, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; + int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; if (class == 0x56 || class == 0x96 || class == 0x99) { subchan = i; @@ -887,73 +893,74 @@ nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) return; /* Save the current ctx object */ - ctx_user = nv_rd32(gr, NV10_PGRAPH_CTX_USER); + ctx_user = nvkm_rd32(device, NV10_PGRAPH_CTX_USER); for (i = 0; i < 5; i++) - ctx_switch[i] = nv_rd32(gr, NV10_PGRAPH_CTX_SWITCH(i)); + ctx_switch[i] = nvkm_rd32(device, NV10_PGRAPH_CTX_SWITCH(i)); /* Save the FIFO state */ - st2 = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2); - st2_dl = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2_DL); - st2_dh = nv_rd32(gr, NV10_PGRAPH_FFINTFC_ST2_DH); - fifo_ptr = nv_rd32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR); + st2 = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2); + st2_dl = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DL); + st2_dh = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_ST2_DH); + fifo_ptr = nvkm_rd32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR); for (i = 0; i < ARRAY_SIZE(fifo); i++) - fifo[i] = nv_rd32(gr, 0x4007a0 + 4 * i); + fifo[i] = nvkm_rd32(device, 0x4007a0 + 4 * i); /* Switch to the celsius subchannel */ for (i = 0; i < 5; i++) - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(i), - nv_rd32(gr, NV10_PGRAPH_CTX_CACHE(subchan, i))); - nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), + nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(subchan, i))); + nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); /* Inject NV10TCL_DMA_VTXBUF */ - nv_wr32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DL, inst); - nv_mask(gr, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); - nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, inst); + nvkm_mask(device, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); /* Restore the FIFO state */ for (i = 0; i < ARRAY_SIZE(fifo); i++) - nv_wr32(gr, 0x4007a0 + 4 * i, fifo[i]); + nvkm_wr32(device, 0x4007a0 + 4 * i, fifo[i]); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, st2); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, st2); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); /* Restore the current ctx object */ for (i = 0; i < 5; i++) - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); - nv_wr32(gr, NV10_PGRAPH_CTX_USER, ctx_user); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); + nvkm_wr32(device, NV10_PGRAPH_CTX_USER, ctx_user); } static int nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) { struct nv10_gr *gr = nv10_gr(chan); + struct nvkm_device *device = gr->base.engine.subdev.device; u32 inst; int i; for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) - nv_wr32(gr, nv10_gr_ctx_regs[i], chan->nv10[i]); + nvkm_wr32(device, nv10_gr_ctx_regs[i], chan->nv10[i]); if (nv_device(gr)->card_type >= NV_11 && nv_device(gr)->chipset >= 0x17) { for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) - nv_wr32(gr, nv17_gr_ctx_regs[i], chan->nv17[i]); + nvkm_wr32(device, nv17_gr_ctx_regs[i], chan->nv17[i]); } nv10_gr_load_pipe(chan); - inst = nv_rd32(gr, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; + inst = nvkm_rd32(device, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; nv10_gr_load_dma_vtxbuf(chan, chid, inst); - nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10010100); - nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); - nv_mask(gr, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); + nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); + nvkm_mask(device, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); return 0; } @@ -961,27 +968,29 @@ static int nv10_gr_unload_context(struct nv10_gr_chan *chan) { struct nv10_gr *gr = nv10_gr(chan); + struct nvkm_device *device = gr->base.engine.subdev.device; int i; for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) - chan->nv10[i] = nv_rd32(gr, nv10_gr_ctx_regs[i]); + chan->nv10[i] = nvkm_rd32(device, nv10_gr_ctx_regs[i]); if (nv_device(gr)->card_type >= NV_11 && nv_device(gr)->chipset >= 0x17) { for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) - chan->nv17[i] = nv_rd32(gr, nv17_gr_ctx_regs[i]); + chan->nv17[i] = nvkm_rd32(device, nv17_gr_ctx_regs[i]); } nv10_gr_save_pipe(chan); - nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000000); - nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000000); + nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); return 0; } static void nv10_gr_context_switch(struct nv10_gr *gr) { + struct nvkm_device *device = gr->base.engine.subdev.device; struct nv10_gr_chan *prev = NULL; struct nv10_gr_chan *next = NULL; unsigned long flags; @@ -996,7 +1005,7 @@ nv10_gr_context_switch(struct nv10_gr *gr) nv10_gr_unload_context(prev); /* load context for next channel */ - chid = (nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; + chid = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; next = gr->chan[chid]; if (next) nv10_gr_load_context(next, chid); @@ -1024,6 +1033,7 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_fifo_chan *fifo = (void *)parent; struct nv10_gr *gr = (void *)engine; struct nv10_gr_chan *chan; + struct nvkm_device *device = gr->base.engine.subdev.device; unsigned long flags; int ret; @@ -1052,8 +1062,8 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_device(gr)->chipset >= 0x17) { /* is it really needed ??? */ NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, - nv_rd32(gr, NV10_PGRAPH_DEBUG_4)); - NV17_WRITE_CTX(0x004006b0, nv_rd32(gr, 0x004006b0)); + nvkm_rd32(device, NV10_PGRAPH_DEBUG_4)); + NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0)); NV17_WRITE_CTX(0x00400eac, 0x0fff0000); NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); NV17_WRITE_CTX(0x00400ec0, 0x00000080); @@ -1088,13 +1098,14 @@ nv10_gr_context_fini(struct nvkm_object *object, bool suspend) { struct nv10_gr *gr = (void *)object->engine; struct nv10_gr_chan *chan = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); - nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); if (nv10_gr_channel(gr) == chan) nv10_gr_unload_context(chan); - nv_mask(gr, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); return nvkm_object_fini(&chan->base, suspend); @@ -1118,17 +1129,18 @@ nv10_gr_cclass = { static void nv10_gr_tile_prog(struct nvkm_engine *engine, int i) { - struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; - struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nv10_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo *fifo = device->fifo; + struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; fifo->pause(fifo, &flags); nv04_gr_idle(gr); - nv_wr32(gr, NV10_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(gr, NV10_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(gr, NV10_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr); fifo->start(fifo, &flags); } @@ -1154,15 +1166,16 @@ nv10_gr_intr(struct nvkm_subdev *subdev) struct nv10_gr_chan *chan = NULL; struct nvkm_namedb *namedb = NULL; struct nvkm_handle *handle = NULL; - u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); + u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); + u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); + u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); u32 chid = (addr & 0x01f00000) >> 20; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xfff; + u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; u32 show = stat; unsigned long flags; @@ -1181,14 +1194,14 @@ nv10_gr_intr(struct nvkm_subdev *subdev) } if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { - nv_wr32(gr, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); + nvkm_wr32(device, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; nv10_gr_context_switch(gr); } - nv_wr32(gr, NV03_PGRAPH_INTR, stat); - nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); + nvkm_wr32(device, NV03_PGRAPH_INTR, stat); + nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { nv_error(gr, "%s", ""); @@ -1249,49 +1262,50 @@ static int nv10_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nvkm_fb *fb = nvkm_fb(object); struct nv10_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; int ret, i; ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x00118700); - /* nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ - nv_wr32(gr, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); - nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700); + /* nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); if (nv_device(gr)->card_type >= NV_11 && nv_device(gr)->chipset >= 0x17) { - nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x1f000000); - nv_wr32(gr, 0x400a10, 0x03ff3fb6); - nv_wr32(gr, 0x400838, 0x002f8684); - nv_wr32(gr, 0x40083c, 0x00115f3f); - nv_wr32(gr, 0x4006b0, 0x40000020); + nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000); + nvkm_wr32(device, 0x400a10, 0x03ff3fb6); + nvkm_wr32(device, 0x400838, 0x002f8684); + nvkm_wr32(device, 0x40083c, 0x00115f3f); + nvkm_wr32(device, 0x4006b0, 0x40000020); } else { - nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); } /* Turn all the tiling regions off. */ for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); - nv_wr32(gr, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); - nv_wr32(gr, NV10_PGRAPH_STATE, 0xFFFFFFFF); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_STATE, 0xFFFFFFFF); - nv_mask(gr, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); - nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(gr, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); + nvkm_mask(device, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); + nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nvkm_wr32(device, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 3e5428552cb2..8e264f79c0df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -118,19 +118,20 @@ nv20_gr_context_fini(struct nvkm_object *object, bool suspend) { struct nv20_gr *gr = (void *)object->engine; struct nv20_gr_chan *chan = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; int chid = -1; - nv_mask(gr, 0x400720, 0x00000001, 0x00000000); - if (nv_rd32(gr, 0x400144) & 0x00010000) - chid = (nv_rd32(gr, 0x400148) & 0x1f000000) >> 24; + nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); + if (nvkm_rd32(device, 0x400144) & 0x00010000) + chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; if (chan->chid == chid) { - nv_wr32(gr, 0x400784, nv_gpuobj(chan)->addr >> 4); - nv_wr32(gr, 0x400788, 0x00000002); + nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4); + nvkm_wr32(device, 0x400788, 0x00000002); nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); - nv_wr32(gr, 0x400144, 0x10000000); - nv_mask(gr, 0x400148, 0xff000000, 0x1f000000); + nvkm_wr32(device, 0x400144, 0x10000000); + nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000); } - nv_mask(gr, 0x400720, 0x00000001, 0x00000001); + nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); nv_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); return nvkm_gr_context_fini(&chan->base, suspend); @@ -156,29 +157,30 @@ nv20_gr_cclass = { void nv20_gr_tile_prog(struct nvkm_engine *engine, int i) { - struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; - struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nv20_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo *fifo = device->fifo; + struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; fifo->pause(fifo, &flags); nv04_gr_idle(gr); - nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->limit); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->pitch); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->addr); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); if (nv_device(engine)->chipset != 0x34) { - nv_wr32(gr, NV20_PGRAPH_ZCOMP(i), tile->zcomp); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, tile->zcomp); + nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); } fifo->start(fifo, &flags); @@ -191,15 +193,16 @@ nv20_gr_intr(struct nvkm_subdev *subdev) struct nvkm_object *engctx; struct nvkm_handle *handle; struct nv20_gr *gr = (void *)subdev; - u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); - u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); + u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); + u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); + u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); u32 chid = (addr & 0x01f00000) >> 20; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xfff; + u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; u32 show = stat; engctx = nvkm_engctx_get(engine, chid); @@ -212,8 +215,8 @@ nv20_gr_intr(struct nvkm_subdev *subdev) } } - nv_wr32(gr, NV03_PGRAPH_INTR, stat); - nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); + nvkm_wr32(device, NV03_PGRAPH_INTR, stat); + nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { nv_error(gr, "%s", ""); @@ -271,7 +274,8 @@ nv20_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nv20_gr *gr = (void *)engine; - struct nvkm_fb *fb = nvkm_fb(object); + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; u32 tmp, vramsz; int ret, i; @@ -279,87 +283,87 @@ nv20_gr_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); + nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); if (nv_device(gr)->chipset == 0x20) { - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x003d0000); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000); for (i = 0; i < 15; i++) - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); } else { - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x02c80000); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000); for (i = 0; i < 32; i++) - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, 0x00000000); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); } - nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x00118700); - nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ - nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00000000); - nv_wr32(gr, 0x40009C , 0x00000040); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ + nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); + nvkm_wr32(device, 0x40009C , 0x00000040); if (nv_device(gr)->chipset >= 0x25) { - nv_wr32(gr, 0x400890, 0x00a8cfff); - nv_wr32(gr, 0x400610, 0x304B1FB6); - nv_wr32(gr, 0x400B80, 0x1cbd3883); - nv_wr32(gr, 0x400B84, 0x44000000); - nv_wr32(gr, 0x400098, 0x40000080); - nv_wr32(gr, 0x400B88, 0x000000ff); + nvkm_wr32(device, 0x400890, 0x00a8cfff); + nvkm_wr32(device, 0x400610, 0x304B1FB6); + nvkm_wr32(device, 0x400B80, 0x1cbd3883); + nvkm_wr32(device, 0x400B84, 0x44000000); + nvkm_wr32(device, 0x400098, 0x40000080); + nvkm_wr32(device, 0x400B88, 0x000000ff); } else { - nv_wr32(gr, 0x400880, 0x0008c7df); - nv_wr32(gr, 0x400094, 0x00000005); - nv_wr32(gr, 0x400B80, 0x45eae20e); - nv_wr32(gr, 0x400B84, 0x24000000); - nv_wr32(gr, 0x400098, 0x00000040); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00038); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000030); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E10038); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000030); + nvkm_wr32(device, 0x400880, 0x0008c7df); + nvkm_wr32(device, 0x400094, 0x00000005); + nvkm_wr32(device, 0x400B80, 0x45eae20e); + nvkm_wr32(device, 0x400B84, 0x24000000); + nvkm_wr32(device, 0x400098, 0x00000040); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030); } /* Turn all the tiling regions off. */ for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); - nv_wr32(gr, 0x4009a0, nv_rd32(gr, 0x100324)); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA, nv_rd32(gr, 0x100324)); + nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324)); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324)); - nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); - tmp = nv_rd32(gr, NV10_PGRAPH_SURFACE) & 0x0007ff00; - nv_wr32(gr, NV10_PGRAPH_SURFACE, tmp); - tmp = nv_rd32(gr, NV10_PGRAPH_SURFACE) | 0x00020100; - nv_wr32(gr, NV10_PGRAPH_SURFACE, tmp); + tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00; + nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp); + tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100; + nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp); /* begin RAM config */ vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; - nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204)); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , nv_rd32(gr, 0x100200)); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , nv_rd32(gr, 0x100204)); - nv_wr32(gr, 0x400820, 0); - nv_wr32(gr, 0x400824, 0); - nv_wr32(gr, 0x400864, vramsz - 1); - nv_wr32(gr, 0x400868, vramsz - 1); + nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204)); + nvkm_wr32(device, 0x400820, 0); + nvkm_wr32(device, 0x400824, 0); + nvkm_wr32(device, 0x400864, vramsz - 1); + nvkm_wr32(device, 0x400868, vramsz - 1); /* interesting.. the below overwrites some of the tile setup above.. */ - nv_wr32(gr, 0x400B20, 0x00000000); - nv_wr32(gr, 0x400B04, 0xFFFFFFFF); + nvkm_wr32(device, 0x400B20, 0x00000000); + nvkm_wr32(device, 0x400B04, 0xFFFFFFFF); - nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); - nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); - nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); - nv_wr32(gr, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); + nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); + nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); + nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); + nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index dea1cb907318..8be77b4f15ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -153,67 +153,68 @@ nv30_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); struct nv20_gr *gr = (void *)engine; - struct nvkm_fb *fb = nvkm_fb(object); + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; int ret, i; ret = nvkm_gr_init(&gr->base); if (ret) return ret; - nv_wr32(gr, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); - - nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(gr, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0); - nv_wr32(gr, 0x400890, 0x01b463ff); - nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xf2de0475); - nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000); - nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); - nv_wr32(gr, 0x400B80, 0x1003d888); - nv_wr32(gr, 0x400B84, 0x0c000000); - nv_wr32(gr, 0x400098, 0x00000000); - nv_wr32(gr, 0x40009C, 0x0005ad00); - nv_wr32(gr, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ - nv_wr32(gr, 0x4000a0, 0x00000000); - nv_wr32(gr, 0x4000a4, 0x00000008); - nv_wr32(gr, 0x4008a8, 0xb784a400); - nv_wr32(gr, 0x400ba0, 0x002f8685); - nv_wr32(gr, 0x400ba4, 0x00231f3f); - nv_wr32(gr, 0x4008a4, 0x40000020); + nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); + + nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); + nvkm_wr32(device, 0x400890, 0x01b463ff); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); + nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); + nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); + nvkm_wr32(device, 0x400B80, 0x1003d888); + nvkm_wr32(device, 0x400B84, 0x0c000000); + nvkm_wr32(device, 0x400098, 0x00000000); + nvkm_wr32(device, 0x40009C, 0x0005ad00); + nvkm_wr32(device, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ + nvkm_wr32(device, 0x4000a0, 0x00000000); + nvkm_wr32(device, 0x4000a4, 0x00000008); + nvkm_wr32(device, 0x4008a8, 0xb784a400); + nvkm_wr32(device, 0x400ba0, 0x002f8685); + nvkm_wr32(device, 0x400ba4, 0x00231f3f); + nvkm_wr32(device, 0x4008a4, 0x40000020); if (nv_device(gr)->chipset == 0x34) { - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00200201); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000008); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000032); - nv_wr32(gr, NV10_PGRAPH_RDI_INDEX, 0x00E00004); - nv_wr32(gr, NV10_PGRAPH_RDI_DATA , 0x00000002); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000008); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000032); + nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00004); + nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000002); } - nv_wr32(gr, 0x4000c0, 0x00000016); + nvkm_wr32(device, 0x4000c0, 0x00000016); /* Turn all the tiling regions off. */ for (i = 0; i < fb->tile.regions; i++) engine->tile_prog(engine, i); - nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10000100); - nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF); - nv_wr32(gr, 0x0040075c , 0x00000001); + nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); + nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nvkm_wr32(device, 0x0040075c , 0x00000001); /* begin RAM config */ /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ - nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204)); + nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); if (nv_device(gr)->chipset != 0x34) { - nv_wr32(gr, 0x400750, 0x00EA0000); - nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x400750, 0x00EA0004); - nv_wr32(gr, 0x400754, nv_rd32(gr, 0x100204)); + nvkm_wr32(device, 0x400750, 0x00EA0000); + nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x400750, 0x00EA0004); + nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); } return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 3c2df9d29ff3..edcaa65b1e09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -42,7 +42,7 @@ struct nv40_gr_chan { static u64 nv40_gr_units(struct nvkm_gr *gr) { - return nv_rd32(gr, 0x1540); + return nvkm_rd32(gr->engine.subdev.device, 0x1540); } /******************************************************************************* @@ -155,31 +155,32 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend) { struct nv40_gr *gr = (void *)object->engine; struct nv40_gr_chan *chan = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; int ret = 0; - nv_mask(gr, 0x400720, 0x00000001, 0x00000000); + nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); - if (nv_rd32(gr, 0x40032c) == inst) { + if (nvkm_rd32(device, 0x40032c) == inst) { if (suspend) { - nv_wr32(gr, 0x400720, 0x00000000); - nv_wr32(gr, 0x400784, inst); - nv_mask(gr, 0x400310, 0x00000020, 0x00000020); - nv_mask(gr, 0x400304, 0x00000001, 0x00000001); + nvkm_wr32(device, 0x400720, 0x00000000); + nvkm_wr32(device, 0x400784, inst); + nvkm_mask(device, 0x400310, 0x00000020, 0x00000020); + nvkm_mask(device, 0x400304, 0x00000001, 0x00000001); if (!nv_wait(gr, 0x400300, 0x00000001, 0x00000000)) { - u32 insn = nv_rd32(gr, 0x400308); + u32 insn = nvkm_rd32(device, 0x400308); nv_warn(gr, "ctxprog timeout 0x%08x\n", insn); ret = -EBUSY; } } - nv_mask(gr, 0x40032c, 0x01000000, 0x00000000); + nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000); } - if (nv_rd32(gr, 0x400330) == inst) - nv_mask(gr, 0x400330, 0x01000000, 0x00000000); + if (nvkm_rd32(device, 0x400330) == inst) + nvkm_mask(device, 0x400330, 0x01000000, 0x00000000); - nv_mask(gr, 0x400720, 0x00000001, 0x00000001); + nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); return ret; } @@ -203,9 +204,10 @@ nv40_gr_cclass = { static void nv40_gr_tile_prog(struct nvkm_engine *engine, int i) { - struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; - struct nvkm_fifo *fifo = nvkm_fifo(engine); struct nv40_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo *fifo = device->fifo; + struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; fifo->pause(fifo, &flags); @@ -218,23 +220,23 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) case 0x43: case 0x45: case 0x4e: - nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr); - nv_wr32(gr, NV40_PGRAPH_TSIZE1(i), tile->pitch); - nv_wr32(gr, NV40_PGRAPH_TLIMIT1(i), tile->limit); - nv_wr32(gr, NV40_PGRAPH_TILE1(i), tile->addr); + nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); switch (nv_device(gr)->chipset) { case 0x40: case 0x45: - nv_wr32(gr, NV20_PGRAPH_ZCOMP(i), tile->zcomp); - nv_wr32(gr, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); + nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); + nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); break; case 0x41: case 0x42: case 0x43: - nv_wr32(gr, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); - nv_wr32(gr, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); + nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); + nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); break; default: break; @@ -242,9 +244,9 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) break; case 0x44: case 0x4a: - nv_wr32(gr, NV20_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(gr, NV20_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(gr, NV20_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); break; case 0x46: case 0x4c: @@ -254,18 +256,18 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) case 0x63: case 0x67: case 0x68: - nv_wr32(gr, NV47_PGRAPH_TSIZE(i), tile->pitch); - nv_wr32(gr, NV47_PGRAPH_TLIMIT(i), tile->limit); - nv_wr32(gr, NV47_PGRAPH_TILE(i), tile->addr); - nv_wr32(gr, NV40_PGRAPH_TSIZE1(i), tile->pitch); - nv_wr32(gr, NV40_PGRAPH_TLIMIT1(i), tile->limit); - nv_wr32(gr, NV40_PGRAPH_TILE1(i), tile->addr); + nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); switch (nv_device(gr)->chipset) { case 0x47: case 0x49: case 0x4b: - nv_wr32(gr, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); - nv_wr32(gr, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); + nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); + nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); break; default: break; @@ -286,15 +288,16 @@ nv40_gr_intr(struct nvkm_subdev *subdev) struct nvkm_object *engctx; struct nvkm_handle *handle = NULL; struct nv40_gr *gr = (void *)subdev; - u32 stat = nv_rd32(gr, NV03_PGRAPH_INTR); - u32 nsource = nv_rd32(gr, NV03_PGRAPH_NSOURCE); - u32 nstatus = nv_rd32(gr, NV03_PGRAPH_NSTATUS); - u32 inst = nv_rd32(gr, 0x40032c) & 0x000fffff; - u32 addr = nv_rd32(gr, NV04_PGRAPH_TRAPPED_ADDR); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); + u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); + u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); + u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff; + u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(gr, NV04_PGRAPH_TRAPPED_DATA); - u32 class = nv_rd32(gr, 0x400160 + subc * 4) & 0xffff; + u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); + u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; u32 show = stat; int chid; @@ -310,12 +313,12 @@ nv40_gr_intr(struct nvkm_subdev *subdev) } if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { - nv_mask(gr, 0x402000, 0, 0); + nvkm_mask(device, 0x402000, 0, 0); } } - nv_wr32(gr, NV03_PGRAPH_INTR, stat); - nv_wr32(gr, NV04_PGRAPH_FIFO, 0x00000001); + nvkm_wr32(device, NV03_PGRAPH_INTR, stat); + nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { nv_error(gr, "%s", ""); @@ -364,8 +367,9 @@ static int nv40_gr_init(struct nvkm_object *object) { struct nvkm_engine *engine = nv_engine(object); - struct nvkm_fb *fb = nvkm_fb(object); struct nv40_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fb *fb = device->fb; int ret, i, j; u32 vramsz; @@ -379,89 +383,89 @@ nv40_gr_init(struct nvkm_object *object) return ret; /* No context present currently */ - nv_wr32(gr, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); + nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); - nv_wr32(gr, NV03_PGRAPH_INTR , 0xFFFFFFFF); - nv_wr32(gr, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); + nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); - nv_wr32(gr, NV04_PGRAPH_DEBUG_0, 0x00000000); - nv_wr32(gr, NV04_PGRAPH_DEBUG_1, 0x401287c0); - nv_wr32(gr, NV04_PGRAPH_DEBUG_3, 0xe0de8055); - nv_wr32(gr, NV10_PGRAPH_DEBUG_4, 0x00008000); - nv_wr32(gr, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055); + nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); + nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); - nv_wr32(gr, NV10_PGRAPH_CTX_CONTROL, 0x10010100); - nv_wr32(gr, NV10_PGRAPH_STATE , 0xFFFFFFFF); + nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100); + nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); - j = nv_rd32(gr, 0x1540) & 0xff; + j = nvkm_rd32(device, 0x1540) & 0xff; if (j) { for (i = 0; !(j & 1); j >>= 1, i++) ; - nv_wr32(gr, 0x405000, i); + nvkm_wr32(device, 0x405000, i); } if (nv_device(gr)->chipset == 0x40) { - nv_wr32(gr, 0x4009b0, 0x83280fff); - nv_wr32(gr, 0x4009b4, 0x000000a0); + nvkm_wr32(device, 0x4009b0, 0x83280fff); + nvkm_wr32(device, 0x4009b4, 0x000000a0); } else { - nv_wr32(gr, 0x400820, 0x83280eff); - nv_wr32(gr, 0x400824, 0x000000a0); + nvkm_wr32(device, 0x400820, 0x83280eff); + nvkm_wr32(device, 0x400824, 0x000000a0); } switch (nv_device(gr)->chipset) { case 0x40: case 0x45: - nv_wr32(gr, 0x4009b8, 0x0078e366); - nv_wr32(gr, 0x4009bc, 0x0000014c); + nvkm_wr32(device, 0x4009b8, 0x0078e366); + nvkm_wr32(device, 0x4009bc, 0x0000014c); break; case 0x41: case 0x42: /* pciid also 0x00Cx */ /* case 0x0120: XXX (pciid) */ - nv_wr32(gr, 0x400828, 0x007596ff); - nv_wr32(gr, 0x40082c, 0x00000108); + nvkm_wr32(device, 0x400828, 0x007596ff); + nvkm_wr32(device, 0x40082c, 0x00000108); break; case 0x43: - nv_wr32(gr, 0x400828, 0x0072cb77); - nv_wr32(gr, 0x40082c, 0x00000108); + nvkm_wr32(device, 0x400828, 0x0072cb77); + nvkm_wr32(device, 0x40082c, 0x00000108); break; case 0x44: case 0x46: /* G72 */ case 0x4a: case 0x4c: /* G7x-based C51 */ case 0x4e: - nv_wr32(gr, 0x400860, 0); - nv_wr32(gr, 0x400864, 0); + nvkm_wr32(device, 0x400860, 0); + nvkm_wr32(device, 0x400864, 0); break; case 0x47: /* G70 */ case 0x49: /* G71 */ case 0x4b: /* G73 */ - nv_wr32(gr, 0x400828, 0x07830610); - nv_wr32(gr, 0x40082c, 0x0000016A); + nvkm_wr32(device, 0x400828, 0x07830610); + nvkm_wr32(device, 0x40082c, 0x0000016A); break; default: break; } - nv_wr32(gr, 0x400b38, 0x2ffff800); - nv_wr32(gr, 0x400b3c, 0x00006000); + nvkm_wr32(device, 0x400b38, 0x2ffff800); + nvkm_wr32(device, 0x400b3c, 0x00006000); /* Tiling related stuff. */ switch (nv_device(gr)->chipset) { case 0x44: case 0x4a: - nv_wr32(gr, 0x400bc4, 0x1003d888); - nv_wr32(gr, 0x400bbc, 0xb7a7b500); + nvkm_wr32(device, 0x400bc4, 0x1003d888); + nvkm_wr32(device, 0x400bbc, 0xb7a7b500); break; case 0x46: - nv_wr32(gr, 0x400bc4, 0x0000e024); - nv_wr32(gr, 0x400bbc, 0xb7a7b520); + nvkm_wr32(device, 0x400bc4, 0x0000e024); + nvkm_wr32(device, 0x400bbc, 0xb7a7b520); break; case 0x4c: case 0x4e: case 0x67: - nv_wr32(gr, 0x400bc4, 0x1003d888); - nv_wr32(gr, 0x400bbc, 0xb7a7b540); + nvkm_wr32(device, 0x400bc4, 0x1003d888); + nvkm_wr32(device, 0x400bbc, 0xb7a7b540); break; default: break; @@ -475,14 +479,14 @@ nv40_gr_init(struct nvkm_object *object) vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; switch (nv_device(gr)->chipset) { case 0x40: - nv_wr32(gr, 0x4009A4, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x4009A8, nv_rd32(gr, 0x100204)); - nv_wr32(gr, 0x4069A4, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x4069A8, nv_rd32(gr, 0x100204)); - nv_wr32(gr, 0x400820, 0); - nv_wr32(gr, 0x400824, 0); - nv_wr32(gr, 0x400864, vramsz); - nv_wr32(gr, 0x400868, vramsz); + nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); + nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204)); + nvkm_wr32(device, 0x400820, 0); + nvkm_wr32(device, 0x400824, 0); + nvkm_wr32(device, 0x400864, vramsz); + nvkm_wr32(device, 0x400868, vramsz); break; default: switch (nv_device(gr)->chipset) { @@ -493,20 +497,20 @@ nv40_gr_init(struct nvkm_object *object) case 0x4e: case 0x44: case 0x4a: - nv_wr32(gr, 0x4009F0, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x4009F4, nv_rd32(gr, 0x100204)); + nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204)); break; default: - nv_wr32(gr, 0x400DF0, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x400DF4, nv_rd32(gr, 0x100204)); + nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204)); break; } - nv_wr32(gr, 0x4069F0, nv_rd32(gr, 0x100200)); - nv_wr32(gr, 0x4069F4, nv_rd32(gr, 0x100204)); - nv_wr32(gr, 0x400840, 0); - nv_wr32(gr, 0x400844, 0); - nv_wr32(gr, 0x4008A0, vramsz); - nv_wr32(gr, 0x4008A4, vramsz); + nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200)); + nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204)); + nvkm_wr32(device, 0x400840, 0); + nvkm_wr32(device, 0x400844, 0); + nvkm_wr32(device, 0x4008A0, vramsz); + nvkm_wr32(device, 0x4008A4, vramsz); break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 70be675b1928..ade34d8a4ea0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -41,7 +41,7 @@ struct nv50_gr_chan { static u64 nv50_gr_units(struct nvkm_gr *gr) { - return nv_rd32(gr, 0x1540); + return nvkm_rd32(gr->engine.subdev.device, 0x1540); } /******************************************************************************* @@ -235,31 +235,32 @@ nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, static int g84_gr_tlb_flush(struct nvkm_engine *engine) { - struct nvkm_timer *tmr = nvkm_timer(engine); struct nv50_gr *gr = (void *)engine; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_timer *tmr = device->timer; bool idle, timeout = false; unsigned long flags; u64 start; u32 tmp; spin_lock_irqsave(&gr->lock, flags); - nv_mask(gr, 0x400500, 0x00000001, 0x00000000); + nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); start = tmr->read(tmr); do { idle = true; - for (tmp = nv_rd32(gr, 0x400380); tmp && idle; tmp >>= 3) { + for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { if ((tmp & 7) == 1) idle = false; } - for (tmp = nv_rd32(gr, 0x400384); tmp && idle; tmp >>= 3) { + for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { if ((tmp & 7) == 1) idle = false; } - for (tmp = nv_rd32(gr, 0x400388); tmp && idle; tmp >>= 3) { + for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { if ((tmp & 7) == 1) idle = false; } @@ -269,24 +270,24 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) if (timeout) { nv_error(gr, "PGRAPH TLB flush idle timeout fail\n"); - tmp = nv_rd32(gr, 0x400700); + tmp = nvkm_rd32(device, 0x400700); nv_error(gr, "PGRAPH_STATUS : 0x%08x", tmp); nvkm_bitfield_print(nv50_gr_status, tmp); pr_cont("\n"); nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, - nv_rd32(gr, 0x400380)); + nvkm_rd32(device, 0x400380)); nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1, - nv_rd32(gr, 0x400384)); + nvkm_rd32(device, 0x400384)); nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2, - nv_rd32(gr, 0x400388)); + nvkm_rd32(device, 0x400388)); } - nv_wr32(gr, 0x100c80, 0x00000001); + nvkm_wr32(device, 0x100c80, 0x00000001); if (!nv_wait(gr, 0x100c80, 0x00000001, 0x00000000)) nv_error(gr, "vm flush timeout\n"); - nv_mask(gr, 0x400500, 0x00000001, 0x00000001); + nvkm_mask(device, 0x400500, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); return timeout ? -EBUSY : 0; } @@ -427,13 +428,14 @@ static void nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp) { - u32 e0c = nv_rd32(gr, ustatus_addr + 0x04); - u32 e10 = nv_rd32(gr, ustatus_addr + 0x08); - u32 e14 = nv_rd32(gr, ustatus_addr + 0x0c); - u32 e18 = nv_rd32(gr, ustatus_addr + 0x10); - u32 e1c = nv_rd32(gr, ustatus_addr + 0x14); - u32 e20 = nv_rd32(gr, ustatus_addr + 0x18); - u32 e24 = nv_rd32(gr, ustatus_addr + 0x1c); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04); + u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08); + u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c); + u32 e18 = nvkm_rd32(device, ustatus_addr + 0x10); + u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14); + u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18); + u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c); /* CUDA memory: l[], g[] or stack. */ if (ustatus & 0x00000080) { @@ -465,7 +467,8 @@ nv50_gr_prop_trap(struct nv50_gr *gr, static void nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) { - u32 units = nv_rd32(gr, 0x1540); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 units = nvkm_rd32(device, 0x1540); u32 addr, mp10, status, pc, oplow, ophigh; int i; int mps = 0; @@ -476,15 +479,15 @@ nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) addr = 0x408200 + (tpid << 12) + (i << 7); else addr = 0x408100 + (tpid << 11) + (i << 7); - mp10 = nv_rd32(gr, addr + 0x10); - status = nv_rd32(gr, addr + 0x14); + mp10 = nvkm_rd32(device, addr + 0x10); + status = nvkm_rd32(device, addr + 0x14); if (!status) continue; if (display) { - nv_rd32(gr, addr + 0x20); - pc = nv_rd32(gr, addr + 0x24); - oplow = nv_rd32(gr, addr + 0x70); - ophigh = nv_rd32(gr, addr + 0x74); + nvkm_rd32(device, addr + 0x20); + pc = nvkm_rd32(device, addr + 0x24); + oplow = nvkm_rd32(device, addr + 0x70); + ophigh = nvkm_rd32(device, addr + 0x74); nv_error(gr, "TRAP_MP_EXEC - " "TP %d MP %d:", tpid, i); nvkm_bitfield_print(nv50_mp_exec_errors, status); @@ -492,8 +495,8 @@ nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) pc&0xffffff, pc >> 24, oplow, ophigh); } - nv_wr32(gr, addr + 0x10, mp10); - nv_wr32(gr, addr + 0x14, 0); + nvkm_wr32(device, addr + 0x10, mp10); + nvkm_wr32(device, addr + 0x14, 0); mps++; } if (!mps && display) @@ -505,8 +508,9 @@ static void nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, u32 ustatus_new, int display, const char *name) { + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 units = nvkm_rd32(device, 0x1540); int tps = 0; - u32 units = nv_rd32(gr, 0x1540); int i, r; u32 ustatus_addr, ustatus; for (i = 0; i < 16; i++) { @@ -516,7 +520,7 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, ustatus_addr = ustatus_old + (i << 12); else ustatus_addr = ustatus_new + (i << 11); - ustatus = nv_rd32(gr, ustatus_addr) & 0x7fffffff; + ustatus = nvkm_rd32(device, ustatus_addr) & 0x7fffffff; if (!ustatus) continue; tps++; @@ -526,7 +530,7 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, nv_error(gr, "magic set %d:\n", i); for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) nv_error(gr, "\t0x%08x: 0x%08x\n", r, - nv_rd32(gr, r)); + nvkm_rd32(device, r)); if (ustatus) { nv_error(gr, "%s - TP%d:", name, i); nvkm_bitfield_print(nv50_tex_traps, @@ -559,7 +563,7 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, if (display) nv_error(gr, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); } - nv_wr32(gr, ustatus_addr, 0xc0000000); + nvkm_wr32(device, ustatus_addr, 0xc0000000); } if (!tps && display) @@ -570,7 +574,8 @@ static int nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, int chid, u64 inst, struct nvkm_object *engctx) { - u32 status = nv_rd32(gr, 0x400108); + struct nvkm_device *device = gr->base.engine.subdev.device; + u32 status = nvkm_rd32(device, 0x400108); u32 ustatus; if (!status && display) { @@ -582,22 +587,22 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, * COND, QUERY. If you get a trap from it, the command is still stuck * in DISPATCH and you need to do something about it. */ if (status & 0x001) { - ustatus = nv_rd32(gr, 0x400804) & 0x7fffffff; + ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff; if (!ustatus && display) { nv_error(gr, "TRAP_DISPATCH - no ustatus?\n"); } - nv_wr32(gr, 0x400500, 0x00000000); + nvkm_wr32(device, 0x400500, 0x00000000); /* Known to be triggered by screwed up NOTIFY and COND... */ if (ustatus & 0x00000001) { - u32 addr = nv_rd32(gr, 0x400808); + u32 addr = nvkm_rd32(device, 0x400808); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 datal = nv_rd32(gr, 0x40080c); - u32 datah = nv_rd32(gr, 0x400810); - u32 class = nv_rd32(gr, 0x400814); - u32 r848 = nv_rd32(gr, 0x400848); + u32 datal = nvkm_rd32(device, 0x40080c); + u32 datah = nvkm_rd32(device, 0x400810); + u32 class = nvkm_rd32(device, 0x400814); + u32 r848 = nvkm_rd32(device, 0x400848); nv_error(gr, "TRAP DISPATCH_FAULT\n"); if (display && (addr & 0x80000000)) { @@ -611,18 +616,18 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, nv_error(gr, "no stuck command?\n"); } - nv_wr32(gr, 0x400808, 0); - nv_wr32(gr, 0x4008e8, nv_rd32(gr, 0x4008e8) & 3); - nv_wr32(gr, 0x400848, 0); + nvkm_wr32(device, 0x400808, 0); + nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3); + nvkm_wr32(device, 0x400848, 0); ustatus &= ~0x00000001; } if (ustatus & 0x00000002) { - u32 addr = nv_rd32(gr, 0x40084c); + u32 addr = nvkm_rd32(device, 0x40084c); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(gr, 0x40085c); - u32 class = nv_rd32(gr, 0x400814); + u32 data = nvkm_rd32(device, 0x40085c); + u32 class = nvkm_rd32(device, 0x400814); nv_error(gr, "TRAP DISPATCH_QUERY\n"); if (display && (addr & 0x80000000)) { @@ -636,7 +641,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, nv_error(gr, "no stuck command?\n"); } - nv_wr32(gr, 0x40084c, 0); + nvkm_wr32(device, 0x40084c, 0); ustatus &= ~0x00000002; } @@ -645,8 +650,8 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, "0x%08x)\n", ustatus); } - nv_wr32(gr, 0x400804, 0xc0000000); - nv_wr32(gr, 0x400108, 0x001); + nvkm_wr32(device, 0x400804, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x001); status &= ~0x001; if (!status) return 0; @@ -654,81 +659,81 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, /* M2MF: Memory to memory copy engine. */ if (status & 0x002) { - u32 ustatus = nv_rd32(gr, 0x406800) & 0x7fffffff; + u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff; if (display) { nv_error(gr, "TRAP_M2MF"); nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus); pr_cont("\n"); nv_error(gr, "TRAP_M2MF %08x %08x %08x %08x\n", - nv_rd32(gr, 0x406804), nv_rd32(gr, 0x406808), - nv_rd32(gr, 0x40680c), nv_rd32(gr, 0x406810)); + nvkm_rd32(device, 0x406804), nvkm_rd32(device, 0x406808), + nvkm_rd32(device, 0x40680c), nvkm_rd32(device, 0x406810)); } /* No sane way found yet -- just reset the bugger. */ - nv_wr32(gr, 0x400040, 2); - nv_wr32(gr, 0x400040, 0); - nv_wr32(gr, 0x406800, 0xc0000000); - nv_wr32(gr, 0x400108, 0x002); + nvkm_wr32(device, 0x400040, 2); + nvkm_wr32(device, 0x400040, 0); + nvkm_wr32(device, 0x406800, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x002); status &= ~0x002; } /* VFETCH: Fetches data from vertex buffers. */ if (status & 0x004) { - u32 ustatus = nv_rd32(gr, 0x400c04) & 0x7fffffff; + u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff; if (display) { nv_error(gr, "TRAP_VFETCH"); nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus); pr_cont("\n"); nv_error(gr, "TRAP_VFETCH %08x %08x %08x %08x\n", - nv_rd32(gr, 0x400c00), nv_rd32(gr, 0x400c08), - nv_rd32(gr, 0x400c0c), nv_rd32(gr, 0x400c10)); + nvkm_rd32(device, 0x400c00), nvkm_rd32(device, 0x400c08), + nvkm_rd32(device, 0x400c0c), nvkm_rd32(device, 0x400c10)); } - nv_wr32(gr, 0x400c04, 0xc0000000); - nv_wr32(gr, 0x400108, 0x004); + nvkm_wr32(device, 0x400c04, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x004); status &= ~0x004; } /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ if (status & 0x008) { - ustatus = nv_rd32(gr, 0x401800) & 0x7fffffff; + ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff; if (display) { nv_error(gr, "TRAP_STRMOUT"); nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus); pr_cont("\n"); nv_error(gr, "TRAP_STRMOUT %08x %08x %08x %08x\n", - nv_rd32(gr, 0x401804), nv_rd32(gr, 0x401808), - nv_rd32(gr, 0x40180c), nv_rd32(gr, 0x401810)); + nvkm_rd32(device, 0x401804), nvkm_rd32(device, 0x401808), + nvkm_rd32(device, 0x40180c), nvkm_rd32(device, 0x401810)); } /* No sane way found yet -- just reset the bugger. */ - nv_wr32(gr, 0x400040, 0x80); - nv_wr32(gr, 0x400040, 0); - nv_wr32(gr, 0x401800, 0xc0000000); - nv_wr32(gr, 0x400108, 0x008); + nvkm_wr32(device, 0x400040, 0x80); + nvkm_wr32(device, 0x400040, 0); + nvkm_wr32(device, 0x401800, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x008); status &= ~0x008; } /* CCACHE: Handles code and c[] caches and fills them. */ if (status & 0x010) { - ustatus = nv_rd32(gr, 0x405018) & 0x7fffffff; + ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff; if (display) { nv_error(gr, "TRAP_CCACHE"); nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus); pr_cont("\n"); nv_error(gr, "TRAP_CCACHE %08x %08x %08x %08x" " %08x %08x %08x\n", - nv_rd32(gr, 0x405000), nv_rd32(gr, 0x405004), - nv_rd32(gr, 0x405008), nv_rd32(gr, 0x40500c), - nv_rd32(gr, 0x405010), nv_rd32(gr, 0x405014), - nv_rd32(gr, 0x40501c)); + nvkm_rd32(device, 0x405000), nvkm_rd32(device, 0x405004), + nvkm_rd32(device, 0x405008), nvkm_rd32(device, 0x40500c), + nvkm_rd32(device, 0x405010), nvkm_rd32(device, 0x405014), + nvkm_rd32(device, 0x40501c)); } - nv_wr32(gr, 0x405018, 0xc0000000); - nv_wr32(gr, 0x400108, 0x010); + nvkm_wr32(device, 0x405018, 0xc0000000); + nvkm_wr32(device, 0x400108, 0x010); status &= ~0x010; } @@ -736,10 +741,10 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, * remaining, so try to handle it anyway. Perhaps related to that * unknown DMA slot on tesla? */ if (status & 0x20) { - ustatus = nv_rd32(gr, 0x402000) & 0x7fffffff; + ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff; if (display) nv_error(gr, "TRAP_UNKC04 0x%08x\n", ustatus); - nv_wr32(gr, 0x402000, 0xc0000000); + nvkm_wr32(device, 0x402000, 0xc0000000); /* no status modifiction on purpose */ } @@ -747,7 +752,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x040) { nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display, "TRAP_TEXTURE"); - nv_wr32(gr, 0x400108, 0x040); + nvkm_wr32(device, 0x400108, 0x040); status &= ~0x040; } @@ -755,7 +760,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x080) { nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display, "TRAP_MP"); - nv_wr32(gr, 0x400108, 0x080); + nvkm_wr32(device, 0x400108, 0x080); status &= ~0x080; } @@ -764,14 +769,14 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x100) { nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display, "TRAP_PROP"); - nv_wr32(gr, 0x400108, 0x100); + nvkm_wr32(device, 0x400108, 0x100); status &= ~0x100; } if (status) { if (display) nv_error(gr, "TRAP: unknown 0x%08x\n", status); - nv_wr32(gr, 0x400108, status); + nvkm_wr32(device, 0x400108, status); } return 1; @@ -780,18 +785,19 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, static void nv50_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *fifo = nvkm_fifo(subdev); + struct nv50_gr *gr = (void *)subdev; + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo *fifo = device->fifo; struct nvkm_engine *engine = nv_engine(subdev); struct nvkm_object *engctx; struct nvkm_handle *handle = NULL; - struct nv50_gr *gr = (void *)subdev; - u32 stat = nv_rd32(gr, 0x400100); - u32 inst = nv_rd32(gr, 0x40032c) & 0x0fffffff; - u32 addr = nv_rd32(gr, 0x400704); + u32 stat = nvkm_rd32(device, 0x400100); + u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff; + u32 addr = nvkm_rd32(device, 0x400704); u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00001ffc); - u32 data = nv_rd32(gr, 0x400708); - u32 class = nv_rd32(gr, 0x400814); + u32 data = nvkm_rd32(device, 0x400708); + u32 class = nvkm_rd32(device, 0x400814); u32 show = stat, show_bitfield = stat; int chid; @@ -806,7 +812,7 @@ nv50_gr_intr(struct nvkm_subdev *subdev) } if (show & 0x00100000) { - u32 ecode = nv_rd32(gr, 0x400110); + u32 ecode = nvkm_rd32(device, 0x400110); nv_error(gr, "DATA_ERROR "); nvkm_enum_print(nv50_data_error_names, ecode); pr_cont("\n"); @@ -820,8 +826,8 @@ nv50_gr_intr(struct nvkm_subdev *subdev) show_bitfield &= ~0x00200000; } - nv_wr32(gr, 0x400100, stat); - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400100, stat); + nvkm_wr32(device, 0x400500, 0x00010001); if (show) { show &= show_bitfield; @@ -836,8 +842,8 @@ nv50_gr_intr(struct nvkm_subdev *subdev) subc, class, mthd, data); } - if (nv_rd32(gr, 0x400824) & (1 << 31)) - nv_wr32(gr, 0x400824, nv_rd32(gr, 0x400824) & ~(1 << 31)); + if (nvkm_rd32(device, 0x400824) & (1 << 31)) + nvkm_wr32(device, 0x400824, nvkm_rd32(device, 0x400824) & ~(1 << 31)); nvkm_engctx_put(engctx); } @@ -902,6 +908,7 @@ static int nv50_gr_init(struct nvkm_object *object) { struct nv50_gr *gr = (void *)object; + struct nvkm_device *device = gr->base.engine.subdev.device; int ret, units, i; ret = nvkm_gr_init(&gr->base); @@ -909,66 +916,66 @@ nv50_gr_init(struct nvkm_object *object) return ret; /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ - nv_wr32(gr, 0x40008c, 0x00000004); + nvkm_wr32(device, 0x40008c, 0x00000004); /* reset/enable traps and interrupts */ - nv_wr32(gr, 0x400804, 0xc0000000); - nv_wr32(gr, 0x406800, 0xc0000000); - nv_wr32(gr, 0x400c04, 0xc0000000); - nv_wr32(gr, 0x401800, 0xc0000000); - nv_wr32(gr, 0x405018, 0xc0000000); - nv_wr32(gr, 0x402000, 0xc0000000); - - units = nv_rd32(gr, 0x001540); + nvkm_wr32(device, 0x400804, 0xc0000000); + nvkm_wr32(device, 0x406800, 0xc0000000); + nvkm_wr32(device, 0x400c04, 0xc0000000); + nvkm_wr32(device, 0x401800, 0xc0000000); + nvkm_wr32(device, 0x405018, 0xc0000000); + nvkm_wr32(device, 0x402000, 0xc0000000); + + units = nvkm_rd32(device, 0x001540); for (i = 0; i < 16; i++) { if (!(units & (1 << i))) continue; if (nv_device(gr)->chipset < 0xa0) { - nv_wr32(gr, 0x408900 + (i << 12), 0xc0000000); - nv_wr32(gr, 0x408e08 + (i << 12), 0xc0000000); - nv_wr32(gr, 0x408314 + (i << 12), 0xc0000000); + nvkm_wr32(device, 0x408900 + (i << 12), 0xc0000000); + nvkm_wr32(device, 0x408e08 + (i << 12), 0xc0000000); + nvkm_wr32(device, 0x408314 + (i << 12), 0xc0000000); } else { - nv_wr32(gr, 0x408600 + (i << 11), 0xc0000000); - nv_wr32(gr, 0x408708 + (i << 11), 0xc0000000); - nv_wr32(gr, 0x40831c + (i << 11), 0xc0000000); + nvkm_wr32(device, 0x408600 + (i << 11), 0xc0000000); + nvkm_wr32(device, 0x408708 + (i << 11), 0xc0000000); + nvkm_wr32(device, 0x40831c + (i << 11), 0xc0000000); } } - nv_wr32(gr, 0x400108, 0xffffffff); - nv_wr32(gr, 0x400138, 0xffffffff); - nv_wr32(gr, 0x400100, 0xffffffff); - nv_wr32(gr, 0x40013c, 0xffffffff); - nv_wr32(gr, 0x400500, 0x00010001); + nvkm_wr32(device, 0x400108, 0xffffffff); + nvkm_wr32(device, 0x400138, 0xffffffff); + nvkm_wr32(device, 0x400100, 0xffffffff); + nvkm_wr32(device, 0x40013c, 0xffffffff); + nvkm_wr32(device, 0x400500, 0x00010001); /* upload context program, initialise ctxctl defaults */ ret = nv50_grctx_init(nv_device(gr), &gr->size); if (ret) return ret; - nv_wr32(gr, 0x400824, 0x00000000); - nv_wr32(gr, 0x400828, 0x00000000); - nv_wr32(gr, 0x40082c, 0x00000000); - nv_wr32(gr, 0x400830, 0x00000000); - nv_wr32(gr, 0x40032c, 0x00000000); - nv_wr32(gr, 0x400330, 0x00000000); + nvkm_wr32(device, 0x400824, 0x00000000); + nvkm_wr32(device, 0x400828, 0x00000000); + nvkm_wr32(device, 0x40082c, 0x00000000); + nvkm_wr32(device, 0x400830, 0x00000000); + nvkm_wr32(device, 0x40032c, 0x00000000); + nvkm_wr32(device, 0x400330, 0x00000000); /* some unknown zcull magic */ switch (nv_device(gr)->chipset & 0xf0) { case 0x50: case 0x80: case 0x90: - nv_wr32(gr, 0x402ca8, 0x00000800); + nvkm_wr32(device, 0x402ca8, 0x00000800); break; case 0xa0: default: if (nv_device(gr)->chipset == 0xa0 || nv_device(gr)->chipset == 0xaa || nv_device(gr)->chipset == 0xac) { - nv_wr32(gr, 0x402ca8, 0x00000802); + nvkm_wr32(device, 0x402ca8, 0x00000802); } else { - nv_wr32(gr, 0x402cc0, 0x00000000); - nv_wr32(gr, 0x402ca8, 0x00000002); + nvkm_wr32(device, 0x402cc0, 0x00000000); + nvkm_wr32(device, 0x402ca8, 0x00000002); } break; @@ -976,10 +983,10 @@ nv50_gr_init(struct nvkm_object *object) /* zero out zcull regions */ for (i = 0; i < 8; i++) { - nv_wr32(gr, 0x402c20 + (i * 0x10), 0x00000000); - nv_wr32(gr, 0x402c24 + (i * 0x10), 0x00000000); - nv_wr32(gr, 0x402c28 + (i * 0x10), 0x00000000); - nv_wr32(gr, 0x402c2c + (i * 0x10), 0x00000000); + nvkm_wr32(device, 0x402c20 + (i * 0x10), 0x00000000); + nvkm_wr32(device, 0x402c24 + (i * 0x10), 0x00000000); + nvkm_wr32(device, 0x402c28 + (i * 0x10), 0x00000000); + nvkm_wr32(device, 0x402c2c + (i * 0x10), 0x00000000); } return 0; } -- cgit v1.2.3 From c4584adc37720b65ae44a84c660d47b3ebcf7dfb Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:11 +1000 Subject: drm/nouveau/gr: switch to new-style timer macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 23 ++++++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 61 ++++++++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 12 ++++- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 15 ++++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 6 ++- 7 files changed, 87 insertions(+), 40 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 43b393f4cd4d..ccce293191a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1312,7 +1312,10 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8); nvkm_wr32(device, 0x100cbc, 0x80000001); - nv_wait(gr, 0x100c80, 0x00008000, 0x00008000); + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x100c80) & 0x00008000) + break; + ); /* setup default state for mmio list construction */ info.gr = gr; @@ -1326,8 +1329,10 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_wr32(device, 0x409840, 0x00000030); nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); nvkm_wr32(device, 0x409504, 0x00000003); - if (!nv_wait(gr, 0x409800, 0x00000010, 0x00000010)) - nv_error(gr, "load_ctx timeout\n"); + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800) & 0x00000010) + break; + ); nv_wo32(chan, 0x8001c, 1); nv_wo32(chan, 0x80020, 0); @@ -1338,8 +1343,10 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_wr32(device, 0x409840, 0x80000000); nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); nvkm_wr32(device, 0x409504, 0x00000001); - if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) - nv_error(gr, "HUB_SET_CHAN timeout\n"); + nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800) & 0x80000000) + break; + ); } oclass->main(gr, &info); @@ -1349,8 +1356,10 @@ gf100_grctx_generate(struct gf100_gr *gr) */ nvkm_mask(device, 0x409b04, 0x80000000, 0x00000000); nvkm_wr32(device, 0x409000, 0x00000100); - if (!nv_wait(gr, 0x409b00, 0x80000000, 0x00000000)) { - nv_error(gr, "grctx template channel unload timeout\n"); + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x409b00) & 0x80000000)) + break; + ) < 0) { ret = -EBUSY; goto done; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index b692e8e2b982..4bfec3aa0dee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -741,7 +741,10 @@ gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p) */ if ((addr & 0xffff) == 0xe100) gf100_gr_wait_idle(gr); - nv_wait(gr, 0x400700, 0x00000004, 0x00000000); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x400700) & 0x00000004)) + break; + ); addr += init->pitch; } } @@ -1312,8 +1315,11 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) nvkm_wr32(device, 0x40910c, 0x00000000); nvkm_wr32(device, 0x41a100, 0x00000002); nvkm_wr32(device, 0x409100, 0x00000002); - if (!nv_wait(gr, 0x409800, 0x00000001, 0x00000001)) - nv_warn(gr, "0x409800 wait failed\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800) & 0x00000001) + break; + ) < 0) + return -EBUSY; nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x409500, 0x7fffffff); @@ -1322,54 +1328,59 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x409500, 0x00000000); nvkm_wr32(device, 0x409504, 0x00000010); - if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(gr, "fuc09 req 0x10 timeout\n"); + if (nvkm_msec(device, 2000, + if ((gr->size = nvkm_rd32(device, 0x409800))) + break; + ) < 0) return -EBUSY; - } - gr->size = nvkm_rd32(device, 0x409800); nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x409500, 0x00000000); nvkm_wr32(device, 0x409504, 0x00000016); - if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(gr, "fuc09 req 0x16 timeout\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) return -EBUSY; - } nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x409500, 0x00000000); nvkm_wr32(device, 0x409504, 0x00000025); - if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(gr, "fuc09 req 0x25 timeout\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) return -EBUSY; - } if (nv_device(gr)->chipset >= 0xe0) { nvkm_wr32(device, 0x409800, 0x00000000); nvkm_wr32(device, 0x409500, 0x00000001); nvkm_wr32(device, 0x409504, 0x00000030); - if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(gr, "fuc09 req 0x30 timeout\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) return -EBUSY; - } nvkm_wr32(device, 0x409810, 0xb00095c8); nvkm_wr32(device, 0x409800, 0x00000000); nvkm_wr32(device, 0x409500, 0x00000001); nvkm_wr32(device, 0x409504, 0x00000031); - if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(gr, "fuc09 req 0x31 timeout\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) return -EBUSY; - } nvkm_wr32(device, 0x409810, 0x00080420); nvkm_wr32(device, 0x409800, 0x00000000); nvkm_wr32(device, 0x409500, 0x00000001); nvkm_wr32(device, 0x409504, 0x00000032); - if (!nv_wait_ne(gr, 0x409800, 0xffffffff, 0x00000000)) { - nv_error(gr, "fuc09 req 0x32 timeout\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800)) + break; + ) < 0) return -EBUSY; - } nvkm_wr32(device, 0x409614, 0x00000070); nvkm_wr32(device, 0x409614, 0x00000770); @@ -1425,8 +1436,10 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) /* start HUB ucode running, it'll init the GPCs */ nvkm_wr32(device, 0x40910c, 0x00000000); nvkm_wr32(device, 0x409100, 0x00000002); - if (!nv_wait(gr, 0x409800, 0x80000000, 0x80000000)) { - nv_error(gr, "HUB_INIT timed out\n"); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x409800) & 0x80000000) + break; + ) < 0) { gf100_gr_ctxctl_debug(gr); return -EBUSY; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 12b34c7a1477..ed944aa6b81b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -220,12 +220,20 @@ gk20a_gr_dtor(struct nvkm_object *object) static int gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) { - if (!nv_wait(gr, 0x40910c, 0x6, 0x0)) { + struct nvkm_device *device = gr->base.engine.subdev.device; + + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x40910c) & 0x00000006)) + break; + ) < 0) { nv_error(gr, "FECS mem scrubbing timeout\n"); return -ETIMEDOUT; } - if (!nv_wait(gr, 0x41a10c, 0x6, 0x0)) { + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006)) + break; + ) < 0) { nv_error(gr, "GPCCS mem scrubbing timeout\n"); return -ETIMEDOUT; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index d1792ef62712..33f3b8219213 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1206,7 +1206,10 @@ nv04_gr_idle(void *obj) if (nv_device(obj)->card_type == NV_40) mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; - if (!nv_wait(gr, NV04_PGRAPH_STATUS, mask, 0)) { + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask)) + break; + ) < 0) { nv_error(gr, "idle timed out with status 0x%08x\n", nvkm_rd32(device, NV04_PGRAPH_STATUS)); return false; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 8e264f79c0df..21aff9b5ed40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -127,7 +127,10 @@ nv20_gr_context_fini(struct nvkm_object *object, bool suspend) if (chan->chid == chid) { nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4); nvkm_wr32(device, 0x400788, 0x00000002); - nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); + nvkm_msec(device, 2000, + if (!nvkm_rd32(device, 0x400700)) + break; + ); nvkm_wr32(device, 0x400144, 0x10000000); nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000); } @@ -289,12 +292,18 @@ nv20_gr_init(struct nvkm_object *object) nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000); for (i = 0; i < 15; i++) nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); - nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); + nvkm_msec(device, 2000, + if (!nvkm_rd32(device, 0x400700)) + break; + ); } else { nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000); for (i = 0; i < 32; i++) nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); - nv_wait(gr, 0x400700, 0xffffffff, 0x00000000); + nvkm_msec(device, 2000, + if (!nvkm_rd32(device, 0x400700)) + break; + ); } nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index edcaa65b1e09..7455049ff178 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -167,7 +167,10 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend) nvkm_wr32(device, 0x400784, inst); nvkm_mask(device, 0x400310, 0x00000020, 0x00000020); nvkm_mask(device, 0x400304, 0x00000001, 0x00000001); - if (!nv_wait(gr, 0x400300, 0x00000001, 0x00000000)) { + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x400300) & 0x00000001)) + break; + ) < 0) { u32 insn = nvkm_rd32(device, 0x400308); nv_warn(gr, "ctxprog timeout 0x%08x\n", insn); ret = -EBUSY; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index ade34d8a4ea0..3b482bcc22d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -285,8 +285,10 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) nvkm_wr32(device, 0x100c80, 0x00000001); - if (!nv_wait(gr, 0x100c80, 0x00000001, 0x00000000)) - nv_error(gr, "vm flush timeout\n"); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) + break; + ); nvkm_mask(device, 0x400500, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); return timeout ? -EBUSY : 0; -- cgit v1.2.3 From 109c2f2f1c42c16a4b265e796dee6ae4ada78417 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:13 +1000 Subject: drm/nouveau/gr: switch to subdev printk macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/enum.h | 1 - drivers/gpu/drm/nouveau/nvkm/core/enum.c | 16 -- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 233 +++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 7 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 27 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 29 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 20 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 26 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 277 +++++++++++++--------- 10 files changed, 339 insertions(+), 302 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h index 573b1eef4b39..a5d4c65bbbc2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/enum.h @@ -17,6 +17,5 @@ struct nvkm_bitfield { const char *name; }; -void nvkm_bitfield_print(const struct nvkm_bitfield *, u32 value); void nvkm_snprintbf(char *, int, const struct nvkm_bitfield *, u32 value); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/core/enum.c b/drivers/gpu/drm/nouveau/nvkm/core/enum.c index 2cfaec406194..64bdbd04a73a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/enum.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/enum.c @@ -49,22 +49,6 @@ nvkm_enum_print(const struct nvkm_enum *en, u32 value) return en; } -void -nvkm_bitfield_print(const struct nvkm_bitfield *bf, u32 value) -{ - while (bf->name) { - if (value & bf->mask) { - pr_cont(" %s", bf->name); - value &= ~bf->mask; - } - - bf++; - } - - if (value) - pr_cont(" (unknown bits 0x%08x)", value); -} - void nvkm_snprintbf(char *data, int size, const struct nvkm_bitfield *bf, u32 value) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index ccce293191a4..7854baff3374 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1271,7 +1271,8 @@ int gf100_grctx_generate(struct gf100_gr *gr) { struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; struct nvkm_bar *bar = device->bar; struct nvkm_gpuobj *chan; struct gf100_grctx info; @@ -1283,7 +1284,7 @@ gf100_grctx_generate(struct gf100_gr *gr) ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size, 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); if (ret) { - nv_error(gr, "failed to allocate channel memory, %d\n", ret); + nvkm_error(subdev, "failed to allocate chan memory, %d\n", ret); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 4bfec3aa0dee..a27daf986ed7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -673,7 +673,8 @@ gf100_gr_zbc_init(struct gf100_gr *gr) int gf100_gr_wait_idle(struct gf100_gr *gr) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000); bool gr_enabled, ctxsw_active, gr_busy; @@ -692,8 +693,9 @@ gf100_gr_wait_idle(struct gf100_gr *gr) return 0; } while (time_before(jiffies, end_jiffies)); - nv_error(gr, "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", - gr_enabled, ctxsw_active, gr_busy); + nvkm_error(subdev, + "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n", + gr_enabled, ctxsw_active, gr_busy); return -EAGAIN; } @@ -790,55 +792,50 @@ gf100_gr_units(struct nvkm_gr *obj) return cfg; } -static const struct nvkm_enum gk104_sked_error[] = { - { 7, "CONSTANT_BUFFER_SIZE" }, - { 9, "LOCAL_MEMORY_SIZE_POS" }, - { 10, "LOCAL_MEMORY_SIZE_NEG" }, - { 11, "WARP_CSTACK_SIZE" }, - { 12, "TOTAL_TEMP_SIZE" }, - { 13, "REGISTER_COUNT" }, - { 18, "TOTAL_THREADS" }, - { 20, "PROGRAM_OFFSET" }, - { 21, "SHARED_MEMORY_SIZE" }, - { 25, "SHARED_CONFIG_TOO_SMALL" }, - { 26, "TOTAL_REGISTER_COUNT" }, +static const struct nvkm_bitfield gk104_sked_error[] = { + { 0x00000080, "CONSTANT_BUFFER_SIZE" }, + { 0x00000200, "LOCAL_MEMORY_SIZE_POS" }, + { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" }, + { 0x00000800, "WARP_CSTACK_SIZE" }, + { 0x00001000, "TOTAL_TEMP_SIZE" }, + { 0x00002000, "REGISTER_COUNT" }, + { 0x00040000, "TOTAL_THREADS" }, + { 0x00100000, "PROGRAM_OFFSET" }, + { 0x00200000, "SHARED_MEMORY_SIZE" }, + { 0x02000000, "SHARED_CONFIG_TOO_SMALL" }, + { 0x04000000, "TOTAL_REGISTER_COUNT" }, {} }; -static const struct nvkm_enum gf100_gpc_rop_error[] = { - { 1, "RT_PITCH_OVERRUN" }, - { 4, "RT_WIDTH_OVERRUN" }, - { 5, "RT_HEIGHT_OVERRUN" }, - { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, - { 8, "RT_STORAGE_TYPE_MISMATCH" }, - { 10, "RT_LINEAR_MISMATCH" }, +static const struct nvkm_bitfield gf100_gpc_rop_error[] = { + { 0x00000002, "RT_PITCH_OVERRUN" }, + { 0x00000010, "RT_WIDTH_OVERRUN" }, + { 0x00000020, "RT_HEIGHT_OVERRUN" }, + { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" }, + { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" }, + { 0x00000400, "RT_LINEAR_MISMATCH" }, {} }; static void gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + char error[128]; u32 trap[4]; - int i; - trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)); + trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); - nv_error(gr, "GPC%d/PROP trap:", gpc); - for (i = 0; i <= 29; ++i) { - if (!(trap[0] & (1 << i))) - continue; - pr_cont(" "); - nvkm_enum_print(gf100_gpc_rop_error, i); - } - pr_cont("\n"); + nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]); - nv_error(gr, "x = %u, y = %u, format = %x, storage type = %x\n", - trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, - trap[3] & 0xff); + nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, " + "format = %x, storage type = %x\n", + gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, + (trap[2] >> 8) & 0x3f, trap[3] & 0xff); nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); } @@ -864,17 +861,19 @@ static const struct nvkm_bitfield gf100_mp_global_error[] = { static void gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); + const struct nvkm_enum *warp; + char glob[128]; - nv_error(gr, "GPC%i/TPC%i/MP trap:", gpc, tpc); - nvkm_bitfield_print(gf100_mp_global_error, gerr); - if (werr) { - pr_cont(" "); - nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff); - } - pr_cont("\n"); + nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr); + warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff); + + nvkm_error(subdev, "GPC%i/TPC%i/MP trap: " + "global %08x [%s] warp %04x [%s]\n", + gpc, tpc, gerr, glob, werr, warp ? warp->name : ""); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr); @@ -883,12 +882,13 @@ gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) static void gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508)); if (stat & 0x00000001) { u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224)); - nv_error(gr, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); + nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); stat &= ~0x00000001; } @@ -900,27 +900,28 @@ gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc) if (stat & 0x00000004) { u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084)); - nv_error(gr, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); + nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); stat &= ~0x00000004; } if (stat & 0x00000008) { u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c)); - nv_error(gr, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); + nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap); nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); stat &= ~0x00000008; } if (stat) { - nv_error(gr, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); + nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat); } } static void gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90)); int tpc; @@ -931,21 +932,21 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) if (stat & 0x00000002) { u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900)); - nv_error(gr, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); + nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap); nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000); stat &= ~0x00000002; } if (stat & 0x00000004) { u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028)); - nv_error(gr, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); + nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap); nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000); stat &= ~0x00000004; } if (stat & 0x00000008) { u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824)); - nv_error(gr, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); + nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap); nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000); stat &= ~0x00000009; } @@ -960,20 +961,21 @@ gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc) } if (stat) { - nv_error(gr, "GPC%d/0x%08x: unknown\n", gpc, stat); + nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat); } } static void gf100_gr_trap_intr(struct gf100_gr *gr) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 trap = nvkm_rd32(device, 0x400108); - int rop, gpc, i; + int rop, gpc; if (trap & 0x00000001) { u32 stat = nvkm_rd32(device, 0x404000); - nv_error(gr, "DISPATCH 0x%08x\n", stat); + nvkm_error(subdev, "DISPATCH %08x\n", stat); nvkm_wr32(device, 0x404000, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000001); trap &= ~0x00000001; @@ -981,7 +983,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000002) { u32 stat = nvkm_rd32(device, 0x404600); - nv_error(gr, "M2MF 0x%08x\n", stat); + nvkm_error(subdev, "M2MF %08x\n", stat); nvkm_wr32(device, 0x404600, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000002); trap &= ~0x00000002; @@ -989,7 +991,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000008) { u32 stat = nvkm_rd32(device, 0x408030); - nv_error(gr, "CCACHE 0x%08x\n", stat); + nvkm_error(subdev, "CCACHE %08x\n", stat); nvkm_wr32(device, 0x408030, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000008); trap &= ~0x00000008; @@ -997,7 +999,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000010) { u32 stat = nvkm_rd32(device, 0x405840); - nv_error(gr, "SHADER 0x%08x\n", stat); + nvkm_error(subdev, "SHADER %08x\n", stat); nvkm_wr32(device, 0x405840, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000010); trap &= ~0x00000010; @@ -1005,7 +1007,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000040) { u32 stat = nvkm_rd32(device, 0x40601c); - nv_error(gr, "UNK6 0x%08x\n", stat); + nvkm_error(subdev, "UNK6 %08x\n", stat); nvkm_wr32(device, 0x40601c, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000040); trap &= ~0x00000040; @@ -1013,25 +1015,20 @@ gf100_gr_trap_intr(struct gf100_gr *gr) if (trap & 0x00000080) { u32 stat = nvkm_rd32(device, 0x404490); - nv_error(gr, "MACRO 0x%08x\n", stat); + nvkm_error(subdev, "MACRO %08x\n", stat); nvkm_wr32(device, 0x404490, 0xc0000000); nvkm_wr32(device, 0x400108, 0x00000080); trap &= ~0x00000080; } if (trap & 0x00000100) { - u32 stat = nvkm_rd32(device, 0x407020); + u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff; + char sked[128]; - nv_error(gr, "SKED:"); - for (i = 0; i <= 29; ++i) { - if (!(stat & (1 << i))) - continue; - pr_cont(" "); - nvkm_enum_print(gk104_sked_error, i); - } - pr_cont("\n"); + nvkm_snprintbf(sked, sizeof(sked), gk104_sked_error, stat); + nvkm_error(subdev, "SKED: %08x [%s]\n", stat, sked); - if (stat & 0x3fffffff) + if (stat) nvkm_wr32(device, 0x407020, 0x40000000); nvkm_wr32(device, 0x400108, 0x00000100); trap &= ~0x00000100; @@ -1055,7 +1052,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) for (rop = 0; rop < gr->rop_nr; rop++) { u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070)); u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144)); - nv_error(gr, "ROP%d 0x%08x 0x%08x\n", + nvkm_error(subdev, "ROP%d %08x %08x\n", rop, statz, statc); nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000); nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000); @@ -1065,7 +1062,7 @@ gf100_gr_trap_intr(struct gf100_gr *gr) } if (trap) { - nv_error(gr, "TRAP UNHANDLED 0x%08x\n", trap); + nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap); nvkm_wr32(device, 0x400108, trap); } } @@ -1073,15 +1070,20 @@ gf100_gr_trap_intr(struct gf100_gr *gr) static void gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base) { - struct nvkm_device *device = gr->base.engine.subdev.device; - nv_error(gr, "%06x - done 0x%08x\n", base, - nvkm_rd32(device, base + 0x400)); - nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nvkm_rd32(device, base + 0x800), nvkm_rd32(device, base + 0x804), - nvkm_rd32(device, base + 0x808), nvkm_rd32(device, base + 0x80c)); - nv_error(gr, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, - nvkm_rd32(device, base + 0x810), nvkm_rd32(device, base + 0x814), - nvkm_rd32(device, base + 0x818), nvkm_rd32(device, base + 0x81c)); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + nvkm_error(subdev, "%06x - done %08x\n", base, + nvkm_rd32(device, base + 0x400)); + nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, + nvkm_rd32(device, base + 0x800), + nvkm_rd32(device, base + 0x804), + nvkm_rd32(device, base + 0x808), + nvkm_rd32(device, base + 0x80c)); + nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base, + nvkm_rd32(device, base + 0x810), + nvkm_rd32(device, base + 0x814), + nvkm_rd32(device, base + 0x818), + nvkm_rd32(device, base + 0x81c)); } void @@ -1099,7 +1101,8 @@ gf100_gr_ctxctl_debug(struct gf100_gr *gr) static void gf100_gr_ctxctl_isr(struct gf100_gr *gr) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, 0x409c18); if (stat & 0x00000001) { @@ -1111,26 +1114,26 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr) u32 mthd = (addr & 0x00003ffc); u32 data = nvkm_rd32(device, 0x409810); - nv_error(gr, "FECS MTHD subc %d class 0x%04x " - "mthd 0x%04x data 0x%08x\n", - subc, class, mthd, data); + nvkm_error(subdev, "FECS MTHD subc %d class %04x " + "mthd %04x data %08x\n", + subc, class, mthd, data); nvkm_wr32(device, 0x409c20, 0x00000001); stat &= ~0x00000001; } else { - nv_error(gr, "FECS ucode error %d\n", code); + nvkm_error(subdev, "FECS ucode error %d\n", code); } } if (stat & 0x00080000) { - nv_error(gr, "FECS watchdog timeout\n"); + nvkm_error(subdev, "FECS watchdog timeout\n"); gf100_gr_ctxctl_debug(gr); nvkm_wr32(device, 0x409c20, 0x00080000); stat &= ~0x00080000; } if (stat) { - nv_error(gr, "FECS 0x%08x\n", stat); + nvkm_error(subdev, "FECS %08x\n", stat); gf100_gr_ctxctl_debug(gr); nvkm_wr32(device, 0x409c20, stat); } @@ -1175,10 +1178,10 @@ gf100_gr_intr(struct nvkm_subdev *subdev) if (stat & 0x00000010) { handle = nvkm_handle_get_class(engctx, class); if (!handle || nv_call(handle->object, mthd, data)) { - nv_error(gr, - "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nvkm_client_name(engctx), - subc, class, mthd, data); + nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " + "subc %d class %04x mthd %04x data %08x\n", + chid, inst << 12, nvkm_client_name(engctx), + subc, class, mthd, data); } nvkm_handle_put(handle); nvkm_wr32(device, 0x400100, 0x00000010); @@ -1186,27 +1189,29 @@ gf100_gr_intr(struct nvkm_subdev *subdev) } if (stat & 0x00000020) { - nv_error(gr, - "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nvkm_client_name(engctx), subc, - class, mthd, data); + nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " + "subc %d class %04x mthd %04x data %08x\n", + chid, inst << 12, nvkm_client_name(engctx), subc, + class, mthd, data); nvkm_wr32(device, 0x400100, 0x00000020); stat &= ~0x00000020; } if (stat & 0x00100000) { - nv_error(gr, "DATA_ERROR ["); - nvkm_enum_print(nv50_data_error_names, code); - pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 12, nvkm_client_name(engctx), subc, - class, mthd, data); + const struct nvkm_enum *en = + nvkm_enum_find(nv50_data_error_names, code); + nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " + "subc %d class %04x mthd %04x data %08x\n", + code, en ? en->name : "", chid, inst << 12, + nvkm_client_name(engctx), subc, class, mthd, data); nvkm_wr32(device, 0x400100, 0x00100000); stat &= ~0x00100000; } if (stat & 0x00200000) { - nv_error(gr, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, - nvkm_client_name(engctx)); + nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", + chid, inst << 12, + nvkm_client_name(engctx)); gf100_gr_trap_intr(gr); nvkm_wr32(device, 0x400100, 0x00200000); stat &= ~0x00200000; @@ -1219,7 +1224,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) } if (stat) { - nv_error(gr, "unknown stat 0x%08x\n", stat); + nvkm_error(subdev, "intr %08x\n", stat); nvkm_wr32(device, 0x400100, stat); } @@ -1295,7 +1300,8 @@ gf100_gr_init_csdata(struct gf100_gr *gr, int gf100_gr_init_ctxctl(struct gf100_gr *gr) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; int i; @@ -1390,7 +1396,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) if (gr->data == NULL) { int ret = gf100_grctx_generate(gr); if (ret) { - nv_error(gr, "failed to construct context\n"); + nvkm_error(subdev, "failed to construct context\n"); return ret; } } @@ -1448,7 +1454,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) if (gr->data == NULL) { int ret = gf100_grctx_generate(gr); if (ret) { - nv_error(gr, "failed to construct context\n"); + nvkm_error(subdev, "failed to construct context\n"); return ret; } } @@ -1580,7 +1586,8 @@ int gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, struct gf100_gr_fuc *fuc) { - struct nvkm_device *device = nv_device(gr); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; const struct firmware *fw; char f[64]; char cname[16]; @@ -1599,7 +1606,7 @@ gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); ret = request_firmware(&fw, f, nv_device_base(device)); if (ret) { - nv_error(gr, "failed to load %s\n", fwname); + nvkm_error(subdev, "failed to load %s\n", fwname); return ret; } @@ -1633,7 +1640,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct gf100_gr_oclass *oclass = (void *)bclass; - struct nvkm_device *device = nv_device(parent); + struct nvkm_device *device = (void *)parent; struct gf100_gr *gr; bool use_ext_fw, enable; int ret, i, j; @@ -1653,7 +1660,7 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gr->base.units = gf100_gr_units; if (use_ext_fw) { - nv_info(gr, "using external firmware\n"); + nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index ed944aa6b81b..6cb8ff3fb68a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -220,13 +220,14 @@ gk20a_gr_dtor(struct nvkm_object *object) static int gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; if (nvkm_msec(device, 2000, if (!(nvkm_rd32(device, 0x40910c) & 0x00000006)) break; ) < 0) { - nv_error(gr, "FECS mem scrubbing timeout\n"); + nvkm_error(subdev, "FECS mem scrubbing timeout\n"); return -ETIMEDOUT; } @@ -234,7 +235,7 @@ gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) if (!(nvkm_rd32(device, 0x41a10c) & 0x00000006)) break; ) < 0) { - nv_error(gr, "GPCCS mem scrubbing timeout\n"); + nvkm_error(subdev, "GPCCS mem scrubbing timeout\n"); return -ETIMEDOUT; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 33f3b8219213..a445712973f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1200,7 +1200,8 @@ bool nv04_gr_idle(void *obj) { struct nvkm_gr *gr = nvkm_gr(obj); - struct nvkm_device *device = gr->engine.subdev.device; + struct nvkm_subdev *subdev = &gr->engine.subdev; + struct nvkm_device *device = subdev->device; u32 mask = 0xffffffff; if (nv_device(obj)->card_type == NV_40) @@ -1210,8 +1211,8 @@ nv04_gr_idle(void *obj) if (!(nvkm_rd32(device, NV04_PGRAPH_STATUS) & mask)) break; ) < 0) { - nv_error(gr, "idle timed out with status 0x%08x\n", - nvkm_rd32(device, NV04_PGRAPH_STATUS)); + nvkm_error(subdev, "idle timed out with status %08x\n", + nvkm_rd32(device, NV04_PGRAPH_STATUS)); return false; } @@ -1276,6 +1277,7 @@ nv04_gr_intr(struct nvkm_subdev *subdev) u32 class = nvkm_rd32(device, 0x400180 + subc * 4) & 0xff; u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4; u32 show = stat; + char msg[128], src[128], sta[128]; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); @@ -1303,17 +1305,14 @@ nv04_gr_intr(struct nvkm_subdev *subdev) nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(gr, "%s", ""); - nvkm_bitfield_print(nv04_gr_intr_name, show); - pr_cont(" nsource:"); - nvkm_bitfield_print(nv04_gr_nsource, nsource); - pr_cont(" nstatus:"); - nvkm_bitfield_print(nv04_gr_nstatus, nstatus); - pr_cont("\n"); - nv_error(gr, - "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nvkm_client_name(chan), subc, class, mthd, - data); + nvkm_snprintbf(msg, sizeof(msg), nv04_gr_intr_name, show); + nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource); + nvkm_snprintbf(sta, sizeof(sta), nv04_gr_nstatus, nstatus); + nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " + "nstatus %08x [%s] ch %d [%s] subc %d " + "class %04x mthd %04x data %08x\n", + show, msg, nsource, src, nstatus, sta, chid, + nvkm_client_name(chan), subc, class, mthd, data); } nvkm_namedb_put(handle); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 6b3ee956ced4..94f7dc794d2f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -690,6 +690,7 @@ static void nv10_gr_create_pipe(struct nv10_gr_chan *chan) { struct nv10_gr *gr = nv10_gr(chan); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct pipe_state *pipe_state = &chan->pipe_state; u32 *pipe_state_addr; int i; @@ -702,7 +703,7 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan) u32 *__end_addr = pipe_state->pipe_##addr + \ ARRAY_SIZE(pipe_state->pipe_##addr); \ if (pipe_state_addr != __end_addr) \ - nv_error(gr, "incomplete pipe init for 0x%x : %p/%p\n", \ + nvkm_error(subdev, "incomplete pipe init for 0x%x : %p/%p\n", \ addr, pipe_state_addr, __end_addr); \ } while (0) #define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value @@ -844,24 +845,26 @@ nv10_gr_create_pipe(struct nv10_gr_chan *chan) static int nv10_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) { + struct nvkm_subdev *subdev = &gr->base.engine.subdev; int i; for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) { if (nv10_gr_ctx_regs[i] == reg) return i; } - nv_error(gr, "unknow offset nv10_ctx_regs %d\n", reg); + nvkm_error(subdev, "unknow offset nv10_ctx_regs %d\n", reg); return -1; } static int nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) { + struct nvkm_subdev *subdev = &gr->base.engine.subdev; int i; for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) { if (nv17_gr_ctx_regs[i] == reg) return i; } - nv_error(gr, "unknow offset nv17_ctx_regs %d\n", reg); + nvkm_error(subdev, "unknow offset nv17_ctx_regs %d\n", reg); return -1; } @@ -1177,6 +1180,7 @@ nv10_gr_intr(struct nvkm_subdev *subdev) u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; u32 show = stat; + char msg[128], src[128], sta[128]; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); @@ -1204,17 +1208,14 @@ nv10_gr_intr(struct nvkm_subdev *subdev) nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(gr, "%s", ""); - nvkm_bitfield_print(nv10_gr_intr_name, show); - pr_cont(" nsource:"); - nvkm_bitfield_print(nv04_gr_nsource, nsource); - pr_cont(" nstatus:"); - nvkm_bitfield_print(nv10_gr_nstatus, nstatus); - pr_cont("\n"); - nv_error(gr, - "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nvkm_client_name(chan), subc, class, mthd, - data); + nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show); + nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource); + nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus); + nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " + "nstatus %08x [%s] ch %d [%s] subc %d " + "class %04x mthd %04x data %08x\n", + show, msg, nsource, src, nstatus, sta, chid, + nvkm_client_name(chan), subc, class, mthd, data); } nvkm_namedb_put(handle); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 21aff9b5ed40..dab64540e69f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -207,6 +207,7 @@ nv20_gr_intr(struct nvkm_subdev *subdev) u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; u32 show = stat; + char msg[128], src[128], sta[128]; engctx = nvkm_engctx_get(engine, chid); if (stat & NV_PGRAPH_INTR_ERROR) { @@ -222,17 +223,14 @@ nv20_gr_intr(struct nvkm_subdev *subdev) nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(gr, "%s", ""); - nvkm_bitfield_print(nv10_gr_intr_name, show); - pr_cont(" nsource:"); - nvkm_bitfield_print(nv04_gr_nsource, nsource); - pr_cont(" nstatus:"); - nvkm_bitfield_print(nv10_gr_nstatus, nstatus); - pr_cont("\n"); - nv_error(gr, - "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, nvkm_client_name(engctx), subc, class, mthd, - data); + nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show); + nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource); + nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus); + nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " + "nstatus %08x [%s] ch %d [%s] subc %d " + "class %04x mthd %04x data %08x\n", + show, msg, nsource, src, nstatus, sta, chid, + nvkm_client_name(engctx), subc, class, mthd, data); } nvkm_engctx_put(engctx); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 7455049ff178..10ffb676e55e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -155,7 +155,8 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend) { struct nv40_gr *gr = (void *)object->engine; struct nv40_gr_chan *chan = (void *)object; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; int ret = 0; @@ -172,7 +173,7 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend) break; ) < 0) { u32 insn = nvkm_rd32(device, 0x400308); - nv_warn(gr, "ctxprog timeout 0x%08x\n", insn); + nvkm_warn(subdev, "ctxprog timeout %08x\n", insn); ret = -EBUSY; } } @@ -302,6 +303,7 @@ nv40_gr_intr(struct nvkm_subdev *subdev) u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; u32 show = stat; + char msg[128], src[128], sta[128]; int chid; engctx = nvkm_engctx_get(engine, inst); @@ -324,17 +326,15 @@ nv40_gr_intr(struct nvkm_subdev *subdev) nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); if (show) { - nv_error(gr, "%s", ""); - nvkm_bitfield_print(nv10_gr_intr_name, show); - pr_cont(" nsource:"); - nvkm_bitfield_print(nv04_gr_nsource, nsource); - pr_cont(" nstatus:"); - nvkm_bitfield_print(nv10_gr_nstatus, nstatus); - pr_cont("\n"); - nv_error(gr, - "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, inst << 4, nvkm_client_name(engctx), subc, - class, mthd, data); + nvkm_snprintbf(msg, sizeof(msg), nv10_gr_intr_name, show); + nvkm_snprintbf(src, sizeof(src), nv04_gr_nsource, nsource); + nvkm_snprintbf(sta, sizeof(sta), nv10_gr_nstatus, nstatus); + nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " + "nstatus %08x [%s] ch %d [%08x %s] subc %d " + "class %04x mthd %04x data %08x\n", + show, msg, nsource, src, nstatus, sta, chid, + inst << 4, nvkm_client_name(engctx), subc, + class, mthd, data); } nvkm_engctx_put(engctx); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 3b482bcc22d0..4ea7f0938769 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -200,46 +200,71 @@ static const struct nvkm_bitfield nv50_gr_status[] = { {} }; -static const char *const nv50_gr_vstatus_0[] = { - "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP", - NULL +static const struct nvkm_bitfield +nv50_gr_vstatus_0[] = { + { 0x01, "VFETCH" }, + { 0x02, "CCACHE" }, + { 0x04, "PREGEOM" }, + { 0x08, "POSTGEOM" }, + { 0x10, "VATTR" }, + { 0x20, "STRMOUT" }, + { 0x40, "VCLIP" }, + {} }; -static const char *const nv50_gr_vstatus_1[] = { - "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL +static const struct nvkm_bitfield +nv50_gr_vstatus_1[] = { + { 0x01, "TPC_RAST" }, + { 0x02, "TPC_PROP" }, + { 0x04, "TPC_TEX" }, + { 0x08, "TPC_GEOM" }, + { 0x10, "TPC_MP" }, + {} }; -static const char *const nv50_gr_vstatus_2[] = { - "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK", - "ROP", NULL +static const struct nvkm_bitfield +nv50_gr_vstatus_2[] = { + { 0x01, "RATTR" }, + { 0x02, "APLANE" }, + { 0x04, "TRAST" }, + { 0x08, "CLIPID" }, + { 0x10, "ZCULL" }, + { 0x20, "ENG2D" }, + { 0x40, "RMASK" }, + { 0x80, "ROP" }, + {} }; static void nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, - const char *const units[], u32 status) + const struct nvkm_bitfield *units, u32 status) { + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + u32 stat = status; + u8 mask = 0x00; + char msg[64]; int i; - nv_error(gr, "PGRAPH_VSTATUS%d: 0x%08x", r, status); - - for (i = 0; units[i] && status; i++) { + for (i = 0; units[i].name && status; i++) { if ((status & 7) == 1) - pr_cont(" %s", units[i]); + mask |= (1 << i); status >>= 3; } - if (status) - pr_cont(" (invalid: 0x%x)", status); - pr_cont("\n"); + + nvkm_snprintbf(msg, sizeof(msg), units, mask); + nvkm_error(subdev, "PGRAPH_VSTATUS%d: %08x [%s]\n", r, stat, msg); } static int g84_gr_tlb_flush(struct nvkm_engine *engine) { struct nv50_gr *gr = (void *)engine; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; struct nvkm_timer *tmr = device->timer; bool idle, timeout = false; unsigned long flags; + char status[128]; u64 start; u32 tmp; @@ -268,12 +293,11 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) !(timeout = tmr->read(tmr) - start > 2000000000)); if (timeout) { - nv_error(gr, "PGRAPH TLB flush idle timeout fail\n"); + nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n"); tmp = nvkm_rd32(device, 0x400700); - nv_error(gr, "PGRAPH_STATUS : 0x%08x", tmp); - nvkm_bitfield_print(nv50_gr_status, tmp); - pr_cont("\n"); + nvkm_snprintbf(status, sizeof(status), nv50_gr_status, tmp); + nvkm_error(subdev, "PGRAPH_STATUS %08x [%s]\n", tmp, status); nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, nvkm_rd32(device, 0x400380)); @@ -427,10 +451,10 @@ static const struct nvkm_bitfield nv50_gr_trap_prop[] = { }; static void -nv50_gr_prop_trap(struct nv50_gr *gr, - u32 ustatus_addr, u32 ustatus, u32 tp) +nv50_gr_prop_trap(struct nv50_gr *gr, u32 ustatus_addr, u32 ustatus, u32 tp) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04); u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08); u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c); @@ -438,40 +462,44 @@ nv50_gr_prop_trap(struct nv50_gr *gr, u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14); u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18); u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c); + char msg[128]; /* CUDA memory: l[], g[] or stack. */ if (ustatus & 0x00000080) { if (e18 & 0x80000000) { /* g[] read fault? */ - nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", + nvkm_error(subdev, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", tp, e14, e10 | ((e18 >> 24) & 0x1f)); e18 &= ~0x1f000000; } else if (e18 & 0xc) { /* g[] write fault? */ - nv_error(gr, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", + nvkm_error(subdev, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", tp, e14, e10 | ((e18 >> 7) & 0x1f)); e18 &= ~0x00000f80; } else { - nv_error(gr, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", + nvkm_error(subdev, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", tp, e14, e10); } ustatus &= ~0x00000080; } if (ustatus) { - nv_error(gr, "TRAP_PROP - TP %d -", tp); - nvkm_bitfield_print(nv50_gr_trap_prop, ustatus); - pr_cont(" - Address %02x%08x\n", e14, e10); + nvkm_snprintbf(msg, sizeof(msg), nv50_gr_trap_prop, ustatus); + nvkm_error(subdev, "TRAP_PROP - TP %d - %08x [%s] - " + "Address %02x%08x\n", + tp, ustatus, msg, e14, e10); } - nv_error(gr, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", + nvkm_error(subdev, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", tp, e0c, e18, e1c, e20, e24); } static void nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 units = nvkm_rd32(device, 0x1540); u32 addr, mp10, status, pc, oplow, ophigh; + char msg[128]; int i; int mps = 0; for (i = 0; i < 4; i++) { @@ -490,19 +518,20 @@ nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) pc = nvkm_rd32(device, addr + 0x24); oplow = nvkm_rd32(device, addr + 0x70); ophigh = nvkm_rd32(device, addr + 0x74); - nv_error(gr, "TRAP_MP_EXEC - " - "TP %d MP %d:", tpid, i); - nvkm_bitfield_print(nv50_mp_exec_errors, status); - pr_cont(" at %06x warp %d, opcode %08x %08x\n", - pc&0xffffff, pc >> 24, - oplow, ophigh); + nvkm_snprintbf(msg, sizeof(msg), + nv50_mp_exec_errors, status); + nvkm_error(subdev, "TRAP_MP_EXEC - TP %d MP %d: " + "%08x [%s] at %06x warp %d, " + "opcode %08x %08x\n", + tpid, i, status, msg, pc & 0xffffff, + pc >> 24, oplow, ophigh); } nvkm_wr32(device, addr + 0x10, mp10); nvkm_wr32(device, addr + 0x14, 0); mps++; } if (!mps && display) - nv_error(gr, "TRAP_MP_EXEC - TP %d: " + nvkm_error(subdev, "TRAP_MP_EXEC - TP %d: " "No MPs claiming errors?\n", tpid); } @@ -510,10 +539,12 @@ static void nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, u32 ustatus_new, int display, const char *name) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 units = nvkm_rd32(device, 0x1540); int tps = 0; int i, r; + char msg[128]; u32 ustatus_addr, ustatus; for (i = 0; i < 16; i++) { if (!(units & (1 << i))) @@ -529,15 +560,16 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, switch (type) { case 6: /* texture error... unknown for now */ if (display) { - nv_error(gr, "magic set %d:\n", i); + nvkm_error(subdev, "magic set %d:\n", i); for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) - nv_error(gr, "\t0x%08x: 0x%08x\n", r, - nvkm_rd32(device, r)); + nvkm_error(subdev, "\t%08x: %08x\n", r, + nvkm_rd32(device, r)); if (ustatus) { - nv_error(gr, "%s - TP%d:", name, i); - nvkm_bitfield_print(nv50_tex_traps, - ustatus); - pr_cont("\n"); + nvkm_snprintbf(msg, sizeof(msg), + nv50_tex_traps, ustatus); + nvkm_error(subdev, + "%s - TP%d: %08x [%s]\n", + name, i, ustatus, msg); ustatus = 0; } } @@ -548,9 +580,10 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, ustatus &= ~0x04030000; } if (ustatus && display) { - nv_error(gr, "%s - TP%d:", name, i); - nvkm_bitfield_print(nv50_mpc_traps, ustatus); - pr_cont("\n"); + nvkm_snprintbf(msg, sizeof(msg), + nv50_mpc_traps, ustatus); + nvkm_error(subdev, "%s - TP%d: %08x [%s]\n", + name, i, ustatus, msg); ustatus = 0; } break; @@ -563,25 +596,27 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, } if (ustatus) { if (display) - nv_error(gr, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); + nvkm_error(subdev, "%s - TP%d: Unhandled ustatus %08x\n", name, i, ustatus); } nvkm_wr32(device, ustatus_addr, 0xc0000000); } if (!tps && display) - nv_warn(gr, "%s - No TPs claiming errors?\n", name); + nvkm_warn(subdev, "%s - No TPs claiming errors?\n", name); } static int nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, int chid, u64 inst, struct nvkm_object *engctx) { - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 status = nvkm_rd32(device, 0x400108); u32 ustatus; + char msg[128]; if (!status && display) { - nv_error(gr, "TRAP: no units reporting traps?\n"); + nvkm_error(subdev, "TRAP: no units reporting traps?\n"); return 1; } @@ -591,7 +626,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x001) { ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff; if (!ustatus && display) { - nv_error(gr, "TRAP_DISPATCH - no ustatus?\n"); + nvkm_error(subdev, "TRAP_DISPATCH - no ustatus?\n"); } nvkm_wr32(device, 0x400500, 0x00000000); @@ -606,16 +641,19 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, u32 class = nvkm_rd32(device, 0x400814); u32 r848 = nvkm_rd32(device, 0x400848); - nv_error(gr, "TRAP DISPATCH_FAULT\n"); + nvkm_error(subdev, "TRAP DISPATCH_FAULT\n"); if (display && (addr & 0x80000000)) { - nv_error(gr, - "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", - chid, inst, - nvkm_client_name(engctx), subc, - class, mthd, datah, datal, addr, r848); + nvkm_error(subdev, + "ch %d [%010llx %s] subc %d " + "class %04x mthd %04x data %08x%08x " + "400808 %08x 400848 %08x\n", + chid, inst, + nvkm_client_name(engctx), + subc, class, mthd, + datah, datal, addr, r848); } else if (display) { - nv_error(gr, "no stuck command?\n"); + nvkm_error(subdev, "no stuck command?\n"); } nvkm_wr32(device, 0x400808, 0); @@ -631,16 +669,17 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, u32 data = nvkm_rd32(device, 0x40085c); u32 class = nvkm_rd32(device, 0x400814); - nv_error(gr, "TRAP DISPATCH_QUERY\n"); + nvkm_error(subdev, "TRAP DISPATCH_QUERY\n"); if (display && (addr & 0x80000000)) { - nv_error(gr, - "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", - chid, inst, - nvkm_client_name(engctx), subc, - class, mthd, data, addr); + nvkm_error(subdev, + "ch %d [%010llx %s] subc %d " + "class %04x mthd %04x data %08x " + "40084c %08x\n", chid, inst, + nvkm_client_name(engctx), subc, + class, mthd, data, addr); } else if (display) { - nv_error(gr, "no stuck command?\n"); + nvkm_error(subdev, "no stuck command?\n"); } nvkm_wr32(device, 0x40084c, 0); @@ -648,8 +687,8 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, } if (ustatus && display) { - nv_error(gr, "TRAP_DISPATCH (unknown " - "0x%08x)\n", ustatus); + nvkm_error(subdev, "TRAP_DISPATCH " + "(unknown %08x)\n", ustatus); } nvkm_wr32(device, 0x400804, 0xc0000000); @@ -663,13 +702,15 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x002) { u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff; if (display) { - nv_error(gr, "TRAP_M2MF"); - nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus); - pr_cont("\n"); - nv_error(gr, "TRAP_M2MF %08x %08x %08x %08x\n", - nvkm_rd32(device, 0x406804), nvkm_rd32(device, 0x406808), - nvkm_rd32(device, 0x40680c), nvkm_rd32(device, 0x406810)); - + nvkm_snprintbf(msg, sizeof(msg), + nv50_gr_trap_m2mf, ustatus); + nvkm_error(subdev, "TRAP_M2MF %08x [%s]\n", + ustatus, msg); + nvkm_error(subdev, "TRAP_M2MF %08x %08x %08x %08x\n", + nvkm_rd32(device, 0x406804), + nvkm_rd32(device, 0x406808), + nvkm_rd32(device, 0x40680c), + nvkm_rd32(device, 0x406810)); } /* No sane way found yet -- just reset the bugger. */ @@ -684,12 +725,15 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x004) { u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff; if (display) { - nv_error(gr, "TRAP_VFETCH"); - nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus); - pr_cont("\n"); - nv_error(gr, "TRAP_VFETCH %08x %08x %08x %08x\n", - nvkm_rd32(device, 0x400c00), nvkm_rd32(device, 0x400c08), - nvkm_rd32(device, 0x400c0c), nvkm_rd32(device, 0x400c10)); + nvkm_snprintbf(msg, sizeof(msg), + nv50_gr_trap_vfetch, ustatus); + nvkm_error(subdev, "TRAP_VFETCH %08x [%s]\n", + ustatus, msg); + nvkm_error(subdev, "TRAP_VFETCH %08x %08x %08x %08x\n", + nvkm_rd32(device, 0x400c00), + nvkm_rd32(device, 0x400c08), + nvkm_rd32(device, 0x400c0c), + nvkm_rd32(device, 0x400c10)); } nvkm_wr32(device, 0x400c04, 0xc0000000); @@ -701,13 +745,15 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x008) { ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff; if (display) { - nv_error(gr, "TRAP_STRMOUT"); - nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus); - pr_cont("\n"); - nv_error(gr, "TRAP_STRMOUT %08x %08x %08x %08x\n", - nvkm_rd32(device, 0x401804), nvkm_rd32(device, 0x401808), - nvkm_rd32(device, 0x40180c), nvkm_rd32(device, 0x401810)); - + nvkm_snprintbf(msg, sizeof(msg), + nv50_gr_trap_strmout, ustatus); + nvkm_error(subdev, "TRAP_STRMOUT %08x [%s]\n", + ustatus, msg); + nvkm_error(subdev, "TRAP_STRMOUT %08x %08x %08x %08x\n", + nvkm_rd32(device, 0x401804), + nvkm_rd32(device, 0x401808), + nvkm_rd32(device, 0x40180c), + nvkm_rd32(device, 0x401810)); } /* No sane way found yet -- just reset the bugger. */ @@ -722,16 +768,19 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x010) { ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff; if (display) { - nv_error(gr, "TRAP_CCACHE"); - nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus); - pr_cont("\n"); - nv_error(gr, "TRAP_CCACHE %08x %08x %08x %08x" - " %08x %08x %08x\n", - nvkm_rd32(device, 0x405000), nvkm_rd32(device, 0x405004), - nvkm_rd32(device, 0x405008), nvkm_rd32(device, 0x40500c), - nvkm_rd32(device, 0x405010), nvkm_rd32(device, 0x405014), - nvkm_rd32(device, 0x40501c)); - + nvkm_snprintbf(msg, sizeof(msg), + nv50_gr_trap_ccache, ustatus); + nvkm_error(subdev, "TRAP_CCACHE %08x [%s]\n", + ustatus, msg); + nvkm_error(subdev, "TRAP_CCACHE %08x %08x %08x %08x " + "%08x %08x %08x\n", + nvkm_rd32(device, 0x405000), + nvkm_rd32(device, 0x405004), + nvkm_rd32(device, 0x405008), + nvkm_rd32(device, 0x40500c), + nvkm_rd32(device, 0x405010), + nvkm_rd32(device, 0x405014), + nvkm_rd32(device, 0x40501c)); } nvkm_wr32(device, 0x405018, 0xc0000000); @@ -745,7 +794,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status & 0x20) { ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff; if (display) - nv_error(gr, "TRAP_UNKC04 0x%08x\n", ustatus); + nvkm_error(subdev, "TRAP_UNKC04 %08x\n", ustatus); nvkm_wr32(device, 0x402000, 0xc0000000); /* no status modifiction on purpose */ } @@ -777,7 +826,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, if (status) { if (display) - nv_error(gr, "TRAP: unknown 0x%08x\n", status); + nvkm_error(subdev, "TRAP: unknown %08x\n", status); nvkm_wr32(device, 0x400108, status); } @@ -801,6 +850,8 @@ nv50_gr_intr(struct nvkm_subdev *subdev) u32 data = nvkm_rd32(device, 0x400708); u32 class = nvkm_rd32(device, 0x400814); u32 show = stat, show_bitfield = stat; + const struct nvkm_enum *en; + char msg[128]; int chid; engctx = nvkm_engctx_get(engine, inst); @@ -815,9 +866,9 @@ nv50_gr_intr(struct nvkm_subdev *subdev) if (show & 0x00100000) { u32 ecode = nvkm_rd32(device, 0x400110); - nv_error(gr, "DATA_ERROR "); - nvkm_enum_print(nv50_data_error_names, ecode); - pr_cont("\n"); + en = nvkm_enum_find(nv50_data_error_names, ecode); + nvkm_error(subdev, "DATA_ERROR %08x [%s]\n", + ecode, en ? en->name : ""); show_bitfield &= ~0x00100000; } @@ -833,15 +884,11 @@ nv50_gr_intr(struct nvkm_subdev *subdev) if (show) { show &= show_bitfield; - if (show) { - nv_error(gr, "%s", ""); - nvkm_bitfield_print(nv50_gr_intr_name, show); - pr_cont("\n"); - } - nv_error(gr, - "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", - chid, (u64)inst << 12, nvkm_client_name(engctx), - subc, class, mthd, data); + nvkm_snprintbf(msg, sizeof(msg), nv50_gr_intr_name, show); + nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] subc %d " + "class %04x mthd %04x data %08x\n", + stat, msg, chid, (u64)inst << 12, + nvkm_client_name(engctx), subc, class, mthd, data); } if (nvkm_rd32(device, 0x400824) & (1 << 31)) -- cgit v1.2.3 From a47474261e77b148480daff855e516dc60e80b48 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:13 +1000 Subject: drm/nouveau/imem: remove object accessor functions Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/instmem.h | 7 +++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c | 24 +++++++++++++--------- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c | 18 ++++++++++------ 6 files changed, 40 insertions(+), 23 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h index d8941b7bebfc..b6906f436e40 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -26,6 +26,13 @@ struct nvkm_instmem { u32 reserved; int (*alloc)(struct nvkm_instmem *, struct nvkm_object *, u32 size, u32 align, struct nvkm_object **); + + const struct nvkm_instmem_func *func; +}; + +struct nvkm_instmem_func { + u32 (*rd32)(struct nvkm_instmem *, u32 addr); + void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data); }; static inline struct nvkm_instmem * diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index a445712973f6..7295a915949e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -573,7 +573,7 @@ nv04_gr_mthd_bind_class(struct nvkm_object *object, u32 *args, u32 size) { struct nvkm_instmem *imem = nvkm_instmem(object); u32 inst = *(u32 *)args << 4; - return nv_ro32(imem, inst); + return imem->func->rd32(imem, inst); } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 4ece5c065412..d4d1abba02f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -63,9 +63,9 @@ nv31_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) struct nvkm_device *device = mpeg->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; u32 inst = *(u32 *)arg << 4; - u32 dma0 = nv_ro32(imem, inst + 0); - u32 dma1 = nv_ro32(imem, inst + 4); - u32 dma2 = nv_ro32(imem, inst + 8); + u32 dma0 = imem->func->rd32(imem, inst + 0); + u32 dma1 = imem->func->rd32(imem, inst + 4); + u32 dma2 = imem->func->rd32(imem, inst + 8); u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); u32 size = dma1 + 1; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index 47ae1d890a7f..7c009c3aa7f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -36,9 +36,9 @@ nv40_mpeg_mthd_dma(struct nvkm_object *object, u32 mthd, void *arg, u32 len) struct nvkm_device *device = mpeg->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; u32 inst = *(u32 *)arg << 4; - u32 dma0 = nv_ro32(imem, inst + 0); - u32 dma1 = nv_ro32(imem, inst + 4); - u32 dma2 = nv_ro32(imem, inst + 8); + u32 dma0 = imem->func->rd32(imem, inst + 0); + u32 dma1 = imem->func->rd32(imem, inst + 4); + u32 dma2 = imem->func->rd32(imem, inst + 8); u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); u32 size = dma1 + 1; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c index 6410cc1fd419..8ba95f366e2f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c @@ -32,17 +32,17 @@ static u32 nv04_instobj_rd32(struct nvkm_object *object, u64 addr) { - struct nv04_instmem *imem = (void *)nvkm_instmem(object); + struct nvkm_instmem *imem = nvkm_instmem(object); struct nv04_instobj *node = (void *)object; - return nv_ro32(imem, node->mem->offset + addr); + return imem->func->rd32(imem, node->mem->offset + addr); } static void nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nv04_instmem *imem = (void *)nvkm_instmem(object); + struct nvkm_instmem *imem = nvkm_instmem(object); struct nv04_instobj *node = (void *)object; - nv_wo32(imem, node->mem->offset + addr, data); + imem->func->wr32(imem, node->mem->offset + addr, data); } static void @@ -103,16 +103,14 @@ nv04_instobj_oclass = { *****************************************************************************/ static u32 -nv04_instmem_rd32(struct nvkm_object *object, u64 addr) +nv04_instmem_rd32(struct nvkm_instmem *imem, u32 addr) { - struct nvkm_instmem *imem = (void *)object; return nvkm_rd32(imem->subdev.device, 0x700000 + addr); } static void -nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data) +nv04_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data) { - struct nvkm_instmem *imem = (void *)object; nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); } @@ -130,6 +128,12 @@ nv04_instmem_dtor(struct nvkm_object *object) nvkm_instmem_destroy(&imem->base); } +static const struct nvkm_instmem_func +nv04_instmem_func = { + .rd32 = nv04_instmem_rd32, + .wr32 = nv04_instmem_wr32, +}; + static int nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -143,6 +147,8 @@ nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + imem->base.func = &nv04_instmem_func; + /* PRAMIN aperture maps over the end of VRAM, reserve it */ imem->base.reserved = 512 * 1024; @@ -184,8 +190,6 @@ nv04_instmem_oclass = &(struct nvkm_instmem_impl) { .dtor = nv04_instmem_dtor, .init = _nvkm_instmem_init, .fini = _nvkm_instmem_fini, - .rd32 = nv04_instmem_rd32, - .wr32 = nv04_instmem_wr32, }, .instobj = &nv04_instobj_oclass.base, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index c194a28b7971..c645e0261530 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -31,19 +31,25 @@ *****************************************************************************/ static u32 -nv40_instmem_rd32(struct nvkm_object *object, u64 addr) +nv40_instmem_rd32(struct nvkm_instmem *obj, u32 addr) { - struct nv04_instmem *imem = (void *)object; + struct nv04_instmem *imem = container_of(obj, typeof(*imem), base); return ioread32_native(imem->iomem + addr); } static void -nv40_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data) +nv40_instmem_wr32(struct nvkm_instmem *obj, u32 addr, u32 data) { - struct nv04_instmem *imem = (void *)object; + struct nv04_instmem *imem = container_of(obj, typeof(*imem), base); iowrite32_native(data, imem->iomem + addr); } +static const struct nvkm_instmem_func +nv40_instmem_func = { + .rd32 = nv40_instmem_rd32, + .wr32 = nv40_instmem_wr32, +}; + static int nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -58,6 +64,8 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + imem->base.func = &nv40_instmem_func; + /* map bar */ if (nv_device_resource_len(device, 2)) bar = 2; @@ -129,8 +137,6 @@ nv40_instmem_oclass = &(struct nvkm_instmem_impl) { .dtor = nv04_instmem_dtor, .init = _nvkm_instmem_init, .fini = _nvkm_instmem_fini, - .rd32 = nv40_instmem_rd32, - .wr32 = nv40_instmem_wr32, }, .instobj = &nv04_instobj_oclass.base, }.base; -- cgit v1.2.3 From 142ea05f49b9517929f8b27ee800160e7ebf3a02 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:14 +1000 Subject: drm/nouveau/gr: switch to gpuobj accessor macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 37 +++++---- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 10 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h | 11 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 16 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 47 +++++++----- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 45 ++++++----- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 84 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 92 ++++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 74 +++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 88 +++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 86 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 86 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 16 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 10 ++- 14 files changed, 385 insertions(+), 317 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 7854baff3374..f36e0896ae9c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1289,27 +1289,28 @@ gf100_grctx_generate(struct gf100_gr *gr) } /* PGD pointer */ - nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); - nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); - nv_wo32(chan, 0x0208, 0xffffffff); - nv_wo32(chan, 0x020c, 0x000000ff); + nvkm_kmap(chan); + nvkm_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); + nvkm_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); + nvkm_wo32(chan, 0x0208, 0xffffffff); + nvkm_wo32(chan, 0x020c, 0x000000ff); /* PGT[0] pointer */ - nv_wo32(chan, 0x1000, 0x00000000); - nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); + nvkm_wo32(chan, 0x1000, 0x00000000); + nvkm_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); /* identity-map the whole "channel" into its own vm */ for (i = 0; i < chan->size / 4096; i++) { u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; - nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); - nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); + nvkm_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); + nvkm_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); } /* context pointer (virt) */ - nv_wo32(chan, 0x0210, 0x00080004); - nv_wo32(chan, 0x0214, 0x00000000); - + nvkm_wo32(chan, 0x0210, 0x00080004); + nvkm_wo32(chan, 0x0214, 0x00000000); bar->flush(bar); + nvkm_done(chan); nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8); nvkm_wr32(device, 0x100cbc, 0x80000001); @@ -1335,11 +1336,13 @@ gf100_grctx_generate(struct gf100_gr *gr) break; ); - nv_wo32(chan, 0x8001c, 1); - nv_wo32(chan, 0x80020, 0); - nv_wo32(chan, 0x80028, 0); - nv_wo32(chan, 0x8002c, 0); + nvkm_kmap(chan); + nvkm_wo32(chan, 0x8001c, 1); + nvkm_wo32(chan, 0x80020, 0); + nvkm_wo32(chan, 0x80028, 0); + nvkm_wo32(chan, 0x8002c, 0); bar->flush(bar); + nvkm_done(chan); } else { nvkm_wr32(device, 0x409840, 0x80000000); nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); @@ -1367,8 +1370,10 @@ gf100_grctx_generate(struct gf100_gr *gr) gr->data = kmalloc(gr->size, GFP_KERNEL); if (gr->data) { + nvkm_kmap(chan); for (i = 0; i < gr->size; i += 4) - gr->data[i / 4] = nv_ro32(chan, 0x80000 + i); + gr->data[i / 4] = nvkm_ro32(chan, 0x80000 + i); + nvkm_done(chan); ret = 0; } else { ret = -ENOMEM; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c index 0c717084b44f..8ecdc94e3538 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c @@ -580,16 +580,18 @@ nv40_gr_construct_shader(struct nvkm_grctx *ctx) if (ctx->mode != NVKM_GRCTX_VALS) return; + nvkm_kmap(obj); offset += 0x0280/4; for (i = 0; i < 16; i++, offset += 2) - nv_wo32(obj, offset * 4, 0x3f800000); + nvkm_wo32(obj, offset * 4, 0x3f800000); for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { for (i = 0; i < vs_nr_b0 * 6; i += 6) - nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); + nvkm_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); for (i = 0; i < vs_nr_b1 * 4; i += 4) - nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); + nvkm_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); } + nvkm_done(obj); } static void @@ -674,7 +676,7 @@ nv40_grctx_init(struct nvkm_device *device, u32 *size) struct nvkm_grctx ctx = { .device = device, .mode = NVKM_GRCTX_PROG, - .data = ctxprog, + .ucode = ctxprog, .ctxprog_max = 256, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h index 8a89961956af..6170b21b50cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h @@ -9,7 +9,8 @@ struct nvkm_grctx { NVKM_GRCTX_PROG, NVKM_GRCTX_VALS } mode; - void *data; + u32 *ucode; + struct nvkm_gpuobj *data; u32 ctxprog_max; u32 ctxprog_len; @@ -22,7 +23,7 @@ struct nvkm_grctx { static inline void cp_out(struct nvkm_grctx *ctx, u32 inst) { - u32 *ctxprog = ctx->data; + u32 *ctxprog = ctx->ucode; if (ctx->mode != NVKM_GRCTX_PROG) return; @@ -56,7 +57,7 @@ cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length) static inline void cp_name(struct nvkm_grctx *ctx, int name) { - u32 *ctxprog = ctx->data; + u32 *ctxprog = ctx->ucode; int i; if (ctx->mode != NVKM_GRCTX_PROG) @@ -124,6 +125,8 @@ gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) reg = (reg - 0x00400000) / 4; reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; - nv_wo32(ctx->data, reg * 4, val); + nvkm_kmap(ctx->data); + nvkm_wo32(ctx->data, reg * 4, val); + nvkm_done(ctx->data); } #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index e76bf4a217dc..69561ee4e115 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -268,7 +268,7 @@ nv50_grctx_init(struct nvkm_device *device, u32 *size) struct nvkm_grctx ctx = { .device = device, .mode = NVKM_GRCTX_PROG, - .data = ctxprog, + .ucode = ctxprog, .ctxprog_max = 512, }; @@ -783,9 +783,12 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx) static void dd_emit(struct nvkm_grctx *ctx, int num, u32 val) { int i; - if (val && ctx->mode == NVKM_GRCTX_VALS) + if (val && ctx->mode == NVKM_GRCTX_VALS) { + nvkm_kmap(ctx->data); for (i = 0; i < num; i++) - nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); + nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); + nvkm_done(ctx->data); + } ctx->ctxvals_pos += num; } @@ -1155,9 +1158,12 @@ nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx) static void xf_emit(struct nvkm_grctx *ctx, int num, u32 val) { int i; - if (val && ctx->mode == NVKM_GRCTX_VALS) + if (val && ctx->mode == NVKM_GRCTX_VALS) { + nvkm_kmap(ctx->data); for (i = 0; i < num; i++) - nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); + nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); + nvkm_done(ctx->data); + } ctx->ctxvals_pos += num << 3; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index a27daf986ed7..a7141e08930c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -283,6 +283,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct gf100_gr_data *data = gr->mmio_data; struct gf100_gr_mmio *mmio = gr->mmio_list; struct gf100_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; /* allocate memory for context, and fill with default values */ @@ -324,6 +325,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } /* finally, fill in the mmio list and point the context at it */ + nvkm_kmap(chan->mmio); for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) { u32 addr = mmio->addr; u32 data = mmio->data; @@ -333,28 +335,32 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, data |= info >> mmio->shift; } - nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); - nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); + nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); + nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data); mmio++; } + nvkm_done(chan->mmio); + image = &chan->base.base.gpuobj; + nvkm_kmap(image); for (i = 0; i < gr->size; i += 4) - nv_wo32(chan, i, gr->data[i / 4]); + nvkm_wo32(image, i, gr->data[i / 4]); if (!gr->firmware) { - nv_wo32(chan, 0x00, chan->mmio_nr / 2); - nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); + nvkm_wo32(image, 0x00, chan->mmio_nr / 2); + nvkm_wo32(image, 0x04, chan->mmio_vma.offset >> 8); } else { - nv_wo32(chan, 0xf4, 0); - nv_wo32(chan, 0xf8, 0); - nv_wo32(chan, 0x10, chan->mmio_nr / 2); - nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); - nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); - nv_wo32(chan, 0x1c, 1); - nv_wo32(chan, 0x20, 0); - nv_wo32(chan, 0x28, 0); - nv_wo32(chan, 0x2c, 0); + nvkm_wo32(image, 0xf4, 0); + nvkm_wo32(image, 0xf8, 0); + nvkm_wo32(image, 0x10, chan->mmio_nr / 2); + nvkm_wo32(image, 0x14, lower_32_bits(chan->mmio_vma.offset)); + nvkm_wo32(image, 0x18, upper_32_bits(chan->mmio_vma.offset)); + nvkm_wo32(image, 0x1c, 1); + nvkm_wo32(image, 0x20, 0); + nvkm_wo32(image, 0x28, 0); + nvkm_wo32(image, 0x2c, 0); } + nvkm_done(image); return 0; } @@ -1679,10 +1685,15 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - for (i = 0; i < 0x1000; i += 4) { - nv_wo32(gr->unk4188b4, i, 0x00000010); - nv_wo32(gr->unk4188b8, i, 0x00000010); - } + nvkm_kmap(gr->unk4188b4); + for (i = 0; i < 0x1000; i += 4) + nvkm_wo32(gr->unk4188b4, i, 0x00000010); + nvkm_done(gr->unk4188b4); + + nvkm_kmap(gr->unk4188b8); + for (i = 0; i < 0x1000; i += 4) + nvkm_wo32(gr->unk4188b8, i, 0x00000010); + nvkm_done(gr->unk4188b8); gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 7295a915949e..323f020166da 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -443,36 +443,42 @@ nv04_gr(struct nv04_gr_chan *chan) */ static void -nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value) +nv04_gr_set_ctx1(struct nvkm_object *obj, u32 mask, u32 value) { - struct nv04_gr *gr = (void *)object->engine; + struct nvkm_gpuobj *object = container_of(obj, typeof(*object), object); + struct nv04_gr *gr = (void *)object->object.engine; struct nvkm_device *device = gr->base.engine.subdev.device; int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; u32 tmp; - tmp = nv_ro32(object, 0x00); + nvkm_kmap(object); + tmp = nvkm_ro32(object, 0x00); tmp &= ~mask; tmp |= value; - nv_wo32(object, 0x00, tmp); + nvkm_wo32(object, 0x00, tmp); + nvkm_done(object); nvkm_wr32(device, NV04_PGRAPH_CTX_SWITCH1, tmp); nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); } static void -nv04_gr_set_ctx_val(struct nvkm_object *object, u32 mask, u32 value) +nv04_gr_set_ctx_val(struct nvkm_object *obj, u32 mask, u32 value) { + struct nvkm_gpuobj *object = container_of(obj, typeof(*object), object); int class, op, valid = 1; u32 tmp, ctx1; - ctx1 = nv_ro32(object, 0x00); + nvkm_kmap(object); + ctx1 = nvkm_ro32(object, 0x00); class = ctx1 & 0xff; op = (ctx1 >> 15) & 7; - tmp = nv_ro32(object, 0x0c); + tmp = nvkm_ro32(object, 0x0c); tmp &= ~mask; tmp |= value; - nv_wo32(object, 0x0c, tmp); + nvkm_wo32(object, 0x0c, tmp); + nvkm_done(object); /* check for valid surf2d/surf_dst/surf_color */ if (!(tmp & 0x02000000)) @@ -504,23 +510,24 @@ nv04_gr_set_ctx_val(struct nvkm_object *object, u32 mask, u32 value) break; } - nv04_gr_set_ctx1(object, 0x01000000, valid << 24); + nv04_gr_set_ctx1(obj, 0x01000000, valid << 24); } static int -nv04_gr_mthd_set_operation(struct nvkm_object *object, u32 mthd, +nv04_gr_mthd_set_operation(struct nvkm_object *obj, u32 mthd, void *args, u32 size) { - u32 class = nv_ro32(object, 0) & 0xff; + struct nvkm_gpuobj *object = container_of(obj, typeof(*object), object); + u32 class = nvkm_ro32(object, 0) & 0xff; u32 data = *(u32 *)args; if (data > 5) return 1; /* Old versions of the objects only accept first three operations. */ if (data > 2 && class < 0x40) return 1; - nv04_gr_set_ctx1(object, 0x00038000, data << 15); + nv04_gr_set_ctx1(obj, 0x00038000, data << 15); /* changing operation changes set of objects needed for validation */ - nv04_gr_set_ctx_val(object, 0, 0); + nv04_gr_set_ctx_val(obj, 0, 0); return 0; } @@ -963,13 +970,15 @@ nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - nv_wo32(obj, 0x00, nv_mclass(obj)); + nvkm_kmap(obj); + nvkm_wo32(obj, 0x00, nv_mclass(obj)); #ifdef __BIG_ENDIAN - nv_mo32(obj, 0x00, 0x00080000, 0x00080000); + nvkm_mo32(obj, 0x00, 0x00080000, 0x00080000); #endif - nv_wo32(obj, 0x04, 0x00000000); - nv_wo32(obj, 0x08, 0x00000000); - nv_wo32(obj, 0x0c, 0x00000000); + nvkm_wo32(obj, 0x04, 0x00000000); + nvkm_wo32(obj, 0x08, 0x00000000); + nvkm_wo32(obj, 0x0c, 0x00000000); + nvkm_done(obj); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index dab64540e69f..f4b8eaced1b6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -41,6 +41,7 @@ nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv20_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, @@ -50,51 +51,54 @@ nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; chan->chid = nvkm_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x033c, 0xffff0000); - nv_wo32(chan, 0x03a0, 0x0fff0000); - nv_wo32(chan, 0x03a4, 0x0fff0000); - nv_wo32(chan, 0x047c, 0x00000101); - nv_wo32(chan, 0x0490, 0x00000111); - nv_wo32(chan, 0x04a8, 0x44400000); + image = &chan->base.base.gpuobj; + + nvkm_kmap(image); + nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(image, 0x033c, 0xffff0000); + nvkm_wo32(image, 0x03a0, 0x0fff0000); + nvkm_wo32(image, 0x03a4, 0x0fff0000); + nvkm_wo32(image, 0x047c, 0x00000101); + nvkm_wo32(image, 0x0490, 0x00000111); + nvkm_wo32(image, 0x04a8, 0x44400000); for (i = 0x04d4; i <= 0x04e0; i += 4) - nv_wo32(chan, i, 0x00030303); + nvkm_wo32(image, i, 0x00030303); for (i = 0x04f4; i <= 0x0500; i += 4) - nv_wo32(chan, i, 0x00080000); + nvkm_wo32(image, i, 0x00080000); for (i = 0x050c; i <= 0x0518; i += 4) - nv_wo32(chan, i, 0x01012000); + nvkm_wo32(image, i, 0x01012000); for (i = 0x051c; i <= 0x0528; i += 4) - nv_wo32(chan, i, 0x000105b8); + nvkm_wo32(image, i, 0x000105b8); for (i = 0x052c; i <= 0x0538; i += 4) - nv_wo32(chan, i, 0x00080008); + nvkm_wo32(image, i, 0x00080008); for (i = 0x055c; i <= 0x0598; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x05a4, 0x4b7fffff); - nv_wo32(chan, 0x05fc, 0x00000001); - nv_wo32(chan, 0x0604, 0x00004000); - nv_wo32(chan, 0x0610, 0x00000001); - nv_wo32(chan, 0x0618, 0x00040000); - nv_wo32(chan, 0x061c, 0x00010000); + nvkm_wo32(image, i, 0x07ff0000); + nvkm_wo32(image, 0x05a4, 0x4b7fffff); + nvkm_wo32(image, 0x05fc, 0x00000001); + nvkm_wo32(image, 0x0604, 0x00004000); + nvkm_wo32(image, 0x0610, 0x00000001); + nvkm_wo32(image, 0x0618, 0x00040000); + nvkm_wo32(image, 0x061c, 0x00010000); for (i = 0x1c1c; i <= 0x248c; i += 16) { - nv_wo32(chan, (i + 0), 0x10700ff9); - nv_wo32(chan, (i + 4), 0x0436086c); - nv_wo32(chan, (i + 8), 0x000c001b); + nvkm_wo32(image, (i + 0), 0x10700ff9); + nvkm_wo32(image, (i + 4), 0x0436086c); + nvkm_wo32(image, (i + 8), 0x000c001b); } - nv_wo32(chan, 0x281c, 0x3f800000); - nv_wo32(chan, 0x2830, 0x3f800000); - nv_wo32(chan, 0x285c, 0x40000000); - nv_wo32(chan, 0x2860, 0x3f800000); - nv_wo32(chan, 0x2864, 0x3f000000); - nv_wo32(chan, 0x286c, 0x40000000); - nv_wo32(chan, 0x2870, 0x3f800000); - nv_wo32(chan, 0x2878, 0xbf800000); - nv_wo32(chan, 0x2880, 0xbf800000); - nv_wo32(chan, 0x34a4, 0x000fe000); - nv_wo32(chan, 0x3530, 0x000003f8); - nv_wo32(chan, 0x3540, 0x002fe000); + nvkm_wo32(image, 0x281c, 0x3f800000); + nvkm_wo32(image, 0x2830, 0x3f800000); + nvkm_wo32(image, 0x285c, 0x40000000); + nvkm_wo32(image, 0x2860, 0x3f800000); + nvkm_wo32(image, 0x2864, 0x3f000000); + nvkm_wo32(image, 0x286c, 0x40000000); + nvkm_wo32(image, 0x2870, 0x3f800000); + nvkm_wo32(image, 0x2878, 0xbf800000); + nvkm_wo32(image, 0x2880, 0xbf800000); + nvkm_wo32(image, 0x34a4, 0x000fe000); + nvkm_wo32(image, 0x3530, 0x000003f8); + nvkm_wo32(image, 0x3540, 0x002fe000); for (i = 0x355c; i <= 0x3578; i += 4) - nv_wo32(chan, i, 0x001c527c); + nvkm_wo32(image, i, 0x001c527c); + nvkm_done(image); return 0; } @@ -109,7 +113,9 @@ nv20_gr_context_init(struct nvkm_object *object) if (ret) return ret; - nv_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); + nvkm_kmap(gr->ctxtab); + nvkm_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); + nvkm_done(gr->ctxtab); return 0; } @@ -136,7 +142,9 @@ nv20_gr_context_fini(struct nvkm_object *object, bool suspend) } nvkm_mask(device, 0x400720, 0x00000001, 0x00000001); - nv_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); + nvkm_kmap(gr->ctxtab); + nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); + nvkm_done(gr->ctxtab); return nvkm_gr_context_fini(&chan->base, suspend); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index 50bad48a3eab..1a186bd93f64 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -37,6 +37,7 @@ nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv20_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, @@ -46,60 +47,63 @@ nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; chan->chid = nvkm_fifo_chan(parent)->chid; + image = &chan->base.base.gpuobj; - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x035c, 0xffff0000); - nv_wo32(chan, 0x03c0, 0x0fff0000); - nv_wo32(chan, 0x03c4, 0x0fff0000); - nv_wo32(chan, 0x049c, 0x00000101); - nv_wo32(chan, 0x04b0, 0x00000111); - nv_wo32(chan, 0x04c8, 0x00000080); - nv_wo32(chan, 0x04cc, 0xffff0000); - nv_wo32(chan, 0x04d0, 0x00000001); - nv_wo32(chan, 0x04e4, 0x44400000); - nv_wo32(chan, 0x04fc, 0x4b800000); + nvkm_kmap(image); + nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(image, 0x035c, 0xffff0000); + nvkm_wo32(image, 0x03c0, 0x0fff0000); + nvkm_wo32(image, 0x03c4, 0x0fff0000); + nvkm_wo32(image, 0x049c, 0x00000101); + nvkm_wo32(image, 0x04b0, 0x00000111); + nvkm_wo32(image, 0x04c8, 0x00000080); + nvkm_wo32(image, 0x04cc, 0xffff0000); + nvkm_wo32(image, 0x04d0, 0x00000001); + nvkm_wo32(image, 0x04e4, 0x44400000); + nvkm_wo32(image, 0x04fc, 0x4b800000); for (i = 0x0510; i <= 0x051c; i += 4) - nv_wo32(chan, i, 0x00030303); + nvkm_wo32(image, i, 0x00030303); for (i = 0x0530; i <= 0x053c; i += 4) - nv_wo32(chan, i, 0x00080000); + nvkm_wo32(image, i, 0x00080000); for (i = 0x0548; i <= 0x0554; i += 4) - nv_wo32(chan, i, 0x01012000); + nvkm_wo32(image, i, 0x01012000); for (i = 0x0558; i <= 0x0564; i += 4) - nv_wo32(chan, i, 0x000105b8); + nvkm_wo32(image, i, 0x000105b8); for (i = 0x0568; i <= 0x0574; i += 4) - nv_wo32(chan, i, 0x00080008); + nvkm_wo32(image, i, 0x00080008); for (i = 0x0598; i <= 0x05d4; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x05e0, 0x4b7fffff); - nv_wo32(chan, 0x0620, 0x00000080); - nv_wo32(chan, 0x0624, 0x30201000); - nv_wo32(chan, 0x0628, 0x70605040); - nv_wo32(chan, 0x062c, 0xb0a09080); - nv_wo32(chan, 0x0630, 0xf0e0d0c0); - nv_wo32(chan, 0x0664, 0x00000001); - nv_wo32(chan, 0x066c, 0x00004000); - nv_wo32(chan, 0x0678, 0x00000001); - nv_wo32(chan, 0x0680, 0x00040000); - nv_wo32(chan, 0x0684, 0x00010000); + nvkm_wo32(image, i, 0x07ff0000); + nvkm_wo32(image, 0x05e0, 0x4b7fffff); + nvkm_wo32(image, 0x0620, 0x00000080); + nvkm_wo32(image, 0x0624, 0x30201000); + nvkm_wo32(image, 0x0628, 0x70605040); + nvkm_wo32(image, 0x062c, 0xb0a09080); + nvkm_wo32(image, 0x0630, 0xf0e0d0c0); + nvkm_wo32(image, 0x0664, 0x00000001); + nvkm_wo32(image, 0x066c, 0x00004000); + nvkm_wo32(image, 0x0678, 0x00000001); + nvkm_wo32(image, 0x0680, 0x00040000); + nvkm_wo32(image, 0x0684, 0x00010000); for (i = 0x1b04; i <= 0x2374; i += 16) { - nv_wo32(chan, (i + 0), 0x10700ff9); - nv_wo32(chan, (i + 4), 0x0436086c); - nv_wo32(chan, (i + 8), 0x000c001b); + nvkm_wo32(image, (i + 0), 0x10700ff9); + nvkm_wo32(image, (i + 4), 0x0436086c); + nvkm_wo32(image, (i + 8), 0x000c001b); } - nv_wo32(chan, 0x2704, 0x3f800000); - nv_wo32(chan, 0x2718, 0x3f800000); - nv_wo32(chan, 0x2744, 0x40000000); - nv_wo32(chan, 0x2748, 0x3f800000); - nv_wo32(chan, 0x274c, 0x3f000000); - nv_wo32(chan, 0x2754, 0x40000000); - nv_wo32(chan, 0x2758, 0x3f800000); - nv_wo32(chan, 0x2760, 0xbf800000); - nv_wo32(chan, 0x2768, 0xbf800000); - nv_wo32(chan, 0x308c, 0x000fe000); - nv_wo32(chan, 0x3108, 0x000003f8); - nv_wo32(chan, 0x3468, 0x002fe000); + nvkm_wo32(image, 0x2704, 0x3f800000); + nvkm_wo32(image, 0x2718, 0x3f800000); + nvkm_wo32(image, 0x2744, 0x40000000); + nvkm_wo32(image, 0x2748, 0x3f800000); + nvkm_wo32(image, 0x274c, 0x3f000000); + nvkm_wo32(image, 0x2754, 0x40000000); + nvkm_wo32(image, 0x2758, 0x3f800000); + nvkm_wo32(image, 0x2760, 0xbf800000); + nvkm_wo32(image, 0x2768, 0xbf800000); + nvkm_wo32(image, 0x308c, 0x000fe000); + nvkm_wo32(image, 0x3108, 0x000003f8); + nvkm_wo32(image, 0x3468, 0x002fe000); for (i = 0x3484; i <= 0x34a0; i += 4) - nv_wo32(chan, i, 0x001c527c); + nvkm_wo32(image, i, 0x001c527c); + nvkm_done(image); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index 5c8ae50ee8e7..dfb62dc6b3b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -13,6 +13,7 @@ nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv20_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, @@ -22,51 +23,54 @@ nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; chan->chid = nvkm_fifo_chan(parent)->chid; + image = &chan->base.base.gpuobj; - nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x033c, 0xffff0000); - nv_wo32(chan, 0x03a0, 0x0fff0000); - nv_wo32(chan, 0x03a4, 0x0fff0000); - nv_wo32(chan, 0x047c, 0x00000101); - nv_wo32(chan, 0x0490, 0x00000111); - nv_wo32(chan, 0x04a8, 0x44400000); + nvkm_kmap(image); + nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(image, 0x033c, 0xffff0000); + nvkm_wo32(image, 0x03a0, 0x0fff0000); + nvkm_wo32(image, 0x03a4, 0x0fff0000); + nvkm_wo32(image, 0x047c, 0x00000101); + nvkm_wo32(image, 0x0490, 0x00000111); + nvkm_wo32(image, 0x04a8, 0x44400000); for (i = 0x04d4; i <= 0x04e0; i += 4) - nv_wo32(chan, i, 0x00030303); + nvkm_wo32(image, i, 0x00030303); for (i = 0x04f4; i <= 0x0500; i += 4) - nv_wo32(chan, i, 0x00080000); + nvkm_wo32(image, i, 0x00080000); for (i = 0x050c; i <= 0x0518; i += 4) - nv_wo32(chan, i, 0x01012000); + nvkm_wo32(image, i, 0x01012000); for (i = 0x051c; i <= 0x0528; i += 4) - nv_wo32(chan, i, 0x000105b8); + nvkm_wo32(image, i, 0x000105b8); for (i = 0x052c; i <= 0x0538; i += 4) - nv_wo32(chan, i, 0x00080008); + nvkm_wo32(image, i, 0x00080008); for (i = 0x055c; i <= 0x0598; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x05a4, 0x4b7fffff); - nv_wo32(chan, 0x05fc, 0x00000001); - nv_wo32(chan, 0x0604, 0x00004000); - nv_wo32(chan, 0x0610, 0x00000001); - nv_wo32(chan, 0x0618, 0x00040000); - nv_wo32(chan, 0x061c, 0x00010000); + nvkm_wo32(image, i, 0x07ff0000); + nvkm_wo32(image, 0x05a4, 0x4b7fffff); + nvkm_wo32(image, 0x05fc, 0x00000001); + nvkm_wo32(image, 0x0604, 0x00004000); + nvkm_wo32(image, 0x0610, 0x00000001); + nvkm_wo32(image, 0x0618, 0x00040000); + nvkm_wo32(image, 0x061c, 0x00010000); for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ - nv_wo32(chan, (i + 0), 0x10700ff9); - nv_wo32(chan, (i + 4), 0x0436086c); - nv_wo32(chan, (i + 8), 0x000c001b); + nvkm_wo32(image, (i + 0), 0x10700ff9); + nvkm_wo32(image, (i + 4), 0x0436086c); + nvkm_wo32(image, (i + 8), 0x000c001b); } - nv_wo32(chan, 0x269c, 0x3f800000); - nv_wo32(chan, 0x26b0, 0x3f800000); - nv_wo32(chan, 0x26dc, 0x40000000); - nv_wo32(chan, 0x26e0, 0x3f800000); - nv_wo32(chan, 0x26e4, 0x3f000000); - nv_wo32(chan, 0x26ec, 0x40000000); - nv_wo32(chan, 0x26f0, 0x3f800000); - nv_wo32(chan, 0x26f8, 0xbf800000); - nv_wo32(chan, 0x2700, 0xbf800000); - nv_wo32(chan, 0x3024, 0x000fe000); - nv_wo32(chan, 0x30a0, 0x000003f8); - nv_wo32(chan, 0x33fc, 0x002fe000); + nvkm_wo32(image, 0x269c, 0x3f800000); + nvkm_wo32(image, 0x26b0, 0x3f800000); + nvkm_wo32(image, 0x26dc, 0x40000000); + nvkm_wo32(image, 0x26e0, 0x3f800000); + nvkm_wo32(image, 0x26e4, 0x3f000000); + nvkm_wo32(image, 0x26ec, 0x40000000); + nvkm_wo32(image, 0x26f0, 0x3f800000); + nvkm_wo32(image, 0x26f8, 0xbf800000); + nvkm_wo32(image, 0x2700, 0xbf800000); + nvkm_wo32(image, 0x3024, 0x000fe000); + nvkm_wo32(image, 0x30a0, 0x000003f8); + nvkm_wo32(image, 0x33fc, 0x002fe000); for (i = 0x341c; i <= 0x3438; i += 4) - nv_wo32(chan, i, 0x001c527c); + nvkm_wo32(image, i, 0x001c527c); + nvkm_done(image); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 8be77b4f15ad..51573736bb48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -40,6 +40,7 @@ nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv20_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, @@ -49,59 +50,62 @@ nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; chan->chid = nvkm_fifo_chan(parent)->chid; - - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x0410, 0x00000101); - nv_wo32(chan, 0x0424, 0x00000111); - nv_wo32(chan, 0x0428, 0x00000060); - nv_wo32(chan, 0x0444, 0x00000080); - nv_wo32(chan, 0x0448, 0xffff0000); - nv_wo32(chan, 0x044c, 0x00000001); - nv_wo32(chan, 0x0460, 0x44400000); - nv_wo32(chan, 0x048c, 0xffff0000); + image = &chan->base.base.gpuobj; + + nvkm_kmap(image); + nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(image, 0x0410, 0x00000101); + nvkm_wo32(image, 0x0424, 0x00000111); + nvkm_wo32(image, 0x0428, 0x00000060); + nvkm_wo32(image, 0x0444, 0x00000080); + nvkm_wo32(image, 0x0448, 0xffff0000); + nvkm_wo32(image, 0x044c, 0x00000001); + nvkm_wo32(image, 0x0460, 0x44400000); + nvkm_wo32(image, 0x048c, 0xffff0000); for (i = 0x04e0; i < 0x04e8; i += 4) - nv_wo32(chan, i, 0x0fff0000); - nv_wo32(chan, 0x04ec, 0x00011100); + nvkm_wo32(image, i, 0x0fff0000); + nvkm_wo32(image, 0x04ec, 0x00011100); for (i = 0x0508; i < 0x0548; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x0550, 0x4b7fffff); - nv_wo32(chan, 0x058c, 0x00000080); - nv_wo32(chan, 0x0590, 0x30201000); - nv_wo32(chan, 0x0594, 0x70605040); - nv_wo32(chan, 0x0598, 0xb8a89888); - nv_wo32(chan, 0x059c, 0xf8e8d8c8); - nv_wo32(chan, 0x05b0, 0xb0000000); + nvkm_wo32(image, i, 0x07ff0000); + nvkm_wo32(image, 0x0550, 0x4b7fffff); + nvkm_wo32(image, 0x058c, 0x00000080); + nvkm_wo32(image, 0x0590, 0x30201000); + nvkm_wo32(image, 0x0594, 0x70605040); + nvkm_wo32(image, 0x0598, 0xb8a89888); + nvkm_wo32(image, 0x059c, 0xf8e8d8c8); + nvkm_wo32(image, 0x05b0, 0xb0000000); for (i = 0x0600; i < 0x0640; i += 4) - nv_wo32(chan, i, 0x00010588); + nvkm_wo32(image, i, 0x00010588); for (i = 0x0640; i < 0x0680; i += 4) - nv_wo32(chan, i, 0x00030303); + nvkm_wo32(image, i, 0x00030303); for (i = 0x06c0; i < 0x0700; i += 4) - nv_wo32(chan, i, 0x0008aae4); + nvkm_wo32(image, i, 0x0008aae4); for (i = 0x0700; i < 0x0740; i += 4) - nv_wo32(chan, i, 0x01012000); + nvkm_wo32(image, i, 0x01012000); for (i = 0x0740; i < 0x0780; i += 4) - nv_wo32(chan, i, 0x00080008); - nv_wo32(chan, 0x085c, 0x00040000); - nv_wo32(chan, 0x0860, 0x00010000); + nvkm_wo32(image, i, 0x00080008); + nvkm_wo32(image, 0x085c, 0x00040000); + nvkm_wo32(image, 0x0860, 0x00010000); for (i = 0x0864; i < 0x0874; i += 4) - nv_wo32(chan, i, 0x00040004); + nvkm_wo32(image, i, 0x00040004); for (i = 0x1f18; i <= 0x3088 ; i += 16) { - nv_wo32(chan, i + 0, 0x10700ff9); - nv_wo32(chan, i + 1, 0x0436086c); - nv_wo32(chan, i + 2, 0x000c001b); + nvkm_wo32(image, i + 0, 0x10700ff9); + nvkm_wo32(image, i + 1, 0x0436086c); + nvkm_wo32(image, i + 2, 0x000c001b); } for (i = 0x30b8; i < 0x30c8; i += 4) - nv_wo32(chan, i, 0x0000ffff); - nv_wo32(chan, 0x344c, 0x3f800000); - nv_wo32(chan, 0x3808, 0x3f800000); - nv_wo32(chan, 0x381c, 0x3f800000); - nv_wo32(chan, 0x3848, 0x40000000); - nv_wo32(chan, 0x384c, 0x3f800000); - nv_wo32(chan, 0x3850, 0x3f000000); - nv_wo32(chan, 0x3858, 0x40000000); - nv_wo32(chan, 0x385c, 0x3f800000); - nv_wo32(chan, 0x3864, 0xbf800000); - nv_wo32(chan, 0x386c, 0xbf800000); + nvkm_wo32(image, i, 0x0000ffff); + nvkm_wo32(image, 0x344c, 0x3f800000); + nvkm_wo32(image, 0x3808, 0x3f800000); + nvkm_wo32(image, 0x381c, 0x3f800000); + nvkm_wo32(image, 0x3848, 0x40000000); + nvkm_wo32(image, 0x384c, 0x3f800000); + nvkm_wo32(image, 0x3850, 0x3f000000); + nvkm_wo32(image, 0x3858, 0x40000000); + nvkm_wo32(image, 0x385c, 0x3f800000); + nvkm_wo32(image, 0x3864, 0xbf800000); + nvkm_wo32(image, 0x386c, 0xbf800000); + nvkm_done(image); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index e17eb0b13277..f9d71185ee74 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -39,6 +39,7 @@ nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv20_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc, @@ -48,59 +49,62 @@ nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; chan->chid = nvkm_fifo_chan(parent)->chid; + image = &chan->base.base.gpuobj; - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x040c, 0x01000101); - nv_wo32(chan, 0x0420, 0x00000111); - nv_wo32(chan, 0x0424, 0x00000060); - nv_wo32(chan, 0x0440, 0x00000080); - nv_wo32(chan, 0x0444, 0xffff0000); - nv_wo32(chan, 0x0448, 0x00000001); - nv_wo32(chan, 0x045c, 0x44400000); - nv_wo32(chan, 0x0480, 0xffff0000); + nvkm_kmap(image); + nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(image, 0x040c, 0x01000101); + nvkm_wo32(image, 0x0420, 0x00000111); + nvkm_wo32(image, 0x0424, 0x00000060); + nvkm_wo32(image, 0x0440, 0x00000080); + nvkm_wo32(image, 0x0444, 0xffff0000); + nvkm_wo32(image, 0x0448, 0x00000001); + nvkm_wo32(image, 0x045c, 0x44400000); + nvkm_wo32(image, 0x0480, 0xffff0000); for (i = 0x04d4; i < 0x04dc; i += 4) - nv_wo32(chan, i, 0x0fff0000); - nv_wo32(chan, 0x04e0, 0x00011100); + nvkm_wo32(image, i, 0x0fff0000); + nvkm_wo32(image, 0x04e0, 0x00011100); for (i = 0x04fc; i < 0x053c; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x0544, 0x4b7fffff); - nv_wo32(chan, 0x057c, 0x00000080); - nv_wo32(chan, 0x0580, 0x30201000); - nv_wo32(chan, 0x0584, 0x70605040); - nv_wo32(chan, 0x0588, 0xb8a89888); - nv_wo32(chan, 0x058c, 0xf8e8d8c8); - nv_wo32(chan, 0x05a0, 0xb0000000); + nvkm_wo32(image, i, 0x07ff0000); + nvkm_wo32(image, 0x0544, 0x4b7fffff); + nvkm_wo32(image, 0x057c, 0x00000080); + nvkm_wo32(image, 0x0580, 0x30201000); + nvkm_wo32(image, 0x0584, 0x70605040); + nvkm_wo32(image, 0x0588, 0xb8a89888); + nvkm_wo32(image, 0x058c, 0xf8e8d8c8); + nvkm_wo32(image, 0x05a0, 0xb0000000); for (i = 0x05f0; i < 0x0630; i += 4) - nv_wo32(chan, i, 0x00010588); + nvkm_wo32(image, i, 0x00010588); for (i = 0x0630; i < 0x0670; i += 4) - nv_wo32(chan, i, 0x00030303); + nvkm_wo32(image, i, 0x00030303); for (i = 0x06b0; i < 0x06f0; i += 4) - nv_wo32(chan, i, 0x0008aae4); + nvkm_wo32(image, i, 0x0008aae4); for (i = 0x06f0; i < 0x0730; i += 4) - nv_wo32(chan, i, 0x01012000); + nvkm_wo32(image, i, 0x01012000); for (i = 0x0730; i < 0x0770; i += 4) - nv_wo32(chan, i, 0x00080008); - nv_wo32(chan, 0x0850, 0x00040000); - nv_wo32(chan, 0x0854, 0x00010000); + nvkm_wo32(image, i, 0x00080008); + nvkm_wo32(image, 0x0850, 0x00040000); + nvkm_wo32(image, 0x0854, 0x00010000); for (i = 0x0858; i < 0x0868; i += 4) - nv_wo32(chan, i, 0x00040004); + nvkm_wo32(image, i, 0x00040004); for (i = 0x15ac; i <= 0x271c ; i += 16) { - nv_wo32(chan, i + 0, 0x10700ff9); - nv_wo32(chan, i + 1, 0x0436086c); - nv_wo32(chan, i + 2, 0x000c001b); + nvkm_wo32(image, i + 0, 0x10700ff9); + nvkm_wo32(image, i + 1, 0x0436086c); + nvkm_wo32(image, i + 2, 0x000c001b); } for (i = 0x274c; i < 0x275c; i += 4) - nv_wo32(chan, i, 0x0000ffff); - nv_wo32(chan, 0x2ae0, 0x3f800000); - nv_wo32(chan, 0x2e9c, 0x3f800000); - nv_wo32(chan, 0x2eb0, 0x3f800000); - nv_wo32(chan, 0x2edc, 0x40000000); - nv_wo32(chan, 0x2ee0, 0x3f800000); - nv_wo32(chan, 0x2ee4, 0x3f000000); - nv_wo32(chan, 0x2eec, 0x40000000); - nv_wo32(chan, 0x2ef0, 0x3f800000); - nv_wo32(chan, 0x2ef8, 0xbf800000); - nv_wo32(chan, 0x2f00, 0xbf800000); + nvkm_wo32(image, i, 0x0000ffff); + nvkm_wo32(image, 0x2ae0, 0x3f800000); + nvkm_wo32(image, 0x2e9c, 0x3f800000); + nvkm_wo32(image, 0x2eb0, 0x3f800000); + nvkm_wo32(image, 0x2edc, 0x40000000); + nvkm_wo32(image, 0x2ee0, 0x3f800000); + nvkm_wo32(image, 0x2ee4, 0x3f000000); + nvkm_wo32(image, 0x2eec, 0x40000000); + nvkm_wo32(image, 0x2ef0, 0x3f800000); + nvkm_wo32(image, 0x2ef8, 0xbf800000); + nvkm_wo32(image, 0x2f00, 0xbf800000); + nvkm_done(image); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 35ba75130f93..c6357f2fdb36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -39,6 +39,7 @@ nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nv20_gr_chan *chan; + struct nvkm_gpuobj *image; int ret, i; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, @@ -48,59 +49,62 @@ nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; chan->chid = nvkm_fifo_chan(parent)->chid; + image = &chan->base.base.gpuobj; - nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); - nv_wo32(chan, 0x040c, 0x00000101); - nv_wo32(chan, 0x0420, 0x00000111); - nv_wo32(chan, 0x0424, 0x00000060); - nv_wo32(chan, 0x0440, 0x00000080); - nv_wo32(chan, 0x0444, 0xffff0000); - nv_wo32(chan, 0x0448, 0x00000001); - nv_wo32(chan, 0x045c, 0x44400000); - nv_wo32(chan, 0x0488, 0xffff0000); + nvkm_kmap(image); + nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(image, 0x040c, 0x00000101); + nvkm_wo32(image, 0x0420, 0x00000111); + nvkm_wo32(image, 0x0424, 0x00000060); + nvkm_wo32(image, 0x0440, 0x00000080); + nvkm_wo32(image, 0x0444, 0xffff0000); + nvkm_wo32(image, 0x0448, 0x00000001); + nvkm_wo32(image, 0x045c, 0x44400000); + nvkm_wo32(image, 0x0488, 0xffff0000); for (i = 0x04dc; i < 0x04e4; i += 4) - nv_wo32(chan, i, 0x0fff0000); - nv_wo32(chan, 0x04e8, 0x00011100); + nvkm_wo32(image, i, 0x0fff0000); + nvkm_wo32(image, 0x04e8, 0x00011100); for (i = 0x0504; i < 0x0544; i += 4) - nv_wo32(chan, i, 0x07ff0000); - nv_wo32(chan, 0x054c, 0x4b7fffff); - nv_wo32(chan, 0x0588, 0x00000080); - nv_wo32(chan, 0x058c, 0x30201000); - nv_wo32(chan, 0x0590, 0x70605040); - nv_wo32(chan, 0x0594, 0xb8a89888); - nv_wo32(chan, 0x0598, 0xf8e8d8c8); - nv_wo32(chan, 0x05ac, 0xb0000000); + nvkm_wo32(image, i, 0x07ff0000); + nvkm_wo32(image, 0x054c, 0x4b7fffff); + nvkm_wo32(image, 0x0588, 0x00000080); + nvkm_wo32(image, 0x058c, 0x30201000); + nvkm_wo32(image, 0x0590, 0x70605040); + nvkm_wo32(image, 0x0594, 0xb8a89888); + nvkm_wo32(image, 0x0598, 0xf8e8d8c8); + nvkm_wo32(image, 0x05ac, 0xb0000000); for (i = 0x0604; i < 0x0644; i += 4) - nv_wo32(chan, i, 0x00010588); + nvkm_wo32(image, i, 0x00010588); for (i = 0x0644; i < 0x0684; i += 4) - nv_wo32(chan, i, 0x00030303); + nvkm_wo32(image, i, 0x00030303); for (i = 0x06c4; i < 0x0704; i += 4) - nv_wo32(chan, i, 0x0008aae4); + nvkm_wo32(image, i, 0x0008aae4); for (i = 0x0704; i < 0x0744; i += 4) - nv_wo32(chan, i, 0x01012000); + nvkm_wo32(image, i, 0x01012000); for (i = 0x0744; i < 0x0784; i += 4) - nv_wo32(chan, i, 0x00080008); - nv_wo32(chan, 0x0860, 0x00040000); - nv_wo32(chan, 0x0864, 0x00010000); + nvkm_wo32(image, i, 0x00080008); + nvkm_wo32(image, 0x0860, 0x00040000); + nvkm_wo32(image, 0x0864, 0x00010000); for (i = 0x0868; i < 0x0878; i += 4) - nv_wo32(chan, i, 0x00040004); + nvkm_wo32(image, i, 0x00040004); for (i = 0x1f1c; i <= 0x308c ; i += 16) { - nv_wo32(chan, i + 0, 0x10700ff9); - nv_wo32(chan, i + 4, 0x0436086c); - nv_wo32(chan, i + 8, 0x000c001b); + nvkm_wo32(image, i + 0, 0x10700ff9); + nvkm_wo32(image, i + 4, 0x0436086c); + nvkm_wo32(image, i + 8, 0x000c001b); } for (i = 0x30bc; i < 0x30cc; i += 4) - nv_wo32(chan, i, 0x0000ffff); - nv_wo32(chan, 0x3450, 0x3f800000); - nv_wo32(chan, 0x380c, 0x3f800000); - nv_wo32(chan, 0x3820, 0x3f800000); - nv_wo32(chan, 0x384c, 0x40000000); - nv_wo32(chan, 0x3850, 0x3f800000); - nv_wo32(chan, 0x3854, 0x3f000000); - nv_wo32(chan, 0x385c, 0x40000000); - nv_wo32(chan, 0x3860, 0x3f800000); - nv_wo32(chan, 0x3868, 0xbf800000); - nv_wo32(chan, 0x3870, 0xbf800000); + nvkm_wo32(image, i, 0x0000ffff); + nvkm_wo32(image, 0x3450, 0x3f800000); + nvkm_wo32(image, 0x380c, 0x3f800000); + nvkm_wo32(image, 0x3820, 0x3f800000); + nvkm_wo32(image, 0x384c, 0x40000000); + nvkm_wo32(image, 0x3850, 0x3f800000); + nvkm_wo32(image, 0x3854, 0x3f000000); + nvkm_wo32(image, 0x385c, 0x40000000); + nvkm_wo32(image, 0x3860, 0x3f800000); + nvkm_wo32(image, 0x3868, 0xbf800000); + nvkm_wo32(image, 0x3870, 0xbf800000); + nvkm_done(image); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 10ffb676e55e..1ebf2edef4d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -63,14 +63,16 @@ nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - nv_wo32(obj, 0x00, nv_mclass(obj)); - nv_wo32(obj, 0x04, 0x00000000); - nv_wo32(obj, 0x08, 0x00000000); + nvkm_kmap(obj); + nvkm_wo32(obj, 0x00, nv_mclass(obj)); + nvkm_wo32(obj, 0x04, 0x00000000); + nvkm_wo32(obj, 0x08, 0x00000000); #ifdef __BIG_ENDIAN - nv_mo32(obj, 0x08, 0x01000000, 0x01000000); + nvkm_mo32(obj, 0x08, 0x01000000, 0x01000000); #endif - nv_wo32(obj, 0x0c, 0x00000000); - nv_wo32(obj, 0x10, 0x00000000); + nvkm_wo32(obj, 0x0c, 0x00000000); + nvkm_wo32(obj, 0x10, 0x00000000); + nvkm_done(obj); return 0; } @@ -146,7 +148,7 @@ nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; nv40_grctx_fill(nv_device(gr), nv_gpuobj(chan)); - nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4); + nvkm_wo32(&chan->base.base.gpuobj, 0x00000, nv_gpuobj(chan)->addr >> 4); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 4ea7f0938769..c50cfe4875ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -62,10 +62,12 @@ nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - nv_wo32(obj, 0x00, nv_mclass(obj)); - nv_wo32(obj, 0x04, 0x00000000); - nv_wo32(obj, 0x08, 0x00000000); - nv_wo32(obj, 0x0c, 0x00000000); + nvkm_kmap(obj); + nvkm_wo32(obj, 0x00, nv_mclass(obj)); + nvkm_wo32(obj, 0x04, 0x00000000); + nvkm_wo32(obj, 0x08, 0x00000000); + nvkm_wo32(obj, 0x0c, 0x00000000); + nvkm_done(obj); return 0; } -- cgit v1.2.3 From d36a99d2da22bdffebf644e4a5f811e8eff82360 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:14 +1000 Subject: drm/nouveau/fb: transition nvkm_ram away from being based on nvkm_object Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/mm.h | 3 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 63 +++-- drivers/gpu/drm/nouveau/nouveau_ttm.c | 39 +-- drivers/gpu/drm/nouveau/nvkm/core/mm.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c | 10 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c | 72 +---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h | 11 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c | 7 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c | 5 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 5 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c | 5 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c | 5 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c | 5 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h | 14 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h | 8 - drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h | 38 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c | 100 +++++++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h | 50 ++++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 295 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 170 ++++++------ drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c | 37 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c | 186 ++++++------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c | 100 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c | 51 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c | 36 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 34 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c | 46 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c | 91 ++++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h | 14 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c | 46 +--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c | 41 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c | 46 +--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c | 34 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 204 +++++++------- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 9 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c | 18 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 2 +- 59 files changed, 872 insertions(+), 1092 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h index 096eb1a623ee..d92fd41e4056 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/mm.h @@ -27,7 +27,7 @@ struct nvkm_mm { static inline bool nvkm_mm_initialised(struct nvkm_mm *mm) { - return mm->block_size != 0; + return mm->heap_nodes; } int nvkm_mm_init(struct nvkm_mm *, u32 offset, u32 length, u32 block); @@ -37,4 +37,5 @@ int nvkm_mm_head(struct nvkm_mm *, u8 heap, u8 type, u32 size_max, int nvkm_mm_tail(struct nvkm_mm *, u8 heap, u8 type, u32 size_max, u32 size_min, u32 align, struct nvkm_mm_node **); void nvkm_mm_free(struct nvkm_mm *, struct nvkm_mm_node **); +void nvkm_mm_dump(struct nvkm_mm *, const char *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index 344cc99f0dc1..f102cf97bb93 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -18,7 +18,7 @@ #define NV_MEM_TARGET_VM 3 #define NV_MEM_TARGET_GART 4 -#define NV_MEM_TYPE_VM 0x7f +#define NVKM_RAM_TYPE_VM 0x7f #define NV_MEM_COMP_VM 0x03 struct nvkm_mem { @@ -52,9 +52,6 @@ struct nvkm_fb { struct nvkm_ram *ram; - struct nvkm_mm vram; - struct nvkm_mm tags; - struct { struct nvkm_fb_tile region[16]; int regions; @@ -112,36 +109,35 @@ struct nvkm_ram_data { u32 freq; }; +enum nvkm_ram_type { + NVKM_RAM_TYPE_UNKNOWN = 0, + NVKM_RAM_TYPE_STOLEN, + NVKM_RAM_TYPE_SGRAM, + NVKM_RAM_TYPE_SDRAM, + NVKM_RAM_TYPE_DDR1, + NVKM_RAM_TYPE_DDR2, + NVKM_RAM_TYPE_DDR3, + NVKM_RAM_TYPE_GDDR2, + NVKM_RAM_TYPE_GDDR3, + NVKM_RAM_TYPE_GDDR4, + NVKM_RAM_TYPE_GDDR5 +}; + struct nvkm_ram { - struct nvkm_object base; - enum { - NV_MEM_TYPE_UNKNOWN = 0, - NV_MEM_TYPE_STOLEN, - NV_MEM_TYPE_SGRAM, - NV_MEM_TYPE_SDRAM, - NV_MEM_TYPE_DDR1, - NV_MEM_TYPE_DDR2, - NV_MEM_TYPE_DDR3, - NV_MEM_TYPE_GDDR2, - NV_MEM_TYPE_GDDR3, - NV_MEM_TYPE_GDDR4, - NV_MEM_TYPE_GDDR5 - } type; - u64 stolen; + const struct nvkm_ram_func *func; + struct nvkm_fb *fb; + enum nvkm_ram_type type; u64 size; - u32 tags; + +#define NVKM_RAM_MM_SHIFT 12 + struct nvkm_mm vram; + struct nvkm_mm tags; + u64 stolen; int ranks; int parts; int part_mask; - int (*get)(struct nvkm_fb *, u64 size, u32 align, u32 size_nc, - u32 type, struct nvkm_mem **); - void (*put)(struct nvkm_fb *, struct nvkm_mem **); - - int (*calc)(struct nvkm_fb *, u32 freq); - int (*prog)(struct nvkm_fb *); - void (*tidy)(struct nvkm_fb *); u32 freq; u32 mr[16]; u32 mr1_nuts; @@ -151,4 +147,17 @@ struct nvkm_ram { struct nvkm_ram_data xition; struct nvkm_ram_data target; }; + +struct nvkm_ram_func { + void *(*dtor)(struct nvkm_ram *); + int (*init)(struct nvkm_ram *); + + int (*get)(struct nvkm_ram *, u64 size, u32 align, u32 size_nc, + u32 type, struct nvkm_mem **); + void (*put)(struct nvkm_ram *, struct nvkm_mem **); + + int (*calc)(struct nvkm_ram *, u32 freq); + int (*prog)(struct nvkm_ram *); + void (*tidy)(struct nvkm_ram *); +}; #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 44e878b5601a..d8999f71a798 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -64,9 +64,9 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram; nvkm_mem_node_cleanup(mem->mm_node); - fb->ram->put(fb, (struct nvkm_mem **)&mem->mm_node); + ram->func->put(ram, (struct nvkm_mem **)&mem->mm_node); } static int @@ -76,7 +76,7 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) { struct nouveau_drm *drm = nouveau_bdev(man->bdev); - struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_ram *ram = nvxx_fb(&drm->device)->ram; struct nouveau_bo *nvbo = nouveau_bo(bo); struct nvkm_mem *node; u32 size_nc = 0; @@ -88,9 +88,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) size_nc = 1 << nvbo->page_shift; - ret = fb->ram->get(fb, mem->num_pages << PAGE_SHIFT, - mem->page_alignment << PAGE_SHIFT, size_nc, - (nvbo->tile_flags >> 8) & 0x3ff, &node); + ret = ram->func->get(ram, mem->num_pages << PAGE_SHIFT, + mem->page_alignment << PAGE_SHIFT, size_nc, + (nvbo->tile_flags >> 8) & 0x3ff, &node); if (ret) { mem->mm_node = NULL; return (ret == -ENOSPC) ? 0 : ret; @@ -103,38 +103,11 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, return 0; } -static void -nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) -{ - struct nvkm_fb *fb = man->priv; - struct nvkm_mm *mm = &fb->vram; - struct nvkm_mm_node *r; - u32 total = 0, free = 0; - - mutex_lock(&nv_subdev(fb)->mutex); - list_for_each_entry(r, &mm->nodes, nl_entry) { - printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n", - prefix, r->type, ((u64)r->offset << 12), - (((u64)r->offset + r->length) << 12)); - - total += r->length; - if (!r->type) - free += r->length; - } - mutex_unlock(&nv_subdev(fb)->mutex); - - printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n", - prefix, (u64)total << 12, (u64)free << 12); - printk(KERN_DEBUG "%s block: 0x%08x\n", - prefix, mm->block_size << 12); -} - const struct ttm_mem_type_manager_func nouveau_vram_manager = { nouveau_vram_manager_init, nouveau_vram_manager_fini, nouveau_vram_manager_new, nouveau_vram_manager_del, - nouveau_vram_manager_debug }; static int diff --git a/drivers/gpu/drm/nouveau/nvkm/core/mm.c b/drivers/gpu/drm/nouveau/nvkm/core/mm.c index 7f458dfd5608..09a1eee8fd33 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/mm.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/mm.c @@ -26,7 +26,7 @@ #define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \ list_entry((root)->nl_entry.dir, struct nvkm_mm_node, nl_entry) -static void +void nvkm_mm_dump(struct nvkm_mm *mm, const char *header) { struct nvkm_mm_node *node; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index 69561ee4e115..5bdb112dc945 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -569,7 +569,7 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx) else if (device->chipset < 0xa0) gr_def(ctx, 0x407d08, 0x00390040); else { - if (nvkm_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) + if (nvkm_fb(device)->ram->type != NVKM_RAM_TYPE_GDDR5) gr_def(ctx, 0x407d08, 0x003d0040); else gr_def(ctx, 0x407d08, 0x003c0040); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c index a05ec57150c6..cfd1feed99c3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c @@ -174,7 +174,7 @@ static int nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) { struct nvkm_subdev *subdev = &clk->subdev; - struct nvkm_fb *fb = subdev->device->fb; + struct nvkm_ram *ram = subdev->device->fb->ram; struct nvkm_pstate *pstate; int ret, idx = 0; @@ -186,14 +186,14 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) nvkm_debug(subdev, "setting performance state %d\n", pstatei); clk->pstate = pstatei; - if (fb->ram && fb->ram->calc) { + if (ram && ram->func->calc) { int khz = pstate->base.domain[nv_clk_src_mem]; do { - ret = fb->ram->calc(fb, khz); + ret = ram->func->calc(ram, khz); if (ret == 0) - ret = fb->ram->prog(fb); + ret = ram->func->prog(ram); } while (ret > 0); - fb->ram->tidy(fb); + ram->func->tidy(ram); } return nvkm_cstate_prog(clk, pstate, 0); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild index d6be4c6c5408..08105701af7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild @@ -23,6 +23,8 @@ nvkm-y += nvkm/subdev/fb/gf100.o nvkm-y += nvkm/subdev/fb/gk104.o nvkm-y += nvkm/subdev/fb/gk20a.o nvkm-y += nvkm/subdev/fb/gm107.o + +nvkm-y += nvkm/subdev/fb/ram.o nvkm-y += nvkm/subdev/fb/ramnv04.o nvkm-y += nvkm/subdev/fb/ramnv10.o nvkm-y += nvkm/subdev/fb/ramnv1a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index f0a5d197e7a0..328381b8f0ac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "priv.h" +#include "ram.h" #include #include @@ -37,32 +38,24 @@ nvkm_fb_bios_memtype(struct nvkm_bios *bios) if (nvbios_M0203Em(bios, ramcfg, &ver, &hdr, &M0203E)) { switch (M0203E.type) { - case M0203E_TYPE_DDR2 : return NV_MEM_TYPE_DDR2; - case M0203E_TYPE_DDR3 : return NV_MEM_TYPE_DDR3; - case M0203E_TYPE_GDDR3: return NV_MEM_TYPE_GDDR3; - case M0203E_TYPE_GDDR5: return NV_MEM_TYPE_GDDR5; + case M0203E_TYPE_DDR2 : return NVKM_RAM_TYPE_DDR2; + case M0203E_TYPE_DDR3 : return NVKM_RAM_TYPE_DDR3; + case M0203E_TYPE_GDDR3: return NVKM_RAM_TYPE_GDDR3; + case M0203E_TYPE_GDDR5: return NVKM_RAM_TYPE_GDDR5; default: nvkm_warn(subdev, "M0203E type %02x\n", M0203E.type); - return NV_MEM_TYPE_UNKNOWN; + return NVKM_RAM_TYPE_UNKNOWN; } } nvkm_warn(subdev, "M0203E not matched!\n"); - return NV_MEM_TYPE_UNKNOWN; + return NVKM_RAM_TYPE_UNKNOWN; } int _nvkm_fb_fini(struct nvkm_object *object, bool suspend) { struct nvkm_fb *fb = (void *)object; - int ret; - - if (fb->ram) { - ret = nv_ofuncs(fb->ram)->fini(nv_object(fb->ram), suspend); - if (ret && suspend) - return ret; - } - return nvkm_subdev_fini(&fb->subdev, suspend); } @@ -76,11 +69,8 @@ _nvkm_fb_init(struct nvkm_object *object) if (ret) return ret; - if (fb->ram) { - ret = nv_ofuncs(fb->ram)->init(nv_object(fb->ram)); - if (ret) - return ret; - } + if (fb->ram) + nvkm_ram_init(fb->ram); for (i = 0; i < fb->tile.regions; i++) fb->tile.prog(fb, i, &fb->tile.region[i]); @@ -96,13 +86,8 @@ _nvkm_fb_dtor(struct nvkm_object *object) for (i = 0; i < fb->tile.regions; i++) fb->tile.fini(fb, i, &fb->tile.region[i]); - nvkm_mm_fini(&fb->tags); - - if (fb->ram) { - nvkm_mm_fini(&fb->vram); - nvkm_object_ref(NULL, (struct nvkm_object **)&fb->ram); - } + nvkm_ram_del(&fb->ram); nvkm_subdev_destroy(&fb->subdev); } @@ -111,20 +96,6 @@ nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) { struct nvkm_fb_impl *impl = (void *)oclass; - static const char *name[] = { - [NV_MEM_TYPE_UNKNOWN] = "of unknown memory type", - [NV_MEM_TYPE_STOLEN ] = "stolen system memory", - [NV_MEM_TYPE_SGRAM ] = "SGRAM", - [NV_MEM_TYPE_SDRAM ] = "SDRAM", - [NV_MEM_TYPE_DDR1 ] = "DDR1", - [NV_MEM_TYPE_DDR2 ] = "DDR2", - [NV_MEM_TYPE_DDR3 ] = "DDR3", - [NV_MEM_TYPE_GDDR2 ] = "GDDR2", - [NV_MEM_TYPE_GDDR3 ] = "GDDR3", - [NV_MEM_TYPE_GDDR4 ] = "GDDR4", - [NV_MEM_TYPE_GDDR5 ] = "GDDR5", - }; - struct nvkm_object *ram; struct nvkm_fb *fb; int ret; @@ -136,33 +107,14 @@ nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, fb->memtype_valid = impl->memtype; - if (!impl->ram) + if (!impl->ram_new) return 0; - ret = nvkm_object_ctor(nv_object(fb), NULL, impl->ram, NULL, 0, &ram); + ret = impl->ram_new(fb, &fb->ram); if (ret) { nvkm_error(&fb->subdev, "vram init failed, %d\n", ret); return ret; } - fb->ram = (void *)ram; - - if (!nvkm_mm_initialised(&fb->vram)) { - ret = nvkm_mm_init(&fb->vram, 0, fb->ram->size >> 12, 1); - if (ret) - return ret; - } - - if (!nvkm_mm_initialised(&fb->tags)) { - ret = nvkm_mm_init(&fb->tags, 0, fb->ram->tags ? - ++fb->ram->tags : 0, 1); - if (ret) - return ret; - - nvkm_debug(&fb->subdev, "%d compression tags\n", fb->ram->tags); - } - - nvkm_info(&fb->subdev, "%d MiB %s\n", (int)(fb->ram->size >> 20), - name[fb->ram->type]); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c index 6c968d1e98b3..1fdb6c3493c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "nv50.h" +#include "ram.h" struct nvkm_oclass * g84_fb_oclass = &(struct nv50_fb_impl) { @@ -33,6 +34,6 @@ g84_fb_oclass = &(struct nv50_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nv50_ram_oclass, + .base.ram_new = nv50_ram_new, .trap = 0x001d07ff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c index 4465446c8063..79b523aa52aa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs * Roy Spliet */ -#include "priv.h" +#include "ram.h" struct ramxlat { int id; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c index f6f9eee1dcd0..24f83b09e6a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "priv.h" +#include "ram.h" /* binary driver only executes this path if the condition (a) is true * for any configuration (combination of rammap+ramcfg+timing) that diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 1ac7d746e476..b269f8f67eea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "gf100.h" +#include "ram.h" extern const u8 gf100_pte_storage_type_map[256]; @@ -113,5 +114,5 @@ gf100_fb_oclass = &(struct nvkm_fb_impl) { .fini = _nvkm_fb_fini, }, .memtype = gf100_fb_memtype_valid, - .ram = &gf100_ram_oclass, + .ram_new = gf100_ram_new, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h index add84641cd81..a0f6497d7a3f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -1,7 +1,6 @@ #ifndef __NVKM_RAM_NVC0_H__ #define __NVKM_RAM_NVC0_H__ #include "priv.h" -#include "nv50.h" struct gf100_fb { struct nvkm_fb base; @@ -15,14 +14,4 @@ int gf100_fb_ctor(struct nvkm_object *, struct nvkm_object *, void gf100_fb_dtor(struct nvkm_object *); int gf100_fb_init(struct nvkm_object *); bool gf100_fb_memtype_valid(struct nvkm_fb *, u32); - -#define gf100_ram_create(p,e,o,m,d) \ - gf100_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d) -int gf100_ram_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, u32, int, void **); -int gf100_ram_get(struct nvkm_fb *, u64, u32, u32, u32, - struct nvkm_mem **); -void gf100_ram_put(struct nvkm_fb *, struct nvkm_mem **); - -int gk104_ram_init(struct nvkm_object*); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c index 1c08317665bb..6ed6181a7b34 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "gf100.h" +#include "ram.h" struct nvkm_oclass * gk104_fb_oclass = &(struct nvkm_fb_impl) { @@ -33,5 +34,5 @@ gk104_fb_oclass = &(struct nvkm_fb_impl) { .fini = _nvkm_fb_fini, }, .memtype = gf100_fb_memtype_valid, - .ram = &gk104_ram_oclass, + .ram_new = gk104_ram_new, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c index 843f9356b360..71e3bd50848a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "gf100.h" +#include "ram.h" struct nvkm_oclass * gm107_fb_oclass = &(struct nvkm_fb_impl) { @@ -33,5 +34,5 @@ gm107_fb_oclass = &(struct nvkm_fb_impl) { .fini = _nvkm_fb_fini, }, .memtype = gf100_fb_memtype_valid, - .ram = &gm107_ram_oclass, + .ram_new = gm107_ram_new, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c index dd9b8a0a3c8e..425d289d4acc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "nv50.h" +#include "ram.h" struct nvkm_oclass * gt215_fb_oclass = &(struct nv50_fb_impl) { @@ -33,6 +34,6 @@ gt215_fb_oclass = &(struct nv50_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = >215_ram_oclass, + .base.ram_new = gt215_ram_new, .trap = 0x000d0fff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c index 7be4a47ef4ad..3caed0f12a77 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "nv50.h" +#include "ram.h" struct nvkm_oclass * mcp77_fb_oclass = &(struct nv50_fb_impl) { @@ -33,6 +34,6 @@ mcp77_fb_oclass = &(struct nv50_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &mcp77_ram_oclass, + .base.ram_new = mcp77_ram_new, .trap = 0x001d07ff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c index 2d00656faef5..3ff0bf9cefd2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "nv50.h" +#include "ram.h" struct nvkm_oclass * mcp89_fb_oclass = &(struct nv50_fb_impl) { @@ -33,6 +34,6 @@ mcp89_fb_oclass = &(struct nv50_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &mcp77_ram_oclass, + .base.ram_new = mcp77_ram_new, .trap = 0x089d1fff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index 7fb578fb8a57..8c8b4b35930d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "nv04.h" +#include "ram.h" #include "regsnv04.h" bool @@ -84,5 +85,5 @@ nv04_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv04_ram_oclass, + .base.ram_new = nv04_ram_new, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index a52cc6c718c2..a51c094df579 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" void nv10_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, @@ -63,7 +64,7 @@ nv10_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv10_ram_oclass, + .base.ram_new = nv10_ram_new, .tile.regions = 8, .tile.init = nv10_fb_tile_init, .tile.fini = nv10_fb_tile_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c index 83bcb73caf0a..e56b93d593c5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" struct nvkm_oclass * nv1a_fb_oclass = &(struct nv04_fb_impl) { @@ -35,7 +36,7 @@ nv1a_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv1a_ram_oclass, + .base.ram_new = nv1a_ram_new, .tile.regions = 8, .tile.init = nv10_fb_tile_init, .tile.fini = nv10_fb_tile_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index f1f3fe5ad46a..ada818ac1735 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" void nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, @@ -44,7 +45,7 @@ nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -62,7 +63,7 @@ nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) tile->limit = 0; tile->pitch = 0; tile->zcomp = 0; - nvkm_mm_free(&fb->tags, &tile->tag); + nvkm_mm_free(&fb->ram->tags, &tile->tag); } void @@ -86,7 +87,7 @@ nv20_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv20_ram_oclass, + .base.ram_new = nv20_ram_new, .tile.regions = 8, .tile.init = nv20_fb_tile_init, .tile.comp = nv20_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index 90b17004ffb2..31dc7cf3aa0c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" static void nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, @@ -31,7 +32,7 @@ nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -51,7 +52,7 @@ nv25_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv20_ram_oclass, + .base.ram_new = nv20_ram_new, .tile.regions = 8, .tile.init = nv20_fb_tile_init, .tile.comp = nv25_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 3a6da4ee407a..6bddaac59ad8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" void nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, @@ -50,7 +51,7 @@ nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -130,7 +131,7 @@ nv30_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv20_ram_oclass, + .base.ram_new = nv20_ram_new, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv30_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index 7de68c6bea74..e4fd94d003aa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" static void nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, @@ -31,7 +32,7 @@ nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -52,7 +53,7 @@ nv35_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv20_ram_oclass, + .base.ram_new = nv20_ram_new, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv35_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index b78062fd6a3a..51b9b4a58930 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" static void nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, @@ -31,7 +32,7 @@ nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / fb->ram->parts, 0x40); - if (!nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -52,7 +53,7 @@ nv36_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv20_ram_oclass, + .base.ram_new = nv20_ram_new, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv36_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index fa02bcba36ca..fa1f8047714e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" void nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, @@ -32,7 +33,7 @@ nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, u32 tiles = DIV_ROUND_UP(size, 0x80); u32 tags = round_up(tiles / fb->ram->parts, 0x100); if ( (flags & 2) && - !nvkm_mm_head(&fb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + !nvkm_mm_head(&fb->ram->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; @@ -67,7 +68,7 @@ nv40_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv40_ram_oclass, + .base.ram_new = nv40_ram_new, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h deleted file mode 100644 index 602182661820..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef __NVKM_FB_NV40_H__ -#define __NVKM_FB_NV40_H__ -#include "priv.h" - -struct nv40_ram { - struct nvkm_ram base; - u32 ctrl; - u32 coef; -}; - -int nv40_ram_calc(struct nvkm_fb *, u32); -int nv40_ram_prog(struct nvkm_fb *); -void nv40_ram_tidy(struct nvkm_fb *); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index 568810536d6f..5e11dd8ab5c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" void nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) @@ -61,7 +62,7 @@ nv41_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv41_ram_oclass, + .base.ram_new = nv41_ram_new, .tile.regions = 12, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index 9b76716982e6..ffdf74b698a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" static void nv44_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, @@ -71,7 +72,7 @@ nv44_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv44_ram_oclass, + .base.ram_new = nv44_ram_new, .tile.regions = 12, .tile.init = nv44_fb_tile_init, .tile.fini = nv20_fb_tile_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index 1f8b69d375f9..c9685991042a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" void nv46_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, @@ -49,7 +50,7 @@ nv46_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv44_ram_oclass, + .base.ram_new = nv44_ram_new, .tile.regions = 15, .tile.init = nv46_fb_tile_init, .tile.fini = nv20_fb_tile_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c index d3b3988d1d49..f150f2df16dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" struct nvkm_oclass * nv47_fb_oclass = &(struct nv04_fb_impl) { @@ -35,7 +36,7 @@ nv47_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv41_ram_oclass, + .base.ram_new = nv41_ram_new, .tile.regions = 15, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c index 236e36c5054e..806c7851a164 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" struct nvkm_oclass * nv49_fb_oclass = &(struct nv04_fb_impl) { @@ -35,7 +36,7 @@ nv49_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv49_ram_oclass, + .base.ram_new = nv49_ram_new, .tile.regions = 15, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c index 1352b6a73fb0..6f24565c9774 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c @@ -24,6 +24,7 @@ * */ #include "nv04.h" +#include "ram.h" struct nvkm_oclass * nv4e_fb_oclass = &(struct nv04_fb_impl) { @@ -35,7 +36,7 @@ nv4e_fb_oclass = &(struct nv04_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, - .base.ram = &nv4e_ram_oclass, + .base.ram_new = nv4e_ram_new, .tile.regions = 12, .tile.init = nv46_fb_tile_init, .tile.fini = nv20_fb_tile_fini, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 1397e715dc14..072b0c3881df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include "nv50.h" +#include "ram.h" #include #include @@ -299,6 +300,6 @@ nv50_fb_oclass = &(struct nv50_fb_impl) { .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nv50_ram_oclass, + .base.ram_new = nv50_ram_new, .trap = 0x000707ff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index 002b95ae419d..92bfc3b9bb6d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -19,13 +19,5 @@ struct nv50_fb_impl { u32 trap; }; -#define nv50_ram_create(p,e,o,d) \ - nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) -int nv50_ram_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); -int nv50_ram_get(struct nvkm_fb *, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nvkm_mem **); -void nv50_ram_put(struct nvkm_fb *, struct nvkm_mem **); -void __nv50_ram_put(struct nvkm_fb *, struct nvkm_mem *); extern int nv50_fb_memtype[0x80]; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index 74eb9a22705b..f206152a3e63 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -3,42 +3,6 @@ #include struct nvkm_bios; -#define nvkm_ram_create(p,e,o,d) \ - nvkm_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d) -#define nvkm_ram_destroy(p) \ - nvkm_object_destroy(&(p)->base) -#define nvkm_ram_init(p) \ - nvkm_object_init(&(p)->base) -#define nvkm_ram_fini(p,s) \ - nvkm_object_fini(&(p)->base, (s)) - -#define nvkm_ram_create_(p,e,o,s,d) \ - nvkm_object_create_((p), (e), (o), 0, (s), (void **)d) -#define _nvkm_ram_dtor nvkm_object_destroy -#define _nvkm_ram_init nvkm_object_init -#define _nvkm_ram_fini nvkm_object_fini - -extern struct nvkm_oclass nv04_ram_oclass; -extern struct nvkm_oclass nv10_ram_oclass; -extern struct nvkm_oclass nv1a_ram_oclass; -extern struct nvkm_oclass nv20_ram_oclass; -extern struct nvkm_oclass nv40_ram_oclass; -extern struct nvkm_oclass nv41_ram_oclass; -extern struct nvkm_oclass nv44_ram_oclass; -extern struct nvkm_oclass nv49_ram_oclass; -extern struct nvkm_oclass nv4e_ram_oclass; -extern struct nvkm_oclass nv50_ram_oclass; -extern struct nvkm_oclass gt215_ram_oclass; -extern struct nvkm_oclass mcp77_ram_oclass; -extern struct nvkm_oclass gf100_ram_oclass; -extern struct nvkm_oclass gk104_ram_oclass; -extern struct nvkm_oclass gm107_ram_oclass; - -int nvkm_sddr2_calc(struct nvkm_ram *ram); -int nvkm_sddr3_calc(struct nvkm_ram *ram); -int nvkm_gddr3_calc(struct nvkm_ram *ram); -int nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts); - #define nvkm_fb_create(p,e,c,d) \ nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d) #define nvkm_fb_destroy(p) ({ \ @@ -62,7 +26,7 @@ int _nvkm_fb_fini(struct nvkm_object *, bool); struct nvkm_fb_impl { struct nvkm_oclass base; - struct nvkm_oclass *ram; + int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **); bool (*memtype)(struct nvkm_fb *, u32); }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c new file mode 100644 index 000000000000..c17d559dbfbe --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.c @@ -0,0 +1,100 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "ram.h" + +int +nvkm_ram_init(struct nvkm_ram *ram) +{ + if (ram->func->init) + return ram->func->init(ram); + return 0; +} + +void +nvkm_ram_del(struct nvkm_ram **pram) +{ + struct nvkm_ram *ram = *pram; + if (ram && !WARN_ON(!ram->func)) { + if (ram->func->dtor) + *pram = ram->func->dtor(ram); + nvkm_mm_fini(&ram->tags); + nvkm_mm_fini(&ram->vram); + kfree(*pram); + *pram = NULL; + } +} + +int +nvkm_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb, + enum nvkm_ram_type type, u64 size, u32 tags, + struct nvkm_ram *ram) +{ + static const char *name[] = { + [NVKM_RAM_TYPE_UNKNOWN] = "of unknown memory type", + [NVKM_RAM_TYPE_STOLEN ] = "stolen system memory", + [NVKM_RAM_TYPE_SGRAM ] = "SGRAM", + [NVKM_RAM_TYPE_SDRAM ] = "SDRAM", + [NVKM_RAM_TYPE_DDR1 ] = "DDR1", + [NVKM_RAM_TYPE_DDR2 ] = "DDR2", + [NVKM_RAM_TYPE_DDR3 ] = "DDR3", + [NVKM_RAM_TYPE_GDDR2 ] = "GDDR2", + [NVKM_RAM_TYPE_GDDR3 ] = "GDDR3", + [NVKM_RAM_TYPE_GDDR4 ] = "GDDR4", + [NVKM_RAM_TYPE_GDDR5 ] = "GDDR5", + }; + struct nvkm_subdev *subdev = &fb->subdev; + int ret; + + nvkm_info(subdev, "%d MiB %s\n", (int)(size >> 20), name[type]); + ram->func = func; + ram->fb = fb; + ram->type = type; + ram->size = size; + + if (!nvkm_mm_initialised(&ram->vram)) { + ret = nvkm_mm_init(&ram->vram, 0, size >> NVKM_RAM_MM_SHIFT, 1); + if (ret) + return ret; + } + + if (!nvkm_mm_initialised(&ram->tags)) { + ret = nvkm_mm_init(&ram->tags, 0, tags ? ++tags : 0, 1); + if (ret) + return ret; + + nvkm_debug(subdev, "%d compression tags\n", tags); + } + + return 0; +} + +int +nvkm_ram_new_(const struct nvkm_ram_func *func, struct nvkm_fb *fb, + enum nvkm_ram_type type, u64 size, u32 tags, + struct nvkm_ram **pram) +{ + if (!(*pram = kzalloc(sizeof(**pram), GFP_KERNEL))) + return -ENOMEM; + return nvkm_ram_ctor(func, fb, type, size, tags, *pram); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h new file mode 100644 index 000000000000..f816cbf2ced3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.h @@ -0,0 +1,50 @@ +#ifndef __NVKM_FB_RAM_PRIV_H__ +#define __NVKM_FB_RAM_PRIV_H__ +#include "priv.h" + +int nvkm_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *, + enum nvkm_ram_type, u64 size, u32 tags, + struct nvkm_ram *); +int nvkm_ram_new_(const struct nvkm_ram_func *, struct nvkm_fb *, + enum nvkm_ram_type, u64 size, u32 tags, + struct nvkm_ram **); +void nvkm_ram_del(struct nvkm_ram **); +int nvkm_ram_init(struct nvkm_ram *); + +extern const struct nvkm_ram_func nv04_ram_func; + +int nv50_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *, + struct nvkm_ram *); +int nv50_ram_get(struct nvkm_ram *, u64, u32, u32, u32, struct nvkm_mem **); +void nv50_ram_put(struct nvkm_ram *, struct nvkm_mem **); +void __nv50_ram_put(struct nvkm_ram *, struct nvkm_mem *); + +int gf100_ram_ctor(const struct nvkm_ram_func *, struct nvkm_fb *, + u32, struct nvkm_ram *); +int gf100_ram_get(struct nvkm_ram *, u64, u32, u32, u32, struct nvkm_mem **); +void gf100_ram_put(struct nvkm_ram *, struct nvkm_mem **); + +int gk104_ram_init(struct nvkm_ram *ram); + +/* RAM type-specific MR calculation routines */ +int nvkm_sddr2_calc(struct nvkm_ram *); +int nvkm_sddr3_calc(struct nvkm_ram *); +int nvkm_gddr3_calc(struct nvkm_ram *); +int nvkm_gddr5_calc(struct nvkm_ram *, bool nuts); + +int nv04_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv10_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv1a_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv20_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv40_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv41_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv44_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv49_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv4e_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int nv50_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int gt215_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int mcp77_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int gf100_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int gk104_ram_new(struct nvkm_fb *, struct nvkm_ram **); +int gm107_ram_new(struct nvkm_fb *, struct nvkm_ram **); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index af7aaabd2bb3..b579e910ef2d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -21,7 +21,8 @@ * * Authors: Ben Skeggs */ -#include "gf100.h" +#define gf100_ram(p) container_of((p), struct gf100_ram, base) +#include "ram.h" #include "ramfuc.h" #include @@ -107,7 +108,7 @@ static void gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic) { struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nvkm_fb *fb = nvkm_fb(ram); + struct nvkm_fb *fb = ram->base.fb; struct nvkm_device *device = fb->subdev.device; u32 part = nvkm_rd32(device, 0x022438), i; u32 mask = nvkm_rd32(device, 0x022554); @@ -124,14 +125,14 @@ gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic) } static int -gf100_ram_calc(struct nvkm_fb *fb, u32 freq) +gf100_ram_calc(struct nvkm_ram *base, u32 freq) { - struct nvkm_subdev *subdev = &fb->subdev; + struct gf100_ram *ram = gf100_ram(base); + struct gf100_ramfuc *fuc = &ram->fuc; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_device *device = subdev->device; struct nvkm_clk *clk = device->clk; struct nvkm_bios *bios = device->bios; - struct gf100_ram *ram = (void *)fb->ram; - struct gf100_ramfuc *fuc = &ram->fuc; struct nvbios_ramcfg cfg; u8 ver, cnt, len, strap; struct { @@ -152,7 +153,7 @@ gf100_ram_calc(struct nvkm_fb *fb, u32 freq) } /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(fb)); + strap = nvbios_ramcfg_index(subdev); if (strap >= cnt) { nvkm_error(subdev, "invalid ramcfg strap\n"); return -EINVAL; @@ -177,7 +178,7 @@ gf100_ram_calc(struct nvkm_fb *fb, u32 freq) timing.data = 0; } - ret = ram_init(fuc, fb); + ret = ram_init(fuc, ram->base.fb); if (ret) return ret; @@ -212,8 +213,8 @@ gf100_ram_calc(struct nvkm_fb *fb, u32 freq) if (mode == 1 && from == 0) { /* calculate refpll */ - ret = gt215_pll_calc(nv_subdev(fb), &ram->refpll, - ram->mempll.refclk, &N1, NULL, &M1, &P); + ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk, + &N1, NULL, &M1, &P); if (ret <= 0) { nvkm_error(subdev, "unable to calc refpll\n"); return ret ? ret : -ERANGE; @@ -227,7 +228,7 @@ gf100_ram_calc(struct nvkm_fb *fb, u32 freq) ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); /* calculate mempll */ - ret = gt215_pll_calc(nv_subdev(fb), &ram->mempll, freq, + ret = gt215_pll_calc(subdev, &ram->mempll, freq, &N1, NULL, &M1, &P); if (ret <= 0) { nvkm_error(subdev, "unable to calc refpll\n"); @@ -404,49 +405,48 @@ gf100_ram_calc(struct nvkm_fb *fb, u32 freq) } static int -gf100_ram_prog(struct nvkm_fb *fb) +gf100_ram_prog(struct nvkm_ram *base) { - struct nvkm_device *device = nv_device(fb); - struct gf100_ram *ram = (void *)fb->ram; - struct gf100_ramfuc *fuc = &ram->fuc; - ram_exec(fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); + struct gf100_ram *ram = gf100_ram(base); + struct nvkm_device *device = ram->base.fb->subdev.device; + ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -gf100_ram_tidy(struct nvkm_fb *fb) +gf100_ram_tidy(struct nvkm_ram *base) { - struct gf100_ram *ram = (void *)fb->ram; - struct gf100_ramfuc *fuc = &ram->fuc; - ram_exec(fuc, false); + struct gf100_ram *ram = gf100_ram(base); + ram_exec(&ram->fuc, false); } extern const u8 gf100_pte_storage_type_map[256]; void -gf100_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) +gf100_ram_put(struct nvkm_ram *ram, struct nvkm_mem **pmem) { - struct nvkm_ltc *ltc = nvkm_ltc(fb); + struct nvkm_ltc *ltc = ram->fb->subdev.device->ltc; struct nvkm_mem *mem = *pmem; *pmem = NULL; if (unlikely(mem == NULL)) return; - mutex_lock(&fb->subdev.mutex); + mutex_lock(&ram->fb->subdev.mutex); if (mem->tag) ltc->tags_free(ltc, &mem->tag); - __nv50_ram_put(fb, mem); - mutex_unlock(&fb->subdev.mutex); + __nv50_ram_put(ram, mem); + mutex_unlock(&ram->fb->subdev.mutex); kfree(mem); } int -gf100_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, +gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, u32 memtype, struct nvkm_mem **pmem) { - struct nvkm_mm *mm = &fb->vram; + struct nvkm_ltc *ltc = ram->fb->subdev.device->ltc; + struct nvkm_mm *mm = &ram->vram; struct nvkm_mm_node *r; struct nvkm_mem *mem; int type = (memtype & 0x0ff); @@ -454,9 +454,9 @@ gf100_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, const bool comp = gf100_pte_storage_type_map[type] != type; int ret; - size >>= 12; - align >>= 12; - ncmin >>= 12; + size >>= NVKM_RAM_MM_SHIFT; + align >>= NVKM_RAM_MM_SHIFT; + ncmin >>= NVKM_RAM_MM_SHIFT; if (!ncmin) ncmin = size; @@ -467,12 +467,10 @@ gf100_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, INIT_LIST_HEAD(&mem->regions); mem->size = size; - mutex_lock(&fb->subdev.mutex); + mutex_lock(&ram->fb->subdev.mutex); if (comp) { - struct nvkm_ltc *ltc = nvkm_ltc(fb); - /* compression only works with lpages */ - if (align == (1 << (17 - 12))) { + if (align == (1 << (17 - NVKM_RAM_MM_SHIFT))) { int n = size >> 5; ltc->tags_alloc(ltc, n, &mem->tag); } @@ -488,157 +486,158 @@ gf100_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, else ret = nvkm_mm_head(mm, 0, 1, size, ncmin, align, &r); if (ret) { - mutex_unlock(&fb->subdev.mutex); - fb->ram->put(fb, &mem); + mutex_unlock(&ram->fb->subdev.mutex); + ram->func->put(ram, &mem); return ret; } list_add_tail(&r->rl_entry, &mem->regions); size -= r->length; } while (size); - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&ram->fb->subdev.mutex); r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); - mem->offset = (u64)r->offset << 12; + mem->offset = (u64)r->offset << NVKM_RAM_MM_SHIFT; *pmem = mem; return 0; } +static int +gf100_ram_init(struct nvkm_ram *base) +{ + static const u8 train0[] = { + 0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc, + 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, + }; + static const u32 train1[] = { + 0x00000000, 0xffffffff, + 0x55555555, 0xaaaaaaaa, + 0x33333333, 0xcccccccc, + 0xf0f0f0f0, 0x0f0f0f0f, + 0x00ff00ff, 0xff00ff00, + 0x0000ffff, 0xffff0000, + }; + struct gf100_ram *ram = gf100_ram(base); + struct nvkm_device *device = ram->base.fb->subdev.device; + int i; + + switch (ram->base.type) { + case NVKM_RAM_TYPE_GDDR5: + break; + default: + return 0; + } + + /* prepare for ddr link training, and load training patterns */ + for (i = 0; i < 0x30; i++) { + nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8)); + nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8)); + nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]); + nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]); + nvkm_wr32(device, 0x10f918, train1[i % 12]); + nvkm_wr32(device, 0x10f91c, train1[i % 12]); + nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]); + nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]); + nvkm_wr32(device, 0x10f918, train1[i % 12]); + nvkm_wr32(device, 0x10f91c, train1[i % 12]); + } + + return 0; +} + +static const struct nvkm_ram_func +gf100_ram_func = { + .init = gf100_ram_init, + .get = gf100_ram_get, + .put = gf100_ram_put, + .calc = gf100_ram_calc, + .prog = gf100_ram_prog, + .tidy = gf100_ram_tidy, +}; + int -gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 maskaddr, int size, - void **pobject) +gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb, + u32 maskaddr, struct nvkm_ram *ram) { - struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_subdev *subdev = &fb->subdev; struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; - struct nvkm_ram *ram; - const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ - const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ + const u32 rsvd_head = ( 256 * 1024); /* vga memory */ + const u32 rsvd_tail = (1024 * 1024); /* vbios etc */ u32 parts = nvkm_rd32(device, 0x022438); u32 pmask = nvkm_rd32(device, maskaddr); - u32 bsize = nvkm_rd32(device, 0x10f20c); - u32 offset, length; + u64 bsize = (u64)nvkm_rd32(device, 0x10f20c) << 20; + u64 psize, size = 0; + enum nvkm_ram_type type = nvkm_fb_bios_memtype(bios); bool uniform = true; - int ret, part; - - ret = nvkm_ram_create_(parent, engine, oclass, size, pobject); - ram = *pobject; - if (ret) - return ret; + int ret, i; nvkm_debug(subdev, "100800: %08x\n", nvkm_rd32(device, 0x100800)); nvkm_debug(subdev, "parts %08x mask %08x\n", parts, pmask); - ram->type = nvkm_fb_bios_memtype(bios); - ram->ranks = (nvkm_rd32(device, 0x10f200) & 0x00000004) ? 2 : 1; - /* read amount of vram attached to each memory controller */ - for (part = 0; part < parts; part++) { - if (!(pmask & (1 << part))) { - u32 size = nvkm_rd32(device, 0x11020c + (part * 0x1000)); - if (size != bsize) { - if (size < bsize) - bsize = size; - uniform = false; - } - - nvkm_debug(subdev, "%d: size %08x\n", part, size); - ram->size += (u64)size << 20; + for (i = 0; i < parts; i++) { + if (pmask & (1 << i)) + continue; + + psize = (u64)nvkm_rd32(device, 0x11020c + (i * 0x1000)) << 20; + if (psize != bsize) { + if (psize < bsize) + bsize = psize; + uniform = false; } + + nvkm_debug(subdev, "%d: %d MiB\n", i, (u32)(psize >> 20)); + size += psize; } + ret = nvkm_ram_ctor(func, fb, type, size, 0, ram); + if (ret) + return ret; + + nvkm_mm_fini(&ram->vram); + /* if all controllers have the same amount attached, there's no holes */ if (uniform) { - offset = rsvd_head; - length = (ram->size >> 12) - rsvd_head - rsvd_tail; - ret = nvkm_mm_init(&fb->vram, offset, length, 1); + ret = nvkm_mm_init(&ram->vram, rsvd_head >> NVKM_RAM_MM_SHIFT, + (size - rsvd_head - rsvd_tail) >> + NVKM_RAM_MM_SHIFT, 1); + if (ret) + return ret; } else { /* otherwise, address lowest common amount from 0GiB */ - ret = nvkm_mm_init(&fb->vram, rsvd_head, - (bsize << 8) * parts - rsvd_head, 1); + ret = nvkm_mm_init(&ram->vram, rsvd_head >> NVKM_RAM_MM_SHIFT, + ((bsize * parts) - rsvd_head) >> + NVKM_RAM_MM_SHIFT, 1); if (ret) return ret; /* and the rest starting from (8GiB + common_size) */ - offset = (0x0200000000ULL >> 12) + (bsize << 8); - length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail; - - ret = nvkm_mm_init(&fb->vram, offset, length, 1); + ret = nvkm_mm_init(&ram->vram, (0x0200000000ULL + bsize) >> + NVKM_RAM_MM_SHIFT, + (size - (bsize * parts) - rsvd_tail) >> + NVKM_RAM_MM_SHIFT, 1); if (ret) - nvkm_mm_fini(&fb->vram); - } - - if (ret) - return ret; - - ram->get = gf100_ram_get; - ram->put = gf100_ram_put; - return 0; -} - -static int -gf100_ram_init(struct nvkm_object *object) -{ - struct nvkm_fb *fb = (void *)object->parent; - struct nvkm_device *device = fb->subdev.device; - struct gf100_ram *ram = (void *)object; - int ret, i; - - ret = nvkm_ram_init(&ram->base); - if (ret) - return ret; - - /* prepare for ddr link training, and load training patterns */ - switch (ram->base.type) { - case NV_MEM_TYPE_GDDR5: { - static const u8 train0[] = { - 0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc, - 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, - }; - static const u32 train1[] = { - 0x00000000, 0xffffffff, - 0x55555555, 0xaaaaaaaa, - 0x33333333, 0xcccccccc, - 0xf0f0f0f0, 0x0f0f0f0f, - 0x00ff00ff, 0xff00ff00, - 0x0000ffff, 0xffff0000, - }; - - for (i = 0; i < 0x30; i++) { - nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8)); - nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8)); - nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]); - nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]); - nvkm_wr32(device, 0x10f918, train1[i % 12]); - nvkm_wr32(device, 0x10f91c, train1[i % 12]); - nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]); - nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]); - nvkm_wr32(device, 0x10f918, train1[i % 12]); - nvkm_wr32(device, 0x10f91c, train1[i % 12]); - } - } break; - default: - break; + return ret; } + ram->ranks = (nvkm_rd32(device, 0x10f200) & 0x00000004) ? 2 : 1; return 0; } -static int -gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_subdev *subdev = &fb->subdev; struct nvkm_bios *bios = subdev->device->bios; struct gf100_ram *ram; int ret; - ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); - *pobject = nv_object(ram); + if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) + return -ENOMEM; + *pram = &ram->base; + + ret = gf100_ram_ctor(&gf100_ram_func, fb, 0x022554, &ram->base); if (ret) return ret; @@ -654,17 +653,6 @@ gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; } - switch (ram->base.type) { - case NV_MEM_TYPE_GDDR5: - ram->base.calc = gf100_ram_calc; - ram->base.prog = gf100_ram_prog; - ram->base.tidy = gf100_ram_tidy; - break; - default: - nvkm_warn(subdev, "reclocking of this ram type unsupported\n"); - return 0; - } - ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20); ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24); ram->fuc.r_0x137320 = ramfuc_reg(0x137320); @@ -725,14 +713,3 @@ gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4); return 0; } - -struct nvkm_oclass -gf100_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_ram_ctor, - .dtor = _nvkm_ram_dtor, - .init = gf100_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 000f45c0f838..28cd633db0f0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -21,8 +21,9 @@ * * Authors: Ben Skeggs */ +#define gk104_ram(p) container_of((p), struct gk104_ram, base) +#include "ram.h" #include "ramfuc.h" -#include "gf100.h" #include #include @@ -228,7 +229,7 @@ static void gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, u32 _mask, u32 _data, u32 _copy) { - struct nvkm_fb *fb = nvkm_fb(ram); + struct nvkm_fb *fb = ram->base.fb; struct ramfuc *fuc = &ram->fuc.base; struct nvkm_device *device = fb->subdev.device; u32 addr = 0x110000 + (reg->addr & 0xfff); @@ -248,9 +249,8 @@ gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) static int -gk104_ram_calc_gddr5(struct nvkm_fb *fb, u32 freq) +gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) { - struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; struct nvkm_ram_data *next = ram->base.next; int vc = !next->bios.ramcfg_11_02_08; @@ -674,9 +674,8 @@ gk104_ram_calc_gddr5(struct nvkm_fb *fb, u32 freq) ******************************************************************************/ static int -gk104_ram_calc_sddr3(struct nvkm_fb *fb, u32 freq) +gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) { - struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; @@ -926,9 +925,9 @@ gk104_ram_calc_sddr3(struct nvkm_fb *fb, u32 freq) ******************************************************************************/ static int -gk104_ram_calc_data(struct nvkm_fb *fb, u32 khz, struct nvkm_ram_data *data) +gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data) { - struct gk104_ram *ram = (void *)fb->ram; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_ram_data *cfg; u32 mhz = khz / 1000; @@ -941,20 +940,19 @@ gk104_ram_calc_data(struct nvkm_fb *fb, u32 khz, struct nvkm_ram_data *data) } } - nvkm_error(&fb->subdev, "ramcfg data for %dMHz not found\n", mhz); + nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz); return -EINVAL; } static int -gk104_ram_calc_xits(struct nvkm_fb *fb, struct nvkm_ram_data *next) +gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next) { - struct gk104_ram *ram = (void *)fb->ram; struct gk104_ramfuc *fuc = &ram->fuc; - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; int refclk, i; int ret; - ret = ram_init(fuc, fb); + ret = ram_init(fuc, ram->base.fb); if (ret) return ret; @@ -974,7 +972,7 @@ gk104_ram_calc_xits(struct nvkm_fb *fb, struct nvkm_ram_data *next) refclk = fuc->mempll.refclk; /* calculate refpll coefficients */ - ret = gt215_pll_calc(nv_subdev(fb), &fuc->refpll, refclk, &ram->N1, + ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1, &ram->fN1, &ram->M1, &ram->P1); fuc->mempll.refclk = ret; if (ret <= 0) { @@ -991,7 +989,7 @@ gk104_ram_calc_xits(struct nvkm_fb *fb, struct nvkm_ram_data *next) fuc->mempll.min_p = 1; fuc->mempll.max_p = 2; - ret = gt215_pll_calc(nv_subdev(fb), &fuc->mempll, next->freq, + ret = gt215_pll_calc(subdev, &fuc->mempll, next->freq, &ram->N2, NULL, &ram->M2, &ram->P2); if (ret <= 0) { nvkm_error(subdev, "unable to calc mempll\n"); @@ -1006,15 +1004,15 @@ gk104_ram_calc_xits(struct nvkm_fb *fb, struct nvkm_ram_data *next) ram->base.freq = next->freq; switch (ram->base.type) { - case NV_MEM_TYPE_DDR3: + case NVKM_RAM_TYPE_DDR3: ret = nvkm_sddr3_calc(&ram->base); if (ret == 0) - ret = gk104_ram_calc_sddr3(fb, next->freq); + ret = gk104_ram_calc_sddr3(ram, next->freq); break; - case NV_MEM_TYPE_GDDR5: + case NVKM_RAM_TYPE_GDDR5: ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); if (ret == 0) - ret = gk104_ram_calc_gddr5(fb, next->freq); + ret = gk104_ram_calc_gddr5(ram, next->freq); break; default: ret = -ENOSYS; @@ -1025,21 +1023,21 @@ gk104_ram_calc_xits(struct nvkm_fb *fb, struct nvkm_ram_data *next) } static int -gk104_ram_calc(struct nvkm_fb *fb, u32 freq) +gk104_ram_calc(struct nvkm_ram *base, u32 freq) { - struct nvkm_clk *clk = nvkm_clk(fb); - struct gk104_ram *ram = (void *)fb->ram; + struct gk104_ram *ram = gk104_ram(base); + struct nvkm_clk *clk = ram->base.fb->subdev.device->clk; struct nvkm_ram_data *xits = &ram->base.xition; struct nvkm_ram_data *copy; int ret; if (ram->base.next == NULL) { - ret = gk104_ram_calc_data(fb, clk->read(clk, nv_clk_src_mem), + ret = gk104_ram_calc_data(ram, clk->read(clk, nv_clk_src_mem), &ram->base.former); if (ret) return ret; - ret = gk104_ram_calc_data(fb, freq, &ram->base.target); + ret = gk104_ram_calc_data(ram, freq, &ram->base.target); if (ret) return ret; @@ -1063,14 +1061,13 @@ gk104_ram_calc(struct nvkm_fb *fb, u32 freq) ram->base.next = &ram->base.target; } - return gk104_ram_calc_xits(fb, ram->base.next); + return gk104_ram_calc_xits(ram, ram->base.next); } static void -gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq) +gk104_ram_prog_0(struct gk104_ram *ram, u32 freq) { - struct nvkm_device *device = fb->subdev.device; - struct gk104_ram *ram = (void *)fb->ram; + struct nvkm_device *device = ram->base.fb->subdev.device; struct nvkm_ram_data *cfg; u32 mhz = freq / 1000; u32 mask, data; @@ -1144,11 +1141,11 @@ gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq) } static int -gk104_ram_prog(struct nvkm_fb *fb) +gk104_ram_prog(struct nvkm_ram *base) { - struct nvkm_device *device = nv_device(fb); - struct gk104_ram *ram = (void *)fb->ram; + struct gk104_ram *ram = gk104_ram(base); struct gk104_ramfuc *fuc = &ram->fuc; + struct nvkm_device *device = ram->base.fb->subdev.device; struct nvkm_ram_data *next = ram->base.next; if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) { @@ -1156,20 +1153,19 @@ gk104_ram_prog(struct nvkm_fb *fb) return (ram->base.next == &ram->base.xition); } - gk104_ram_prog_0(fb, 1000); + gk104_ram_prog_0(ram, 1000); ram_exec(fuc, true); - gk104_ram_prog_0(fb, next->freq); + gk104_ram_prog_0(ram, next->freq); return (ram->base.next == &ram->base.xition); } static void -gk104_ram_tidy(struct nvkm_fb *fb) +gk104_ram_tidy(struct nvkm_ram *base) { - struct gk104_ram *ram = (void *)fb->ram; - struct gk104_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = gk104_ram(base); ram->base.next = NULL; - ram_exec(fuc, false); + ram_exec(&ram->fuc, false); } struct gk104_ram_train { @@ -1185,10 +1181,10 @@ struct gk104_ram_train { }; static int -gk104_ram_train_type(struct nvkm_fb *fb, int i, u8 ramcfg, +gk104_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg, struct gk104_ram_train *train) { - struct nvkm_bios *bios = nvkm_bios(fb); + struct nvkm_bios *bios = ram->fb->subdev.device->bios; struct nvbios_M0205E M0205E; struct nvbios_M0205S M0205S; struct nvbios_M0209E M0209E; @@ -1246,9 +1242,9 @@ gk104_ram_train_type(struct nvkm_fb *fb, int i, u8 ramcfg, } static int -gk104_ram_train_init_0(struct nvkm_fb *fb, struct gk104_ram_train *train) +gk104_ram_train_init_0(struct nvkm_ram *ram, struct gk104_ram_train *train) { - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->fb->subdev; struct nvkm_device *device = subdev->device; int i, j; @@ -1282,9 +1278,9 @@ gk104_ram_train_init_0(struct nvkm_fb *fb, struct gk104_ram_train *train) } static int -gk104_ram_train_init(struct nvkm_fb *fb) +gk104_ram_train_init(struct nvkm_ram *ram) { - u8 ramcfg = nvbios_ramcfg_index(nv_subdev(fb)); + u8 ramcfg = nvbios_ramcfg_index(&ram->fb->subdev); struct gk104_ram_train *train; int ret, i; @@ -1292,14 +1288,14 @@ gk104_ram_train_init(struct nvkm_fb *fb) return -ENOMEM; for (i = 0; i < 0x100; i++) { - ret = gk104_ram_train_type(fb, i, ramcfg, train); + ret = gk104_ram_train_type(ram, i, ramcfg, train); if (ret && ret != -ENOENT) break; } - switch (fb->ram->type) { - case NV_MEM_TYPE_GDDR5: - ret = gk104_ram_train_init_0(fb, train); + switch (ram->type) { + case NVKM_RAM_TYPE_GDDR5: + ret = gk104_ram_train_init_0(ram, train); break; default: ret = 0; @@ -1311,19 +1307,14 @@ gk104_ram_train_init(struct nvkm_fb *fb) } int -gk104_ram_init(struct nvkm_object *object) +gk104_ram_init(struct nvkm_ram *ram) { - struct nvkm_fb *fb = (void *)object->parent; - struct gk104_ram *ram = (void *)object; - struct nvkm_device *device = fb->subdev.device; + struct nvkm_subdev *subdev = &ram->fb->subdev; + struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; u8 ver, hdr, cnt, len, snr, ssz; u32 data, save; - int ret, i; - - ret = nvkm_ram_init(&ram->base); - if (ret) - return ret; + int i; /* run a bunch of tables from rammap table. there's actually * individual pointers for each rammap entry too, but, nvidia @@ -1347,7 +1338,7 @@ gk104_ram_init(struct nvkm_object *object) if (i != save >> 4) { nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4); nvbios_exec(&(struct nvbios_init) { - .subdev = nv_subdev(fb), + .subdev = subdev, .bios = bios, .offset = nvbios_rd32(bios, data), .execute = 1, @@ -1359,14 +1350,13 @@ gk104_ram_init(struct nvkm_object *object) nvkm_wr32(device, 0x10ecc0, 0xffffffff); nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010); - return gk104_ram_train_init(fb); + return gk104_ram_train_init(ram); } static int gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) { - struct nvkm_fb *fb = (void *)nv_object(ram)->parent; - struct nvkm_bios *bios = nvkm_bios(fb); + struct nvkm_bios *bios = ram->base.fb->subdev.device->bios; struct nvkm_ram_data *cfg; struct nvbios_ramcfg *d = &ram->diff; struct nvbios_ramcfg *p, *n; @@ -1432,25 +1422,33 @@ done: return ret; } -static void -gk104_ram_dtor(struct nvkm_object *object) +static void * +gk104_ram_dtor(struct nvkm_ram *base) { - struct gk104_ram *ram = (void *)object; + struct gk104_ram *ram = gk104_ram(base); struct nvkm_ram_data *cfg, *tmp; list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { kfree(cfg); } - nvkm_ram_destroy(&ram->base); + return ram; } -static int -gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_ram_func +gk104_ram_func = { + .dtor = gk104_ram_dtor, + .init = gk104_ram_init, + .get = gf100_ram_get, + .put = gf100_ram_put, + .calc = gk104_ram_calc, + .prog = gk104_ram_prog, + .tidy = gk104_ram_tidy, +}; + +int +gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_subdev *subdev = &fb->subdev; struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; @@ -1461,25 +1459,16 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, u8 ramcfg = nvbios_ramcfg_index(nv_subdev(fb)); u32 tmp; - ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); - *pobject = nv_object(ram); + if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) + return -ENOMEM; + *pram = &ram->base; + + ret = gf100_ram_ctor(&gk104_ram_func, fb, 0x022554, &ram->base); if (ret) return ret; INIT_LIST_HEAD(&ram->cfg); - switch (ram->base.type) { - case NV_MEM_TYPE_DDR3: - case NV_MEM_TYPE_GDDR5: - ram->base.calc = gk104_ram_calc; - ram->base.prog = gk104_ram_prog; - ram->base.tidy = gk104_ram_tidy; - break; - default: - nvkm_warn(subdev, "reclocking of this RAM type is unsupported\n"); - break; - } - /* calculate a mask of differently configured memory partitions, * because, of course reclocking wasn't complicated enough * already without having to treat some of them differently to @@ -1596,7 +1585,7 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); switch (ram->base.type) { - case NV_MEM_TYPE_GDDR5: + case NVKM_RAM_TYPE_GDDR5: ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); ram->fuc.r_mr[1] = ramfuc_reg(0x10f330); ram->fuc.r_mr[2] = ramfuc_reg(0x10f334); @@ -1608,7 +1597,7 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ram->fuc.r_mr[8] = ramfuc_reg(0x10f354); ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c); break; - case NV_MEM_TYPE_DDR3: + case NVKM_RAM_TYPE_DDR3: ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); break; @@ -1634,14 +1623,3 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, ram->fuc.r_0x100750 = ramfuc_reg(0x100750); return 0; } - -struct nvkm_oclass -gk104_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_ram_ctor, - .dtor = gk104_ram_dtor, - .init = gk104_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c index 40079eb44e70..43d807f6ca71 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c @@ -21,31 +21,20 @@ * * Authors: Ben Skeggs */ -#include "gf100.h" +#include "ram.h" -static int -gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_ram *ram; - int ret; +static const struct nvkm_ram_func +gm107_ram_func = { + .init = gk104_ram_init, + .get = gf100_ram_get, + .put = gf100_ram_put, +}; - ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; +int +gm107_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) +{ + if (!(*pram = kzalloc(sizeof(**pram), GFP_KERNEL))) + return -ENOMEM; - return 0; + return gf100_ram_ctor(&gm107_ram_func, fb, 0x021c14, *pram); } - -struct nvkm_oclass -gm107_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gm107_ram_ctor, - .dtor = _nvkm_ram_dtor, - .init = gk104_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index 660079bb4cd4..2cfedc0e1592 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -22,9 +22,9 @@ * Authors: Ben Skeggs * Roy Spliet */ - +#define gt215_ram(p) container_of((p), struct gt215_ram, base) +#include "ram.h" #include "ramfuc.h" -#include "nv50.h" #include #include @@ -153,12 +153,11 @@ gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) * Link training for (at least) DDR3 */ int -gt215_link_train(struct nvkm_fb *fb) +gt215_link_train(struct gt215_ram *ram) { - struct gt215_ram *ram = (void *)fb->ram; struct gt215_ltrain *train = &ram->ltrain; struct gt215_ramfuc *fuc = &ram->fuc; - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; struct nvkm_clk *clk = device->clk; @@ -194,7 +193,7 @@ gt215_link_train(struct nvkm_fb *fb) goto out; /* First: clock up/down */ - ret = ram->base.calc(fb, (u32) M0205T.freq * 1000); + ret = ram->base.func->calc(&ram->base, (u32) M0205T.freq * 1000); if (ret) goto out; @@ -237,7 +236,7 @@ gt215_link_train(struct nvkm_fb *fb) ram_exec(fuc, true); - ram->base.calc(fb, clk_current); + ram->base.func->calc(&ram->base, clk_current); ram_exec(fuc, true); /* Post-processing, avoids flicker */ @@ -246,7 +245,7 @@ gt215_link_train(struct nvkm_fb *fb) gt215_clk_post(clk, f); - ram_train_result(fb, result, 64); + ram_train_result(ram->base.fb, result, 64); for (i = 0; i < 64; i++) nvkm_debug(subdev, "Train: %08x", result[i]); gt215_link_train_calc(result, train); @@ -272,7 +271,7 @@ out: } int -gt215_link_train_init(struct nvkm_fb *fb) +gt215_link_train_init(struct gt215_ram *ram) { static const u32 pattern[16] = { 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, @@ -280,10 +279,9 @@ gt215_link_train_init(struct nvkm_fb *fb) 0x33333333, 0x55555555, 0x77777777, 0x66666666, 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, }; - struct nvkm_device *device = fb->subdev.device; - struct nvkm_bios *bios = device->bios; - struct gt215_ram *ram = (void *)fb->ram; struct gt215_ltrain *train = &ram->ltrain; + struct nvkm_device *device = ram->base.fb->subdev.device; + struct nvkm_bios *bios = device->bios; struct nvkm_mem *mem; struct nvbios_M0205E M0205E; u8 ver, hdr, cnt, len; @@ -302,7 +300,8 @@ gt215_link_train_init(struct nvkm_fb *fb) train->state = NVA3_TRAIN_ONCE; - ret = fb->ram->get(fb, 0x8000, 0x10000, 0, 0x800, &ram->ltrain.mem); + ret = ram->base.func->get(&ram->base, 0x8000, 0x10000, 0, 0x800, + &ram->ltrain.mem); if (ret) return ret; @@ -338,12 +337,10 @@ gt215_link_train_init(struct nvkm_fb *fb) } void -gt215_link_train_fini(struct nvkm_fb *fb) +gt215_link_train_fini(struct gt215_ram *ram) { - struct gt215_ram *ram = (void *)fb->ram; - if (ram->ltrain.mem) - fb->ram->put(fb, &ram->ltrain.mem); + ram->base.func->put(&ram->base, &ram->ltrain.mem); } /* @@ -351,11 +348,10 @@ gt215_link_train_fini(struct nvkm_fb *fb) */ #define T(t) cfg->timing_10_##t static int -gt215_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) +gt215_ram_timing_calc(struct gt215_ram *ram, u32 *timing) { - struct gt215_ram *ram = (void *)fb->ram; struct nvbios_ramcfg *cfg = &ram->base.target.bios; - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_device *device = subdev->device; int tUNK_base, tUNK_40_0, prevCL; u32 cur2, cur3, cur7, cur8; @@ -367,10 +363,10 @@ gt215_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) switch ((!T(CWL)) * ram->base.type) { - case NV_MEM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR2: T(CWL) = T(CL) - 1; break; - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; break; } @@ -408,8 +404,8 @@ gt215_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) timing[8] = cur8 & 0xffffff00; switch (ram->base.type) { - case NV_MEM_TYPE_DDR2: - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_DDR2: + case NVKM_RAM_TYPE_GDDR3: tUNK_40_0 = prevCL - (cur8 & 0xff); if (tUNK_40_0 > 0) timing[8] |= T(CL); @@ -493,12 +489,12 @@ gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) } static int -gt215_ram_calc(struct nvkm_fb *fb, u32 freq) +gt215_ram_calc(struct nvkm_ram *base, u32 freq) { - struct gt215_ram *ram = (void *)fb->ram; + struct gt215_ram *ram = gt215_ram(base); struct gt215_ramfuc *fuc = &ram->fuc; struct gt215_ltrain *train = &ram->ltrain; - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; struct gt215_clk_info mclk; @@ -516,7 +512,7 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) ram->base.next = next; if (ram->ltrain.state == NVA3_TRAIN_ONCE) - gt215_link_train(fb); + gt215_link_train(ram); /* lookup memory config data relevant to the target frequency */ data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len, @@ -527,7 +523,7 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) } /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(fb)); + strap = nvbios_ramcfg_index(subdev); if (strap >= cnt) { nvkm_error(subdev, "invalid ramcfg strap\n"); return -EINVAL; @@ -551,15 +547,15 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) } } - ret = gt215_pll_info(nvkm_clk(fb), 0x12, 0x4000, freq, &mclk); + ret = gt215_pll_info(device->clk, 0x12, 0x4000, freq, &mclk); if (ret < 0) { nvkm_error(subdev, "failed mclk calculation\n"); return ret; } - gt215_ram_timing_calc(fb, timing); + gt215_ram_timing_calc(ram, timing); - ret = ram_init(fuc, fb); + ret = ram_init(fuc, ram->base.fb); if (ret) return ret; @@ -569,13 +565,13 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) ram->base.mr[2] = ram_rd32(fuc, mr[2]); switch (ram->base.type) { - case NV_MEM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR2: ret = nvkm_sddr2_calc(&ram->base); break; - case NV_MEM_TYPE_DDR3: + case NVKM_RAM_TYPE_DDR3: ret = nvkm_sddr3_calc(&ram->base); break; - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: ret = nvkm_gddr3_calc(&ram->base); break; default: @@ -630,7 +626,7 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) ram_nsec(fuc, 2000); if (!next->bios.ramcfg_10_02_10) { - if (ram->base.type == NV_MEM_TYPE_GDDR3) + if (ram->base.type == NVKM_RAM_TYPE_GDDR3) ram_mask(fuc, 0x111100, 0x04020000, 0x00020000); else ram_mask(fuc, 0x111100, 0x04020000, 0x04020000); @@ -638,10 +634,10 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) /* If we're disabling the DLL, do it now */ switch (next->bios.ramcfg_DLLoff * ram->base.type) { - case NV_MEM_TYPE_DDR3: + case NVKM_RAM_TYPE_DDR3: nvkm_sddr3_dll_disable(fuc, ram->base.mr); break; - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: nvkm_gddr3_dll_disable(fuc, ram->base.mr); break; } @@ -657,7 +653,7 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) ram_wr32(fuc, 0x1002dc, 0x00000001); ram_nsec(fuc, 2000); - if (nv_device(fb)->chipset == 0xa3 && freq <= 500000) + if (device->chipset == 0xa3 && freq <= 500000) ram_mask(fuc, 0x100700, 0x00000006, 0x00000006); /* Fiddle with clocks */ @@ -715,7 +711,7 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) ram_mask(fuc, 0x1007e0, 0x22222222, r100760); } - if (nv_device(fb)->chipset == 0xa3 && freq > 500000) { + if (device->chipset == 0xa3 && freq > 500000) { ram_mask(fuc, 0x100700, 0x00000006, 0x00000000); } @@ -759,11 +755,11 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) if (next->bios.ramcfg_10_02_04) { switch (ram->base.type) { - case NV_MEM_TYPE_DDR3: - if (nv_device(fb)->chipset != 0xa8) + case NVKM_RAM_TYPE_DDR3: + if (device->chipset != 0xa8) r111100 |= 0x00000004; /* no break */ - case NV_MEM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR2: r111100 |= 0x08000000; break; default: @@ -771,12 +767,12 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) } } else { switch (ram->base.type) { - case NV_MEM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR2: r111100 |= 0x1a800000; unk714 |= 0x00000010; break; - case NV_MEM_TYPE_DDR3: - if (nv_device(fb)->chipset == 0xa8) { + case NVKM_RAM_TYPE_DDR3: + if (device->chipset == 0xa8) { r111100 |= 0x08000000; } else { r111100 &= ~0x00000004; @@ -784,7 +780,7 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) } unk714 |= 0x00000010; break; - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: r111100 |= 0x30000000; unk714 |= 0x00000020; break; @@ -820,13 +816,13 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) if (!next->bios.ramcfg_DLLoff) nvkm_sddr2_dll_reset(fuc); - if (ram->base.type == NV_MEM_TYPE_GDDR3) { + if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { ram_nsec(fuc, 31000); } else { ram_nsec(fuc, 14000); } - if (ram->base.type == NV_MEM_TYPE_DDR3) { + if (ram->base.type == NVKM_RAM_TYPE_DDR3) { ram_wr32(fuc, 0x100264, 0x1); ram_nsec(fuc, 2000); } @@ -862,11 +858,11 @@ gt215_ram_calc(struct nvkm_fb *fb, u32 freq) } static int -gt215_ram_prog(struct nvkm_fb *fb) +gt215_ram_prog(struct nvkm_ram *base) { - struct nvkm_device *device = nv_device(fb); - struct gt215_ram *ram = (void *)fb->ram; + struct gt215_ram *ram = gt215_ram(base); struct gt215_ramfuc *fuc = &ram->fuc; + struct nvkm_device *device = ram->base.fb->subdev.device; bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true); if (exec) { @@ -887,70 +883,56 @@ gt215_ram_prog(struct nvkm_fb *fb) } static void -gt215_ram_tidy(struct nvkm_fb *fb) +gt215_ram_tidy(struct nvkm_ram *base) { - struct gt215_ram *ram = (void *)fb->ram; - struct gt215_ramfuc *fuc = &ram->fuc; - ram_exec(fuc, false); + struct gt215_ram *ram = gt215_ram(base); + ram_exec(&ram->fuc, false); } static int -gt215_ram_init(struct nvkm_object *object) +gt215_ram_init(struct nvkm_ram *base) { - struct nvkm_fb *fb = (void *)object->parent; - struct gt215_ram *ram = (void *)object; - int ret; - - ret = nvkm_ram_init(&ram->base); - if (ret) - return ret; - - gt215_link_train_init(fb); + struct gt215_ram *ram = gt215_ram(base); + gt215_link_train_init(ram); return 0; } -static int -gt215_ram_fini(struct nvkm_object *object, bool suspend) +static void * +gt215_ram_dtor(struct nvkm_ram *base) { - struct nvkm_fb *fb = (void *)object->parent; - - if (!suspend) - gt215_link_train_fini(fb); - - return 0; + struct gt215_ram *ram = gt215_ram(base); + gt215_link_train_fini(ram); + return ram; } -static int -gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 datasize, - struct nvkm_object **pobject) +static const struct nvkm_ram_func +gt215_ram_func = { + .dtor = gt215_ram_dtor, + .init = gt215_ram_init, + .get = nv50_ram_get, + .put = nv50_ram_put, + .calc = gt215_ram_calc, + .prog = gt215_ram_prog, + .tidy = gt215_ram_tidy, +}; + +int +gt215_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_subdev *subdev = &fb->subdev; - struct nvkm_gpio *gpio = subdev->device->gpio; + struct nvkm_gpio *gpio = fb->subdev.device->gpio; struct dcb_gpio_func func; struct gt215_ram *ram; - int ret, i; u32 reg, shift; + int ret, i; + + if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) + return -ENOMEM; + *pram = &ram->base; - ret = nv50_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); + ret = nv50_ram_ctor(>215_ram_func, fb, &ram->base); if (ret) return ret; - switch (ram->base.type) { - case NV_MEM_TYPE_DDR2: - case NV_MEM_TYPE_DDR3: - case NV_MEM_TYPE_GDDR3: - ram->base.calc = gt215_ram_calc; - ram->base.prog = gt215_ram_prog; - ram->base.tidy = gt215_ram_tidy; - break; - default: - nvkm_warn(subdev, "reclocking of this ram type unsupported\n"); - return 0; - } - ram->fuc.r_0x001610 = ramfuc_reg(0x001610); ram->fuc.r_0x001700 = ramfuc_reg(0x001700); ram->fuc.r_0x002504 = ramfuc_reg(0x002504); @@ -1008,13 +990,3 @@ gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } - -struct nvkm_oclass -gt215_ram_oclass = { - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gt215_ram_ctor, - .dtor = _nvkm_ram_dtor, - .init = gt215_ram_init, - .fini = gt215_ram_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c index e1d82ab25dbc..0a0e44b75577 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c @@ -21,7 +21,8 @@ * * Authors: Ben Skeggs */ -#include "nv50.h" +#define mcp77_ram(p) container_of((p), struct mcp77_ram, base) +#include "ram.h" struct mcp77_ram { struct nvkm_ram base; @@ -29,56 +30,13 @@ struct mcp77_ram { }; static int -mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 datasize, - struct nvkm_object **pobject) +mcp77_ram_init(struct nvkm_ram *base) { - u32 rsvd_head = ( 256 * 1024); /* vga memory */ - u32 rsvd_tail = (1024 * 1024); /* vbios etc */ - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_device *device = fb->subdev.device; - struct mcp77_ram *ram; - int ret; - - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(fb); - if (ret) - return ret; - - ram->base.type = NV_MEM_TYPE_STOLEN; - ram->base.stolen = (u64)nvkm_rd32(device, 0x100e10) << 12; - ram->base.size = (u64)nvkm_rd32(device, 0x100e14) << 12; - - rsvd_tail += 0x1000; - ram->poller_base = ram->base.size - rsvd_tail; - - ret = nvkm_mm_init(&fb->vram, rsvd_head >> 12, - (ram->base.size - (rsvd_head + rsvd_tail)) >> 12, - 1); - if (ret) - return ret; - - ram->base.get = nv50_ram_get; - ram->base.put = nv50_ram_put; - return 0; -} - -static int -mcp77_ram_init(struct nvkm_object *object) -{ - struct nvkm_fb *fb = nvkm_fb(object); - struct nvkm_device *device = fb->subdev.device; - struct mcp77_ram *ram = (void *)object; - int ret; - u64 dniso, hostnb, flush; - - ret = nvkm_ram_init(&ram->base); - if (ret) - return ret; - - dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; - hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; - flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; + struct mcp77_ram *ram = mcp77_ram(base); + struct nvkm_device *device = ram->base.fb->subdev.device; + u32 dniso = ((ram->base.size - (ram->poller_base + 0x00)) >> 5) - 1; + u32 hostnb = ((ram->base.size - (ram->poller_base + 0x20)) >> 5) - 1; + u32 flush = ((ram->base.size - (ram->poller_base + 0x40)) >> 5) - 1; /* Enable NISO poller for various clients and set their associated * read address, only for MCP77/78 and MCP79/7A. (fd#25701) @@ -92,12 +50,38 @@ mcp77_ram_init(struct nvkm_object *object) return 0; } -struct nvkm_oclass -mcp77_ram_oclass = { - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = mcp77_ram_ctor, - .dtor = _nvkm_ram_dtor, - .init = mcp77_ram_init, - .fini = _nvkm_ram_fini, - }, +static const struct nvkm_ram_func +mcp77_ram_func = { + .init = mcp77_ram_init, + .get = nv50_ram_get, + .put = nv50_ram_put, }; + +int +mcp77_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) +{ + struct nvkm_device *device = fb->subdev.device; + u32 rsvd_head = ( 256 * 1024); /* vga memory */ + u32 rsvd_tail = (1024 * 1024) + 0x1000; /* vbios etc + poller mem */ + u64 base = (u64)nvkm_rd32(device, 0x100e10) << 12; + u64 size = (u64)nvkm_rd32(device, 0x100e14) << 12; + struct mcp77_ram *ram; + int ret; + + if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) + return -ENOMEM; + *pram = &ram->base; + + ret = nvkm_ram_ctor(&mcp77_ram_func, fb, NVKM_RAM_TYPE_STOLEN, + size, 0, &ram->base); + if (ret) + return ret; + + ram->poller_base = size - rsvd_tail; + ram->base.stolen = base; + nvkm_mm_fini(&ram->base.vram); + + return nvkm_mm_init(&ram->base.vram, rsvd_head >> NVKM_RAM_MM_SHIFT, + (size - rsvd_head - rsvd_tail) >> + NVKM_RAM_MM_SHIFT, 1); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c index db9c29dfabea..6f053a03d61c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c @@ -21,60 +21,45 @@ * * Authors: Ben Skeggs */ -#include "priv.h" +#include "ram.h" #include "regsnv04.h" -static int -nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +const struct nvkm_ram_func +nv04_ram_func = { +}; + +int +nv04_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_ram *ram; struct nvkm_device *device = fb->subdev.device; u32 boot0 = nvkm_rd32(device, NV04_PFB_BOOT_0); - int ret; - - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; + u64 size; + enum nvkm_ram_type type; if (boot0 & 0x00000100) { - ram->size = ((boot0 >> 12) & 0xf) * 2 + 2; - ram->size *= 1024 * 1024; + size = ((boot0 >> 12) & 0xf) * 2 + 2; + size *= 1024 * 1024; } else { switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: - ram->size = 32 * 1024 * 1024; + size = 32 * 1024 * 1024; break; case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: - ram->size = 16 * 1024 * 1024; + size = 16 * 1024 * 1024; break; case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: - ram->size = 8 * 1024 * 1024; + size = 8 * 1024 * 1024; break; case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: - ram->size = 4 * 1024 * 1024; + size = 4 * 1024 * 1024; break; } } if ((boot0 & 0x00000038) <= 0x10) - ram->type = NV_MEM_TYPE_SGRAM; + type = NVKM_RAM_TYPE_SGRAM; else - ram->type = NV_MEM_TYPE_SDRAM; + type = NVKM_RAM_TYPE_SDRAM; - return 0; + return nvkm_ram_new_(&nv04_ram_func, fb, type, size, 0, pram); } - -struct nvkm_oclass -nv04_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c index 76cc560e1de3..dfd155c98dbb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c @@ -21,40 +21,20 @@ * * Authors: Ben Skeggs */ -#include "priv.h" +#include "ram.h" -static int -nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv10_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_ram *ram; struct nvkm_device *device = fb->subdev.device; + u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; u32 cfg0 = nvkm_rd32(device, 0x100200); - int ret; - - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; + enum nvkm_ram_type type; if (cfg0 & 0x00000001) - ram->type = NV_MEM_TYPE_DDR1; + type = NVKM_RAM_TYPE_DDR1; else - ram->type = NV_MEM_TYPE_SDRAM; + type = NVKM_RAM_TYPE_SDRAM; - ram->size = nvkm_rd32(device, 0x10020c) & 0xff000000; - return 0; + return nvkm_ram_new_(&nv04_ram_func, fb, type, size, 0, pram); } - -struct nvkm_oclass -nv10_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv10_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c index 6bbdf817471f..3c6a8710e812 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c @@ -21,18 +21,13 @@ * * Authors: Ben Skeggs */ -#include "priv.h" +#include "ram.h" -static int -nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv1a_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_ram *ram; struct pci_dev *bridge; u32 mem, mib; - int ret; bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); if (!bridge) { @@ -40,12 +35,7 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, return -ENODEV; } - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; - - if (nv_device(fb)->chipset == 0x1a) { + if (fb->subdev.device->chipset == 0x1a) { pci_read_config_dword(bridge, 0x7c, &mem); mib = ((mem >> 6) & 31) + 1; } else { @@ -53,18 +43,6 @@ nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, mib = ((mem >> 4) & 127) + 1; } - ram->type = NV_MEM_TYPE_STOLEN; - ram->size = mib * 1024 * 1024; - return 0; + return nvkm_ram_new_(&nv04_ram_func, fb, NVKM_RAM_TYPE_STOLEN, + mib * 1024 * 1024, 0, pram); } - -struct nvkm_oclass -nv1a_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv1a_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c index 017f82e5b61e..747e47c10cc7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c @@ -21,43 +21,29 @@ * * Authors: Ben Skeggs */ -#include "priv.h" +#include "ram.h" -static int -nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv20_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_ram *ram; struct nvkm_device *device = fb->subdev.device; - u32 pbus1218 = nvkm_rd32(device, 0x001218); + u32 pbus1218 = nvkm_rd32(device, 0x001218); + u32 size = (nvkm_rd32(device, 0x10020c) & 0xff000000); + u32 tags = nvkm_rd32(device, 0x100320); + enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; int ret; - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); + switch (pbus1218 & 0x00000300) { + case 0x00000000: type = NVKM_RAM_TYPE_SDRAM; break; + case 0x00000100: type = NVKM_RAM_TYPE_DDR1 ; break; + case 0x00000200: type = NVKM_RAM_TYPE_GDDR3; break; + case 0x00000300: type = NVKM_RAM_TYPE_GDDR2; break; + } + + ret = nvkm_ram_new_(&nv04_ram_func, fb, type, size, tags, pram); if (ret) return ret; - switch (pbus1218 & 0x00000300) { - case 0x00000000: ram->type = NV_MEM_TYPE_SDRAM; break; - case 0x00000100: ram->type = NV_MEM_TYPE_DDR1; break; - case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break; - case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break; - } - ram->size = (nvkm_rd32(device, 0x10020c) & 0xff000000); - ram->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; - ram->tags = nvkm_rd32(device, 0x100320); + (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; return 0; } - -struct nvkm_oclass -nv20_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv20_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 6b2ca3ff8397..56f8cffc2560 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv40.h" +#include "ramnv40.h" #include #include @@ -30,12 +30,12 @@ #include #include -int -nv40_ram_calc(struct nvkm_fb *fb, u32 freq) +static int +nv40_ram_calc(struct nvkm_ram *base, u32 freq) { - struct nvkm_subdev *subdev = &fb->subdev; + struct nv40_ram *ram = nv40_ram(base); + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_bios *bios = subdev->device->bios; - struct nv40_ram *ram = (void *)fb->ram; struct nvbios_pll pll; int N1, M1, N2, M2; int log2P, ret; @@ -46,8 +46,7 @@ nv40_ram_calc(struct nvkm_fb *fb, u32 freq) return ret; } - ret = nv04_pll_calc(nv_subdev(fb), &pll, freq, - &N1, &M1, &N2, &M2, &log2P); + ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); if (ret < 0) return ret; @@ -64,12 +63,13 @@ nv40_ram_calc(struct nvkm_fb *fb, u32 freq) return 0; } -int -nv40_ram_prog(struct nvkm_fb *fb) +static int +nv40_ram_prog(struct nvkm_ram *base) { - struct nvkm_device *device = fb->subdev.device; + struct nv40_ram *ram = nv40_ram(base); + struct nvkm_subdev *subdev = &ram->base.fb->subdev; + struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; - struct nv40_ram *ram = (void *)fb->ram; struct bit_entry M; u32 crtc_mask = 0; u8 sr1[2]; @@ -152,7 +152,7 @@ nv40_ram_prog(struct nvkm_fb *fb) /* execute memory reset script from vbios */ if (!bit_entry(bios, 'M', &M)) { struct nvbios_init init = { - .subdev = nv_subdev(fb), + .subdev = subdev, .bios = bios, .offset = nvbios_rd16(bios, M.offset + 0x00), .execute = 1, @@ -181,51 +181,50 @@ nv40_ram_prog(struct nvkm_fb *fb) return 0; } -void -nv40_ram_tidy(struct nvkm_fb *fb) +static void +nv40_ram_tidy(struct nvkm_ram *base) { } -static int -nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_ram_func +nv40_ram_func = { + .calc = nv40_ram_calc, + .prog = nv40_ram_prog, + .tidy = nv40_ram_tidy, +}; + +int +nv40_ram_new_(struct nvkm_fb *fb, enum nvkm_ram_type type, u64 size, + u32 tags, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); struct nv40_ram *ram; + if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) + return -ENOMEM; + *pram = &ram->base; + return nvkm_ram_ctor(&nv40_ram_func, fb, type, size, tags, &ram->base); +} + +int +nv40_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) +{ struct nvkm_device *device = fb->subdev.device; u32 pbus1218 = nvkm_rd32(device, 0x001218); + u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; + u32 tags = nvkm_rd32(device, 0x100320); + enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; int ret; - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; - switch (pbus1218 & 0x00000300) { - case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break; - case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break; - case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break; - case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break; + case 0x00000000: type = NVKM_RAM_TYPE_SDRAM; break; + case 0x00000100: type = NVKM_RAM_TYPE_DDR1 ; break; + case 0x00000200: type = NVKM_RAM_TYPE_GDDR3; break; + case 0x00000300: type = NVKM_RAM_TYPE_DDR2 ; break; } - ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000; - ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; - ram->base.tags = nvkm_rd32(device, 0x100320); - ram->base.calc = nv40_ram_calc; - ram->base.prog = nv40_ram_prog; - ram->base.tidy = nv40_ram_tidy; + ret = nv40_ram_new_(fb, type, size, tags, pram); + if (ret) + return ret; + + (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; return 0; } - - -struct nvkm_oclass -nv40_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv40_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h new file mode 100644 index 000000000000..8a0524566b48 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.h @@ -0,0 +1,14 @@ +#ifndef __NV40_FB_RAM_H__ +#define __NV40_FB_RAM_H__ +#define nv40_ram(p) container_of((p), struct nv40_ram, base) +#include "ram.h" + +struct nv40_ram { + struct nvkm_ram base; + u32 ctrl; + u32 coef; +}; + +int nv40_ram_new_(struct nvkm_fb *fb, enum nvkm_ram_type, u64, u32, + struct nvkm_ram **); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c index 9ebfb0d8fdd7..114828be292e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c @@ -21,47 +21,29 @@ * * Authors: Ben Skeggs */ -#include "nv40.h" +#include "ramnv40.h" -static int -nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv41_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nv40_ram *ram; struct nvkm_device *device = fb->subdev.device; + u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; + u32 tags = nvkm_rd32(device, 0x100320); u32 fb474 = nvkm_rd32(device, 0x100474); + enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; int ret; - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; - if (fb474 & 0x00000004) - ram->base.type = NV_MEM_TYPE_GDDR3; + type = NVKM_RAM_TYPE_GDDR3; if (fb474 & 0x00000002) - ram->base.type = NV_MEM_TYPE_DDR2; + type = NVKM_RAM_TYPE_DDR2; if (fb474 & 0x00000001) - ram->base.type = NV_MEM_TYPE_DDR1; + type = NVKM_RAM_TYPE_DDR1; - ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000; - ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; - ram->base.tags = nvkm_rd32(device, 0x100320); - ram->base.calc = nv40_ram_calc; - ram->base.prog = nv40_ram_prog; - ram->base.tidy = nv40_ram_tidy; + ret = nv40_ram_new_(fb, type, size, tags, pram); + if (ret) + return ret; + + (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; return 0; } - -struct nvkm_oclass -nv41_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv41_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c index ac0ba6deb576..bc56fbf1c788 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c @@ -21,45 +21,22 @@ * * Authors: Ben Skeggs */ -#include "nv40.h" +#include "ramnv40.h" -static int -nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv44_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nv40_ram *ram; struct nvkm_device *device = fb->subdev.device; + u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; u32 fb474 = nvkm_rd32(device, 0x100474); - int ret; - - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; + enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; if (fb474 & 0x00000004) - ram->base.type = NV_MEM_TYPE_GDDR3; + type = NVKM_RAM_TYPE_GDDR3; if (fb474 & 0x00000002) - ram->base.type = NV_MEM_TYPE_DDR2; + type = NVKM_RAM_TYPE_DDR2; if (fb474 & 0x00000001) - ram->base.type = NV_MEM_TYPE_DDR1; + type = NVKM_RAM_TYPE_DDR1; - ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000; - ram->base.calc = nv40_ram_calc; - ram->base.prog = nv40_ram_prog; - ram->base.tidy = nv40_ram_tidy; - return 0; + return nv40_ram_new_(fb, type, size, 0, pram); } - -struct nvkm_oclass -nv44_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv44_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c index 4a19da6a26ba..c01f4b1022b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c @@ -21,47 +21,29 @@ * * Authors: Ben Skeggs */ -#include "nv40.h" +#include "ramnv40.h" -static int -nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv49_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nv40_ram *ram; struct nvkm_device *device = fb->subdev.device; + u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; + u32 tags = nvkm_rd32(device, 0x100320); u32 fb914 = nvkm_rd32(device, 0x100914); + enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; int ret; - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; - switch (fb914 & 0x00000003) { - case 0x00000000: ram->base.type = NV_MEM_TYPE_DDR1; break; - case 0x00000001: ram->base.type = NV_MEM_TYPE_DDR2; break; - case 0x00000002: ram->base.type = NV_MEM_TYPE_GDDR3; break; + case 0x00000000: type = NVKM_RAM_TYPE_DDR1 ; break; + case 0x00000001: type = NVKM_RAM_TYPE_DDR2 ; break; + case 0x00000002: type = NVKM_RAM_TYPE_GDDR3; break; case 0x00000003: break; } - ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000; - ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; - ram->base.tags = nvkm_rd32(device, 0x100320); - ram->base.calc = nv40_ram_calc; - ram->base.prog = nv40_ram_prog; - ram->base.tidy = nv40_ram_tidy; + ret = nv40_ram_new_(fb, type, size, tags, pram); + if (ret) + return ret; + + (*pram)->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1; return 0; } - -struct nvkm_oclass -nv49_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv49_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c index 1778b3c7c897..fa3c2e06203d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c @@ -21,35 +21,13 @@ * * Authors: Ben Skeggs */ -#include "priv.h" +#include "ram.h" -static int -nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv4e_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_ram *ram; struct nvkm_device *device = fb->subdev.device; - int ret; - - ret = nvkm_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); - if (ret) - return ret; - - ram->size = nvkm_rd32(device, 0x10020c) & 0xff000000; - ram->type = NV_MEM_TYPE_STOLEN; - return 0; + u32 size = nvkm_rd32(device, 0x10020c) & 0xff000000; + return nvkm_ram_new_(&nv04_ram_func, fb, NVKM_RAM_TYPE_UNKNOWN, + size, 0, pram); } - -struct nvkm_oclass -nv4e_ram_oclass = { - .handle = 0, - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv4e_ram_create, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 1c38fb4d9c1f..9197e0ef5cdb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -21,8 +21,10 @@ * * Authors: Ben Skeggs */ -#include "nv50.h" +#define nv50_ram(p) container_of((p), struct nv50_ram, base) +#include "ram.h" #include "ramseq.h" +#include "nv50.h" #include #include @@ -66,11 +68,10 @@ struct nv50_ram { #define T(t) cfg->timing_10_##t static int -nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) +nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) { - struct nv50_ram *ram = (void *)fb->ram; struct nvbios_ramcfg *cfg = &ram->base.target.bios; - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_device *device = subdev->device; u32 cur2, cur4, cur7, cur8; u8 unkt3b; @@ -81,16 +82,16 @@ nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) cur8 = nvkm_rd32(device, 0x100240); switch ((!T(CWL)) * ram->base.type) { - case NV_MEM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR2: T(CWL) = T(CL) - 1; break; - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; break; } /* XXX: N=1 is not proper statistics */ - if (nv_device(fb)->chipset == 0xa0) { + if (device->chipset == 0xa0) { unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; timing[6] = (0x2d + T(CL) - T(CWL) + ram->base.next->bios.rammap_00_16_40) << 16 | @@ -127,10 +128,11 @@ nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing) timing[8] = (cur8 & 0xffffff00); /* XXX: P.version == 1 only has DDR2 and GDDR3? */ - if (fb->ram->type == NV_MEM_TYPE_DDR2) { + if (ram->base.type == NVKM_RAM_TYPE_DDR2) { timing[5] |= (T(CL) + 3) << 8; timing[8] |= (T(CL) - 4); - } else if (fb->ram->type == NV_MEM_TYPE_GDDR3) { + } else + if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { timing[5] |= (T(CL) + 2) << 8; timing[8] |= (T(CL) - 2); } @@ -153,11 +155,11 @@ nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) } static int -nv50_ram_calc(struct nvkm_fb *fb, u32 freq) +nv50_ram_calc(struct nvkm_ram *base, u32 freq) { - struct nv50_ram *ram = (void *)fb->ram; + struct nv50_ram *ram = nv50_ram(base); struct nv50_ramseq *hwsq = &ram->hwsq; - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; struct nvkm_bios *bios = subdev->device->bios; struct nvbios_perfE perfE; struct nvbios_pll mpll; @@ -177,7 +179,7 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) i = 0; do { data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, - &size, &perfE); + &size, &perfE); if (!data || (ver < 0x25 || ver >= 0x40) || (size < 2)) { nvkm_error(subdev, "invalid/missing perftab entry\n"); @@ -188,7 +190,7 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios); /* locate specific data set for the attached memory */ - strap = nvbios_ramcfg_index(nv_subdev(fb)); + strap = nvbios_ramcfg_index(subdev); if (strap >= cnt) { nvkm_error(subdev, "invalid ramcfg strap\n"); return -EINVAL; @@ -213,9 +215,9 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) } } - nv50_ram_timing_calc(fb, timing); + nv50_ram_timing_calc(ram, timing); - ret = ram_init(hwsq, nv_subdev(fb)); + ret = ram_init(hwsq, subdev); if (ret) return ret; @@ -225,7 +227,7 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) ram->base.mr[2] = ram_rd32(hwsq, mr[2]); switch (ram->base.type) { - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: ret = nvkm_gddr3_calc(&ram->base); break; default: @@ -257,7 +259,7 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) ret = nvbios_pll_parse(bios, 0x004008, &mpll); mpll.vco2.max_freq = 0; if (ret >= 0) { - ret = nv04_pll_calc(nv_subdev(fb), &mpll, freq, + ret = nv04_pll_calc(subdev, &mpll, freq, &N1, &M1, &N2, &M2, &P); if (ret <= 0) ret = -EINVAL; @@ -284,7 +286,7 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) next->bios.rammap_00_16_40 << 14); ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); - if (nv_device(fb)->chipset >= 0x96) + if (subdev->device->chipset >= 0x96) ram_wr32(hwsq, 0x100da0, r100da0); ram_nsec(hwsq, 64000); /*XXX*/ ram_nsec(hwsq, 32000); /*XXX*/ @@ -298,11 +300,11 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) ram_nsec(hwsq, 12000); switch (ram->base.type) { - case NV_MEM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR2: ram_nuke(hwsq, mr[0]); /* force update */ ram_mask(hwsq, mr[0], 0x000, 0x000); break; - case NV_MEM_TYPE_GDDR3: + case NVKM_RAM_TYPE_GDDR3: ram_nuke(hwsq, mr[1]); /* force update */ ram_wr32(hwsq, mr[1], ram->base.mr[1]); ram_nuke(hwsq, mr[0]); /* force update */ @@ -382,26 +384,23 @@ nv50_ram_calc(struct nvkm_fb *fb, u32 freq) } static int -nv50_ram_prog(struct nvkm_fb *fb) +nv50_ram_prog(struct nvkm_ram *base) { - struct nvkm_device *device = nv_device(fb); - struct nv50_ram *ram = (void *)fb->ram; - struct nv50_ramseq *hwsq = &ram->hwsq; - - ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); + struct nv50_ram *ram = nv50_ram(base); + struct nvkm_device *device = ram->base.fb->subdev.device; + ram_exec(&ram->hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -nv50_ram_tidy(struct nvkm_fb *fb) +nv50_ram_tidy(struct nvkm_ram *base) { - struct nv50_ram *ram = (void *)fb->ram; - struct nv50_ramseq *hwsq = &ram->hwsq; - ram_exec(hwsq, false); + struct nv50_ram *ram = nv50_ram(base); + ram_exec(&ram->hwsq, false); } void -__nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem *mem) +__nv50_ram_put(struct nvkm_ram *ram, struct nvkm_mem *mem) { struct nvkm_mm_node *this; @@ -409,14 +408,14 @@ __nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem *mem) this = list_first_entry(&mem->regions, typeof(*this), rl_entry); list_del(&this->rl_entry); - nvkm_mm_free(&fb->vram, &this); + nvkm_mm_free(&ram->vram, &this); } - nvkm_mm_free(&fb->tags, &mem->tag); + nvkm_mm_free(&ram->tags, &mem->tag); } void -nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) +nv50_ram_put(struct nvkm_ram *ram, struct nvkm_mem **pmem) { struct nvkm_mem *mem = *pmem; @@ -424,19 +423,19 @@ nv50_ram_put(struct nvkm_fb *fb, struct nvkm_mem **pmem) if (unlikely(mem == NULL)) return; - mutex_lock(&fb->subdev.mutex); - __nv50_ram_put(fb, mem); - mutex_unlock(&fb->subdev.mutex); + mutex_lock(&ram->fb->subdev.mutex); + __nv50_ram_put(ram, mem); + mutex_unlock(&ram->fb->subdev.mutex); kfree(mem); } int -nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, +nv50_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, u32 memtype, struct nvkm_mem **pmem) { - struct nvkm_mm *heap = &fb->vram; - struct nvkm_mm *tags = &fb->tags; + struct nvkm_mm *heap = &ram->vram; + struct nvkm_mm *tags = &ram->tags; struct nvkm_mm_node *r; struct nvkm_mem *mem; int comp = (memtype & 0x300) >> 8; @@ -444,17 +443,17 @@ nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, int back = (memtype & 0x800); int min, max, ret; - max = (size >> 12); - min = ncmin ? (ncmin >> 12) : max; - align >>= 12; + max = (size >> NVKM_RAM_MM_SHIFT); + min = ncmin ? (ncmin >> NVKM_RAM_MM_SHIFT) : max; + align >>= NVKM_RAM_MM_SHIFT; mem = kzalloc(sizeof(*mem), GFP_KERNEL); if (!mem) return -ENOMEM; - mutex_lock(&fb->subdev.mutex); + mutex_lock(&ram->fb->subdev.mutex); if (comp) { - if (align == 16) { + if (align == (1 << (16 - NVKM_RAM_MM_SHIFT))) { int n = (max >> 4) * comp; ret = nvkm_mm_head(tags, 0, 1, n, n, 1, &mem->tag); @@ -477,26 +476,35 @@ nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin, else ret = nvkm_mm_head(heap, 0, type, max, min, align, &r); if (ret) { - mutex_unlock(&fb->subdev.mutex); - fb->ram->put(fb, &mem); + mutex_unlock(&ram->fb->subdev.mutex); + ram->func->put(ram, &mem); return ret; } list_add_tail(&r->rl_entry, &mem->regions); max -= r->length; } while (max); - mutex_unlock(&fb->subdev.mutex); + mutex_unlock(&ram->fb->subdev.mutex); r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); - mem->offset = (u64)r->offset << 12; + mem->offset = (u64)r->offset << NVKM_RAM_MM_SHIFT; *pmem = mem; return 0; } +static const struct nvkm_ram_func +nv50_ram_func = { + .get = nv50_ram_get, + .put = nv50_ram_put, + .calc = nv50_ram_calc, + .prog = nv50_ram_prog, + .tidy = nv50_ram_tidy, +}; + static u32 -nv50_fb_vram_rblock(struct nvkm_fb *fb, struct nvkm_ram *ram) +nv50_fb_vram_rblock(struct nvkm_ram *ram) { - struct nvkm_subdev *subdev = &fb->subdev; + struct nvkm_subdev *subdev = &ram->fb->subdev; struct nvkm_device *device = subdev->device; int colbits, rowbitsa, rowbitsb, banks; u64 rowsize, predicted; @@ -532,83 +540,63 @@ nv50_fb_vram_rblock(struct nvkm_fb *fb, struct nvkm_ram *ram) } int -nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) +nv50_ram_ctor(const struct nvkm_ram_func *func, + struct nvkm_fb *fb, struct nvkm_ram *ram) { - const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ - const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ - struct nvkm_fb *fb = nvkm_fb(parent); struct nvkm_device *device = fb->subdev.device; struct nvkm_bios *bios = device->bios; - struct nvkm_ram *ram; + const u32 rsvd_head = ( 256 * 1024); /* vga memory */ + const u32 rsvd_tail = (1024 * 1024); /* vbios etc */ + u64 size = nvkm_rd32(device, 0x10020c); + u32 tags = nvkm_rd32(device, 0x100320); + enum nvkm_ram_type type = NVKM_RAM_TYPE_UNKNOWN; int ret; - ret = nvkm_ram_create_(parent, engine, oclass, length, pobject); - ram = *pobject; - if (ret) - return ret; - - ram->size = nvkm_rd32(device, 0x10020c); - ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); - - ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; - ram->parts = hweight8(ram->part_mask); - switch (nvkm_rd32(device, 0x100714) & 0x00000007) { - case 0: ram->type = NV_MEM_TYPE_DDR1; break; + case 0: type = NVKM_RAM_TYPE_DDR1; break; case 1: - if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) - ram->type = NV_MEM_TYPE_DDR3; + if (nvkm_fb_bios_memtype(bios) == NVKM_RAM_TYPE_DDR3) + type = NVKM_RAM_TYPE_DDR3; else - ram->type = NV_MEM_TYPE_DDR2; + type = NVKM_RAM_TYPE_DDR2; break; - case 2: ram->type = NV_MEM_TYPE_GDDR3; break; - case 3: ram->type = NV_MEM_TYPE_GDDR4; break; - case 4: ram->type = NV_MEM_TYPE_GDDR5; break; + case 2: type = NVKM_RAM_TYPE_GDDR3; break; + case 3: type = NVKM_RAM_TYPE_GDDR4; break; + case 4: type = NVKM_RAM_TYPE_GDDR5; break; default: break; } - ret = nvkm_mm_init(&fb->vram, rsvd_head, (ram->size >> 12) - - (rsvd_head + rsvd_tail), - nv50_fb_vram_rblock(fb, ram) >> 12); + size = (size & 0x000000ff) << 32 | (size & 0xffffff00); + + ret = nvkm_ram_ctor(func, fb, type, size, tags, ram); if (ret) return ret; + ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; + ram->parts = hweight8(ram->part_mask); ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1; - ram->tags = nvkm_rd32(device, 0x100320); - ram->get = nv50_ram_get; - ram->put = nv50_ram_put; - return 0; + nvkm_mm_fini(&ram->vram); + + return nvkm_mm_init(&ram->vram, rsvd_head >> NVKM_RAM_MM_SHIFT, + (size - rsvd_head - rsvd_tail) >> NVKM_RAM_MM_SHIFT, + nv50_fb_vram_rblock(ram) >> NVKM_RAM_MM_SHIFT); } -static int -nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 datasize, - struct nvkm_object **pobject) +int +nv50_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_fb *fb = nvkm_fb(parent); - struct nvkm_subdev *subdev = &fb->subdev; struct nv50_ram *ram; int ret, i; - ret = nv50_ram_create(parent, engine, oclass, &ram); - *pobject = nv_object(ram); + if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) + return -ENOMEM; + *pram = &ram->base; + + ret = nv50_ram_ctor(&nv50_ram_func, fb, &ram->base); if (ret) return ret; - switch (ram->base.type) { - case NV_MEM_TYPE_GDDR3: - ram->base.calc = nv50_ram_calc; - ram->base.prog = nv50_ram_prog; - ram->base.tidy = nv50_ram_tidy; - break; - case NV_MEM_TYPE_DDR2: - default: - nvkm_warn(subdev, "reclocking of this ram type unsupported\n"); - return 0; - } - ram->hwsq.r_0x002504 = hwsq_reg(0x002504); ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); ram->hwsq.r_0x004008 = hwsq_reg(0x004008); @@ -648,13 +636,3 @@ nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } - -struct nvkm_oclass -nv50_ram_oclass = { - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_ram_ctor, - .dtor = _nvkm_ram_dtor, - .init = _nvkm_ram_init, - .fini = _nvkm_ram_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 339dd19e0e45..4f6354df538a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -84,8 +84,8 @@ static void nv50_instobj_dtor(struct nvkm_object *object) { struct nv50_instobj *node = (void *)object; - struct nvkm_fb *fb = nvkm_fb(object); - fb->ram->put(fb, &node->mem); + struct nvkm_ram *ram = nvkm_fb(object)->ram; + ram->func->put(ram, &node->mem); nvkm_instobj_destroy(&node->base); } @@ -94,7 +94,7 @@ nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fb *fb = nvkm_fb(parent); + struct nvkm_ram *ram = nvkm_fb(parent)->ram; struct nvkm_instobj_args *args = data; struct nv50_instobj *node; int ret; @@ -107,7 +107,8 @@ nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = fb->ram->get(fb, args->size, args->align, 0, 0x800, &node->mem); + ret = ram->func->get(ram, args->size, args->align, 0, 0x800, + &node->mem); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index 22712cdc01b3..5cb7604beeb6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -145,12 +145,12 @@ gf100_ltc_init(struct nvkm_object *object) void gf100_ltc_dtor(struct nvkm_object *object) { - struct nvkm_fb *fb = nvkm_fb(object); struct nvkm_ltc_priv *ltc = (void *)object; + struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram; nvkm_mm_fini(<c->tags); - if (fb->ram) - nvkm_mm_free(&fb->vram, <c->tag_ram); + if (ram) + nvkm_mm_free(&ram->vram, <c->tag_ram); nvkm_ltc_destroy(ltc); } @@ -158,19 +158,20 @@ gf100_ltc_dtor(struct nvkm_object *object) /* TODO: Figure out tag memory details and drop the over-cautious allocation. */ int -gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *ltc) +gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *ltc) { + struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram; u32 tag_size, tag_margin, tag_align; int ret; /* No VRAM, no tags for now. */ - if (!fb->ram) { + if (!ram) { ltc->num_tags = 0; goto mm_init; } /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ - ltc->num_tags = (fb->ram->size >> 17) / 4; + ltc->num_tags = (ram->size >> 17) / 4; if (ltc->num_tags > (1 << 17)) ltc->num_tags = 1 << 17; /* we have 17 bits in PTE */ ltc->num_tags = (ltc->num_tags + 63) & ~63; /* round up to 64 */ @@ -190,7 +191,7 @@ gf100_ltc_init_tag_ram(struct nvkm_fb *fb, struct nvkm_ltc_priv *ltc) tag_size += tag_align; tag_size = (tag_size + 0xfff) >> 12; /* round up */ - ret = nvkm_mm_tail(&fb->vram, 1, 1, tag_size, tag_size, 1, + ret = nvkm_mm_tail(&ram->vram, 1, 1, tag_size, tag_size, 1, <c->tag_ram); if (ret) { ltc->num_tags = 0; @@ -214,7 +215,6 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_device *device = (void *)parent; - struct nvkm_fb *fb = device->fb; struct nvkm_ltc_priv *ltc; u32 parts, mask; int ret, i; @@ -232,7 +232,7 @@ gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } ltc->lts_nr = nvkm_rd32(device, 0x17e8dc) >> 28; - ret = gf100_ltc_init_tag_ram(fb, ltc); + ret = gf100_ltc_init_tag_ram(ltc); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index 222f37e50a95..431acbef6bb7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -124,7 +124,6 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_device *device = (void *)parent; - struct nvkm_fb *fb = device->fb; struct nvkm_ltc_priv *ltc; u32 parts, mask; int ret, i; @@ -142,7 +141,7 @@ gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, } ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; - ret = gf100_ltc_init_tag_ram(fb, ltc); + ret = gf100_ltc_init_tag_ram(ltc); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 09537d7b6783..0544288b0d1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -45,7 +45,7 @@ int gf100_ltc_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); void gf100_ltc_dtor(struct nvkm_object *); -int gf100_ltc_init_tag_ram(struct nvkm_fb *, struct nvkm_ltc_priv *); +int gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *); int gf100_ltc_tags_alloc(struct nvkm_ltc *, u32, struct nvkm_mm_node **); void gf100_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **); -- cgit v1.2.3 From aa35888ff024b18c7b6b29eb773a221f642987f7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:16 +1000 Subject: drm/nouveau/object: rename some functions to avoid upcoming conflicts Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h | 4 ++-- drivers/gpu/drm/nouveau/include/nvkm/core/object.h | 6 +++--- drivers/gpu/drm/nouveau/include/nvkm/core/parent.h | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 10 +++++----- drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/core/object.c | 10 +++++----- drivers/gpu/drm/nouveau/nvkm/core/subdev.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c | 4 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c | 6 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 2 +- 22 files changed, 51 insertions(+), 51 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h index 0dd216c055f6..46975785ba3c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h @@ -32,8 +32,8 @@ nv_gpuobj(void *obj) #define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \ nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \ sizeof(**d), (void **)d) -#define nvkm_gpuobj_init(p) nvkm_object_init(&(p)->object) -#define nvkm_gpuobj_fini(p,s) nvkm_object_fini(&(p)->object, (s)) +#define nvkm_gpuobj_init(p) _nvkm_object_init(&(p)->object) +#define nvkm_gpuobj_fini(p,s) _nvkm_object_fini(&(p)->object, (s)) int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, u32 pclass, struct nvkm_object *, u32 size, u32 align, diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h index 005cd4a86849..39a4962d3982 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h @@ -50,8 +50,8 @@ nv_object(void *obj) int nvkm_object_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, u32, int size, void **); void nvkm_object_destroy(struct nvkm_object *); -int nvkm_object_init(struct nvkm_object *); -int nvkm_object_fini(struct nvkm_object *, bool suspend); +int _nvkm_object_init(struct nvkm_object *); +int _nvkm_object_fini(struct nvkm_object *, bool suspend); int _nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, @@ -112,7 +112,7 @@ nv_ofuncs(void *obj) return nv_oclass(obj)->ofuncs; } -int nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *, +int nvkm_object_old(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h index 45d2066ff97a..92270afc666a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/parent.h @@ -30,9 +30,9 @@ nv_parent(void *obj) nvkm_parent_create_((p), (e), (c), (v), (s), (m), \ sizeof(**d), (void **)d) #define nvkm_parent_init(p) \ - nvkm_object_init(&(p)->object) + _nvkm_object_init(&(p)->object) #define nvkm_parent_fini(p,s) \ - nvkm_object_fini(&(p)->object, (s)) + _nvkm_object_fini(&(p)->object, (s)) int nvkm_parent_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, u32 pclass, @@ -41,8 +41,8 @@ int nvkm_parent_create_(struct nvkm_object *, struct nvkm_object *, void nvkm_parent_destroy(struct nvkm_parent *); void _nvkm_parent_dtor(struct nvkm_object *); -#define _nvkm_parent_init nvkm_object_init -#define _nvkm_parent_fini nvkm_object_fini +#define _nvkm_parent_init _nvkm_object_init +#define _nvkm_parent_fini _nvkm_object_fini int nvkm_parent_sclass(struct nvkm_object *, s32 handle, struct nvkm_object **pengine, diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index 6e2683323570..1ca5479ee38b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -223,9 +223,9 @@ nvkm_gpuobj_new(struct nvkm_object *parent, struct nvkm_object *pargpu, .flags = flags, }; - return nvkm_object_ctor(parent, &parent->engine->subdev.object, - &_nvkm_gpuobj_oclass, &args, sizeof(args), - (struct nvkm_object **)pgpuobj); + return nvkm_object_old(parent, &parent->engine->subdev.object, + &_nvkm_gpuobj_oclass, &args, sizeof(args), + (struct nvkm_object **)pgpuobj); } int @@ -288,8 +288,8 @@ nvkm_gpudup_oclass = { .handle = NV_GPUOBJ_CLASS, .ofuncs = &(struct nvkm_ofuncs) { .dtor = nvkm_gpudup_dtor, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index ee6ff01c2b1b..7a15b15bfce0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -137,7 +137,7 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) * between the parent and its children (eg. PGRAPH context) */ if (engine && nv_engine(engine)->cclass) { - ret = nvkm_object_ctor(&parent->object, engine, + ret = nvkm_object_old(&parent->object, engine, nv_engine(engine)->cclass, data, size, &engctx); if (ret) @@ -147,7 +147,7 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) } /* finally, create new object and bind it to its handle */ - ret = nvkm_object_ctor(engctx, engine, oclass, data, size, &object); + ret = nvkm_object_old(engctx, engine, oclass, data, size, &object); client->data = object; if (ret) goto fail_ctor; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c index 98ba58ec1d39..1c117f0a7245 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/object.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c @@ -136,13 +136,13 @@ nvkm_object_destroy(struct nvkm_object *object) } int -nvkm_object_init(struct nvkm_object *object) +_nvkm_object_init(struct nvkm_object *object) { return 0; } int -nvkm_object_fini(struct nvkm_object *object, bool suspend) +_nvkm_object_fini(struct nvkm_object *object, bool suspend) { return 0; } @@ -151,12 +151,12 @@ struct nvkm_ofuncs nvkm_object_ofuncs = { .ctor = _nvkm_object_ctor, .dtor = nvkm_object_destroy, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, }; int -nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, +nvkm_object_old(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c index 25f3503cd37a..0c313468d94e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c @@ -48,7 +48,7 @@ nvkm_subdev_reset(struct nvkm_object *obj) int nvkm_subdev_init(struct nvkm_subdev *subdev) { - int ret = nvkm_object_init(&subdev->object); + int ret = _nvkm_object_init(&subdev->object); if (ret) return ret; @@ -72,7 +72,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) nvkm_mask(device, 0x000200, subdev->unit, subdev->unit); } - return nvkm_object_fini(&subdev->object, suspend); + return _nvkm_object_fini(&subdev->object, suspend); } int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 479181c839b4..b7892e6f080b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -152,7 +152,7 @@ nvkm_device_init(struct nvkm_device *device) for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) { #define _(s,m) case s: if (device->oclass[s] && !device->subdev[s]) { \ - ret = nvkm_object_ctor(nv_object(device), NULL, \ + ret = nvkm_object_old(nv_object(device), NULL, \ device->oclass[s], NULL, (s), \ (struct nvkm_object **)&device->m); \ if (ret == -ENODEV) { \ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c index c13cd9d46a1a..0abee2d21a78 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c @@ -185,8 +185,8 @@ static struct nvkm_ofuncs nvkm_control_ofuncs = { .ctor = _nvkm_object_ctor, .dtor = nvkm_object_destroy, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, .mthd = nvkm_control_mthd, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index d6c0cf0e5a35..ab5f8429e680 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -106,8 +106,8 @@ static struct nvkm_ofuncs nv04_disp_ofuncs = { .ctor = _nvkm_object_ctor, .dtor = nvkm_object_destroy, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, .mthd = nv04_disp_mthd, .ntfy = nvkm_disp_ntfy, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h index 44ae8a0ca65c..c4c210bdbf7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/priv.h @@ -9,8 +9,8 @@ int nvkm_dmaobj_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void **, u32 *, int, void **); #define _nvkm_dmaobj_dtor nvkm_object_destroy -#define _nvkm_dmaobj_init nvkm_object_init -#define _nvkm_dmaobj_fini nvkm_object_fini +#define _nvkm_dmaobj_init _nvkm_object_init +#define _nvkm_dmaobj_fini _nvkm_object_fini int _nvkm_dmaeng_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 48b526cb8cb5..3562b791162f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -272,7 +272,7 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, .ofuncs = &nvkm_object_ofuncs, }; args->v0.engine = engines; - return nvkm_object_ctor(parent, engine, &oclass, NULL, 0, pobject); + return nvkm_object_old(parent, engine, &oclass, NULL, 0, pobject); } engines &= args->v0.engine; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index a7141e08930c..6afdb20cf304 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -228,8 +228,8 @@ struct nvkm_ofuncs gf100_fermi_ofuncs = { .ctor = _nvkm_object_ctor, .dtor = nvkm_object_destroy, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, .mthd = gf100_fermi_mthd, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 323f020166da..617161e4fc15 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1187,7 +1187,7 @@ nv04_gr_context_fini(struct nvkm_object *object, bool suspend) nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); - return nvkm_object_fini(&chan->base, suspend); + return _nvkm_object_fini(&chan->base, suspend); } static struct nvkm_oclass @@ -1196,7 +1196,7 @@ nv04_gr_cclass = { .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_gr_context_ctor, .dtor = nv04_gr_context_dtor, - .init = nvkm_object_init, + .init = _nvkm_object_init, .fini = nv04_gr_context_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 94f7dc794d2f..be92015d8f9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -1111,7 +1111,7 @@ nv10_gr_context_fini(struct nvkm_object *object, bool suspend) nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); - return nvkm_object_fini(&chan->base, suspend); + return _nvkm_object_fini(&chan->base, suspend); } static struct nvkm_oclass @@ -1120,7 +1120,7 @@ nv10_gr_cclass = { .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv10_gr_context_ctor, .dtor = nv10_gr_context_dtor, - .init = nvkm_object_init, + .init = _nvkm_object_init, .fini = nv10_gr_context_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 1586213b0830..0f02b281f34e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -173,8 +173,8 @@ nv31_mpeg_cclass = { .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv31_mpeg_context_ctor, .dtor = nv31_mpeg_context_dtor, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index b75395bf8ffa..ac27f511163a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -419,8 +419,8 @@ static struct nvkm_ofuncs nvkm_perfdom_ofuncs = { .ctor = nvkm_perfdom_ctor, .dtor = nvkm_perfdom_dtor, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, .mthd = nvkm_perfdom_mthd, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 0cdb49e983ab..6fe71b2276cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -94,8 +94,8 @@ nvkm_barobj_oclass = { .ofuncs = &(struct nvkm_ofuncs) { .ctor = nvkm_barobj_ctor, .dtor = nvkm_barobj_dtor, - .init = nvkm_object_init, - .fini = nvkm_object_fini, + .init = _nvkm_object_init, + .fini = _nvkm_object_fini, .rd32 = nvkm_barobj_rd32, .wr32 = nvkm_barobj_wr32, }, @@ -106,7 +106,7 @@ nvkm_bar_alloc(struct nvkm_bar *bar, struct nvkm_object *parent, struct nvkm_mem *mem, struct nvkm_object **pobject) { struct nvkm_object *gpuobj; - int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object, + int ret = nvkm_object_old(parent, &parent->engine->subdev.object, &nvkm_barobj_oclass, mem, 0, &gpuobj); if (ret == 0) *pobject = gpuobj; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c index 4219eb39cf45..495da913bd11 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c @@ -72,7 +72,7 @@ nvkm_instmem_alloc(struct nvkm_instmem *imem, struct nvkm_object *parent, { struct nvkm_instmem_impl *impl = (void *)imem->subdev.object.oclass; struct nvkm_instobj_args args = { .size = size, .align = align }; - return nvkm_object_ctor(parent, &parent->engine->subdev.object, + return nvkm_object_old(parent, &parent->engine->subdev.object, impl->instobj, &args, sizeof(args), pobject); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h index e217ebebd325..819f615782cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -18,15 +18,15 @@ struct nvkm_instobj_args { _nvkm_instobj_dtor(nv_object(iobj)); \ }) #define nvkm_instobj_init(p) \ - nvkm_object_init(&(p)->base) + _nvkm_object_init(&(p)->base) #define nvkm_instobj_fini(p,s) \ - nvkm_object_fini(&(p)->base, (s)) + _nvkm_object_fini(&(p)->base, (s)) int nvkm_instobj_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, int, void **); void _nvkm_instobj_dtor(struct nvkm_object *); -#define _nvkm_instobj_init nvkm_object_init -#define _nvkm_instobj_fini nvkm_object_fini +#define _nvkm_instobj_init _nvkm_object_init +#define _nvkm_instobj_fini _nvkm_object_fini struct nvkm_instmem_impl { struct nvkm_oclass base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index c44f880120ab..26192b91e456 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -96,7 +96,7 @@ nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) { - return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, + return nvkm_object_old(parent, engine, &nv04_mmu_oclass, data, size, pobject); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index 3be8a796d797..3e51dc772536 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -169,7 +169,7 @@ nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) { - return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, + return nvkm_object_old(parent, engine, &nv04_mmu_oclass, data, size, pobject); } -- cgit v1.2.3 From 6cf813fb26640ef539051fb7f965af8c9ff10d92 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:17 +1000 Subject: drm/nouveau/device: prepare for new-style subdevs Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 50 +- drivers/gpu/drm/nouveau/nvkm/core/engine.c | 10 + drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 25 +- drivers/gpu/drm/nouveau/nvkm/core/object.c | 48 +- drivers/gpu/drm/nouveau/nvkm/core/subdev.c | 39 +- drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 2251 +++++++++++++++++++- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 41 - drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 40 - drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 36 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 19 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 26 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 23 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 24 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 39 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 48 - drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h | 36 + drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c | 8 +- drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 4 +- 28 files changed, 2378 insertions(+), 437 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index eb843e3ff005..3786982c1360 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -84,9 +84,9 @@ struct nvkm_device { struct nvkm_event event; - const char *cname; u64 disable_mask; + const struct nvkm_device_chip *chip; enum { NV_04 = 0x04, NV_10 = 0x10, @@ -104,7 +104,6 @@ struct nvkm_device { u32 crystal; struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR]; - struct nvkm_object *subdev[NVDEV_SUBDEV_NR]; struct { struct notifier_block nb; @@ -153,6 +152,9 @@ struct nvkm_device { struct nouveau_platform_gpu *gpu; }; +struct nvkm_subdev *nvkm_device_subdev(struct nvkm_device *, int index); +struct nvkm_engine *nvkm_device_engine(struct nvkm_device *, int index); + struct nvkm_device_func { struct nvkm_device_pci *(*pci)(struct nvkm_device *); struct nvkm_device_tegra *(*tegra)(struct nvkm_device *); @@ -164,6 +166,50 @@ struct nvkm_device_func { struct nvkm_device_quirk { }; +struct nvkm_device_chip { + const char *name; + + int (*bar )(struct nvkm_device *, int idx, struct nvkm_bar **); + int (*bios )(struct nvkm_device *, int idx, struct nvkm_bios **); + int (*bus )(struct nvkm_device *, int idx, struct nvkm_bus **); + int (*clk )(struct nvkm_device *, int idx, struct nvkm_clk **); + int (*devinit)(struct nvkm_device *, int idx, struct nvkm_devinit **); + int (*fb )(struct nvkm_device *, int idx, struct nvkm_fb **); + int (*fuse )(struct nvkm_device *, int idx, struct nvkm_fuse **); + int (*gpio )(struct nvkm_device *, int idx, struct nvkm_gpio **); + int (*i2c )(struct nvkm_device *, int idx, struct nvkm_i2c **); + int (*ibus )(struct nvkm_device *, int idx, struct nvkm_subdev **); + int (*imem )(struct nvkm_device *, int idx, struct nvkm_instmem **); + int (*ltc )(struct nvkm_device *, int idx, struct nvkm_ltc **); + int (*mc )(struct nvkm_device *, int idx, struct nvkm_mc **); + int (*mmu )(struct nvkm_device *, int idx, struct nvkm_mmu **); + int (*mxm )(struct nvkm_device *, int idx, struct nvkm_subdev **); + int (*pmu )(struct nvkm_device *, int idx, struct nvkm_pmu **); + int (*therm )(struct nvkm_device *, int idx, struct nvkm_therm **); + int (*timer )(struct nvkm_device *, int idx, struct nvkm_timer **); + int (*volt )(struct nvkm_device *, int idx, struct nvkm_volt **); + + int (*bsp )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*ce[3] )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*cipher )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*disp )(struct nvkm_device *, int idx, struct nvkm_disp **); + int (*dma )(struct nvkm_device *, int idx, struct nvkm_dmaeng **); + int (*fifo )(struct nvkm_device *, int idx, struct nvkm_fifo **); + int (*gr )(struct nvkm_device *, int idx, struct nvkm_gr **); + int (*ifb )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*me )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*mpeg )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*msenc )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*pm )(struct nvkm_device *, int idx, struct nvkm_pm **); + int (*sec )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **); + int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **); + int (*vp )(struct nvkm_device *, int idx, struct nvkm_engine **); +}; + struct nvkm_device *nvkm_device_find(u64 name); int nvkm_device_list(u64 *name, int size); diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index 07559e7c4c4c..eabd271f68b3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -68,6 +68,8 @@ static int nvkm_engine_fini(struct nvkm_subdev *obj, bool suspend) { struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); + if (engine->subdev.object.oclass) + return engine->subdev.object.oclass->ofuncs->fini(&engine->subdev.object, suspend); if (engine->func->fini) return engine->func->fini(engine, suspend); return 0; @@ -86,6 +88,9 @@ nvkm_engine_init(struct nvkm_subdev *obj) return ret; } + if (engine->subdev.object.oclass) + return engine->subdev.object.oclass->ofuncs->init(&engine->subdev.object); + if (engine->func->oneinit && !engine->subdev.oneinit) { nvkm_trace(subdev, "one-time init running...\n"); time = ktime_to_us(ktime_get()); @@ -110,6 +115,10 @@ static void * nvkm_engine_dtor(struct nvkm_subdev *obj) { struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); + if (engine->subdev.object.oclass) { + engine->subdev.object.oclass->ofuncs->dtor(&engine->subdev.object); + return NULL; + } if (engine->func->dtor) return engine->func->dtor(engine); return engine; @@ -201,5 +210,6 @@ nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj, INIT_LIST_HEAD(&engine->contexts); spin_lock_init(&engine->lock); + engine->subdev.func = &nvkm_engine_func; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index 6e5ff942a6da..d9c26e40ae32 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -91,7 +91,7 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) struct nvkm_object *engctx = NULL; struct nvkm_object *object = NULL; struct nvkm_parent *parent; - struct nvkm_object *engine; + struct nvkm_engine *engine; struct nvkm_oclass *oclass; u32 _handle, _oclass; int ret; @@ -117,7 +117,8 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) parent = nv_parent(handle->object); /* check that parent supports the requested subclass */ - ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass); + ret = nvkm_parent_sclass(&parent->object, _oclass, + (struct nvkm_object **)&engine, &oclass); if (ret) { nvif_debug(&parent->object, "illegal class 0x%04x\n", _oclass); goto fail_class; @@ -128,18 +129,20 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) * state calculated at init (ie. default context construction) */ if (engine) { - ret = nvkm_object_inc(engine); - if (ret) + engine = nvkm_engine_ref(engine); + if (IS_ERR(engine)) { + ret = PTR_ERR(engine); + engine = NULL; goto fail_class; + } } /* if engine requires it, create a context object to insert * between the parent and its children (eg. PGRAPH context) */ - if (engine && nv_engine(engine)->cclass) { - ret = nvkm_object_old(&parent->object, engine, - nv_engine(engine)->cclass, - data, size, &engctx); + if (engine && engine->cclass) { + ret = nvkm_object_old(&parent->object, &engine->subdev.object, + engine->cclass, data, size, &engctx); if (ret) goto fail_engctx; } else { @@ -147,7 +150,8 @@ nvkm_ioctl_new(struct nvkm_handle *handle, void *data, u32 size) } /* finally, create new object and bind it to its handle */ - ret = nvkm_object_old(engctx, engine, oclass, data, size, &object); + ret = nvkm_object_old(engctx, &engine->subdev.object, oclass, + data, size, &object); client->data = object; if (ret) goto fail_ctor; @@ -178,8 +182,7 @@ fail_init: fail_ctor: nvkm_object_ref(NULL, &engctx); fail_engctx: - if (engine) - nvkm_object_dec(engine, false); + nvkm_engine_unref(&engine); fail_class: return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c index 0abee7816874..0680eae072cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/object.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c @@ -201,6 +201,7 @@ nvkm_object_del(struct nvkm_object **pobject) if (object && !WARN_ON(!object->func)) { if (object->func->dtor) *pobject = object->func->dtor(object); + nvkm_engine_unref(&object->engine); kfree(*pobject); *pobject = NULL; } @@ -212,7 +213,7 @@ nvkm_object_ctor(const struct nvkm_object_func *func, { object->func = func; object->client = oclass->client; - object->engine = oclass->engine; + object->engine = nvkm_engine_ref(oclass->engine); object->oclass_name = oclass->base.oclass; object->handle = oclass->handle; object->parent = oclass->parent; @@ -251,10 +252,11 @@ nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, } int -nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, +nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engobj, struct nvkm_oclass *oclass, u32 pclass, int size, void **pobject) { + struct nvkm_engine *engine = engobj ? nv_engine(engobj) : NULL; struct nvkm_object *object; object = *pobject = kzalloc(size, GFP_KERNEL); @@ -262,7 +264,7 @@ nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, return -ENOMEM; nvkm_object_ref(parent, &object->parent); - nvkm_object_ref(engine, (struct nvkm_object **)&object->engine); + object->engine = nvkm_engine_ref(engine); object->oclass = oclass; object->pclass = pclass; atomic_set(&object->refcount, 1); @@ -287,7 +289,7 @@ _nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, void nvkm_object_destroy(struct nvkm_object *object) { - nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine); + nvkm_engine_unref(&object->engine); nvkm_object_ref(NULL, &object->parent); kfree(object); } @@ -333,7 +335,8 @@ nvkm_object_old(struct nvkm_object *parent, struct nvkm_object *engine, } if (ret == 0) { - atomic_set(&object->refcount, 1); + if (!nv_iclass(object, NV_SUBDEV_CLASS)) + atomic_set(&object->refcount, 1); } return 0; @@ -370,14 +373,6 @@ nvkm_object_inc(struct nvkm_object *object) goto fail_parent; } - if (object->engine) { - mutex_lock(&nv_subdev(object->engine)->mutex); - ret = nvkm_object_inc(&object->engine->subdev.object); - mutex_unlock(&nv_subdev(object->engine)->mutex); - if (ret) - goto fail_engine; - } - ret = nvkm_object_init(object); atomic_set(&object->usecount, 1); if (ret) @@ -386,12 +381,6 @@ nvkm_object_inc(struct nvkm_object *object) return 0; fail_self: - if (object->engine) { - mutex_lock(&nv_subdev(object->engine)->mutex); - nvkm_object_dec(&object->engine->subdev.object, false); - mutex_unlock(&nv_subdev(object->engine)->mutex); - } -fail_engine: if (object->parent) nvkm_object_dec(object->parent, false); fail_parent: @@ -405,12 +394,6 @@ nvkm_object_decf(struct nvkm_object *object) nvkm_object_fini(object, false); atomic_set(&object->usecount, 0); - if (object->engine) { - mutex_lock(&nv_subdev(object->engine)->mutex); - nvkm_object_dec(&object->engine->subdev.object, false); - mutex_unlock(&nv_subdev(object->engine)->mutex); - } - if (object->parent) nvkm_object_dec(object->parent, false); @@ -427,14 +410,6 @@ nvkm_object_decs(struct nvkm_object *object) if (ret) return ret; - if (object->engine) { - mutex_lock(&nv_subdev(object->engine)->mutex); - ret = nvkm_object_dec(&object->engine->subdev.object, true); - mutex_unlock(&nv_subdev(object->engine)->mutex); - if (ret) - goto fail_engine; - } - if (object->parent) { ret = nvkm_object_dec(object->parent, true); if (ret) @@ -444,13 +419,6 @@ nvkm_object_decs(struct nvkm_object *object) return 0; fail_parent: - if (object->engine) { - mutex_lock(&nv_subdev(object->engine)->mutex); - nvkm_object_inc(&object->engine->subdev.object); - mutex_unlock(&nv_subdev(object->engine)->mutex); - } - -fail_engine: nvkm_object_init(object); return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c index 5af13d8be2f5..b0647c233478 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c @@ -74,6 +74,12 @@ nvkm_subdev_name[64] = { void nvkm_subdev_intr(struct nvkm_subdev *subdev) { + if (subdev->object.oclass) { + if (subdev->intr) + subdev->intr(subdev); + return; + } + if (subdev->func->intr) subdev->func->intr(subdev); } @@ -85,10 +91,18 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) const char *action = suspend ? "suspend" : "fini"; u32 pmc_enable = subdev->pmc_enable; s64 time; + int ret; nvkm_trace(subdev, "%s running...\n", action); time = ktime_to_us(ktime_get()); + if (!subdev->func) { + ret = subdev->object.oclass->ofuncs->fini(&subdev->object, suspend); + if (ret) + return ret; + goto done; + } + if (subdev->func->fini) { int ret = subdev->func->fini(subdev, suspend); if (ret) { @@ -104,6 +118,7 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) nvkm_rd32(device, 0x000200); } +done: time = ktime_to_us(ktime_get()) - time; nvkm_trace(subdev, "%s completed in %lldus\n", action, time); return 0; @@ -117,7 +132,7 @@ nvkm_subdev_preinit(struct nvkm_subdev *subdev) nvkm_trace(subdev, "preinit running...\n"); time = ktime_to_us(ktime_get()); - if (subdev->func->preinit) { + if (!subdev->object.oclass && subdev->func->preinit) { int ret = subdev->func->preinit(subdev); if (ret) { nvkm_error(subdev, "preinit failed, %d\n", ret); @@ -139,6 +154,13 @@ nvkm_subdev_init(struct nvkm_subdev *subdev) nvkm_trace(subdev, "init running...\n"); time = ktime_to_us(ktime_get()); + if (!subdev->func) { + ret = subdev->object.oclass->ofuncs->init(&subdev->object); + if (ret) + return ret; + goto done; + } + if (subdev->func->oneinit && !subdev->oneinit) { s64 time; nvkm_trace(subdev, "one-time init running...\n"); @@ -162,6 +184,7 @@ nvkm_subdev_init(struct nvkm_subdev *subdev) } } +done: time = ktime_to_us(ktime_get()) - time; nvkm_trace(subdev, "init completed in %lldus\n", time); return 0; @@ -172,6 +195,12 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) { struct nvkm_subdev *subdev = *psubdev; s64 time; + + if (subdev && subdev->object.oclass) { + subdev->object.oclass->ofuncs->dtor(&subdev->object); + return; + } + if (subdev && !WARN_ON(!subdev->func)) { nvkm_trace(subdev, "destroy running...\n"); time = ktime_to_us(ktime_get()); @@ -211,8 +240,10 @@ nvkm_subdev(void *obj, int idx) struct nvkm_object *object = nv_object(obj); while (object && !nv_iclass(object, NV_SUBDEV_CLASS)) object = object->parent; - if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) - object = nv_device(obj)->subdev[idx]; + if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) { + struct nvkm_device *device = nv_device(obj); + return nvkm_device_subdev(device, idx); + } return object ? nv_subdev(object) : NULL; } @@ -266,8 +297,6 @@ _nvkm_subdev_fini(struct nvkm_object *object, bool suspend) void nvkm_subdev_destroy(struct nvkm_subdev *subdev) { - int subidx = nv_hclass(subdev) & 0xff; - nv_device(subdev)->subdev[subidx] = NULL; nvkm_object_destroy(&subdev->object); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c index f42706e1d5db..fdca90bc8f0e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.c @@ -40,21 +40,19 @@ nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) } #endif -int -nvkm_acpi_fini(struct nvkm_device *device, bool suspend) +void +nvkm_acpi_fini(struct nvkm_device *device) { #ifdef CONFIG_ACPI unregister_acpi_notifier(&device->acpi.nb); #endif - return 0; } -int +void nvkm_acpi_init(struct nvkm_device *device) { #ifdef CONFIG_ACPI device->acpi.nb.notifier_call = nvkm_acpi_ntfy; register_acpi_notifier(&device->acpi.nb); #endif - return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h index 82dd359ddfa4..1bbe76e0740a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.h @@ -3,6 +3,6 @@ #include struct nvkm_device; -int nvkm_acpi_init(struct nvkm_device *); -int nvkm_acpi_fini(struct nvkm_device *, bool); +void nvkm_acpi_init(struct nvkm_device *); +void nvkm_acpi_fini(struct nvkm_device *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index c7d8e2902c6c..b3f333602582 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -67,6 +67,1916 @@ nvkm_device_list(u64 *name, int size) return nr; } +static const struct nvkm_device_chip +null_chipset = { + .name = "NULL", +// .bios = nvkm_bios_new, +}; + +static const struct nvkm_device_chip +nv4_chipset = { + .name = "NV04", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv04_devinit_new, +// .fb = nv04_fb_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv04_fifo_new, +// .gr = nv04_gr_new, +// .sw = nv04_sw_new, +}; + +static const struct nvkm_device_chip +nv5_chipset = { + .name = "NV05", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv05_devinit_new, +// .fb = nv04_fb_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv04_fifo_new, +// .gr = nv04_gr_new, +// .sw = nv04_sw_new, +}; + +static const struct nvkm_device_chip +nv10_chipset = { + .name = "NV10", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv10_devinit_new, +// .fb = nv10_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .gr = nv10_gr_new, +}; + +static const struct nvkm_device_chip +nv11_chipset = { + .name = "NV11", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv10_devinit_new, +// .fb = nv10_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv10_fifo_new, +// .gr = nv10_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv15_chipset = { + .name = "NV15", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv10_devinit_new, +// .fb = nv10_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv10_fifo_new, +// .gr = nv10_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv17_chipset = { + .name = "NV17", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv10_devinit_new, +// .fb = nv10_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv10_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv18_chipset = { + .name = "NV18", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv10_devinit_new, +// .fb = nv10_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv10_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv1a_chipset = { + .name = "nForce", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv1a_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv10_fifo_new, +// .gr = nv10_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv1f_chipset = { + .name = "nForce2", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv1a_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv10_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv20_chipset = { + .name = "NV20", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv20_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv20_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv25_chipset = { + .name = "NV25", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv25_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv25_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv28_chipset = { + .name = "NV28", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv25_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv25_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv2a_chipset = { + .name = "NV2A", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv25_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv2a_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv30_chipset = { + .name = "NV30", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv30_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv30_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv31_chipset = { + .name = "NV31", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv30_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv30_gr_new, +// .mpeg = nv31_mpeg_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv34_chipset = { + .name = "NV34", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv10_devinit_new, +// .fb = nv10_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv34_gr_new, +// .mpeg = nv31_mpeg_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv35_chipset = { + .name = "NV35", +// .bios = nvkm_bios_new, +// .bus = nv04_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv35_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv35_gr_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv36_chipset = { + .name = "NV36", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv04_clk_new, +// .devinit = nv20_devinit_new, +// .fb = nv36_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv04_instmem_new, +// .mc = nv04_mc_new, +// .mmu = nv04_mmu_new, +// .timer = nv04_timer_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv17_fifo_new, +// .gr = nv35_gr_new, +// .mpeg = nv31_mpeg_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv40_chipset = { + .name = "NV40", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv40_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv04_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv40_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv41_chipset = { + .name = "NV41", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv41_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv41_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv40_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv42_chipset = { + .name = "NV42", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv41_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv41_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv40_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv43_chipset = { + .name = "NV43", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv41_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv41_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv40_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv44_chipset = { + .name = "NV44", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv44_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv44_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv45_chipset = { + .name = "NV45", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv40_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv04_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv46_chipset = { + .name = "G72", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv46_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv44_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv47_chipset = { + .name = "G70", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv47_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv41_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv49_chipset = { + .name = "G71", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv49_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv41_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv4a_chipset = { + .name = "NV44A", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv44_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv44_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv4b_chipset = { + .name = "G73", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv49_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv40_mc_new, +// .mmu = nv41_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv4c_chipset = { + .name = "C61", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv46_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv4c_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv4e_chipset = { + .name = "C51", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv4e_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv4e_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv4c_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv50_chipset = { + .name = "G80", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = nv50_bus_new, +// .clk = nv50_clk_new, +// .devinit = nv50_devinit_new, +// .fb = nv50_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = nv50_gpio_new, +// .i2c = nv50_i2c_new, +// .imem = nv50_instmem_new, +// .mc = nv50_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = nv50_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv50_disp_new, +// .dma = nv50_dma_new, +// .fifo = nv50_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = nv50_mpeg_new, +// .pm = nv50_pm_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nv63_chipset = { + .name = "C73", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv46_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv4c_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv67_chipset = { + .name = "C67", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv46_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv4c_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv68_chipset = { + .name = "C68", +// .bios = nvkm_bios_new, +// .bus = nv31_bus_new, +// .clk = nv40_clk_new, +// .devinit = nv1a_devinit_new, +// .fb = nv46_fb_new, +// .gpio = nv10_gpio_new, +// .i2c = nv04_i2c_new, +// .imem = nv40_instmem_new, +// .mc = nv4c_mc_new, +// .mmu = nv44_mmu_new, +// .therm = nv40_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = nv04_disp_new, +// .dma = nv04_dma_new, +// .fifo = nv40_fifo_new, +// .gr = nv40_gr_new, +// .mpeg = nv44_mpeg_new, +// .pm = nv40_pm_new, +// .sw = nv10_sw_new, +}; + +static const struct nvkm_device_chip +nv84_chipset = { + .name = "G84", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = nv50_bus_new, +// .clk = g84_clk_new, +// .devinit = g84_devinit_new, +// .fb = g84_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = nv50_gpio_new, +// .i2c = nv50_i2c_new, +// .imem = nv50_instmem_new, +// .mc = nv50_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .bsp = g84_bsp_new, +// .cipher = g84_cipher_new, +// .disp = g84_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .pm = g84_pm_new, +// .sw = nv50_sw_new, +// .vp = g84_vp_new, +}; + +static const struct nvkm_device_chip +nv86_chipset = { + .name = "G86", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = nv50_bus_new, +// .clk = g84_clk_new, +// .devinit = g84_devinit_new, +// .fb = g84_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = nv50_gpio_new, +// .i2c = nv50_i2c_new, +// .imem = nv50_instmem_new, +// .mc = nv50_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .bsp = g84_bsp_new, +// .cipher = g84_cipher_new, +// .disp = g84_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .pm = g84_pm_new, +// .sw = nv50_sw_new, +// .vp = g84_vp_new, +}; + +static const struct nvkm_device_chip +nv92_chipset = { + .name = "G92", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = nv50_bus_new, +// .clk = g84_clk_new, +// .devinit = g84_devinit_new, +// .fb = g84_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = nv50_gpio_new, +// .i2c = nv50_i2c_new, +// .imem = nv50_instmem_new, +// .mc = nv50_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .bsp = g84_bsp_new, +// .cipher = g84_cipher_new, +// .disp = g84_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .pm = g84_pm_new, +// .sw = nv50_sw_new, +// .vp = g84_vp_new, +}; + +static const struct nvkm_device_chip +nv94_chipset = { + .name = "G94", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = g84_clk_new, +// .devinit = g84_devinit_new, +// .fb = g84_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g94_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .bsp = g84_bsp_new, +// .cipher = g84_cipher_new, +// .disp = g94_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .pm = g84_pm_new, +// .sw = nv50_sw_new, +// .vp = g84_vp_new, +}; + +static const struct nvkm_device_chip +nv96_chipset = { + .name = "G96", +// .bios = nvkm_bios_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .fuse = nv50_fuse_new, +// .clk = g84_clk_new, +// .therm = g84_therm_new, +// .mxm = nv50_mxm_new, +// .devinit = g84_devinit_new, +// .mc = g94_mc_new, +// .bus = g94_bus_new, +// .timer = nv04_timer_new, +// .fb = g84_fb_new, +// .imem = nv50_instmem_new, +// .mmu = nv50_mmu_new, +// .bar = nv50_bar_new, +// .volt = nv40_volt_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .sw = nv50_sw_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .vp = g84_vp_new, +// .cipher = g84_cipher_new, +// .bsp = g84_bsp_new, +// .disp = g94_disp_new, +// .pm = g84_pm_new, +}; + +static const struct nvkm_device_chip +nv98_chipset = { + .name = "G98", +// .bios = nvkm_bios_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .fuse = nv50_fuse_new, +// .clk = g84_clk_new, +// .therm = g84_therm_new, +// .mxm = nv50_mxm_new, +// .devinit = g98_devinit_new, +// .mc = g98_mc_new, +// .bus = g94_bus_new, +// .timer = nv04_timer_new, +// .fb = g84_fb_new, +// .imem = nv50_instmem_new, +// .mmu = nv50_mmu_new, +// .bar = nv50_bar_new, +// .volt = nv40_volt_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .sw = nv50_sw_new, +// .gr = nv50_gr_new, +// .mspdec = g98_mspdec_new, +// .sec = g98_sec_new, +// .msvld = g98_msvld_new, +// .msppp = g98_msppp_new, +// .disp = g94_disp_new, +// .pm = g84_pm_new, +}; + +static const struct nvkm_device_chip +nva0_chipset = { + .name = "GT200", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = g84_clk_new, +// .devinit = g84_devinit_new, +// .fb = g84_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = nv50_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .bsp = g84_bsp_new, +// .cipher = g84_cipher_new, +// .disp = gt200_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .pm = gt200_pm_new, +// .sw = nv50_sw_new, +// .vp = g84_vp_new, +}; + +static const struct nvkm_device_chip +nva3_chipset = { + .name = "GT215", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = gt215_clk_new, +// .devinit = gt215_devinit_new, +// .fb = gt215_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gt215_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gt215_ce_new, +// .disp = gt215_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mpeg = g84_mpeg_new, +// .mspdec = g98_mspdec_new, +// .msppp = g98_msppp_new, +// .msvld = g98_msvld_new, +// .pm = gt215_pm_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nva5_chipset = { + .name = "GT216", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = gt215_clk_new, +// .devinit = gt215_devinit_new, +// .fb = gt215_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gt215_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gt215_ce_new, +// .disp = gt215_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mspdec = g98_mspdec_new, +// .msppp = g98_msppp_new, +// .msvld = g98_msvld_new, +// .pm = gt215_pm_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nva8_chipset = { + .name = "GT218", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = gt215_clk_new, +// .devinit = gt215_devinit_new, +// .fb = gt215_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gt215_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gt215_ce_new, +// .disp = gt215_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mspdec = g98_mspdec_new, +// .msppp = g98_msppp_new, +// .msvld = g98_msvld_new, +// .pm = gt215_pm_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nvaa_chipset = { + .name = "MCP77/MCP78", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = mcp77_clk_new, +// .devinit = g98_devinit_new, +// .fb = mcp77_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = g94_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mspdec = g98_mspdec_new, +// .msppp = g98_msppp_new, +// .msvld = g98_msvld_new, +// .pm = g84_pm_new, +// .sec = g98_sec_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nvac_chipset = { + .name = "MCP79/MCP7A", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = mcp77_clk_new, +// .devinit = g98_devinit_new, +// .fb = mcp77_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = g84_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .disp = g94_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mspdec = g98_mspdec_new, +// .msppp = g98_msppp_new, +// .msvld = g98_msvld_new, +// .pm = g84_pm_new, +// .sec = g98_sec_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nvaf_chipset = { + .name = "MCP89", +// .bar = nv50_bar_new, +// .bios = nvkm_bios_new, +// .bus = g94_bus_new, +// .clk = gt215_clk_new, +// .devinit = mcp89_devinit_new, +// .fb = mcp89_fb_new, +// .fuse = nv50_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .imem = nv50_instmem_new, +// .mc = g98_mc_new, +// .mmu = nv50_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gt215_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gt215_ce_new, +// .disp = gt215_disp_new, +// .dma = nv50_dma_new, +// .fifo = g84_fifo_new, +// .gr = nv50_gr_new, +// .mspdec = g98_mspdec_new, +// .msppp = g98_msppp_new, +// .msvld = g98_msvld_new, +// .pm = gt215_pm_new, +// .sw = nv50_sw_new, +}; + +static const struct nvkm_device_chip +nvc0_chipset = { + .name = "GF100", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf100_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .ce[1] = gf100_ce1_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf100_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf100_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvc1_chipset = { + .name = "GF108", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf108_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf108_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvc3_chipset = { + .name = "GF106", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf104_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf100_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvc4_chipset = { + .name = "GF104", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf100_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .ce[1] = gf100_ce1_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf104_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf100_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvc8_chipset = { + .name = "GF110", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf100_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .ce[1] = gf100_ce1_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf110_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf100_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvce_chipset = { + .name = "GF114", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf100_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .ce[1] = gf100_ce1_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf104_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf100_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvcf_chipset = { + .name = "GF116", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = g94_gpio_new, +// .i2c = g94_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf100_pmu_new, +// .therm = gt215_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .disp = gt215_disp_new, +// .dma = gf100_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf104_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf100_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvd7_chipset = { + .name = "GF117", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gf110_gpio_new, +// .i2c = gf117_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .ce[0] = gf100_ce0_new, +// .disp = gf119_disp_new, +// .dma = gf119_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf117_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf117_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvd9_chipset = { + .name = "GF119", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gf100_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gf100_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gf110_gpio_new, +// .i2c = gf110_i2c_new, +// .ibus = gf100_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gf100_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf110_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gf100_ce0_new, +// .disp = gf119_disp_new, +// .dma = gf119_dma_new, +// .fifo = gf100_fifo_new, +// .gr = gf119_gr_new, +// .mspdec = gf100_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gf100_msvld_new, +// .pm = gf117_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nve4_chipset = { + .name = "GK104", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gk104_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk104_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk104_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk104_fifo_new, +// .gr = gk104_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .pm = gk104_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nve6_chipset = { + .name = "GK106", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gk104_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk104_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk104_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk104_fifo_new, +// .gr = gk104_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .pm = gk104_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nve7_chipset = { + .name = "GK107", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gk104_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gf110_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk104_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk104_fifo_new, +// .gr = gk104_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .pm = gk104_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvea_chipset = { + .name = "GK20A", +// .bar = gk20a_bar_new, +// .bus = gf100_bus_new, +// .clk = gk20a_clk_new, +// .fb = gk20a_fb_new, +// .fuse = gf100_fuse_new, +// .ibus = gk20a_ibus_new, +// .imem = gk20a_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .pmu = gk20a_pmu_new, +// .timer = gk20a_timer_new, +// .volt = gk20a_volt_new, +// .ce[2] = gk104_ce2_new, +// .dma = gf119_dma_new, +// .fifo = gk20a_fifo_new, +// .gr = gk20a_gr_new, +// .pm = gk104_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvf0_chipset = { + .name = "GK110", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gk104_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk110_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk110_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk104_fifo_new, +// .gr = gk110_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .pm = gk110_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nvf1_chipset = { + .name = "GK110B", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gf110_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gf106_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk110_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk110_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk104_fifo_new, +// .gr = gk110b_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .pm = gk110_pm_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv106_chipset = { + .name = "GK208B", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gk104_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk208_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk110_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk208_fifo_new, +// .gr = gk208_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv108_chipset = { + .name = "GK208", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gf100_devinit_new, +// .fb = gk104_fb_new, +// .fuse = gf100_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gk104_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gk104_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk208_pmu_new, +// .therm = gf110_therm_new, +// .timer = nv04_timer_new, +// .volt = nv40_volt_new, +// .ce[0] = gk104_ce0_new, +// .ce[1] = gk104_ce1_new, +// .ce[2] = gk104_ce2_new, +// .disp = gk110_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk208_fifo_new, +// .gr = gk208_gr_new, +// .mspdec = gk104_mspdec_new, +// .msppp = gf100_msppp_new, +// .msvld = gk104_msvld_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv117_chipset = { + .name = "GM107", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .clk = gk104_clk_new, +// .devinit = gm107_devinit_new, +// .fb = gm107_fb_new, +// .fuse = gm107_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gf110_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gm107_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk208_pmu_new, +// .therm = gm107_therm_new, +// .timer = gk20a_timer_new, +// .ce[0] = gk104_ce0_new, +// .ce[2] = gk104_ce2_new, +// .disp = gm107_disp_new, +// .dma = gf119_dma_new, +// .fifo = gk208_fifo_new, +// .gr = gm107_gr_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv124_chipset = { + .name = "GM204", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .devinit = gm204_devinit_new, +// .fb = gm107_fb_new, +// .fuse = gm107_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gm204_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gm107_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk208_pmu_new, +// .timer = gk20a_timer_new, +// .ce[0] = gm204_ce0_new, +// .ce[1] = gm204_ce1_new, +// .ce[2] = gm204_ce2_new, +// .disp = gm204_disp_new, +// .dma = gf119_dma_new, +// .fifo = gm204_fifo_new, +// .gr = gm204_gr_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv126_chipset = { + .name = "GM206", +// .bar = gf100_bar_new, +// .bios = nvkm_bios_new, +// .bus = gf100_bus_new, +// .devinit = gm204_devinit_new, +// .fb = gm107_fb_new, +// .fuse = gm107_fuse_new, +// .gpio = gk104_gpio_new, +// .i2c = gm204_i2c_new, +// .ibus = gk104_ibus_new, +// .imem = nv50_instmem_new, +// .ltc = gm107_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .mxm = nv50_mxm_new, +// .pmu = gk208_pmu_new, +// .timer = gk20a_timer_new, +// .ce[0] = gm204_ce0_new, +// .ce[1] = gm204_ce1_new, +// .ce[2] = gm204_ce2_new, +// .disp = gm204_disp_new, +// .dma = gf119_dma_new, +// .fifo = gm204_fifo_new, +// .gr = gm206_gr_new, +// .sw = gf100_sw_new, +}; + +static const struct nvkm_device_chip +nv12b_chipset = { + .name = "GM20B", +// .bar = gk20a_bar_new, +// .bus = gf100_bus_new, +// .fb = gk20a_fb_new, +// .fuse = gm107_fuse_new, +// .ibus = gk20a_ibus_new, +// .imem = gk20a_instmem_new, +// .ltc = gm107_ltc_new, +// .mc = gk20a_mc_new, +// .mmu = gf100_mmu_new, +// .mmu = gf100_mmu_new, +// .timer = gk20a_timer_new, +// .ce[2] = gm204_ce2_new, +// .dma = gf119_dma_new, +// .fifo = gm20b_fifo_new, +// .gr = gm20b_gr_new, +// .sw = gf100_sw_new, +}; + #include #include @@ -116,45 +2026,129 @@ nvkm_device_event_func = { .ctor = nvkm_device_event_ctor, }; +struct nvkm_subdev * +nvkm_device_subdev(struct nvkm_device *device, int index) +{ + struct nvkm_engine *engine; + + if (device->disable_mask & (1ULL << index)) + return NULL; + + switch (index) { +#define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break + _(BAR , device->bar , &device->bar->subdev); + _(VBIOS , device->bios , &device->bios->subdev); + _(BUS , device->bus , &device->bus->subdev); + _(CLK , device->clk , &device->clk->subdev); + _(DEVINIT, device->devinit, &device->devinit->subdev); + _(FB , device->fb , &device->fb->subdev); + _(FUSE , device->fuse , &device->fuse->subdev); + _(GPIO , device->gpio , &device->gpio->subdev); + _(I2C , device->i2c , &device->i2c->subdev); + _(IBUS , device->ibus , device->ibus); + _(INSTMEM, device->imem , &device->imem->subdev); + _(LTC , device->ltc , &device->ltc->subdev); + _(MC , device->mc , &device->mc->subdev); + _(MMU , device->mmu , &device->mmu->subdev); + _(MXM , device->mxm , device->mxm); + _(PMU , device->pmu , &device->pmu->subdev); + _(THERM , device->therm , &device->therm->subdev); + _(TIMER , device->timer , &device->timer->subdev); + _(VOLT , device->volt , &device->volt->subdev); +#undef _ + default: + engine = nvkm_device_engine(device, index); + if (engine) + return &engine->subdev; + break; + } + return NULL; +} + +struct nvkm_engine * +nvkm_device_engine(struct nvkm_device *device, int index) +{ + if (device->disable_mask & (1ULL << index)) + return NULL; + + switch (index) { +#define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break + _(BSP , device->bsp , device->bsp); + _(CE0 , device->ce[0] , device->ce[0]); + _(CE1 , device->ce[1] , device->ce[1]); + _(CE2 , device->ce[2] , device->ce[2]); + _(CIPHER , device->cipher , device->cipher); + _(DISP , device->disp , &device->disp->engine); + _(DMAOBJ , device->dma , &device->dma->engine); + _(FIFO , device->fifo , &device->fifo->engine); + _(GR , device->gr , &device->gr->engine); + _(IFB , device->ifb , device->ifb); + _(ME , device->me , device->me); + _(MPEG , device->mpeg , device->mpeg); + _(MSENC , device->msenc , device->msenc); + _(MSPDEC , device->mspdec , device->mspdec); + _(MSPPP , device->msppp , device->msppp); + _(MSVLD , device->msvld , device->msvld); + _(PM , device->pm , &device->pm->engine); + _(SEC , device->sec , device->sec); + _(SW , device->sw , &device->sw->engine); + _(VIC , device->vic , device->vic); + _(VP , device->vp , device->vp); +#undef _ + default: + WARN_ON(1); + break; + } + return NULL; +} + int nvkm_device_fini(struct nvkm_device *device, bool suspend) { - struct nvkm_object *subdev; + const char *action = suspend ? "suspend" : "fini"; + struct nvkm_subdev *subdev; int ret, i; + s64 time; + + nvdev_trace(device, "%s running...\n", action); + time = ktime_to_us(ktime_get()); + + nvkm_acpi_fini(device); for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nvkm_object_dec(subdev, suspend); - if (ret && suspend) - goto fail; - } + if ((subdev = nvkm_device_subdev(device, i))) { + ret = nvkm_subdev_fini(subdev, suspend); + if (ret && suspend) + goto fail; } } - ret = nvkm_acpi_fini(device, suspend); if (device->func->fini) device->func->fini(device, suspend); + + time = ktime_to_us(ktime_get()) - time; + nvdev_trace(device, "%s completed in %lldus...\n", action, time); + return 0; + fail: - for (; ret && i < NVDEV_SUBDEV_NR; i++) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nvkm_object_inc(subdev); - if (ret) { - /* XXX */ - } - } + do { + if ((subdev = nvkm_device_subdev(device, i))) { + int rret = nvkm_subdev_init(subdev); + if (rret) + nvkm_fatal(subdev, "failed restart, %d\n", ret); } - } + } while (++i < NVDEV_SUBDEV_NR); + nvdev_trace(device, "%s failed with %d\n", action, ret); return ret; } -int +static int nvkm_device_preinit(struct nvkm_device *device) { - int ret; + struct nvkm_subdev *subdev; + int ret, i; s64 time; nvdev_trace(device, "preinit running...\n"); @@ -166,6 +2160,16 @@ nvkm_device_preinit(struct nvkm_device *device) goto fail; } + for (i = 0; i < NVDEV_SUBDEV_NR; i++) { + if ((subdev = nvkm_device_subdev(device, i))) { + ret = nvkm_subdev_preinit(subdev); + if (ret) + goto fail; + } + } + + /*XXX: devinit */ + time = ktime_to_us(ktime_get()) - time; nvdev_trace(device, "preinit completed in %lldus\n", time); return 0; @@ -178,19 +2182,21 @@ fail: int nvkm_device_init(struct nvkm_device *device) { - struct nvkm_object *subdev; + struct nvkm_subdev *subdev; int ret, i = 0, c; + s64 time; ret = nvkm_device_preinit(device); if (ret) return ret; - ret = nvkm_acpi_init(device); - if (ret) - goto fail; + nvkm_device_fini(device, false); + + nvdev_trace(device, "init running...\n"); + time = ktime_to_us(ktime_get()); for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) { -#define _(s,m) case s: if (device->oclass[s] && !device->subdev[s]) { \ +#define _(s,m) case s: if (device->oclass[s] && !device->m) { \ ret = nvkm_object_old(nv_object(device), NULL, \ device->oclass[s], NULL, (s), \ (struct nvkm_object **)&device->m); \ @@ -200,7 +2206,6 @@ nvkm_device_init(struct nvkm_device *device) } \ if (ret) \ goto fail; \ - device->subdev[s] = (struct nvkm_object *)device->m; \ } break switch (i) { _(NVDEV_SUBDEV_BAR , bar); @@ -259,29 +2264,27 @@ nvkm_device_init(struct nvkm_device *device) * subdev in turn as they're created. */ while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { - struct nvkm_object *subdev = device->subdev[c++]; - if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { - ret = nvkm_object_inc(subdev); + if ((subdev = nvkm_device_subdev(device, c++))) { + ret = nvkm_subdev_init(subdev); if (ret) goto fail; - } else - if (subdev) { - nvkm_subdev_reset(subdev); } } } - ret = 0; + nvkm_acpi_init(device); + + time = ktime_to_us(ktime_get()) - time; + nvdev_trace(device, "init completed in %lldus\n", time); + return 0; + fail: - for (--i; ret && i >= 0; i--) { - if ((subdev = device->subdev[i])) { - if (!nv_iclass(subdev, NV_ENGINE_CLASS)) - nvkm_object_dec(subdev, false); - } - } + do { + if ((subdev = nvkm_device_subdev(device, i))) + nvkm_subdev_fini(subdev, false); + } while (--i >= 0); - if (ret) - nvkm_acpi_fini(device, false); + nvdev_error(device, "init failed with %d\n", ret); return ret; } @@ -333,8 +2336,12 @@ nvkm_device_del(struct nvkm_device **pdevice) int i; if (device) { mutex_lock(&nv_devices_mutex); - for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) - nvkm_object_ref(NULL, &device->subdev[i]); + device->disable_mask = 0; + for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { + struct nvkm_subdev *subdev = + nvkm_device_subdev(device, i); + nvkm_subdev_del(&subdev); + } nvkm_event_fini(&device->event); @@ -363,6 +2370,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, bool detect, bool mmio, u64 subdev_mask, struct nvkm_device *device) { + struct nvkm_subdev *subdev; u64 mmio_base, mmio_size; u32 boot0, strap; void __iomem *map; @@ -373,13 +2381,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, if (nvkm_device_find_locked(handle)) goto done; - ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0, - true, &device->engine); - device->engine.subdev.object.parent = NULL; device->func = func; - if (ret) - goto done; - device->quirk = quirk; switch (type) { case NVKM_BUS_PCI: @@ -395,9 +2397,14 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->cfgopt = cfg; device->dbgopt = dbg; device->name = name; - list_add_tail(&device->head, &nv_devices); + ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0, + true, &device->engine); + device->engine.subdev.object.parent = NULL; + if (ret) + goto done; + ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); if (ret) goto done; @@ -482,12 +2489,83 @@ nvkm_device_ctor(const struct nvkm_device_func *func, break; } - if (ret) { + switch (!ret * device->chipset) { + case 0x004: device->chip = &nv4_chipset; break; + case 0x005: device->chip = &nv5_chipset; break; + case 0x010: device->chip = &nv10_chipset; break; + case 0x011: device->chip = &nv11_chipset; break; + case 0x015: device->chip = &nv15_chipset; break; + case 0x017: device->chip = &nv17_chipset; break; + case 0x018: device->chip = &nv18_chipset; break; + case 0x01a: device->chip = &nv1a_chipset; break; + case 0x01f: device->chip = &nv1f_chipset; break; + case 0x020: device->chip = &nv20_chipset; break; + case 0x025: device->chip = &nv25_chipset; break; + case 0x028: device->chip = &nv28_chipset; break; + case 0x02a: device->chip = &nv2a_chipset; break; + case 0x030: device->chip = &nv30_chipset; break; + case 0x031: device->chip = &nv31_chipset; break; + case 0x034: device->chip = &nv34_chipset; break; + case 0x035: device->chip = &nv35_chipset; break; + case 0x036: device->chip = &nv36_chipset; break; + case 0x040: device->chip = &nv40_chipset; break; + case 0x041: device->chip = &nv41_chipset; break; + case 0x042: device->chip = &nv42_chipset; break; + case 0x043: device->chip = &nv43_chipset; break; + case 0x044: device->chip = &nv44_chipset; break; + case 0x045: device->chip = &nv45_chipset; break; + case 0x046: device->chip = &nv46_chipset; break; + case 0x047: device->chip = &nv47_chipset; break; + case 0x049: device->chip = &nv49_chipset; break; + case 0x04a: device->chip = &nv4a_chipset; break; + case 0x04b: device->chip = &nv4b_chipset; break; + case 0x04c: device->chip = &nv4c_chipset; break; + case 0x04e: device->chip = &nv4e_chipset; break; + case 0x050: device->chip = &nv50_chipset; break; + case 0x063: device->chip = &nv63_chipset; break; + case 0x067: device->chip = &nv67_chipset; break; + case 0x068: device->chip = &nv68_chipset; break; + case 0x084: device->chip = &nv84_chipset; break; + case 0x086: device->chip = &nv86_chipset; break; + case 0x092: device->chip = &nv92_chipset; break; + case 0x094: device->chip = &nv94_chipset; break; + case 0x096: device->chip = &nv96_chipset; break; + case 0x098: device->chip = &nv98_chipset; break; + case 0x0a0: device->chip = &nva0_chipset; break; + case 0x0a3: device->chip = &nva3_chipset; break; + case 0x0a5: device->chip = &nva5_chipset; break; + case 0x0a8: device->chip = &nva8_chipset; break; + case 0x0aa: device->chip = &nvaa_chipset; break; + case 0x0ac: device->chip = &nvac_chipset; break; + case 0x0af: device->chip = &nvaf_chipset; break; + case 0x0c0: device->chip = &nvc0_chipset; break; + case 0x0c1: device->chip = &nvc1_chipset; break; + case 0x0c3: device->chip = &nvc3_chipset; break; + case 0x0c4: device->chip = &nvc4_chipset; break; + case 0x0c8: device->chip = &nvc8_chipset; break; + case 0x0ce: device->chip = &nvce_chipset; break; + case 0x0cf: device->chip = &nvcf_chipset; break; + case 0x0d7: device->chip = &nvd7_chipset; break; + case 0x0d9: device->chip = &nvd9_chipset; break; + case 0x0e4: device->chip = &nve4_chipset; break; + case 0x0e6: device->chip = &nve6_chipset; break; + case 0x0e7: device->chip = &nve7_chipset; break; + case 0x0ea: device->chip = &nvea_chipset; break; + case 0x0f0: device->chip = &nvf0_chipset; break; + case 0x0f1: device->chip = &nvf1_chipset; break; + case 0x106: device->chip = &nv106_chipset; break; + case 0x108: device->chip = &nv108_chipset; break; + case 0x117: device->chip = &nv117_chipset; break; + case 0x124: device->chip = &nv124_chipset; break; + case 0x126: device->chip = &nv126_chipset; break; + case 0x12b: device->chip = &nv12b_chipset; break; + default: nvdev_error(device, "unknown chipset (%08x)\n", boot0); goto done; } - nvdev_info(device, "NVIDIA %s (%08x)\n", device->cname, boot0); + nvdev_info(device, "NVIDIA %s (%08x)\n", + device->chip->name, boot0); /* determine frequency of timing crystal */ if ( device->card_type <= NV_10 || device->chipset < 0x17 || @@ -503,10 +2581,13 @@ nvkm_device_ctor(const struct nvkm_device_func *func, case 0x00400040: device->crystal = 25000; break; } } else { - device->cname = "NULL"; + device->chip = &null_chipset; device->oclass[NVDEV_SUBDEV_VBIOS] = &nvkm_bios_oclass; } + if (!device->name) + device->name = device->chip->name; + if (mmio) { device->pri = ioremap(mmio_base, mmio_size); if (!device->pri) { @@ -523,6 +2604,72 @@ nvkm_device_ctor(const struct nvkm_device_func *func, atomic_set(&device->engine.subdev.object.usecount, 2); mutex_init(&device->mutex); + + for (i = 0; i < NVDEV_SUBDEV_NR; i++) { +#define _(s,m) case s: \ + if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ + ret = device->chip->m(device, (s), &device->m); \ + if (ret) { \ + subdev = nvkm_device_subdev(device, (s)); \ + nvkm_subdev_del(&subdev); \ + device->m = NULL; \ + if (ret != -ENODEV) { \ + nvdev_error(device, "%s ctor failed, %d\n", \ + nvkm_subdev_name[s], ret); \ + goto done; \ + } \ + } \ + } \ + break + switch (i) { + _(NVDEV_SUBDEV_BAR , bar); + _(NVDEV_SUBDEV_VBIOS , bios); + _(NVDEV_SUBDEV_BUS , bus); + _(NVDEV_SUBDEV_CLK , clk); + _(NVDEV_SUBDEV_DEVINIT, devinit); + _(NVDEV_SUBDEV_FB , fb); + _(NVDEV_SUBDEV_FUSE , fuse); + _(NVDEV_SUBDEV_GPIO , gpio); + _(NVDEV_SUBDEV_I2C , i2c); + _(NVDEV_SUBDEV_IBUS , ibus); + _(NVDEV_SUBDEV_INSTMEM, imem); + _(NVDEV_SUBDEV_LTC , ltc); + _(NVDEV_SUBDEV_MC , mc); + _(NVDEV_SUBDEV_MMU , mmu); + _(NVDEV_SUBDEV_MXM , mxm); + _(NVDEV_SUBDEV_PMU , pmu); + _(NVDEV_SUBDEV_THERM , therm); + _(NVDEV_SUBDEV_TIMER , timer); + _(NVDEV_SUBDEV_VOLT , volt); + _(NVDEV_ENGINE_BSP , bsp); + _(NVDEV_ENGINE_CE0 , ce[0]); + _(NVDEV_ENGINE_CE1 , ce[1]); + _(NVDEV_ENGINE_CE2 , ce[2]); + _(NVDEV_ENGINE_CIPHER , cipher); + _(NVDEV_ENGINE_DISP , disp); + _(NVDEV_ENGINE_DMAOBJ , dma); + _(NVDEV_ENGINE_FIFO , fifo); + _(NVDEV_ENGINE_GR , gr); + _(NVDEV_ENGINE_IFB , ifb); + _(NVDEV_ENGINE_ME , me); + _(NVDEV_ENGINE_MPEG , mpeg); + _(NVDEV_ENGINE_MSENC , msenc); + _(NVDEV_ENGINE_MSPDEC , mspdec); + _(NVDEV_ENGINE_MSPPP , msppp); + _(NVDEV_ENGINE_MSVLD , msvld); + _(NVDEV_ENGINE_PM , pm); + _(NVDEV_ENGINE_SEC , sec); + _(NVDEV_ENGINE_SW , sw); + _(NVDEV_ENGINE_VIC , vic); + _(NVDEV_ENGINE_VP , vp); + default: + WARN_ON(1); + continue; + } +#undef _ + } + + ret = 0; done: mutex_unlock(&nv_devices_mutex); return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index d8ddd228491a..cc152e78d0b2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -23,44 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - int gf100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xc0: - device->cname = "GF100"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -93,7 +60,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc4: - device->cname = "GF104"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -126,7 +92,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc3: - device->cname = "GF106"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -158,7 +123,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xce: - device->cname = "GF114"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -191,7 +155,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xcf: - device->cname = "GF116"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -223,7 +186,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc1: - device->cname = "GF108"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -255,7 +217,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; case 0xc8: - device->cname = "GF110"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -288,7 +249,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xd9: - device->cname = "GF119"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; @@ -320,7 +280,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; case 0xd7: - device->cname = "GF117"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 4e0d30944359..8811a40e8727 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -23,44 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - int gk104_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xe4: - device->cname = "GK104"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; @@ -94,7 +61,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: - device->cname = "GK107"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; @@ -128,7 +94,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: - device->cname = "GK106"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; @@ -162,7 +127,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: - device->cname = "GK20A"; device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; @@ -184,7 +148,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; break; case 0xf0: - device->cname = "GK110"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; @@ -218,7 +181,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: - device->cname = "GK110B"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; @@ -252,7 +214,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: - device->cname = "GK208B"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; @@ -285,7 +246,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; case 0x108: - device->cname = "GK208"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gk104_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index cd979543cdff..41bfec2dd63a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -23,44 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - int gm100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x117: - device->cname = "GM107"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass; @@ -100,7 +67,6 @@ gm100_identify(struct nvkm_device *device) #endif break; case 0x124: - device->cname = "GM204"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; @@ -141,7 +107,6 @@ gm100_identify(struct nvkm_device *device) #endif break; case 0x126: - device->cname = "GM206"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = gk104_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = gm204_i2c_oclass; @@ -182,7 +147,6 @@ gm100_identify(struct nvkm_device *device) #endif break; case 0x12b: - device->cname = "GM20B"; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index ec357da766e5..5245b78794f9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -23,29 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - int nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->cname = "NV04"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; @@ -63,7 +45,6 @@ nv04_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: - device->cname = "NV05"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 37997e848d29..3794c53cfbda 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -23,30 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - int nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: - device->cname = "NV10"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -63,7 +44,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: - device->cname = "NV15"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -82,7 +62,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: - device->cname = "NV16"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -101,7 +80,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: - device->cname = "nForce"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -120,7 +98,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: - device->cname = "NV11"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -139,7 +116,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: - device->cname = "NV17"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -158,7 +134,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: - device->cname = "nForce2"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -177,7 +152,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: - device->cname = "NV18"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index a0d414dcc1fd..9acdadeea0ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -23,31 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - int nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->cname = "NV20"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -66,7 +46,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: - device->cname = "NV25"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -85,7 +64,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: - device->cname = "NV28"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -104,7 +82,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: - device->cname = "NV2A"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index ea1739739e5f..3d687d760601 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -23,31 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - int nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->cname = "NV30"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -66,7 +46,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: - device->cname = "NV35"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -85,7 +64,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: - device->cname = "NV31"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -105,7 +83,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x36: - device->cname = "NV36"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -125,7 +102,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x34: - device->cname = "NV34"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 9c7aa8d0ebd4..35fb2f92d171 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -23,35 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - int nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: - device->cname = "NV40"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -74,7 +50,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: - device->cname = "NV41"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -97,7 +72,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: - device->cname = "NV42"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -120,7 +94,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: - device->cname = "NV43"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -143,7 +116,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: - device->cname = "NV45"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -166,7 +138,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: - device->cname = "G70"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -189,7 +160,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: - device->cname = "G71"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -212,7 +182,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: - device->cname = "G73"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -235,7 +204,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: - device->cname = "NV44"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -258,7 +226,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: - device->cname = "G72"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -281,7 +248,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: - device->cname = "NV44A"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -304,7 +270,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: - device->cname = "C61"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -327,7 +292,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: - device->cname = "C51"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; @@ -350,7 +314,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: - device->cname = "C73"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -373,7 +336,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: - device->cname = "C67"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; @@ -396,7 +358,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: - device->cname = "C68"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 3c97dba02fc4..56a443a1c74e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -23,46 +23,11 @@ */ #include "priv.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - int nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: - device->cname = "G80"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; @@ -88,7 +53,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: - device->cname = "G84"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; @@ -117,7 +81,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x86: - device->cname = "G86"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; @@ -146,7 +109,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x92: - device->cname = "G92"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; @@ -175,7 +137,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x94: - device->cname = "G94"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -204,7 +165,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x96: - device->cname = "G96"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -233,7 +193,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x98: - device->cname = "G98"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -262,7 +221,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa0: - device->cname = "G200"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; @@ -291,7 +249,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; break; case 0xaa: - device->cname = "MCP77/MCP78"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -320,7 +277,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xac: - device->cname = "MCP79/MCP7A"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -349,7 +305,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa3: - device->cname = "GT215"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -380,7 +335,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa5: - device->cname = "GT216"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -410,7 +364,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa8: - device->cname = "GT218"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; @@ -440,7 +393,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xaf: - device->cname = "MCP89"; device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass; device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass; device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index df9c1550301f..59e902662408 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -2,6 +2,42 @@ #define __NVKM_DEVICE_PRIV_H__ #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + int nvkm_device_ctor(const struct nvkm_device_func *, const struct nvkm_device_quirk *, void *, enum nv_bus_type type, u64 handle, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index cb3f3deefb01..0df54c657469 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -107,8 +107,8 @@ nvkm_udevice_info(struct nvkm_object *object, void *data, u32 size) if (imem && args->v0.ram_size > 0) args->v0.ram_user = args->v0.ram_user - imem->reserved; - strncpy(args->v0.chip, device->cname, sizeof(args->v0.chip)); - strncpy(args->v0.name, device->cname, sizeof(args->v0.name)); + strncpy(args->v0.chip, device->chip->name, sizeof(args->v0.chip)); + strncpy(args->v0.name, device->name, sizeof(args->v0.name)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 52f6a6e49216..ac39cb7e7299 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -138,7 +138,7 @@ _nvkm_falcon_init(struct nvkm_object *object) ret = request_firmware(&fw, name, nv_device_base(device)); if (ret) { nvkm_error(subdev, "unable to load firmware data\n"); - return ret; + return -ENODEV; } falcon->data.data = vmemdup(fw->data, fw->size); @@ -153,7 +153,7 @@ _nvkm_falcon_init(struct nvkm_object *object) ret = request_firmware(&fw, name, nv_device_base(device)); if (ret) { nvkm_error(subdev, "unable to load firmware code\n"); - return ret; + return -ENODEV; } falcon->code.data = vmemdup(fw->data, fw->size); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 975a2547b8cd..ba6b390a1fef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -435,7 +435,7 @@ gf100_fifo_recover_work(struct work_struct *work) { struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_object *engine; + struct nvkm_engine *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; @@ -450,9 +450,9 @@ gf100_fifo_recover_work(struct work_struct *work) nvkm_mask(device, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nvkm_engine(fifo, engn))) { - nvkm_object_fini(engine, false); - WARN_ON(nvkm_object_init(engine)); + if ((engine = nvkm_device_engine(device, engn))) { + nvkm_subdev_fini(&engine->subdev, false); + WARN_ON(nvkm_subdev_init(&engine->subdev)); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 216205cdf115..62b3de4e9353 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -481,7 +481,7 @@ gk104_fifo_recover_work(struct work_struct *work) { struct gk104_fifo *fifo = container_of(work, typeof(*fifo), fault); struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_object *engine; + struct nvkm_engine *engine; unsigned long flags; u32 engn, engm = 0; u64 mask, todo; @@ -496,9 +496,9 @@ gk104_fifo_recover_work(struct work_struct *work) nvkm_mask(device, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { - if ((engine = (void *)nvkm_engine(fifo, engn))) { - nvkm_object_fini(engine, false); - WARN_ON(nvkm_object_init(engine)); + if ((engine = nvkm_device_engine(device, engn))) { + nvkm_subdev_fini(&engine->subdev, false); + WARN_ON(nvkm_subdev_init(&engine->subdev)); } gk104_fifo_runlist_update(fifo, gk104_fifo_engidx(fifo, engn)); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 6afdb20cf304..1e712355a70b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1601,7 +1601,7 @@ gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, int i; /* Convert device name to lowercase */ - strncpy(cname, device->cname, sizeof(cname)); + strncpy(cname, device->chip->name, sizeof(cname)); cname[sizeof(cname) - 1] = '\0'; i = strlen(cname); while (i) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index a441fd3b69bc..b3ae0d96ddb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -638,8 +638,8 @@ nvkm_perfctx_dtor(struct nvkm_object *object) struct nvkm_pm *pm = (void *)object->engine; struct nvkm_perfctx *ctx = (void *)object; - mutex_lock(&nv_subdev(pm)->mutex); nvkm_gpuobj_destroy(&ctx->base); + mutex_lock(&nv_subdev(pm)->mutex); if (pm->context == ctx) pm->context = NULL; mutex_unlock(&nv_subdev(pm)->mutex); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c index 3b57f50db4de..ab6aecf29f4b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c @@ -40,8 +40,8 @@ nv04_bus_intr(struct nvkm_subdev *subdev) if (stat & 0x00000110) { struct nvkm_gpio *gpio = device->gpio; - if (gpio && gpio->subdev.intr) - gpio->subdev.intr(&gpio->subdev); + if (gpio) + nvkm_subdev_intr(&gpio->subdev); stat &= ~0x00000110; nvkm_wr32(device, 0x001100, 0x00000110); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c index e99d7a20f90e..2e5340a2c94d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c @@ -36,8 +36,8 @@ nv31_bus_intr(struct nvkm_subdev *subdev) if (gpio) { struct nvkm_gpio *gpio = device->gpio; - if (gpio && gpio->subdev.intr) - gpio->subdev.intr(&gpio->subdev); + if (gpio) + nvkm_subdev_intr(&gpio->subdev); } if (stat & 0x00000008) { /* NV41- */ @@ -54,8 +54,8 @@ nv31_bus_intr(struct nvkm_subdev *subdev) if (stat & 0x00070000) { struct nvkm_therm *therm = device->therm; - if (therm && therm->subdev.intr) - therm->subdev.intr(&therm->subdev); + if (therm) + nvkm_subdev_intr(&therm->subdev); stat &= ~0x00070000; nvkm_wr32(device, 0x001100, 0x00070000); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c index 47d1e436bd44..3948ec73d31a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c @@ -69,8 +69,8 @@ nv50_bus_intr(struct nvkm_subdev *subdev) if (stat & 0x00010000) { struct nvkm_therm *therm = device->therm; - if (therm && therm->subdev.intr) - therm->subdev.intr(&therm->subdev); + if (therm) + nvkm_subdev_intr(&therm->subdev); stat &= ~0x00010000; nvkm_wr32(device, 0x001100, 0x00010000); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index f861a02d8d59..ee4c34f4b9c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -65,8 +65,8 @@ nvkm_mc_intr(int irq, void *arg) while (map->stat) { if (intr & map->stat) { unit = nvkm_subdev(mc, map->unit); - if (unit && unit->intr) - unit->intr(unit); + if (unit) + nvkm_subdev_intr(unit); stat &= ~map->stat; } map++; -- cgit v1.2.3 From d8e83994aaf6749b7124a219f5b46bd1329e2a08 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:17 +1000 Subject: drm/nouveau/imem: improve management of instance memory Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h | 33 +-- drivers/gpu/drm/nouveau/include/nvkm/core/memory.h | 53 +++++ drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h | 9 +- .../gpu/drm/nouveau/include/nvkm/subdev/instmem.h | 27 +-- drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h | 1 + drivers/gpu/drm/nouveau/nouveau_bo.c | 6 +- drivers/gpu/drm/nouveau/nvkm/core/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 133 ++++++----- drivers/gpu/drm/nouveau/nvkm/core/memory.c | 64 ++++++ drivers/gpu/drm/nouveau/nvkm/core/ramht.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c | 9 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 9 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 9 - drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 11 - drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c | 3 - drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c | 90 -------- drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 43 +--- drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 32 +-- drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h | 3 - drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c | 244 ++++++++++++++++----- .../gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 214 ++++++++++-------- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c | 160 ++++++++------ drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h | 36 --- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c | 146 +++++++++++- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 198 ++++++++++++----- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h | 31 +-- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 19 ++ drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c | 4 - drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 4 - 34 files changed, 968 insertions(+), 656 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/core/memory.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/core/memory.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h index 2260aef3ec3e..4e4a9964d235 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h @@ -1,6 +1,7 @@ #ifndef __NVKM_GPUOBJ_H__ #define __NVKM_GPUOBJ_H__ #include +#include #include struct nvkm_vma; struct nvkm_vm; @@ -11,13 +12,23 @@ struct nvkm_vm; struct nvkm_gpuobj { struct nvkm_object object; - struct nvkm_object *parent; + struct nvkm_memory *memory; + struct nvkm_gpuobj *parent; struct nvkm_mm_node *node; struct nvkm_mm heap; u32 flags; u64 addr; u32 size; + + const struct nvkm_gpuobj_func *func; +}; + +struct nvkm_gpuobj_func { + void (*acquire)(struct nvkm_gpuobj *); + void (*release)(struct nvkm_gpuobj *); + u32 (*rd32)(struct nvkm_gpuobj *, u32 offset); + void (*wr32)(struct nvkm_gpuobj *, u32 offset, u32 data); }; static inline struct nvkm_gpuobj * @@ -60,24 +71,4 @@ int _nvkm_gpuobj_init(struct nvkm_object *); int _nvkm_gpuobj_fini(struct nvkm_object *, bool); u32 _nvkm_gpuobj_rd32(struct nvkm_object *, u64); void _nvkm_gpuobj_wr32(struct nvkm_object *, u64, u32); - -/* accessor macros - kmap()/done() must bracket use of the other accessor - * macros to guarantee correct behaviour across all chipsets - */ -#define nvkm_kmap(o) do { \ - struct nvkm_gpuobj *_gpuobj = (o); \ - (void)_gpuobj; \ -} while(0) -#define nvkm_ro32(o,a) ({ \ - u32 _data; \ - nvkm_object_rd32(&(o)->object, (a), &_data); \ - _data; \ -}) -#define nvkm_wo32(o,a,d) nvkm_object_wr32(&(o)->object, (a), (d)) -#define nvkm_mo32(o,a,m,d) ({ \ - u32 _addr = (a), _data = nvkm_ro32((o), _addr); \ - nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \ - _data; \ -}) -#define nvkm_done(o) nvkm_kmap(o) #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h new file mode 100644 index 000000000000..9363b839a9da --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/memory.h @@ -0,0 +1,53 @@ +#ifndef __NVKM_MEMORY_H__ +#define __NVKM_MEMORY_H__ +#include +struct nvkm_device; +struct nvkm_vma; +struct nvkm_vm; + +enum nvkm_memory_target { + NVKM_MEM_TARGET_INST, + NVKM_MEM_TARGET_VRAM, + NVKM_MEM_TARGET_HOST, +}; + +struct nvkm_memory { + const struct nvkm_memory_func *func; +}; + +struct nvkm_memory_func { + void *(*dtor)(struct nvkm_memory *); + enum nvkm_memory_target (*target)(struct nvkm_memory *); + u64 (*addr)(struct nvkm_memory *); + u64 (*size)(struct nvkm_memory *); + void (*boot)(struct nvkm_memory *, struct nvkm_vm *); + void __iomem *(*acquire)(struct nvkm_memory *); + void (*release)(struct nvkm_memory *); + u32 (*rd32)(struct nvkm_memory *, u64 offset); + void (*wr32)(struct nvkm_memory *, u64 offset, u32 data); + void (*map)(struct nvkm_memory *, struct nvkm_vma *, u64 offset); +}; + +void nvkm_memory_ctor(const struct nvkm_memory_func *, struct nvkm_memory *); +int nvkm_memory_new(struct nvkm_device *, enum nvkm_memory_target, + u64 size, u32 align, bool zero, struct nvkm_memory **); +void nvkm_memory_del(struct nvkm_memory **); +#define nvkm_memory_target(p) (p)->func->target(p) +#define nvkm_memory_addr(p) (p)->func->addr(p) +#define nvkm_memory_size(p) (p)->func->size(p) +#define nvkm_memory_boot(p,v) (p)->func->boot((p),(v)) +#define nvkm_memory_map(p,v,o) (p)->func->map((p),(v),(o)) + +/* accessor macros - kmap()/done() must bracket use of the other accessor + * macros to guarantee correct behaviour across all chipsets + */ +#define nvkm_kmap(o) (o)->func->acquire(o) +#define nvkm_ro32(o,a) (o)->func->rd32((o), (a)) +#define nvkm_wo32(o,a,d) (o)->func->wr32((o), (a), (d)) +#define nvkm_mo32(o,a,m,d) ({ \ + u32 _addr = (a), _data = nvkm_ro32((o), _addr); \ + nvkm_wo32((o), _addr, (_data & ~(m)) | (d)); \ + _data; \ +}) +#define nvkm_done(o) (o)->func->release(o) +#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h index 753b7e953035..1eaf7de79d50 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bar.h @@ -7,13 +7,8 @@ struct nvkm_vma; struct nvkm_bar { struct nvkm_subdev subdev; - int (*alloc)(struct nvkm_bar *, struct nvkm_object *, - struct nvkm_mem *, struct nvkm_object **); - - int (*kmap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, - struct nvkm_vma *); - int (*umap)(struct nvkm_bar *, struct nvkm_mem *, u32 flags, - struct nvkm_vma *); + struct nvkm_vm *(*kmap)(struct nvkm_bar *); + int (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *); void (*unmap)(struct nvkm_bar *, struct nvkm_vma *); void (*flush)(struct nvkm_bar *); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h index 7ba3ff27e89e..2e9e6f058dc0 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -1,33 +1,22 @@ #ifndef __NVKM_INSTMEM_H__ #define __NVKM_INSTMEM_H__ #include - -struct nvkm_instobj { - struct nvkm_object object; - struct list_head head; - u32 *suspend; - u64 addr; - u32 size; -}; - -static inline struct nvkm_instobj * -nv_memobj(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - BUG_ON(!nv_iclass(obj, NV_MEMOBJ_CLASS)); -#endif - return obj; -} +struct nvkm_memory; struct nvkm_instmem { struct nvkm_subdev subdev; struct list_head list; u32 reserved; - int (*alloc)(struct nvkm_instmem *, struct nvkm_object *, - u32 size, u32 align, struct nvkm_object **); + int (*alloc)(struct nvkm_instmem *, u32 size, u32 align, bool zero, + struct nvkm_memory **); const struct nvkm_instmem_func *func; + + struct nvkm_gpuobj *vbios; + struct nvkm_ramht *ramht; + struct nvkm_gpuobj *ramro; + struct nvkm_gpuobj *ramfc; }; struct nvkm_instmem_func { diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h index 0991c9011dc1..677f6c0cbb9b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -97,6 +97,7 @@ int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset, int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset, struct lock_class_key *, struct nvkm_vm **); int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd); +int nvkm_vm_boot(struct nvkm_vm *, u64 size); int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access, struct nvkm_vma *); void nvkm_vm_put(struct nvkm_vma *); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 496c00d585cd..982c0ed163eb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1388,12 +1388,16 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) mem->bus.is_iomem = true; if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { struct nvkm_bar *bar = nvxx_bar(&drm->device); + int page_shift = 12; + if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI) + page_shift = node->page_shift; - ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, + ret = bar->umap(bar, node->size << 12, page_shift, &node->bar_vma); if (ret) return ret; + nvkm_vm_map(&node->bar_vma, node); mem->bus.offset = node->bar_vma.offset; } break; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild index c4198164bc59..98cf39f732c1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild @@ -6,6 +6,7 @@ nvkm-y += nvkm/core/event.o nvkm-y += nvkm/core/gpuobj.o nvkm-y += nvkm/core/handle.o nvkm-y += nvkm/core/ioctl.o +nvkm-y += nvkm/core/memory.o nvkm-y += nvkm/core/mm.o nvkm-y += nvkm/core/namedb.o nvkm-y += nvkm/core/notify.o diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index bc4b3c2d075e..037036069839 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -28,6 +28,44 @@ #include #include +static void +nvkm_gpuobj_release(struct nvkm_gpuobj *gpuobj) +{ + if (gpuobj->node) { + nvkm_done(gpuobj->parent); + return; + } + nvkm_done(gpuobj->memory); +} + +static void +nvkm_gpuobj_acquire(struct nvkm_gpuobj *gpuobj) +{ + if (gpuobj->node) { + nvkm_kmap(gpuobj->parent); + return; + } + nvkm_kmap(gpuobj->memory); +} + +static u32 +nvkm_gpuobj_rd32(struct nvkm_gpuobj *gpuobj, u32 offset) +{ + if (gpuobj->node) + return nvkm_ro32(gpuobj->parent, gpuobj->node->offset + offset); + return nvkm_ro32(gpuobj->memory, offset); +} + +static void +nvkm_gpuobj_wr32(struct nvkm_gpuobj *gpuobj, u32 offset, u32 data) +{ + if (gpuobj->node) { + nvkm_wo32(gpuobj->parent, gpuobj->node->offset + offset, data); + return; + } + nvkm_wo32(gpuobj->memory, offset, data); +} + void nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) { @@ -46,17 +84,27 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) if (gpuobj->heap.block_size) nvkm_mm_fini(&gpuobj->heap); + nvkm_memory_del(&gpuobj->memory); nvkm_object_destroy(&gpuobj->object); } +static const struct nvkm_gpuobj_func +nvkm_gpuobj_func = { + .acquire = nvkm_gpuobj_acquire, + .release = nvkm_gpuobj_release, + .rd32 = nvkm_gpuobj_rd32, + .wr32 = nvkm_gpuobj_wr32, +}; + int nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, - struct nvkm_object *pargpu, u32 size, u32 align, u32 flags, + struct nvkm_object *objgpu, u32 size, u32 align, u32 flags, int length, void **pobject) { - struct nvkm_instmem *imem = nvkm_instmem(parent); - struct nvkm_bar *bar = nvkm_bar(parent); + struct nvkm_device *device = nv_device(parent); + struct nvkm_memory *memory = NULL; + struct nvkm_gpuobj *pargpu = NULL; struct nvkm_gpuobj *gpuobj; struct nvkm_mm *heap = NULL; int ret, i; @@ -64,46 +112,39 @@ nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, *pobject = NULL; - if (pargpu) { - while ((pargpu = nv_pclass(pargpu, NV_GPUOBJ_CLASS))) { - if (nv_gpuobj(pargpu)->heap.block_size) + if (objgpu) { + while ((objgpu = nv_pclass(objgpu, NV_GPUOBJ_CLASS))) { + if (nv_gpuobj(objgpu)->heap.block_size) break; - pargpu = pargpu->parent; + objgpu = objgpu->parent; } - if (WARN_ON(pargpu == NULL)) + if (WARN_ON(objgpu == NULL)) return -EINVAL; + pargpu = nv_gpuobj(objgpu); - addr = nv_gpuobj(pargpu)->addr; - heap = &nv_gpuobj(pargpu)->heap; - atomic_inc(&parent->refcount); + addr = pargpu->addr; + heap = &pargpu->heap; } else { - ret = imem->alloc(imem, parent, size, align, &parent); - pargpu = parent; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, + size, align, false, &memory); if (ret) return ret; - addr = nv_memobj(pargpu)->addr; - size = nv_memobj(pargpu)->size; - - if (bar && bar->alloc) { - struct nvkm_instobj *iobj = (void *)parent; - struct nvkm_mem **mem = (void *)(iobj + 1); - struct nvkm_mem *node = *mem; - if (!bar->alloc(bar, parent, node, &pargpu)) { - nvkm_object_ref(NULL, &parent); - parent = pargpu; - } - } + addr = nvkm_memory_addr(memory); + size = nvkm_memory_size(memory); } ret = nvkm_object_create_(parent, engine, oclass, pclass | NV_GPUOBJ_CLASS, length, pobject); - nvkm_object_ref(NULL, &parent); gpuobj = *pobject; - if (ret) + if (ret) { + nvkm_memory_del(&memory); return ret; + } + gpuobj->func = &nvkm_gpuobj_func; + gpuobj->memory = memory; gpuobj->parent = pargpu; gpuobj->flags = flags; gpuobj->addr = addr; @@ -182,20 +223,14 @@ u32 _nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr) { struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); - u32 data; - if (gpuobj->node) - addr += gpuobj->node->offset; - nvkm_object_rd32(gpuobj->parent, addr, &data); - return data; + return nvkm_ro32(gpuobj, addr); } void _nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data) { struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); - if (gpuobj->node) - addr += gpuobj->node->offset; - nvkm_object_wr32(gpuobj->parent, addr, data); + nvkm_wo32(gpuobj, addr, data); } static struct nvkm_oclass @@ -231,14 +266,14 @@ nvkm_gpuobj_new(struct nvkm_object *parent, struct nvkm_object *pargpu, int nvkm_gpuobj_map(struct nvkm_gpuobj *gpuobj, u32 access, struct nvkm_vma *vma) { + struct nvkm_memory *memory = gpuobj->memory; struct nvkm_bar *bar = nvkm_bar(gpuobj); int ret = -EINVAL; if (bar && bar->umap) { - struct nvkm_instobj *iobj = (void *) - nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); - struct nvkm_mem **mem = (void *)(iobj + 1); - ret = bar->umap(bar, *mem, access, vma); + ret = bar->umap(bar, gpuobj->size, 12, vma); + if (ret == 0) + nvkm_memory_map(memory, vma, 0); } return ret; @@ -248,17 +283,11 @@ int nvkm_gpuobj_map_vm(struct nvkm_gpuobj *gpuobj, struct nvkm_vm *vm, u32 access, struct nvkm_vma *vma) { - struct nvkm_instobj *iobj = (void *) - nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); - struct nvkm_mem **mem = (void *)(iobj + 1); - int ret; - - ret = nvkm_vm_get(vm, gpuobj->size, 12, access, vma); - if (ret) - return ret; - - nvkm_vm_map(vma, *mem); - return 0; + struct nvkm_memory *memory = gpuobj->memory; + int ret = nvkm_vm_get(vm, gpuobj->size, 12, access, vma); + if (ret == 0) + nvkm_memory_map(memory, vma, 0); + return ret; } void @@ -279,7 +308,7 @@ static void nvkm_gpudup_dtor(struct nvkm_object *object) { struct nvkm_gpuobj *gpuobj = (void *)object; - nvkm_object_ref(NULL, &gpuobj->parent); + nvkm_object_ref(NULL, (struct nvkm_object **)&gpuobj->parent); nvkm_object_destroy(&gpuobj->object); } @@ -306,7 +335,7 @@ nvkm_gpuobj_dup(struct nvkm_object *parent, struct nvkm_gpuobj *base, if (ret) return ret; - nvkm_object_ref(nv_object(base), &gpuobj->parent); + nvkm_object_ref(nv_object(base), (struct nvkm_object **)&gpuobj->parent); gpuobj->addr = base->addr; gpuobj->size = base->size; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/memory.c b/drivers/gpu/drm/nouveau/nvkm/core/memory.c new file mode 100644 index 000000000000..0b88faa845f3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/core/memory.c @@ -0,0 +1,64 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include +#include + +void +nvkm_memory_ctor(const struct nvkm_memory_func *func, + struct nvkm_memory *memory) +{ + memory->func = func; +} + +void +nvkm_memory_del(struct nvkm_memory **pmemory) +{ + struct nvkm_memory *memory = *pmemory; + if (memory && !WARN_ON(!memory->func)) { + if (memory->func->dtor) + *pmemory = memory->func->dtor(memory); + kfree(*pmemory); + *pmemory = NULL; + } +} + +int +nvkm_memory_new(struct nvkm_device *device, enum nvkm_memory_target target, + u64 size, u32 align, bool zero, + struct nvkm_memory **pmemory) +{ + struct nvkm_instmem *imem = device->imem; + struct nvkm_memory *memory; + int ret = -ENOSYS; + + if (unlikely(target != NVKM_MEM_TARGET_INST || !imem)) + return -ENOSYS; + + ret = imem->alloc(imem, size, align, zero, &memory); + if (ret) + return ret; + + *pmemory = memory; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c index 4717af0800e9..061adedc6e2c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c @@ -22,8 +22,6 @@ #include #include -#include - static u32 nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) { @@ -43,7 +41,6 @@ int nvkm_ramht_insert(struct nvkm_ramht *ramht, int chid, u32 handle, u32 context) { struct nvkm_gpuobj *gpuobj = &ramht->gpuobj; - struct nvkm_bar *bar = nvkm_bar(ramht); int ret = -ENOSPC; u32 co, ho; @@ -53,8 +50,6 @@ nvkm_ramht_insert(struct nvkm_ramht *ramht, int chid, u32 handle, u32 context) if (!nvkm_ro32(gpuobj, co + 4)) { nvkm_wo32(gpuobj, co + 0, handle); nvkm_wo32(gpuobj, co + 4, context); - if (bar) - bar->flush(bar); ret = co; break; } @@ -72,12 +67,9 @@ void nvkm_ramht_remove(struct nvkm_ramht *ramht, int cookie) { struct nvkm_gpuobj *gpuobj = &ramht->gpuobj; - struct nvkm_bar *bar = nvkm_bar(ramht); nvkm_kmap(gpuobj); nvkm_wo32(gpuobj, cookie + 0, 0x00000000); nvkm_wo32(gpuobj, cookie + 4, 0x00000000); - if (bar) - bar->flush(bar); nvkm_done(gpuobj); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index 64523d7eea58..c6150eaf16f0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -41,7 +40,6 @@ static int g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent->parent; struct nvkm_gpuobj *ectx = (void *)object; u64 limit = ectx->addr + ectx->size - 1; @@ -73,7 +71,6 @@ g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) upper_32_bits(start)); nvkm_wo32(base->eng, addr + 0x10, 0x00000000); nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - bar->flush(bar); nvkm_done(base->eng); return 0; } @@ -87,7 +84,6 @@ g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nv50_fifo_chan *chan = (void *)parent; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; u32 addr, save, engn; bool done; @@ -128,7 +124,6 @@ g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); nvkm_wo32(base->eng, addr + 0x10, 0x00000000); nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - bar->flush(bar); nvkm_done(base->eng); return 0; } @@ -175,7 +170,6 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, union { struct nv50_channel_dma_v0 v0; } *args = data; - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; int ret; @@ -239,7 +233,6 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, (chan->ramht->gpuobj.node->offset >> 4)); nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); - bar->flush(bar); nvkm_done(base->ramfc); return 0; } @@ -252,7 +245,6 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; u64 ioffset, ilength; @@ -318,7 +310,6 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, (chan->ramht->gpuobj.node->offset >> 4)); nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); - bar->flush(bar); nvkm_done(base->ramfc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index ba6b390a1fef..763a2db7603a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -79,7 +78,6 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; struct nvkm_gpuobj *cur; int i, p; @@ -96,7 +94,6 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo) p += 8; } } - bar->flush(bar); nvkm_done(cur); nvkm_wr32(device, 0x002270, cur->addr >> 12); @@ -113,7 +110,6 @@ static int gf100_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nvkm_bar *bar = nvkm_bar(parent); struct gf100_fifo_base *base = (void *)parent->parent; struct nvkm_gpuobj *engn = &base->base.gpuobj; struct nvkm_engctx *ectx = (void *)object; @@ -144,7 +140,6 @@ gf100_fifo_context_attach(struct nvkm_object *parent, nvkm_kmap(engn); nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); - bar->flush(bar); nvkm_done(engn); return 0; } @@ -159,7 +154,6 @@ gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_gpuobj *engn = &base->base.gpuobj; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; u32 addr; switch (nv_engidx(object->engine)) { @@ -188,7 +182,6 @@ gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, nvkm_kmap(engn); nvkm_wo32(engn, addr + 0x00, 0x00000000); nvkm_wo32(engn, addr + 0x04, 0x00000000); - bar->flush(bar); nvkm_done(engn); return 0; } @@ -201,7 +194,6 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, union { struct fermi_channel_gpfifo_v0 v0; } *args = data; - struct nvkm_bar *bar = nvkm_bar(parent); struct gf100_fifo *fifo = (void *)engine; struct gf100_fifo_base *base = (void *)parent; struct gf100_fifo_chan *chan; @@ -264,7 +256,6 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_wo32(ramfc, 0xb8, 0xf8000000); nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ - bar->flush(bar); nvkm_done(ramfc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 62b3de4e9353..d1238aa7bec5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -99,7 +98,6 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) struct gk104_fifo_engn *engn = &fifo->engine[engine]; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; struct nvkm_gpuobj *cur; int i, p; @@ -116,7 +114,6 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) p += 8; } } - bar->flush(bar); nvkm_done(cur); nvkm_wr32(device, 0x002270, cur->addr >> 12); @@ -133,7 +130,6 @@ static int gk104_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nvkm_bar *bar = nvkm_bar(parent); struct gk104_fifo_base *base = (void *)parent->parent; struct nvkm_gpuobj *engn = &base->base.gpuobj; struct nvkm_engctx *ectx = (void *)object; @@ -168,7 +164,6 @@ gk104_fifo_context_attach(struct nvkm_object *parent, nvkm_kmap(engn); nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); - bar->flush(bar); nvkm_done(engn); return 0; } @@ -198,7 +193,6 @@ static int gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nvkm_object *object) { - struct nvkm_bar *bar = nvkm_bar(parent); struct gk104_fifo_base *base = (void *)parent->parent; struct gk104_fifo_chan *chan = (void *)parent; struct nvkm_gpuobj *engn = &base->base.gpuobj; @@ -226,7 +220,6 @@ gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, nvkm_kmap(engn); nvkm_wo32(engn, addr + 0x00, 0x00000000); nvkm_wo32(engn, addr + 0x04, 0x00000000); - bar->flush(bar); nvkm_done(engn); } @@ -241,7 +234,6 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, union { struct kepler_channel_gpfifo_a_v0 v0; } *args = data; - struct nvkm_bar *bar = nvkm_bar(parent); struct gk104_fifo *fifo = (void *)engine; struct gk104_fifo_base *base = (void *)parent; struct gk104_fifo_chan *chan; @@ -320,7 +312,6 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_wo32(ramfc, 0xb8, 0xf8000000); nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ - bar->flush(bar); nvkm_done(ramfc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 51b8fce9e0fc..b01490f71f09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include @@ -574,7 +574,8 @@ nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_instmem *imem = nv04_instmem(parent); + struct nvkm_device *device = (void *)parent; + struct nvkm_instmem *imem = device->imem; struct nv04_fifo *fifo; int ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index 046acc281381..7491b10a76b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include @@ -145,7 +145,8 @@ nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_instmem *imem = nv04_instmem(parent); + struct nvkm_device *device = (void *)parent; + struct nvkm_instmem *imem = device->imem; struct nv04_fifo *fifo; int ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index 7be6fea90010..e652941d04f3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include @@ -152,7 +152,8 @@ nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_instmem *imem = nv04_instmem(parent); + struct nvkm_device *device = (void *)parent; + struct nvkm_instmem *imem = device->imem; struct nv04_fifo *fifo; int ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index cad4b4be1938..f35ae7647239 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include @@ -276,7 +276,8 @@ nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_instmem *imem = nv04_instmem(parent); + struct nvkm_device *device = (void *)parent; + struct nvkm_instmem *imem = device->imem; struct nv04_fifo *fifo; int ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index 402639cb4ec9..ffa495c1692b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include @@ -42,7 +41,6 @@ static void nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo) { struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_bar *bar = device->bar; struct nvkm_gpuobj *cur; int i, p; @@ -54,7 +52,6 @@ nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo) if (nvkm_rd32(device, 0x002600 + (i * 4)) & 0x80000000) nvkm_wo32(cur, p++ * 4, i); } - bar->flush(bar); nvkm_done(cur); nvkm_wr32(device, 0x0032f4, cur->addr >> 12); @@ -73,7 +70,6 @@ nv50_fifo_playlist_update(struct nv50_fifo *fifo) static int nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) { - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent->parent; struct nvkm_gpuobj *ectx = (void *)object; u64 limit = ectx->addr + ectx->size - 1; @@ -98,7 +94,6 @@ nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) upper_32_bits(start)); nvkm_wo32(base->eng, addr + 0x10, 0x00000000); nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - bar->flush(bar); nvkm_done(base->eng); return 0; } @@ -112,7 +107,6 @@ nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, struct nv50_fifo_chan *chan = (void *)parent; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; u32 addr, me; int ret = 0; @@ -159,7 +153,6 @@ nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); nvkm_wo32(base->eng, addr + 0x10, 0x00000000); nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - bar->flush(bar); nvkm_done(base->eng); } @@ -205,7 +198,6 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, union { struct nv50_channel_dma_v0 v0; } *args = data; - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; int ret; @@ -257,7 +249,6 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | (chan->ramht->gpuobj.node->offset >> 4)); - bar->flush(bar); nvkm_done(base->ramfc); return 0; } @@ -270,7 +261,6 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_fifo_base *base = (void *)parent; struct nv50_fifo_chan *chan; u64 ioffset, ilength; @@ -324,7 +314,6 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | (chan->ramht->gpuobj.node->offset >> 4)); - bar->flush(bar); nvkm_done(base->ramfc); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index f36e0896ae9c..a2e60b1ddb27 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -23,7 +23,6 @@ */ #include "ctxgf100.h" -#include #include #include #include @@ -1273,7 +1272,6 @@ gf100_grctx_generate(struct gf100_gr *gr) struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; struct nvkm_gpuobj *chan; struct gf100_grctx info; int ret, i; @@ -1309,7 +1307,6 @@ gf100_grctx_generate(struct gf100_gr *gr) /* context pointer (virt) */ nvkm_wo32(chan, 0x0210, 0x00080004); nvkm_wo32(chan, 0x0214, 0x00000000); - bar->flush(bar); nvkm_done(chan); nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8); @@ -1341,7 +1338,6 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_wo32(chan, 0x80020, 0); nvkm_wo32(chan, 0x80028, 0); nvkm_wo32(chan, 0x8002c, 0); - bar->flush(bar); nvkm_done(chan); } else { nvkm_wr32(device, 0x409840, 0x80000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c index 6af707b5be18..c906c43e9065 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c @@ -23,7 +23,6 @@ */ #include -#include #include struct nv50_mpeg_chan { @@ -84,7 +83,6 @@ nv50_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_bar *bar = nvkm_bar(parent); struct nv50_mpeg_chan *chan; struct nvkm_gpuobj *image; int ret; @@ -100,7 +98,6 @@ nv50_mpeg_context_ctor(struct nvkm_object *parent, nvkm_kmap(image); nvkm_wo32(image, 0x0070, 0x00801ec1); nvkm_wo32(image, 0x007c, 0x0000037c); - bar->flush(bar); nvkm_done(image); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c index 6fe71b2276cc..8daaa65fc8cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.c @@ -23,96 +23,6 @@ */ #include "priv.h" -#include -#include - -struct nvkm_barobj { - struct nvkm_object base; - struct nvkm_vma vma; - void __iomem *iomem; -}; - -static int -nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_device(parent); - struct nvkm_bar *bar = nvkm_bar(device); - struct nvkm_mem *mem = data; - struct nvkm_barobj *barobj; - int ret; - - ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); - *pobject = nv_object(barobj); - if (ret) - return ret; - - ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma); - if (ret) - return ret; - - barobj->iomem = ioremap(nv_device_resource_start(device, 3) + - (u32)barobj->vma.offset, mem->size << 12); - if (!barobj->iomem) { - nvkm_warn(&bar->subdev, "PRAMIN ioremap failed\n"); - return -ENOMEM; - } - - return 0; -} - -static void -nvkm_barobj_dtor(struct nvkm_object *object) -{ - struct nvkm_bar *bar = nvkm_bar(object); - struct nvkm_barobj *barobj = (void *)object; - if (barobj->vma.node) { - if (barobj->iomem) - iounmap(barobj->iomem); - bar->unmap(bar, &barobj->vma); - } - nvkm_object_destroy(&barobj->base); -} - -static u32 -nvkm_barobj_rd32(struct nvkm_object *object, u64 addr) -{ - struct nvkm_barobj *barobj = (void *)object; - return ioread32_native(barobj->iomem + addr); -} - -static void -nvkm_barobj_wr32(struct nvkm_object *object, u64 addr, u32 data) -{ - struct nvkm_barobj *barobj = (void *)object; - iowrite32_native(data, barobj->iomem + addr); -} - -static struct nvkm_oclass -nvkm_barobj_oclass = { - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nvkm_barobj_ctor, - .dtor = nvkm_barobj_dtor, - .init = _nvkm_object_init, - .fini = _nvkm_object_fini, - .rd32 = nvkm_barobj_rd32, - .wr32 = nvkm_barobj_wr32, - }, -}; - -int -nvkm_bar_alloc(struct nvkm_bar *bar, struct nvkm_object *parent, - struct nvkm_mem *mem, struct nvkm_object **pobject) -{ - struct nvkm_object *gpuobj; - int ret = nvkm_object_old(parent, &parent->engine->subdev.object, - &nvkm_barobj_oclass, mem, 0, &gpuobj); - if (ret == 0) - *pobject = gpuobj; - return ret; -} - int nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 01e26213fd88..1ea6b3909c3a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -39,35 +39,18 @@ struct gf100_bar { struct gf100_bar_vm bar[2]; }; -static int -gf100_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags, - struct nvkm_vma *vma) +static struct nvkm_vm * +gf100_bar_kmap(struct nvkm_bar *obj) { struct gf100_bar *bar = container_of(obj, typeof(*bar), base); - int ret; - - ret = nvkm_vm_get(bar->bar[0].vm, mem->size << 12, 12, flags, vma); - if (ret) - return ret; - - nvkm_vm_map(vma, mem); - return 0; + return bar->bar[0].vm; } static int -gf100_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags, - struct nvkm_vma *vma) +gf100_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma) { struct gf100_bar *bar = container_of(obj, typeof(*bar), base); - int ret; - - ret = nvkm_vm_get(bar->bar[1].vm, mem->size << 12, - mem->page_shift, flags, vma); - if (ret) - return ret; - - nvkm_vm_map(vma, mem); - return 0; + return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma); } static void @@ -109,11 +92,7 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, * Bootstrap page table lookup. */ if (bar_nr == 3) { - ret = nvkm_gpuobj_new(nv_object(bar), NULL, - (bar_len >> 12) * 8, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, - &vm->pgt[0].obj[0]); - vm->pgt[0].refcount[0] = 1; + ret = nvkm_vm_boot(vm, bar_len); if (ret) return ret; } @@ -149,6 +128,10 @@ gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + device->bar = &bar->base; + bar->base.flush = g84_bar_flush; + spin_lock_init(&bar->lock); + /* BAR3 */ if (has_bar3) { ret = gf100_bar_ctor_vm(bar, &bar->bar[0], &bar3_lock, 3); @@ -161,14 +144,10 @@ gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - if (has_bar3) { - bar->base.alloc = nvkm_bar_alloc; + if (has_bar3) bar->base.kmap = gf100_bar_kmap; - } bar->base.umap = gf100_bar_umap; bar->base.unmap = gf100_bar_unmap; - bar->base.flush = g84_bar_flush; - spin_lock_init(&bar->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index cb58cc5b2b57..ec864afc8862 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -40,34 +40,18 @@ struct nv50_bar { struct nvkm_gpuobj *bar3; }; -static int -nv50_bar_kmap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags, - struct nvkm_vma *vma) +static struct nvkm_vm * +nv50_bar_kmap(struct nvkm_bar *obj) { struct nv50_bar *bar = container_of(obj, typeof(*bar), base); - int ret; - - ret = nvkm_vm_get(bar->bar3_vm, mem->size << 12, 12, flags, vma); - if (ret) - return ret; - - nvkm_vm_map(vma, mem); - return 0; + return bar->bar3_vm; } static int -nv50_bar_umap(struct nvkm_bar *obj, struct nvkm_mem *mem, u32 flags, - struct nvkm_vma *vma) +nv50_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma) { struct nv50_bar *bar = container_of(obj, typeof(*bar), base); - int ret; - - ret = nvkm_vm_get(bar->bar1_vm, mem->size << 12, 12, flags, vma); - if (ret) - return ret; - - nvkm_vm_map(vma, mem); - return 0; + return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma); } static void @@ -152,10 +136,7 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); - ret = nvkm_gpuobj_new(nv_object(bar), heap, - ((limit-- - start) >> 12) * 8, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); - vm->pgt[0].refcount[0] = 1; + ret = nvkm_vm_boot(vm, limit-- - start); if (ret) return ret; @@ -207,7 +188,6 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_wo32(bar->bar1, 0x14, 0x00000000); nvkm_done(bar->bar1); - bar->base.alloc = nvkm_bar_alloc; bar->base.kmap = nv50_bar_kmap; bar->base.umap = nv50_bar_umap; bar->base.unmap = nv50_bar_unmap; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h index e9d2f7b6b22f..3a8fbaea582d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/priv.h @@ -17,9 +17,6 @@ void _nvkm_bar_dtor(struct nvkm_object *); #define _nvkm_bar_init _nvkm_subdev_init #define _nvkm_bar_fini _nvkm_subdev_fini -int nvkm_bar_alloc(struct nvkm_bar *, struct nvkm_object *, - struct nvkm_mem *, struct nvkm_object **); - void g84_bar_flush(struct nvkm_bar *); int gf100_bar_ctor(struct nvkm_object *, struct nvkm_object *, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c index 8ac8e4f4fa4b..2a1dab304087 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c @@ -23,83 +23,221 @@ */ #include "priv.h" -#include +#include +#include /****************************************************************************** * instmem object base implementation *****************************************************************************/ +#define nvkm_instobj(p) container_of((p), struct nvkm_instobj, memory) -void -_nvkm_instobj_dtor(struct nvkm_object *object) +struct nvkm_instobj { + struct nvkm_memory memory; + struct nvkm_memory *parent; + struct nvkm_instmem *imem; + struct list_head head; + u32 *suspend; + void __iomem *map; +}; + +static enum nvkm_memory_target +nvkm_instobj_target(struct nvkm_memory *memory) +{ + memory = nvkm_instobj(memory)->parent; + return nvkm_memory_target(memory); +} + +static u64 +nvkm_instobj_addr(struct nvkm_memory *memory) +{ + memory = nvkm_instobj(memory)->parent; + return nvkm_memory_addr(memory); +} + +static u64 +nvkm_instobj_size(struct nvkm_memory *memory) +{ + memory = nvkm_instobj(memory)->parent; + return nvkm_memory_size(memory); +} + +static void +nvkm_instobj_release(struct nvkm_memory *memory) +{ + struct nvkm_instobj *iobj = nvkm_instobj(memory); + struct nvkm_bar *bar = iobj->imem->subdev.device->bar; + if (bar && bar->flush) + bar->flush(bar); +} + +static void __iomem * +nvkm_instobj_acquire(struct nvkm_memory *memory) +{ + return nvkm_instobj(memory)->map; +} + +static u32 +nvkm_instobj_rd32(struct nvkm_memory *memory, u64 offset) +{ + return ioread32_native(nvkm_instobj(memory)->map + offset); +} + +static void +nvkm_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) { - struct nvkm_instmem *imem = nvkm_instmem(object); - struct nvkm_instobj *iobj = (void *)object; + iowrite32_native(data, nvkm_instobj(memory)->map + offset); +} + +static void +nvkm_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset) +{ + memory = nvkm_instobj(memory)->parent; + nvkm_memory_map(memory, vma, offset); +} - mutex_lock(&nv_subdev(imem)->mutex); +static void * +nvkm_instobj_dtor(struct nvkm_memory *memory) +{ + struct nvkm_instobj *iobj = nvkm_instobj(memory); list_del(&iobj->head); - mutex_unlock(&nv_subdev(imem)->mutex); + nvkm_memory_del(&iobj->parent); + return iobj; +} - return nvkm_object_destroy(&iobj->object); +const struct nvkm_memory_func +nvkm_instobj_func = { + .dtor = nvkm_instobj_dtor, + .target = nvkm_instobj_target, + .addr = nvkm_instobj_addr, + .size = nvkm_instobj_size, + .acquire = nvkm_instobj_acquire, + .release = nvkm_instobj_release, + .rd32 = nvkm_instobj_rd32, + .wr32 = nvkm_instobj_wr32, + .map = nvkm_instobj_map, +}; + +static void +nvkm_instobj_boot(struct nvkm_memory *memory, struct nvkm_vm *vm) +{ + memory = nvkm_instobj(memory)->parent; + nvkm_memory_boot(memory, vm); } -int -nvkm_instobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) +static void +nvkm_instobj_release_slow(struct nvkm_memory *memory) +{ + struct nvkm_instobj *iobj = nvkm_instobj(memory); + nvkm_instobj_release(memory); + nvkm_done(iobj->parent); +} + +static void __iomem * +nvkm_instobj_acquire_slow(struct nvkm_memory *memory) +{ + struct nvkm_instobj *iobj = nvkm_instobj(memory); + iobj->map = nvkm_kmap(iobj->parent); + if (iobj->map) + memory->func = &nvkm_instobj_func; + return iobj->map; +} + +static u32 +nvkm_instobj_rd32_slow(struct nvkm_memory *memory, u64 offset) +{ + struct nvkm_instobj *iobj = nvkm_instobj(memory); + return nvkm_ro32(iobj->parent, offset); +} + +static void +nvkm_instobj_wr32_slow(struct nvkm_memory *memory, u64 offset, u32 data) +{ + struct nvkm_instobj *iobj = nvkm_instobj(memory); + return nvkm_wo32(iobj->parent, offset, data); +} + +const struct nvkm_memory_func +nvkm_instobj_func_slow = { + .dtor = nvkm_instobj_dtor, + .target = nvkm_instobj_target, + .addr = nvkm_instobj_addr, + .size = nvkm_instobj_size, + .boot = nvkm_instobj_boot, + .acquire = nvkm_instobj_acquire_slow, + .release = nvkm_instobj_release_slow, + .rd32 = nvkm_instobj_rd32_slow, + .wr32 = nvkm_instobj_wr32_slow, + .map = nvkm_instobj_map, +}; + +static int +nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero, + struct nvkm_memory **pmemory) { - struct nvkm_instmem *imem = nvkm_instmem(parent); + struct nvkm_instmem_impl *impl = (void *)imem->subdev.object.oclass; + struct nvkm_memory *memory; struct nvkm_instobj *iobj; + u32 offset; int ret; - ret = nvkm_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, - length, pobject); - iobj = *pobject; + ret = impl->memory_new(imem, size, align, zero, &memory); if (ret) - return ret; + goto done; - mutex_lock(&imem->subdev.mutex); - list_add(&iobj->head, &imem->list); - mutex_unlock(&imem->subdev.mutex); - return 0; + if (!impl->persistent) { + if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) { + ret = -ENOMEM; + goto done; + } + + nvkm_memory_ctor(&nvkm_instobj_func_slow, &iobj->memory); + iobj->parent = memory; + iobj->imem = imem; + list_add_tail(&iobj->head, &imem->list); + memory = &iobj->memory; + } + + if (!impl->zero && zero) { + void __iomem *map = nvkm_kmap(memory); + if (unlikely(!map)) { + for (offset = 0; offset < size; offset += 4) + nvkm_wo32(memory, offset, 0x00000000); + } else { + memset_io(map, 0x00, size); + } + nvkm_done(memory); + } + +done: + if (ret) + nvkm_memory_del(&memory); + *pmemory = memory; + return ret; } /****************************************************************************** * instmem subdev base implementation *****************************************************************************/ -static int -nvkm_instmem_alloc(struct nvkm_instmem *imem, struct nvkm_object *parent, - u32 size, u32 align, struct nvkm_object **pobject) -{ - struct nvkm_instmem_impl *impl = (void *)imem->subdev.object.oclass; - struct nvkm_instobj_args args = { .size = size, .align = align }; - return nvkm_object_old(parent, &parent->engine->subdev.object, - impl->instobj, &args, sizeof(args), pobject); -} - int _nvkm_instmem_fini(struct nvkm_object *object, bool suspend) { struct nvkm_instmem *imem = (void *)object; struct nvkm_instobj *iobj; - int i, ret = 0; + int i; if (suspend) { - mutex_lock(&imem->subdev.mutex); list_for_each_entry(iobj, &imem->list, head) { - iobj->suspend = vmalloc(iobj->size); - if (!iobj->suspend) { - ret = -ENOMEM; - break; - } - - for (i = 0; i < iobj->size; i += 4) { - nvkm_object_rd32(&iobj->object, i, (u32 *) - &iobj->suspend[i/4]); - } + struct nvkm_memory *memory = iobj->parent; + u64 size = nvkm_memory_size(memory); + + iobj->suspend = vmalloc(size); + if (!iobj->suspend) + return -ENOMEM; + + for (i = 0; i < size; i += 4) + iobj->suspend[i / 4] = nvkm_ro32(memory, i); } - mutex_unlock(&imem->subdev.mutex); - if (ret) - return ret; } return nvkm_subdev_fini_old(&imem->subdev, suspend); @@ -116,18 +254,17 @@ _nvkm_instmem_init(struct nvkm_object *object) if (ret) return ret; - mutex_lock(&imem->subdev.mutex); list_for_each_entry(iobj, &imem->list, head) { if (iobj->suspend) { - for (i = 0; i < iobj->size; i += 4) { - nvkm_object_wr32(&iobj->object, i, *(u32 *) - &iobj->suspend[i/4]); - } + struct nvkm_memory *memory = iobj->parent; + u64 size = nvkm_memory_size(memory); + for (i = 0; i < size; i += 4) + nvkm_wo32(memory, i, iobj->suspend[i / 4]); vfree(iobj->suspend); iobj->suspend = NULL; } } - mutex_unlock(&imem->subdev.mutex); + return 0; } @@ -135,6 +272,7 @@ int nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int length, void **pobject) { + struct nvkm_device *device = (void *)parent; struct nvkm_instmem *imem; int ret; @@ -144,7 +282,9 @@ nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + device->imem = imem; + INIT_LIST_HEAD(&imem->list); - imem->alloc = nvkm_instmem_alloc; + imem->alloc = nvkm_instobj_new; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index e6370382109b..a64c3f9bfc3d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -37,9 +37,12 @@ * to use more "relaxed" allocation parameters when using the DMA API, since we * never need a kernel mapping. */ +#define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base) +#include "priv.h" -#include +#include #include +#include #ifdef __KERNEL__ #include @@ -47,14 +50,12 @@ #include #endif -#include "priv.h" +#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) struct gk20a_instobj { - struct nvkm_instobj base; - /* Must be second member here - see nouveau_gpuobj_map_vm() */ - struct nvkm_mem *mem; - /* Pointed by mem */ - struct nvkm_mem _mem; + struct nvkm_memory memory; + struct gk20a_instmem *imem; + struct nvkm_mem mem; }; /* @@ -80,6 +81,7 @@ struct gk20a_instobj_iommu { struct gk20a_instmem { struct nvkm_instmem base; + unsigned long lock_flags; spinlock_t lock; u64 addr; @@ -93,6 +95,42 @@ struct gk20a_instmem { struct dma_attrs attrs; }; +static enum nvkm_memory_target +gk20a_instobj_target(struct nvkm_memory *memory) +{ + return NVKM_MEM_TARGET_HOST; +} + +static u64 +gk20a_instobj_addr(struct nvkm_memory *memory) +{ + return gk20a_instobj(memory)->mem.offset; + +} + +static u64 +gk20a_instobj_size(struct nvkm_memory *memory) +{ + return (u64)gk20a_instobj(memory)->mem.size << 12; +} + +static void __iomem * +gk20a_instobj_acquire(struct nvkm_memory *memory) +{ + struct gk20a_instmem *imem = gk20a_instobj(memory)->imem; + unsigned long flags; + spin_lock_irqsave(&imem->lock, flags); + imem->lock_flags = flags; + return NULL; +} + +static void +gk20a_instobj_release(struct nvkm_memory *memory) +{ + struct gk20a_instmem *imem = gk20a_instobj(memory)->imem; + spin_unlock_irqrestore(&imem->lock, imem->lock_flags); +} + /* * Use PRAMIN to read/write data and avoid coherency issues. * PRAMIN uses the GPU path and ensures data will always be coherent. @@ -103,56 +141,57 @@ struct gk20a_instmem { */ static u32 -gk20a_instobj_rd32(struct nvkm_object *object, u64 offset) +gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset) { - struct gk20a_instmem *imem = (void *)nvkm_instmem(object); - struct gk20a_instobj *node = (void *)object; + struct gk20a_instobj *node = gk20a_instobj(memory); + struct gk20a_instmem *imem = node->imem; struct nvkm_device *device = imem->base.subdev.device; - unsigned long flags; - u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; - u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; + u64 base = (node->mem.offset + offset) & 0xffffff00000ULL; + u64 addr = (node->mem.offset + offset) & 0x000000fffffULL; u32 data; - spin_lock_irqsave(&imem->lock, flags); if (unlikely(imem->addr != base)) { nvkm_wr32(device, 0x001700, base >> 16); imem->addr = base; } data = nvkm_rd32(device, 0x700000 + addr); - spin_unlock_irqrestore(&imem->lock, flags); return data; } static void -gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data) +gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) { - struct gk20a_instmem *imem = (void *)nvkm_instmem(object); - struct gk20a_instobj *node = (void *)object; + struct gk20a_instobj *node = gk20a_instobj(memory); + struct gk20a_instmem *imem = node->imem; struct nvkm_device *device = imem->base.subdev.device; - unsigned long flags; - u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; - u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; + u64 base = (node->mem.offset + offset) & 0xffffff00000ULL; + u64 addr = (node->mem.offset + offset) & 0x000000fffffULL; - spin_lock_irqsave(&imem->lock, flags); if (unlikely(imem->addr != base)) { nvkm_wr32(device, 0x001700, base >> 16); imem->addr = base; } nvkm_wr32(device, 0x700000 + addr, data); - spin_unlock_irqrestore(&imem->lock, flags); +} + +static void +gk20a_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset) +{ + struct gk20a_instobj *node = gk20a_instobj(memory); + nvkm_vm_map_at(vma, offset, &node->mem); } static void gk20a_instobj_dtor_dma(struct gk20a_instobj *_node) { struct gk20a_instobj_dma *node = (void *)_node; - struct gk20a_instmem *imem = (void *)nvkm_instmem(node); + struct gk20a_instmem *imem = _node->imem; struct device *dev = nv_device_base(nv_device(imem)); if (unlikely(!node->cpuaddr)) return; - dma_free_attrs(dev, _node->mem->size << PAGE_SHIFT, node->cpuaddr, + dma_free_attrs(dev, _node->mem.size << PAGE_SHIFT, node->cpuaddr, node->handle, &imem->attrs); } @@ -160,21 +199,21 @@ static void gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node) { struct gk20a_instobj_iommu *node = (void *)_node; - struct gk20a_instmem *imem = (void *)nvkm_instmem(node); + struct gk20a_instmem *imem = _node->imem; struct nvkm_mm_node *r; int i; - if (unlikely(list_empty(&_node->mem->regions))) + if (unlikely(list_empty(&_node->mem.regions))) return; - r = list_first_entry(&_node->mem->regions, struct nvkm_mm_node, + r = list_first_entry(&_node->mem.regions, struct nvkm_mm_node, rl_entry); /* clear bit 34 to unmap pages */ r->offset &= ~BIT(34 - imem->iommu_pgshift); /* Unmap pages from GPU address space and free them */ - for (i = 0; i < _node->mem->size; i++) { + for (i = 0; i < _node->mem.size; i++) { iommu_unmap(imem->domain, (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE); __free_page(node->pages[i]); @@ -186,36 +225,44 @@ gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node) mutex_unlock(imem->mm_mutex); } -static void -gk20a_instobj_dtor(struct nvkm_object *object) +static void * +gk20a_instobj_dtor(struct nvkm_memory *memory) { - struct gk20a_instobj *node = (void *)object; - struct gk20a_instmem *imem = (void *)nvkm_instmem(node); + struct gk20a_instobj *node = gk20a_instobj(memory); + struct gk20a_instmem *imem = node->imem; if (imem->domain) gk20a_instobj_dtor_iommu(node); else gk20a_instobj_dtor_dma(node); - nvkm_instobj_destroy(&node->base); + return node; } +static const struct nvkm_memory_func +gk20a_instobj_func = { + .dtor = gk20a_instobj_dtor, + .target = gk20a_instobj_target, + .addr = gk20a_instobj_addr, + .size = gk20a_instobj_size, + .acquire = gk20a_instobj_acquire, + .release = gk20a_instobj_release, + .rd32 = gk20a_instobj_rd32, + .wr32 = gk20a_instobj_wr32, + .map = gk20a_instobj_map, +}; + static int -gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 npages, u32 align, +gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align, struct gk20a_instobj **_node) { struct gk20a_instobj_dma *node; - struct gk20a_instmem *imem = (void *)nvkm_instmem(parent); struct nvkm_subdev *subdev = &imem->base.subdev; - struct device *dev = nv_device_base(nv_device(parent)); - int ret; + struct device *dev = subdev->device->dev; - ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node), - (void **)&node); + if (!(node = kzalloc(sizeof(*node), GFP_KERNEL))) + return -ENOMEM; *_node = &node->base; - if (ret) - return ret; node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, &node->handle, GFP_KERNEL, @@ -236,32 +283,28 @@ gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, node->r.offset = node->handle >> 12; node->r.length = (npages << PAGE_SHIFT) >> 12; - node->base._mem.offset = node->handle; + node->base.mem.offset = node->handle; - INIT_LIST_HEAD(&node->base._mem.regions); - list_add_tail(&node->r.rl_entry, &node->base._mem.regions); + INIT_LIST_HEAD(&node->base.mem.regions); + list_add_tail(&node->r.rl_entry, &node->base.mem.regions); return 0; } static int -gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 npages, u32 align, +gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align, struct gk20a_instobj **_node) { struct gk20a_instobj_iommu *node; - struct gk20a_instmem *imem = (void *)nvkm_instmem(parent); struct nvkm_subdev *subdev = &imem->base.subdev; struct nvkm_mm_node *r; int ret; int i; - ret = nvkm_instobj_create_(parent, engine, oclass, - sizeof(*node) + sizeof(node->pages[0]) * npages, - (void **)&node); + if (!(node = kzalloc(sizeof(*node) + + sizeof( node->pages[0]) * npages, GFP_KERNEL))) + return -ENOMEM; *_node = &node->base; - if (ret) - return ret; /* Allocate backing memory */ for (i = 0; i < npages; i++) { @@ -305,10 +348,10 @@ gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine, /* Bit 34 tells that an address is to be resolved through the IOMMU */ r->offset |= BIT(34 - imem->iommu_pgshift); - node->base._mem.offset = ((u64)r->offset) << imem->iommu_pgshift; + node->base.mem.offset = ((u64)r->offset) << imem->iommu_pgshift; - INIT_LIST_HEAD(&node->base._mem.regions); - list_add_tail(&r->rl_entry, &node->base._mem.regions); + INIT_LIST_HEAD(&node->base.mem.regions); + list_add_tail(&r->rl_entry, &node->base.mem.regions); return 0; @@ -325,64 +368,45 @@ free_pages: } static int -gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 _size, - struct nvkm_object **pobject) +gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, + struct nvkm_memory **pmemory) { - struct nvkm_instobj_args *args = data; - struct gk20a_instmem *imem = (void *)nvkm_instmem(parent); + struct gk20a_instmem *imem = gk20a_instmem(base); struct gk20a_instobj *node; struct nvkm_subdev *subdev = &imem->base.subdev; - u32 size, align; int ret; nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__, - imem->domain ? "IOMMU" : "DMA", args->size, args->align); + imem->domain ? "IOMMU" : "DMA", size, align); /* Round size and align to page bounds */ - size = max(roundup(args->size, PAGE_SIZE), PAGE_SIZE); - align = max(roundup(args->align, PAGE_SIZE), PAGE_SIZE); + size = max(roundup(size, PAGE_SIZE), PAGE_SIZE); + align = max(roundup(align, PAGE_SIZE), PAGE_SIZE); if (imem->domain) - ret = gk20a_instobj_ctor_iommu(parent, engine, oclass, - size >> PAGE_SHIFT, align, &node); + ret = gk20a_instobj_ctor_iommu(imem, size >> PAGE_SHIFT, + align, &node); else - ret = gk20a_instobj_ctor_dma(parent, engine, oclass, - size >> PAGE_SHIFT, align, &node); - *pobject = nv_object(node); + ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT, + align, &node); if (ret) return ret; + *pmemory = &node->memory; - node->mem = &node->_mem; + nvkm_memory_ctor(&gk20a_instobj_func, &node->memory); + node->imem = imem; /* present memory for being mapped using small pages */ - node->mem->size = size >> 12; - node->mem->memtype = 0; - node->mem->page_shift = 12; - - node->base.addr = node->mem->offset; - node->base.size = size; + node->mem.size = size >> 12; + node->mem.memtype = 0; + node->mem.page_shift = 12; nvkm_debug(subdev, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n", - size, align, node->mem->offset); + size, align, node->mem.offset); return 0; } -static struct nvkm_instobj_impl -gk20a_instobj_oclass = { - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk20a_instobj_ctor, - .dtor = gk20a_instobj_dtor, - .init = _nvkm_instobj_init, - .fini = _nvkm_instobj_fini, - .rd32 = gk20a_instobj_rd32, - .wr32 = gk20a_instobj_wr32, - }, -}; - - - static int gk20a_instmem_fini(struct nvkm_object *object, bool suspend) { @@ -440,5 +464,7 @@ gk20a_instmem_oclass = &(struct nvkm_instmem_impl) { .init = _nvkm_instmem_init, .fini = gk20a_instmem_fini, }, - .instobj = &gk20a_instobj_oclass.base, + .memory_new = gk20a_instobj_new, + .persistent = true, + .zero = false, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c index 8ba95f366e2f..c499e485373b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c @@ -21,83 +21,119 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#define nv04_instmem(p) container_of((p), struct nv04_instmem, base) +#include "priv.h" +#include #include +struct nv04_instmem { + struct nvkm_instmem base; + struct nvkm_mm heap; +}; + /****************************************************************************** * instmem object implementation *****************************************************************************/ +#define nv04_instobj(p) container_of((p), struct nv04_instobj, memory) -static u32 -nv04_instobj_rd32(struct nvkm_object *object, u64 addr) +struct nv04_instobj { + struct nvkm_memory memory; + struct nv04_instmem *imem; + struct nvkm_mm_node *node; +}; + +static enum nvkm_memory_target +nv04_instobj_target(struct nvkm_memory *memory) +{ + return NVKM_MEM_TARGET_INST; +} + +static u64 +nv04_instobj_addr(struct nvkm_memory *memory) +{ + return nv04_instobj(memory)->node->offset; +} + +static u64 +nv04_instobj_size(struct nvkm_memory *memory) +{ + return nv04_instobj(memory)->node->length; +} + +static void __iomem * +nv04_instobj_acquire(struct nvkm_memory *memory) { - struct nvkm_instmem *imem = nvkm_instmem(object); - struct nv04_instobj *node = (void *)object; - return imem->func->rd32(imem, node->mem->offset + addr); + struct nv04_instobj *iobj = nv04_instobj(memory); + struct nvkm_device *device = iobj->imem->base.subdev.device; + return device->pri + 0x700000 + iobj->node->offset; } static void -nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data) +nv04_instobj_release(struct nvkm_memory *memory) { - struct nvkm_instmem *imem = nvkm_instmem(object); - struct nv04_instobj *node = (void *)object; - imem->func->wr32(imem, node->mem->offset + addr, data); +} + +static u32 +nv04_instobj_rd32(struct nvkm_memory *memory, u64 offset) +{ + struct nv04_instobj *iobj = nv04_instobj(memory); + struct nvkm_device *device = iobj->imem->base.subdev.device; + return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); } static void -nv04_instobj_dtor(struct nvkm_object *object) +nv04_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) { - struct nv04_instmem *imem = (void *)nvkm_instmem(object); - struct nv04_instobj *node = (void *)object; - mutex_lock(&imem->base.subdev.mutex); - nvkm_mm_free(&imem->heap, &node->mem); - mutex_unlock(&imem->base.subdev.mutex); - nvkm_instobj_destroy(&node->base); + struct nv04_instobj *iobj = nv04_instobj(memory); + struct nvkm_device *device = iobj->imem->base.subdev.device; + nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); } +static void * +nv04_instobj_dtor(struct nvkm_memory *memory) +{ + struct nv04_instobj *iobj = nv04_instobj(memory); + mutex_lock(&iobj->imem->base.subdev.mutex); + nvkm_mm_free(&iobj->imem->heap, &iobj->node); + mutex_unlock(&iobj->imem->base.subdev.mutex); + return iobj; +} + +static const struct nvkm_memory_func +nv04_instobj_func = { + .dtor = nv04_instobj_dtor, + .target = nv04_instobj_target, + .size = nv04_instobj_size, + .addr = nv04_instobj_addr, + .acquire = nv04_instobj_acquire, + .release = nv04_instobj_release, + .rd32 = nv04_instobj_rd32, + .wr32 = nv04_instobj_wr32, +}; + static int -nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, + struct nvkm_memory **pmemory) { - struct nv04_instmem *imem = (void *)nvkm_instmem(parent); - struct nv04_instobj *node; - struct nvkm_instobj_args *args = data; + struct nv04_instmem *imem = nv04_instmem(base); + struct nv04_instobj *iobj; int ret; - if (!args->align) - args->align = 1; + if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) + return -ENOMEM; + *pmemory = &iobj->memory; - ret = nvkm_instobj_create(parent, engine, oclass, &node); - *pobject = nv_object(node); - if (ret) - return ret; + nvkm_memory_ctor(&nv04_instobj_func, &iobj->memory); + iobj->imem = imem; mutex_lock(&imem->base.subdev.mutex); - ret = nvkm_mm_head(&imem->heap, 0, 1, args->size, args->size, - args->align, &node->mem); + ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, + align ? align : 1, &iobj->node); mutex_unlock(&imem->base.subdev.mutex); - if (ret) - return ret; - - node->base.addr = node->mem->offset; - node->base.size = node->mem->length; - return 0; + return ret; } -struct nvkm_instobj_impl -nv04_instobj_oclass = { - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_instobj_ctor, - .dtor = nv04_instobj_dtor, - .init = _nvkm_instobj_init, - .fini = _nvkm_instobj_fini, - .rd32 = nv04_instobj_rd32, - .wr32 = nv04_instobj_wr32, - }, -}; - /****************************************************************************** * instmem subdev implementation *****************************************************************************/ @@ -114,17 +150,15 @@ nv04_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data) nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); } -void +static void nv04_instmem_dtor(struct nvkm_object *object) { struct nv04_instmem *imem = (void *)object; - nvkm_gpuobj_ref(NULL, &imem->ramfc); - nvkm_gpuobj_ref(NULL, &imem->ramro); - nvkm_ramht_ref(NULL, &imem->ramht); - nvkm_gpuobj_ref(NULL, &imem->vbios); + nvkm_gpuobj_ref(NULL, &imem->base.ramfc); + nvkm_gpuobj_ref(NULL, &imem->base.ramro); + nvkm_ramht_ref(NULL, &imem->base.ramht); + nvkm_gpuobj_ref(NULL, &imem->base.vbios); nvkm_mm_fini(&imem->heap); - if (imem->iomem) - iounmap(imem->iomem); nvkm_instmem_destroy(&imem->base); } @@ -158,24 +192,26 @@ nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, /* 0x00000-0x10000: reserve for probable vbios image */ ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x10000, 0, 0, - &imem->vbios); + &imem->base.vbios); if (ret) return ret; /* 0x10000-0x18000: reserve for RAMHT */ - ret = nvkm_ramht_new(nv_object(imem), NULL, 0x08000, 0, &imem->ramht); + ret = nvkm_ramht_new(nv_object(imem), NULL, 0x08000, 0, + &imem->base.ramht); if (ret) return ret; /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */ ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x00800, 0, - NVOBJ_FLAG_ZERO_ALLOC, &imem->ramfc); + NVOBJ_FLAG_ZERO_ALLOC, + &imem->base.ramfc); if (ret) return ret; /* 0x18800-0x18a00: reserve for RAMRO */ ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x00200, 0, 0, - &imem->ramro); + &imem->base.ramro); if (ret) return ret; @@ -191,5 +227,7 @@ nv04_instmem_oclass = &(struct nvkm_instmem_impl) { .init = _nvkm_instmem_init, .fini = _nvkm_instmem_fini, }, - .instobj = &nv04_instobj_oclass.base, + .memory_new = nv04_instobj_new, + .persistent = false, + .zero = false, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h deleted file mode 100644 index 6065e34e2f0d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef __NV04_INSTMEM_H__ -#define __NV04_INSTMEM_H__ -#include "priv.h" - -#include - -extern struct nvkm_instobj_impl nv04_instobj_oclass; - -struct nv04_instmem { - struct nvkm_instmem base; - - void __iomem *iomem; - struct nvkm_mm heap; - - struct nvkm_gpuobj *vbios; - struct nvkm_ramht *ramht; - struct nvkm_gpuobj *ramro; - struct nvkm_gpuobj *ramfc; -}; - -static inline struct nv04_instmem * -nv04_instmem(void *obj) -{ - return (void *)nvkm_instmem(obj); -} - -struct nv04_instobj { - struct nvkm_instobj base; - struct nvkm_mm_node *mem; -}; - -void nv04_instmem_dtor(struct nvkm_object *); - -int nv04_instmem_alloc(struct nvkm_instmem *, struct nvkm_object *, - u32 size, u32 align, struct nvkm_object **pobject); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index c645e0261530..3ac55481cc97 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -21,11 +21,118 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#define nv40_instmem(p) container_of((p), struct nv40_instmem, base) +#include "priv.h" +#include #include #include +struct nv40_instmem { + struct nvkm_instmem base; + struct nvkm_mm heap; + void __iomem *iomem; +}; + +/****************************************************************************** + * instmem object implementation + *****************************************************************************/ +#define nv40_instobj(p) container_of((p), struct nv40_instobj, memory) + +struct nv40_instobj { + struct nvkm_memory memory; + struct nv40_instmem *imem; + struct nvkm_mm_node *node; +}; + +static enum nvkm_memory_target +nv40_instobj_target(struct nvkm_memory *memory) +{ + return NVKM_MEM_TARGET_INST; +} + +static u64 +nv40_instobj_addr(struct nvkm_memory *memory) +{ + return nv40_instobj(memory)->node->offset; +} + +static u64 +nv40_instobj_size(struct nvkm_memory *memory) +{ + return nv40_instobj(memory)->node->length; +} + +static void __iomem * +nv40_instobj_acquire(struct nvkm_memory *memory) +{ + struct nv40_instobj *iobj = nv40_instobj(memory); + return iobj->imem->iomem + iobj->node->offset; +} + +static void +nv40_instobj_release(struct nvkm_memory *memory) +{ +} + +static u32 +nv40_instobj_rd32(struct nvkm_memory *memory, u64 offset) +{ + struct nv40_instobj *iobj = nv40_instobj(memory); + return ioread32_native(iobj->imem->iomem + iobj->node->offset + offset); +} + +static void +nv40_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) +{ + struct nv40_instobj *iobj = nv40_instobj(memory); + iowrite32_native(data, iobj->imem->iomem + iobj->node->offset + offset); +} + +static void * +nv40_instobj_dtor(struct nvkm_memory *memory) +{ + struct nv40_instobj *iobj = nv40_instobj(memory); + mutex_lock(&iobj->imem->base.subdev.mutex); + nvkm_mm_free(&iobj->imem->heap, &iobj->node); + mutex_unlock(&iobj->imem->base.subdev.mutex); + return iobj; +} + +static const struct nvkm_memory_func +nv40_instobj_func = { + .dtor = nv40_instobj_dtor, + .target = nv40_instobj_target, + .size = nv40_instobj_size, + .addr = nv40_instobj_addr, + .acquire = nv40_instobj_acquire, + .release = nv40_instobj_release, + .rd32 = nv40_instobj_rd32, + .wr32 = nv40_instobj_wr32, +}; + +static int +nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, + struct nvkm_memory **pmemory) +{ + struct nv40_instmem *imem = nv40_instmem(base); + struct nv40_instobj *iobj; + int ret; + + if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) + return -ENOMEM; + *pmemory = &iobj->memory; + + nvkm_memory_ctor(&nv40_instobj_func, &iobj->memory); + iobj->imem = imem; + + mutex_lock(&imem->base.subdev.mutex); + ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, + align ? align : 1, &iobj->node); + mutex_unlock(&imem->base.subdev.mutex); + return ret; +} + /****************************************************************************** * instmem subdev implementation *****************************************************************************/ @@ -33,17 +140,31 @@ static u32 nv40_instmem_rd32(struct nvkm_instmem *obj, u32 addr) { - struct nv04_instmem *imem = container_of(obj, typeof(*imem), base); + struct nv40_instmem *imem = container_of(obj, typeof(*imem), base); return ioread32_native(imem->iomem + addr); } static void nv40_instmem_wr32(struct nvkm_instmem *obj, u32 addr, u32 data) { - struct nv04_instmem *imem = container_of(obj, typeof(*imem), base); + struct nv40_instmem *imem = container_of(obj, typeof(*imem), base); iowrite32_native(data, imem->iomem + addr); } +static void +nv40_instmem_dtor(struct nvkm_object *object) +{ + struct nv40_instmem *imem = (void *)object; + nvkm_gpuobj_ref(NULL, &imem->base.ramfc); + nvkm_gpuobj_ref(NULL, &imem->base.ramro); + nvkm_ramht_ref(NULL, &imem->base.ramht); + nvkm_gpuobj_ref(NULL, &imem->base.vbios); + nvkm_mm_fini(&imem->heap); + if (imem->iomem) + iounmap(imem->iomem); + nvkm_instmem_destroy(&imem->base); +} + static const struct nvkm_instmem_func nv40_instmem_func = { .rd32 = nv40_instmem_rd32, @@ -56,7 +177,7 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_object **pobject) { struct nvkm_device *device = (void *)parent; - struct nv04_instmem *imem; + struct nv40_instmem *imem; int ret, bar, vs; ret = nvkm_instmem_create(parent, engine, oclass, &imem); @@ -86,7 +207,7 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8); if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; - else if (nv44_gr_class(imem)) imem->base.reserved = 0x4980 * vs; + else if (nv44_gr_class(imem)) imem->base.reserved = 0x4980 * vs; else imem->base.reserved = 0x4a40 * vs; imem->base.reserved += 16 * 1024; imem->base.reserved *= 32; /* per-channel */ @@ -101,12 +222,13 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, /* 0x00000-0x10000: reserve for probable vbios image */ ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x10000, 0, 0, - &imem->vbios); + &imem->base.vbios); if (ret) return ret; /* 0x10000-0x18000: reserve for RAMHT */ - ret = nvkm_ramht_new(nv_object(imem), NULL, 0x08000, 0, &imem->ramht); + ret = nvkm_ramht_new(nv_object(imem), NULL, 0x08000, 0, + &imem->base.ramht); if (ret) return ret; @@ -114,7 +236,7 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, * 0x18200-0x20000: padding */ ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x08000, 0, 0, - &imem->ramro); + &imem->base.ramro); if (ret) return ret; @@ -122,7 +244,7 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, * 0x21000-0x40000: padding and some unknown crap */ ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x20000, 0, - NVOBJ_FLAG_ZERO_ALLOC, &imem->ramfc); + NVOBJ_FLAG_ZERO_ALLOC, &imem->base.ramfc); if (ret) return ret; @@ -134,9 +256,11 @@ nv40_instmem_oclass = &(struct nvkm_instmem_impl) { .base.handle = NV_SUBDEV(INSTMEM, 0x40), .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_instmem_ctor, - .dtor = nv04_instmem_dtor, + .dtor = nv40_instmem_dtor, .init = _nvkm_instmem_init, .fini = _nvkm_instmem_fini, }, - .instobj = &nv04_instobj_oclass.base, + .memory_new = nv40_instobj_new, + .persistent = false, + .zero = false, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index 4f6354df538a..535a8f9c23ce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -21,115 +21,201 @@ * * Authors: Ben Skeggs */ +#define nv50_instmem(p) container_of((p), struct nv50_instmem, base) #include "priv.h" +#include +#include #include +#include struct nv50_instmem { struct nvkm_instmem base; + unsigned long lock_flags; spinlock_t lock; u64 addr; }; +/****************************************************************************** + * instmem object implementation + *****************************************************************************/ +#define nv50_instobj(p) container_of((p), struct nv50_instobj, memory) + struct nv50_instobj { - struct nvkm_instobj base; + struct nvkm_memory memory; + struct nv50_instmem *imem; struct nvkm_mem *mem; + struct nvkm_vma bar; + void *map; }; -/****************************************************************************** - * instmem object implementation - *****************************************************************************/ +static enum nvkm_memory_target +nv50_instobj_target(struct nvkm_memory *memory) +{ + return NVKM_MEM_TARGET_VRAM; +} + +static u64 +nv50_instobj_addr(struct nvkm_memory *memory) +{ + return nv50_instobj(memory)->mem->offset; +} + +static u64 +nv50_instobj_size(struct nvkm_memory *memory) +{ + return (u64)nv50_instobj(memory)->mem->size << NVKM_RAM_MM_SHIFT; +} + +static void +nv50_instobj_boot(struct nvkm_memory *memory, struct nvkm_vm *vm) +{ + struct nv50_instobj *iobj = nv50_instobj(memory); + struct nvkm_subdev *subdev = &iobj->imem->base.subdev; + struct nvkm_device *device = subdev->device; + u64 size = nvkm_memory_size(memory); + void __iomem *map; + int ret; + + iobj->map = ERR_PTR(-ENOMEM); + + ret = nvkm_vm_get(vm, size, 12, NV_MEM_ACCESS_RW, &iobj->bar); + if (ret == 0) { + map = ioremap(nv_device_resource_start(device, 3) + + (u32)iobj->bar.offset, size); + if (map) { + nvkm_memory_map(memory, &iobj->bar, 0); + iobj->map = map; + } else { + nvkm_warn(subdev, "PRAMIN ioremap failed\n"); + nvkm_vm_put(&iobj->bar); + } + } else { + nvkm_warn(subdev, "PRAMIN exhausted\n"); + } +} + +static void +nv50_instobj_release(struct nvkm_memory *memory) +{ + struct nv50_instmem *imem = nv50_instobj(memory)->imem; + spin_unlock_irqrestore(&imem->lock, imem->lock_flags); +} + +static void __iomem * +nv50_instobj_acquire(struct nvkm_memory *memory) +{ + struct nv50_instobj *iobj = nv50_instobj(memory); + struct nv50_instmem *imem = iobj->imem; + struct nvkm_bar *bar = imem->base.subdev.device->bar; + struct nvkm_vm *vm; + unsigned long flags; + + if (!iobj->map && bar && bar->kmap && (vm = bar->kmap(bar))) + nvkm_memory_boot(memory, vm); + if (!IS_ERR_OR_NULL(iobj->map)) + return iobj->map; + + spin_lock_irqsave(&imem->lock, flags); + imem->lock_flags = flags; + return NULL; +} static u32 -nv50_instobj_rd32(struct nvkm_object *object, u64 offset) +nv50_instobj_rd32(struct nvkm_memory *memory, u64 offset) { - struct nv50_instmem *imem = (void *)nvkm_instmem(object); - struct nv50_instobj *node = (void *)object; + struct nv50_instobj *iobj = nv50_instobj(memory); + struct nv50_instmem *imem = iobj->imem; struct nvkm_device *device = imem->base.subdev.device; - unsigned long flags; - u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; - u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; + u64 base = (iobj->mem->offset + offset) & 0xffffff00000ULL; + u64 addr = (iobj->mem->offset + offset) & 0x000000fffffULL; u32 data; - spin_lock_irqsave(&imem->lock, flags); if (unlikely(imem->addr != base)) { nvkm_wr32(device, 0x001700, base >> 16); imem->addr = base; } data = nvkm_rd32(device, 0x700000 + addr); - spin_unlock_irqrestore(&imem->lock, flags); return data; } static void -nv50_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data) +nv50_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) { - struct nv50_instmem *imem = (void *)nvkm_instmem(object); - struct nv50_instobj *node = (void *)object; + struct nv50_instobj *iobj = nv50_instobj(memory); + struct nv50_instmem *imem = iobj->imem; struct nvkm_device *device = imem->base.subdev.device; - unsigned long flags; - u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; - u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; + u64 base = (iobj->mem->offset + offset) & 0xffffff00000ULL; + u64 addr = (iobj->mem->offset + offset) & 0x000000fffffULL; - spin_lock_irqsave(&imem->lock, flags); if (unlikely(imem->addr != base)) { nvkm_wr32(device, 0x001700, base >> 16); imem->addr = base; } nvkm_wr32(device, 0x700000 + addr, data); - spin_unlock_irqrestore(&imem->lock, flags); } static void -nv50_instobj_dtor(struct nvkm_object *object) +nv50_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset) { - struct nv50_instobj *node = (void *)object; - struct nvkm_ram *ram = nvkm_fb(object)->ram; - ram->func->put(ram, &node->mem); - nvkm_instobj_destroy(&node->base); + struct nv50_instobj *iobj = nv50_instobj(memory); + nvkm_vm_map_at(vma, offset, iobj->mem); } +static void * +nv50_instobj_dtor(struct nvkm_memory *memory) +{ + struct nv50_instobj *iobj = nv50_instobj(memory); + struct nvkm_ram *ram = iobj->imem->base.subdev.device->fb->ram; + if (!IS_ERR_OR_NULL(iobj->map)) { + nvkm_vm_put(&iobj->bar); + iounmap(iobj->map); + } + ram->func->put(ram, &iobj->mem); + return iobj; +} + +static const struct nvkm_memory_func +nv50_instobj_func = { + .dtor = nv50_instobj_dtor, + .target = nv50_instobj_target, + .size = nv50_instobj_size, + .addr = nv50_instobj_addr, + .boot = nv50_instobj_boot, + .acquire = nv50_instobj_acquire, + .release = nv50_instobj_release, + .rd32 = nv50_instobj_rd32, + .wr32 = nv50_instobj_wr32, + .map = nv50_instobj_map, +}; + static int -nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv50_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, + struct nvkm_memory **pmemory) { - struct nvkm_ram *ram = nvkm_fb(parent)->ram; - struct nvkm_instobj_args *args = data; - struct nv50_instobj *node; + struct nv50_instmem *imem = nv50_instmem(base); + struct nv50_instobj *iobj; + struct nvkm_ram *ram = imem->base.subdev.device->fb->ram; int ret; - args->size = max((args->size + 4095) & ~4095, (u32)4096); - args->align = max((args->align + 4095) & ~4095, (u32)4096); + if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) + return -ENOMEM; + *pmemory = &iobj->memory; - ret = nvkm_instobj_create(parent, engine, oclass, &node); - *pobject = nv_object(node); - if (ret) - return ret; + nvkm_memory_ctor(&nv50_instobj_func, &iobj->memory); + iobj->imem = imem; + + size = max((size + 4095) & ~4095, (u32)4096); + align = max((align + 4095) & ~4095, (u32)4096); - ret = ram->func->get(ram, args->size, args->align, 0, 0x800, - &node->mem); + ret = ram->func->get(ram, size, align, 0, 0x800, &iobj->mem); if (ret) return ret; - node->base.addr = node->mem->offset; - node->base.size = node->mem->size << 12; - node->mem->page_shift = 12; + iobj->mem->page_shift = 12; return 0; } -static struct nvkm_instobj_impl -nv50_instobj_oclass = { - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_instobj_ctor, - .dtor = nv50_instobj_dtor, - .init = _nvkm_instobj_init, - .fini = _nvkm_instobj_fini, - .rd32 = nv50_instobj_rd32, - .wr32 = nv50_instobj_wr32, - }, -}; - /****************************************************************************** * instmem subdev implementation *****************************************************************************/ @@ -168,5 +254,7 @@ nv50_instmem_oclass = &(struct nvkm_instmem_impl) { .init = _nvkm_instmem_init, .fini = nv50_instmem_fini, }, - .instobj = &nv50_instobj_oclass.base, + .memory_new = nv50_instobj_new, + .persistent = false, + .zero = false, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h index 819f615782cf..2b6d73005767 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -2,35 +2,12 @@ #define __NVKM_INSTMEM_PRIV_H__ #include -struct nvkm_instobj_impl { - struct nvkm_oclass base; -}; - -struct nvkm_instobj_args { - u32 size; - u32 align; -}; - -#define nvkm_instobj_create(p,e,o,d) \ - nvkm_instobj_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nvkm_instobj_destroy(p) ({ \ - struct nvkm_instobj *iobj = (p); \ - _nvkm_instobj_dtor(nv_object(iobj)); \ -}) -#define nvkm_instobj_init(p) \ - _nvkm_object_init(&(p)->base) -#define nvkm_instobj_fini(p,s) \ - _nvkm_object_fini(&(p)->base, (s)) - -int nvkm_instobj_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); -void _nvkm_instobj_dtor(struct nvkm_object *); -#define _nvkm_instobj_init _nvkm_object_init -#define _nvkm_instobj_fini _nvkm_object_fini - struct nvkm_instmem_impl { struct nvkm_oclass base; - struct nvkm_oclass *instobj; + int (*memory_new)(struct nvkm_instmem *, u32 size, u32 align, + bool zero, struct nvkm_memory **); + bool persistent; + bool zero; }; #define nvkm_instmem_create(p,e,o,d) \ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index e81d3170325f..35b6d33f6669 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -338,6 +338,25 @@ nvkm_vm_put(struct nvkm_vma *vma) nvkm_vm_ref(NULL, &vma->vm, NULL); } +int +nvkm_vm_boot(struct nvkm_vm *vm, u64 size) +{ + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_gpuobj *pgt; + int ret; + + ret = nvkm_gpuobj_new(nv_object(mmu), NULL, + (size >> mmu->spg_shift) * 8, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &pgt); + if (ret == 0) { + vm->pgt[0].refcount[0] = 1; + vm->pgt[0].obj[0] = pgt; + nvkm_memory_boot(pgt->memory, vm); + } + + return ret; +} + int nvkm_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, u32 block, struct lock_class_key *key, struct nvkm_vm **pvm) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index e801e57946ad..12d6ef461c62 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs */ #include -#include #include #include #include @@ -163,12 +162,9 @@ gf100_vm_flush(struct nvkm_vm *vm) { struct nvkm_mmu *mmu = (void *)vm->mmu; struct nvkm_device *device = mmu->subdev.device; - struct nvkm_bar *bar = device->bar; struct nvkm_vm_pgd *vpgd; u32 type; - bar->flush(bar); - type = 0x00000001; /* PAGE_ALL */ if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index b87fef9ee198..cd63b9288507 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs */ #include -#include #include #include @@ -156,12 +155,9 @@ nv50_vm_flush(struct nvkm_vm *vm) struct nvkm_mmu *mmu = (void *)vm->mmu; struct nvkm_subdev *subdev = &mmu->subdev; struct nvkm_device *device = subdev->device; - struct nvkm_bar *bar = device->bar; struct nvkm_engine *engine; int i, vme; - bar->flush(bar); - mutex_lock(&subdev->mutex); for (i = 0; i < NVDEV_SUBDEV_NR; i++) { if (!atomic_read(&vm->engref[i])) -- cgit v1.2.3 From 227c95d90a3c50defbc7b4f98605e13af4e6214c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:17 +1000 Subject: drm/nouveau/gr: directly use instmem where currently possible Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 27 +++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 48 ++++++++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 8 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 8 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 10 +++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 5 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 5 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 8 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 5 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 5 ++- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 7 +++- 15 files changed, 87 insertions(+), 63 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index a2e60b1ddb27..d04c015eea81 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1272,34 +1272,37 @@ gf100_grctx_generate(struct gf100_gr *gr) struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nvkm_gpuobj *chan; + struct nvkm_memory *chan; struct gf100_grctx info; int ret, i; + u64 addr; /* allocate memory to for a "channel", which we'll use to generate * the default context values */ - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x80000 + gr->size, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x80000 + gr->size, + 0x1000, true, &chan); if (ret) { nvkm_error(subdev, "failed to allocate chan memory, %d\n", ret); return ret; } + addr = nvkm_memory_addr(chan); + /* PGD pointer */ nvkm_kmap(chan); - nvkm_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); - nvkm_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); + nvkm_wo32(chan, 0x0200, lower_32_bits(addr + 0x1000)); + nvkm_wo32(chan, 0x0204, upper_32_bits(addr + 0x1000)); nvkm_wo32(chan, 0x0208, 0xffffffff); nvkm_wo32(chan, 0x020c, 0x000000ff); /* PGT[0] pointer */ nvkm_wo32(chan, 0x1000, 0x00000000); - nvkm_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); + nvkm_wo32(chan, 0x1004, 0x00000001 | (addr + 0x2000) >> 8); /* identity-map the whole "channel" into its own vm */ - for (i = 0; i < chan->size / 4096; i++) { - u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; + for (i = 0; i < nvkm_memory_size(chan) / 4096; i++) { + u64 addr = ((nvkm_memory_addr(chan) + (i * 4096)) >> 8) | 1; nvkm_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); nvkm_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); } @@ -1309,7 +1312,7 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_wo32(chan, 0x0214, 0x00000000); nvkm_done(chan); - nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8); + nvkm_wr32(device, 0x100cb8, (addr + 0x1000) >> 8); nvkm_wr32(device, 0x100cbc, 0x80000001); nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x100c80) & 0x00008000) @@ -1326,7 +1329,7 @@ gf100_grctx_generate(struct gf100_gr *gr) /* make channel current */ if (gr->firmware) { nvkm_wr32(device, 0x409840, 0x00000030); - nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); + nvkm_wr32(device, 0x409500, 0x80000000 | addr >> 12); nvkm_wr32(device, 0x409504, 0x00000003); nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800) & 0x00000010) @@ -1341,7 +1344,7 @@ gf100_grctx_generate(struct gf100_gr *gr) nvkm_done(chan); } else { nvkm_wr32(device, 0x409840, 0x80000000); - nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12); + nvkm_wr32(device, 0x409500, 0x80000000 | addr >> 12); nvkm_wr32(device, 0x409504, 0x00000001); nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800) & 0x80000000) @@ -1376,7 +1379,7 @@ gf100_grctx_generate(struct gf100_gr *gr) } done: - nvkm_gpuobj_ref(NULL, &chan); + nvkm_memory_del(&chan); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 1e712355a70b..362d5fa394d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -283,6 +283,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct gf100_gr_data *data = gr->mmio_data; struct gf100_gr_mmio *mmio = gr->mmio_list; struct gf100_gr_chan *chan; + struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_gpuobj *image; int ret, i; @@ -298,29 +299,32 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, * fuc to modify some per-context register settings on first load * of the context. */ - ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, - &chan->mmio); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100, + false, &chan->mmio); if (ret) return ret; - ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, - NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, - &chan->mmio_vma); + ret = nvkm_vm_get(vm, 0x1000, 12, NV_MEM_ACCESS_RW | + NV_MEM_ACCESS_SYS, &chan->mmio_vma); if (ret) return ret; + nvkm_memory_map(chan->mmio, &chan->mmio_vma, 0); + /* allocate buffers referenced by mmio list */ for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) { - ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size, - data->align, 0, &chan->data[i].mem); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, + data->size, data->align, false, + &chan->data[i].mem); if (ret) return ret; - ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access, - &chan->data[i].vma); + ret = nvkm_vm_get(vm, nvkm_memory_size(chan->data[i].mem), + 12, data->access, &chan->data[i].vma); if (ret) return ret; + nvkm_memory_map(chan->data[i].mem, &chan->data[i].vma, 0); data++; } @@ -372,12 +376,18 @@ gf100_gr_context_dtor(struct nvkm_object *object) int i; for (i = 0; i < ARRAY_SIZE(chan->data); i++) { - nvkm_gpuobj_unmap(&chan->data[i].vma); - nvkm_gpuobj_ref(NULL, &chan->data[i].mem); + if (chan->data[i].vma.node) { + nvkm_vm_unmap(&chan->data[i].vma); + nvkm_vm_put(&chan->data[i].vma); + } + nvkm_memory_del(&chan->data[i].mem); } - nvkm_gpuobj_unmap(&chan->mmio_vma); - nvkm_gpuobj_ref(NULL, &chan->mmio); + if (chan->mmio_vma.node) { + nvkm_vm_unmap(&chan->mmio_vma); + nvkm_vm_put(&chan->mmio_vma); + } + nvkm_memory_del(&chan->mmio); nvkm_gr_context_destroy(&chan->base); } @@ -1490,8 +1500,8 @@ gf100_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); - nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); - nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); gf100_gr_mmio(gr, oclass->mmio); @@ -1634,8 +1644,8 @@ gf100_gr_dtor(struct nvkm_object *object) gf100_gr_dtor_fw(&gr->fuc41ac); gf100_gr_dtor_fw(&gr->fuc41ad); - nvkm_gpuobj_ref(NULL, &gr->unk4188b8); - nvkm_gpuobj_ref(NULL, &gr->unk4188b4); + nvkm_memory_del(&gr->unk4188b8); + nvkm_memory_del(&gr->unk4188b4); nvkm_gr_destroy(&gr->base); } @@ -1675,12 +1685,12 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gr->firmware = true; } - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, &gr->unk4188b4); if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 0x1000, 256, 0, + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, &gr->unk4188b8); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index b23bc32536fe..62bf56906cbe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -95,8 +95,8 @@ struct gf100_gr { u8 ppc_nr[GPC_MAX]; u8 ppc_tpc_nr[GPC_MAX][4]; - struct nvkm_gpuobj *unk4188b4; - struct nvkm_gpuobj *unk4188b8; + struct nvkm_memory *unk4188b4; + struct nvkm_memory *unk4188b8; struct gf100_gr_data mmio_data[4]; struct gf100_gr_mmio mmio_list[4096/8]; @@ -109,11 +109,11 @@ struct gf100_gr { struct gf100_gr_chan { struct nvkm_gr_chan base; - struct nvkm_gpuobj *mmio; + struct nvkm_memory *mmio; struct nvkm_vma mmio_vma; int mmio_nr; struct { - struct nvkm_gpuobj *mem; + struct nvkm_memory *mem; struct nvkm_vma vma; } data[4]; }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 89bb10161554..94c6ca1d739a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -218,8 +218,8 @@ gk104_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); - nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); - nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); gf100_gr_mmio(gr, oclass->mmio); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index 6cb8ff3fb68a..a80fda50719a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -280,8 +280,8 @@ gk20a_gr_init(struct nvkm_object *object) return ret; /* MMU debug buffer */ - nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8); - nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8); + nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); + nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); if (oclass->init_gpc_mmu) oclass->init_gpc_mmu(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 1e451a9e2290..97b0e1ad040f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -339,8 +339,8 @@ gm107_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); - nvkm_wr32(device, GPC_BCAST(0x08b4), gr->unk4188b4->addr >> 8); - nvkm_wr32(device, GPC_BCAST(0x08b8), gr->unk4188b8->addr >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); + nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); gf100_gr_mmio(gr, oclass->mmio); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c index c3d2343d41d3..0a8d850051ee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c @@ -269,13 +269,13 @@ gm204_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff)); nvkm_wr32(device, 0x418890, 0x00000000); nvkm_wr32(device, 0x418894, 0x00000000); - nvkm_wr32(device, 0x4188b4, gr->unk4188b4->addr >> 8); - nvkm_wr32(device, 0x4188b8, gr->unk4188b8->addr >> 8); + nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(gr->unk4188b4) >> 8); + nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(gr->unk4188b8) >> 8); nvkm_mask(device, 0x4188b0, 0x00040000, 0x00040000); /*XXX: belongs in fb */ - nvkm_wr32(device, 0x100cc8, gr->unk4188b4->addr >> 8); - nvkm_wr32(device, 0x100ccc, gr->unk4188b8->addr >> 8); + nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); + nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000); gf100_gr_mmio(gr, oclass->mmio); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index f4b8eaced1b6..6e5b321128a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -249,6 +249,7 @@ nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv20_gr *gr; int ret; @@ -257,8 +258,8 @@ nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, + &gr->ctxtab); if (ret) return ret; @@ -274,7 +275,7 @@ void nv20_gr_dtor(struct nvkm_object *object) { struct nv20_gr *gr = (void *)object; - nvkm_gpuobj_ref(NULL, &gr->ctxtab); + nvkm_memory_del(&gr->ctxtab); nvkm_gr_destroy(&gr->base); } @@ -292,7 +293,8 @@ nv20_gr_init(struct nvkm_object *object) if (ret) return ret; - nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); + nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, + nvkm_memory_addr(gr->ctxtab) >> 4); if (nv_device(gr)->chipset == 0x20) { nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index 06dfe4bd50b1..bffbba075b4d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -4,7 +4,7 @@ struct nv20_gr { struct nvkm_gr base; - struct nvkm_gpuobj *ctxtab; + struct nvkm_memory *ctxtab; }; struct nv20_gr_chan { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index 1a186bd93f64..f0df11e47975 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -129,6 +129,7 @@ nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv20_gr *gr; int ret; @@ -137,8 +138,8 @@ nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, + &gr->ctxtab); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index dfb62dc6b3b8..3bc6dae76fa5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -96,6 +96,7 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv20_gr *gr; int ret; @@ -104,8 +105,8 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, + &gr->ctxtab); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 51573736bb48..3c369f4b09e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -131,6 +131,7 @@ nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv20_gr *gr; int ret; @@ -139,8 +140,8 @@ nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, + &gr->ctxtab); if (ret) return ret; @@ -165,7 +166,8 @@ nv30_gr_init(struct nvkm_object *object) if (ret) return ret; - nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, gr->ctxtab->addr >> 4); + nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, + nvkm_memory_addr(gr->ctxtab) >> 4); nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index f9d71185ee74..48bd9da606be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -130,6 +130,7 @@ nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv20_gr *gr; int ret; @@ -138,8 +139,8 @@ nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, + &gr->ctxtab); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index c6357f2fdb36..d25d3303f2fd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -130,6 +130,7 @@ nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv20_gr *gr; int ret; @@ -138,8 +139,8 @@ nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16, - NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, + &gr->ctxtab); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index 6f284e5dc2c8..9c712818528b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -321,12 +321,15 @@ nvkm_vm_get(struct nvkm_vm *vm, u64 size, u32 page_shift, u32 access, void nvkm_vm_put(struct nvkm_vma *vma) { - struct nvkm_vm *vm = vma->vm; - struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_mmu *mmu; + struct nvkm_vm *vm; u32 fpde, lpde; if (unlikely(vma->node == NULL)) return; + vm = vma->vm; + mmu = vm->mmu; + fpde = (vma->node->offset >> mmu->pgt_bits); lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; -- cgit v1.2.3 From a65955e19e769e92a0e29cccdc29aea0b19f3809 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:18 +1000 Subject: drm/nouveau/gr: remove dependence on namedb/engctx lookup Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 81 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 2 - drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 787 ++++++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 104 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 21 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 59 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 34 +- 15 files changed, 593 insertions(+), 533 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 362d5fa394d4..c6ff24b5a11d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -26,12 +26,11 @@ #include "fuc/os.h" #include -#include #include -#include #include #include #include +#include #include #include @@ -233,39 +232,39 @@ gf100_fermi_ofuncs = { .mthd = gf100_fermi_mthd, }; -static int -gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd, - void *pdata, u32 size) +static void +gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data) { - struct gf100_gr *gr = (void *)object->engine; - struct nvkm_device *device = gr->base.engine.subdev.device; - if (size >= sizeof(u32)) { - u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; - nvkm_wr32(device, 0x419e44, data); - nvkm_wr32(device, 0x419e4c, data); - return 0; - } - return -EINVAL; + nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000); + nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000); } -struct nvkm_omthds -gf100_gr_9097_omthds[] = { - { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, - {} -}; - -struct nvkm_omthds -gf100_gr_90c0_omthds[] = { - { 0x1528, 0x1528, gf100_gr_set_shader_exceptions }, - {} -}; +static bool +gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) +{ + switch (class & 0x00ff) { + case 0x97: + case 0xc0: + switch (mthd) { + case 0x1528: + gf100_gr_mthd_set_shader_exceptions(device, data); + return true; + default: + break; + } + break; + default: + break; + } + return false; +} struct nvkm_oclass gf100_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, - { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { FERMI_A, &gf100_fermi_ofuncs }, + { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, {} }; @@ -365,7 +364,6 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_wo32(image, 0x2c, 0); } nvkm_done(image); - return 0; } @@ -1160,10 +1158,8 @@ gf100_gr_intr(struct nvkm_subdev *subdev) { struct gf100_gr *gr = (void *)subdev; struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_fifo *fifo = device->fifo; - struct nvkm_engine *engine = nv_engine(subdev); - struct nvkm_object *engctx; - struct nvkm_handle *handle; + struct nvkm_fifo_chan *chan; + unsigned long flags; u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; u32 stat = nvkm_rd32(device, 0x400100); u32 addr = nvkm_rd32(device, 0x400704); @@ -1174,14 +1170,14 @@ gf100_gr_intr(struct nvkm_subdev *subdev) u32 class; int chid; + chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); + chid = chan ? chan->chid : -1; + if (nv_device(gr)->card_type < NV_E0 || subc < 4) class = nvkm_rd32(device, 0x404200 + (subc * 4)); else class = 0x0000; - engctx = nvkm_engctx_get(engine, inst); - chid = fifo->chid(fifo, engctx); - if (stat & 0x00000001) { /* * notifier interrupt, only needed for cyclestats @@ -1192,14 +1188,12 @@ gf100_gr_intr(struct nvkm_subdev *subdev) } if (stat & 0x00000010) { - handle = nvkm_handle_get_class(engctx, class); - if (!handle || nv_call(handle->object, mthd, data)) { + if (!gf100_gr_mthd_sw(device, class, mthd, data)) { nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " "subc %d class %04x mthd %04x data %08x\n", - chid, inst << 12, nvkm_client_name(engctx), + chid, inst << 12, nvkm_client_name(chan), subc, class, mthd, data); } - nvkm_handle_put(handle); nvkm_wr32(device, 0x400100, 0x00000010); stat &= ~0x00000010; } @@ -1207,7 +1201,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) if (stat & 0x00000020) { nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " "subc %d class %04x mthd %04x data %08x\n", - chid, inst << 12, nvkm_client_name(engctx), subc, + chid, inst << 12, nvkm_client_name(chan), subc, class, mthd, data); nvkm_wr32(device, 0x400100, 0x00000020); stat &= ~0x00000020; @@ -1219,15 +1213,14 @@ gf100_gr_intr(struct nvkm_subdev *subdev) nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " "subc %d class %04x mthd %04x data %08x\n", code, en ? en->name : "", chid, inst << 12, - nvkm_client_name(engctx), subc, class, mthd, data); + nvkm_client_name(chan), subc, class, mthd, data); nvkm_wr32(device, 0x400100, 0x00100000); stat &= ~0x00100000; } if (stat & 0x00200000) { nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", - chid, inst << 12, - nvkm_client_name(engctx)); + chid, inst << 12, nvkm_client_name(chan)); gf100_gr_trap_intr(gr); nvkm_wr32(device, 0x400100, 0x00200000); stat &= ~0x00200000; @@ -1245,7 +1238,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) } nvkm_wr32(device, 0x400500, 0x00010001); - nvkm_engctx_put(engctx); + nvkm_fifo_chan_put(device->fifo, flags, &chan); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 62bf56906cbe..612d5346eae9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -152,8 +152,6 @@ int gm204_gr_init(struct nvkm_object *); extern struct nvkm_ofuncs gf100_fermi_ofuncs; extern struct nvkm_oclass gf100_gr_sclass[]; -extern struct nvkm_omthds gf100_gr_9097_omthds[]; -extern struct nvkm_omthds gf100_gr_90c0_omthds[]; extern struct nvkm_oclass gf110_gr_sclass[]; extern struct nvkm_oclass gk110_gr_sclass[]; extern struct nvkm_oclass gm204_gr_sclass[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 8df73421c78c..1e8290ab1d37 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -34,9 +34,9 @@ static struct nvkm_oclass gf108_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, - { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { FERMI_A, &gf100_fermi_ofuncs }, + { FERMI_B, &gf100_fermi_ofuncs }, + { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index ef76e2dd1d31..4fe0f969de82 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -34,10 +34,10 @@ struct nvkm_oclass gf110_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, - { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { FERMI_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { FERMI_A, &gf100_fermi_ofuncs }, + { FERMI_B, &gf100_fermi_ofuncs }, + { FERMI_C, &gf100_fermi_ofuncs }, + { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 94c6ca1d739a..a00731979698 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -36,8 +36,8 @@ static struct nvkm_oclass gk104_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs }, - { KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { KEPLER_A, &gf100_fermi_ofuncs }, + { KEPLER_COMPUTE_A, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index f4cd8e5546af..ec21f62e7248 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -36,8 +36,8 @@ struct nvkm_oclass gk110_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { KEPLER_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { KEPLER_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { KEPLER_B, &gf100_fermi_ofuncs }, + { KEPLER_COMPUTE_B, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index a80fda50719a..c213e9a005c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -29,8 +29,8 @@ static struct nvkm_oclass gk20a_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs }, - { KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { KEPLER_C, &gf100_fermi_ofuncs }, + { KEPLER_COMPUTE_A, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index 97b0e1ad040f..aad5fdb29c60 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -37,8 +37,8 @@ static struct nvkm_oclass gm107_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { MAXWELL_A, &gf100_fermi_ofuncs }, + { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c index 0a8d850051ee..39f42a1c2b78 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c @@ -34,8 +34,8 @@ struct nvkm_oclass gm204_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { MAXWELL_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { MAXWELL_B, &gf100_fermi_ofuncs }, + { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 719ebfb6e640..87388926efa6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -29,8 +29,8 @@ static struct nvkm_oclass gm20b_gr_sclass[] = { { FERMI_TWOD_A, &nvkm_object_ofuncs }, { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { MAXWELL_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds }, - { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds }, + { MAXWELL_B, &gf100_fermi_ofuncs }, + { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 617161e4fc15..b15b86478c4f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -25,7 +25,6 @@ #include "regs.h" #include -#include #include #include #include @@ -443,42 +442,34 @@ nv04_gr(struct nv04_gr_chan *chan) */ static void -nv04_gr_set_ctx1(struct nvkm_object *obj, u32 mask, u32 value) +nv04_gr_set_ctx1(struct nvkm_device *device, u32 inst, u32 mask, u32 value) { - struct nvkm_gpuobj *object = container_of(obj, typeof(*object), object); - struct nv04_gr *gr = (void *)object->object.engine; - struct nvkm_device *device = gr->base.engine.subdev.device; int subc = (nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; u32 tmp; - nvkm_kmap(object); - tmp = nvkm_ro32(object, 0x00); + tmp = nvkm_rd32(device, 0x700000 + inst); tmp &= ~mask; tmp |= value; - nvkm_wo32(object, 0x00, tmp); - nvkm_done(object); + nvkm_wr32(device, 0x700000 + inst, tmp); nvkm_wr32(device, NV04_PGRAPH_CTX_SWITCH1, tmp); - nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); + nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc << 2), tmp); } static void -nv04_gr_set_ctx_val(struct nvkm_object *obj, u32 mask, u32 value) +nv04_gr_set_ctx_val(struct nvkm_device *device, u32 inst, u32 mask, u32 value) { - struct nvkm_gpuobj *object = container_of(obj, typeof(*object), object); int class, op, valid = 1; u32 tmp, ctx1; - nvkm_kmap(object); - ctx1 = nvkm_ro32(object, 0x00); + ctx1 = nvkm_rd32(device, 0x700000 + inst); class = ctx1 & 0xff; op = (ctx1 >> 15) & 7; - tmp = nvkm_ro32(object, 0x0c); + tmp = nvkm_rd32(device, 0x70000c + inst); tmp &= ~mask; tmp |= value; - nvkm_wo32(object, 0x0c, tmp); - nvkm_done(object); + nvkm_wr32(device, 0x70000c + inst, tmp); /* check for valid surf2d/surf_dst/surf_color */ if (!(tmp & 0x02000000)) @@ -510,39 +501,32 @@ nv04_gr_set_ctx_val(struct nvkm_object *obj, u32 mask, u32 value) break; } - nv04_gr_set_ctx1(obj, 0x01000000, valid << 24); + nv04_gr_set_ctx1(device, inst, 0x01000000, valid << 24); } -static int -nv04_gr_mthd_set_operation(struct nvkm_object *obj, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_set_operation(struct nvkm_device *device, u32 inst, u32 data) { - struct nvkm_gpuobj *object = container_of(obj, typeof(*object), object); - u32 class = nvkm_ro32(object, 0) & 0xff; - u32 data = *(u32 *)args; + u8 class = nvkm_rd32(device, 0x700000) & 0x000000ff; if (data > 5) - return 1; + return false; /* Old versions of the objects only accept first three operations. */ if (data > 2 && class < 0x40) - return 1; - nv04_gr_set_ctx1(obj, 0x00038000, data << 15); + return false; + nv04_gr_set_ctx1(device, inst, 0x00038000, data << 15); /* changing operation changes set of objects needed for validation */ - nv04_gr_set_ctx_val(obj, 0, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0, 0); + return true; } -static int -nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_surf3d_clip_h(struct nvkm_device *device, u32 inst, u32 data) { - struct nv04_gr *gr = (void *)object->engine; - struct nvkm_device *device = gr->base.engine.subdev.device; - u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; if (min & 0x8000) /* too large */ - return 1; + return false; if (w & 0x8000) /* yes, it accepts negative for some reason. */ w |= 0xffff0000; @@ -550,21 +534,17 @@ nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd, max &= 0x3ffff; nvkm_wr32(device, 0x40053c, min); nvkm_wr32(device, 0x400544, max); - return 0; + return true; } -static int -nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_surf3d_clip_v(struct nvkm_device *device, u32 inst, u32 data) { - struct nv04_gr *gr = (void *)object->engine; - struct nvkm_device *device = gr->base.engine.subdev.device; - u32 data = *(u32 *)args; u32 min = data & 0xffff, max; u32 w = data >> 16; if (min & 0x8000) /* too large */ - return 1; + return false; if (w & 0x8000) /* yes, it accepts negative for some reason. */ w |= 0xffff0000; @@ -572,389 +552,492 @@ nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd, max &= 0x3ffff; nvkm_wr32(device, 0x400540, min); nvkm_wr32(device, 0x400548, max); - return 0; + return true; } -static u16 -nv04_gr_mthd_bind_class(struct nvkm_object *object, u32 *args, u32 size) +static u8 +nv04_gr_mthd_bind_class(struct nvkm_device *device, u32 inst) { - struct nvkm_instmem *imem = nvkm_instmem(object); - u32 inst = *(u32 *)args << 4; - return imem->func->rd32(imem, inst); + return nvkm_rd32(device, 0x700000 + (inst << 4)); } -static int -nv04_gr_mthd_bind_surf2d(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_surf2d(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx1(object, 0x00004000, 0); - nv04_gr_set_ctx_val(object, 0x02000000, 0); - return 0; + nv04_gr_set_ctx1(device, inst, 0x00004000, 0); + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); + return true; case 0x42: - nv04_gr_set_ctx1(object, 0x00004000, 0); - nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; + nv04_gr_set_ctx1(device, inst, 0x00004000, 0); + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx1(object, 0x00004000, 0); - nv04_gr_set_ctx_val(object, 0x02000000, 0); - return 0; + nv04_gr_set_ctx1(device, inst, 0x00004000, 0); + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); + return true; case 0x42: - nv04_gr_set_ctx1(object, 0x00004000, 0); - nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; + nv04_gr_set_ctx1(device, inst, 0x00004000, 0); + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); + return true; case 0x52: - nv04_gr_set_ctx1(object, 0x00004000, 0x00004000); - nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; + nv04_gr_set_ctx1(device, inst, 0x00004000, 0x00004000); + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); + return true; } - return 1; + return false; } -static int -nv01_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv01_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x08000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x08000000, 0); + return true; case 0x18: - nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_patt(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x08000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x08000000, 0); + return true; case 0x44: - nv04_gr_set_ctx_val(object, 0x08000000, 0x08000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x08000000, 0x08000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_rop(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_rop(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x10000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x10000000, 0); + return true; case 0x43: - nv04_gr_set_ctx_val(object, 0x10000000, 0x10000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x10000000, 0x10000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_beta1(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_beta1(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x20000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x20000000, 0); + return true; case 0x12: - nv04_gr_set_ctx_val(object, 0x20000000, 0x20000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x20000000, 0x20000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_beta4(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_beta4(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x40000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x40000000, 0); + return true; case 0x72: - nv04_gr_set_ctx_val(object, 0x40000000, 0x40000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x40000000, 0x40000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_surf_dst(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_surf_dst(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x02000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); + return true; case 0x58: - nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_surf_src(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_surf_src(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x04000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x04000000, 0); + return true; case 0x59: - nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_surf_color(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_surf_color(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x02000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0); + return true; case 0x5a: - nv04_gr_set_ctx_val(object, 0x02000000, 0x02000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x02000000, 0x02000000); + return true; } - return 1; + return false; } -static int -nv04_gr_mthd_bind_surf_zeta(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv04_gr_mthd_bind_surf_zeta(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx_val(object, 0x04000000, 0); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x04000000, 0); + return true; case 0x5b: - nv04_gr_set_ctx_val(object, 0x04000000, 0x04000000); - return 0; + nv04_gr_set_ctx_val(device, inst, 0x04000000, 0x04000000); + return true; } - return 1; + return false; } -static int -nv01_gr_mthd_bind_clip(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv01_gr_mthd_bind_clip(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx1(object, 0x2000, 0); - return 0; + nv04_gr_set_ctx1(device, inst, 0x2000, 0); + return true; case 0x19: - nv04_gr_set_ctx1(object, 0x2000, 0x2000); - return 0; + nv04_gr_set_ctx1(device, inst, 0x2000, 0x2000); + return true; } - return 1; + return false; } -static int -nv01_gr_mthd_bind_chroma(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static bool +nv01_gr_mthd_bind_chroma(struct nvkm_device *device, u32 inst, u32 data) { - switch (nv04_gr_mthd_bind_class(object, args, size)) { + switch (nv04_gr_mthd_bind_class(device, data)) { case 0x30: - nv04_gr_set_ctx1(object, 0x1000, 0); - return 0; + nv04_gr_set_ctx1(device, inst, 0x1000, 0); + return true; /* Yes, for some reason even the old versions of objects * accept 0x57 and not 0x17. Consistency be damned. */ case 0x57: - nv04_gr_set_ctx1(object, 0x1000, 0x1000); - return 0; + nv04_gr_set_ctx1(device, inst, 0x1000, 0x1000); + return true; } - return 1; + return false; } -static struct nvkm_omthds -nv03_gr_gdi_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_patt }, - { 0x0188, 0x0188, nv04_gr_mthd_bind_rop }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_beta1 }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv03_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_patt; break; + case 0x0188: func = nv04_gr_mthd_bind_rop; break; + case 0x018c: func = nv04_gr_mthd_bind_beta1; break; + case 0x0190: func = nv04_gr_mthd_bind_surf_dst; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_gdi_omthds[] = { - { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_gdi(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0188: func = nv04_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_beta4; break; + case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv01_gr_blit_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, - { 0x018c, 0x018c, nv01_gr_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst }, - { 0x019c, 0x019c, nv04_gr_mthd_bind_surf_src }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv01_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_chroma; break; + case 0x0188: func = nv01_gr_mthd_bind_clip; break; + case 0x018c: func = nv01_gr_mthd_bind_patt; break; + case 0x0190: func = nv04_gr_mthd_bind_rop; break; + case 0x0194: func = nv04_gr_mthd_bind_beta1; break; + case 0x0198: func = nv04_gr_mthd_bind_surf_dst; break; + case 0x019c: func = nv04_gr_mthd_bind_surf_src; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_blit_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 }, - { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_blit(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_chroma; break; + case 0x0188: func = nv01_gr_mthd_bind_clip; break; + case 0x018c: func = nv04_gr_mthd_bind_patt; break; + case 0x0190: func = nv04_gr_mthd_bind_rop; break; + case 0x0194: func = nv04_gr_mthd_bind_beta1; break; + case 0x0198: func = nv04_gr_mthd_bind_beta4; break; + case 0x019c: func = nv04_gr_mthd_bind_surf2d; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_iifc_omthds[] = { - { 0x0188, 0x0188, nv01_gr_mthd_bind_chroma }, - { 0x018c, 0x018c, nv01_gr_mthd_bind_clip }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_patt }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_rop }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_beta1 }, - { 0x019c, 0x019c, nv04_gr_mthd_bind_beta4 }, - { 0x01a0, 0x01a0, nv04_gr_mthd_bind_surf2d_swzsurf }, - { 0x03e4, 0x03e4, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_iifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0188: func = nv01_gr_mthd_bind_chroma; break; + case 0x018c: func = nv01_gr_mthd_bind_clip; break; + case 0x0190: func = nv04_gr_mthd_bind_patt; break; + case 0x0194: func = nv04_gr_mthd_bind_rop; break; + case 0x0198: func = nv04_gr_mthd_bind_beta1; break; + case 0x019c: func = nv04_gr_mthd_bind_beta4; break; + case 0x01a0: func = nv04_gr_mthd_bind_surf2d_swzsurf; break; + case 0x03e4: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv01_gr_ifc_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, - { 0x018c, 0x018c, nv01_gr_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv01_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_chroma; break; + case 0x0188: func = nv01_gr_mthd_bind_clip; break; + case 0x018c: func = nv01_gr_mthd_bind_patt; break; + case 0x0190: func = nv04_gr_mthd_bind_rop; break; + case 0x0194: func = nv04_gr_mthd_bind_beta1; break; + case 0x0198: func = nv04_gr_mthd_bind_surf_dst; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_ifc_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_patt }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_rop }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta1 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_beta4 }, - { 0x019c, 0x019c, nv04_gr_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_ifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_chroma; break; + case 0x0188: func = nv01_gr_mthd_bind_clip; break; + case 0x018c: func = nv04_gr_mthd_bind_patt; break; + case 0x0190: func = nv04_gr_mthd_bind_rop; break; + case 0x0194: func = nv04_gr_mthd_bind_beta1; break; + case 0x0198: func = nv04_gr_mthd_bind_beta4; break; + case 0x019c: func = nv04_gr_mthd_bind_surf2d; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv03_gr_sifc_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, - { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv03_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_chroma; break; + case 0x0188: func = nv01_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_sifc_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_chroma }, - { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_sifc(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_chroma; break; + case 0x0188: func = nv04_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_beta4; break; + case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv03_gr_sifm_omthds[] = { - { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, - { 0x0304, 0x0304, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv03_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0188: func = nv01_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break; + case 0x0304: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_sifm_omthds[] = { - { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, - { 0x0304, 0x0304, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_sifm(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0188: func = nv04_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_beta4; break; + case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; + case 0x0304: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_surf3d_omthds[] = { - { 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h }, - { 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v }, - {} -}; +static bool +nv04_gr_mthd_surf3d(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x02f8: func = nv04_gr_mthd_surf3d_clip_h; break; + case 0x02fc: func = nv04_gr_mthd_surf3d_clip_v; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv03_gr_ttri_omthds[] = { - { 0x0188, 0x0188, nv01_gr_mthd_bind_clip }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_surf_zeta }, - {} -}; +static bool +nv03_gr_mthd_ttri(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0188: func = nv01_gr_mthd_bind_clip; break; + case 0x018c: func = nv04_gr_mthd_bind_surf_color; break; + case 0x0190: func = nv04_gr_mthd_bind_surf_zeta; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv01_gr_prim_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_clip }, - { 0x0188, 0x0188, nv01_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_surf_dst }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv01_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_clip; break; + case 0x0188: func = nv01_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_surf_dst; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} -static struct nvkm_omthds -nv04_gr_prim_omthds[] = { - { 0x0184, 0x0184, nv01_gr_mthd_bind_clip }, - { 0x0188, 0x0188, nv04_gr_mthd_bind_patt }, - { 0x018c, 0x018c, nv04_gr_mthd_bind_rop }, - { 0x0190, 0x0190, nv04_gr_mthd_bind_beta1 }, - { 0x0194, 0x0194, nv04_gr_mthd_bind_beta4 }, - { 0x0198, 0x0198, nv04_gr_mthd_bind_surf2d }, - { 0x02fc, 0x02fc, nv04_gr_mthd_set_operation }, - {} -}; +static bool +nv04_gr_mthd_prim(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32); + switch (mthd) { + case 0x0184: func = nv01_gr_mthd_bind_clip; break; + case 0x0188: func = nv04_gr_mthd_bind_patt; break; + case 0x018c: func = nv04_gr_mthd_bind_rop; break; + case 0x0190: func = nv04_gr_mthd_bind_beta1; break; + case 0x0194: func = nv04_gr_mthd_bind_beta4; break; + case 0x0198: func = nv04_gr_mthd_bind_surf2d; break; + case 0x02fc: func = nv04_gr_mthd_set_operation; break; + default: + return false; + } + return func(device, inst, data); +} + +static bool +nv04_gr_mthd(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) +{ + bool (*func)(struct nvkm_device *, u32, u32, u32); + switch (nvkm_rd32(device, 0x700000 + inst) & 0x000000ff) { + case 0x1c ... 0x1e: + func = nv01_gr_mthd_prim; break; + case 0x1f: func = nv01_gr_mthd_blit; break; + case 0x21: func = nv01_gr_mthd_ifc; break; + case 0x36: func = nv03_gr_mthd_sifc; break; + case 0x37: func = nv03_gr_mthd_sifm; break; + case 0x48: func = nv03_gr_mthd_ttri; break; + case 0x4a: func = nv04_gr_mthd_gdi; break; + case 0x4b: func = nv03_gr_mthd_gdi; break; + case 0x53: func = nv04_gr_mthd_surf3d; break; + case 0x5c ... 0x5e: + func = nv04_gr_mthd_prim; break; + case 0x5f: func = nv04_gr_mthd_blit; break; + case 0x60: func = nv04_gr_mthd_iifc; break; + case 0x61: func = nv04_gr_mthd_ifc; break; + case 0x76: func = nv04_gr_mthd_sifc; break; + case 0x77: func = nv04_gr_mthd_sifm; break; + default: + return false; + } + return func(device, inst, mthd, data); +} static int nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, @@ -998,24 +1081,24 @@ nv04_gr_sclass[] = { { 0x0017, &nv04_gr_ofuncs }, /* chroma */ { 0x0018, &nv04_gr_ofuncs }, /* pattern (nv01) */ { 0x0019, &nv04_gr_ofuncs }, /* clip */ - { 0x001c, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* line */ - { 0x001d, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* tri */ - { 0x001e, &nv04_gr_ofuncs, nv01_gr_prim_omthds }, /* rect */ - { 0x001f, &nv04_gr_ofuncs, nv01_gr_blit_omthds }, - { 0x0021, &nv04_gr_ofuncs, nv01_gr_ifc_omthds }, + { 0x001c, &nv04_gr_ofuncs }, /* line */ + { 0x001d, &nv04_gr_ofuncs }, /* tri */ + { 0x001e, &nv04_gr_ofuncs }, /* rect */ + { 0x001f, &nv04_gr_ofuncs }, + { 0x0021, &nv04_gr_ofuncs }, { 0x0030, &nv04_gr_ofuncs }, /* null */ - { 0x0036, &nv04_gr_ofuncs, nv03_gr_sifc_omthds }, - { 0x0037, &nv04_gr_ofuncs, nv03_gr_sifm_omthds }, + { 0x0036, &nv04_gr_ofuncs }, + { 0x0037, &nv04_gr_ofuncs }, { 0x0038, &nv04_gr_ofuncs }, /* dvd subpicture */ { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ { 0x0042, &nv04_gr_ofuncs }, /* surf2d */ { 0x0043, &nv04_gr_ofuncs }, /* rop */ { 0x0044, &nv04_gr_ofuncs }, /* pattern */ - { 0x0048, &nv04_gr_ofuncs, nv03_gr_ttri_omthds }, - { 0x004a, &nv04_gr_ofuncs, nv04_gr_gdi_omthds }, - { 0x004b, &nv04_gr_ofuncs, nv03_gr_gdi_omthds }, + { 0x0048, &nv04_gr_ofuncs }, + { 0x004a, &nv04_gr_ofuncs }, + { 0x004b, &nv04_gr_ofuncs }, { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ - { 0x0053, &nv04_gr_ofuncs, nv04_gr_surf3d_omthds }, + { 0x0053, &nv04_gr_ofuncs }, { 0x0054, &nv04_gr_ofuncs }, /* ttri */ { 0x0055, &nv04_gr_ofuncs }, /* mtri */ { 0x0057, &nv04_gr_ofuncs }, /* chroma */ @@ -1023,18 +1106,18 @@ nv04_gr_sclass[] = { { 0x0059, &nv04_gr_ofuncs }, /* surf_src */ { 0x005a, &nv04_gr_ofuncs }, /* surf_color */ { 0x005b, &nv04_gr_ofuncs }, /* surf_zeta */ - { 0x005c, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* line */ - { 0x005d, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* tri */ - { 0x005e, &nv04_gr_ofuncs, nv04_gr_prim_omthds }, /* rect */ - { 0x005f, &nv04_gr_ofuncs, nv04_gr_blit_omthds }, - { 0x0060, &nv04_gr_ofuncs, nv04_gr_iifc_omthds }, - { 0x0061, &nv04_gr_ofuncs, nv04_gr_ifc_omthds }, + { 0x005c, &nv04_gr_ofuncs }, /* line */ + { 0x005d, &nv04_gr_ofuncs }, /* tri */ + { 0x005e, &nv04_gr_ofuncs }, /* rect */ + { 0x005f, &nv04_gr_ofuncs }, + { 0x0060, &nv04_gr_ofuncs }, + { 0x0061, &nv04_gr_ofuncs }, { 0x0064, &nv04_gr_ofuncs }, /* iifc (nv05) */ { 0x0065, &nv04_gr_ofuncs }, /* ifc (nv05) */ { 0x0066, &nv04_gr_ofuncs }, /* sifc (nv05) */ { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ - { 0x0076, &nv04_gr_ofuncs, nv04_gr_sifc_omthds }, - { 0x0077, &nv04_gr_ofuncs, nv04_gr_sifm_omthds }, + { 0x0076, &nv04_gr_ofuncs }, + { 0x0077, &nv04_gr_ofuncs }, {}, }; @@ -1092,10 +1175,8 @@ nv04_gr_context_switch(struct nv04_gr *gr) struct nvkm_device *device = gr->base.engine.subdev.device; struct nv04_gr_chan *prev = NULL; struct nv04_gr_chan *next = NULL; - unsigned long flags; int chid; - spin_lock_irqsave(&gr->lock, flags); nv04_gr_idle(gr); /* If previous context is valid, we need to save it */ @@ -1108,8 +1189,6 @@ nv04_gr_context_switch(struct nv04_gr *gr) next = gr->chan[chid]; if (next) nv04_gr_load_context(next, chid); - - spin_unlock_irqrestore(&gr->lock, flags); } static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) @@ -1272,8 +1351,6 @@ nv04_gr_intr(struct nvkm_subdev *subdev) { struct nv04_gr *gr = (void *)subdev; struct nv04_gr_chan *chan = NULL; - struct nvkm_namedb *namedb = NULL; - struct nvkm_handle *handle = NULL; struct nvkm_device *device = gr->base.engine.subdev.device; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); @@ -1291,14 +1368,10 @@ nv04_gr_intr(struct nvkm_subdev *subdev) spin_lock_irqsave(&gr->lock, flags); chan = gr->chan[chid]; - if (chan) - namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); - spin_unlock_irqrestore(&gr->lock, flags); if (stat & NV_PGRAPH_INTR_NOTIFY) { if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { - handle = nvkm_namedb_get_vinst(namedb, inst); - if (handle && !nv_call(handle->object, mthd, data)) + if (!nv04_gr_mthd(device, inst, mthd, data)) show &= ~NV_PGRAPH_INTR_NOTIFY; } } @@ -1324,7 +1397,7 @@ nv04_gr_intr(struct nvkm_subdev *subdev) nvkm_client_name(chan), subc, class, mthd, data); } - nvkm_namedb_put(handle); + spin_unlock_irqrestore(&gr->lock, flags); } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index be92015d8f9e..8f0c62d56d9d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -25,7 +25,6 @@ #include "regs.h" #include -#include #include #include @@ -473,40 +472,37 @@ nv15_gr_sclass[] = { {}, }; -static int -nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static void +nv17_gr_mthd_lma_window(struct nv10_gr_chan *chan, u32 mthd, u32 data) { - struct nv10_gr_chan *chan = (void *)object->parent; - struct nv10_gr *gr = nv10_gr(chan); + struct nvkm_device *device = chan->base.engine->subdev.device; + struct nvkm_gr *gr = nvkm_gr(chan); struct pipe_state *pipe = &chan->pipe_state; - struct nvkm_device *device = gr->base.engine.subdev.device; u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; u32 xfmode0, xfmode1; - u32 data = *(u32 *)args; int i; chan->lma_window[(mthd - 0x1638) / 4] = data; if (mthd != 0x1644) - return 0; + return; nv04_gr_idle(gr); - PIPE_SAVE(gr, pipe_0x0040, 0x0040); - PIPE_SAVE(gr, pipe->pipe_0x0200, 0x0200); + PIPE_SAVE(device, pipe_0x0040, 0x0040); + PIPE_SAVE(device, pipe->pipe_0x0200, 0x0200); - PIPE_RESTORE(gr, chan->lma_window, 0x6790); + PIPE_RESTORE(device, chan->lma_window, 0x6790); nv04_gr_idle(gr); xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); - PIPE_SAVE(gr, pipe->pipe_0x4400, 0x4400); - PIPE_SAVE(gr, pipe_0x64c0, 0x64c0); - PIPE_SAVE(gr, pipe_0x6ab0, 0x6ab0); - PIPE_SAVE(gr, pipe_0x6a80, 0x6a80); + PIPE_SAVE(device, pipe->pipe_0x4400, 0x4400); + PIPE_SAVE(device, pipe_0x64c0, 0x64c0); + PIPE_SAVE(device, pipe_0x6ab0, 0x6ab0); + PIPE_SAVE(device, pipe_0x6a80, 0x6a80); nv04_gr_idle(gr); @@ -529,52 +525,64 @@ nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd, nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000008); - PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); + PIPE_RESTORE(device, pipe->pipe_0x0200, 0x0200); nv04_gr_idle(gr); - PIPE_RESTORE(gr, pipe_0x0040, 0x0040); + PIPE_RESTORE(device, pipe_0x0040, 0x0040); nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0); nvkm_wr32(device, NV10_PGRAPH_XFMODE1, xfmode1); - PIPE_RESTORE(gr, pipe_0x64c0, 0x64c0); - PIPE_RESTORE(gr, pipe_0x6ab0, 0x6ab0); - PIPE_RESTORE(gr, pipe_0x6a80, 0x6a80); - PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); + PIPE_RESTORE(device, pipe_0x64c0, 0x64c0); + PIPE_RESTORE(device, pipe_0x6ab0, 0x6ab0); + PIPE_RESTORE(device, pipe_0x6a80, 0x6a80); + PIPE_RESTORE(device, pipe->pipe_0x4400, 0x4400); nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); nv04_gr_idle(gr); - - return 0; } -static int -nv17_gr_mthd_lma_enable(struct nvkm_object *object, u32 mthd, - void *args, u32 size) +static void +nv17_gr_mthd_lma_enable(struct nv10_gr_chan *chan, u32 mthd, u32 data) { - struct nv10_gr_chan *chan = (void *)object->parent; - struct nv10_gr *gr = nv10_gr(chan); - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_device *device = chan->base.engine->subdev.device; + struct nvkm_gr *gr = nvkm_gr(chan); nv04_gr_idle(gr); nvkm_mask(device, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); nvkm_mask(device, 0x4006b0, 0x08000000, 0x08000000); - return 0; } -static struct nvkm_omthds -nv17_celcius_omthds[] = { - { 0x1638, 0x1638, nv17_gr_mthd_lma_window }, - { 0x163c, 0x163c, nv17_gr_mthd_lma_window }, - { 0x1640, 0x1640, nv17_gr_mthd_lma_window }, - { 0x1644, 0x1644, nv17_gr_mthd_lma_window }, - { 0x1658, 0x1658, nv17_gr_mthd_lma_enable }, - {} -}; +static bool +nv17_gr_mthd_celcius(struct nv10_gr_chan *chan, u32 mthd, u32 data) +{ + void (*func)(struct nv10_gr_chan *, u32, u32); + switch (mthd) { + case 0x1638 ... 0x1644: + func = nv17_gr_mthd_lma_window; break; + case 0x1658: func = nv17_gr_mthd_lma_enable; break; + default: + return false; + } + func(chan, mthd, data); + return true; +} + +static bool +nv10_gr_mthd(struct nv10_gr_chan *chan, u8 class, u32 mthd, u32 data) +{ + bool (*func)(struct nv10_gr_chan *, u32, u32); + switch (class) { + case 0x99: func = nv17_gr_mthd_celcius; break; + default: + return false; + } + return func(chan, mthd, data); +} static struct nvkm_oclass nv17_gr_sclass[] = { @@ -595,7 +603,7 @@ nv17_gr_sclass[] = { { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ { 0x0094, &nv04_gr_ofuncs }, /* ttri */ { 0x0095, &nv04_gr_ofuncs }, /* mtri */ - { 0x0099, &nv04_gr_ofuncs, nv17_celcius_omthds }, + { 0x0099, &nv04_gr_ofuncs }, {}, }; @@ -996,10 +1004,8 @@ nv10_gr_context_switch(struct nv10_gr *gr) struct nvkm_device *device = gr->base.engine.subdev.device; struct nv10_gr_chan *prev = NULL; struct nv10_gr_chan *next = NULL; - unsigned long flags; int chid; - spin_lock_irqsave(&gr->lock, flags); nv04_gr_idle(gr); /* If previous context is valid, we need to save it */ @@ -1012,8 +1018,6 @@ nv10_gr_context_switch(struct nv10_gr *gr) next = gr->chan[chid]; if (next) nv10_gr_load_context(next, chid); - - spin_unlock_irqrestore(&gr->lock, flags); } #define NV_WRITE_CTX(reg, val) do { \ @@ -1167,8 +1171,6 @@ nv10_gr_intr(struct nvkm_subdev *subdev) { struct nv10_gr *gr = (void *)subdev; struct nv10_gr_chan *chan = NULL; - struct nvkm_namedb *namedb = NULL; - struct nvkm_handle *handle = NULL; struct nvkm_device *device = gr->base.engine.subdev.device; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); @@ -1185,14 +1187,10 @@ nv10_gr_intr(struct nvkm_subdev *subdev) spin_lock_irqsave(&gr->lock, flags); chan = gr->chan[chid]; - if (chan) - namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); - spin_unlock_irqrestore(&gr->lock, flags); if (stat & NV_PGRAPH_INTR_ERROR) { if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { - handle = nvkm_namedb_get_class(namedb, class); - if (handle && !nv_call(handle->object, mthd, data)) + if (!nv10_gr_mthd(chan, class, mthd, data)) show &= ~NV_PGRAPH_INTR_ERROR; } } @@ -1218,7 +1216,7 @@ nv10_gr_intr(struct nvkm_subdev *subdev) nvkm_client_name(chan), subc, class, mthd, data); } - nvkm_namedb_put(handle); + spin_unlock_irqrestore(&gr->lock, flags); } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 6e5b321128a6..a33ed6121d7f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -2,7 +2,6 @@ #include "regs.h" #include -#include #include #include #include @@ -145,6 +144,7 @@ nv20_gr_context_fini(struct nvkm_object *object, bool suspend) nvkm_kmap(gr->ctxtab); nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); nvkm_done(gr->ctxtab); + return nvkm_gr_context_fini(&chan->base, suspend); } @@ -200,11 +200,9 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) void nv20_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_engine *engine = nv_engine(subdev); - struct nvkm_object *engctx; - struct nvkm_handle *handle; struct nv20_gr *gr = (void *)subdev; struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo_chan *chan; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); @@ -216,16 +214,9 @@ nv20_gr_intr(struct nvkm_subdev *subdev) u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; u32 show = stat; char msg[128], src[128], sta[128]; + unsigned long flags; - engctx = nvkm_engctx_get(engine, chid); - if (stat & NV_PGRAPH_INTR_ERROR) { - if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - handle = nvkm_handle_get_class(engctx, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~NV_PGRAPH_INTR_ERROR; - nvkm_handle_put(handle); - } - } + chan = nvkm_fifo_chan_chid(device->fifo, chid, &flags); nvkm_wr32(device, NV03_PGRAPH_INTR, stat); nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001); @@ -238,10 +229,10 @@ nv20_gr_intr(struct nvkm_subdev *subdev) "nstatus %08x [%s] ch %d [%s] subc %d " "class %04x mthd %04x data %08x\n", show, msg, nsource, src, nstatus, sta, chid, - nvkm_client_name(engctx), subc, class, mthd, data); + nvkm_client_name(chan), subc, class, mthd, data); } - nvkm_engctx_put(engctx); + nvkm_fifo_chan_put(device->fifo, flags, &chan); } static int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 1ebf2edef4d4..4db2a17f5308 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -25,7 +25,6 @@ #include "regs.h" #include -#include #include #include #include @@ -33,10 +32,14 @@ struct nv40_gr { struct nvkm_gr base; u32 size; + struct list_head chan; }; struct nv40_gr_chan { struct nvkm_gr_chan base; + struct nvkm_fifo_chan *fifo; + u32 inst; + struct list_head head; }; static u64 @@ -132,6 +135,16 @@ nv44_gr_sclass[] = { * PGRAPH context ******************************************************************************/ +static void +nv40_gr_context_dtor(struct nvkm_object *object) +{ + struct nv40_gr_chan *chan = (void *)object; + unsigned long flags; + spin_lock_irqsave(&object->engine->lock, flags); + list_del(&chan->head); + spin_unlock_irqrestore(&object->engine->lock, flags); +} + static int nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -139,6 +152,7 @@ nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, { struct nv40_gr *gr = (void *)engine; struct nv40_gr_chan *chan; + unsigned long flags; int ret; ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size, @@ -149,6 +163,12 @@ nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_grctx_fill(nv_device(gr), nv_gpuobj(chan)); nvkm_wo32(&chan->base.base.gpuobj, 0x00000, nv_gpuobj(chan)->addr >> 4); + + spin_lock_irqsave(&gr->base.engine.lock, flags); + chan->fifo = (void *)parent; + chan->inst = chan->base.base.gpuobj.addr; + list_add(&chan->head, &gr->chan); + spin_unlock_irqrestore(&gr->base.engine.lock, flags); return 0; } @@ -195,7 +215,7 @@ nv40_gr_cclass = { .handle = NV_ENGCTX(GR, 0x40), .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, + .dtor = nv40_gr_context_dtor, .init = _nvkm_gr_context_init, .fini = nv40_gr_context_fini, .rd32 = _nvkm_gr_context_rd32, @@ -289,11 +309,8 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) static void nv40_gr_intr(struct nvkm_subdev *subdev) { - struct nvkm_fifo *fifo = nvkm_fifo(subdev); - struct nvkm_engine *engine = nv_engine(subdev); - struct nvkm_object *engctx; - struct nvkm_handle *handle = NULL; struct nv40_gr *gr = (void *)subdev; + struct nv40_gr_chan *temp, *chan = NULL; struct nvkm_device *device = gr->base.engine.subdev.device; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); @@ -306,19 +323,19 @@ nv40_gr_intr(struct nvkm_subdev *subdev) u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff; u32 show = stat; char msg[128], src[128], sta[128]; - int chid; - - engctx = nvkm_engctx_get(engine, inst); - chid = fifo->chid(fifo, engctx); + unsigned long flags; - if (stat & NV_PGRAPH_INTR_ERROR) { - if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { - handle = nvkm_handle_get_class(engctx, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~NV_PGRAPH_INTR_ERROR; - nvkm_handle_put(handle); + spin_lock_irqsave(&gr->base.engine.lock, flags); + list_for_each_entry(temp, &gr->chan, head) { + if (temp->inst >> 4 == inst) { + chan = temp; + list_del(&chan->head); + list_add(&chan->head, &gr->chan); + break; } + } + if (stat & NV_PGRAPH_INTR_ERROR) { if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { nvkm_mask(device, 0x402000, 0, 0); } @@ -334,12 +351,12 @@ nv40_gr_intr(struct nvkm_subdev *subdev) nvkm_error(subdev, "intr %08x [%s] nsource %08x [%s] " "nstatus %08x [%s] ch %d [%08x %s] subc %d " "class %04x mthd %04x data %08x\n", - show, msg, nsource, src, nstatus, sta, chid, - inst << 4, nvkm_client_name(engctx), subc, - class, mthd, data); + show, msg, nsource, src, nstatus, sta, + chan ? chan->fifo->chid : -1, inst << 4, + nvkm_client_name(chan), subc, class, mthd, data); } - nvkm_engctx_put(engctx); + spin_unlock_irqrestore(&gr->base.engine.lock, flags); } static int @@ -355,6 +372,8 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + INIT_LIST_HEAD(&gr->chan); + nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv40_gr_intr; nv_engine(gr)->cclass = &nv40_gr_cclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index c50cfe4875ef..daac54075705 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -24,9 +24,8 @@ #include "nv50.h" #include -#include -#include #include +#include struct nv50_gr { struct nvkm_gr base; @@ -609,7 +608,7 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, static int nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, - int chid, u64 inst, struct nvkm_object *engctx) + int chid, u64 inst, struct nvkm_fifo_chan *chan) { struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; @@ -649,8 +648,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, "ch %d [%010llx %s] subc %d " "class %04x mthd %04x data %08x%08x " "400808 %08x 400848 %08x\n", - chid, inst, - nvkm_client_name(engctx), + chid, inst, nvkm_client_name(chan), subc, class, mthd, datah, datal, addr, r848); } else @@ -677,7 +675,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, "ch %d [%010llx %s] subc %d " "class %04x mthd %04x data %08x " "40084c %08x\n", chid, inst, - nvkm_client_name(engctx), subc, + nvkm_client_name(chan), subc, class, mthd, data, addr); } else if (display) { @@ -840,10 +838,7 @@ nv50_gr_intr(struct nvkm_subdev *subdev) { struct nv50_gr *gr = (void *)subdev; struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_fifo *fifo = device->fifo; - struct nvkm_engine *engine = nv_engine(subdev); - struct nvkm_object *engctx; - struct nvkm_handle *handle = NULL; + struct nvkm_fifo_chan *chan; u32 stat = nvkm_rd32(device, 0x400100); u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff; u32 addr = nvkm_rd32(device, 0x400704); @@ -853,18 +848,12 @@ nv50_gr_intr(struct nvkm_subdev *subdev) u32 class = nvkm_rd32(device, 0x400814); u32 show = stat, show_bitfield = stat; const struct nvkm_enum *en; + unsigned long flags; char msg[128]; int chid; - engctx = nvkm_engctx_get(engine, inst); - chid = fifo->chid(fifo, engctx); - - if (stat & 0x00000010) { - handle = nvkm_handle_get_class(engctx, class); - if (handle && !nv_call(handle->object, mthd, data)) - show &= ~0x00000010; - nvkm_handle_put(handle); - } + chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); + chid = chan ? chan->chid : -1; if (show & 0x00100000) { u32 ecode = nvkm_rd32(device, 0x400110); @@ -875,8 +864,7 @@ nv50_gr_intr(struct nvkm_subdev *subdev) } if (stat & 0x00200000) { - if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, - engctx)) + if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, chan)) show &= ~0x00200000; show_bitfield &= ~0x00200000; } @@ -890,13 +878,13 @@ nv50_gr_intr(struct nvkm_subdev *subdev) nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] subc %d " "class %04x mthd %04x data %08x\n", stat, msg, chid, (u64)inst << 12, - nvkm_client_name(engctx), subc, class, mthd, data); + nvkm_client_name(chan), subc, class, mthd, data); } if (nvkm_rd32(device, 0x400824) & (1 << 31)) nvkm_wr32(device, 0x400824, nvkm_rd32(device, 0x400824) & ~(1 << 31)); - nvkm_engctx_put(engctx); + nvkm_fifo_chan_put(device->fifo, flags, &chan); } static int -- cgit v1.2.3 From 9a65a38c456ebac97f0498e85fe26f6d26fe3936 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:19 +1000 Subject: drm/nouveau/fifo: split user classes out from engine implementations Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 24 -- drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 17 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 194 ++------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 162 +++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h | 28 ++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c | 231 ++++++++++ .../gpu/drm/nouveau/nvkm/engine/fifo/changf100.h | 23 + .../gpu/drm/nouveau/nvkm/engine/fifo/changk104.h | 27 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/channv04.h | 24 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/channv50.c | 259 +++++++++++ .../gpu/drm/nouveau/nvkm/engine/fifo/channv50.h | 42 ++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c | 127 ++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c | 282 ++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c | 102 +++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c | 104 +++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c | 225 ++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c | 115 +++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c | 424 +----------------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 473 ++++---------------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h | 26 ++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 403 +---------------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 39 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c | 9 +- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c | 122 ++++++ .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c | 304 +++++++++++++ .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 357 ++++++++++++++++ .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c | 32 ++ .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c | 110 +++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 329 ++------------ drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h | 146 +------ drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 92 +--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 138 ++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 258 ++--------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 475 ++------------------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h | 30 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 8 + .../gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h | 132 ++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 1 + 45 files changed, 3147 insertions(+), 2754 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index d70fe7f9a44d..ac97072dcfef 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -18,30 +18,6 @@ nvkm_fifo_chan(void *obj) return (void *)nv_namedb(obj); } -#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ - nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ - (m), sizeof(**d), (void **)d) -#define nvkm_fifo_channel_init(p) \ - nvkm_namedb_init(&(p)->namedb) -#define nvkm_fifo_channel_fini(p,s) \ - nvkm_namedb_fini(&(p)->namedb, (s)) - -int nvkm_fifo_channel_create_(struct nvkm_object *, - struct nvkm_object *, - struct nvkm_oclass *, - int bar, u32 addr, u32 size, u64 push, - u64 engmask, int len, void **); -void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *); - -#define _nvkm_fifo_channel_init _nvkm_namedb_init -#define _nvkm_fifo_channel_fini _nvkm_namedb_fini - -void _nvkm_fifo_channel_dtor(struct nvkm_object *); -int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *); -u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64); -void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32); -int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **); - #include struct nvkm_fifo_base { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild index dc81a8b64f35..4525b01598a9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -11,3 +11,20 @@ nvkm-y += nvkm/engine/fifo/gk20a.o nvkm-y += nvkm/engine/fifo/gk208.o nvkm-y += nvkm/engine/fifo/gm204.o nvkm-y += nvkm/engine/fifo/gm20b.o + +nvkm-y += nvkm/engine/fifo/chan.o +nvkm-y += nvkm/engine/fifo/channv50.o +nvkm-y += nvkm/engine/fifo/chang84.o + +nvkm-y += nvkm/engine/fifo/dmanv04.o +nvkm-y += nvkm/engine/fifo/dmanv10.o +nvkm-y += nvkm/engine/fifo/dmanv17.o +nvkm-y += nvkm/engine/fifo/dmanv40.o +nvkm-y += nvkm/engine/fifo/dmanv50.o +nvkm-y += nvkm/engine/fifo/dmag84.o + +nvkm-y += nvkm/engine/fifo/gpfifonv50.o +nvkm-y += nvkm/engine/fifo/gpfifog84.o +nvkm-y += nvkm/engine/fifo/gpfifogf100.o +nvkm-y += nvkm/engine/fifo/gpfifogk104.o +nvkm-y += nvkm/engine/fifo/gpfifogm204.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 958f290d088e..510de3c2d2e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ -#include +#include "priv.h" +#include "chan.h" #include -#include #include -#include -#include #include #include @@ -74,138 +72,51 @@ nvkm_fifo_chan_chid(struct nvkm_fifo *fifo, int chid, unsigned long *rflags) } static int -nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, - struct nvkm_notify *notify) -{ - if (size == 0) { - notify->size = 0; - notify->types = 1; - notify->index = 0; - return 0; - } - return -ENOSYS; -} - -static const struct nvkm_event_func -nvkm_fifo_event_func = { - .ctor = nvkm_fifo_event_ctor, -}; - -int -nvkm_fifo_channel_create_(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, - int bar, u32 addr, u32 size, u64 pushbuf, - u64 engmask, int len, void **ptr) +nvkm_fifo_chid(struct nvkm_fifo *fifo, struct nvkm_object *object) { - struct nvkm_client *client = nvkm_client(parent); - struct nvkm_dmaobj *dmaobj; - struct nvkm_fifo *fifo = (void *)engine; - struct nvkm_fifo_base *base = (void *)parent; - struct nvkm_fifo_chan *chan; - struct nvkm_subdev *subdev = &fifo->engine.subdev; - struct nvkm_device *device = subdev->device; - struct nvkm_dma *dma = device->dma; - unsigned long flags; - int ret; - - /* create base object class */ - ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, - engmask, len, ptr); - chan = *ptr; - if (ret) - return ret; - - /* validate dma object representing push buffer */ - if (pushbuf) { - dmaobj = nvkm_dma_search(dma, client, pushbuf); - if (!dmaobj) - return -ENOENT; - - ret = dmaobj->func->bind(dmaobj, &base->gpuobj, 16, - &chan->pushgpu); - if (ret) - return ret; - } - - /* find a free fifo channel */ - spin_lock_irqsave(&fifo->lock, flags); - for (chan->chid = fifo->min; chan->chid < fifo->max; chan->chid++) { - if (!fifo->channel[chan->chid]) { - fifo->channel[chan->chid] = nv_object(chan); - break; - } - } - spin_unlock_irqrestore(&fifo->lock, flags); + int engidx = nv_hclass(fifo) & 0xff; - if (chan->chid == fifo->max) { - nvkm_error(subdev, "no free channels\n"); - return -ENOSPC; + while (object && object->parent) { + if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && + (nv_hclass(object->parent) & 0xff) == engidx) + return nvkm_fifo_chan(object)->chid; + object = object->parent; } - chan->addr = nv_device_resource_start(device, bar) + - addr + size * chan->chid; - chan->size = size; - nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0); - return 0; + return -1; } -void -nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan) +const char * +nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) { - struct nvkm_fifo *fifo = (void *)nv_object(chan)->engine; + struct nvkm_fifo_chan *chan = NULL; unsigned long flags; - if (chan->user) - iounmap(chan->user); - spin_lock_irqsave(&fifo->lock, flags); - fifo->channel[chan->chid] = NULL; + if (chid >= fifo->min && chid <= fifo->max) + chan = (void *)fifo->channel[chid]; spin_unlock_irqrestore(&fifo->lock, flags); - nvkm_gpuobj_del(&chan->pushgpu); - nvkm_namedb_destroy(&chan->namedb); -} - -void -_nvkm_fifo_channel_dtor(struct nvkm_object *object) -{ - struct nvkm_fifo_chan *chan = (void *)object; - nvkm_fifo_channel_destroy(chan); -} - -int -_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size) -{ - struct nvkm_fifo_chan *chan = (void *)object; - *addr = chan->addr; - *size = chan->size; - return 0; + return nvkm_client_name(chan); } -u32 -_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr) +static int +nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, + struct nvkm_notify *notify) { - struct nvkm_fifo_chan *chan = (void *)object; - if (unlikely(!chan->user)) { - chan->user = ioremap(chan->addr, chan->size); - if (WARN_ON_ONCE(chan->user == NULL)) - return 0; + if (size == 0) { + notify->size = 0; + notify->types = 1; + notify->index = 0; + return 0; } - return ioread32_native(chan->user + addr); + return -ENOSYS; } -void -_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data) -{ - struct nvkm_fifo_chan *chan = (void *)object; - if (unlikely(!chan->user)) { - chan->user = ioremap(chan->addr, chan->size); - if (WARN_ON_ONCE(chan->user == NULL)) - return; - } - iowrite32_native(data, chan->user + addr); -} +static const struct nvkm_event_func +nvkm_fifo_event_func = { + .ctor = nvkm_fifo_event_ctor, +}; int nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, @@ -233,53 +144,6 @@ nvkm_fifo_uevent(struct nvkm_fifo *fifo) nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep)); } -int -_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type, - struct nvkm_event **event) -{ - struct nvkm_fifo *fifo = (void *)object->engine; - switch (type) { - case G82_CHANNEL_DMA_V0_NTFY_UEVENT: - if (nv_mclass(object) >= G82_CHANNEL_DMA) { - *event = &fifo->uevent; - return 0; - } - break; - default: - break; - } - return -EINVAL; -} - -static int -nvkm_fifo_chid(struct nvkm_fifo *fifo, struct nvkm_object *object) -{ - int engidx = nv_hclass(fifo) & 0xff; - - while (object && object->parent) { - if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && - (nv_hclass(object->parent) & 0xff) == engidx) - return nvkm_fifo_chan(object)->chid; - object = object->parent; - } - - return -1; -} - -const char * -nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) -{ - struct nvkm_fifo_chan *chan = NULL; - unsigned long flags; - - spin_lock_irqsave(&fifo->lock, flags); - if (chid >= fifo->min && chid <= fifo->max) - chan = (void *)fifo->channel[chid]; - spin_unlock_irqrestore(&fifo->lock, flags); - - return nvkm_client_name(chan); -} - void nvkm_fifo_destroy(struct nvkm_fifo *fifo) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c new file mode 100644 index 000000000000..cc401ae1d6a5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -0,0 +1,162 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "chan.h" + +#include +#include + +#include + +int +_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type, + struct nvkm_event **event) +{ + struct nvkm_fifo *fifo = (void *)object->engine; + switch (type) { + case G82_CHANNEL_DMA_V0_NTFY_UEVENT: + if (nv_mclass(object) >= G82_CHANNEL_DMA) { + *event = &fifo->uevent; + return 0; + } + break; + default: + break; + } + return -EINVAL; +} + +int +_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size) +{ + struct nvkm_fifo_chan *chan = (void *)object; + *addr = chan->addr; + *size = chan->size; + return 0; +} + +u32 +_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr) +{ + struct nvkm_fifo_chan *chan = (void *)object; + if (unlikely(!chan->user)) { + chan->user = ioremap(chan->addr, chan->size); + if (WARN_ON_ONCE(chan->user == NULL)) + return 0; + } + return ioread32_native(chan->user + addr); +} + +void +_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data) +{ + struct nvkm_fifo_chan *chan = (void *)object; + if (unlikely(!chan->user)) { + chan->user = ioremap(chan->addr, chan->size); + if (WARN_ON_ONCE(chan->user == NULL)) + return; + } + iowrite32_native(data, chan->user + addr); +} + +void +nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan) +{ + struct nvkm_fifo *fifo = (void *)nv_object(chan)->engine; + unsigned long flags; + + if (chan->user) + iounmap(chan->user); + + spin_lock_irqsave(&fifo->lock, flags); + fifo->channel[chan->chid] = NULL; + spin_unlock_irqrestore(&fifo->lock, flags); + + nvkm_gpuobj_del(&chan->pushgpu); + nvkm_namedb_destroy(&chan->namedb); +} + +void +_nvkm_fifo_channel_dtor(struct nvkm_object *object) +{ + struct nvkm_fifo_chan *chan = (void *)object; + nvkm_fifo_channel_destroy(chan); +} + +int +nvkm_fifo_channel_create_(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, + int bar, u32 addr, u32 size, u64 pushbuf, + u64 engmask, int len, void **ptr) +{ + struct nvkm_client *client = nvkm_client(parent); + struct nvkm_fifo *fifo = (void *)engine; + struct nvkm_fifo_base *base = (void *)parent; + struct nvkm_fifo_chan *chan; + struct nvkm_subdev *subdev = &fifo->engine.subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_dmaobj *dmaobj; + unsigned long flags; + int ret; + + /* create base object class */ + ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, + engmask, len, ptr); + chan = *ptr; + if (ret) + return ret; + + /* validate dma object representing push buffer */ + if (pushbuf) { + dmaobj = nvkm_dma_search(device->dma, client, pushbuf); + if (!dmaobj) + return -ENOENT; + + ret = nvkm_object_bind(&dmaobj->object, &base->gpuobj, 16, + &chan->pushgpu); + if (ret) + return ret; + } + + /* find a free fifo channel */ + spin_lock_irqsave(&fifo->lock, flags); + for (chan->chid = fifo->min; chan->chid < fifo->max; chan->chid++) { + if (!fifo->channel[chan->chid]) { + fifo->channel[chan->chid] = nv_object(chan); + break; + } + } + spin_unlock_irqrestore(&fifo->lock, flags); + + if (chan->chid == fifo->max) { + nvkm_error(subdev, "no free channels\n"); + return -ENOSPC; + } + + chan->addr = nv_device_resource_start(device, bar) + + addr + size * chan->chid; + chan->size = size; + nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h new file mode 100644 index 000000000000..63209bc8856b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_FIFO_CHAN_H__ +#define __NVKM_FIFO_CHAN_H__ +#include "priv.h" + +#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ + nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ + (m), sizeof(**d), (void **)d) +#define nvkm_fifo_channel_init(p) \ + nvkm_namedb_init(&(p)->namedb) +#define nvkm_fifo_channel_fini(p,s) \ + nvkm_namedb_fini(&(p)->namedb, (s)) + +int nvkm_fifo_channel_create_(struct nvkm_object *, + struct nvkm_object *, + struct nvkm_oclass *, + int bar, u32 addr, u32 size, u64 push, + u64 engmask, int len, void **); +void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *); + +#define _nvkm_fifo_channel_init _nvkm_namedb_init +#define _nvkm_fifo_channel_fini _nvkm_namedb_fini + +void _nvkm_fifo_channel_dtor(struct nvkm_object *); +int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *); +u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64); +void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32); +int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c new file mode 100644 index 000000000000..f2b4a96f8794 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -0,0 +1,231 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv50.h" + +#include +#include +#include + +int +g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) +{ + struct nv50_fifo *fifo = (void *)parent->engine; + struct nv50_fifo_base *base = (void *)parent->parent; + struct nv50_fifo_chan *chan = (void *)parent; + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 addr, save, engn; + bool done; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break; + case NVDEV_ENGINE_MSPPP : + case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; + case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; + default: + return -EINVAL; + } + + save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); + nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); + done = nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) + break; + ) >= 0; + nvkm_wr32(device, 0x002520, save); + if (!done) { + nvkm_error(subdev, "channel %d [%s] unload timeout\n", + chan->base.chid, nvkm_client_name(chan)); + if (suspend) + return -EBUSY; + } + + nvkm_kmap(base->eng); + nvkm_wo32(base->eng, addr + 0x00, 0x00000000); + nvkm_wo32(base->eng, addr + 0x04, 0x00000000); + nvkm_wo32(base->eng, addr + 0x08, 0x00000000); + nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); + nvkm_wo32(base->eng, addr + 0x10, 0x00000000); + nvkm_wo32(base->eng, addr + 0x14, 0x00000000); + nvkm_done(base->eng); + return 0; +} + + +int +g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) +{ + struct nv50_fifo_base *base = (void *)parent->parent; + struct nvkm_gpuobj *ectx = (void *)object; + u64 limit = ectx->addr + ectx->size - 1; + u64 start = ectx->addr; + u32 addr; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0020; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break; + case NVDEV_ENGINE_MSPPP : + case NVDEV_ENGINE_MPEG : addr = 0x0060; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : addr = 0x00a0; break; + case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; + default: + return -EINVAL; + } + + nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + nvkm_kmap(base->eng); + nvkm_wo32(base->eng, addr + 0x00, 0x00190000); + nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); + nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); + nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | + upper_32_bits(start)); + nvkm_wo32(base->eng, addr + 0x10, 0x00000000); + nvkm_wo32(base->eng, addr + 0x14, 0x00000000); + nvkm_done(base->eng); + return 0; +} + +int +g84_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) +{ + struct nv50_fifo_chan *chan = (void *)parent; + u32 context; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) + context = nv_gpuobj(object)->node->offset >> 4; + else + context = 0x00000004; /* just non-zero */ + + if (object->engine) { + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : context |= 0x00000000; break; + case NVDEV_ENGINE_GR : context |= 0x00100000; break; + case NVDEV_ENGINE_MPEG : + case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break; + case NVDEV_ENGINE_ME : + case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : + case NVDEV_ENGINE_VIC : context |= 0x00500000; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; + default: + return -EINVAL; + } + } + + return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); +} + +int +g84_fifo_chan_init(struct nvkm_object *object) +{ + struct nv50_fifo *fifo = (void *)object->engine; + struct nv50_fifo_base *base = (void *)object->parent; + struct nv50_fifo_chan *chan = (void *)object; + struct nvkm_gpuobj *ramfc = base->ramfc; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + int ret; + + ret = nvkm_fifo_channel_init(&chan->base); + if (ret) + return ret; + + nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); + nv50_fifo_runlist_update(fifo); + return 0; +} + +static int +g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_engine(engine)->subdev.device; + struct nv50_fifo_base *base; + int ret; + + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, + 0x1000, NVOBJ_FLAG_HEAP, &base); + *pobject = nv_object(base); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x0200, 0, true, &base->base.gpuobj, + &base->eng); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, + &base->pgd); + if (ret) + return ret; + + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, &base->base.gpuobj, + &base->cache); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, &base->base.gpuobj, + &base->ramfc); + if (ret) + return ret; + + return 0; +} + +struct nvkm_oclass +g84_fifo_cclass = { + .handle = NV_ENGCTX(FIFO, 0x84), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = g84_fifo_context_ctor, + .dtor = nv50_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h new file mode 100644 index 000000000000..99324222dade --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h @@ -0,0 +1,23 @@ +#ifndef __GF100_FIFO_CHAN_H__ +#define __GF100_FIFO_CHAN_H__ +#include "chan.h" +#include "gf100.h" + +struct gf100_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct gf100_fifo_chan { + struct nvkm_fifo_chan base; + enum { + STOPPED, + RUNNING, + KILLED + } state; +}; + +extern struct nvkm_oclass gf100_fifo_cclass; +extern struct nvkm_oclass gf100_fifo_sclass[]; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h new file mode 100644 index 000000000000..3490cb6d8bd3 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h @@ -0,0 +1,27 @@ +#ifndef __GK104_FIFO_CHAN_H__ +#define __GK104_FIFO_CHAN_H__ +#include "chan.h" +#include "gk104.h" + +struct gk104_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct gk104_fifo_chan { + struct nvkm_fifo_chan base; + u32 engine; + enum { + STOPPED, + RUNNING, + KILLED + } state; +}; + +extern struct nvkm_oclass gk104_fifo_cclass; +extern struct nvkm_oclass gk104_fifo_sclass[]; +extern struct nvkm_ofuncs gk104_fifo_chan_ofuncs; + +extern struct nvkm_oclass gm204_fifo_sclass[]; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h new file mode 100644 index 000000000000..028212df41bc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h @@ -0,0 +1,24 @@ +#ifndef __NV04_FIFO_CHAN_H__ +#define __NV04_FIFO_CHAN_H__ +#include "chan.h" +#include "nv04.h" + +struct nv04_fifo_chan { + struct nvkm_fifo_chan base; + u32 subc[8]; + u32 ramfc; +}; + +int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); +void nv04_fifo_object_detach(struct nvkm_object *, int); + +void nv04_fifo_chan_dtor(struct nvkm_object *); +int nv04_fifo_chan_init(struct nvkm_object *); +int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend); + +extern struct nvkm_oclass nv04_fifo_cclass; +extern struct nvkm_oclass nv04_fifo_sclass[]; +extern struct nvkm_oclass nv10_fifo_sclass[]; +extern struct nvkm_oclass nv17_fifo_sclass[]; +extern struct nvkm_oclass nv40_fifo_sclass[]; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c new file mode 100644 index 000000000000..aeaba7b9bcae --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c @@ -0,0 +1,259 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv50.h" + +#include +#include +#include + +int +nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) +{ + struct nv50_fifo *fifo = (void *)parent->engine; + struct nv50_fifo_base *base = (void *)parent->parent; + struct nv50_fifo_chan *chan = (void *)parent; + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 addr, me; + int ret = 0; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0000; break; + case NVDEV_ENGINE_MPEG : addr = 0x0060; break; + default: + return -EINVAL; + } + + /* HW bug workaround: + * + * PFIFO will hang forever if the connected engines don't report + * that they've processed the context switch request. + * + * In order for the kickoff to work, we need to ensure all the + * connected engines are in a state where they can answer. + * + * Newer chipsets don't seem to suffer from this issue, and well, + * there's also a "ignore these engines" bitmask reg we can use + * if we hit the issue there.. + */ + me = nvkm_mask(device, 0x00b860, 0x00000001, 0x00000001); + + /* do the kickoff... */ + nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) + break; + ) < 0) { + nvkm_error(subdev, "channel %d [%s] unload timeout\n", + chan->base.chid, nvkm_client_name(chan)); + if (suspend) + ret = -EBUSY; + } + nvkm_wr32(device, 0x00b860, me); + + if (ret == 0) { + nvkm_kmap(base->eng); + nvkm_wo32(base->eng, addr + 0x00, 0x00000000); + nvkm_wo32(base->eng, addr + 0x04, 0x00000000); + nvkm_wo32(base->eng, addr + 0x08, 0x00000000); + nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); + nvkm_wo32(base->eng, addr + 0x10, 0x00000000); + nvkm_wo32(base->eng, addr + 0x14, 0x00000000); + nvkm_done(base->eng); + } + + return ret; +} + +int +nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) +{ + struct nv50_fifo_base *base = (void *)parent->parent; + struct nvkm_gpuobj *ectx = (void *)object; + u64 limit = ectx->addr + ectx->size - 1; + u64 start = ectx->addr; + u32 addr; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0000; break; + case NVDEV_ENGINE_MPEG : addr = 0x0060; break; + default: + return -EINVAL; + } + + nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + + nvkm_kmap(base->eng); + nvkm_wo32(base->eng, addr + 0x00, 0x00190000); + nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); + nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); + nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | + upper_32_bits(start)); + nvkm_wo32(base->eng, addr + 0x10, 0x00000000); + nvkm_wo32(base->eng, addr + 0x14, 0x00000000); + nvkm_done(base->eng); + return 0; +} + +void +nv50_fifo_object_detach(struct nvkm_object *parent, int cookie) +{ + struct nv50_fifo_chan *chan = (void *)parent; + nvkm_ramht_remove(chan->ramht, cookie); +} + +int +nv50_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) +{ + struct nv50_fifo_chan *chan = (void *)parent; + u32 context; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) + context = nv_gpuobj(object)->node->offset >> 4; + else + context = 0x00000004; /* just non-zero */ + + if (object->engine) { + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : context |= 0x00000000; break; + case NVDEV_ENGINE_GR : context |= 0x00100000; break; + case NVDEV_ENGINE_MPEG : context |= 0x00200000; break; + default: + return -EINVAL; + } + } + + return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); +} + +int +nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct nv50_fifo *fifo = (void *)object->engine; + struct nv50_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + + /* remove channel from runlist, fifo will unload context */ + nvkm_mask(device, 0x002600 + (chid * 4), 0x80000000, 0x00000000); + nv50_fifo_runlist_update(fifo); + nvkm_wr32(device, 0x002600 + (chid * 4), 0x00000000); + + return nvkm_fifo_channel_fini(&chan->base, suspend); +} + +int +nv50_fifo_chan_init(struct nvkm_object *object) +{ + struct nv50_fifo *fifo = (void *)object->engine; + struct nv50_fifo_base *base = (void *)object->parent; + struct nv50_fifo_chan *chan = (void *)object; + struct nvkm_gpuobj *ramfc = base->ramfc; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + int ret; + + ret = nvkm_fifo_channel_init(&chan->base); + if (ret) + return ret; + + nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); + nv50_fifo_runlist_update(fifo); + return 0; +} + +void +nv50_fifo_chan_dtor(struct nvkm_object *object) +{ + struct nv50_fifo_chan *chan = (void *)object; + nvkm_ramht_del(&chan->ramht); + nvkm_fifo_channel_destroy(&chan->base); +} + +void +nv50_fifo_context_dtor(struct nvkm_object *object) +{ + struct nv50_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_del(&base->pgd); + nvkm_gpuobj_del(&base->eng); + nvkm_gpuobj_del(&base->ramfc); + nvkm_gpuobj_del(&base->cache); + nvkm_fifo_context_destroy(&base->base); +} + +static int +nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_engine(engine)->subdev.device; + struct nv50_fifo_base *base; + int ret; + + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, + 0x1000, NVOBJ_FLAG_HEAP, &base); + *pobject = nv_object(base); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, &base->base.gpuobj, + &base->ramfc); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x1200, 0, true, &base->base.gpuobj, + &base->eng); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, + &base->pgd); + if (ret) + return ret; + + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); + if (ret) + return ret; + + return 0; +} + +struct nvkm_oclass +nv50_fifo_cclass = { + .handle = NV_ENGCTX(FIFO, 0x50), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv50_fifo_context_ctor, + .dtor = nv50_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h new file mode 100644 index 000000000000..c4f2f1ff4c9e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h @@ -0,0 +1,42 @@ +#ifndef __NV50_FIFO_CHAN_H__ +#define __NV50_FIFO_CHAN_H__ +#include "chan.h" +#include "nv50.h" + +struct nv50_fifo_base { + struct nvkm_fifo_base base; + struct nvkm_gpuobj *ramfc; + struct nvkm_gpuobj *cache; + struct nvkm_gpuobj *eng; + struct nvkm_gpuobj *pgd; + struct nvkm_vm *vm; +}; + +struct nv50_fifo_chan { + struct nvkm_fifo_chan base; + u32 subc[8]; + struct nvkm_ramht *ramht; +}; + +extern struct nvkm_oclass nv50_fifo_cclass; +extern struct nvkm_oclass nv50_fifo_sclass[]; +void nv50_fifo_context_dtor(struct nvkm_object *); +void nv50_fifo_chan_dtor(struct nvkm_object *); +int nv50_fifo_chan_init(struct nvkm_object *); +int nv50_fifo_chan_fini(struct nvkm_object *, bool); +int nv50_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); +int nv50_fifo_context_detach(struct nvkm_object *, bool, + struct nvkm_object *); +int nv50_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); +void nv50_fifo_object_detach(struct nvkm_object *, int); +extern struct nvkm_ofuncs nv50_fifo_ofuncs_ind; + +extern struct nvkm_oclass g84_fifo_cclass; +extern struct nvkm_oclass g84_fifo_sclass[]; +int g84_fifo_chan_init(struct nvkm_object *); +int g84_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); +int g84_fifo_context_detach(struct nvkm_object *, bool, + struct nvkm_object *); +int g84_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); +extern struct nvkm_ofuncs g84_fifo_ofuncs_ind; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c new file mode 100644 index 000000000000..2016a9884b38 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c @@ -0,0 +1,127 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv50.h" + +#include +#include + +#include +#include + +static int +g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv50_channel_dma_v0 v0; + } *args = data; + struct nvkm_device *device = parent->engine->subdev.device; + struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo_chan *chan; + int ret; + + nvif_ioctl(parent, "create channel dma size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel dma vers %d vm %llx " + "pushbuf %llx offset %016llx\n", + args->v0.version, args->v0.vm, args->v0.pushbuf, + args->v0.offset); + if (args->v0.vm) + return -ENOENT; + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_VP) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_VIC), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->base.inst = base->base.gpuobj.addr; + args->v0.chid = chan->base.chid; + + ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, + &chan->ramht); + if (ret) + return ret; + + nv_parent(chan)->context_attach = g84_fifo_context_attach; + nv_parent(chan)->context_detach = g84_fifo_context_detach; + nv_parent(chan)->object_attach = g84_fifo_object_attach; + nv_parent(chan)->object_detach = nv50_fifo_object_detach; + + nvkm_kmap(base->ramfc); + nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); + nvkm_wo32(base->ramfc, 0x44, 0x01003fff); + nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); + nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); + nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(base->ramfc, 0x78, 0x00000000); + nvkm_wo32(base->ramfc, 0x7c, 0x30000001); + nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + (4 << 24) /* SEARCH_FULL */ | + (chan->ramht->gpuobj->node->offset >> 4)); + nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); + nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); + nvkm_done(base->ramfc); + return 0; +} + +static struct nvkm_ofuncs +g84_fifo_ofuncs_dma = { + .ctor = g84_fifo_chan_ctor_dma, + .dtor = nv50_fifo_chan_dtor, + .init = g84_fifo_chan_init, + .fini = nv50_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +g84_fifo_sclass[] = { + { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, + { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c new file mode 100644 index 000000000000..8cc87103a369 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -0,0 +1,282 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv04.h" +#include "regsnv04.h" + +#include +#include +#include + +#include +#include + +int +nv04_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) +{ + nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid; + return 0; +} + +void +nv04_fifo_object_detach(struct nvkm_object *parent, int cookie) +{ + struct nv04_fifo *fifo = (void *)parent->engine; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + mutex_lock(&nv_subdev(fifo)->mutex); + nvkm_ramht_remove(imem->ramht, cookie); + mutex_unlock(&nv_subdev(fifo)->mutex); +} + +int +nv04_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) +{ + struct nv04_fifo *fifo = (void *)parent->engine; + struct nv04_fifo_chan *chan = (void *)parent; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + u32 context, chid = chan->base.chid; + int ret; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) + context = nv_gpuobj(object)->addr >> 4; + else + context = 0x00000004; /* just non-zero */ + + if (object->engine) { + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW: + context |= 0x00000000; + break; + case NVDEV_ENGINE_GR: + context |= 0x00010000; + break; + case NVDEV_ENGINE_MPEG: + context |= 0x00020000; + break; + default: + return -EINVAL; + } + } + + context |= 0x80000000; /* valid */ + context |= chid << 24; + + mutex_lock(&nv_subdev(fifo)->mutex); + ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context); + mutex_unlock(&nv_subdev(fifo)->mutex); + return ret; +} + +int +nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct nv04_fifo *fifo = (void *)object->engine; + struct nv04_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_memory *fctx = device->imem->ramfc; + struct ramfc_desc *c; + unsigned long flags; + u32 data = chan->ramfc; + u32 chid; + + /* prevent fifo context switches */ + spin_lock_irqsave(&fifo->base.lock, flags); + nvkm_wr32(device, NV03_PFIFO_CACHES, 0); + + /* if this channel is active, replace it with a null context */ + chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max; + if (chid == chan->base.chid) { + nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); + nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); + + c = fifo->ramfc_desc; + do { + u32 rm = ((1ULL << c->bits) - 1) << c->regs; + u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; + u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; + u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm); + nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); + } while ((++c)->bits); + + c = fifo->ramfc_desc; + do { + nvkm_wr32(device, c->regp, 0x00000000); + } while ((++c)->bits); + + nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); + nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); + } + + /* restore normal operation, after disabling dma mode */ + nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); + nvkm_wr32(device, NV03_PFIFO_CACHES, 1); + spin_unlock_irqrestore(&fifo->base.lock, flags); + + return nvkm_fifo_channel_fini(&chan->base, suspend); +} + +int +nv04_fifo_chan_init(struct nvkm_object *object) +{ + struct nv04_fifo *fifo = (void *)object->engine; + struct nv04_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 mask = 1 << chan->base.chid; + unsigned long flags; + int ret; + + ret = nvkm_fifo_channel_init(&chan->base); + if (ret) + return ret; + + spin_lock_irqsave(&fifo->base.lock, flags); + nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); + spin_unlock_irqrestore(&fifo->base.lock, flags); + return 0; +} + +void +nv04_fifo_chan_dtor(struct nvkm_object *object) +{ + struct nv04_fifo *fifo = (void *)object->engine; + struct nv04_fifo_chan *chan = (void *)object; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + struct ramfc_desc *c = fifo->ramfc_desc; + + nvkm_kmap(imem->ramfc); + do { + nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); + } while ((++c)->bits); + nvkm_done(imem->ramfc); + + nvkm_fifo_channel_destroy(&chan->base); +} + +static int +nv04_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv03_channel_dma_v0 v0; + } *args = data; + struct nv04_fifo *fifo = (void *)engine; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + struct nv04_fifo_chan *chan; + int ret; + + nvif_ioctl(parent, "create channel dma size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " + "offset %08x\n", args->v0.version, + args->v0.pushbuf, args->v0.offset); + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + args->v0.chid = chan->base.chid; + + nv_parent(chan)->object_attach = nv04_fifo_object_attach; + nv_parent(chan)->object_detach = nv04_fifo_object_detach; + nv_parent(chan)->context_attach = nv04_fifo_context_attach; + chan->ramfc = chan->base.chid * 32; + + nvkm_kmap(imem->ramfc); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, + NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); + nvkm_done(imem->ramfc); + return 0; +} + +static struct nvkm_ofuncs +nv04_fifo_ofuncs = { + .ctor = nv04_fifo_chan_ctor, + .dtor = nv04_fifo_chan_dtor, + .init = nv04_fifo_chan_init, + .fini = nv04_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +nv04_fifo_sclass[] = { + { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, + {} +}; + +int +nv04_fifo_context_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nv04_fifo_base *base; + int ret; + + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_HEAP, &base); + *pobject = nv_object(base); + if (ret) + return ret; + + return 0; +} + +struct nvkm_oclass +nv04_fifo_cclass = { + .handle = NV_ENGCTX(FIFO, 0x04), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = nv04_fifo_context_ctor, + .dtor = _nvkm_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c new file mode 100644 index 000000000000..a542515e63f0 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -0,0 +1,102 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv04.h" +#include "regsnv04.h" + +#include +#include + +#include +#include + +static int +nv10_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv03_channel_dma_v0 v0; + } *args = data; + struct nv04_fifo *fifo = (void *)engine; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + struct nv04_fifo_chan *chan; + int ret; + + nvif_ioctl(parent, "create channel dma size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " + "offset %08x\n", args->v0.version, + args->v0.pushbuf, args->v0.offset); + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + args->v0.chid = chan->base.chid; + + nv_parent(chan)->object_attach = nv04_fifo_object_attach; + nv_parent(chan)->object_detach = nv04_fifo_object_detach; + nv_parent(chan)->context_attach = nv04_fifo_context_attach; + chan->ramfc = chan->base.chid * 32; + + nvkm_kmap(imem->ramfc); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, + NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); + nvkm_done(imem->ramfc); + return 0; +} + +static struct nvkm_ofuncs +nv10_fifo_ofuncs = { + .ctor = nv10_fifo_chan_ctor, + .dtor = nv04_fifo_chan_dtor, + .init = nv04_fifo_chan_init, + .fini = nv04_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +nv10_fifo_sclass[] = { + { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c new file mode 100644 index 000000000000..d0ece53a750b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -0,0 +1,104 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv04.h" +#include "regsnv04.h" + +#include +#include + +#include +#include + +static int +nv17_fifo_chan_ctor(struct nvkm_object *parent, + struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv03_channel_dma_v0 v0; + } *args = data; + struct nv04_fifo *fifo = (void *)engine; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + struct nv04_fifo_chan *chan; + int ret; + + nvif_ioctl(parent, "create channel dma size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " + "offset %08x\n", args->v0.version, + args->v0.pushbuf, args->v0.offset); + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, + 0x10000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ + &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + args->v0.chid = chan->base.chid; + + nv_parent(chan)->object_attach = nv04_fifo_object_attach; + nv_parent(chan)->object_detach = nv04_fifo_object_detach; + nv_parent(chan)->context_attach = nv04_fifo_context_attach; + chan->ramfc = chan->base.chid * 64; + + nvkm_kmap(imem->ramfc); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, + NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); + nvkm_done(imem->ramfc); + return 0; +} + +static struct nvkm_ofuncs +nv17_fifo_ofuncs = { + .ctor = nv17_fifo_chan_ctor, + .dtor = nv04_fifo_chan_dtor, + .init = nv04_fifo_chan_init, + .fini = nv04_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +nv17_fifo_sclass[] = { + { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c new file mode 100644 index 000000000000..cd3503cb6837 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c @@ -0,0 +1,225 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv04.h" +#include "regsnv04.h" + +#include +#include +#include + +#include +#include + +static int +nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *engctx) +{ + struct nv04_fifo *fifo = (void *)parent->engine; + struct nv04_fifo_chan *chan = (void *)parent; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_instmem *imem = device->imem; + unsigned long flags; + u32 reg, ctx; + + switch (nv_engidx(engctx->engine)) { + case NVDEV_ENGINE_SW: + return 0; + case NVDEV_ENGINE_GR: + reg = 0x32e0; + ctx = 0x38; + break; + case NVDEV_ENGINE_MPEG: + reg = 0x330c; + ctx = 0x54; + break; + default: + return -EINVAL; + } + + spin_lock_irqsave(&fifo->base.lock, flags); + nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); + + if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid) + nvkm_wr32(device, reg, 0x00000000); + nvkm_kmap(imem->ramfc); + nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); + nvkm_done(imem->ramfc); + + nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&fifo->base.lock, flags); + return 0; +} + +static int +nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) +{ + struct nv04_fifo *fifo = (void *)parent->engine; + struct nv04_fifo_chan *chan = (void *)parent; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_instmem *imem = device->imem; + unsigned long flags; + u32 reg, ctx; + + switch (nv_engidx(engctx->engine)) { + case NVDEV_ENGINE_SW: + return 0; + case NVDEV_ENGINE_GR: + reg = 0x32e0; + ctx = 0x38; + break; + case NVDEV_ENGINE_MPEG: + reg = 0x330c; + ctx = 0x54; + break; + default: + return -EINVAL; + } + + spin_lock_irqsave(&fifo->base.lock, flags); + nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; + nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); + + if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid) + nvkm_wr32(device, reg, nv_engctx(engctx)->addr); + nvkm_kmap(imem->ramfc); + nvkm_wo32(imem->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); + nvkm_done(imem->ramfc); + + nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&fifo->base.lock, flags); + return 0; +} + +static int +nv40_fifo_object_attach(struct nvkm_object *parent, + struct nvkm_object *object, u32 handle) +{ + struct nv04_fifo *fifo = (void *)parent->engine; + struct nv04_fifo_chan *chan = (void *)parent; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + u32 context, chid = chan->base.chid; + int ret; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) + context = nv_gpuobj(object)->addr >> 4; + else + context = 0x00000004; /* just non-zero */ + + if (object->engine) { + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW: + context |= 0x00000000; + break; + case NVDEV_ENGINE_GR: + context |= 0x00100000; + break; + case NVDEV_ENGINE_MPEG: + context |= 0x00200000; + break; + default: + return -EINVAL; + } + } + + context |= chid << 23; + + mutex_lock(&nv_subdev(fifo)->mutex); + ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context); + mutex_unlock(&nv_subdev(fifo)->mutex); + return ret; +} + +static int +nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv03_channel_dma_v0 v0; + } *args = data; + struct nv04_fifo *fifo = (void *)engine; + struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; + struct nv04_fifo_chan *chan; + int ret; + + nvif_ioctl(parent, "create channel dma size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " + "offset %08x\n", args->v0.version, + args->v0.pushbuf, args->v0.offset); + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x1000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + args->v0.chid = chan->base.chid; + + nv_parent(chan)->context_attach = nv40_fifo_context_attach; + nv_parent(chan)->context_detach = nv40_fifo_context_detach; + nv_parent(chan)->object_attach = nv40_fifo_object_attach; + nv_parent(chan)->object_detach = nv04_fifo_object_detach; + chan->ramfc = chan->base.chid * 128; + + nvkm_kmap(imem->ramfc); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | + NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | + NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +#ifdef __BIG_ENDIAN + NV_PFIFO_CACHE1_BIG_ENDIAN | +#endif + NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); + nvkm_done(imem->ramfc); + return 0; +} + +static struct nvkm_ofuncs +nv40_fifo_ofuncs = { + .ctor = nv40_fifo_chan_ctor, + .dtor = nv04_fifo_chan_dtor, + .init = nv04_fifo_chan_init, + .fini = nv04_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +nv40_fifo_sclass[] = { + { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c new file mode 100644 index 000000000000..11a283099235 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c @@ -0,0 +1,115 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv50.h" + +#include +#include + +#include +#include + +static int +nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv50_channel_dma_v0 v0; + } *args = data; + struct nvkm_device *device = parent->engine->subdev.device; + struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo_chan *chan; + int ret; + + nvif_ioctl(parent, "create channel dma size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel dma vers %d vm %llx " + "pushbuf %llx offset %016llx\n", + args->v0.version, args->v0.vm, args->v0.pushbuf, + args->v0.offset); + if (args->v0.vm) + return -ENOENT; + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->base.inst = base->base.gpuobj.addr; + args->v0.chid = chan->base.chid; + + nv_parent(chan)->context_attach = nv50_fifo_context_attach; + nv_parent(chan)->context_detach = nv50_fifo_context_detach; + nv_parent(chan)->object_attach = nv50_fifo_object_attach; + nv_parent(chan)->object_detach = nv50_fifo_object_detach; + + ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, + &chan->ramht); + if (ret) + return ret; + + nvkm_kmap(base->ramfc); + nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); + nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); + nvkm_wo32(base->ramfc, 0x44, 0x01003fff); + nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); + nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); + nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(base->ramfc, 0x78, 0x00000000); + nvkm_wo32(base->ramfc, 0x7c, 0x30000001); + nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + (4 << 24) /* SEARCH_FULL */ | + (chan->ramht->gpuobj->node->offset >> 4)); + nvkm_done(base->ramfc); + return 0; +} + +static struct nvkm_ofuncs +nv50_fifo_ofuncs_dma = { + .ctor = nv50_fifo_chan_ctor_dma, + .dtor = nv50_fifo_chan_dtor, + .init = nv50_fifo_chan_init, + .fini = nv50_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +nv50_fifo_sclass[] = { + { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, + { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index c2ce3fa31f10..ab0ecc423e68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -22,432 +22,22 @@ * Authors: Ben Skeggs */ #include "nv50.h" -#include "nv04.h" - -#include -#include -#include -#include -#include - -#include -#include - -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ - -static int -g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) -{ - struct nv50_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *ectx = (void *)object; - u64 limit = ectx->addr + ectx->size - 1; - u64 start = ectx->addr; - u32 addr; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0020; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break; - case NVDEV_ENGINE_MSPPP : - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : addr = 0x00a0; break; - case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; - default: - return -EINVAL; - } - - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00190000); - nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); - nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | - upper_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); - return 0; -} - -static int -g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) -{ - struct nv50_fifo *fifo = (void *)parent->engine; - struct nv50_fifo_base *base = (void *)parent->parent; - struct nv50_fifo_chan *chan = (void *)parent; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 addr, save, engn; - bool done; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break; - case NVDEV_ENGINE_MSPPP : - case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; - case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; - default: - return -EINVAL; - } - - save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); - nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); - done = nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) - break; - ) >= 0; - nvkm_wr32(device, 0x002520, save); - if (!done) { - nvkm_error(subdev, "channel %d [%s] unload timeout\n", - chan->base.chid, nvkm_client_name(chan)); - if (suspend) - return -EBUSY; - } - - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00000000); - nvkm_wo32(base->eng, addr + 0x04, 0x00000000); - nvkm_wo32(base->eng, addr + 0x08, 0x00000000); - nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); - return 0; -} - -static int -g84_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) -{ - struct nv50_fifo_chan *chan = (void *)parent; - u32 context; - - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->node->offset >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context |= 0x00000000; break; - case NVDEV_ENGINE_GR : context |= 0x00100000; break; - case NVDEV_ENGINE_MPEG : - case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break; - case NVDEV_ENGINE_ME : - case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : - case NVDEV_ENGINE_VIC : context |= 0x00500000; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; - default: - return -EINVAL; - } - } - - return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); -} - -static int -g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv50_channel_dma_v0 v0; - } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; - struct nv50_fifo_chan *chan; - int ret; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " - "offset %016llx\n", args->v0.version, - args->v0.pushbuf, args->v0.offset); - if (args->v0.vm) - return -ENOENT; - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); - if (ret) - return ret; - - nv_parent(chan)->context_attach = g84_fifo_context_attach; - nv_parent(chan)->context_detach = g84_fifo_context_detach; - nv_parent(chan)->object_attach = g84_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; - - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | - (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); - nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); - nvkm_done(base->ramfc); - return 0; -} - -static int -g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv50_channel_gpfifo_v0 v0; - } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; - struct nv50_fifo_chan *chan; - u64 ioffset, ilength; - int ret; - - nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %llx " - "ioffset %016llx ilength %08x\n", - args->v0.version, args->v0.pushbuf, args->v0.ioffset, - args->v0.ilength); - if (args->v0.vm) - return -ENOENT; - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); - if (ret) - return ret; - - nv_parent(chan)->context_attach = g84_fifo_context_attach; - nv_parent(chan)->context_detach = g84_fifo_context_detach; - nv_parent(chan)->object_attach = g84_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; - - ioffset = args->v0.ioffset; - ilength = order_base_2(args->v0.ilength / 8); - - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); - nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | - (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); - nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); - nvkm_done(base->ramfc); - return 0; -} - -static int -g84_fifo_chan_init(struct nvkm_object *object) -{ - struct nv50_fifo *fifo = (void *)object->engine; - struct nv50_fifo_base *base = (void *)object->parent; - struct nv50_fifo_chan *chan = (void *)object; - struct nvkm_gpuobj *ramfc = base->ramfc; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - - nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); - nv50_fifo_playlist_update(fifo); - return 0; -} - -static struct nvkm_ofuncs -g84_fifo_ofuncs_dma = { - .ctor = g84_fifo_chan_ctor_dma, - .dtor = nv50_fifo_chan_dtor, - .init = g84_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_ofuncs -g84_fifo_ofuncs_ind = { - .ctor = g84_fifo_chan_ctor_ind, - .dtor = nv50_fifo_chan_dtor, - .init = g84_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -g84_fifo_sclass[] = { - { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, - { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, - {} -}; - -/******************************************************************************* - * FIFO context - basically just the instmem reserved for the channel - ******************************************************************************/ - -static int -g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct nv50_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x0200, 0, true, &base->base.gpuobj, - &base->eng); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, - &base->pgd); - if (ret) - return ret; - - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, &base->base.gpuobj, - &base->cache); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, &base->base.gpuobj, - &base->ramfc); - if (ret) - return ret; - - return 0; -} - -static struct nvkm_oclass -g84_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x84), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g84_fifo_context_ctor, - .dtor = nv50_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; - -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ +#include "channv50.h" static void -g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; - nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); + nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); } static void -g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) { struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; - nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); + nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); } static const struct nvkm_event_func @@ -472,12 +62,12 @@ g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->playlist[0]); + false, &fifo->runlist[0]); if (ret) return ret; ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->playlist[1]); + false, &fifo->runlist[1]); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 7f05985ebb37..b88e7c569c0a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -21,61 +21,41 @@ * * Authors: Ben Skeggs */ -#include +#include "gf100.h" +#include "changf100.h" #include -#include #include #include #include -#include -#include -#include #include #include -#include -#include - -struct gf100_fifo { - struct nvkm_fifo base; - - struct work_struct fault; - u64 mask; - - struct { - struct nvkm_memory *mem[2]; - int active; - wait_queue_head_t wait; - } runlist; - - struct { - struct nvkm_memory *mem; - struct nvkm_vma bar; - } user; - int spoon_nr; -}; -struct gf100_fifo_base { - struct nvkm_fifo_base base; - struct nvkm_gpuobj *pgd; - struct nvkm_vm *vm; -}; +static void +gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) +{ + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_device *device = fifo->engine.subdev.device; + nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); +} -struct gf100_fifo_chan { - struct nvkm_fifo_chan base; - enum { - STOPPED, - RUNNING, - KILLED - } state; -}; +static void +gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +{ + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_device *device = fifo->engine.subdev.device; + nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); +} -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ +static const struct nvkm_event_func +gf100_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = gf100_fifo_uevent_init, + .fini = gf100_fifo_uevent_fini, +}; -static void +void gf100_fifo_runlist_update(struct gf100_fifo *fifo) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; @@ -108,289 +88,6 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo) mutex_unlock(&nv_subdev(fifo)->mutex); } -static int -gf100_fifo_context_attach(struct nvkm_object *parent, - struct nvkm_object *object) -{ - struct gf100_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - struct nvkm_engctx *ectx = (void *)object; - u32 addr; - int ret; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_CE0 : addr = 0x0230; break; - case NVDEV_ENGINE_CE1 : addr = 0x0240; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; - default: - return -EINVAL; - } - - if (!ectx->vma.node) { - ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); - if (ret) - return ret; - - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - } - - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); - nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); - nvkm_done(engn); - return 0; -} - -static int -gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) -{ - struct gf100_fifo *fifo = (void *)parent->engine; - struct gf100_fifo_base *base = (void *)parent->parent; - struct gf100_fifo_chan *chan = (void *)parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 addr; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_CE0 : addr = 0x0230; break; - case NVDEV_ENGINE_CE1 : addr = 0x0240; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; - default: - return -EINVAL; - } - - nvkm_wr32(device, 0x002634, chan->base.chid); - if (nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x002634) == chan->base.chid) - break; - ) < 0) { - nvkm_error(subdev, "channel %d [%s] kick timeout\n", - chan->base.chid, nvkm_client_name(chan)); - if (suspend) - return -EBUSY; - } - - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, 0x00000000); - nvkm_wo32(engn, addr + 0x04, 0x00000000); - nvkm_done(engn); - return 0; -} - -static int -gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct fermi_channel_gpfifo_v0 v0; - } *args = data; - struct gf100_fifo *fifo = (void *)engine; - struct gf100_fifo_base *base = (void *)parent; - struct gf100_fifo_chan *chan; - struct nvkm_gpuobj *ramfc = &base->base.gpuobj; - u64 usermem, ioffset, ilength; - int ret, i; - - nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel gpfifo vers %d " - "ioffset %016llx ilength %08x\n", - args->v0.version, args->v0.ioffset, - args->v0.ilength); - if (args->v0.vm) - return -ENOENT; - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, - fifo->user.bar.offset, 0x1000, 0, - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_CE1) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = gf100_fifo_context_attach; - nv_parent(chan)->context_detach = gf100_fifo_context_detach; - - usermem = chan->base.chid * 0x1000; - ioffset = args->v0.ioffset; - ilength = order_base_2(args->v0.ilength / 8); - - nvkm_kmap(fifo->user.mem); - for (i = 0; i < 0x1000; i += 4) - nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); - nvkm_done(fifo->user.mem); - usermem = nvkm_memory_addr(fifo->user.mem) + usermem; - - nvkm_kmap(ramfc); - nvkm_wo32(ramfc, 0x08, lower_32_bits(usermem)); - nvkm_wo32(ramfc, 0x0c, upper_32_bits(usermem)); - nvkm_wo32(ramfc, 0x10, 0x0000face); - nvkm_wo32(ramfc, 0x30, 0xfffff902); - nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); - nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(ramfc, 0x54, 0x00000002); - nvkm_wo32(ramfc, 0x84, 0x20400000); - nvkm_wo32(ramfc, 0x94, 0x30000001); - nvkm_wo32(ramfc, 0x9c, 0x00000100); - nvkm_wo32(ramfc, 0xa4, 0x1f1f1f1f); - nvkm_wo32(ramfc, 0xa8, 0x1f1f1f1f); - nvkm_wo32(ramfc, 0xac, 0x0000001f); - nvkm_wo32(ramfc, 0xb8, 0xf8000000); - nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ - nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ - nvkm_done(ramfc); - return 0; -} - -static int -gf100_fifo_chan_init(struct nvkm_object *object) -{ - struct nvkm_gpuobj *base = nv_gpuobj(object->parent); - struct gf100_fifo *fifo = (void *)object->engine; - struct gf100_fifo_chan *chan = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - - nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); - - if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { - nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001); - gf100_fifo_runlist_update(fifo); - } - - return 0; -} - -static void gf100_fifo_intr_engine(struct gf100_fifo *fifo); - -static int -gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) -{ - struct gf100_fifo *fifo = (void *)object->engine; - struct gf100_fifo_chan *chan = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - - if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { - nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000); - gf100_fifo_runlist_update(fifo); - } - - gf100_fifo_intr_engine(fifo); - - nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000); - return nvkm_fifo_channel_fini(&chan->base, suspend); -} - -static struct nvkm_ofuncs -gf100_fifo_ofuncs = { - .ctor = gf100_fifo_chan_ctor, - .dtor = _nvkm_fifo_channel_dtor, - .init = gf100_fifo_chan_init, - .fini = gf100_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -gf100_fifo_sclass[] = { - { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, - {} -}; - -/******************************************************************************* - * FIFO context - instmem heap and vm setup - ******************************************************************************/ - -static int -gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct gf100_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd); - if (ret) - return ret; - - nvkm_kmap(&base->base.gpuobj); - nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); - nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); - nvkm_done(&base->base.gpuobj); - - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); - if (ret) - return ret; - - return 0; -} - -static void -gf100_fifo_context_dtor(struct nvkm_object *object) -{ - struct gf100_fifo_base *base = (void *)object; - nvkm_vm_ref(NULL, &base->vm, base->pgd); - nvkm_gpuobj_del(&base->pgd); - nvkm_fifo_context_destroy(&base->base); -} - -static struct nvkm_oclass -gf100_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_fifo_context_ctor, - .dtor = gf100_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; - -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ - static inline int gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) { @@ -739,7 +436,7 @@ gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) } } -static void +void gf100_fifo_intr_engine(struct gf100_fifo *fifo) { struct nvkm_device *device = fifo->base.engine.subdev.device; @@ -825,28 +522,62 @@ gf100_fifo_intr(struct nvkm_subdev *subdev) } } -static void -gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) +static int +gf100_fifo_init(struct nvkm_object *object) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); - struct nvkm_device *device = fifo->engine.subdev.device; - nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); + struct gf100_fifo *fifo = (void *)object; + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + int ret, i; + + ret = nvkm_fifo_init(&fifo->base); + if (ret) + return ret; + + nvkm_wr32(device, 0x000204, 0xffffffff); + nvkm_wr32(device, 0x002204, 0xffffffff); + + fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204)); + nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr); + + /* assign engines to PBDMAs */ + if (fifo->spoon_nr >= 3) { + nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ + nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ + nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ + nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ + nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ + nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ + } + + /* PBDMA[n] */ + for (i = 0; i < fifo->spoon_nr; i++) { + nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); + nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ + nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ + } + + nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); + nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); + + nvkm_wr32(device, 0x002100, 0xffffffff); + nvkm_wr32(device, 0x002140, 0x7fffffff); + nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ + return 0; } static void -gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +gf100_fifo_dtor(struct nvkm_object *object) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); - struct nvkm_device *device = fifo->engine.subdev.device; - nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); -} + struct gf100_fifo *fifo = (void *)object; -static const struct nvkm_event_func -gf100_fifo_uevent_func = { - .ctor = nvkm_fifo_uevent_ctor, - .init = gf100_fifo_uevent_init, - .fini = gf100_fifo_uevent_fini, -}; + nvkm_vm_put(&fifo->user.bar); + nvkm_memory_del(&fifo->user.mem); + nvkm_memory_del(&fifo->runlist.mem[0]); + nvkm_memory_del(&fifo->runlist.mem[1]); + + nvkm_fifo_destroy(&fifo->base); +} static int gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, @@ -899,62 +630,6 @@ gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } -static void -gf100_fifo_dtor(struct nvkm_object *object) -{ - struct gf100_fifo *fifo = (void *)object; - - nvkm_vm_put(&fifo->user.bar); - nvkm_memory_del(&fifo->user.mem); - nvkm_memory_del(&fifo->runlist.mem[0]); - nvkm_memory_del(&fifo->runlist.mem[1]); - - nvkm_fifo_destroy(&fifo->base); -} - -static int -gf100_fifo_init(struct nvkm_object *object) -{ - struct gf100_fifo *fifo = (void *)object; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - int ret, i; - - ret = nvkm_fifo_init(&fifo->base); - if (ret) - return ret; - - nvkm_wr32(device, 0x000204, 0xffffffff); - nvkm_wr32(device, 0x002204, 0xffffffff); - - fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204)); - nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr); - - /* assign engines to PBDMAs */ - if (fifo->spoon_nr >= 3) { - nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ - nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ - nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ - nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ - nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ - nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ - } - - /* PBDMA[n] */ - for (i = 0; i < fifo->spoon_nr; i++) { - nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); - nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ - nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ - } - - nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); - nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); - - nvkm_wr32(device, 0x002100, 0xffffffff); - nvkm_wr32(device, 0x002140, 0x7fffffff); - nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ - return 0; -} struct nvkm_oclass * gf100_fifo_oclass = &(struct nvkm_oclass) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h new file mode 100644 index 000000000000..5190bbc6e1a1 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h @@ -0,0 +1,26 @@ +#ifndef __GF100_FIFO_H__ +#define __GF100_FIFO_H__ +#include "priv.h" + +struct gf100_fifo { + struct nvkm_fifo base; + + struct work_struct fault; + u64 mask; + + struct { + struct nvkm_memory *mem[2]; + int active; + wait_queue_head_t wait; + } runlist; + + struct { + struct nvkm_memory *mem; + struct nvkm_vma bar; + } user; + int spoon_nr; +}; + +void gf100_fifo_intr_engine(struct gf100_fifo *); +void gf100_fifo_runlist_update(struct gf100_fifo *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index e0badfc54dc8..9ab3fd40b7dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -22,20 +22,15 @@ * Authors: Ben Skeggs */ #include "gk104.h" +#include "changk104.h" #include -#include #include #include #include -#include -#include -#include #include #include -#include -#include #define _(a,b) { (a), ((1ULL << (a)) | (b)) } static const struct { @@ -54,47 +49,30 @@ static const struct { #undef _ #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) -struct gk104_fifo_engn { - struct nvkm_memory *runlist[2]; - int cur_runlist; - wait_queue_head_t wait; -}; - -struct gk104_fifo { - struct nvkm_fifo base; - - struct work_struct fault; - u64 mask; - - struct gk104_fifo_engn engine[FIFO_ENGINE_NR]; - struct { - struct nvkm_memory *mem; - struct nvkm_vma bar; - } user; - int spoon_nr; -}; +static void +gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +{ + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_device *device = fifo->engine.subdev.device; + nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); +} -struct gk104_fifo_base { - struct nvkm_fifo_base base; - struct nvkm_gpuobj *pgd; - struct nvkm_vm *vm; -}; +static void +gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index) +{ + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); + struct nvkm_device *device = fifo->engine.subdev.device; + nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); +} -struct gk104_fifo_chan { - struct nvkm_fifo_chan base; - u32 engine; - enum { - STOPPED, - RUNNING, - KILLED - } state; +static const struct nvkm_event_func +gk104_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = gk104_fifo_uevent_init, + .fini = gk104_fifo_uevent_fini, }; -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ - -static void +void gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) { struct gk104_fifo_engn *engn = &fifo->engine[engine]; @@ -128,322 +106,6 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) mutex_unlock(&nv_subdev(fifo)->mutex); } -static int -gk104_fifo_context_attach(struct nvkm_object *parent, - struct nvkm_object *object) -{ - struct gk104_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - struct nvkm_engctx *ectx = (void *)object; - u32 addr; - int ret; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : - return 0; - case NVDEV_ENGINE_CE0: - case NVDEV_ENGINE_CE1: - case NVDEV_ENGINE_CE2: - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; - default: - return -EINVAL; - } - - if (!ectx->vma.node) { - ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); - if (ret) - return ret; - - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - } - - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); - nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); - nvkm_done(engn); - return 0; -} - -static int -gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) -{ - struct nvkm_object *obj = (void *)chan; - struct gk104_fifo *fifo = (void *)obj->engine; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - - nvkm_wr32(device, 0x002634, chan->base.chid); - if (nvkm_msec(device, 2000, - if (!(nvkm_rd32(device, 0x002634) & 0x00100000)) - break; - ) < 0) { - nvkm_error(subdev, "channel %d [%s] kick timeout\n", - chan->base.chid, nvkm_client_name(chan)); - return -EBUSY; - } - - return 0; -} - -static int -gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) -{ - struct gk104_fifo_base *base = (void *)parent->parent; - struct gk104_fifo_chan *chan = (void *)parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - u32 addr; - int ret; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_CE0 : - case NVDEV_ENGINE_CE1 : - case NVDEV_ENGINE_CE2 : addr = 0x0000; break; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; - default: - return -EINVAL; - } - - ret = gk104_fifo_chan_kick(chan); - if (ret && suspend) - return ret; - - if (addr) { - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, 0x00000000); - nvkm_wo32(engn, addr + 0x04, 0x00000000); - nvkm_done(engn); - } - - return 0; -} - -static int -gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct kepler_channel_gpfifo_a_v0 v0; - } *args = data; - struct gk104_fifo *fifo = (void *)engine; - struct gk104_fifo_base *base = (void *)parent; - struct gk104_fifo_chan *chan; - struct nvkm_gpuobj *ramfc = &base->base.gpuobj; - u64 usermem, ioffset, ilength; - u32 engines; - int ret, i; - - nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel gpfifo vers %d " - "ioffset %016llx ilength %08x engine %08x\n", - args->v0.version, args->v0.ioffset, - args->v0.ilength, args->v0.engine); - if (args->v0.vm) - return -ENOENT; - } else - return ret; - - for (i = 0, engines = 0; i < FIFO_ENGINE_NR; i++) { - if (!nvkm_engine(parent, fifo_engine[i].subdev)) - continue; - engines |= (1 << i); - } - - if (!args->v0.engine) { - static struct nvkm_oclass oclass = { - .ofuncs = &nvkm_object_ofuncs, - }; - args->v0.engine = engines; - return nvkm_object_old(parent, engine, &oclass, NULL, 0, pobject); - } - - engines &= args->v0.engine; - if (!engines) { - nvif_ioctl(parent, "unsupported engines %08x\n", - args->v0.engine); - return -ENODEV; - } - i = __ffs(engines); - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, - fifo->user.bar.offset, 0x200, 0, - fifo_engine[i].mask, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = gk104_fifo_context_attach; - nv_parent(chan)->context_detach = gk104_fifo_context_detach; - chan->engine = i; - - usermem = chan->base.chid * 0x200; - ioffset = args->v0.ioffset; - ilength = order_base_2(args->v0.ilength / 8); - - nvkm_kmap(fifo->user.mem); - for (i = 0; i < 0x200; i += 4) - nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); - nvkm_done(fifo->user.mem); - usermem = nvkm_memory_addr(fifo->user.mem) + usermem; - - nvkm_kmap(ramfc); - nvkm_wo32(ramfc, 0x08, lower_32_bits(usermem)); - nvkm_wo32(ramfc, 0x0c, upper_32_bits(usermem)); - nvkm_wo32(ramfc, 0x10, 0x0000face); - nvkm_wo32(ramfc, 0x30, 0xfffff902); - nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); - nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(ramfc, 0x84, 0x20400000); - nvkm_wo32(ramfc, 0x94, 0x30000001); - nvkm_wo32(ramfc, 0x9c, 0x00000100); - nvkm_wo32(ramfc, 0xac, 0x0000001f); - nvkm_wo32(ramfc, 0xe8, chan->base.chid); - nvkm_wo32(ramfc, 0xb8, 0xf8000000); - nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ - nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ - nvkm_done(ramfc); - return 0; -} - -static int -gk104_fifo_chan_init(struct nvkm_object *object) -{ - struct nvkm_gpuobj *base = nv_gpuobj(object->parent); - struct gk104_fifo *fifo = (void *)object->engine; - struct gk104_fifo_chan *chan = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - - nvkm_mask(device, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); - nvkm_wr32(device, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); - - if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { - nvkm_mask(device, 0x800004 + (chid * 8), 0x00000400, 0x00000400); - gk104_fifo_runlist_update(fifo, chan->engine); - nvkm_mask(device, 0x800004 + (chid * 8), 0x00000400, 0x00000400); - } - - return 0; -} - -static int -gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) -{ - struct gk104_fifo *fifo = (void *)object->engine; - struct gk104_fifo_chan *chan = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - - if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { - nvkm_mask(device, 0x800004 + (chid * 8), 0x00000800, 0x00000800); - gk104_fifo_runlist_update(fifo, chan->engine); - } - - nvkm_wr32(device, 0x800000 + (chid * 8), 0x00000000); - return nvkm_fifo_channel_fini(&chan->base, suspend); -} - -struct nvkm_ofuncs -gk104_fifo_chan_ofuncs = { - .ctor = gk104_fifo_chan_ctor, - .dtor = _nvkm_fifo_channel_dtor, - .init = gk104_fifo_chan_init, - .fini = gk104_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -gk104_fifo_sclass[] = { - { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, - {} -}; - -/******************************************************************************* - * FIFO context - instmem heap and vm setup - ******************************************************************************/ - -static int -gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct gk104_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd); - if (ret) - return ret; - - nvkm_kmap(&base->base.gpuobj); - nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); - nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); - nvkm_done(&base->base.gpuobj); - - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); - if (ret) - return ret; - - return 0; -} - -static void -gk104_fifo_context_dtor(struct nvkm_object *object) -{ - struct gk104_fifo_base *base = (void *)object; - nvkm_vm_ref(NULL, &base->vm, base->pgd); - nvkm_gpuobj_del(&base->pgd); - nvkm_fifo_context_destroy(&base->base); -} - -static struct nvkm_oclass -gk104_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0xe0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_fifo_context_ctor, - .dtor = gk104_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; - -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ - static inline int gk104_fifo_engidx(struct gk104_fifo *fifo, u32 engn) { @@ -998,29 +660,6 @@ gk104_fifo_intr(struct nvkm_subdev *subdev) } } -static void -gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index) -{ - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); - struct nvkm_device *device = fifo->engine.subdev.device; - nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); -} - -static void -gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) -{ - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); - struct nvkm_device *device = fifo->engine.subdev.device; - nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); -} - -static const struct nvkm_event_func -gk104_fifo_uevent_func = { - .ctor = nvkm_fifo_uevent_ctor, - .init = gk104_fifo_uevent_init, - .fini = gk104_fifo_uevent_fini, -}; - int gk104_fifo_fini(struct nvkm_object *object, bool suspend) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index b77d75f86b73..b71abef84349 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -1,20 +1,39 @@ -#ifndef __NVKM_FIFO_NVE0_H__ -#define __NVKM_FIFO_NVE0_H__ -#include +#ifndef __GK104_FIFO_H__ +#define __GK104_FIFO_H__ +#include "priv.h" -int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void gk104_fifo_dtor(struct nvkm_object *); -int gk104_fifo_init(struct nvkm_object *); -int gk104_fifo_fini(struct nvkm_object *, bool); +struct gk104_fifo_engn { + struct nvkm_memory *runlist[2]; + int cur_runlist; + wait_queue_head_t wait; +}; + +struct gk104_fifo { + struct nvkm_fifo base; + + struct work_struct fault; + u64 mask; + + struct gk104_fifo_engn engine[7]; + struct { + struct nvkm_memory *mem; + struct nvkm_vma bar; + } user; + int spoon_nr; +}; struct gk104_fifo_impl { struct nvkm_oclass base; u32 channels; }; -extern struct nvkm_ofuncs gk104_fifo_chan_ofuncs; +int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gk104_fifo_dtor(struct nvkm_object *); +int gk104_fifo_init(struct nvkm_object *); +int gk104_fifo_fini(struct nvkm_object *, bool); +void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine); int gm204_fifo_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c index 6a93b911e8a8..2367b4f81a91 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c @@ -22,14 +22,7 @@ * Authors: Ben Skeggs */ #include "gk104.h" - -#include - -static struct nvkm_oclass -gm204_fifo_sclass[] = { - { MAXWELL_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, - {} -}; +#include "changk104.h" int gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c new file mode 100644 index 000000000000..fd11e0afec25 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c @@ -0,0 +1,122 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv50.h" + +#include +#include + +#include +#include + +static int +g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv50_channel_gpfifo_v0 v0; + } *args = data; + struct nvkm_device *device = parent->engine->subdev.device; + struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo_chan *chan; + u64 ioffset, ilength; + int ret; + + nvif_ioctl(parent, "create channel gpfifo size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " + "pushbuf %llx ioffset %016llx " + "ilength %08x\n", + args->v0.version, args->v0.vm, args->v0.pushbuf, + args->v0.ioffset, args->v0.ilength); + if (args->v0.vm) + return -ENOENT; + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_VP) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_VIC), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->base.inst = base->base.gpuobj.addr; + args->v0.chid = chan->base.chid; + + ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, + &chan->ramht); + if (ret) + return ret; + + nv_parent(chan)->context_attach = g84_fifo_context_attach; + nv_parent(chan)->context_detach = g84_fifo_context_detach; + nv_parent(chan)->object_attach = g84_fifo_object_attach; + nv_parent(chan)->object_detach = nv50_fifo_object_detach; + + ioffset = args->v0.ioffset; + ilength = order_base_2(args->v0.ilength / 8); + + nvkm_kmap(base->ramfc); + nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); + nvkm_wo32(base->ramfc, 0x44, 0x01003fff); + nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); + nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); + nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); + nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(base->ramfc, 0x78, 0x00000000); + nvkm_wo32(base->ramfc, 0x7c, 0x30000001); + nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + (4 << 24) /* SEARCH_FULL */ | + (chan->ramht->gpuobj->node->offset >> 4)); + nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); + nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); + nvkm_done(base->ramfc); + return 0; +} + +struct nvkm_ofuncs +g84_fifo_ofuncs_ind = { + .ctor = g84_fifo_chan_ctor_ind, + .dtor = nv50_fifo_chan_dtor, + .init = g84_fifo_chan_init, + .fini = nv50_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c new file mode 100644 index 000000000000..7fd6401ca905 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -0,0 +1,304 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "changf100.h" + +#include +#include +#include + +#include +#include + +static int +gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) +{ + struct gf100_fifo *fifo = (void *)parent->engine; + struct gf100_fifo_base *base = (void *)parent->parent; + struct gf100_fifo_chan *chan = (void *)parent; + struct nvkm_gpuobj *engn = &base->base.gpuobj; + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 addr; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_CE0 : addr = 0x0230; break; + case NVDEV_ENGINE_CE1 : addr = 0x0240; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; + default: + return -EINVAL; + } + + nvkm_wr32(device, 0x002634, chan->base.chid); + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x002634) == chan->base.chid) + break; + ) < 0) { + nvkm_error(subdev, "channel %d [%s] kick timeout\n", + chan->base.chid, nvkm_client_name(chan)); + if (suspend) + return -EBUSY; + } + + nvkm_kmap(engn); + nvkm_wo32(engn, addr + 0x00, 0x00000000); + nvkm_wo32(engn, addr + 0x04, 0x00000000); + nvkm_done(engn); + return 0; +} + +static int +gf100_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) +{ + struct gf100_fifo_base *base = (void *)parent->parent; + struct nvkm_gpuobj *engn = &base->base.gpuobj; + struct nvkm_engctx *ectx = (void *)object; + u32 addr; + int ret; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_CE0 : addr = 0x0230; break; + case NVDEV_ENGINE_CE1 : addr = 0x0240; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; + default: + return -EINVAL; + } + + if (!ectx->vma.node) { + ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm, + NV_MEM_ACCESS_RW, &ectx->vma); + if (ret) + return ret; + + nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + } + + nvkm_kmap(engn); + nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); + nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); + nvkm_done(engn); + return 0; +} + +static int +gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct gf100_fifo *fifo = (void *)object->engine; + struct gf100_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + + if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { + nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000); + gf100_fifo_runlist_update(fifo); + } + + gf100_fifo_intr_engine(fifo); + + nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000); + return nvkm_fifo_channel_fini(&chan->base, suspend); +} + +static int +gf100_fifo_chan_init(struct nvkm_object *object) +{ + struct nvkm_gpuobj *base = nv_gpuobj(object->parent); + struct gf100_fifo *fifo = (void *)object->engine; + struct gf100_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + int ret; + + ret = nvkm_fifo_channel_init(&chan->base); + if (ret) + return ret; + + nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); + + if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { + nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001); + gf100_fifo_runlist_update(fifo); + } + + return 0; +} + +static int +gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct fermi_channel_gpfifo_v0 v0; + } *args = data; + struct gf100_fifo *fifo = (void *)engine; + struct gf100_fifo_base *base = (void *)parent; + struct gf100_fifo_chan *chan; + struct nvkm_gpuobj *ramfc = &base->base.gpuobj; + u64 usermem, ioffset, ilength; + int ret, i; + + nvif_ioctl(parent, "create channel gpfifo size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx" + "ioffset %016llx ilength %08x\n", + args->v0.version, args->v0.vm, args->v0.ioffset, + args->v0.ilength); + if (args->v0.vm) + return -ENOENT; + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, + fifo->user.bar.offset, 0x1000, 0, + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_CE1) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->base.inst = base->base.gpuobj.addr; + args->v0.chid = chan->base.chid; + + nv_parent(chan)->context_attach = gf100_fifo_context_attach; + nv_parent(chan)->context_detach = gf100_fifo_context_detach; + + usermem = chan->base.chid * 0x1000; + ioffset = args->v0.ioffset; + ilength = order_base_2(args->v0.ilength / 8); + + nvkm_kmap(fifo->user.mem); + for (i = 0; i < 0x1000; i += 4) + nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); + nvkm_done(fifo->user.mem); + usermem = nvkm_memory_addr(fifo->user.mem) + usermem; + + nvkm_kmap(ramfc); + nvkm_wo32(ramfc, 0x08, lower_32_bits(usermem)); + nvkm_wo32(ramfc, 0x0c, upper_32_bits(usermem)); + nvkm_wo32(ramfc, 0x10, 0x0000face); + nvkm_wo32(ramfc, 0x30, 0xfffff902); + nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); + nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); + nvkm_wo32(ramfc, 0x54, 0x00000002); + nvkm_wo32(ramfc, 0x84, 0x20400000); + nvkm_wo32(ramfc, 0x94, 0x30000001); + nvkm_wo32(ramfc, 0x9c, 0x00000100); + nvkm_wo32(ramfc, 0xa4, 0x1f1f1f1f); + nvkm_wo32(ramfc, 0xa8, 0x1f1f1f1f); + nvkm_wo32(ramfc, 0xac, 0x0000001f); + nvkm_wo32(ramfc, 0xb8, 0xf8000000); + nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ + nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ + nvkm_done(ramfc); + return 0; +} + +static struct nvkm_ofuncs +gf100_fifo_ofuncs = { + .ctor = gf100_fifo_chan_ctor, + .dtor = _nvkm_fifo_channel_dtor, + .init = gf100_fifo_chan_init, + .fini = gf100_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +gf100_fifo_sclass[] = { + { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, + {} +}; + +static int +gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_engine(engine)->subdev.device; + struct gf100_fifo_base *base; + int ret; + + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC | + NVOBJ_FLAG_HEAP, &base); + *pobject = nv_object(base); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd); + if (ret) + return ret; + + nvkm_kmap(&base->base.gpuobj); + nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); + nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); + nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); + nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); + nvkm_done(&base->base.gpuobj); + + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); + if (ret) + return ret; + + return 0; +} + +static void +gf100_fifo_context_dtor(struct nvkm_object *object) +{ + struct gf100_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_del(&base->pgd); + nvkm_fifo_context_destroy(&base->base); +} + +struct nvkm_oclass +gf100_fifo_cclass = { + .handle = NV_ENGCTX(FIFO, 0xc0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fifo_context_ctor, + .dtor = gf100_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c new file mode 100644 index 000000000000..264c9705bccc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -0,0 +1,357 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "changk104.h" + +#include +#include +#include +#include + +#include +#include + +#define _(a,b) { (a), ((1ULL << (a)) | (b)) } +static const struct { + u64 subdev; + u64 mask; +} fifo_engine[] = { + _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_CE2)), + _(NVDEV_ENGINE_MSPDEC , 0), + _(NVDEV_ENGINE_MSPPP , 0), + _(NVDEV_ENGINE_MSVLD , 0), + _(NVDEV_ENGINE_CE0 , 0), + _(NVDEV_ENGINE_CE1 , 0), + _(NVDEV_ENGINE_MSENC , 0), +}; +#undef _ +#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) + +static int +gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) +{ + struct nvkm_object *obj = (void *)chan; + struct gk104_fifo *fifo = (void *)obj->engine; + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + + nvkm_wr32(device, 0x002634, chan->base.chid); + if (nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x002634) & 0x00100000)) + break; + ) < 0) { + nvkm_error(subdev, "channel %d [%s] kick timeout\n", + chan->base.chid, nvkm_client_name(chan)); + return -EBUSY; + } + + return 0; +} + +static int +gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, + struct nvkm_object *object) +{ + struct gk104_fifo_base *base = (void *)parent->parent; + struct gk104_fifo_chan *chan = (void *)parent; + struct nvkm_gpuobj *engn = &base->base.gpuobj; + u32 addr; + int ret; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : return 0; + case NVDEV_ENGINE_CE0 : + case NVDEV_ENGINE_CE1 : + case NVDEV_ENGINE_CE2 : addr = 0x0000; break; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; + default: + return -EINVAL; + } + + ret = gk104_fifo_chan_kick(chan); + if (ret && suspend) + return ret; + + if (addr) { + nvkm_kmap(engn); + nvkm_wo32(engn, addr + 0x00, 0x00000000); + nvkm_wo32(engn, addr + 0x04, 0x00000000); + nvkm_done(engn); + } + + return 0; +} + +static int +gk104_fifo_context_attach(struct nvkm_object *parent, + struct nvkm_object *object) +{ + struct gk104_fifo_base *base = (void *)parent->parent; + struct nvkm_gpuobj *engn = &base->base.gpuobj; + struct nvkm_engctx *ectx = (void *)object; + u32 addr; + int ret; + + switch (nv_engidx(object->engine)) { + case NVDEV_ENGINE_SW : + return 0; + case NVDEV_ENGINE_CE0: + case NVDEV_ENGINE_CE1: + case NVDEV_ENGINE_CE2: + nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + return 0; + case NVDEV_ENGINE_GR : addr = 0x0210; break; + case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; + case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; + case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; + default: + return -EINVAL; + } + + if (!ectx->vma.node) { + ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm, + NV_MEM_ACCESS_RW, &ectx->vma); + if (ret) + return ret; + + nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + } + + nvkm_kmap(engn); + nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); + nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); + nvkm_done(engn); + return 0; +} + +static int +gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct gk104_fifo *fifo = (void *)object->engine; + struct gk104_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + + if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { + nvkm_mask(device, 0x800004 + (chid * 8), 0x00000800, 0x00000800); + gk104_fifo_runlist_update(fifo, chan->engine); + } + + nvkm_wr32(device, 0x800000 + (chid * 8), 0x00000000); + return nvkm_fifo_channel_fini(&chan->base, suspend); +} + +static int +gk104_fifo_chan_init(struct nvkm_object *object) +{ + struct nvkm_gpuobj *base = nv_gpuobj(object->parent); + struct gk104_fifo *fifo = (void *)object->engine; + struct gk104_fifo_chan *chan = (void *)object; + struct nvkm_device *device = fifo->base.engine.subdev.device; + u32 chid = chan->base.chid; + int ret; + + ret = nvkm_fifo_channel_init(&chan->base); + if (ret) + return ret; + + nvkm_mask(device, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); + nvkm_wr32(device, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); + + if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { + nvkm_mask(device, 0x800004 + (chid * 8), 0x00000400, 0x00000400); + gk104_fifo_runlist_update(fifo, chan->engine); + nvkm_mask(device, 0x800004 + (chid * 8), 0x00000400, 0x00000400); + } + + return 0; +} + +static int +gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct kepler_channel_gpfifo_a_v0 v0; + } *args = data; + struct gk104_fifo *fifo = (void *)engine; + struct gk104_fifo_base *base = (void *)parent; + struct gk104_fifo_chan *chan; + struct nvkm_gpuobj *ramfc = &base->base.gpuobj; + u64 usermem, ioffset, ilength; + u32 engines; + int ret, i; + + nvif_ioctl(parent, "create channel gpfifo size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx" + "ioffset %016llx ilength %08x engine %08x\n", + args->v0.version, args->v0.vm, args->v0.ioffset, + args->v0.ilength, args->v0.engine); + if (args->v0.vm) + return -ENOENT; + } else + return ret; + + for (i = 0, engines = 0; i < FIFO_ENGINE_NR; i++) { + if (!nvkm_engine(parent, fifo_engine[i].subdev)) + continue; + engines |= (1 << i); + } + + if (!args->v0.engine) { + static struct nvkm_oclass oclass = { + .ofuncs = &nvkm_object_ofuncs, + }; + args->v0.engine = engines; + return nvkm_object_old(parent, engine, &oclass, NULL, 0, pobject); + } + + engines &= args->v0.engine; + if (!engines) { + nvif_ioctl(parent, "unsupported engines %08x\n", + args->v0.engine); + return -ENODEV; + } + i = __ffs(engines); + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, + fifo->user.bar.offset, 0x200, 0, + fifo_engine[i].mask, &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->base.inst = base->base.gpuobj.addr; + args->v0.chid = chan->base.chid; + + nv_parent(chan)->context_attach = gk104_fifo_context_attach; + nv_parent(chan)->context_detach = gk104_fifo_context_detach; + chan->engine = i; + + usermem = chan->base.chid * 0x200; + ioffset = args->v0.ioffset; + ilength = order_base_2(args->v0.ilength / 8); + + nvkm_kmap(fifo->user.mem); + for (i = 0; i < 0x200; i += 4) + nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); + nvkm_done(fifo->user.mem); + usermem = nvkm_memory_addr(fifo->user.mem) + usermem; + + nvkm_kmap(ramfc); + nvkm_wo32(ramfc, 0x08, lower_32_bits(usermem)); + nvkm_wo32(ramfc, 0x0c, upper_32_bits(usermem)); + nvkm_wo32(ramfc, 0x10, 0x0000face); + nvkm_wo32(ramfc, 0x30, 0xfffff902); + nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); + nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); + nvkm_wo32(ramfc, 0x84, 0x20400000); + nvkm_wo32(ramfc, 0x94, 0x30000001); + nvkm_wo32(ramfc, 0x9c, 0x00000100); + nvkm_wo32(ramfc, 0xac, 0x0000001f); + nvkm_wo32(ramfc, 0xe8, chan->base.chid); + nvkm_wo32(ramfc, 0xb8, 0xf8000000); + nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ + nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ + nvkm_done(ramfc); + return 0; +} + +struct nvkm_ofuncs +gk104_fifo_chan_ofuncs = { + .ctor = gk104_fifo_chan_ctor, + .dtor = _nvkm_fifo_channel_dtor, + .init = gk104_fifo_chan_init, + .fini = gk104_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; + +struct nvkm_oclass +gk104_fifo_sclass[] = { + { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, + {} +}; + +static int +gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_device *device = nv_engine(engine)->subdev.device; + struct gk104_fifo_base *base; + int ret; + + ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, + 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); + *pobject = nv_object(base); + if (ret) + return ret; + + ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd); + if (ret) + return ret; + + nvkm_kmap(&base->base.gpuobj); + nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); + nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); + nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); + nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); + nvkm_done(&base->base.gpuobj); + + ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); + if (ret) + return ret; + + return 0; +} + +static void +gk104_fifo_context_dtor(struct nvkm_object *object) +{ + struct gk104_fifo_base *base = (void *)object; + nvkm_vm_ref(NULL, &base->vm, base->pgd); + nvkm_gpuobj_del(&base->pgd); + nvkm_fifo_context_destroy(&base->base); +} + +struct nvkm_oclass +gk104_fifo_cclass = { + .handle = NV_ENGCTX(FIFO, 0xe0), + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_fifo_context_ctor, + .dtor = gk104_fifo_context_dtor, + .init = _nvkm_fifo_context_init, + .fini = _nvkm_fifo_context_fini, + .rd32 = _nvkm_fifo_context_rd32, + .wr32 = _nvkm_fifo_context_wr32, + }, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c new file mode 100644 index 000000000000..7beee1f8729a --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c @@ -0,0 +1,32 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "changk104.h" + +#include + +struct nvkm_oclass +gm204_fifo_sclass[] = { + { MAXWELL_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, + {} +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c new file mode 100644 index 000000000000..ca7de9a6d67f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c @@ -0,0 +1,110 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "channv50.h" + +#include +#include + +#include +#include + +static int +nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + union { + struct nv50_channel_gpfifo_v0 v0; + } *args = data; + struct nvkm_device *device = parent->engine->subdev.device; + struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo_chan *chan; + u64 ioffset, ilength; + int ret; + + nvif_ioctl(parent, "create channel gpfifo size %d\n", size); + if (nvif_unpack(args->v0, 0, 0, false)) { + nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " + "pushbuf %llx ioffset %016llx " + "ilength %08x\n", + args->v0.version, args->v0.vm, args->v0.pushbuf, + args->v0.ioffset, args->v0.ilength); + if (args->v0.vm) + return -ENOENT; + } else + return ret; + + ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, + 0x2000, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), &chan); + *pobject = nv_object(chan); + if (ret) + return ret; + + chan->base.inst = base->base.gpuobj.addr; + args->v0.chid = chan->base.chid; + + nv_parent(chan)->context_attach = nv50_fifo_context_attach; + nv_parent(chan)->context_detach = nv50_fifo_context_detach; + nv_parent(chan)->object_attach = nv50_fifo_object_attach; + nv_parent(chan)->object_detach = nv50_fifo_object_detach; + + ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, + &chan->ramht); + if (ret) + return ret; + + ioffset = args->v0.ioffset; + ilength = order_base_2(args->v0.ilength / 8); + + nvkm_kmap(base->ramfc); + nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); + nvkm_wo32(base->ramfc, 0x44, 0x01003fff); + nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); + nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); + nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); + nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(base->ramfc, 0x78, 0x00000000); + nvkm_wo32(base->ramfc, 0x7c, 0x30000001); + nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + (4 << 24) /* SEARCH_FULL */ | + (chan->ramht->gpuobj->node->offset >> 4)); + nvkm_done(base->ramfc); + return 0; +} + +struct nvkm_ofuncs +nv50_fifo_ofuncs_ind = { + .ctor = nv50_fifo_chan_ctor_ind, + .dtor = nv50_fifo_chan_dtor, + .init = nv50_fifo_chan_init, + .fini = nv50_fifo_chan_fini, + .map = _nvkm_fifo_channel_map, + .rd32 = _nvkm_fifo_channel_rd32, + .wr32 = _nvkm_fifo_channel_wr32, + .ntfy = _nvkm_fifo_channel_ntfy +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index 8bdb71f5f1c5..d880cfa6de9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -22,18 +22,15 @@ * Authors: Ben Skeggs */ #include "nv04.h" +#include "channv04.h" +#include "regsnv04.h" -#include -#include #include #include #include #include #include -#include -#include - static struct ramfc_desc nv04_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, @@ -47,268 +44,6 @@ nv04_ramfc[] = { {} }; -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ - -int -nv04_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) -{ - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - u32 context, chid = chan->base.chid; - int ret; - - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->addr >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW: - context |= 0x00000000; - break; - case NVDEV_ENGINE_GR: - context |= 0x00010000; - break; - case NVDEV_ENGINE_MPEG: - context |= 0x00020000; - break; - default: - return -EINVAL; - } - } - - context |= 0x80000000; /* valid */ - context |= chid << 24; - - mutex_lock(&nv_subdev(fifo)->mutex); - ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context); - mutex_unlock(&nv_subdev(fifo)->mutex); - return ret; -} - -void -nv04_fifo_object_detach(struct nvkm_object *parent, int cookie) -{ - struct nv04_fifo *fifo = (void *)parent->engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - mutex_lock(&nv_subdev(fifo)->mutex); - nvkm_ramht_remove(imem->ramht, cookie); - mutex_unlock(&nv_subdev(fifo)->mutex); -} - -int -nv04_fifo_context_attach(struct nvkm_object *parent, - struct nvkm_object *object) -{ - nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid; - return 0; -} - -static int -nv04_fifo_chan_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv03_channel_dma_v0 v0; - } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; - int ret; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " - "offset %08x\n", args->v0.version, - args->v0.pushbuf, args->v0.offset); - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - args->v0.chid = chan->base.chid; - - nv_parent(chan)->object_attach = nv04_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - nv_parent(chan)->context_attach = nv04_fifo_context_attach; - chan->ramfc = chan->base.chid * 32; - - nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, - NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nvkm_done(imem->ramfc); - return 0; -} - -void -nv04_fifo_chan_dtor(struct nvkm_object *object) -{ - struct nv04_fifo *fifo = (void *)object->engine; - struct nv04_fifo_chan *chan = (void *)object; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct ramfc_desc *c = fifo->ramfc_desc; - - nvkm_kmap(imem->ramfc); - do { - nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); - } while ((++c)->bits); - nvkm_done(imem->ramfc); - - nvkm_fifo_channel_destroy(&chan->base); -} - -int -nv04_fifo_chan_init(struct nvkm_object *object) -{ - struct nv04_fifo *fifo = (void *)object->engine; - struct nv04_fifo_chan *chan = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 mask = 1 << chan->base.chid; - unsigned long flags; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - - spin_lock_irqsave(&fifo->base.lock, flags); - nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); - spin_unlock_irqrestore(&fifo->base.lock, flags); - return 0; -} - -int -nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) -{ - struct nv04_fifo *fifo = (void *)object->engine; - struct nv04_fifo_chan *chan = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_memory *fctx = device->imem->ramfc; - struct ramfc_desc *c; - unsigned long flags; - u32 data = chan->ramfc; - u32 chid; - - /* prevent fifo context switches */ - spin_lock_irqsave(&fifo->base.lock, flags); - nvkm_wr32(device, NV03_PFIFO_CACHES, 0); - - /* if this channel is active, replace it with a null context */ - chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max; - if (chid == chan->base.chid) { - nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); - nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); - - c = fifo->ramfc_desc; - do { - u32 rm = ((1ULL << c->bits) - 1) << c->regs; - u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; - u32 rv = (nvkm_rd32(device, c->regp) & rm) >> c->regs; - u32 cv = (nvkm_ro32(fctx, c->ctxp + data) & ~cm); - nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); - } while ((++c)->bits); - - c = fifo->ramfc_desc; - do { - nvkm_wr32(device, c->regp, 0x00000000); - } while ((++c)->bits); - - nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); - nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); - } - - /* restore normal operation, after disabling dma mode */ - nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); - nvkm_wr32(device, NV03_PFIFO_CACHES, 1); - spin_unlock_irqrestore(&fifo->base.lock, flags); - - return nvkm_fifo_channel_fini(&chan->base, suspend); -} - -static struct nvkm_ofuncs -nv04_fifo_ofuncs = { - .ctor = nv04_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -nv04_fifo_sclass[] = { - { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, - {} -}; - -/******************************************************************************* - * FIFO context - basically just the instmem reserved for the channel - ******************************************************************************/ - -int -nv04_fifo_context_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv04_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - return 0; -} - -static struct nvkm_oclass -nv04_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fifo_context_ctor, - .dtor = _nvkm_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; - -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ - void nv04_fifo_pause(struct nvkm_fifo *obj, unsigned long *pflags) __acquires(fifo->base.lock) @@ -552,36 +287,6 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); } -static int -nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv04_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv04_fifo_cclass; - nv_engine(fifo)->sclass = nv04_fifo_sclass; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv04_ramfc; - return 0; -} - -void -nv04_fifo_dtor(struct nvkm_object *object) -{ - struct nv04_fifo *fifo = (void *)object; - nvkm_fifo_destroy(&fifo->base); -} - int nv04_fifo_init(struct nvkm_object *object) { @@ -617,6 +322,36 @@ nv04_fifo_init(struct nvkm_object *object) return 0; } +void +nv04_fifo_dtor(struct nvkm_object *object) +{ + struct nv04_fifo *fifo = (void *)object; + nvkm_fifo_destroy(&fifo->base); +} + +static int +nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nv04_fifo *fifo; + int ret; + + ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &fifo); + *pobject = nv_object(fifo); + if (ret) + return ret; + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv04_fifo_cclass; + nv_engine(fifo)->sclass = nv04_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv04_ramfc; + return 0; +} + struct nvkm_oclass * nv04_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x04), diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index c7ce656eca7b..5cde3310ee4d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -1,135 +1,6 @@ #ifndef __NV04_FIFO_H__ #define __NV04_FIFO_H__ -#include - -#define NV04_PFIFO_DELAY_0 0x00002040 -#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 -#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 -#define NV03_PFIFO_INTR_0 0x00002100 -#define NV03_PFIFO_INTR_EN_0 0x00002140 -# define NV_PFIFO_INTR_CACHE_ERROR (1<<0) -# define NV_PFIFO_INTR_RUNOUT (1<<4) -# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) -# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) -# define NV_PFIFO_INTR_DMA_PT (1<<16) -# define NV_PFIFO_INTR_SEMAPHORE (1<<20) -# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) -#define NV03_PFIFO_RAMHT 0x00002210 -#define NV03_PFIFO_RAMFC 0x00002214 -#define NV03_PFIFO_RAMRO 0x00002218 -#define NV40_PFIFO_RAMFC 0x00002220 -#define NV03_PFIFO_CACHES 0x00002500 -#define NV04_PFIFO_MODE 0x00002504 -#define NV04_PFIFO_DMA 0x00002508 -#define NV04_PFIFO_SIZE 0x0000250c -#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) -#define NV50_PFIFO_CTX_TABLE__SIZE 128 -#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) -#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) -#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF -#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF -#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 -#define NV03_PFIFO_CACHE0_PULL0 0x00003040 -#define NV04_PFIFO_CACHE0_PULL0 0x00003050 -#define NV04_PFIFO_CACHE0_PULL1 0x00003054 -#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 -#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 -#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) -#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) -#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f -#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f -#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f -#define NV03_PFIFO_CACHE1_PUT 0x00003210 -#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 -#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 -# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 -# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 -# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 -# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 -# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF -# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 -#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 -#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c -#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 -#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 -#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 -#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 -#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C -#define NV03_PFIFO_CACHE1_PULL0 0x00003240 -#define NV04_PFIFO_CACHE1_PULL0 0x00003250 -# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 -# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 -#define NV03_PFIFO_CACHE1_PULL1 0x00003250 -#define NV04_PFIFO_CACHE1_PULL1 0x00003254 -#define NV04_PFIFO_CACHE1_HASH 0x00003258 -#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 -#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 -#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 -#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C -#define NV03_PFIFO_CACHE1_GET 0x00003270 -#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 -#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 -#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 -#define NV40_PFIFO_UNK32E4 0x000032E4 -#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) -#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) -#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) -#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) +#include "priv.h" struct ramfc_desc { unsigned bits:6; @@ -148,25 +19,10 @@ struct nv04_fifo_base { struct nvkm_fifo_base base; }; -struct nv04_fifo_chan { - struct nvkm_fifo_chan base; - u32 subc[8]; - u32 ramfc; -}; - -int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); -void nv04_fifo_object_detach(struct nvkm_object *, int); - -void nv04_fifo_chan_dtor(struct nvkm_object *); -int nv04_fifo_chan_init(struct nvkm_object *); -int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend); - int nv04_fifo_context_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); void nv04_fifo_dtor(struct nvkm_object *); int nv04_fifo_init(struct nvkm_object *); -void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); -void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index 734c3a767873..ae0a1b17eb92 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -22,13 +22,8 @@ * Authors: Ben Skeggs */ #include "nv04.h" - -#include -#include -#include - -#include -#include +#include "channv04.h" +#include "regsnv04.h" static struct ramfc_desc nv10_ramfc[] = { @@ -44,85 +39,6 @@ nv10_ramfc[] = { {} }; -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ - -static int -nv10_fifo_chan_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv03_channel_dma_v0 v0; - } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; - int ret; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " - "offset %08x\n", args->v0.version, - args->v0.pushbuf, args->v0.offset); - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - args->v0.chid = chan->base.chid; - - nv_parent(chan)->object_attach = nv04_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - nv_parent(chan)->context_attach = nv04_fifo_context_attach; - chan->ramfc = chan->base.chid * 32; - - nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, - NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nvkm_done(imem->ramfc); - return 0; -} - -static struct nvkm_ofuncs -nv10_fifo_ofuncs = { - .ctor = nv10_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -nv10_fifo_sclass[] = { - { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, - {} -}; - -/******************************************************************************* - * FIFO context - basically just the instmem reserved for the channel - ******************************************************************************/ - static struct nvkm_oclass nv10_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x10), @@ -136,10 +52,6 @@ nv10_fifo_cclass = { }, }; -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ - static int nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index e27180435bff..ff2b6d95d804 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -22,15 +22,12 @@ * Authors: Ben Skeggs */ #include "nv04.h" +#include "channv04.h" +#include "regsnv04.h" -#include -#include #include #include -#include -#include - static struct ramfc_desc nv17_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, @@ -50,87 +47,6 @@ nv17_ramfc[] = { {} }; -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ - -static int -nv17_fifo_chan_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv03_channel_dma_v0 v0; - } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; - int ret; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " - "offset %08x\n", args->v0.version, - args->v0.pushbuf, args->v0.offset); - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ - &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - args->v0.chid = chan->base.chid; - - nv_parent(chan)->object_attach = nv04_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - nv_parent(chan)->context_attach = nv04_fifo_context_attach; - chan->ramfc = chan->base.chid * 64; - - nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, - NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nvkm_done(imem->ramfc); - return 0; -} - -static struct nvkm_ofuncs -nv17_fifo_ofuncs = { - .ctor = nv17_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -nv17_fifo_sclass[] = { - { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, - {} -}; - -/******************************************************************************* - * FIFO context - basically just the instmem reserved for the channel - ******************************************************************************/ - static struct nvkm_oclass nv17_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x17), @@ -144,33 +60,6 @@ nv17_fifo_cclass = { }, }; -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ - -static int -nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv04_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv17_fifo_cclass; - nv_engine(fifo)->sclass = nv17_fifo_sclass; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv17_ramfc; - return 0; -} - static int nv17_fifo_init(struct nvkm_object *object) { @@ -207,6 +96,29 @@ nv17_fifo_init(struct nvkm_object *object) return 0; } +static int +nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nv04_fifo *fifo; + int ret; + + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); + *pobject = nv_object(fifo); + if (ret) + return ret; + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv17_fifo_cclass; + nv_engine(fifo)->sclass = nv17_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv17_ramfc; + return 0; +} + struct nvkm_oclass * nv17_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x17), diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index f2f0e3d74493..64be69fc9572 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -22,16 +22,13 @@ * Authors: Ben Skeggs */ #include "nv04.h" +#include "channv04.h" +#include "regsnv04.h" -#include -#include #include #include #include -#include -#include - static struct ramfc_desc nv40_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, @@ -59,207 +56,6 @@ nv40_ramfc[] = { {} }; -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ - -static int -nv40_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) -{ - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - u32 context, chid = chan->base.chid; - int ret; - - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->addr >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW: - context |= 0x00000000; - break; - case NVDEV_ENGINE_GR: - context |= 0x00100000; - break; - case NVDEV_ENGINE_MPEG: - context |= 0x00200000; - break; - default: - return -EINVAL; - } - } - - context |= chid << 23; - - mutex_lock(&nv_subdev(fifo)->mutex); - ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context); - mutex_unlock(&nv_subdev(fifo)->mutex); - return ret; -} - -static int -nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) -{ - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; - struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_instmem *imem = device->imem; - unsigned long flags; - u32 reg, ctx; - - switch (nv_engidx(engctx->engine)) { - case NVDEV_ENGINE_SW: - return 0; - case NVDEV_ENGINE_GR: - reg = 0x32e0; - ctx = 0x38; - break; - case NVDEV_ENGINE_MPEG: - reg = 0x330c; - ctx = 0x54; - break; - default: - return -EINVAL; - } - - spin_lock_irqsave(&fifo->base.lock, flags); - nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; - nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); - - if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid) - nvkm_wr32(device, reg, nv_engctx(engctx)->addr); - nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); - nvkm_done(imem->ramfc); - - nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&fifo->base.lock, flags); - return 0; -} - -static int -nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *engctx) -{ - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; - struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_instmem *imem = device->imem; - unsigned long flags; - u32 reg, ctx; - - switch (nv_engidx(engctx->engine)) { - case NVDEV_ENGINE_SW: - return 0; - case NVDEV_ENGINE_GR: - reg = 0x32e0; - ctx = 0x38; - break; - case NVDEV_ENGINE_MPEG: - reg = 0x330c; - ctx = 0x54; - break; - default: - return -EINVAL; - } - - spin_lock_irqsave(&fifo->base.lock, flags); - nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); - - if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid) - nvkm_wr32(device, reg, 0x00000000); - nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); - nvkm_done(imem->ramfc); - - nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&fifo->base.lock, flags); - return 0; -} - -static int -nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv03_channel_dma_v0 v0; - } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; - int ret; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " - "offset %08x\n", args->v0.version, - args->v0.pushbuf, args->v0.offset); - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x1000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = nv40_fifo_context_attach; - nv_parent(chan)->context_detach = nv40_fifo_context_detach; - nv_parent(chan)->object_attach = nv40_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - chan->ramfc = chan->base.chid * 128; - - nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | - NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | - NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | -#ifdef __BIG_ENDIAN - NV_PFIFO_CACHE1_BIG_ENDIAN | -#endif - NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); - nvkm_done(imem->ramfc); - return 0; -} - -static struct nvkm_ofuncs -nv40_fifo_ofuncs = { - .ctor = nv40_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -nv40_fifo_sclass[] = { - { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, - {} -}; - -/******************************************************************************* - * FIFO context - basically just the instmem reserved for the channel - ******************************************************************************/ - static struct nvkm_oclass nv40_fifo_cclass = { .handle = NV_ENGCTX(FIFO, 0x40), @@ -273,33 +69,6 @@ nv40_fifo_cclass = { }, }; -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ - -static int -nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv04_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv40_fifo_cclass; - nv_engine(fifo)->sclass = nv40_fifo_sclass; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv40_ramfc; - return 0; -} - static int nv40_fifo_init(struct nvkm_object *object) { @@ -357,6 +126,29 @@ nv40_fifo_init(struct nvkm_object *object) return 0; } +static int +nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nv04_fifo *fifo; + int ret; + + ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); + *pobject = nv_object(fifo); + if (ret) + return ret; + + nv_subdev(fifo)->unit = 0x00000100; + nv_subdev(fifo)->intr = nv04_fifo_intr; + nv_engine(fifo)->cclass = &nv40_fifo_cclass; + nv_engine(fifo)->sclass = nv40_fifo_sclass; + fifo->base.pause = nv04_fifo_pause; + fifo->base.start = nv04_fifo_start; + fifo->ramfc_desc = nv40_ramfc; + return 0; +} + struct nvkm_oclass * nv40_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x40), diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index 23d5ee2fed85..bf17cb0e8385 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -22,30 +22,17 @@ * Authors: Ben Skeggs */ #include "nv50.h" -#include "nv04.h" - -#include -#include -#include -#include -#include - -#include -#include - -/******************************************************************************* - * FIFO channel objects - ******************************************************************************/ +#include "channv50.h" static void -nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo) +nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) { struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_memory *cur; int i, p; - cur = fifo->playlist[fifo->cur_playlist]; - fifo->cur_playlist = !fifo->cur_playlist; + cur = fifo->runlist[fifo->cur_runlist]; + fifo->cur_runlist = !fifo->cur_runlist; nvkm_kmap(cur); for (i = fifo->base.min, p = 0; i < fifo->base.max; i++) { @@ -60,414 +47,52 @@ nv50_fifo_playlist_update_locked(struct nv50_fifo *fifo) } void -nv50_fifo_playlist_update(struct nv50_fifo *fifo) +nv50_fifo_runlist_update(struct nv50_fifo *fifo) { mutex_lock(&nv_subdev(fifo)->mutex); - nv50_fifo_playlist_update_locked(fifo); + nv50_fifo_runlist_update_locked(fifo); mutex_unlock(&nv_subdev(fifo)->mutex); } -static int -nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) -{ - struct nv50_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *ectx = (void *)object; - u64 limit = ectx->addr + ectx->size - 1; - u64 start = ectx->addr; - u32 addr; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0000; break; - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - default: - return -EINVAL; - } - - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00190000); - nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); - nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | - upper_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); - return 0; -} - -static int -nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) -{ - struct nv50_fifo *fifo = (void *)parent->engine; - struct nv50_fifo_base *base = (void *)parent->parent; - struct nv50_fifo_chan *chan = (void *)parent; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 addr, me; - int ret = 0; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0000; break; - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - default: - return -EINVAL; - } - - /* HW bug workaround: - * - * PFIFO will hang forever if the connected engines don't report - * that they've processed the context switch request. - * - * In order for the kickoff to work, we need to ensure all the - * connected engines are in a state where they can answer. - * - * Newer chipsets don't seem to suffer from this issue, and well, - * there's also a "ignore these engines" bitmask reg we can use - * if we hit the issue there.. - */ - me = nvkm_mask(device, 0x00b860, 0x00000001, 0x00000001); - - /* do the kickoff... */ - nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); - if (nvkm_msec(device, 2000, - if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) - break; - ) < 0) { - nvkm_error(subdev, "channel %d [%s] unload timeout\n", - chan->base.chid, nvkm_client_name(chan)); - if (suspend) - ret = -EBUSY; - } - nvkm_wr32(device, 0x00b860, me); - - if (ret == 0) { - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00000000); - nvkm_wo32(base->eng, addr + 0x04, 0x00000000); - nvkm_wo32(base->eng, addr + 0x08, 0x00000000); - nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); - } - - return ret; -} - -static int -nv50_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) -{ - struct nv50_fifo_chan *chan = (void *)parent; - u32 context; - - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->node->offset >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context |= 0x00000000; break; - case NVDEV_ENGINE_GR : context |= 0x00100000; break; - case NVDEV_ENGINE_MPEG : context |= 0x00200000; break; - default: - return -EINVAL; - } - } - - return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); -} - -void -nv50_fifo_object_detach(struct nvkm_object *parent, int cookie) -{ - struct nv50_fifo_chan *chan = (void *)parent; - nvkm_ramht_remove(chan->ramht, cookie); -} - -static int -nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv50_channel_dma_v0 v0; - } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; - struct nv50_fifo_chan *chan; - int ret; - - nvif_ioctl(parent, "create channel dma size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " - "offset %016llx\n", args->v0.version, - args->v0.pushbuf, args->v0.offset); - if (args->v0.vm) - return -ENOENT; - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = nv50_fifo_context_attach; - nv_parent(chan)->context_detach = nv50_fifo_context_detach; - nv_parent(chan)->object_attach = nv50_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; - - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); - if (ret) - return ret; - - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | - (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_done(base->ramfc); - return 0; -} - -static int -nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - union { - struct nv50_channel_gpfifo_v0 v0; - } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; - struct nv50_fifo_chan *chan; - u64 ioffset, ilength; - int ret; - - nvif_ioctl(parent, "create channel gpfifo size %d\n", size); - if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %llx " - "ioffset %016llx ilength %08x\n", - args->v0.version, args->v0.pushbuf, args->v0.ioffset, - args->v0.ilength); - if (args->v0.vm) - return -ENOENT; - } else - return ret; - - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = nv50_fifo_context_attach; - nv_parent(chan)->context_detach = nv50_fifo_context_detach; - nv_parent(chan)->object_attach = nv50_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; - - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); - if (ret) - return ret; - - ioffset = args->v0.ioffset; - ilength = order_base_2(args->v0.ilength / 8); - - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); - nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | - (4 << 24) /* SEARCH_FULL */ | - (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_done(base->ramfc); - return 0; -} - -void -nv50_fifo_chan_dtor(struct nvkm_object *object) -{ - struct nv50_fifo_chan *chan = (void *)object; - nvkm_ramht_del(&chan->ramht); - nvkm_fifo_channel_destroy(&chan->base); -} - -static int -nv50_fifo_chan_init(struct nvkm_object *object) -{ - struct nv50_fifo *fifo = (void *)object->engine; - struct nv50_fifo_base *base = (void *)object->parent; - struct nv50_fifo_chan *chan = (void *)object; - struct nvkm_gpuobj *ramfc = base->ramfc; - struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - - nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); - nv50_fifo_playlist_update(fifo); - return 0; -} - int -nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) +nv50_fifo_init(struct nvkm_object *object) { - struct nv50_fifo *fifo = (void *)object->engine; - struct nv50_fifo_chan *chan = (void *)object; + struct nv50_fifo *fifo = (void *)object; struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - - /* remove channel from playlist, fifo will unload context */ - nvkm_mask(device, 0x002600 + (chid * 4), 0x80000000, 0x00000000); - nv50_fifo_playlist_update(fifo); - nvkm_wr32(device, 0x002600 + (chid * 4), 0x00000000); - - return nvkm_fifo_channel_fini(&chan->base, suspend); -} - -static struct nvkm_ofuncs -nv50_fifo_ofuncs_dma = { - .ctor = nv50_fifo_chan_ctor_dma, - .dtor = nv50_fifo_chan_dtor, - .init = nv50_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_ofuncs -nv50_fifo_ofuncs_ind = { - .ctor = nv50_fifo_chan_ctor_ind, - .dtor = nv50_fifo_chan_dtor, - .init = nv50_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -static struct nvkm_oclass -nv50_fifo_sclass[] = { - { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, - { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, - {} -}; - -/******************************************************************************* - * FIFO context - basically just the instmem reserved for the channel - ******************************************************************************/ - -static int -nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct nv50_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); - if (ret) - return ret; + int ret, i; - ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, &base->base.gpuobj, - &base->ramfc); + ret = nvkm_fifo_init(&fifo->base); if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x1200, 0, true, &base->base.gpuobj, - &base->eng); - if (ret) - return ret; + nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); + nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); + nvkm_wr32(device, 0x00250c, 0x6f3cfc34); + nvkm_wr32(device, 0x002044, 0x01003fff); - ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, - &base->pgd); - if (ret) - return ret; + nvkm_wr32(device, 0x002100, 0xffffffff); + nvkm_wr32(device, 0x002140, 0xbfffffff); - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); - if (ret) - return ret; + for (i = 0; i < 128; i++) + nvkm_wr32(device, 0x002600 + (i * 4), 0x00000000); + nv50_fifo_runlist_update_locked(fifo); + nvkm_wr32(device, 0x003200, 0x00000001); + nvkm_wr32(device, 0x003250, 0x00000001); + nvkm_wr32(device, 0x002500, 0x00000001); return 0; } void -nv50_fifo_context_dtor(struct nvkm_object *object) +nv50_fifo_dtor(struct nvkm_object *object) { - struct nv50_fifo_base *base = (void *)object; - nvkm_vm_ref(NULL, &base->vm, base->pgd); - nvkm_gpuobj_del(&base->pgd); - nvkm_gpuobj_del(&base->eng); - nvkm_gpuobj_del(&base->ramfc); - nvkm_gpuobj_del(&base->cache); - nvkm_fifo_context_destroy(&base->base); -} + struct nv50_fifo *fifo = (void *)object; -static struct nvkm_oclass -nv50_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x50), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fifo_context_ctor, - .dtor = nv50_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; + nvkm_memory_del(&fifo->runlist[1]); + nvkm_memory_del(&fifo->runlist[0]); -/******************************************************************************* - * PFIFO engine - ******************************************************************************/ + nvkm_fifo_destroy(&fifo->base); +} static int nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, @@ -484,12 +109,12 @@ nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->playlist[0]); + false, &fifo->runlist[0]); if (ret) return ret; ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->playlist[1]); + false, &fifo->runlist[1]); if (ret) return ret; @@ -502,46 +127,6 @@ nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } -void -nv50_fifo_dtor(struct nvkm_object *object) -{ - struct nv50_fifo *fifo = (void *)object; - - nvkm_memory_del(&fifo->playlist[1]); - nvkm_memory_del(&fifo->playlist[0]); - - nvkm_fifo_destroy(&fifo->base); -} - -int -nv50_fifo_init(struct nvkm_object *object) -{ - struct nv50_fifo *fifo = (void *)object; - struct nvkm_device *device = fifo->base.engine.subdev.device; - int ret, i; - - ret = nvkm_fifo_init(&fifo->base); - if (ret) - return ret; - - nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); - nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); - nvkm_wr32(device, 0x00250c, 0x6f3cfc34); - nvkm_wr32(device, 0x002044, 0x01003fff); - - nvkm_wr32(device, 0x002100, 0xffffffff); - nvkm_wr32(device, 0x002140, 0xbfffffff); - - for (i = 0; i < 128; i++) - nvkm_wr32(device, 0x002600 + (i * 4), 0x00000000); - nv50_fifo_playlist_update_locked(fifo); - - nvkm_wr32(device, 0x003200, 0x00000001); - nvkm_wr32(device, 0x003250, 0x00000001); - nvkm_wr32(device, 0x002500, 0x00000001); - return 0; -} - struct nvkm_oclass * nv50_fifo_oclass = &(struct nvkm_oclass) { .handle = NV_ENGINE(FIFO, 0x50), diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index 0c826153bac6..306593fc56bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -1,36 +1,14 @@ #ifndef __NV50_FIFO_H__ #define __NV50_FIFO_H__ -#include +#include "priv.h" struct nv50_fifo { struct nvkm_fifo base; - struct nvkm_memory *playlist[2]; - int cur_playlist; + struct nvkm_memory *runlist[2]; + int cur_runlist; }; -struct nv50_fifo_base { - struct nvkm_fifo_base base; - struct nvkm_gpuobj *ramfc; - struct nvkm_gpuobj *cache; - struct nvkm_gpuobj *eng; - struct nvkm_gpuobj *pgd; - struct nvkm_vm *vm; -}; - -struct nv50_fifo_chan { - struct nvkm_fifo_chan base; - u32 subc[8]; - struct nvkm_ramht *ramht; -}; - -void nv50_fifo_playlist_update(struct nv50_fifo *); - -void nv50_fifo_object_detach(struct nvkm_object *, int); -void nv50_fifo_chan_dtor(struct nvkm_object *); -int nv50_fifo_chan_fini(struct nvkm_object *, bool); - -void nv50_fifo_context_dtor(struct nvkm_object *); - void nv50_fifo_dtor(struct nvkm_object *); int nv50_fifo_init(struct nvkm_object *); +void nv50_fifo_runlist_update(struct nv50_fifo *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h new file mode 100644 index 000000000000..b202f7f9413d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -0,0 +1,8 @@ +#ifndef __NVKM_FIFO_PRIV_H__ +#define __NVKM_FIFO_PRIV_H__ +#include +#include + +void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); +void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h new file mode 100644 index 000000000000..92d56221197b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/regsnv04.h @@ -0,0 +1,132 @@ +#ifndef __NV04_FIFO_REGS_H__ +#define __NV04_FIFO_REGS_H__ + +#define NV04_PFIFO_DELAY_0 0x00002040 +#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 +#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 +#define NV03_PFIFO_INTR_0 0x00002100 +#define NV03_PFIFO_INTR_EN_0 0x00002140 +# define NV_PFIFO_INTR_CACHE_ERROR (1<<0) +# define NV_PFIFO_INTR_RUNOUT (1<<4) +# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) +# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) +# define NV_PFIFO_INTR_DMA_PT (1<<16) +# define NV_PFIFO_INTR_SEMAPHORE (1<<20) +# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) +#define NV03_PFIFO_RAMHT 0x00002210 +#define NV03_PFIFO_RAMFC 0x00002214 +#define NV03_PFIFO_RAMRO 0x00002218 +#define NV40_PFIFO_RAMFC 0x00002220 +#define NV03_PFIFO_CACHES 0x00002500 +#define NV04_PFIFO_MODE 0x00002504 +#define NV04_PFIFO_DMA 0x00002508 +#define NV04_PFIFO_SIZE 0x0000250c +#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) +#define NV50_PFIFO_CTX_TABLE__SIZE 128 +#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) +#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) +#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF +#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF +#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 +#define NV03_PFIFO_CACHE0_PULL0 0x00003040 +#define NV04_PFIFO_CACHE0_PULL0 0x00003050 +#define NV04_PFIFO_CACHE0_PULL1 0x00003054 +#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 +#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 +#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) +#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) +#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f +#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f +#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f +#define NV03_PFIFO_CACHE1_PUT 0x00003210 +#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 +#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 +# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 +# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 +# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 +# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 +# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF +# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 +#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 +#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c +#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 +#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 +#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 +#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 +#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C +#define NV03_PFIFO_CACHE1_PULL0 0x00003240 +#define NV04_PFIFO_CACHE1_PULL0 0x00003250 +# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 +# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 +#define NV03_PFIFO_CACHE1_PULL1 0x00003250 +#define NV04_PFIFO_CACHE1_PULL1 0x00003254 +#define NV04_PFIFO_CACHE1_HASH 0x00003258 +#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 +#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 +#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 +#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C +#define NV03_PFIFO_CACHE1_GET 0x00003270 +#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 +#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 +#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 +#define NV40_PFIFO_UNK32E4 0x000032E4 +#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) +#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) +#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) +#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index b15b86478c4f..e2d3d79ee37b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 8f0c62d56d9d..761aaa451e21 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -26,6 +26,7 @@ #include #include +#include #include struct pipe_state { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index a33ed6121d7f..262638b4e0c5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -3,6 +3,7 @@ #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index f0df11e47975..9cb5a90dde51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -2,6 +2,7 @@ #include "regs.h" #include +#include /******************************************************************************* * Graphics object classes diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index 3bc6dae76fa5..c5d8cd6d66c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -2,6 +2,7 @@ #include "regs.h" #include +#include /******************************************************************************* * PGRAPH context diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 3c369f4b09e1..733de46a30dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -2,6 +2,7 @@ #include "regs.h" #include +#include #include /******************************************************************************* diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 48bd9da606be..368c0cff35fb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -2,6 +2,7 @@ #include "regs.h" #include +#include /******************************************************************************* * Graphics object classes diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index d25d3303f2fd..676234d28e50 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -2,6 +2,7 @@ #include "regs.h" #include +#include /******************************************************************************* * Graphics object classes -- cgit v1.2.3 From 8f0649b5c6e70ec18122255690e39f010c12a614 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:19 +1000 Subject: drm/nouveau/fifo: convert user classes to new-style nvkm_object Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h | 3 - drivers/gpu/drm/nouveau/include/nvkm/core/engine.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/core/handle.h | 1 - drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h | 52 --- drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 60 +-- drivers/gpu/drm/nouveau/nv84_fence.c | 2 +- drivers/gpu/drm/nouveau/nvkm/core/Kbuild | 1 - drivers/gpu/drm/nouveau/nvkm/core/engctx.c | 75 +--- drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 10 + drivers/gpu/drm/nouveau/nvkm/core/handle.c | 52 +-- drivers/gpu/drm/nouveau/nvkm/core/ioctl.c | 2 +- drivers/gpu/drm/nouveau/nvkm/core/namedb.c | 201 --------- drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c | 7 +- .../gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c | 106 +---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 108 +++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 477 +++++++++++++++++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h | 44 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c | 327 ++++++++------ .../gpu/drm/nouveau/nvkm/engine/fifo/changf100.h | 25 +- .../gpu/drm/nouveau/nvkm/engine/fifo/changk104.h | 32 +- .../gpu/drm/nouveau/nvkm/engine/fifo/channv04.h | 24 +- .../gpu/drm/nouveau/nvkm/engine/fifo/channv50.c | 293 +++++++------ .../gpu/drm/nouveau/nvkm/engine/fifo/channv50.h | 47 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c | 102 ++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c | 216 ++++------ drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c | 61 ++- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c | 64 ++- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c | 240 ++++++----- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c | 88 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c | 13 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 61 ++- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h | 5 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 114 +++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 42 ++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c | 10 +- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c | 90 ++-- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c | 374 ++++++++-------- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 407 ++++++++---------- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c | 10 +- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c | 76 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 40 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h | 9 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 19 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 27 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 27 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 1 - drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 19 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 24 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 10 +- 61 files changed, 2025 insertions(+), 2121 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/core/namedb.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 78c6649407e6..d52ef8419fd2 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -64,6 +64,6 @@ u64 nvif_device_time(struct nvif_device *); #include #include -#define nvxx_fifo(a) nvkm_fifo(nvxx_device(a)) +#define nvxx_fifo(a) nvxx_device(a)->fifo #define nvxx_gr(a) nvkm_gr(nvxx_device(a)) #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h index dfa24d233321..4a77fdaa8b90 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engctx.h @@ -45,7 +45,4 @@ int _nvkm_engctx_init(struct nvkm_object *); int _nvkm_engctx_fini(struct nvkm_object *, bool suspend); #define _nvkm_engctx_rd32 _nvkm_gpuobj_rd32 #define _nvkm_engctx_wr32 _nvkm_gpuobj_wr32 - -struct nvkm_object *nvkm_engctx_get(struct nvkm_engine *, u64 addr); -void nvkm_engctx_put(struct nvkm_object *); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index 8c67d755e5c1..9d9c0e779f3f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -42,6 +42,7 @@ struct nvkm_engine_func { int (*sclass)(struct nvkm_oclass *, int index); } fifo; + const struct nvkm_object_func *cclass; struct nvkm_sclass sclass[]; }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h index 88e8bb17a280..539278916d23 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/handle.h @@ -4,7 +4,6 @@ struct nvkm_object; struct nvkm_handle { - struct nvkm_namedb *namedb; struct list_head node; struct list_head head; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h b/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h deleted file mode 100644 index 16337f69b113..000000000000 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/namedb.h +++ /dev/null @@ -1,52 +0,0 @@ -#ifndef __NVKM_NAMEDB_H__ -#define __NVKM_NAMEDB_H__ -#include -struct nvkm_handle; - -struct nvkm_namedb { - struct nvkm_parent parent; - rwlock_t lock; - struct list_head list; -}; - -static inline struct nvkm_namedb * -nv_namedb(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - BUG_ON(!nv_iclass(obj, NV_NAMEDB_CLASS)); -#endif - return obj; -} - -#define nvkm_namedb_create(p,e,c,v,s,m,d) \ - nvkm_namedb_create_((p), (e), (c), (v), (s), (m), \ - sizeof(**d), (void **)d) -#define nvkm_namedb_init(p) \ - nvkm_parent_init(&(p)->parent) -#define nvkm_namedb_fini(p,s) \ - nvkm_parent_fini(&(p)->parent, (s)) -#define nvkm_namedb_destroy(p) \ - nvkm_parent_destroy(&(p)->parent) - -int nvkm_namedb_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, u32 pclass, - struct nvkm_oclass *, u64 engcls, - int size, void **); - -int _nvkm_namedb_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -#define _nvkm_namedb_dtor _nvkm_parent_dtor -#define _nvkm_namedb_init _nvkm_parent_init -#define _nvkm_namedb_fini _nvkm_parent_fini - -int nvkm_namedb_insert(struct nvkm_namedb *, u32 name, struct nvkm_object *, - struct nvkm_handle *); -void nvkm_namedb_remove(struct nvkm_handle *); - -struct nvkm_handle *nvkm_namedb_get(struct nvkm_namedb *, u32); -struct nvkm_handle *nvkm_namedb_get_class(struct nvkm_namedb *, s32); -struct nvkm_handle *nvkm_namedb_get_vinst(struct nvkm_namedb *, u64); -struct nvkm_handle *nvkm_namedb_get_cinst(struct nvkm_namedb *, u32); -void nvkm_namedb_put(struct nvkm_handle *); -#endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index ac97072dcfef..d9e494ba5033 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -1,25 +1,39 @@ #ifndef __NVKM_FIFO_H__ #define __NVKM_FIFO_H__ -#include +#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object) +#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine) +#include +#include + +#define NVKM_FIFO_CHID_NR 4096 + +struct nvkm_fifo_engn { + struct nvkm_object *object; + int refcount; + int usecount; +}; struct nvkm_fifo_chan { - struct nvkm_namedb namedb; - struct nvkm_gpuobj *pushgpu; + const struct nvkm_fifo_chan_func *func; + struct nvkm_fifo *fifo; + u64 engines; + struct nvkm_object object; + + struct list_head head; + u16 chid; + struct nvkm_gpuobj *inst; + struct nvkm_gpuobj *push; + struct nvkm_vm *vm; void __iomem *user; u64 addr; u32 size; - u16 chid; - u64 inst; + + struct nvkm_fifo_engn engn[NVDEV_SUBDEV_NR]; }; -static inline struct nvkm_fifo_chan * -nvkm_fifo_chan(void *obj) -{ - return (void *)nv_namedb(obj); -} +extern const struct nvkm_object_func nvkm_fifo_chan_func; #include - struct nvkm_fifo_base { struct nvkm_gpuobj gpuobj; }; @@ -39,25 +53,27 @@ struct nvkm_fifo_base { #define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32 #define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32 -#include -#include - struct nvkm_fifo { struct nvkm_engine engine; + const struct nvkm_fifo_func *func; struct nvkm_event cevent; /* channel creation event */ struct nvkm_event uevent; /* async user trigger */ - struct nvkm_object **channel; + DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR); + int nr; + struct list_head chan; spinlock_t lock; - u16 min; - u16 max; - int (*chid)(struct nvkm_fifo *, struct nvkm_object *); void (*pause)(struct nvkm_fifo *, unsigned long *); void (*start)(struct nvkm_fifo *, unsigned long *); }; +struct nvkm_fifo_func { + void *(*dtor)(struct nvkm_fifo *); + const struct nvkm_fifo_chan_oclass *chan[]; +}; + void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags, struct nvkm_fifo_chan **); struct nvkm_fifo_chan * @@ -65,12 +81,6 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags); struct nvkm_fifo_chan * nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags); -static inline struct nvkm_fifo * -nvkm_fifo(void *obj) -{ - return (void *)nvkm_engine(obj, NVDEV_ENGINE_FIFO); -} - #define nvkm_fifo_create(o,e,c,fc,lc,d) \ nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) #define nvkm_fifo_init(p) \ @@ -82,8 +92,6 @@ int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, int min, int max, int size, void **); void nvkm_fifo_destroy(struct nvkm_fifo *); -const char * -nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid); #define _nvkm_fifo_init _nvkm_engine_init #define _nvkm_fifo_fini _nvkm_engine_fini diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index 4d7ad6d3fbd4..412c5be5a9ca 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c @@ -228,7 +228,7 @@ nv84_fence_create(struct nouveau_drm *drm) priv->base.context_new = nv84_fence_context_new; priv->base.context_del = nv84_fence_context_del; - priv->base.contexts = fifo->max + 1; + priv->base.contexts = fifo->nr; priv->base.context_base = fence_context_alloc(priv->base.contexts); priv->base.uevent = true; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild index e56c8eb9b054..d3932d59ff09 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/core/Kbuild @@ -8,7 +8,6 @@ nvkm-y += nvkm/core/handle.o nvkm-y += nvkm/core/ioctl.o nvkm-y += nvkm/core/memory.o nvkm-y += nvkm/core/mm.o -nvkm-y += nvkm/core/namedb.o nvkm-y += nvkm/core/notify.o nvkm-y += nvkm/core/object.o nvkm-y += nvkm/core/oproxy.o diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c index be640fd24f77..bd13facc53d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c @@ -124,58 +124,12 @@ nvkm_engctx_destroy(struct nvkm_engctx *engctx) int nvkm_engctx_init(struct nvkm_engctx *engctx) { - struct nvkm_object *object = nv_object(engctx); - struct nvkm_subdev *subdev = nv_subdev(object->engine); - struct nvkm_object *parent; - struct nvkm_subdev *pardev; - int ret; - - ret = nvkm_gpuobj_init(&engctx->gpuobj); - if (ret) - return ret; - - parent = nv_pclass(object->parent, NV_PARENT_CLASS); - pardev = nv_subdev(parent->engine); - if (nv_parent(parent)->context_attach) { - mutex_lock(&pardev->mutex); - ret = nv_parent(parent)->context_attach(parent, object); - mutex_unlock(&pardev->mutex); - } - - if (ret) { - nvkm_error(pardev, "failed to attach %s context, %d\n", - nvkm_subdev_name[subdev->index], ret); - return ret; - } - - nvkm_trace(pardev, "attached %s context\n", nvkm_subdev_name[subdev->index]); - return 0; + return nvkm_gpuobj_init(&engctx->gpuobj); } int nvkm_engctx_fini(struct nvkm_engctx *engctx, bool suspend) { - struct nvkm_object *object = nv_object(engctx); - struct nvkm_subdev *subdev = nv_subdev(object->engine); - struct nvkm_object *parent; - struct nvkm_subdev *pardev; - int ret = 0; - - parent = nv_pclass(object->parent, NV_PARENT_CLASS); - pardev = nv_subdev(parent->engine); - if (nv_parent(parent)->context_detach) { - mutex_lock(&pardev->mutex); - ret = nv_parent(parent)->context_detach(parent, suspend, object); - mutex_unlock(&pardev->mutex); - } - - if (ret) { - nvkm_error(pardev, "failed to detach %s context, %d\n", - nvkm_subdev_name[subdev->index], ret); - return ret; - } - - nvkm_trace(pardev, "detached %s context\n", nvkm_subdev_name[subdev->index]); return nvkm_gpuobj_fini(&engctx->gpuobj, suspend); } @@ -210,30 +164,3 @@ _nvkm_engctx_fini(struct nvkm_object *object, bool suspend) { return nvkm_engctx_fini(nv_engctx(object), suspend); } - -struct nvkm_object * -nvkm_engctx_get(struct nvkm_engine *engine, u64 addr) -{ - struct nvkm_engctx *engctx; - unsigned long flags; - - spin_lock_irqsave(&engine->lock, flags); - list_for_each_entry(engctx, &engine->contexts, head) { - if (engctx->addr == addr) { - engctx->save = flags; - return nv_object(engctx); - } - } - spin_unlock_irqrestore(&engine->lock, flags); - return NULL; -} - -void -nvkm_engctx_put(struct nvkm_object *object) -{ - if (object) { - struct nvkm_engine *engine = nv_engine(object->engine); - struct nvkm_engctx *engctx = nv_engctx(object); - spin_unlock_irqrestore(&engine->lock, engctx->save); - } -} diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index 54b46037f4ba..e056f7afc35c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -231,6 +231,8 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) nvkm_object_destroy(&gpuobj->object); } +#include + int nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pclass, @@ -240,11 +242,19 @@ nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_device *device = nv_device(parent); struct nvkm_gpuobj *pargpu = NULL; struct nvkm_gpuobj *gpuobj; + struct nvkm_object *object = objgpu; const bool zero = (flags & NVOBJ_FLAG_ZERO_ALLOC); int ret; *pobject = NULL; + while (object && object->func != &nvkm_fifo_chan_func) + object = object->parent; + + if (object) { + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + pargpu = chan->inst; + } else if (objgpu) { while ((objgpu = nv_pclass(objgpu, NV_GPUOBJ_CLASS))) { if (nv_gpuobj(objgpu)->heap.block_size) diff --git a/drivers/gpu/drm/nouveau/nvkm/core/handle.c b/drivers/gpu/drm/nouveau/nvkm/core/handle.c index 2b52a655309b..a74ee1c29f8c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/handle.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/handle.c @@ -23,7 +23,7 @@ */ #include #include -#include +#include #define hprintk(h,l,f,a...) do { \ struct nvkm_handle *p = (h)->parent; u32 n = p ? p->name : ~0; \ @@ -98,14 +98,9 @@ int nvkm_handle_create(struct nvkm_handle *parent, u32 _handle, struct nvkm_object *object, struct nvkm_handle **phandle) { - struct nvkm_object *namedb; struct nvkm_handle *handle; int ret; - namedb = parent ? parent->object : NULL; - while (namedb && !nv_iclass(namedb, NV_NAMEDB_CLASS)) - namedb = namedb->parent; - handle = kzalloc(sizeof(*handle), GFP_KERNEL); if (!handle) return -ENOMEM; @@ -118,15 +113,6 @@ nvkm_handle_create(struct nvkm_handle *parent, u32 _handle, handle->parent = parent; nvkm_object_ref(object, &handle->object); - if (namedb) { - ret = nvkm_namedb_insert(nv_namedb(namedb), _handle, - object, handle); - if (ret) { - kfree(handle); - return ret; - } - } - if (parent) { if (nv_iclass(parent->object, NV_PARENT_CLASS) && nv_parent(parent->object)->object_attach) { @@ -168,40 +154,6 @@ nvkm_handle_destroy(struct nvkm_handle *handle) } hprintk(handle, TRACE, "destroy completed\n"); - nvkm_namedb_remove(handle); + nvkm_object_ref(NULL, &handle->object); kfree(handle); } - -struct nvkm_handle * -nvkm_handle_get_class(struct nvkm_object *engctx, u16 oclass) -{ - struct nvkm_namedb *namedb; - if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) - return nvkm_namedb_get_class(namedb, oclass); - return NULL; -} - -struct nvkm_handle * -nvkm_handle_get_vinst(struct nvkm_object *engctx, u64 vinst) -{ - struct nvkm_namedb *namedb; - if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) - return nvkm_namedb_get_vinst(namedb, vinst); - return NULL; -} - -struct nvkm_handle * -nvkm_handle_get_cinst(struct nvkm_object *engctx, u32 cinst) -{ - struct nvkm_namedb *namedb; - if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) - return nvkm_namedb_get_cinst(namedb, cinst); - return NULL; -} - -void -nvkm_handle_put(struct nvkm_handle *handle) -{ - if (handle) - nvkm_namedb_put(handle); -} diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c index 04f1bc2d0f8e..28f9fa289e80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ioctl.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/core/namedb.c b/drivers/gpu/drm/nouveau/nvkm/core/namedb.c deleted file mode 100644 index 9be1ce967034..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/core/namedb.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include -#include -#include - -static struct nvkm_handle * -nvkm_namedb_lookup(struct nvkm_namedb *namedb, u32 name) -{ - struct nvkm_handle *handle; - - list_for_each_entry(handle, &namedb->list, node) { - if (handle->name == name) - return handle; - } - - return NULL; -} - -static struct nvkm_handle * -nvkm_namedb_lookup_class(struct nvkm_namedb *namedb, s32 oclass) -{ - struct nvkm_handle *handle; - - list_for_each_entry(handle, &namedb->list, node) { - if (nv_mclass(handle->object) == oclass) - return handle; - } - - return NULL; -} - -static struct nvkm_handle * -nvkm_namedb_lookup_vinst(struct nvkm_namedb *namedb, u64 vinst) -{ - struct nvkm_handle *handle; - - list_for_each_entry(handle, &namedb->list, node) { - if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { - if (nv_gpuobj(handle->object)->addr == vinst) - return handle; - } - } - - return NULL; -} - -static struct nvkm_handle * -nvkm_namedb_lookup_cinst(struct nvkm_namedb *namedb, u32 cinst) -{ - struct nvkm_handle *handle; - - list_for_each_entry(handle, &namedb->list, node) { - if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { - if (nv_gpuobj(handle->object)->node && - nv_gpuobj(handle->object)->node->offset == cinst) - return handle; - } - } - - return NULL; -} - -int -nvkm_namedb_insert(struct nvkm_namedb *namedb, u32 name, - struct nvkm_object *object, - struct nvkm_handle *handle) -{ - int ret = -EEXIST; - write_lock_irq(&namedb->lock); - if (!nvkm_namedb_lookup(namedb, name)) { - nvkm_object_ref(object, &handle->object); - handle->namedb = namedb; - list_add(&handle->node, &namedb->list); - ret = 0; - } - write_unlock_irq(&namedb->lock); - return ret; -} - -void -nvkm_namedb_remove(struct nvkm_handle *handle) -{ - struct nvkm_namedb *namedb = handle->namedb; - struct nvkm_object *object = handle->object; - if (handle->namedb) { - write_lock_irq(&namedb->lock); - list_del(&handle->node); - write_unlock_irq(&namedb->lock); - } - nvkm_object_ref(NULL, &object); -} - -struct nvkm_handle * -nvkm_namedb_get(struct nvkm_namedb *namedb, u32 name) -{ - struct nvkm_handle *handle; - read_lock(&namedb->lock); - handle = nvkm_namedb_lookup(namedb, name); - if (handle == NULL) - read_unlock(&namedb->lock); - return handle; -} - -struct nvkm_handle * -nvkm_namedb_get_class(struct nvkm_namedb *namedb, s32 oclass) -{ - struct nvkm_handle *handle; - read_lock(&namedb->lock); - handle = nvkm_namedb_lookup_class(namedb, oclass); - if (handle == NULL) - read_unlock(&namedb->lock); - return handle; -} - -struct nvkm_handle * -nvkm_namedb_get_vinst(struct nvkm_namedb *namedb, u64 vinst) -{ - struct nvkm_handle *handle; - read_lock(&namedb->lock); - handle = nvkm_namedb_lookup_vinst(namedb, vinst); - if (handle == NULL) - read_unlock(&namedb->lock); - return handle; -} - -struct nvkm_handle * -nvkm_namedb_get_cinst(struct nvkm_namedb *namedb, u32 cinst) -{ - struct nvkm_handle *handle; - read_lock(&namedb->lock); - handle = nvkm_namedb_lookup_cinst(namedb, cinst); - if (handle == NULL) - read_unlock(&namedb->lock); - return handle; -} - -void -nvkm_namedb_put(struct nvkm_handle *handle) -{ - if (handle) - read_unlock(&handle->namedb->lock); -} - -int -nvkm_namedb_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 pclass, - struct nvkm_oclass *sclass, u64 engcls, - int length, void **pobject) -{ - struct nvkm_namedb *namedb; - int ret; - - ret = nvkm_parent_create_(parent, engine, oclass, pclass | - NV_NAMEDB_CLASS, sclass, engcls, - length, pobject); - namedb = *pobject; - if (ret) - return ret; - - rwlock_init(&namedb->lock); - INIT_LIST_HEAD(&namedb->list); - return 0; -} - -int -_nvkm_namedb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_namedb *object; - int ret; - - ret = nvkm_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); - *pobject = nv_object(object); - if (ret) - return ret; - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index a632570f20e1..1a15b8d6fece 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -85,7 +85,8 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010llx %s] " "subc %d mthd %04x data %08x\n", ssta, en ? en->name : "", chan ? chan->chid : -1, - chan ? chan->inst : 0, nvkm_client_name(chan), + chan ? chan->inst->addr : 0, + chan ? chan->object.client->name : "unknown", subc, mthd, data); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index 62cdd1e50a95..74bea4397bf4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -121,9 +121,10 @@ g84_cipher_intr(struct nvkm_subdev *subdev) if (stat) { nvkm_snprintbf(msg, sizeof(msg), g84_cipher_intr_mask, stat); nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] " - "mthd %04x data %08x\n", - stat, msg, chan ? chan->chid : -1, (u64)inst << 12, - nvkm_client_name(chan), mthd, data); + "mthd %04x data %08x\n", stat, msg, + chan ? chan->chid : -1, (u64)inst << 12, + chan ? chan->object.client->name : "unknown", + mthd, data); } nvkm_fifo_chan_put(fifo, flags, &chan); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c index 2d9b81fb83a2..62d3fb66d0ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#define nv04_disp_root(p) container_of((p), struct nv04_disp_root, object); +#define nv04_disp_root(p) container_of((p), struct nv04_disp_root, object) #include "priv.h" #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c index 57f6eca078ef..1a377201949c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dma/base.c @@ -24,6 +24,7 @@ #include "priv.h" #include +#include #include @@ -88,11 +89,19 @@ nvkm_dma_oclass_base = { .ctor = nvkm_dma_oclass_new, }; +static int +nvkm_dma_oclass_fifo_new(const struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + return nvkm_dma_oclass_new(oclass->engine->subdev.device, + oclass, data, size, pobject); +} + static const struct nvkm_sclass nvkm_dma_sclass[] = { - { 0, 0, NV_DMA_FROM_MEMORY }, - { 0, 0, NV_DMA_TO_MEMORY }, - { 0, 0, NV_DMA_IN_MEMORY }, + { 0, 0, NV_DMA_FROM_MEMORY, NULL, nvkm_dma_oclass_fifo_new }, + { 0, 0, NV_DMA_TO_MEMORY, NULL, nvkm_dma_oclass_fifo_new }, + { 0, 0, NV_DMA_IN_MEMORY, NULL, nvkm_dma_oclass_fifo_new }, }; static int @@ -110,89 +119,21 @@ nvkm_dma_oclass_base_get(struct nvkm_oclass *sclass, int index, return count; } -static const struct nvkm_engine_func -nvkm_dma = { - .base.sclass = nvkm_dma_oclass_base_get, -}; - -#include - -static struct nvkm_oclass empty = { - .ofuncs = &(struct nvkm_ofuncs) { - .dtor = nvkm_object_destroy, - .init = _nvkm_object_init, - .fini = _nvkm_object_fini, - }, -}; - static int -nvkm_dmaobj_compat_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_oclass hack = { - .base.oclass = oclass->handle, - .client = nvkm_client(parent), - .parent = parent, - .engine = nv_engine(engine), - }; - struct nvkm_dma *dma = (void *)engine; - struct nvkm_dma_impl *impl = (void *)dma->engine.subdev.object.oclass; - struct nvkm_dmaobj *dmaobj = NULL; - struct nvkm_gpuobj *gpuobj; - int ret; - - ret = impl->class_new(dma, &hack, data, size, &dmaobj); - if (dmaobj) - *pobject = &dmaobj->object; - if (ret) - return ret; - - gpuobj = (void *)nv_pclass(parent, NV_GPUOBJ_CLASS); - - ret = dmaobj->func->bind(dmaobj, gpuobj, 16, &gpuobj); - nvkm_object_ref(NULL, pobject); - if (ret) - return ret; - - ret = nvkm_object_create(parent, engine, &empty, 0, pobject); - if (ret) - return ret; - - gpuobj->object.parent = *pobject; - gpuobj->object.engine = &dma->engine; - gpuobj->object.oclass = oclass; - gpuobj->object.pclass = NV_GPUOBJ_CLASS; -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - gpuobj->object._magic = NVKM_OBJECT_MAGIC; -#endif - *pobject = &gpuobj->object; - return 0; -} - -static void -nvkm_dmaobj_compat_dtor(struct nvkm_object *object) +nvkm_dma_oclass_fifo_get(struct nvkm_oclass *oclass, int index) { - struct nvkm_object *parent = object->parent; - struct nvkm_gpuobj *gpuobj = (void *)object; - nvkm_gpuobj_del(&gpuobj); - nvkm_object_ref(NULL, &parent); + const int count = ARRAY_SIZE(nvkm_dma_sclass); + if (index < count) { + oclass->base = nvkm_dma_sclass[index]; + return index; + } + return count; } -static struct nvkm_ofuncs -nvkm_dmaobj_compat_ofuncs = { - .ctor = nvkm_dmaobj_compat_ctor, - .dtor = nvkm_dmaobj_compat_dtor, - .init = _nvkm_object_init, - .fini = _nvkm_object_fini, -}; - -static struct nvkm_oclass -nvkm_dma_compat_sclass[] = { - { NV_DMA_FROM_MEMORY, &nvkm_dmaobj_compat_ofuncs }, - { NV_DMA_TO_MEMORY, &nvkm_dmaobj_compat_ofuncs }, - { NV_DMA_IN_MEMORY, &nvkm_dmaobj_compat_ofuncs }, - {} +static const struct nvkm_engine_func +nvkm_dma = { + .base.sclass = nvkm_dma_oclass_base_get, + .fifo.sclass = nvkm_dma_oclass_fifo_get, }; int @@ -209,7 +150,6 @@ _nvkm_dma_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - dmaeng->engine.sclass = nvkm_dma_compat_sclass; dmaeng->engine.func = &nvkm_dma; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index 510de3c2d2e4..b693127d80e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -44,12 +44,13 @@ nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags, struct nvkm_fifo_chan * nvkm_fifo_chan_inst(struct nvkm_fifo *fifo, u64 inst, unsigned long *rflags) { + struct nvkm_fifo_chan *chan; unsigned long flags; - int i; spin_lock_irqsave(&fifo->lock, flags); - for (i = fifo->min; i < fifo->max; i++) { - struct nvkm_fifo_chan *chan = (void *)fifo->channel[i]; - if (chan && chan->inst == inst) { + list_for_each_entry(chan, &fifo->chan, head) { + if (chan->inst->addr == inst) { + list_del(&chan->head); + list_add(&chan->head, &fifo->chan); *rflags = flags; return chan; } @@ -61,45 +62,21 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *fifo, u64 inst, unsigned long *rflags) struct nvkm_fifo_chan * nvkm_fifo_chan_chid(struct nvkm_fifo *fifo, int chid, unsigned long *rflags) { + struct nvkm_fifo_chan *chan; unsigned long flags; spin_lock_irqsave(&fifo->lock, flags); - if (fifo->channel[chid]) { - *rflags = flags; - return (void *)fifo->channel[chid]; + list_for_each_entry(chan, &fifo->chan, head) { + if (chan->chid == chid) { + list_del(&chan->head); + list_add(&chan->head, &fifo->chan); + *rflags = flags; + return chan; + } } spin_unlock_irqrestore(&fifo->lock, flags); return NULL; } -static int -nvkm_fifo_chid(struct nvkm_fifo *fifo, struct nvkm_object *object) -{ - int engidx = nv_hclass(fifo) & 0xff; - - while (object && object->parent) { - if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && - (nv_hclass(object->parent) & 0xff) == engidx) - return nvkm_fifo_chan(object)->chid; - object = object->parent; - } - - return -1; -} - -const char * -nvkm_client_name_for_fifo_chid(struct nvkm_fifo *fifo, u32 chid) -{ - struct nvkm_fifo_chan *chan = NULL; - unsigned long flags; - - spin_lock_irqsave(&fifo->lock, flags); - if (chid >= fifo->min && chid <= fifo->max) - chan = (void *)fifo->channel[chid]; - spin_unlock_irqrestore(&fifo->lock, flags); - - return nvkm_client_name(chan); -} - static int nvkm_fifo_event_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) @@ -144,21 +121,62 @@ nvkm_fifo_uevent(struct nvkm_fifo *fifo) nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep)); } +static int +nvkm_fifo_class_new(struct nvkm_device *device, + const struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + const struct nvkm_fifo_chan_oclass *sclass = oclass->engn; + struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); + return sclass->ctor(fifo, oclass, data, size, pobject); +} + +static const struct nvkm_device_oclass +nvkm_fifo_class = { + .ctor = nvkm_fifo_class_new, +}; + +static int +nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index, + const struct nvkm_device_oclass **class) +{ + struct nvkm_fifo *fifo = nvkm_fifo(oclass->engine); + const struct nvkm_fifo_chan_oclass *sclass; + int c = 0; + + while ((sclass = fifo->func->chan[c])) { + if (c++ == index) { + oclass->base = sclass->base; + oclass->engn = sclass; + *class = &nvkm_fifo_class; + return 0; + } + } + + return c; +} + void nvkm_fifo_destroy(struct nvkm_fifo *fifo) { - kfree(fifo->channel); nvkm_event_fini(&fifo->uevent); nvkm_event_fini(&fifo->cevent); nvkm_engine_destroy(&fifo->engine); } +static const struct nvkm_engine_func +nvkm_fifo_func = { + .base.sclass = nvkm_fifo_class_get, +}; + int nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int min, int max, int length, void **pobject) { struct nvkm_fifo *fifo; + int nr = max + 1; + int cnt = nr - min; int ret; ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", @@ -167,17 +185,21 @@ nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - fifo->min = min; - fifo->max = max; - fifo->channel = kzalloc(sizeof(*fifo->channel) * (max + 1), GFP_KERNEL); - if (!fifo->channel) - return -ENOMEM; + fifo->engine.func = &nvkm_fifo_func; + INIT_LIST_HEAD(&fifo->chan); + + fifo->nr = nr; + if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) { + fifo->nr = NVKM_FIFO_CHID_NR; + cnt = fifo->nr - min; + } + bitmap_fill(fifo->mask, NVKM_FIFO_CHID_NR); + bitmap_clear(fifo->mask, min, cnt); ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent); if (ret) return ret; - fifo->chid = nvkm_fifo_chid; spin_lock_init(&fifo->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index cc401ae1d6a5..2735c2df2218 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -24,139 +24,472 @@ #include "chan.h" #include +#include +#include #include -#include +struct nvkm_fifo_chan_object { + struct nvkm_oproxy oproxy; + struct nvkm_fifo_chan *chan; + int hash; +}; -int -_nvkm_fifo_channel_ntfy(struct nvkm_object *object, u32 type, - struct nvkm_event **event) +static int +nvkm_fifo_chan_child_fini(struct nvkm_oproxy *base, bool suspend) +{ + struct nvkm_fifo_chan_object *object = + container_of(base, typeof(*object), oproxy); + struct nvkm_engine *engine = object->oproxy.object->engine; + struct nvkm_fifo_chan *chan = object->chan; + struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + const char *name = nvkm_subdev_name[engine->subdev.index]; + int ret = 0; + + if (--engn->usecount) + return 0; + + if (chan->func->engine_fini) { + ret = chan->func->engine_fini(chan, engine, suspend); + if (ret) { + nvif_error(&chan->object, + "detach %s failed, %d\n", name, ret); + return ret; + } + } + + if (engn->object) { + ret = nvkm_object_fini(engn->object, suspend); + if (ret && suspend) + return ret; + } + + nvif_trace(&chan->object, "detached %s\n", name); + return ret; +} + +static int +nvkm_fifo_chan_child_init(struct nvkm_oproxy *base) +{ + struct nvkm_fifo_chan_object *object = + container_of(base, typeof(*object), oproxy); + struct nvkm_engine *engine = object->oproxy.object->engine; + struct nvkm_fifo_chan *chan = object->chan; + struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + const char *name = nvkm_subdev_name[engine->subdev.index]; + int ret; + + if (engn->usecount++) + return 0; + + if (engn->object) { + ret = nvkm_object_init(engn->object); + if (ret) + return ret; + } + + if (chan->func->engine_init) { + ret = chan->func->engine_init(chan, engine); + if (ret) { + nvif_error(&chan->object, + "attach %s failed, %d\n", name, ret); + return ret; + } + } + + nvif_trace(&chan->object, "attached %s\n", name); + return 0; +} + +static void +nvkm_fifo_chan_child_del(struct nvkm_oproxy *base) +{ + struct nvkm_fifo_chan_object *object = + container_of(base, typeof(*object), oproxy); + struct nvkm_engine *engine = object->oproxy.base.engine; + struct nvkm_fifo_chan *chan = object->chan; + struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + + if (chan->func->object_dtor) + chan->func->object_dtor(chan, object->hash); + + if (!--engn->refcount) { + if (chan->func->engine_dtor) + chan->func->engine_dtor(chan, engine); + nvkm_object_ref(NULL, &engn->object); + if (chan->vm) + atomic_dec(&chan->vm->engref[engine->subdev.index]); + } +} + +static const struct nvkm_oproxy_func +nvkm_fifo_chan_child_func = { + .dtor[0] = nvkm_fifo_chan_child_del, + .init[0] = nvkm_fifo_chan_child_init, + .fini[0] = nvkm_fifo_chan_child_fini, +}; + +static int +nvkm_fifo_chan_child_old(const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_fifo *fifo = (void *)object->engine; - switch (type) { - case G82_CHANNEL_DMA_V0_NTFY_UEVENT: - if (nv_mclass(object) >= G82_CHANNEL_DMA) { - *event = &fifo->uevent; - return 0; + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(oclass->parent); + struct nvkm_object *parent = &chan->object; + struct nvkm_engine *engine = oclass->engine; + struct nvkm_oclass *eclass = (void *)oclass->priv; + struct nvkm_object *engctx = NULL; + struct nvkm_fifo_chan_object *object; + struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + int ret; + + if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) + return -ENOMEM; + nvkm_oproxy_ctor(&nvkm_fifo_chan_child_func, oclass, &object->oproxy); + *pobject = &object->oproxy.base; + object->chan = chan; + + if (!engn->refcount++) { + if (chan->vm) + atomic_inc(&chan->vm->engref[engine->subdev.index]); + if (engine->cclass && !engn->object) { + ret = nvkm_object_old(parent, &engine->subdev.object, + engine->cclass, NULL, 0, + &engn->object); + if (ret) { + nvkm_engine_unref(&engine); + return ret; + } + } else { + nvkm_object_ref(parent, &engn->object); } - break; - default: - break; + + if (chan->func->engine_ctor) { + ret = chan->func->engine_ctor(chan, engine, + engn->object); + if (ret) + return ret; + } + } + nvkm_object_ref(engn->object, &engctx); + + ret = nvkm_object_old(engctx, &engine->subdev.object, eclass, + data, size, &object->oproxy.object); + nvkm_object_ref(NULL, &engctx); + if (ret) + return ret; + + object->oproxy.object->handle = oclass->handle; + + if (chan->func->object_ctor) { + object->hash = + chan->func->object_ctor(chan, object->oproxy.object); + if (object->hash < 0) + return object->hash; } + + return 0; +} + +static int +nvkm_fifo_chan_child_new(const struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) +{ + struct nvkm_engine *engine = oclass->engine; + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(oclass->parent); + struct nvkm_fifo_engn *engn = &chan->engn[engine->subdev.index]; + struct nvkm_fifo_chan_object *object; + int ret = 0; + + if (!(object = kzalloc(sizeof(*object), GFP_KERNEL))) + return -ENOMEM; + nvkm_oproxy_ctor(&nvkm_fifo_chan_child_func, oclass, &object->oproxy); + object->chan = chan; + *pobject = &object->oproxy.base; + + if (!engn->refcount++) { + struct nvkm_oclass cclass = { + .client = oclass->client, + .engine = oclass->engine, + }; + + if (chan->vm) + atomic_inc(&chan->vm->engref[engine->subdev.index]); + + if (engine->func->fifo.cclass) { + ret = engine->func->fifo.cclass(chan, &cclass, + &engn->object); + } else + if (engine->func->cclass) { + ret = nvkm_object_new_(engine->func->cclass, &cclass, + NULL, 0, &engn->object); + } + if (ret) + return ret; + + if (chan->func->engine_ctor) { + ret = chan->func->engine_ctor(chan, oclass->engine, + engn->object); + if (ret) + return ret; + } + } + + ret = oclass->base.ctor(&(const struct nvkm_oclass) { + .base = oclass->base, + .engn = oclass->engn, + .handle = oclass->handle, + .object = oclass->object, + .client = oclass->client, + .parent = engn->object ? + engn->object : + oclass->parent, + .engine = engine, + }, data, size, &object->oproxy.object); + if (ret) + return ret; + + if (chan->func->object_ctor) { + object->hash = + chan->func->object_ctor(chan, object->oproxy.object); + if (object->hash < 0) + return object->hash; + } + + return 0; +} + +static int +nvkm_fifo_chan_child_get(struct nvkm_object *object, int index, + struct nvkm_oclass *oclass) +{ + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + struct nvkm_fifo *fifo = chan->fifo; + struct nvkm_device *device = fifo->engine.subdev.device; + struct nvkm_engine *engine; + u64 mask = chan->engines; + int ret, i, c; + + for (; c = 0, i = __ffs64(mask), mask; mask &= ~(1ULL << i)) { + if ((engine = nvkm_device_engine(device, i)) && + !engine->func) { + struct nvkm_oclass *sclass = engine->sclass; + int c = 0; + while (sclass && sclass->ofuncs) { + if (c++ == index) { + oclass->base.oclass = sclass->handle; + oclass->base.minver = -2; + oclass->base.maxver = -2; + oclass->ctor = nvkm_fifo_chan_child_old; + oclass->priv = sclass; + oclass->engine = engine; + return 0; + } + sclass++; + } + index -= c; + continue; + } + + if (!(engine = nvkm_device_engine(device, i))) + continue; + oclass->engine = engine; + oclass->base.oclass = 0; + + if (engine->func->fifo.sclass) { + ret = engine->func->fifo.sclass(oclass, index); + if (oclass->base.oclass) { + if (!oclass->base.ctor) + oclass->base.ctor = nvkm_object_new; + oclass->ctor = nvkm_fifo_chan_child_new; + return 0; + } + + index -= ret; + continue; + } + + while (engine->func->sclass[c].oclass) { + if (c++ == index) { + oclass->base = engine->func->sclass[index]; + if (!oclass->base.ctor) + oclass->base.ctor = nvkm_object_new; + oclass->ctor = nvkm_fifo_chan_child_new; + return 0; + } + } + index -= c; + } + return -EINVAL; } -int -_nvkm_fifo_channel_map(struct nvkm_object *object, u64 *addr, u32 *size) +static int +nvkm_fifo_chan_ntfy(struct nvkm_object *object, u32 type, + struct nvkm_event **pevent) { - struct nvkm_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + if (chan->func->ntfy) + return chan->func->ntfy(chan, type, pevent); + return -ENODEV; +} + +static int +nvkm_fifo_chan_map(struct nvkm_object *object, u64 *addr, u32 *size) +{ + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); *addr = chan->addr; *size = chan->size; return 0; } -u32 -_nvkm_fifo_channel_rd32(struct nvkm_object *object, u64 addr) +static int +nvkm_fifo_chan_rd32(struct nvkm_object *object, u64 addr, u32 *data) { - struct nvkm_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); if (unlikely(!chan->user)) { chan->user = ioremap(chan->addr, chan->size); - if (WARN_ON_ONCE(chan->user == NULL)) - return 0; + if (!chan->user) + return -ENOMEM; } - return ioread32_native(chan->user + addr); + if (unlikely(addr + 4 > chan->size)) + return -EINVAL; + *data = ioread32_native(chan->user + addr); + return 0; } -void -_nvkm_fifo_channel_wr32(struct nvkm_object *object, u64 addr, u32 data) +static int +nvkm_fifo_chan_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nvkm_fifo_chan *chan = (void *)object; + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); if (unlikely(!chan->user)) { chan->user = ioremap(chan->addr, chan->size); - if (WARN_ON_ONCE(chan->user == NULL)) - return; + if (!chan->user) + return -ENOMEM; } + if (unlikely(addr + 4 > chan->size)) + return -EINVAL; iowrite32_native(data, chan->user + addr); + return 0; +} + +static int +nvkm_fifo_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + chan->func->fini(chan); + return 0; } -void -nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *chan) +static int +nvkm_fifo_chan_init(struct nvkm_object *object) { - struct nvkm_fifo *fifo = (void *)nv_object(chan)->engine; + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + chan->func->init(chan); + return 0; +} + +static void * +nvkm_fifo_chan_dtor(struct nvkm_object *object) +{ + struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); + struct nvkm_fifo *fifo = chan->fifo; + void *data = chan->func->dtor(chan); unsigned long flags; + spin_lock_irqsave(&fifo->lock, flags); + if (!list_empty(&chan->head)) { + __clear_bit(chan->chid, fifo->mask); + list_del(&chan->head); + } + spin_unlock_irqrestore(&fifo->lock, flags); + if (chan->user) iounmap(chan->user); - spin_lock_irqsave(&fifo->lock, flags); - fifo->channel[chan->chid] = NULL; - spin_unlock_irqrestore(&fifo->lock, flags); + nvkm_vm_ref(NULL, &chan->vm, NULL); - nvkm_gpuobj_del(&chan->pushgpu); - nvkm_namedb_destroy(&chan->namedb); + nvkm_gpuobj_del(&chan->push); + nvkm_gpuobj_del(&chan->inst); + return data; } -void -_nvkm_fifo_channel_dtor(struct nvkm_object *object) -{ - struct nvkm_fifo_chan *chan = (void *)object; - nvkm_fifo_channel_destroy(chan); -} +const struct nvkm_object_func +nvkm_fifo_chan_func = { + .dtor = nvkm_fifo_chan_dtor, + .init = nvkm_fifo_chan_init, + .fini = nvkm_fifo_chan_fini, + .ntfy = nvkm_fifo_chan_ntfy, + .map = nvkm_fifo_chan_map, + .rd32 = nvkm_fifo_chan_rd32, + .wr32 = nvkm_fifo_chan_wr32, + .sclass = nvkm_fifo_chan_child_get, +}; int -nvkm_fifo_channel_create_(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, - int bar, u32 addr, u32 size, u64 pushbuf, - u64 engmask, int len, void **ptr) +nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, + struct nvkm_fifo *fifo, u32 size, u32 align, bool zero, + u64 vm, u64 push, u64 engines, int bar, u32 base, u32 user, + const struct nvkm_oclass *oclass, + struct nvkm_fifo_chan *chan) { - struct nvkm_client *client = nvkm_client(parent); - struct nvkm_fifo *fifo = (void *)engine; - struct nvkm_fifo_base *base = (void *)parent; - struct nvkm_fifo_chan *chan; - struct nvkm_subdev *subdev = &fifo->engine.subdev; - struct nvkm_device *device = subdev->device; + struct nvkm_client *client = oclass->client; + struct nvkm_device *device = fifo->engine.subdev.device; + struct nvkm_mmu *mmu = device->mmu; struct nvkm_dmaobj *dmaobj; unsigned long flags; int ret; - /* create base object class */ - ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, - engmask, len, ptr); - chan = *ptr; + nvkm_object_ctor(&nvkm_fifo_chan_func, oclass, &chan->object); + chan->func = func; + chan->fifo = fifo; + chan->engines = engines; + INIT_LIST_HEAD(&chan->head); + + /* instance memory */ + ret = nvkm_gpuobj_new(device, size, align, zero, NULL, &chan->inst); if (ret) return ret; - /* validate dma object representing push buffer */ - if (pushbuf) { - dmaobj = nvkm_dma_search(device->dma, client, pushbuf); + /* allocate push buffer ctxdma instance */ + if (push) { + dmaobj = nvkm_dma_search(device->dma, oclass->client, push); if (!dmaobj) return -ENOENT; - ret = nvkm_object_bind(&dmaobj->object, &base->gpuobj, 16, - &chan->pushgpu); + ret = nvkm_object_bind(&dmaobj->object, chan->inst, -16, + &chan->push); if (ret) return ret; } - /* find a free fifo channel */ - spin_lock_irqsave(&fifo->lock, flags); - for (chan->chid = fifo->min; chan->chid < fifo->max; chan->chid++) { - if (!fifo->channel[chan->chid]) { - fifo->channel[chan->chid] = nv_object(chan); - break; + /* channel address space */ + if (!vm && mmu) { + if (!client->vm || client->vm->mmu == mmu) { + ret = nvkm_vm_ref(client->vm, &chan->vm, NULL); + if (ret) + return ret; + } else { + return -EINVAL; } + } else { + return -ENOENT; } - spin_unlock_irqrestore(&fifo->lock, flags); - if (chan->chid == fifo->max) { - nvkm_error(subdev, "no free channels\n"); + /* allocate channel id */ + spin_lock_irqsave(&fifo->lock, flags); + chan->chid = find_first_zero_bit(fifo->mask, NVKM_FIFO_CHID_NR); + if (chan->chid >= NVKM_FIFO_CHID_NR) { + spin_unlock_irqrestore(&fifo->lock, flags); return -ENOSPC; } + list_add(&chan->head, &fifo->chan); + __set_bit(chan->chid, fifo->mask); + spin_unlock_irqrestore(&fifo->lock, flags); + /* determine address of this channel's user registers */ chan->addr = nv_device_resource_start(device, bar) + - addr + size * chan->chid; - chan->size = size; + base + user * chan->chid; + chan->size = user; + nvkm_event_send(&fifo->cevent, 1, 0, NULL, 0); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h index 63209bc8856b..bfec12dbf492 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -2,27 +2,31 @@ #define __NVKM_FIFO_CHAN_H__ #include "priv.h" -#define nvkm_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ - nvkm_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ - (m), sizeof(**d), (void **)d) -#define nvkm_fifo_channel_init(p) \ - nvkm_namedb_init(&(p)->namedb) -#define nvkm_fifo_channel_fini(p,s) \ - nvkm_namedb_fini(&(p)->namedb, (s)) +struct nvkm_fifo_chan_func { + void *(*dtor)(struct nvkm_fifo_chan *); + void (*init)(struct nvkm_fifo_chan *); + void (*fini)(struct nvkm_fifo_chan *); + int (*ntfy)(struct nvkm_fifo_chan *, u32 type, struct nvkm_event **); + int (*engine_ctor)(struct nvkm_fifo_chan *, struct nvkm_engine *, + struct nvkm_object *); + void (*engine_dtor)(struct nvkm_fifo_chan *, struct nvkm_engine *); + int (*engine_init)(struct nvkm_fifo_chan *, struct nvkm_engine *); + int (*engine_fini)(struct nvkm_fifo_chan *, struct nvkm_engine *, + bool suspend); + int (*object_ctor)(struct nvkm_fifo_chan *, struct nvkm_object *); + void (*object_dtor)(struct nvkm_fifo_chan *, int); +}; -int nvkm_fifo_channel_create_(struct nvkm_object *, - struct nvkm_object *, - struct nvkm_oclass *, - int bar, u32 addr, u32 size, u64 push, - u64 engmask, int len, void **); -void nvkm_fifo_channel_destroy(struct nvkm_fifo_chan *); +int nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *, struct nvkm_fifo *, + u32 size, u32 align, bool zero, u64 vm, u64 push, + u64 engines, int bar, u32 base, u32 user, + const struct nvkm_oclass *, struct nvkm_fifo_chan *); -#define _nvkm_fifo_channel_init _nvkm_namedb_init -#define _nvkm_fifo_channel_fini _nvkm_namedb_fini +struct nvkm_fifo_chan_oclass { + int (*ctor)(struct nvkm_fifo *, const struct nvkm_oclass *, + void *data, u32 size, struct nvkm_object **); + struct nvkm_sclass base; +}; -void _nvkm_fifo_channel_dtor(struct nvkm_object *); -int _nvkm_fifo_channel_map(struct nvkm_object *, u64 *, u32 *); -u32 _nvkm_fifo_channel_rd32(struct nvkm_object *, u64); -void _nvkm_fifo_channel_wr32(struct nvkm_object *, u64, u32); -int _nvkm_fifo_channel_ntfy(struct nvkm_object *, u32, struct nvkm_event **); +int g84_fifo_chan_ntfy(struct nvkm_fifo_chan *, u32, struct nvkm_event **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index f2b4a96f8794..a7e5dfae3833 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -25,38 +25,86 @@ #include #include +#include #include +#include + int -g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) +g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type, + struct nvkm_event **pevent) { - struct nv50_fifo *fifo = (void *)parent->engine; - struct nv50_fifo_base *base = (void *)parent->parent; - struct nv50_fifo_chan *chan = (void *)parent; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 addr, save, engn; - bool done; + switch (type) { + case G82_CHANNEL_DMA_V0_NTFY_UEVENT: + *pevent = &chan->fifo->uevent; + return 0; + default: + break; + } + return -EINVAL; +} - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; +static int +g84_fifo_chan_engine(struct nvkm_engine *engine) +{ + switch (engine->subdev.index) { + case NVDEV_ENGINE_GR : return 0; + case NVDEV_ENGINE_MPEG : + case NVDEV_ENGINE_MSPPP : return 1; + case NVDEV_ENGINE_CE0 : return 2; case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break; - case NVDEV_ENGINE_MSPPP : - case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; + case NVDEV_ENGINE_MSPDEC: return 3; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : return 4; case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break; + case NVDEV_ENGINE_MSVLD : return 5; + default: + WARN_ON(1); + return 0; + } +} + +static int +g84_fifo_chan_engine_addr(struct nvkm_engine *engine) +{ + switch (engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : return -1; + case NVDEV_ENGINE_GR : return 0x0020; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: return 0x0040; + case NVDEV_ENGINE_MPEG : + case NVDEV_ENGINE_MSPPP : return 0x0060; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : return 0x0080; case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : engn = 4; addr = 0x00a0; break; - case NVDEV_ENGINE_CE0 : engn = 2; addr = 0x00c0; break; + case NVDEV_ENGINE_SEC : return 0x00a0; + case NVDEV_ENGINE_CE0 : return 0x00c0; default: - return -EINVAL; + WARN_ON(1); + return -1; } +} +static int +g84_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, bool suspend) +{ + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nv50_fifo *fifo = chan->fifo; + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 engn, save; + int offset; + bool done; + + offset = g84_fifo_chan_engine_addr(engine); + if (offset < 0) + return 0; + + engn = g84_fifo_chan_engine(engine); save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn); - nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); + nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); done = nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) break; @@ -64,168 +112,179 @@ g84_fifo_context_detach(struct nvkm_object *parent, bool suspend, nvkm_wr32(device, 0x002520, save); if (!done) { nvkm_error(subdev, "channel %d [%s] unload timeout\n", - chan->base.chid, nvkm_client_name(chan)); + chan->base.chid, chan->base.object.client->name); if (suspend) return -EBUSY; } - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00000000); - nvkm_wo32(base->eng, addr + 0x04, 0x00000000); - nvkm_wo32(base->eng, addr + 0x08, 0x00000000); - nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); + nvkm_kmap(chan->eng); + nvkm_wo32(chan->eng, offset + 0x00, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x04, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x08, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); + nvkm_done(chan->eng); return 0; } int -g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) +g84_fifo_chan_engine_init(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) { - struct nv50_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *ectx = (void *)object; - u64 limit = ectx->addr + ectx->size - 1; - u64 start = ectx->addr; - u32 addr; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0020; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break; - case NVDEV_ENGINE_MSPPP : - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : addr = 0x0080; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : addr = 0x00a0; break; - case NVDEV_ENGINE_CE0 : addr = 0x00c0; break; - default: - return -EINVAL; - } + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; + u64 limit, start; + int offset; - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00190000); - nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); - nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | - upper_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); + offset = g84_fifo_chan_engine_addr(engine); + if (offset < 0) + return 0; + limit = engn->addr + engn->size - 1; + start = engn->addr; + + nvkm_kmap(chan->eng); + nvkm_wo32(chan->eng, offset + 0x00, 0x00190000); + nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit)); + nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start)); + nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | + upper_32_bits(start)); + nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); + nvkm_done(chan->eng); return 0; } +static int +g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, + struct nvkm_object *object) +{ + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + int engn = engine->subdev.index; + + if (g84_fifo_chan_engine_addr(engine) < 0) + return 0; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) { + chan->engn[engn] = nv_gpuobj(object); + return 0; + } + + return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); +} + int -g84_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) +g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, + struct nvkm_object *object) { - struct nv50_fifo_chan *chan = (void *)parent; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + u32 handle = object->handle; u32 context; - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->node->offset >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context |= 0x00000000; break; - case NVDEV_ENGINE_GR : context |= 0x00100000; break; - case NVDEV_ENGINE_MPEG : - case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break; - case NVDEV_ENGINE_ME : - case NVDEV_ENGINE_CE0 : context |= 0x00300000; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : - case NVDEV_ENGINE_VIC : context |= 0x00500000; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; - default: - return -EINVAL; - } + switch (object->engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : context = 0x00000000; break; + case NVDEV_ENGINE_GR : context = 0x00100000; break; + case NVDEV_ENGINE_MPEG : + case NVDEV_ENGINE_MSPPP : context = 0x00200000; break; + case NVDEV_ENGINE_ME : + case NVDEV_ENGINE_CE0 : context = 0x00300000; break; + case NVDEV_ENGINE_VP : + case NVDEV_ENGINE_MSPDEC: context = 0x00400000; break; + case NVDEV_ENGINE_CIPHER: + case NVDEV_ENGINE_SEC : + case NVDEV_ENGINE_VIC : context = 0x00500000; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : context = 0x00600000; break; + default: + WARN_ON(1); + return -EINVAL; } - return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); + return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context); } -int -g84_fifo_chan_init(struct nvkm_object *object) +static void +g84_fifo_chan_init(struct nvkm_fifo_chan *base) { - struct nv50_fifo *fifo = (void *)object->engine; - struct nv50_fifo_base *base = (void *)object->parent; - struct nv50_fifo_chan *chan = (void *)object; - struct nvkm_gpuobj *ramfc = base->ramfc; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nv50_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; + u64 addr = chan->ramfc->addr >> 8; u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); + nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | addr); nv50_fifo_runlist_update(fifo); - return 0; } -static int -g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_fifo_chan_func +g84_fifo_chan_func = { + .dtor = nv50_fifo_chan_dtor, + .init = g84_fifo_chan_init, + .fini = nv50_fifo_chan_fini, + .ntfy = g84_fifo_chan_ntfy, + .engine_ctor = g84_fifo_chan_engine_ctor, + .engine_dtor = nv50_fifo_chan_engine_dtor, + .engine_init = g84_fifo_chan_engine_init, + .engine_fini = g84_fifo_chan_engine_fini, + .object_ctor = g84_fifo_chan_object_ctor, + .object_dtor = nv50_fifo_chan_object_dtor, +}; + +int +g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push, + const struct nvkm_oclass *oclass, + struct nv50_fifo_chan *chan) { - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct nv50_fifo_base *base; + struct nvkm_device *device = fifo->base.engine.subdev.device; int ret; - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); + ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base, + 0x10000, 0x1000, false, vm, push, + (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_CIPHER) | + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_ME) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_SEC) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_VIC) | + (1ULL << NVDEV_ENGINE_VP), + 0, 0xc00000, 0x2000, oclass, &chan->base); + chan->fifo = fifo; if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x0200, 0, true, &base->base.gpuobj, - &base->eng); + ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->base.inst, + &chan->eng); if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, - &base->pgd); + ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst, + &chan->pgd); if (ret) return ret; - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->base.inst, + &chan->cache); if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, &base->base.gpuobj, - &base->cache); + ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->base.inst, + &chan->ramfc); if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, &base->base.gpuobj, - &base->ramfc); + ret = nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); if (ret) return ret; - return 0; + return nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); } - -struct nvkm_oclass -g84_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x84), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g84_fifo_context_ctor, - .dtor = nv50_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h index 99324222dade..413288597e04 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h @@ -1,23 +1,24 @@ #ifndef __GF100_FIFO_CHAN_H__ #define __GF100_FIFO_CHAN_H__ +#define gf100_fifo_chan(p) container_of((p), struct gf100_fifo_chan, base) #include "chan.h" #include "gf100.h" -struct gf100_fifo_base { - struct nvkm_fifo_base base; +struct gf100_fifo_chan { + struct nvkm_fifo_chan base; + struct gf100_fifo *fifo; + + struct list_head head; + bool killed; + struct nvkm_gpuobj *pgd; struct nvkm_vm *vm; -}; -struct gf100_fifo_chan { - struct nvkm_fifo_chan base; - enum { - STOPPED, - RUNNING, - KILLED - } state; + struct { + struct nvkm_gpuobj *inst; + struct nvkm_vma vma; + } engn[NVDEV_SUBDEV_NR]; }; -extern struct nvkm_oclass gf100_fifo_cclass; -extern struct nvkm_oclass gf100_fifo_sclass[]; +extern const struct nvkm_fifo_chan_oclass gf100_fifo_gpfifo_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h index 3490cb6d8bd3..2b9d8bfc7fd7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h @@ -1,27 +1,29 @@ #ifndef __GK104_FIFO_CHAN_H__ #define __GK104_FIFO_CHAN_H__ +#define gk104_fifo_chan(p) container_of((p), struct gk104_fifo_chan, base) #include "chan.h" #include "gk104.h" -struct gk104_fifo_base { - struct nvkm_fifo_base base; +struct gk104_fifo_chan { + struct nvkm_fifo_chan base; + struct gk104_fifo *fifo; + int engine; + + struct list_head head; + bool killed; + struct nvkm_gpuobj *pgd; struct nvkm_vm *vm; -}; -struct gk104_fifo_chan { - struct nvkm_fifo_chan base; - u32 engine; - enum { - STOPPED, - RUNNING, - KILLED - } state; + struct { + struct nvkm_gpuobj *inst; + struct nvkm_vma vma; + } engn[NVDEV_SUBDEV_NR]; }; -extern struct nvkm_oclass gk104_fifo_cclass; -extern struct nvkm_oclass gk104_fifo_sclass[]; -extern struct nvkm_ofuncs gk104_fifo_chan_ofuncs; +int gk104_fifo_gpfifo_new(struct nvkm_fifo *, const struct nvkm_oclass *, + void *data, u32 size, struct nvkm_object **); -extern struct nvkm_oclass gm204_fifo_sclass[]; +extern const struct nvkm_fifo_chan_oclass gk104_fifo_gpfifo_oclass; +extern const struct nvkm_fifo_chan_oclass gm204_fifo_gpfifo_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h index 028212df41bc..ac62a6404f87 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h @@ -1,24 +1,24 @@ #ifndef __NV04_FIFO_CHAN_H__ #define __NV04_FIFO_CHAN_H__ +#define nv04_fifo_chan(p) container_of((p), struct nv04_fifo_chan, base) #include "chan.h" #include "nv04.h" struct nv04_fifo_chan { struct nvkm_fifo_chan base; - u32 subc[8]; + struct nv04_fifo *fifo; u32 ramfc; + struct nvkm_gpuobj *engn[NVDEV_SUBDEV_NR]; }; -int nv04_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); -void nv04_fifo_object_detach(struct nvkm_object *, int); +extern const struct nvkm_fifo_chan_func nv04_fifo_dma_func; +void *nv04_fifo_dma_dtor(struct nvkm_fifo_chan *); +void nv04_fifo_dma_init(struct nvkm_fifo_chan *); +void nv04_fifo_dma_fini(struct nvkm_fifo_chan *); +void nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *, int); -void nv04_fifo_chan_dtor(struct nvkm_object *); -int nv04_fifo_chan_init(struct nvkm_object *); -int nv04_fifo_chan_fini(struct nvkm_object *, bool suspend); - -extern struct nvkm_oclass nv04_fifo_cclass; -extern struct nvkm_oclass nv04_fifo_sclass[]; -extern struct nvkm_oclass nv10_fifo_sclass[]; -extern struct nvkm_oclass nv17_fifo_sclass[]; -extern struct nvkm_oclass nv40_fifo_sclass[]; +extern const struct nvkm_fifo_chan_oclass nv04_fifo_dma_oclass; +extern const struct nvkm_fifo_chan_oclass nv10_fifo_dma_oclass; +extern const struct nvkm_fifo_chan_oclass nv17_fifo_dma_oclass; +extern const struct nvkm_fifo_chan_oclass nv40_fifo_dma_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c index aeaba7b9bcae..2a25019ce0f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c @@ -25,27 +25,37 @@ #include #include +#include #include -int -nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) +static int +nv50_fifo_chan_engine_addr(struct nvkm_engine *engine) { - struct nv50_fifo *fifo = (void *)parent->engine; - struct nv50_fifo_base *base = (void *)parent->parent; - struct nv50_fifo_chan *chan = (void *)parent; + switch (engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : return -1; + case NVDEV_ENGINE_GR : return 0x0000; + case NVDEV_ENGINE_MPEG : return 0x0060; + default: + WARN_ON(1); + return -1; + } +} + +static int +nv50_fifo_chan_engine_fini(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, bool suspend) +{ + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nv50_fifo *fifo = chan->fifo; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - u32 addr, me; - int ret = 0; + int offset, ret = 0; + u32 me; - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0000; break; - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - default: - return -EINVAL; - } + offset = nv50_fifo_chan_engine_addr(engine); + if (offset < 0) + return 0; /* HW bug workaround: * @@ -62,101 +72,124 @@ nv50_fifo_context_detach(struct nvkm_object *parent, bool suspend, me = nvkm_mask(device, 0x00b860, 0x00000001, 0x00000001); /* do the kickoff... */ - nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12); + nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x0032fc) != 0xffffffff) break; ) < 0) { nvkm_error(subdev, "channel %d [%s] unload timeout\n", - chan->base.chid, nvkm_client_name(chan)); + chan->base.chid, chan->base.object.client->name); if (suspend) ret = -EBUSY; } nvkm_wr32(device, 0x00b860, me); if (ret == 0) { - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00000000); - nvkm_wo32(base->eng, addr + 0x04, 0x00000000); - nvkm_wo32(base->eng, addr + 0x08, 0x00000000); - nvkm_wo32(base->eng, addr + 0x0c, 0x00000000); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); + nvkm_kmap(chan->eng); + nvkm_wo32(chan->eng, offset + 0x00, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x04, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x08, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x0c, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); + nvkm_done(chan->eng); } return ret; } -int -nv50_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object) +static int +nv50_fifo_chan_engine_init(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) { - struct nv50_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *ectx = (void *)object; - u64 limit = ectx->addr + ectx->size - 1; - u64 start = ectx->addr; - u32 addr; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0000; break; - case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - default: - return -EINVAL; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nvkm_gpuobj *engn = chan->engn[engine->subdev.index]; + u64 limit, start; + int offset; + + offset = nv50_fifo_chan_engine_addr(engine); + if (offset < 0) + return 0; + limit = engn->addr + engn->size - 1; + start = engn->addr; + + nvkm_kmap(chan->eng); + nvkm_wo32(chan->eng, offset + 0x00, 0x00190000); + nvkm_wo32(chan->eng, offset + 0x04, lower_32_bits(limit)); + nvkm_wo32(chan->eng, offset + 0x08, lower_32_bits(start)); + nvkm_wo32(chan->eng, offset + 0x0c, upper_32_bits(limit) << 24 | + upper_32_bits(start)); + nvkm_wo32(chan->eng, offset + 0x10, 0x00000000); + nvkm_wo32(chan->eng, offset + 0x14, 0x00000000); + nvkm_done(chan->eng); + return 0; +} + +void +nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) +{ + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + if (!chan->engn[engine->subdev.index] || + chan->engn[engine->subdev.index]->object.oclass) { + chan->engn[engine->subdev.index] = NULL; + return; } + nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); +} - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; - - nvkm_kmap(base->eng); - nvkm_wo32(base->eng, addr + 0x00, 0x00190000); - nvkm_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); - nvkm_wo32(base->eng, addr + 0x08, lower_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | - upper_32_bits(start)); - nvkm_wo32(base->eng, addr + 0x10, 0x00000000); - nvkm_wo32(base->eng, addr + 0x14, 0x00000000); - nvkm_done(base->eng); - return 0; +static int +nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, + struct nvkm_object *object) +{ + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + int engn = engine->subdev.index; + + if (nv50_fifo_chan_engine_addr(engine) < 0) + return 0; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) { + chan->engn[engn] = nv_gpuobj(object); + return 0; + } + + return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); } void -nv50_fifo_object_detach(struct nvkm_object *parent, int cookie) +nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *base, int cookie) { - struct nv50_fifo_chan *chan = (void *)parent; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); nvkm_ramht_remove(chan->ramht, cookie); } -int -nv50_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) +static int +nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, + struct nvkm_object *object) { - struct nv50_fifo_chan *chan = (void *)parent; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + u32 handle = object->handle; u32 context; - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->node->offset >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context |= 0x00000000; break; - case NVDEV_ENGINE_GR : context |= 0x00100000; break; - case NVDEV_ENGINE_MPEG : context |= 0x00200000; break; - default: - return -EINVAL; - } + switch (object->engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : context = 0x00000000; break; + case NVDEV_ENGINE_GR : context = 0x00100000; break; + case NVDEV_ENGINE_MPEG : context = 0x00200000; break; + default: + WARN_ON(1); + return -EINVAL; } - return nvkm_ramht_insert(chan->ramht, NULL, 0, 0, handle, context); + return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context); } -int -nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) +void +nv50_fifo_chan_fini(struct nvkm_fifo_chan *base) { - struct nv50_fifo *fifo = (void *)object->engine; - struct nv50_fifo_chan *chan = (void *)object; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nv50_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; u32 chid = chan->base.chid; @@ -164,96 +197,84 @@ nv50_fifo_chan_fini(struct nvkm_object *object, bool suspend) nvkm_mask(device, 0x002600 + (chid * 4), 0x80000000, 0x00000000); nv50_fifo_runlist_update(fifo); nvkm_wr32(device, 0x002600 + (chid * 4), 0x00000000); - - return nvkm_fifo_channel_fini(&chan->base, suspend); } -int -nv50_fifo_chan_init(struct nvkm_object *object) +static void +nv50_fifo_chan_init(struct nvkm_fifo_chan *base) { - struct nv50_fifo *fifo = (void *)object->engine; - struct nv50_fifo_base *base = (void *)object->parent; - struct nv50_fifo_chan *chan = (void *)object; - struct nvkm_gpuobj *ramfc = base->ramfc; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + struct nv50_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; + u64 addr = chan->ramfc->addr >> 12; u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); + nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | addr); nv50_fifo_runlist_update(fifo); - return 0; } -void -nv50_fifo_chan_dtor(struct nvkm_object *object) +void * +nv50_fifo_chan_dtor(struct nvkm_fifo_chan *base) { - struct nv50_fifo_chan *chan = (void *)object; + struct nv50_fifo_chan *chan = nv50_fifo_chan(base); + nvkm_vm_ref(NULL, &chan->vm, chan->pgd); nvkm_ramht_del(&chan->ramht); - nvkm_fifo_channel_destroy(&chan->base); + nvkm_gpuobj_del(&chan->pgd); + nvkm_gpuobj_del(&chan->eng); + nvkm_gpuobj_del(&chan->cache); + nvkm_gpuobj_del(&chan->ramfc); + return chan; } -void -nv50_fifo_context_dtor(struct nvkm_object *object) -{ - struct nv50_fifo_base *base = (void *)object; - nvkm_vm_ref(NULL, &base->vm, base->pgd); - nvkm_gpuobj_del(&base->pgd); - nvkm_gpuobj_del(&base->eng); - nvkm_gpuobj_del(&base->ramfc); - nvkm_gpuobj_del(&base->cache); - nvkm_fifo_context_destroy(&base->base); -} +static const struct nvkm_fifo_chan_func +nv50_fifo_chan_func = { + .dtor = nv50_fifo_chan_dtor, + .init = nv50_fifo_chan_init, + .fini = nv50_fifo_chan_fini, + .engine_ctor = nv50_fifo_chan_engine_ctor, + .engine_dtor = nv50_fifo_chan_engine_dtor, + .engine_init = nv50_fifo_chan_engine_init, + .engine_fini = nv50_fifo_chan_engine_fini, + .object_ctor = nv50_fifo_chan_object_ctor, + .object_dtor = nv50_fifo_chan_object_dtor, +}; -static int -nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push, + const struct nvkm_oclass *oclass, + struct nv50_fifo_chan *chan) { - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct nv50_fifo_base *base; + struct nvkm_device *device = fifo->base.engine.subdev.device; int ret; - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, - 0x1000, NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); + ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, + 0x10000, 0x1000, false, vm, push, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG), + 0, 0xc00000, 0x2000, oclass, &chan->base); + chan->fifo = fifo; if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, &base->base.gpuobj, - &base->ramfc); + ret = nvkm_gpuobj_new(device, 0x0200, 0x1000, true, chan->base.inst, + &chan->ramfc); if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x1200, 0, true, &base->base.gpuobj, - &base->eng); + ret = nvkm_gpuobj_new(device, 0x1200, 0, true, chan->base.inst, + &chan->eng); if (ret) return ret; - ret = nvkm_gpuobj_new(device, 0x4000, 0, false, &base->base.gpuobj, - &base->pgd); + ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->base.inst, + &chan->pgd); if (ret) return ret; - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); + ret = nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); if (ret) return ret; - return 0; + return nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); } - -struct nvkm_oclass -nv50_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x50), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fifo_context_ctor, - .dtor = nv50_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h index c4f2f1ff4c9e..7ef6bc2e27ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h @@ -1,42 +1,35 @@ #ifndef __NV50_FIFO_CHAN_H__ #define __NV50_FIFO_CHAN_H__ +#define nv50_fifo_chan(p) container_of((p), struct nv50_fifo_chan, base) #include "chan.h" #include "nv50.h" -struct nv50_fifo_base { - struct nvkm_fifo_base base; +struct nv50_fifo_chan { + struct nv50_fifo *fifo; + struct nvkm_fifo_chan base; + struct nvkm_gpuobj *ramfc; struct nvkm_gpuobj *cache; struct nvkm_gpuobj *eng; struct nvkm_gpuobj *pgd; + struct nvkm_ramht *ramht; struct nvkm_vm *vm; -}; -struct nv50_fifo_chan { - struct nvkm_fifo_chan base; - u32 subc[8]; - struct nvkm_ramht *ramht; + struct nvkm_gpuobj *engn[NVDEV_SUBDEV_NR]; }; -extern struct nvkm_oclass nv50_fifo_cclass; -extern struct nvkm_oclass nv50_fifo_sclass[]; -void nv50_fifo_context_dtor(struct nvkm_object *); -void nv50_fifo_chan_dtor(struct nvkm_object *); -int nv50_fifo_chan_init(struct nvkm_object *); -int nv50_fifo_chan_fini(struct nvkm_object *, bool); -int nv50_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); -int nv50_fifo_context_detach(struct nvkm_object *, bool, - struct nvkm_object *); -int nv50_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); -void nv50_fifo_object_detach(struct nvkm_object *, int); -extern struct nvkm_ofuncs nv50_fifo_ofuncs_ind; +int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push, + const struct nvkm_oclass *, struct nv50_fifo_chan *); +void *nv50_fifo_chan_dtor(struct nvkm_fifo_chan *); +void nv50_fifo_chan_fini(struct nvkm_fifo_chan *); +void nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *, struct nvkm_engine *); +void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); + +int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push, + const struct nvkm_oclass *, struct nv50_fifo_chan *); -extern struct nvkm_oclass g84_fifo_cclass; -extern struct nvkm_oclass g84_fifo_sclass[]; -int g84_fifo_chan_init(struct nvkm_object *); -int g84_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); -int g84_fifo_context_detach(struct nvkm_object *, bool, - struct nvkm_object *); -int g84_fifo_object_attach(struct nvkm_object *, struct nvkm_object *, u32); -extern struct nvkm_ofuncs g84_fifo_ofuncs_ind; +extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass; +extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass; +extern const struct nvkm_fifo_chan_oclass g84_fifo_dma_oclass; +extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c index 2016a9884b38..a5ca52c7b74f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c @@ -30,15 +30,14 @@ #include static int -g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv50_channel_dma_v0 v0; } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; int ret; @@ -48,80 +47,47 @@ g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, "pushbuf %llx offset %016llx\n", args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.offset); - if (args->v0.vm) - return -ENOENT; + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); + ret = g84_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, + oclass, chan); if (ret) return ret; - nv_parent(chan)->context_attach = g84_fifo_context_attach; - nv_parent(chan)->context_detach = g84_fifo_context_detach; - nv_parent(chan)->object_attach = g84_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; + args->v0.chid = chan->base.chid; - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + nvkm_kmap(chan->ramfc); + nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); + nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); + nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); + nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); + nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(chan->ramfc, 0x78, 0x00000000); + nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); + nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); - nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); - nvkm_done(base->ramfc); + nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); + nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); + nvkm_done(chan->ramfc); return 0; } -static struct nvkm_ofuncs -g84_fifo_ofuncs_dma = { - .ctor = g84_fifo_chan_ctor_dma, - .dtor = nv50_fifo_chan_dtor, - .init = g84_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -g84_fifo_sclass[] = { - { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma }, - { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind }, - {} +const struct nvkm_fifo_chan_oclass +g84_fifo_dma_oclass = { + .base.oclass = G82_CHANNEL_DMA, + .base.minver = 0, + .base.maxver = 0, + .ctor = g84_fifo_dma_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c index 8cc87103a369..eafa87886643 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -31,74 +31,51 @@ #include #include -int -nv04_fifo_context_attach(struct nvkm_object *parent, - struct nvkm_object *object) -{ - nv_engctx(object)->addr = nvkm_fifo_chan(parent)->chid; - return 0; -} - void -nv04_fifo_object_detach(struct nvkm_object *parent, int cookie) +nv04_fifo_dma_object_dtor(struct nvkm_fifo_chan *base, int cookie) { - struct nv04_fifo *fifo = (void *)parent->engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - mutex_lock(&nv_subdev(fifo)->mutex); + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; nvkm_ramht_remove(imem->ramht, cookie); - mutex_unlock(&nv_subdev(fifo)->mutex); } -int -nv04_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) +static int +nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, + struct nvkm_object *object) { - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - u32 context, chid = chan->base.chid; - int ret; - - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->addr >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW: - context |= 0x00000000; - break; - case NVDEV_ENGINE_GR: - context |= 0x00010000; - break; - case NVDEV_ENGINE_MPEG: - context |= 0x00020000; - break; - default: - return -EINVAL; - } + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; + u32 context = 0x80000000 | chan->base.chid << 24; + u32 handle = object->handle; + int hash; + + switch (object->engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : context |= 0x00000000; break; + case NVDEV_ENGINE_GR : context |= 0x00010000; break; + case NVDEV_ENGINE_MPEG : context |= 0x00020000; break; + default: + WARN_ON(1); + return -EINVAL; } - context |= 0x80000000; /* valid */ - context |= chid << 24; - - mutex_lock(&nv_subdev(fifo)->mutex); - ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context); - mutex_unlock(&nv_subdev(fifo)->mutex); - return ret; + mutex_lock(&chan->fifo->base.engine.subdev.mutex); + hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, + handle, context); + mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + return hash; } -int -nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) +void +nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) { - struct nv04_fifo *fifo = (void *)object->engine; - struct nv04_fifo_chan *chan = (void *)object; + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nv04_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_memory *fctx = device->imem->ramfc; struct ramfc_desc *c; unsigned long flags; + u32 mask = fifo->base.nr - 1; u32 data = chan->ramfc; u32 chid; @@ -107,7 +84,7 @@ nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) nvkm_wr32(device, NV03_PFIFO_CACHES, 0); /* if this channel is active, replace it with a null context */ - chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max; + chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & mask; if (chid == chan->base.chid) { nvkm_mask(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); @@ -129,7 +106,7 @@ nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask); nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); } @@ -138,35 +115,26 @@ nv04_fifo_chan_fini(struct nvkm_object *object, bool suspend) nvkm_mask(device, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); nvkm_wr32(device, NV03_PFIFO_CACHES, 1); spin_unlock_irqrestore(&fifo->base.lock, flags); - - return nvkm_fifo_channel_fini(&chan->base, suspend); } -int -nv04_fifo_chan_init(struct nvkm_object *object) +void +nv04_fifo_dma_init(struct nvkm_fifo_chan *base) { - struct nv04_fifo *fifo = (void *)object->engine; - struct nv04_fifo_chan *chan = (void *)object; + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nv04_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; u32 mask = 1 << chan->base.chid; unsigned long flags; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; - spin_lock_irqsave(&fifo->base.lock, flags); nvkm_mask(device, NV04_PFIFO_MODE, mask, mask); spin_unlock_irqrestore(&fifo->base.lock, flags); - return 0; } -void -nv04_fifo_chan_dtor(struct nvkm_object *object) +void * +nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base) { - struct nv04_fifo *fifo = (void *)object->engine; - struct nv04_fifo_chan *chan = (void *)object; + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nv04_fifo *fifo = chan->fifo; struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; struct ramfc_desc *c = fifo->ramfc_desc; @@ -175,22 +143,30 @@ nv04_fifo_chan_dtor(struct nvkm_object *object) nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); } while ((++c)->bits); nvkm_done(imem->ramfc); - - nvkm_fifo_channel_destroy(&chan->base); + return chan; } +const struct nvkm_fifo_chan_func +nv04_fifo_dma_func = { + .dtor = nv04_fifo_dma_dtor, + .init = nv04_fifo_dma_init, + .fini = nv04_fifo_dma_fini, + .object_ctor = nv04_fifo_dma_object_ctor, + .object_dtor = nv04_fifo_dma_object_dtor, +}; + static int -nv04_fifo_chan_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; + struct nv04_fifo *fifo = nv04_fifo(base); + struct nv04_fifo_chan *chan = NULL; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_instmem *imem = device->imem; int ret; nvif_ioctl(parent, "create channel dma size %d\n", size); @@ -198,29 +174,32 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent, nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + + ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, + 0x1000, 0x1000, false, 0, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_SW), + 0, 0x800000, 0x10000, oclass, &chan->base); + chan->fifo = fifo; if (ret) return ret; args->v0.chid = chan->base.chid; - - nv_parent(chan)->object_attach = nv04_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - nv_parent(chan)->context_attach = nv04_fifo_context_attach; chan->ramfc = chan->base.chid * 32; nvkm_kmap(imem->ramfc); nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | @@ -232,51 +211,10 @@ nv04_fifo_chan_ctor(struct nvkm_object *parent, return 0; } -static struct nvkm_ofuncs -nv04_fifo_ofuncs = { - .ctor = nv04_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -nv04_fifo_sclass[] = { - { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, - {} -}; - -int -nv04_fifo_context_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv04_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - return 0; -} - -struct nvkm_oclass -nv04_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fifo_context_ctor, - .dtor = _nvkm_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, +const struct nvkm_fifo_chan_oclass +nv04_fifo_dma_oclass = { + .base.oclass = NV03_CHANNEL_DMA, + .base.minver = 0, + .base.maxver = 0, + .ctor = nv04_fifo_dma_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c index a542515e63f0..1ad16205305f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -31,17 +31,17 @@ #include static int -nv10_fifo_chan_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; + struct nv04_fifo *fifo = nv04_fifo(base); + struct nv04_fifo_chan *chan = NULL; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_instmem *imem = device->imem; int ret; nvif_ioctl(parent, "create channel dma size %d\n", size); @@ -49,29 +49,32 @@ nv10_fifo_chan_ctor(struct nvkm_object *parent, nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR), &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + + ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, + 0x1000, 0x1000, false, 0, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_SW), + 0, 0x800000, 0x10000, oclass, &chan->base); + chan->fifo = fifo; if (ret) return ret; args->v0.chid = chan->base.chid; - - nv_parent(chan)->object_attach = nv04_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - nv_parent(chan)->context_attach = nv04_fifo_context_attach; chan->ramfc = chan->base.chid * 32; nvkm_kmap(imem->ramfc); nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | @@ -83,20 +86,10 @@ nv10_fifo_chan_ctor(struct nvkm_object *parent, return 0; } -static struct nvkm_ofuncs -nv10_fifo_ofuncs = { - .ctor = nv10_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -nv10_fifo_sclass[] = { - { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, - {} +const struct nvkm_fifo_chan_oclass +nv10_fifo_dma_oclass = { + .base.oclass = NV10_CHANNEL_DMA, + .base.minver = 0, + .base.maxver = 0, + .ctor = nv10_fifo_dma_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c index d0ece53a750b..2fbb9d4f0900 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -31,17 +31,17 @@ #include static int -nv17_fifo_chan_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; + struct nv04_fifo *fifo = nv04_fifo(base); + struct nv04_fifo_chan *chan = NULL; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_instmem *imem = device->imem; int ret; nvif_ioctl(parent, "create channel dma size %d\n", size); @@ -49,31 +49,33 @@ nv17_fifo_chan_ctor(struct nvkm_object *parent, nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, - 0x10000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ - &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + + ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, + 0x1000, 0x1000, false, 0, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | /* NV31- */ + (1ULL << NVDEV_ENGINE_SW), + 0, 0x800000, 0x10000, oclass, &chan->base); + chan->fifo = fifo; if (ret) return ret; args->v0.chid = chan->base.chid; - - nv_parent(chan)->object_attach = nv04_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; - nv_parent(chan)->context_attach = nv04_fifo_context_attach; chan->ramfc = chan->base.chid * 64; nvkm_kmap(imem->ramfc); nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | @@ -85,20 +87,10 @@ nv17_fifo_chan_ctor(struct nvkm_object *parent, return 0; } -static struct nvkm_ofuncs -nv17_fifo_ofuncs = { - .ctor = nv17_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -nv17_fifo_sclass[] = { - { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, - {} +const struct nvkm_fifo_chan_oclass +nv17_fifo_dma_oclass = { + .base.oclass = NV17_CHANNEL_DMA, + .base.minver = 0, + .base.maxver = 0, + .ctor = nv17_fifo_dma_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c index cd3503cb6837..b46a3b3cd092 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c @@ -31,36 +31,47 @@ #include #include +static bool +nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) +{ + switch (engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW: + return false; + case NVDEV_ENGINE_GR: + *reg = 0x0032e0; + *ctx = 0x38; + return true; + case NVDEV_ENGINE_MPEG: + *reg = 0x00330c; + *ctx = 0x54; + return true; + default: + WARN_ON(1); + return false; + } +} + static int -nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *engctx) +nv40_fifo_dma_engine_fini(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, bool suspend) { - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nv04_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; unsigned long flags; u32 reg, ctx; + int chid; - switch (nv_engidx(engctx->engine)) { - case NVDEV_ENGINE_SW: + if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - case NVDEV_ENGINE_GR: - reg = 0x32e0; - ctx = 0x38; - break; - case NVDEV_ENGINE_MPEG: - reg = 0x330c; - ctx = 0x54; - break; - default: - return -EINVAL; - } spin_lock_irqsave(&fifo->base.lock, flags); nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); - if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid) + chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); + if (chid == chan->base.chid) nvkm_wr32(device, reg, 0x00000000); nvkm_kmap(imem->ramfc); nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); @@ -72,38 +83,29 @@ nv40_fifo_context_detach(struct nvkm_object *parent, bool suspend, } static int -nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) +nv40_fifo_dma_engine_init(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) { - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nv04_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; unsigned long flags; - u32 reg, ctx; + u32 inst, reg, ctx; + int chid; - switch (nv_engidx(engctx->engine)) { - case NVDEV_ENGINE_SW: + if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - case NVDEV_ENGINE_GR: - reg = 0x32e0; - ctx = 0x38; - break; - case NVDEV_ENGINE_MPEG: - reg = 0x330c; - ctx = 0x54; - break; - default: - return -EINVAL; - } + inst = chan->engn[engine->subdev.index]->addr >> 4; spin_lock_irqsave(&fifo->base.lock, flags); - nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; nvkm_mask(device, 0x002500, 0x00000001, 0x00000000); - if ((nvkm_rd32(device, 0x003204) & fifo->base.max) == chan->base.chid) - nvkm_wr32(device, reg, nv_engctx(engctx)->addr); + chid = nvkm_rd32(device, 0x003204) & (fifo->base.nr - 1); + if (chid == chan->base.chid) + nvkm_wr32(device, reg, inst); nvkm_kmap(imem->ramfc); - nvkm_wo32(imem->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); + nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); nvkm_done(imem->ramfc); nvkm_mask(device, 0x002500, 0x00000001, 0x00000001); @@ -111,57 +113,91 @@ nv40_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *engctx) return 0; } +static void +nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) +{ + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + if (!chan->engn[engine->subdev.index] || + chan->engn[engine->subdev.index]->object.oclass) { + chan->engn[engine->subdev.index] = NULL; + return; + } + nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); +} + static int -nv40_fifo_object_attach(struct nvkm_object *parent, - struct nvkm_object *object, u32 handle) +nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, + struct nvkm_object *object) { - struct nv04_fifo *fifo = (void *)parent->engine; - struct nv04_fifo_chan *chan = (void *)parent; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - u32 context, chid = chan->base.chid; - int ret; + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + const int engn = engine->subdev.index; + u32 reg, ctx; - if (nv_iclass(object, NV_GPUOBJ_CLASS)) - context = nv_gpuobj(object)->addr >> 4; - else - context = 0x00000004; /* just non-zero */ - - if (object->engine) { - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW: - context |= 0x00000000; - break; - case NVDEV_ENGINE_GR: - context |= 0x00100000; - break; - case NVDEV_ENGINE_MPEG: - context |= 0x00200000; - break; - default: - return -EINVAL; - } + if (!nv40_fifo_dma_engine(engine, ®, &ctx)) + return 0; + + if (nv_iclass(object, NV_GPUOBJ_CLASS)) { + chan->engn[engn] = nv_gpuobj(object); + return 0; } - context |= chid << 23; + return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); +} - mutex_lock(&nv_subdev(fifo)->mutex); - ret = nvkm_ramht_insert(imem->ramht, NULL, chid, 0, handle, context); - mutex_unlock(&nv_subdev(fifo)->mutex); - return ret; +static int +nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, + struct nvkm_object *object) +{ + struct nv04_fifo_chan *chan = nv04_fifo_chan(base); + struct nvkm_instmem *imem = chan->fifo->base.engine.subdev.device->imem; + u32 context = chan->base.chid << 23; + u32 handle = object->handle; + int hash; + + switch (object->engine->subdev.index) { + case NVDEV_ENGINE_DMAOBJ: + case NVDEV_ENGINE_SW : context |= 0x00000000; break; + case NVDEV_ENGINE_GR : context |= 0x00100000; break; + case NVDEV_ENGINE_MPEG : context |= 0x00200000; break; + default: + WARN_ON(1); + return -EINVAL; + } + + mutex_lock(&chan->fifo->base.engine.subdev.mutex); + hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, + handle, context); + mutex_unlock(&chan->fifo->base.engine.subdev.mutex); + return hash; } +static const struct nvkm_fifo_chan_func +nv40_fifo_dma_func = { + .dtor = nv04_fifo_dma_dtor, + .init = nv04_fifo_dma_init, + .fini = nv04_fifo_dma_fini, + .engine_ctor = nv40_fifo_dma_engine_ctor, + .engine_dtor = nv40_fifo_dma_engine_dtor, + .engine_init = nv40_fifo_dma_engine_init, + .engine_fini = nv40_fifo_dma_engine_fini, + .object_ctor = nv40_fifo_dma_object_ctor, + .object_dtor = nv04_fifo_dma_object_dtor, +}; + static int -nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv03_channel_dma_v0 v0; } *args = data; - struct nv04_fifo *fifo = (void *)engine; - struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct nv04_fifo_chan *chan; + struct nv04_fifo *fifo = nv04_fifo(base); + struct nv04_fifo_chan *chan = NULL; + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_instmem *imem = device->imem; int ret; nvif_ioctl(parent, "create channel dma size %d\n", size); @@ -169,31 +205,33 @@ nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvif_ioctl(parent, "create channel dma vers %d pushbuf %llx " "offset %08x\n", args->v0.version, args->v0.pushbuf, args->v0.offset); + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x1000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + + ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, + 0x1000, 0x1000, false, 0, args->v0.pushbuf, + (1ULL << NVDEV_ENGINE_DMAOBJ) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MPEG) | + (1ULL << NVDEV_ENGINE_SW), + 0, 0xc00000, 0x1000, oclass, &chan->base); + chan->fifo = fifo; if (ret) return ret; args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = nv40_fifo_context_attach; - nv_parent(chan)->context_detach = nv40_fifo_context_detach; - nv_parent(chan)->object_attach = nv40_fifo_object_attach; - nv_parent(chan)->object_detach = nv04_fifo_object_detach; chan->ramfc = chan->base.chid * 128; nvkm_kmap(imem->ramfc); nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); - nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); + nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | @@ -206,20 +244,10 @@ nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } -static struct nvkm_ofuncs -nv40_fifo_ofuncs = { - .ctor = nv40_fifo_chan_ctor, - .dtor = nv04_fifo_chan_dtor, - .init = nv04_fifo_chan_init, - .fini = nv04_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -nv40_fifo_sclass[] = { - { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, - {} +const struct nvkm_fifo_chan_oclass +nv40_fifo_dma_oclass = { + .base.oclass = NV40_CHANNEL_DMA, + .base.minver = 0, + .base.maxver = 0, + .ctor = nv40_fifo_dma_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c index 11a283099235..6b3b15f12c39 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c @@ -30,15 +30,14 @@ #include static int -nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv50_channel_dma_v0 v0; } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; int ret; @@ -48,68 +47,45 @@ nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, "pushbuf %llx offset %016llx\n", args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.offset); - if (args->v0.vm) - return -ENOENT; + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + + ret = nv50_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, + oclass, chan); if (ret) return ret; - chan->base.inst = base->base.gpuobj.addr; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = nv50_fifo_context_attach; - nv_parent(chan)->context_detach = nv50_fifo_context_detach; - nv_parent(chan)->object_attach = nv50_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; - - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); - if (ret) - return ret; - - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); - nvkm_wo32(base->ramfc, 0x3c, 0x003f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x4c, 0xffffffff); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + nvkm_kmap(chan->ramfc); + nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); + nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); + nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); + nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); + nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); + nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(chan->ramfc, 0x78, 0x00000000); + nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); + nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_done(base->ramfc); + nvkm_done(chan->ramfc); return 0; } -static struct nvkm_ofuncs -nv50_fifo_ofuncs_dma = { - .ctor = nv50_fifo_chan_ctor_dma, - .dtor = nv50_fifo_chan_dtor, - .init = nv50_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -nv50_fifo_sclass[] = { - { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, - { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, - {} +const struct nvkm_fifo_chan_oclass +nv50_fifo_dma_oclass = { + .base.oclass = NV50_CHANNEL_DMA, + .base.minver = 0, + .base.maxver = 0, + .ctor = nv50_fifo_dma_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index ab0ecc423e68..00fa9d3eff7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -47,6 +47,15 @@ g84_fifo_uevent_func = { .fini = g84_fifo_uevent_fini, }; +static const struct nvkm_fifo_func +g84_fifo_func = { + .chan = { + &g84_fifo_dma_oclass, + &g84_fifo_gpfifo_oclass, + NULL + }, +}; + static int g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -61,6 +70,8 @@ g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &g84_fifo_func; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, false, &fifo->runlist[0]); if (ret) @@ -77,8 +88,6 @@ g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &g84_fifo_cclass; - nv_engine(fifo)->sclass = g84_fifo_sclass; fifo->base.pause = nv04_fifo_pause; fifo->base.start = nv04_fifo_start; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index b88e7c569c0a..bdad44e84b92 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -58,28 +58,26 @@ gf100_fifo_uevent_func = { void gf100_fifo_runlist_update(struct gf100_fifo *fifo) { + struct gf100_fifo_chan *chan; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; struct nvkm_memory *cur; - int i, p; + int nr = 0; mutex_lock(&nv_subdev(fifo)->mutex); cur = fifo->runlist.mem[fifo->runlist.active]; fifo->runlist.active = !fifo->runlist.active; nvkm_kmap(cur); - for (i = 0, p = 0; i < 128; i++) { - struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i]; - if (chan && chan->state == RUNNING) { - nvkm_wo32(cur, p + 0, i); - nvkm_wo32(cur, p + 4, 0x00000004); - p += 8; - } + list_for_each_entry(chan, &fifo->chan, head) { + nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); + nvkm_wo32(cur, (nr * 8) + 4, 0x00000004); + nr++; } nvkm_done(cur); nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12); - nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3)); + nvkm_wr32(device, 0x002274, 0x01f00000 | nr); if (wait_event_timeout(fifo->runlist.wait, !(nvkm_rd32(device, 0x00227c) & 0x00100000), @@ -166,7 +164,8 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, assert_spin_locked(&fifo->base.lock); nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); - chan->state = KILLED; + list_del_init(&chan->head); + chan->killed = true; fifo->mask |= 1ULL << nv_engidx(engine); schedule_work(&fifo->fault); @@ -198,11 +197,15 @@ gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) (void)save; if (busy && unk0 && unk1) { - if (!(chan = (void *)fifo->base.channel[chid])) - continue; - if (!(engine = gf100_fifo_engine(fifo, engn))) - continue; - gf100_fifo_recover(fifo, engine, chan); + list_for_each_entry(chan, &fifo->chan, head) { + if (chan->base.chid == chid) { + engine = gf100_fifo_engine(fifo, engn); + if (!engine) + break; + gf100_fifo_recover(fifo, engine, chan); + break; + } + } } } spin_unlock_irqrestore(&fifo->base.lock, flags); @@ -343,7 +346,8 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) write ? "write" : "read", (u64)vahi << 32 | valo, unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", reason, er ? er->name : "", chan ? chan->chid : -1, - (u64)inst << 12, nvkm_client_name(chan)); + (u64)inst << 12, + chan ? chan->object.client->name : "unknown"); if (engine && chan) gf100_fifo_recover(fifo, engine, (void *)chan); @@ -369,6 +373,8 @@ gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00003ffc); + struct nvkm_fifo_chan *chan; + unsigned long flags; u32 show= stat; char msg[128]; @@ -381,11 +387,13 @@ gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) if (show) { nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show); - nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%s] subc %d " - "mthd %04x data %08x\n", - unit, show, msg, chid, - nvkm_client_name_for_fifo_chid(&fifo->base, chid), + chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); + nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " + "subc %d mthd %04x data %08x\n", + unit, show, msg, chid, chan ? chan->inst->addr : 0, + chan ? chan->object.client->name : "unknown", subc, mthd, data); + nvkm_fifo_chan_put(&fifo->base, flags, &chan); } nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); @@ -579,6 +587,14 @@ gf100_fifo_dtor(struct nvkm_object *object) nvkm_fifo_destroy(&fifo->base); } +static const struct nvkm_fifo_func +gf100_fifo_func = { + .chan = { + &gf100_fifo_gpfifo_oclass, + NULL + }, +}; + static int gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -594,6 +610,9 @@ gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &gf100_fifo_func; + + INIT_LIST_HEAD(&fifo->chan); INIT_WORK(&fifo->fault, gf100_fifo_recover_work); ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, @@ -625,8 +644,6 @@ gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = gf100_fifo_intr; - nv_engine(fifo)->cclass = &gf100_fifo_cclass; - nv_engine(fifo)->sclass = gf100_fifo_sclass; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h index 5190bbc6e1a1..c649ca9b53e3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.h @@ -1,10 +1,15 @@ #ifndef __GF100_FIFO_H__ #define __GF100_FIFO_H__ +#define gf100_fifo(p) container_of((p), struct gf100_fifo, base) #include "priv.h" +#include + struct gf100_fifo { struct nvkm_fifo base; + struct list_head chan; + struct work_struct fault; u64 mask; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 9ab3fd40b7dd..e7f467997194 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -32,23 +32,6 @@ #include -#define _(a,b) { (a), ((1ULL << (a)) | (b)) } -static const struct { - u64 subdev; - u64 mask; -} fifo_engine[] = { - _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_CE2)), - _(NVDEV_ENGINE_MSPDEC , 0), - _(NVDEV_ENGINE_MSPPP , 0), - _(NVDEV_ENGINE_MSVLD , 0), - _(NVDEV_ENGINE_CE0 , 0), - _(NVDEV_ENGINE_CE1 , 0), - _(NVDEV_ENGINE_MSENC , 0), -}; -#undef _ -#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) - static void gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) { @@ -76,28 +59,26 @@ void gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) { struct gk104_fifo_engn *engn = &fifo->engine[engine]; + struct gk104_fifo_chan *chan; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; struct nvkm_memory *cur; - int i, p; + int nr = 0; mutex_lock(&nv_subdev(fifo)->mutex); cur = engn->runlist[engn->cur_runlist]; engn->cur_runlist = !engn->cur_runlist; nvkm_kmap(cur); - for (i = 0, p = 0; i < fifo->base.max; i++) { - struct gk104_fifo_chan *chan = (void *)fifo->base.channel[i]; - if (chan && chan->state == RUNNING && chan->engine == engine) { - nvkm_wo32(cur, p + 0, i); - nvkm_wo32(cur, p + 4, 0x00000000); - p += 8; - } + list_for_each_entry(chan, &engn->chan, head) { + nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid); + nvkm_wo32(cur, (nr * 8) + 4, 0x00000000); + nr++; } nvkm_done(cur); nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12); - nvkm_wr32(device, 0x002274, (engine << 20) | (p >> 3)); + nvkm_wr32(device, 0x002274, (engine << 20) | nr); if (wait_event_timeout(engn->wait, !(nvkm_rd32(device, 0x002284 + (engine * 0x08)) & 0x00100000), @@ -106,31 +87,13 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) mutex_unlock(&nv_subdev(fifo)->mutex); } -static inline int -gk104_fifo_engidx(struct gk104_fifo *fifo, u32 engn) -{ - switch (engn) { - case NVDEV_ENGINE_GR : - case NVDEV_ENGINE_CE2 : engn = 0; break; - case NVDEV_ENGINE_MSVLD : engn = 1; break; - case NVDEV_ENGINE_MSPPP : engn = 2; break; - case NVDEV_ENGINE_MSPDEC: engn = 3; break; - case NVDEV_ENGINE_CE0 : engn = 4; break; - case NVDEV_ENGINE_CE1 : engn = 5; break; - case NVDEV_ENGINE_MSENC : engn = 6; break; - default: - return -1; - } - - return engn; -} - static inline struct nvkm_engine * gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn) { - if (engn >= ARRAY_SIZE(fifo_engine)) - return NULL; - return nvkm_engine(fifo, fifo_engine[engn].subdev); + u64 subdevs = gk104_fifo_engine_subdev(engn); + if (subdevs) + return nvkm_engine(fifo, __ffs(subdevs)); + return NULL; } static void @@ -149,7 +112,7 @@ gk104_fifo_recover_work(struct work_struct *work) spin_unlock_irqrestore(&fifo->base.lock, flags); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) - engm |= 1 << gk104_fifo_engidx(fifo, engn); + engm |= 1 << gk104_fifo_subdev_engine(engn); nvkm_mask(device, 0x002630, engm, engm); for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { @@ -157,7 +120,7 @@ gk104_fifo_recover_work(struct work_struct *work) nvkm_subdev_fini(&engine->subdev, false); WARN_ON(nvkm_subdev_init(&engine->subdev)); } - gk104_fifo_runlist_update(fifo, gk104_fifo_engidx(fifo, engn)); + gk104_fifo_runlist_update(fifo, gk104_fifo_subdev_engine(engn)); } nvkm_wr32(device, 0x00262c, engm); @@ -177,7 +140,8 @@ gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, assert_spin_locked(&fifo->base.lock); nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); - chan->state = KILLED; + list_del_init(&chan->head); + chan->killed = true; fifo->mask |= 1ULL << nv_engidx(engine); schedule_work(&fifo->fault); @@ -223,7 +187,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) u32 engn; spin_lock_irqsave(&fifo->base.lock, flags); - for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) { + for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) { u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); u32 busy = (stat & 0x80000000); u32 next = (stat & 0x07ff0000) >> 16; @@ -235,11 +199,15 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) (void)save; if (busy && chsw) { - if (!(chan = (void *)fifo->base.channel[chid])) - continue; - if (!(engine = gk104_fifo_engine(fifo, engn))) - continue; - gk104_fifo_recover(fifo, engine, chan); + list_for_each_entry(chan, &fifo->engine[engn].chan, head) { + if (chan->base.chid == chid) { + engine = gk104_fifo_engine(fifo, engn); + if (!engine) + break; + gk104_fifo_recover(fifo, engine, chan); + break; + } + } } } spin_unlock_irqrestore(&fifo->base.lock, flags); @@ -444,7 +412,8 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) write ? "write" : "read", (u64)vahi << 32 | valo, unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", reason, er ? er->name : "", chan ? chan->chid : -1, - (u64)inst << 12, nvkm_client_name(chan)); + (u64)inst << 12, + chan ? chan->object.client->name : "unknown"); if (engine && chan) gk104_fifo_recover(fifo, engine, (void *)chan); @@ -498,6 +467,8 @@ gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) u32 subc = (addr & 0x00070000) >> 16; u32 mthd = (addr & 0x00003ffc); u32 show = stat; + struct nvkm_fifo_chan *chan; + unsigned long flags; char msg[128]; if (stat & 0x00800000) { @@ -510,11 +481,13 @@ gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit) if (show) { nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show); - nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%s] subc %d " - "mthd %04x data %08x\n", - unit, show, msg, chid, - nvkm_client_name_for_fifo_chid(&fifo->base, chid), + chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); + nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] " + "subc %d mthd %04x data %08x\n", + unit, show, msg, chid, chan ? chan->inst->addr : 0, + chan ? chan->object.client->name : "unknown", subc, mthd, data); + nvkm_fifo_chan_put(&fifo->base, flags, &chan); } nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); @@ -722,7 +695,7 @@ gk104_fifo_dtor(struct nvkm_object *object) nvkm_vm_put(&fifo->user.bar); nvkm_memory_del(&fifo->user.mem); - for (i = 0; i < FIFO_ENGINE_NR; i++) { + for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) { nvkm_memory_del(&fifo->engine[i].runlist[1]); nvkm_memory_del(&fifo->engine[i].runlist[0]); } @@ -730,6 +703,14 @@ gk104_fifo_dtor(struct nvkm_object *object) nvkm_fifo_destroy(&fifo->base); } +static const struct nvkm_fifo_func +gk104_fifo_func = { + .chan = { + &gk104_fifo_gpfifo_oclass, + NULL + }, +}; + int gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -747,9 +728,11 @@ gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &gk104_fifo_func; + INIT_WORK(&fifo->fault, gk104_fifo_recover_work); - for (i = 0; i < FIFO_ENGINE_NR; i++) { + for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) { ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x8000, 0x1000, false, &fifo->engine[i].runlist[0]); @@ -763,6 +746,7 @@ gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; init_waitqueue_head(&fifo->engine[i].wait); + INIT_LIST_HEAD(&fifo->engine[i].chan); } ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, @@ -783,8 +767,6 @@ gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = gk104_fifo_intr; - nv_engine(fifo)->cclass = &gk104_fifo_cclass; - nv_engine(fifo)->sclass = gk104_fifo_sclass; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index b71abef84349..1103e6b1ee5a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -1,11 +1,15 @@ #ifndef __GK104_FIFO_H__ #define __GK104_FIFO_H__ +#define gk104_fifo(p) container_of((p), struct gk104_fifo, base) #include "priv.h" +#include + struct gk104_fifo_engn { struct nvkm_memory *runlist[2]; int cur_runlist; wait_queue_head_t wait; + struct list_head chan; }; struct gk104_fifo { @@ -38,4 +42,42 @@ void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine); int gm204_fifo_ctor(struct nvkm_object *, struct nvkm_object *, struct nvkm_oclass *, void *, u32, struct nvkm_object **); + +static inline u64 +gk104_fifo_engine_subdev(int engine) +{ + switch (engine) { + case 0: return (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_SW) | + (1ULL << NVDEV_ENGINE_CE2); + case 1: return (1ULL << NVDEV_ENGINE_MSPDEC); + case 2: return (1ULL << NVDEV_ENGINE_MSPPP); + case 3: return (1ULL << NVDEV_ENGINE_MSVLD); + case 4: return (1ULL << NVDEV_ENGINE_CE0); + case 5: return (1ULL << NVDEV_ENGINE_CE1); + case 6: return (1ULL << NVDEV_ENGINE_MSENC); + default: + WARN_ON(1); + return 0; + } +} + +static inline int +gk104_fifo_subdev_engine(int subdev) +{ + switch (subdev) { + case NVDEV_ENGINE_GR: + case NVDEV_ENGINE_SW: + case NVDEV_ENGINE_CE2 : return 0; + case NVDEV_ENGINE_MSPDEC: return 1; + case NVDEV_ENGINE_MSPPP : return 2; + case NVDEV_ENGINE_MSVLD : return 3; + case NVDEV_ENGINE_CE0 : return 4; + case NVDEV_ENGINE_CE1 : return 5; + case NVDEV_ENGINE_MSENC : return 6; + default: + WARN_ON(1); + return 0; + } +} #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c index 2367b4f81a91..18c68ac741a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c @@ -24,6 +24,14 @@ #include "gk104.h" #include "changk104.h" +static const struct nvkm_fifo_func +gm204_fifo_func = { + .chan = { + &gm204_fifo_gpfifo_oclass, + NULL + }, +}; + int gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -32,7 +40,7 @@ gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); if (ret == 0) { struct gk104_fifo *fifo = (void *)*pobject; - nv_engine(fifo)->sclass = gm204_fifo_sclass; + fifo->base.func = &gm204_fifo_func; } return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c index fd11e0afec25..820132363f68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c @@ -30,15 +30,14 @@ #include static int -g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +g84_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; u64 ioffset, ilength; int ret; @@ -50,73 +49,46 @@ g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, "ilength %08x\n", args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.ioffset, args->v0.ilength); - if (args->v0.vm) - return -ENOENT; + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_VP) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_VIC), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); + ret = g84_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, + oclass, chan); if (ret) return ret; - nv_parent(chan)->context_attach = g84_fifo_context_attach; - nv_parent(chan)->context_detach = g84_fifo_context_detach; - nv_parent(chan)->object_attach = g84_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; - + args->v0.chid = chan->base.chid; ioffset = args->v0.ioffset; ilength = order_base_2(args->v0.ilength / 8); - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); - nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + nvkm_kmap(chan->ramfc); + nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); + nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); + nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); + nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); + nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); + nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(chan->ramfc, 0x78, 0x00000000); + nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); + nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_wo32(base->ramfc, 0x88, base->cache->addr >> 10); - nvkm_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); - nvkm_done(base->ramfc); + nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); + nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); + nvkm_done(chan->ramfc); return 0; } -struct nvkm_ofuncs -g84_fifo_ofuncs_ind = { - .ctor = g84_fifo_chan_ctor_ind, - .dtor = nv50_fifo_chan_dtor, - .init = g84_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy +const struct nvkm_fifo_chan_oclass +g84_fifo_gpfifo_oclass = { + .base.oclass = G82_CHANNEL_GPFIFO, + .base.minver = 0, + .base.maxver = 0, + .ctor = g84_fifo_gpfifo_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index 7fd6401ca905..eb9195a6f375 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -30,29 +30,33 @@ #include #include -static int -gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) +static u32 +gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { - struct gf100_fifo *fifo = (void *)parent->engine; - struct gf100_fifo_base *base = (void *)parent->parent; - struct gf100_fifo_chan *chan = (void *)parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 addr; - - switch (nv_engidx(object->engine)) { + switch (engine->subdev.index) { case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_CE0 : addr = 0x0230; break; - case NVDEV_ENGINE_CE1 : addr = 0x0240; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; + case NVDEV_ENGINE_GR : return 0x0210; + case NVDEV_ENGINE_CE0 : return 0x0230; + case NVDEV_ENGINE_CE1 : return 0x0240; + case NVDEV_ENGINE_MSPDEC: return 0x0250; + case NVDEV_ENGINE_MSPPP : return 0x0260; + case NVDEV_ENGINE_MSVLD : return 0x0270; default: - return -EINVAL; + WARN_ON(1); + return 0; } +} + +static int +gf100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, bool suspend) +{ + const u32 offset = gf100_fifo_gpfifo_engine_addr(engine); + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + struct nvkm_subdev *subdev = &chan->fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_gpuobj *inst = chan->base.inst; + int ret = 0; nvkm_wr32(device, 0x002634, chan->base.chid); if (nvkm_msec(device, 2000, @@ -60,143 +64,197 @@ gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, break; ) < 0) { nvkm_error(subdev, "channel %d [%s] kick timeout\n", - chan->base.chid, nvkm_client_name(chan)); + chan->base.chid, chan->base.object.client->name); + ret = -EBUSY; if (suspend) - return -EBUSY; + return ret; + } + + if (offset) { + nvkm_kmap(inst); + nvkm_wo32(inst, offset + 0x00, 0x00000000); + nvkm_wo32(inst, offset + 0x04, 0x00000000); + nvkm_done(inst); + } + + return ret; +} + +static int +gf100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) +{ + const u32 offset = gf100_fifo_gpfifo_engine_addr(engine); + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + struct nvkm_gpuobj *inst = chan->base.inst; + + if (offset) { + u64 addr = chan->engn[engine->subdev.index].vma.offset; + nvkm_kmap(inst); + nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); + nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); + nvkm_done(inst); } - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, 0x00000000); - nvkm_wo32(engn, addr + 0x04, 0x00000000); - nvkm_done(engn); return 0; } +static void +gf100_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) +{ + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma); + nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); +} + static int -gf100_fifo_context_attach(struct nvkm_object *parent, - struct nvkm_object *object) +gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, + struct nvkm_object *object) { - struct gf100_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - struct nvkm_engctx *ectx = (void *)object; - u32 addr; + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + int engn = engine->subdev.index; int ret; - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_CE0 : addr = 0x0230; break; - case NVDEV_ENGINE_CE1 : addr = 0x0240; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; - default: - return -EINVAL; - } - - if (!ectx->vma.node) { - ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); - if (ret) - return ret; + if (!gf100_fifo_gpfifo_engine_addr(engine)) + return 0; - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + if (object->oclass) { + return nvkm_gpuobj_map(nv_gpuobj(object), chan->vm, + NV_MEM_ACCESS_RW, + &chan->engn[engn].vma); } - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); - nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); - nvkm_done(engn); - return 0; + ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); + if (ret) + return ret; + + return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm, + NV_MEM_ACCESS_RW, &chan->engn[engn].vma); } -static int -gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) +static void +gf100_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) { - struct gf100_fifo *fifo = (void *)object->engine; - struct gf100_fifo_chan *chan = (void *)object; + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + struct gf100_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; + u32 coff = chan->base.chid * 8; - if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { - nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000); + if (!list_empty(&chan->head) && !chan->killed) { + list_del_init(&chan->head); + nvkm_mask(device, 0x003004 + coff, 0x00000001, 0x00000000); gf100_fifo_runlist_update(fifo); } gf100_fifo_intr_engine(fifo); - nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000); - return nvkm_fifo_channel_fini(&chan->base, suspend); + nvkm_wr32(device, 0x003000 + coff, 0x00000000); } -static int -gf100_fifo_chan_init(struct nvkm_object *object) +static void +gf100_fifo_gpfifo_init(struct nvkm_fifo_chan *base) { - struct nvkm_gpuobj *base = nv_gpuobj(object->parent); - struct gf100_fifo *fifo = (void *)object->engine; - struct gf100_fifo_chan *chan = (void *)object; + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + struct gf100_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - int ret; - - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; + u32 addr = chan->base.inst->addr >> 12; + u32 coff = chan->base.chid * 8; - nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); + nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr); - if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { - nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001); + if (list_empty(&chan->head) && !chan->killed) { + list_add_tail(&chan->head, &fifo->chan); + nvkm_wr32(device, 0x003004 + coff, 0x001f0001); gf100_fifo_runlist_update(fifo); } +} - return 0; +static void * +gf100_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) +{ + struct gf100_fifo_chan *chan = gf100_fifo_chan(base); + nvkm_vm_ref(NULL, &chan->vm, chan->pgd); + nvkm_gpuobj_del(&chan->pgd); + return chan; } +static const struct nvkm_fifo_chan_func +gf100_fifo_gpfifo_func = { + .dtor = gf100_fifo_gpfifo_dtor, + .init = gf100_fifo_gpfifo_init, + .fini = gf100_fifo_gpfifo_fini, + .ntfy = g84_fifo_chan_ntfy, + .engine_ctor = gf100_fifo_gpfifo_engine_ctor, + .engine_dtor = gf100_fifo_gpfifo_engine_dtor, + .engine_init = gf100_fifo_gpfifo_engine_init, + .engine_fini = gf100_fifo_gpfifo_engine_fini, +}; + static int -gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { union { struct fermi_channel_gpfifo_v0 v0; } *args = data; - struct gf100_fifo *fifo = (void *)engine; - struct gf100_fifo_base *base = (void *)parent; + struct gf100_fifo *fifo = gf100_fifo(base); + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_object *parent = oclass->parent; struct gf100_fifo_chan *chan; - struct nvkm_gpuobj *ramfc = &base->base.gpuobj; u64 usermem, ioffset, ilength; int ret, i; nvif_ioctl(parent, "create channel gpfifo size %d\n", size); if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx" + nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " "ioffset %016llx ilength %08x\n", args->v0.version, args->v0.vm, args->v0.ioffset, args->v0.ilength); - if (args->v0.vm) - return -ENOENT; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, - fifo->user.bar.offset, 0x1000, 0, - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_CE1) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP), &chan); - *pobject = nv_object(chan); + /* allocate channel */ + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + chan->fifo = fifo; + INIT_LIST_HEAD(&chan->head); + + ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, + 0x1000, 0x1000, true, args->v0.vm, 0, + (1ULL << NVDEV_ENGINE_CE0) | + (1ULL << NVDEV_ENGINE_CE1) | + (1ULL << NVDEV_ENGINE_GR) | + (1ULL << NVDEV_ENGINE_MSPDEC) | + (1ULL << NVDEV_ENGINE_MSPPP) | + (1ULL << NVDEV_ENGINE_MSVLD) | + (1ULL << NVDEV_ENGINE_SW), + 1, fifo->user.bar.offset, 0x1000, + oclass, &chan->base); if (ret) return ret; - chan->base.inst = base->base.gpuobj.addr; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = gf100_fifo_context_attach; - nv_parent(chan)->context_detach = gf100_fifo_context_detach; + /* page directory */ + ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd); + if (ret) + return ret; + + nvkm_kmap(chan->base.inst); + nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr)); + nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr)); + nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff); + nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff); + nvkm_done(chan->base.inst); + + ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); + if (ret) + return ret; + + /* clear channel control registers */ usermem = chan->base.chid * 0x1000; ioffset = args->v0.ioffset; @@ -208,97 +266,33 @@ gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_done(fifo->user.mem); usermem = nvkm_memory_addr(fifo->user.mem) + usermem; - nvkm_kmap(ramfc); - nvkm_wo32(ramfc, 0x08, lower_32_bits(usermem)); - nvkm_wo32(ramfc, 0x0c, upper_32_bits(usermem)); - nvkm_wo32(ramfc, 0x10, 0x0000face); - nvkm_wo32(ramfc, 0x30, 0xfffff902); - nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); - nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(ramfc, 0x54, 0x00000002); - nvkm_wo32(ramfc, 0x84, 0x20400000); - nvkm_wo32(ramfc, 0x94, 0x30000001); - nvkm_wo32(ramfc, 0x9c, 0x00000100); - nvkm_wo32(ramfc, 0xa4, 0x1f1f1f1f); - nvkm_wo32(ramfc, 0xa8, 0x1f1f1f1f); - nvkm_wo32(ramfc, 0xac, 0x0000001f); - nvkm_wo32(ramfc, 0xb8, 0xf8000000); - nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ - nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ - nvkm_done(ramfc); - return 0; -} - -static struct nvkm_ofuncs -gf100_fifo_ofuncs = { - .ctor = gf100_fifo_chan_ctor, - .dtor = _nvkm_fifo_channel_dtor, - .init = gf100_fifo_chan_init, - .fini = gf100_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -gf100_fifo_sclass[] = { - { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, - {} -}; - -static int -gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct gf100_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC | - NVOBJ_FLAG_HEAP, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd); - if (ret) - return ret; - - nvkm_kmap(&base->base.gpuobj); - nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); - nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); - nvkm_done(&base->base.gpuobj); - - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); - if (ret) - return ret; - + /* RAMFC */ + nvkm_kmap(chan->base.inst); + nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); + nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); + nvkm_wo32(chan->base.inst, 0x10, 0x0000face); + nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); + nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); + nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | + (ilength << 16)); + nvkm_wo32(chan->base.inst, 0x54, 0x00000002); + nvkm_wo32(chan->base.inst, 0x84, 0x20400000); + nvkm_wo32(chan->base.inst, 0x94, 0x30000001); + nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); + nvkm_wo32(chan->base.inst, 0xa4, 0x1f1f1f1f); + nvkm_wo32(chan->base.inst, 0xa8, 0x1f1f1f1f); + nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); + nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); + nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ + nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */ + nvkm_done(chan->base.inst); return 0; } -static void -gf100_fifo_context_dtor(struct nvkm_object *object) -{ - struct gf100_fifo_base *base = (void *)object; - nvkm_vm_ref(NULL, &base->vm, base->pgd); - nvkm_gpuobj_del(&base->pgd); - nvkm_fifo_context_destroy(&base->base); -} - -struct nvkm_oclass -gf100_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_fifo_context_ctor, - .dtor = gf100_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, +const struct nvkm_fifo_chan_oclass +gf100_fifo_gpfifo_oclass = { + .base.oclass = FERMI_CHANNEL_GPFIFO, + .base.minver = 0, + .base.maxver = 0, + .ctor = gf100_fifo_gpfifo_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 264c9705bccc..2595cf92ff80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -31,30 +31,13 @@ #include #include -#define _(a,b) { (a), ((1ULL << (a)) | (b)) } -static const struct { - u64 subdev; - u64 mask; -} fifo_engine[] = { - _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_CE2)), - _(NVDEV_ENGINE_MSPDEC , 0), - _(NVDEV_ENGINE_MSPPP , 0), - _(NVDEV_ENGINE_MSVLD , 0), - _(NVDEV_ENGINE_CE0 , 0), - _(NVDEV_ENGINE_CE1 , 0), - _(NVDEV_ENGINE_MSENC , 0), -}; -#undef _ -#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) - static int -gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) +gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan) { - struct nvkm_object *obj = (void *)chan; - struct gk104_fifo *fifo = (void *)obj->engine; + struct gk104_fifo *fifo = chan->fifo; struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; + struct nvkm_client *client = chan->base.object.client; nvkm_wr32(device, 0x002634, chan->base.chid); if (nvkm_msec(device, 2000, @@ -62,198 +45,249 @@ gk104_fifo_chan_kick(struct gk104_fifo_chan *chan) break; ) < 0) { nvkm_error(subdev, "channel %d [%s] kick timeout\n", - chan->base.chid, nvkm_client_name(chan)); + chan->base.chid, client->name); return -EBUSY; } return 0; } -static int -gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, - struct nvkm_object *object) +static u32 +gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { - struct gk104_fifo_base *base = (void *)parent->parent; - struct gk104_fifo_chan *chan = (void *)parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - u32 addr; - int ret; - - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : return 0; + switch (engine->subdev.index) { + case NVDEV_ENGINE_SW : case NVDEV_ENGINE_CE0 : case NVDEV_ENGINE_CE1 : - case NVDEV_ENGINE_CE2 : addr = 0x0000; break; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; + case NVDEV_ENGINE_CE2 : return 0x0000; + case NVDEV_ENGINE_GR : return 0x0210; + case NVDEV_ENGINE_MSPDEC: return 0x0250; + case NVDEV_ENGINE_MSPPP : return 0x0260; + case NVDEV_ENGINE_MSVLD : return 0x0270; default: - return -EINVAL; + WARN_ON(1); + return 0; } +} - ret = gk104_fifo_chan_kick(chan); +static int +gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, bool suspend) +{ + const u32 offset = gk104_fifo_gpfifo_engine_addr(engine); + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct nvkm_gpuobj *inst = chan->base.inst; + int ret; + + ret = gk104_fifo_gpfifo_kick(chan); if (ret && suspend) return ret; - if (addr) { - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, 0x00000000); - nvkm_wo32(engn, addr + 0x04, 0x00000000); - nvkm_done(engn); + if (offset) { + nvkm_kmap(inst); + nvkm_wo32(inst, offset + 0x00, 0x00000000); + nvkm_wo32(inst, offset + 0x04, 0x00000000); + nvkm_done(inst); + } + + return ret; +} + +static int +gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) +{ + const u32 offset = gk104_fifo_gpfifo_engine_addr(engine); + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct nvkm_gpuobj *inst = chan->base.inst; + + if (offset) { + u64 addr = chan->engn[engine->subdev.index].vma.offset; + nvkm_kmap(inst); + nvkm_wo32(inst, offset + 0x00, lower_32_bits(addr) | 4); + nvkm_wo32(inst, offset + 0x04, upper_32_bits(addr)); + nvkm_done(inst); } return 0; } +static void +gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine) +{ + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + nvkm_gpuobj_unmap(&chan->engn[engine->subdev.index].vma); + nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst); +} + static int -gk104_fifo_context_attach(struct nvkm_object *parent, - struct nvkm_object *object) +gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, + struct nvkm_engine *engine, + struct nvkm_object *object) { - struct gk104_fifo_base *base = (void *)parent->parent; - struct nvkm_gpuobj *engn = &base->base.gpuobj; - struct nvkm_engctx *ectx = (void *)object; - u32 addr; + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + int engn = engine->subdev.index; int ret; - switch (nv_engidx(object->engine)) { - case NVDEV_ENGINE_SW : - return 0; - case NVDEV_ENGINE_CE0: - case NVDEV_ENGINE_CE1: - case NVDEV_ENGINE_CE2: - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + if (!gk104_fifo_gpfifo_engine_addr(engine)) return 0; - case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; - case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; - case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; - default: - return -EINVAL; - } - if (!ectx->vma.node) { - ret = nvkm_gpuobj_map(nv_gpuobj(ectx), base->vm, - NV_MEM_ACCESS_RW, &ectx->vma); - if (ret) - return ret; - - nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; + if (object->oclass) { + return nvkm_gpuobj_map(nv_gpuobj(object), chan->vm, + NV_MEM_ACCESS_RW, + &chan->engn[engn].vma); } - nvkm_kmap(engn); - nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); - nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); - nvkm_done(engn); - return 0; + ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); + if (ret) + return ret; + + return nvkm_gpuobj_map(chan->engn[engn].inst, chan->vm, + NV_MEM_ACCESS_RW, &chan->engn[engn].vma); } -static int -gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend) +static void +gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base) { - struct gk104_fifo *fifo = (void *)object->engine; - struct gk104_fifo_chan *chan = (void *)object; + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct gk104_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; + u32 coff = chan->base.chid * 8; - if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { - nvkm_mask(device, 0x800004 + (chid * 8), 0x00000800, 0x00000800); + if (!list_empty(&chan->head)) { + list_del_init(&chan->head); + nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800); gk104_fifo_runlist_update(fifo, chan->engine); } - nvkm_wr32(device, 0x800000 + (chid * 8), 0x00000000); - return nvkm_fifo_channel_fini(&chan->base, suspend); + nvkm_wr32(device, 0x800000 + coff, 0x00000000); } -static int -gk104_fifo_chan_init(struct nvkm_object *object) +static void +gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base) { - struct nvkm_gpuobj *base = nv_gpuobj(object->parent); - struct gk104_fifo *fifo = (void *)object->engine; - struct gk104_fifo_chan *chan = (void *)object; + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + struct gk104_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; - u32 chid = chan->base.chid; - int ret; + u32 addr = chan->base.inst->addr >> 12; + u32 coff = chan->base.chid * 8; - ret = nvkm_fifo_channel_init(&chan->base); - if (ret) - return ret; + nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->engine << 16); + nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr); - nvkm_mask(device, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); - nvkm_wr32(device, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); - - if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { - nvkm_mask(device, 0x800004 + (chid * 8), 0x00000400, 0x00000400); + if (list_empty(&chan->head) && !chan->killed) { + list_add_tail(&chan->head, &fifo->engine[chan->engine].chan); + nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); gk104_fifo_runlist_update(fifo, chan->engine); - nvkm_mask(device, 0x800004 + (chid * 8), 0x00000400, 0x00000400); + nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400); } +} - return 0; +static void * +gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base) +{ + struct gk104_fifo_chan *chan = gk104_fifo_chan(base); + nvkm_vm_ref(NULL, &chan->vm, chan->pgd); + nvkm_gpuobj_del(&chan->pgd); + return chan; } -static int -gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_fifo_chan_func +gk104_fifo_gpfifo_func = { + .dtor = gk104_fifo_gpfifo_dtor, + .init = gk104_fifo_gpfifo_init, + .fini = gk104_fifo_gpfifo_fini, + .ntfy = g84_fifo_chan_ntfy, + .engine_ctor = gk104_fifo_gpfifo_engine_ctor, + .engine_dtor = gk104_fifo_gpfifo_engine_dtor, + .engine_init = gk104_fifo_gpfifo_engine_init, + .engine_fini = gk104_fifo_gpfifo_engine_fini, +}; + +int +gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { union { struct kepler_channel_gpfifo_a_v0 v0; } *args = data; - struct gk104_fifo *fifo = (void *)engine; - struct gk104_fifo_base *base = (void *)parent; + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_object *parent = oclass->parent; struct gk104_fifo_chan *chan; - struct nvkm_gpuobj *ramfc = &base->base.gpuobj; u64 usermem, ioffset, ilength; u32 engines; int ret, i; nvif_ioctl(parent, "create channel gpfifo size %d\n", size); if (nvif_unpack(args->v0, 0, 0, false)) { - nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx" + nvif_ioctl(parent, "create channel gpfifo vers %d vm %llx " "ioffset %016llx ilength %08x engine %08x\n", args->v0.version, args->v0.vm, args->v0.ioffset, args->v0.ilength, args->v0.engine); - if (args->v0.vm) - return -ENOENT; } else return ret; - for (i = 0, engines = 0; i < FIFO_ENGINE_NR; i++) { - if (!nvkm_engine(parent, fifo_engine[i].subdev)) + /* determine which downstream engines are present */ + for (i = 0, engines = 0; i < ARRAY_SIZE(fifo->engine); i++) { + u64 subdevs = gk104_fifo_engine_subdev(i); + if (!nvkm_device_engine(device, __ffs64(subdevs))) continue; engines |= (1 << i); } + /* if this is an engine mask query, we're done */ if (!args->v0.engine) { - static struct nvkm_oclass oclass = { - .ofuncs = &nvkm_object_ofuncs, - }; args->v0.engine = engines; - return nvkm_object_old(parent, engine, &oclass, NULL, 0, pobject); + return nvkm_object_new(oclass, NULL, 0, pobject); } - engines &= args->v0.engine; - if (!engines) { - nvif_ioctl(parent, "unsupported engines %08x\n", - args->v0.engine); + /* check that we support a requested engine - note that the user + * argument is a mask in order to allow the user to request (for + * example) *any* copy engine, but doesn't matter which. + */ + args->v0.engine &= engines; + if (!args->v0.engine) { + nvif_ioctl(parent, "no supported engine\n"); return -ENODEV; } - i = __ffs(engines); - ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, - fifo->user.bar.offset, 0x200, 0, - fifo_engine[i].mask, &chan); - *pobject = nv_object(chan); + /* allocate the channel */ + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; + chan->fifo = fifo; + chan->engine = __ffs(args->v0.engine); + INIT_LIST_HEAD(&chan->head); + + ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base, + 0x1000, 0x1000, true, args->v0.vm, 0, + gk104_fifo_engine_subdev(chan->engine), + 1, fifo->user.bar.offset, 0x200, + oclass, &chan->base); if (ret) return ret; - chan->base.inst = base->base.gpuobj.addr; args->v0.chid = chan->base.chid; - nv_parent(chan)->context_attach = gk104_fifo_context_attach; - nv_parent(chan)->context_detach = gk104_fifo_context_detach; - chan->engine = i; + /* page directory */ + ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &chan->pgd); + if (ret) + return ret; + + nvkm_kmap(chan->base.inst); + nvkm_wo32(chan->base.inst, 0x0200, lower_32_bits(chan->pgd->addr)); + nvkm_wo32(chan->base.inst, 0x0204, upper_32_bits(chan->pgd->addr)); + nvkm_wo32(chan->base.inst, 0x0208, 0xffffffff); + nvkm_wo32(chan->base.inst, 0x020c, 0x000000ff); + nvkm_done(chan->base.inst); + ret = nvkm_vm_ref(chan->base.vm, &chan->vm, chan->pgd); + if (ret) + return ret; + + /* clear channel control registers */ usermem = chan->base.chid * 0x200; ioffset = args->v0.ioffset; ilength = order_base_2(args->v0.ilength / 8); @@ -264,94 +298,31 @@ gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_done(fifo->user.mem); usermem = nvkm_memory_addr(fifo->user.mem) + usermem; - nvkm_kmap(ramfc); - nvkm_wo32(ramfc, 0x08, lower_32_bits(usermem)); - nvkm_wo32(ramfc, 0x0c, upper_32_bits(usermem)); - nvkm_wo32(ramfc, 0x10, 0x0000face); - nvkm_wo32(ramfc, 0x30, 0xfffff902); - nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); - nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(ramfc, 0x84, 0x20400000); - nvkm_wo32(ramfc, 0x94, 0x30000001); - nvkm_wo32(ramfc, 0x9c, 0x00000100); - nvkm_wo32(ramfc, 0xac, 0x0000001f); - nvkm_wo32(ramfc, 0xe8, chan->base.chid); - nvkm_wo32(ramfc, 0xb8, 0xf8000000); - nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ - nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ - nvkm_done(ramfc); - return 0; -} - -struct nvkm_ofuncs -gk104_fifo_chan_ofuncs = { - .ctor = gk104_fifo_chan_ctor, - .dtor = _nvkm_fifo_channel_dtor, - .init = gk104_fifo_chan_init, - .fini = gk104_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy -}; - -struct nvkm_oclass -gk104_fifo_sclass[] = { - { KEPLER_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, - {} -}; - -static int -gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = nv_engine(engine)->subdev.device; - struct gk104_fifo_base *base; - int ret; - - ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, - 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); - *pobject = nv_object(base); - if (ret) - return ret; - - ret = nvkm_gpuobj_new(device, 0x10000, 0x1000, false, NULL, &base->pgd); - if (ret) - return ret; - - nvkm_kmap(&base->base.gpuobj); - nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); - nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); - nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); - nvkm_done(&base->base.gpuobj); - - ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); - if (ret) - return ret; - + /* RAMFC */ + nvkm_kmap(chan->base.inst); + nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem)); + nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem)); + nvkm_wo32(chan->base.inst, 0x10, 0x0000face); + nvkm_wo32(chan->base.inst, 0x30, 0xfffff902); + nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); + nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | + (ilength << 16)); + nvkm_wo32(chan->base.inst, 0x84, 0x20400000); + nvkm_wo32(chan->base.inst, 0x94, 0x30000001); + nvkm_wo32(chan->base.inst, 0x9c, 0x00000100); + nvkm_wo32(chan->base.inst, 0xac, 0x0000001f); + nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid); + nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000); + nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */ + nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */ + nvkm_done(chan->base.inst); return 0; } -static void -gk104_fifo_context_dtor(struct nvkm_object *object) -{ - struct gk104_fifo_base *base = (void *)object; - nvkm_vm_ref(NULL, &base->vm, base->pgd); - nvkm_gpuobj_del(&base->pgd); - nvkm_fifo_context_destroy(&base->base); -} - -struct nvkm_oclass -gk104_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0xe0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_fifo_context_ctor, - .dtor = gk104_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, +const struct nvkm_fifo_chan_oclass +gk104_fifo_gpfifo_oclass = { + .base.oclass = KEPLER_CHANNEL_GPFIFO_A, + .base.minver = 0, + .base.maxver = 0, + .ctor = gk104_fifo_gpfifo_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c index 7beee1f8729a..6511d6e21ecc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogm204.c @@ -25,8 +25,10 @@ #include -struct nvkm_oclass -gm204_fifo_sclass[] = { - { MAXWELL_CHANNEL_GPFIFO_A, &gk104_fifo_chan_ofuncs }, - {} +const struct nvkm_fifo_chan_oclass +gm204_fifo_gpfifo_oclass = { + .base.oclass = MAXWELL_CHANNEL_GPFIFO_A, + .base.minver = 0, + .base.maxver = 0, + .ctor = gk104_fifo_gpfifo_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c index ca7de9a6d67f..a8c69f878221 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c @@ -30,15 +30,14 @@ #include static int -nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv50_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, + void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_object *parent = oclass->parent; union { struct nv50_channel_gpfifo_v0 v0; } *args = data; - struct nvkm_device *device = parent->engine->subdev.device; - struct nv50_fifo_base *base = (void *)parent; + struct nv50_fifo *fifo = nv50_fifo(base); struct nv50_fifo_chan *chan; u64 ioffset, ilength; int ret; @@ -50,61 +49,44 @@ nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, "ilength %08x\n", args->v0.version, args->v0.vm, args->v0.pushbuf, args->v0.ioffset, args->v0.ilength); - if (args->v0.vm) - return -ENOENT; + if (!args->v0.pushbuf) + return -EINVAL; } else return ret; - ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, - 0x2000, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->base.inst = base->base.gpuobj.addr; - args->v0.chid = chan->base.chid; - - nv_parent(chan)->context_attach = nv50_fifo_context_attach; - nv_parent(chan)->context_detach = nv50_fifo_context_detach; - nv_parent(chan)->object_attach = nv50_fifo_object_attach; - nv_parent(chan)->object_detach = nv50_fifo_object_detach; + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + *pobject = &chan->base.object; - ret = nvkm_ramht_new(device, 0x8000, 16, &base->base.gpuobj, - &chan->ramht); + ret = nv50_fifo_chan_ctor(fifo, args->v0.vm, args->v0.pushbuf, + oclass, chan); if (ret) return ret; + args->v0.chid = chan->base.chid; ioffset = args->v0.ioffset; ilength = order_base_2(args->v0.ilength / 8); - nvkm_kmap(base->ramfc); - nvkm_wo32(base->ramfc, 0x3c, 0x403f6078); - nvkm_wo32(base->ramfc, 0x44, 0x01003fff); - nvkm_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); - nvkm_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); - nvkm_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); - nvkm_wo32(base->ramfc, 0x60, 0x7fffffff); - nvkm_wo32(base->ramfc, 0x78, 0x00000000); - nvkm_wo32(base->ramfc, 0x7c, 0x30000001); - nvkm_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | + nvkm_kmap(chan->ramfc); + nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); + nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); + nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); + nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); + nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); + nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); + nvkm_wo32(chan->ramfc, 0x78, 0x00000000); + nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); + nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | (4 << 24) /* SEARCH_FULL */ | (chan->ramht->gpuobj->node->offset >> 4)); - nvkm_done(base->ramfc); + nvkm_done(chan->ramfc); return 0; } -struct nvkm_ofuncs -nv50_fifo_ofuncs_ind = { - .ctor = nv50_fifo_chan_ctor_ind, - .dtor = nv50_fifo_chan_dtor, - .init = nv50_fifo_chan_init, - .fini = nv50_fifo_chan_fini, - .map = _nvkm_fifo_channel_map, - .rd32 = _nvkm_fifo_channel_rd32, - .wr32 = _nvkm_fifo_channel_wr32, - .ntfy = _nvkm_fifo_channel_ntfy +const struct nvkm_fifo_chan_oclass +nv50_fifo_gpfifo_oclass = { + .base.oclass = NV50_CHANNEL_GPFIFO, + .base.minver = 0, + .base.maxver = 0, + .ctor = nv50_fifo_gpfifo_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index d880cfa6de9e..d1ad3fa72c34 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -25,6 +25,7 @@ #include "channv04.h" #include "regsnv04.h" +#include #include #include #include @@ -136,6 +137,8 @@ nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get) { struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; + struct nvkm_fifo_chan *chan; + unsigned long flags; u32 pull0 = nvkm_rd32(device, 0x003250); u32 mthd, data; int ptr; @@ -157,12 +160,12 @@ nv04_fifo_cache_error(struct nv04_fifo *fifo, u32 chid, u32 get) if (!(pull0 & 0x00000100) || !nv04_fifo_swmthd(device, chid, mthd, data)) { - const char *client_name = - nvkm_client_name_for_fifo_chid(&fifo->base, chid); + chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); nvkm_error(subdev, "CACHE_ERROR - " "ch %d [%s] subc %d mthd %04x data %08x\n", - chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, - data); + chid, chan ? chan->object.client->name : "unknown", + (mthd >> 13) & 7, mthd & 0x1ffc, data); + nvkm_fifo_chan_put(&fifo->base, flags, &chan); } nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); @@ -189,10 +192,12 @@ nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) u32 dma_put = nvkm_rd32(device, 0x003240); u32 push = nvkm_rd32(device, 0x003220); u32 state = nvkm_rd32(device, 0x003228); - const char *client_name; - - client_name = nvkm_client_name_for_fifo_chid(&fifo->base, chid); + struct nvkm_fifo_chan *chan; + unsigned long flags; + const char *name; + chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags); + name = chan ? chan->object.client->name : "unknown"; if (device->card_type == NV_50) { u32 ho_get = nvkm_rd32(device, 0x003328); u32 ho_put = nvkm_rd32(device, 0x003320); @@ -202,7 +207,7 @@ nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) nvkm_error(subdev, "DMA_PUSHER - " "ch %d [%s] get %02x%08x put %02x%08x ib_get %08x " "ib_put %08x state %08x (err: %s) push %08x\n", - chid, client_name, ho_get, dma_get, ho_put, dma_put, + chid, name, ho_get, dma_get, ho_put, dma_put, ib_get, ib_put, state, nv_dma_state_err(state), push); @@ -217,12 +222,13 @@ nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) } else { nvkm_error(subdev, "DMA_PUSHER - ch %d [%s] get %08x put %08x " "state %08x (err: %s) push %08x\n", - chid, client_name, dma_get, dma_put, state, + chid, name, dma_get, dma_put, state, nv_dma_state_err(state), push); if (dma_get != dma_put) nvkm_wr32(device, 0x003244, dma_put); } + nvkm_fifo_chan_put(&fifo->base, flags, &chan); nvkm_wr32(device, 0x003228, 0x00000000); nvkm_wr32(device, 0x003220, 0x00000001); @@ -241,7 +247,7 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; nvkm_wr32(device, NV03_PFIFO_CACHES, 0); - chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & fifo->base.max; + chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1); get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); if (stat & NV_PFIFO_INTR_CACHE_ERROR) { @@ -311,7 +317,7 @@ nv04_fifo_init(struct nvkm_object *object) nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); @@ -329,6 +335,14 @@ nv04_fifo_dtor(struct nvkm_object *object) nvkm_fifo_destroy(&fifo->base); } +static const struct nvkm_fifo_func +nv04_fifo_func = { + .chan = { + &nv04_fifo_dma_oclass, + NULL + }, +}; + static int nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -342,10 +356,10 @@ nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &nv04_fifo_func; + nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv04_fifo_cclass; - nv_engine(fifo)->sclass = nv04_fifo_sclass; fifo->base.pause = nv04_fifo_pause; fifo->base.start = nv04_fifo_start; fifo->ramfc_desc = nv04_ramfc; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index 5cde3310ee4d..c33dc56f8e02 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -1,5 +1,6 @@ #ifndef __NV04_FIFO_H__ #define __NV04_FIFO_H__ +#define nv04_fifo(p) container_of((p), struct nv04_fifo, base) #include "priv.h" struct ramfc_desc { @@ -15,14 +16,6 @@ struct nv04_fifo { struct ramfc_desc *ramfc_desc; }; -struct nv04_fifo_base { - struct nvkm_fifo_base base; -}; - -int nv04_fifo_context_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); - void nv04_fifo_dtor(struct nvkm_object *); int nv04_fifo_init(struct nvkm_object *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index ae0a1b17eb92..d7fab9598fb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -39,16 +39,11 @@ nv10_ramfc[] = { {} }; -static struct nvkm_oclass -nv10_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x10), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fifo_context_ctor, - .dtor = _nvkm_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, +static const struct nvkm_fifo_func +nv10_fifo_func = { + .chan = { + &nv10_fifo_dma_oclass, + NULL }, }; @@ -65,10 +60,10 @@ nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &nv10_fifo_func; + nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv10_fifo_cclass; - nv_engine(fifo)->sclass = nv10_fifo_sclass; fifo->base.pause = nv04_fifo_pause; fifo->base.start = nv04_fifo_start; fifo->ramfc_desc = nv10_ramfc; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index ff2b6d95d804..a8e28fc24e75 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -47,19 +47,6 @@ nv17_ramfc[] = { {} }; -static struct nvkm_oclass -nv17_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x17), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fifo_context_ctor, - .dtor = _nvkm_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; - static int nv17_fifo_init(struct nvkm_object *object) { @@ -85,7 +72,7 @@ nv17_fifo_init(struct nvkm_object *object) nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | 0x00010000); - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); @@ -96,6 +83,14 @@ nv17_fifo_init(struct nvkm_object *object) return 0; } +static const struct nvkm_fifo_func +nv17_fifo_func = { + .chan = { + &nv17_fifo_dma_oclass, + NULL + }, +}; + static int nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -109,10 +104,10 @@ nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &nv17_fifo_func; + nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv17_fifo_cclass; - nv_engine(fifo)->sclass = nv17_fifo_sclass; fifo->base.pause = nv04_fifo_pause; fifo->base.start = nv04_fifo_start; fifo->ramfc_desc = nv17_ramfc; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 64be69fc9572..aca146377d36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -56,19 +56,6 @@ nv40_ramfc[] = { {} }; -static struct nvkm_oclass -nv40_fifo_cclass = { - .handle = NV_ENGCTX(FIFO, 0x40), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fifo_context_ctor, - .dtor = _nvkm_fifo_context_dtor, - .init = _nvkm_fifo_context_init, - .fini = _nvkm_fifo_context_fini, - .rd32 = _nvkm_fifo_context_rd32, - .wr32 = _nvkm_fifo_context_wr32, - }, -}; - static int nv40_fifo_init(struct nvkm_object *object) { @@ -115,7 +102,7 @@ nv40_fifo_init(struct nvkm_object *object) break; } - nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.max); + nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); @@ -126,6 +113,14 @@ nv40_fifo_init(struct nvkm_object *object) return 0; } +static const struct nvkm_fifo_func +nv40_fifo_func = { + .chan = { + &nv40_fifo_dma_oclass, + NULL + }, +}; + static int nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -139,10 +134,10 @@ nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &nv40_fifo_func; + nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv40_fifo_cclass; - nv_engine(fifo)->sclass = nv40_fifo_sclass; fifo->base.pause = nv04_fifo_pause; fifo->base.start = nv04_fifo_start; fifo->ramfc_desc = nv40_ramfc; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index bf17cb0e8385..ad653e9c461a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -35,7 +35,7 @@ nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) fifo->cur_runlist = !fifo->cur_runlist; nvkm_kmap(cur); - for (i = fifo->base.min, p = 0; i < fifo->base.max; i++) { + for (i = 0, p = 0; i < fifo->base.nr; i++) { if (nvkm_rd32(device, 0x002600 + (i * 4)) & 0x80000000) nvkm_wo32(cur, p++ * 4, i); } @@ -94,6 +94,15 @@ nv50_fifo_dtor(struct nvkm_object *object) nvkm_fifo_destroy(&fifo->base); } +static const struct nvkm_fifo_func +nv50_fifo_func = { + .chan = { + &nv50_fifo_dma_oclass, + &nv50_fifo_gpfifo_oclass, + NULL + }, +}; + static int nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -108,6 +117,8 @@ nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + fifo->base.func = &nv50_fifo_func; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, false, &fifo->runlist[0]); if (ret) @@ -120,8 +131,6 @@ nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(fifo)->unit = 0x00000100; nv_subdev(fifo)->intr = nv04_fifo_intr; - nv_engine(fifo)->cclass = &nv50_fifo_cclass; - nv_engine(fifo)->sclass = nv50_fifo_sclass; fifo->base.pause = nv04_fifo_pause; fifo->base.start = nv04_fifo_start; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index 306593fc56bb..a7d5dba12fb8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -1,5 +1,6 @@ #ifndef __NV50_FIFO_H__ #define __NV50_FIFO_H__ +#define nv50_fifo(p) container_of((p), struct nv50_fifo, base) #include "priv.h" struct nv50_fifo { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index b202f7f9413d..a30d160f30db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -1,7 +1,6 @@ #ifndef __NVKM_FIFO_PRIV_H__ #define __NVKM_FIFO_PRIV_H__ #include -#include void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index c6ff24b5a11d..ebc9dee03beb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1168,10 +1168,14 @@ gf100_gr_intr(struct nvkm_subdev *subdev) u32 data = nvkm_rd32(device, 0x400708); u32 code = nvkm_rd32(device, 0x400110); u32 class; - int chid; + const char *name = "unknown"; + int chid = -1; chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); - chid = chan ? chan->chid : -1; + if (chan) { + name = chan->object.client->name; + chid = chan->chid; + } if (nv_device(gr)->card_type < NV_E0 || subc < 4) class = nvkm_rd32(device, 0x404200 + (subc * 4)); @@ -1191,8 +1195,8 @@ gf100_gr_intr(struct nvkm_subdev *subdev) if (!gf100_gr_mthd_sw(device, class, mthd, data)) { nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] " "subc %d class %04x mthd %04x data %08x\n", - chid, inst << 12, nvkm_client_name(chan), - subc, class, mthd, data); + chid, inst << 12, name, subc, + class, mthd, data); } nvkm_wr32(device, 0x400100, 0x00000010); stat &= ~0x00000010; @@ -1201,8 +1205,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) if (stat & 0x00000020) { nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] " "subc %d class %04x mthd %04x data %08x\n", - chid, inst << 12, nvkm_client_name(chan), subc, - class, mthd, data); + chid, inst << 12, name, subc, class, mthd, data); nvkm_wr32(device, 0x400100, 0x00000020); stat &= ~0x00000020; } @@ -1213,14 +1216,14 @@ gf100_gr_intr(struct nvkm_subdev *subdev) nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] " "subc %d class %04x mthd %04x data %08x\n", code, en ? en->name : "", chid, inst << 12, - nvkm_client_name(chan), subc, class, mthd, data); + name, subc, class, mthd, data); nvkm_wr32(device, 0x400100, 0x00100000); stat &= ~0x00100000; } if (stat & 0x00200000) { nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n", - chid, inst << 12, nvkm_client_name(chan)); + chid, inst << 12, name); gf100_gr_trap_intr(gr); nvkm_wr32(device, 0x400100, 0x00200000); stat &= ~0x00200000; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 262638b4e0c5..29feab391fe4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -230,7 +230,8 @@ nv20_gr_intr(struct nvkm_subdev *subdev) "nstatus %08x [%s] ch %d [%s] subc %d " "class %04x mthd %04x data %08x\n", show, msg, nsource, src, nstatus, sta, chid, - nvkm_client_name(chan), subc, class, mthd, data); + chan ? chan->object.client->name : "unknown", + subc, class, mthd, data); } nvkm_fifo_chan_put(device->fifo, flags, &chan); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 4db2a17f5308..e716ae12b55c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -353,7 +353,8 @@ nv40_gr_intr(struct nvkm_subdev *subdev) "class %04x mthd %04x data %08x\n", show, msg, nsource, src, nstatus, sta, chan ? chan->fifo->chid : -1, inst << 4, - nvkm_client_name(chan), subc, class, mthd, data); + chan ? chan->fifo->object.client->name : "unknown", + subc, class, mthd, data); } spin_unlock_irqrestore(&gr->base.engine.lock, flags); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index daac54075705..5f22dd3c788c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -608,7 +608,7 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, static int nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, - int chid, u64 inst, struct nvkm_fifo_chan *chan) + int chid, u64 inst, const char *name) { struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; @@ -648,8 +648,7 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, "ch %d [%010llx %s] subc %d " "class %04x mthd %04x data %08x%08x " "400808 %08x 400848 %08x\n", - chid, inst, nvkm_client_name(chan), - subc, class, mthd, + chid, inst, name, subc, class, mthd, datah, datal, addr, r848); } else if (display) { @@ -674,9 +673,8 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, nvkm_error(subdev, "ch %d [%010llx %s] subc %d " "class %04x mthd %04x data %08x " - "40084c %08x\n", chid, inst, - nvkm_client_name(chan), subc, - class, mthd, data, addr); + "40084c %08x\n", chid, inst, name, + subc, class, mthd, data, addr); } else if (display) { nvkm_error(subdev, "no stuck command?\n"); @@ -849,11 +847,15 @@ nv50_gr_intr(struct nvkm_subdev *subdev) u32 show = stat, show_bitfield = stat; const struct nvkm_enum *en; unsigned long flags; + const char *name = "unknown"; char msg[128]; - int chid; + int chid = -1; chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags); - chid = chan ? chan->chid : -1; + if (chan) { + name = chan->object.client->name; + chid = chan->chid; + } if (show & 0x00100000) { u32 ecode = nvkm_rd32(device, 0x400110); @@ -864,7 +866,7 @@ nv50_gr_intr(struct nvkm_subdev *subdev) } if (stat & 0x00200000) { - if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, chan)) + if (!nv50_gr_trap_handler(gr, show, chid, (u64)inst << 12, name)) show &= ~0x00200000; show_bitfield &= ~0x00200000; } @@ -877,8 +879,8 @@ nv50_gr_intr(struct nvkm_subdev *subdev) nvkm_snprintbf(msg, sizeof(msg), nv50_gr_intr_name, show); nvkm_error(subdev, "%08x [%s] ch %d [%010llx %s] subc %d " "class %04x mthd %04x data %08x\n", - stat, msg, chid, (u64)inst << 12, - nvkm_client_name(chan), subc, class, mthd, data); + stat, msg, chid, (u64)inst << 12, name, + subc, class, mthd, data); } if (nvkm_rd32(device, 0x400824) & (1 << 31)) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 05597f2070ed..211b44c00c85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -231,8 +231,8 @@ nv31_mpeg_intr(struct nvkm_subdev *subdev) if (show) { nvkm_error(subdev, "ch %d [%s] %08x %08x %08x %08x\n", mpeg->chan ? mpeg->chan->fifo->chid : -1, - nvkm_client_name(mpeg->chan), - stat, type, mthd, data); + mpeg->chan ? mpeg->chan->fifo->object.client->name : + "unknown", stat, type, mthd, data); } spin_unlock_irqrestore(&mpeg->base.engine.lock, flags); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index 1223baddfb9a..ff9ddc67a292 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -145,13 +145,11 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev) u32 mthd = nvkm_rd32(device, 0x00b234); u32 data = nvkm_rd32(device, 0x00b238); u32 show = stat; - int chid = -1; spin_lock_irqsave(&mpeg->base.engine.lock, flags); list_for_each_entry(temp, &mpeg->chan, head) { if (temp->inst >> 4 == inst) { chan = temp; - chid = chan->fifo->chid; list_del(&chan->head); list_add(&chan->head, &mpeg->chan); break; @@ -176,7 +174,8 @@ nv44_mpeg_intr(struct nvkm_subdev *subdev) if (show) { nvkm_error(subdev, "ch %d [%08x %s] %08x %08x %08x %08x\n", - chid, inst << 4, nvkm_client_name(chan), + chan ? chan->fifo->chid : -1, inst << 4, + chan ? chan->fifo->object.client->name : "unknown", stat, type, mthd, data); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index e6544097726c..c15934d7ff63 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -84,7 +84,8 @@ g98_sec_intr(struct nvkm_falcon *sec, struct nvkm_fifo_chan *chan) nvkm_error(subdev, "DISPATCH_ERROR %04x [%s] ch %d [%010llx %s] " "subc %d mthd %04x data %08x\n", ssta, en ? en->name : "UNKNOWN", chan ? chan->chid : -1, - chan ? chan->inst : 0, nvkm_client_name(chan), + chan ? chan->inst->addr : 0, + chan ? chan->object.client->name : "unknown", subc, mthd, data); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 4e8b632ef5b1..35ec1cffb53a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -24,8 +24,8 @@ #include "nv50.h" #include -#include #include +#include #include #include @@ -136,7 +136,7 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return ret; } - chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; + chan->vblank.channel = nvkm_fifo_chan(parent)->inst->addr >> 12; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index 4a88bbd814b7..383030434079 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -338,7 +338,7 @@ void gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) { struct nvkm_device *device = clk->subdev.device; - struct nvkm_fifo *fifo = nvkm_fifo(clk); + struct nvkm_fifo *fifo = device->fifo; if (fifo && flags) fifo->start(fifo, flags); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index ea83f7d9ddc8..711ea96bcd36 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -189,12 +189,14 @@ nv50_fb_intr(struct nvkm_subdev *subdev) else sc = NULL; chan = nvkm_fifo_chan_inst(fifo, inst, &flags); - nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel " - "%08x [%s] engine %02x [%s] client %02x [%s] " + nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel %d [%08x %s] " + "engine %02x [%s] client %02x [%s] " "subclient %02x [%s] reason %08x [%s]\n", (trap[5] & 0x00000100) ? "read" : "write", - trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, inst, - nvkm_client_name(chan), st0, en ? en->name : "", + trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, + chan ? chan->chid : -1, inst, + chan ? chan->object.client->name : "unknown", + st0, en ? en->name : "", st2, cl ? cl->name : "", st3, sc ? sc->name : "", st1, re ? re->name : ""); nvkm_fifo_chan_put(fifo, flags, &chan); -- cgit v1.2.3 From 27f3d6cf80324940edd29be7758f81145e73d1ff Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:19 +1000 Subject: drm/nouveau/gr: convert user classes to new-style nvkm_object Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/core/client.h | 1 - drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 37 +-- drivers/gpu/drm/nouveau/nvkm/core/client.c | 10 - drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c | 84 ++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 63 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 39 ++- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c | 29 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c | 53 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 57 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 71 ++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c | 39 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h | 2 - drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 204 +++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 27 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c | 17 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c | 30 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c | 32 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c | 19 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c | 19 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 28 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 28 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 17 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c | 28 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 28 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 28 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c | 17 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 265 ++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 319 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 238 +++++++-------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 184 ++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 144 ++++++---- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 182 ++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 182 ++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 182 ++++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 259 ++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 19 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 249 ++++++++-------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h | 24 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h | 15 + 55 files changed, 1760 insertions(+), 1738 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index d52ef8419fd2..14da7ad79c17 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -65,5 +65,5 @@ u64 nvif_device_time(struct nvif_device *); #include #define nvxx_fifo(a) nvxx_device(a)->fifo -#define nvxx_gr(a) nvkm_gr(nvxx_device(a)) +#define nvxx_gr(a) nvxx_device(a)->gr #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h index 7ec1762a0ec1..5485bbac5677 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/client.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/client.h @@ -30,7 +30,6 @@ int nvkm_client_new(const char *name, u64 device, const char *cfg, void nvkm_client_del(struct nvkm_client **); int nvkm_client_init(struct nvkm_client *); int nvkm_client_fini(struct nvkm_client *, bool suspend); -const char *nvkm_client_name(void *obj); static inline struct nvkm_client * nvkm_client(struct nvkm_object *object) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h index 0fd02c27b869..f09f1521e6ad 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -1,44 +1,22 @@ #ifndef __NVKM_GR_H__ #define __NVKM_GR_H__ -#include - -struct nvkm_gr_chan { - struct nvkm_engctx base; -}; - -#define nvkm_gr_context_create(p,e,c,g,s,a,f,d) \ - nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) -#define nvkm_gr_context_destroy(d) \ - nvkm_engctx_destroy(&(d)->base) -#define nvkm_gr_context_init(d) \ - nvkm_engctx_init(&(d)->base) -#define nvkm_gr_context_fini(d,s) \ - nvkm_engctx_fini(&(d)->base, (s)) - -#define _nvkm_gr_context_dtor _nvkm_engctx_dtor -#define _nvkm_gr_context_init _nvkm_engctx_init -#define _nvkm_gr_context_fini _nvkm_engctx_fini -#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32 -#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32 - #include struct nvkm_gr { struct nvkm_engine engine; + const struct nvkm_gr_func *func; /* Returns chipset-specific counts of units packed into an u64. */ u64 (*units)(struct nvkm_gr *); }; -static inline struct nvkm_gr * -nvkm_gr(void *obj) -{ - return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR); -} - #define nvkm_gr_create(p,e,c,y,d) \ - nvkm_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d)) + nvkm_gr_create_((p), (e), (c), (y), sizeof(**d), (void **)(d)) +int +nvkm_gr_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, bool enable, + int length, void **pobject); #define nvkm_gr_destroy(d) \ nvkm_engine_destroy(&(d)->engine) #define nvkm_gr_init(d) \ @@ -79,8 +57,7 @@ extern struct nvkm_oclass *gm20b_gr_oclass; #include extern const struct nvkm_bitfield nv04_gr_nsource[]; -extern struct nvkm_ofuncs nv04_gr_ofuncs; -bool nv04_gr_idle(void *obj); +bool nv04_gr_idle(struct nvkm_gr *); extern const struct nvkm_bitfield nv10_gr_intr_name[]; extern const struct nvkm_bitfield nv10_gr_nstatus[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/client.c b/drivers/gpu/drm/nouveau/nvkm/core/client.c index 910f736cd1b6..ab98f8c45950 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/client.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/client.c @@ -321,13 +321,3 @@ nvkm_client_new(const char *name, u64 device, const char *cfg, nvkm_client_del(pclient); return ret; } - -const char * -nvkm_client_name(void *obj) -{ - const char *client_name = "unknown"; - struct nvkm_client *client = nvkm_client(obj); - if (client) - client_name = client->name; - return client_name; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild index cbdab5a686af..79eceaac3c1d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -1,3 +1,4 @@ +nvkm-y += nvkm/engine/gr/base.o nvkm-y += nvkm/engine/gr/nv04.o nvkm-y += nvkm/engine/gr/nv10.o nvkm-y += nvkm/engine/gr/nv20.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c new file mode 100644 index 000000000000..c6fb25847b89 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -0,0 +1,84 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" + +#include + +static int +nvkm_gr_oclass_get(struct nvkm_oclass *oclass, int index) +{ + struct nvkm_gr *gr = nvkm_gr(oclass->engine); + int c = 0; + + if (gr->func->object_get) { + int ret = gr->func->object_get(gr, index, &oclass->base); + if (oclass->base.oclass) + return index; + return ret; + } + + while (gr->func->sclass[c].oclass) { + if (c++ == index) { + oclass->base = gr->func->sclass[index]; + return index; + } + } + + return c; +} + +static int +nvkm_gr_cclass_new(struct nvkm_fifo_chan *chan, + const struct nvkm_oclass *oclass, + struct nvkm_object **pobject) +{ + struct nvkm_gr *gr = nvkm_gr(oclass->engine); + if (gr->func->chan_new) + return gr->func->chan_new(gr, chan, oclass, pobject); + return 0; +} + +struct nvkm_engine_func +nvkm_gr = { + .fifo.cclass = nvkm_gr_cclass_new, + .fifo.sclass = nvkm_gr_oclass_get, +}; + +int +nvkm_gr_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, bool enable, + int length, void **pobject) +{ + struct nvkm_gr *gr; + int ret; + + ret = nvkm_engine_create_(parent, engine, oclass, enable, + "gr", "gr", length, pobject); + gr = *pobject; + if (ret) + return ret; + + gr->engine.func = &nvkm_gr; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index d04c015eea81..96525b49e686 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1027,23 +1027,23 @@ gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data, void gf100_grctx_generate_bundle(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); + const struct gf100_grctx_func *grctx = info->gr->func->grctx; const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; - const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); + const int b = mmio_vram(info, grctx->bundle_size, (1 << s), access); mmio_refn(info, 0x408004, 0x00000000, s, b); - mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); + mmio_wr32(info, 0x408008, 0x80000000 | (grctx->bundle_size >> s)); mmio_refn(info, 0x418808, 0x00000000, s, b); - mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s)); + mmio_wr32(info, 0x41880c, 0x80000000 | (grctx->bundle_size >> s)); } void gf100_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); + const struct gf100_grctx_func *grctx = info->gr->func->grctx; const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; - const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); + const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), access); mmio_refn(info, 0x40800c, 0x00000000, s, b); mmio_wr32(info, 0x408010, 0x80000000); mmio_refn(info, 0x419004, 0x00000000, s, b); @@ -1054,9 +1054,9 @@ void gf100_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr); - const u32 attrib = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const struct gf100_grctx_func *grctx = gr->func->grctx; + const u32 attrib = grctx->attrib_nr; + const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); @@ -1072,7 +1072,7 @@ gf100_grctx_generate_attrib(struct gf100_grctx *info) const u32 o = TPC_UNIT(gpc, tpc, 0x0520); mmio_skip(info, o, (attrib << 16) | ++bo); mmio_wr32(info, o, (attrib << 16) | --bo); - bo += impl->attrib_nr_max; + bo += grctx->attrib_nr_max; } } } @@ -1237,22 +1237,22 @@ void gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - gf100_gr_mmio(gr, oclass->hub); - gf100_gr_mmio(gr, oclass->gpc); - gf100_gr_mmio(gr, oclass->zcull); - gf100_gr_mmio(gr, oclass->tpc); - gf100_gr_mmio(gr, oclass->ppc); + gf100_gr_mmio(gr, grctx->hub); + gf100_gr_mmio(gr, grctx->gpc); + gf100_gr_mmio(gr, grctx->zcull); + gf100_gr_mmio(gr, grctx->tpc); + gf100_gr_mmio(gr, grctx->ppc); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(gr); + grctx->bundle(info); + grctx->pagepool(info); + grctx->attrib(info); + grctx->unkn(gr); gf100_grctx_generate_tpcid(gr); gf100_grctx_generate_r406028(gr); @@ -1260,16 +1260,16 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_grctx_generate_r418bb8(gr); gf100_grctx_generate_r406800(gr); - gf100_gr_icmd(gr, oclass->icmd); + gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); - gf100_gr_mthd(gr, oclass->mthd); + gf100_gr_mthd(gr, grctx->mthd); nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); } int gf100_grctx_generate(struct gf100_gr *gr) { - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; struct nvkm_memory *chan; @@ -1352,7 +1352,7 @@ gf100_grctx_generate(struct gf100_gr *gr) ); } - oclass->main(gr, &info); + grctx->main(gr, &info); /* trigger a context unload by unsetting the "next channel valid" bit * and faking a context switch interrupt @@ -1383,17 +1383,8 @@ done: return ret; } -struct nvkm_oclass * -gf100_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gf100_grctx = { .main = gf100_grctx_generate_main, .unkn = gf100_grctx_generate_unkn, .hub = gf100_grctx_pack_hub, @@ -1409,4 +1400,4 @@ gf100_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib = gf100_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index a555835b5789..3c64040ec5a2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -19,8 +19,7 @@ void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int) #define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) #define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1) -struct gf100_grctx_oclass { - struct nvkm_oclass base; +struct gf100_grctx_func { /* main context generation function */ void (*main)(struct gf100_gr *, struct gf100_grctx *); /* context-specific modify-on-first-load list generation function */ @@ -50,13 +49,7 @@ struct gf100_grctx_oclass { u32 alpha_nr; }; -static inline const struct gf100_grctx_oclass * -gf100_grctx_impl(struct gf100_gr *gr) -{ - return (void *)nv_engine(gr)->cclass; -} - -extern struct nvkm_oclass *gf100_grctx_oclass; +extern const struct gf100_grctx_func gf100_grctx; int gf100_grctx_generate(struct gf100_gr *); void gf100_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); void gf100_grctx_generate_bundle(struct gf100_grctx *); @@ -69,20 +62,20 @@ void gf100_grctx_generate_r4060a8(struct gf100_gr *); void gf100_grctx_generate_r418bb8(struct gf100_gr *); void gf100_grctx_generate_r406800(struct gf100_gr *); -extern struct nvkm_oclass *gf108_grctx_oclass; +extern const struct gf100_grctx_func gf108_grctx; void gf108_grctx_generate_attrib(struct gf100_grctx *); void gf108_grctx_generate_unkn(struct gf100_gr *); -extern struct nvkm_oclass *gf104_grctx_oclass; -extern struct nvkm_oclass *gf110_grctx_oclass; +extern const struct gf100_grctx_func gf104_grctx; +extern const struct gf100_grctx_func gf110_grctx; -extern struct nvkm_oclass *gf117_grctx_oclass; +extern const struct gf100_grctx_func gf117_grctx; void gf117_grctx_generate_attrib(struct gf100_grctx *); -extern struct nvkm_oclass *gf119_grctx_oclass; +extern const struct gf100_grctx_func gf119_grctx; -extern struct nvkm_oclass *gk104_grctx_oclass; -extern struct nvkm_oclass *gk20a_grctx_oclass; +extern const struct gf100_grctx_func gk104_grctx; +extern const struct gf100_grctx_func gk20a_grctx; void gk104_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); void gk104_grctx_generate_bundle(struct gf100_grctx *); void gk104_grctx_generate_pagepool(struct gf100_grctx *); @@ -95,22 +88,22 @@ void gm107_grctx_generate_bundle(struct gf100_grctx *); void gm107_grctx_generate_pagepool(struct gf100_grctx *); void gm107_grctx_generate_attrib(struct gf100_grctx *); -extern struct nvkm_oclass *gk110_grctx_oclass; -extern struct nvkm_oclass *gk110b_grctx_oclass; -extern struct nvkm_oclass *gk208_grctx_oclass; +extern const struct gf100_grctx_func gk110_grctx; +extern const struct gf100_grctx_func gk110b_grctx; +extern const struct gf100_grctx_func gk208_grctx; -extern struct nvkm_oclass *gm107_grctx_oclass; +extern const struct gf100_grctx_func gm107_grctx; void gm107_grctx_generate_bundle(struct gf100_grctx *); void gm107_grctx_generate_pagepool(struct gf100_grctx *); void gm107_grctx_generate_attrib(struct gf100_grctx *); -extern struct nvkm_oclass *gm204_grctx_oclass; +extern const struct gf100_grctx_func gm204_grctx; void gm204_grctx_generate_main(struct gf100_gr *, struct gf100_grctx *); void gm204_grctx_generate_tpcid(struct gf100_gr *); void gm204_grctx_generate_405b60(struct gf100_gr *); -extern struct nvkm_oclass *gm206_grctx_oclass; -extern struct nvkm_oclass *gm20b_grctx_oclass; +extern const struct gf100_grctx_func gm206_grctx; +extern const struct gf100_grctx_func gm20b_grctx; /* context init value lists */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c index c5a8d55e2cac..54fd74e9cca0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c @@ -79,17 +79,8 @@ gf104_grctx_pack_tpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nvkm_oclass * -gf104_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc3), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gf104_grctx = { .main = gf100_grctx_generate_main, .unkn = gf100_grctx_generate_unkn, .hub = gf100_grctx_pack_hub, @@ -105,4 +96,4 @@ gf104_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib = gf100_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c index caccfed4ac7c..505cdcbfc085 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c @@ -731,17 +731,17 @@ void gf108_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr); - const u32 alpha = impl->alpha_nr; - const u32 beta = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const struct gf100_grctx_func *grctx = gr->func->grctx; + const u32 alpha = grctx->alpha_nr; + const u32 beta = grctx->attrib_nr; + const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); const int timeslice_mode = 1; const int max_batches = 0xffff; u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * gr->tpc_total; + u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; int gpc, tpc; mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -757,9 +757,9 @@ gf108_grctx_generate_attrib(struct gf100_grctx *info) const u32 o = TPC_UNIT(gpc, tpc, 0x500); mmio_skip(info, o + 0x20, (t << 28) | (b << 16) | ++bo); mmio_wr32(info, o + 0x20, (t << 28) | (b << 16) | --bo); - bo += impl->attrib_nr_max; + bo += grctx->attrib_nr_max; mmio_wr32(info, o + 0x44, (a << 16) | ao); - ao += impl->alpha_nr_max; + ao += grctx->alpha_nr_max; } } } @@ -776,17 +776,8 @@ gf108_grctx_generate_unkn(struct gf100_gr *gr) nvkm_mask(device, 0x419c00, 0x00000008, 0x00000008); } -struct nvkm_oclass * -gf108_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc1), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gf108_grctx = { .main = gf100_grctx_generate_main, .unkn = gf108_grctx_generate_unkn, .hub = gf108_grctx_pack_hub, @@ -804,4 +795,4 @@ gf108_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x324, .alpha_nr = 0x218, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c index b3acd931b978..7df398b53f8f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c @@ -330,17 +330,8 @@ gf110_grctx_pack_gpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nvkm_oclass * -gf110_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xc8), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gf110_grctx = { .main = gf100_grctx_generate_main, .unkn = gf100_grctx_generate_unkn, .hub = gf100_grctx_pack_hub, @@ -356,4 +347,4 @@ gf110_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib = gf100_grctx_generate_attrib, .attrib_nr_max = 0x324, .attrib_nr = 0x218, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c index 78f6be2e92db..6a3833b7cc4f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c @@ -183,17 +183,17 @@ void gf117_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(gr); - const u32 alpha = impl->alpha_nr; - const u32 beta = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const struct gf100_grctx_func *grctx = gr->func->grctx; + const u32 alpha = grctx->alpha_nr; + const u32 beta = grctx->attrib_nr; + const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); const int timeslice_mode = 1; const int max_batches = 0xffff; u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * gr->tpc_total; + u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; int gpc, ppc; mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -209,9 +209,9 @@ gf117_grctx_generate_attrib(struct gf100_grctx *info) const u32 o = PPC_UNIT(gpc, ppc, 0); mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); - bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; + bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, (a << 16) | ao); - ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; + ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; } } } @@ -220,23 +220,23 @@ void gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; int i; nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - gf100_gr_mmio(gr, oclass->hub); - gf100_gr_mmio(gr, oclass->gpc); - gf100_gr_mmio(gr, oclass->zcull); - gf100_gr_mmio(gr, oclass->tpc); - gf100_gr_mmio(gr, oclass->ppc); + gf100_gr_mmio(gr, grctx->hub); + gf100_gr_mmio(gr, grctx->gpc); + gf100_gr_mmio(gr, grctx->zcull); + gf100_gr_mmio(gr, grctx->tpc); + gf100_gr_mmio(gr, grctx->ppc); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(gr); + grctx->bundle(info); + grctx->pagepool(info); + grctx->attrib(info); + grctx->unkn(gr); gf100_grctx_generate_tpcid(gr); gf100_grctx_generate_r406028(gr); @@ -247,23 +247,14 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) for (i = 0; i < 8; i++) nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); - gf100_gr_icmd(gr, oclass->icmd); + gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); - gf100_gr_mthd(gr, oclass->mthd); + gf100_gr_mthd(gr, grctx->mthd); nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); } -struct nvkm_oclass * -gf117_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xd7), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gf117_grctx = { .main = gf117_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gf117_grctx_pack_hub, @@ -282,4 +273,4 @@ gf117_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, .alpha_nr = 0x324, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c index 8d8761443809..605185b078be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c @@ -498,17 +498,8 @@ gf119_grctx_pack_tpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nvkm_oclass * -gf119_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xd9), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gf119_grctx = { .main = gf100_grctx_generate_main, .unkn = gf108_grctx_generate_unkn, .hub = gf119_grctx_pack_hub, @@ -526,4 +517,4 @@ gf119_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x324, .alpha_nr = 0x218, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index 0365acaf8c70..77110ea019ea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -843,27 +843,27 @@ gk104_grctx_pack_ppc[] = { void gk104_grctx_generate_bundle(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); - const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, - impl->bundle_size / 0x20); - const u32 token_limit = impl->bundle_token_limit; + const struct gf100_grctx_func *grctx = info->gr->func->grctx; + const u32 state_limit = min(grctx->bundle_min_gpm_fifo_depth, + grctx->bundle_size / 0x20); + const u32 token_limit = grctx->bundle_token_limit; const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; - const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); + const int b = mmio_vram(info, grctx->bundle_size, (1 << s), access); mmio_refn(info, 0x408004, 0x00000000, s, b); - mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); + mmio_wr32(info, 0x408008, 0x80000000 | (grctx->bundle_size >> s)); mmio_refn(info, 0x418808, 0x00000000, s, b); - mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s)); + mmio_wr32(info, 0x41880c, 0x80000000 | (grctx->bundle_size >> s)); mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); } void gk104_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); + const struct gf100_grctx_func *grctx = info->gr->func->grctx; const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; - const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); + const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), access); mmio_refn(info, 0x40800c, 0x00000000, s, b); mmio_wr32(info, 0x408010, 0x80000000); mmio_refn(info, 0x419004, 0x00000000, s, b); @@ -955,23 +955,23 @@ void gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; int i; nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); - gf100_gr_mmio(gr, oclass->hub); - gf100_gr_mmio(gr, oclass->gpc); - gf100_gr_mmio(gr, oclass->zcull); - gf100_gr_mmio(gr, oclass->tpc); - gf100_gr_mmio(gr, oclass->ppc); + gf100_gr_mmio(gr, grctx->hub); + gf100_gr_mmio(gr, grctx->gpc); + gf100_gr_mmio(gr, grctx->zcull); + gf100_gr_mmio(gr, grctx->tpc); + gf100_gr_mmio(gr, grctx->ppc); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(gr); + grctx->bundle(info); + grctx->pagepool(info); + grctx->attrib(info); + grctx->unkn(gr); gf100_grctx_generate_tpcid(gr); gf100_grctx_generate_r406028(gr); @@ -985,26 +985,17 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_rop_active_fbps(gr); nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); - gf100_gr_icmd(gr, oclass->icmd); + gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); - gf100_gr_mthd(gr, oclass->mthd); + gf100_gr_mthd(gr, grctx->mthd); nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); } -struct nvkm_oclass * -gk104_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xe4), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gk104_grctx = { .main = gk104_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gk104_grctx_pack_hub, @@ -1025,4 +1016,4 @@ gk104_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, .alpha_nr = 0x648, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c index b3f58be04e9c..7b95ec2fe453 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c @@ -808,17 +808,8 @@ gk110_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nvkm_oclass * -gk110_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xf0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gk110_grctx = { .main = gk104_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gk110_grctx_pack_hub, @@ -839,4 +830,4 @@ gk110_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, .alpha_nr = 0x648, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c index b11c26794fde..048b1152da44 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c @@ -69,17 +69,8 @@ gk110b_grctx_pack_tpc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nvkm_oclass * -gk110b_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xf1), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gk110b_grctx = { .main = gk104_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gk110_grctx_pack_hub, @@ -100,4 +91,4 @@ gk110b_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, .alpha_nr = 0x648, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c index 6e8ce9fc311a..67b7a1b43617 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c @@ -530,17 +530,8 @@ gk208_grctx_pack_ppc[] = { * PGRAPH context implementation ******************************************************************************/ -struct nvkm_oclass * -gk208_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x08), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gk208_grctx = { .main = gk104_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gk208_grctx_pack_hub, @@ -561,4 +552,4 @@ gk208_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x218, .alpha_nr_max = 0x7ff, .alpha_nr = 0x648, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 252bcc331a5a..43d9ce227668 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -29,7 +29,7 @@ static void gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; int idle_timeout_save; int i; @@ -40,9 +40,9 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) idle_timeout_save = nvkm_rd32(device, 0x404154); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->attrib(info); + grctx->attrib(info); - oclass->unkn(gr); + grctx->unkn(gr); gf100_grctx_generate_tpcid(gr); gf100_grctx_generate_r406028(gr); @@ -67,21 +67,12 @@ gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_wait_idle(gr); gf100_gr_icmd(gr, gr->fuc_bundle); - oclass->pagepool(info); - oclass->bundle(info); + grctx->pagepool(info); + grctx->bundle(info); } -struct nvkm_oclass * -gk20a_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gk20a_grctx = { .main = gk20a_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .bundle = gk104_grctx_generate_bundle, @@ -95,4 +86,4 @@ gk20a_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x240, .alpha_nr_max = 0x648 + (0x648 / 2), .alpha_nr = 0x648, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 9c361ee21fbf..95f59e3169f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -863,27 +863,27 @@ gm107_grctx_pack_ppc[] = { void gm107_grctx_generate_bundle(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); - const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, - impl->bundle_size / 0x20); - const u32 token_limit = impl->bundle_token_limit; + const struct gf100_grctx_func *grctx = info->gr->func->grctx; + const u32 state_limit = min(grctx->bundle_min_gpm_fifo_depth, + grctx->bundle_size / 0x20); + const u32 token_limit = grctx->bundle_token_limit; const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; - const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); + const int b = mmio_vram(info, grctx->bundle_size, (1 << s), access); mmio_refn(info, 0x408004, 0x00000000, s, b); - mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s)); + mmio_wr32(info, 0x408008, 0x80000000 | (grctx->bundle_size >> s)); mmio_refn(info, 0x418e24, 0x00000000, s, b); - mmio_wr32(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s)); + mmio_wr32(info, 0x418e28, 0x80000000 | (grctx->bundle_size >> s)); mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); } void gm107_grctx_generate_pagepool(struct gf100_grctx *info) { - const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->gr); + const struct gf100_grctx_func *grctx = info->gr->func->grctx; const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; const int s = 8; - const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); + const int b = mmio_vram(info, grctx->pagepool_size, (1 << s), access); mmio_refn(info, 0x40800c, 0x00000000, s, b); mmio_wr32(info, 0x408010, 0x80000000); mmio_refn(info, 0x419004, 0x00000000, s, b); @@ -896,16 +896,16 @@ void gm107_grctx_generate_attrib(struct gf100_grctx *info) { struct gf100_gr *gr = info->gr; - const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(gr); - const u32 alpha = impl->alpha_nr; - const u32 attrib = impl->attrib_nr; - const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); + const struct gf100_grctx_func *grctx = gr->func->grctx; + const u32 alpha = grctx->alpha_nr; + const u32 attrib = grctx->attrib_nr; + const u32 size = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 access = NV_MEM_ACCESS_RW; const int s = 12; const int b = mmio_vram(info, size * gr->tpc_total, (1 << s), access); const int max_batches = 0xffff; u32 bo = 0; - u32 ao = bo + impl->attrib_nr_max * gr->tpc_total; + u32 ao = bo + grctx->attrib_nr_max * gr->tpc_total; int gpc, ppc, n = 0; mmio_refn(info, 0x418810, 0x80000000, s, b); @@ -922,10 +922,10 @@ gm107_grctx_generate_attrib(struct gf100_grctx *info) const u32 o = PPC_UNIT(gpc, ppc, 0); mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, o + 0xf4, bo); - bo += impl->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; + bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xf8, ao); - ao += impl->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; + ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; mmio_wr32(info, u, ((bs / 3 /*XXX*/) << 16) | bs); } } @@ -956,21 +956,21 @@ static void gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; int i; - gf100_gr_mmio(gr, oclass->hub); - gf100_gr_mmio(gr, oclass->gpc); - gf100_gr_mmio(gr, oclass->zcull); - gf100_gr_mmio(gr, oclass->tpc); - gf100_gr_mmio(gr, oclass->ppc); + gf100_gr_mmio(gr, grctx->hub); + gf100_gr_mmio(gr, grctx->gpc); + gf100_gr_mmio(gr, grctx->zcull); + gf100_gr_mmio(gr, grctx->tpc); + gf100_gr_mmio(gr, grctx->ppc); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(gr); + grctx->bundle(info); + grctx->pagepool(info); + grctx->attrib(info); + grctx->unkn(gr); gm107_grctx_generate_tpcid(gr); gf100_grctx_generate_r406028(gr); @@ -986,9 +986,9 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gk104_grctx_generate_rop_active_fbps(gr); - gf100_gr_icmd(gr, oclass->icmd); + gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); - gf100_gr_mthd(gr, oclass->mthd); + gf100_gr_mthd(gr, grctx->mthd); nvkm_mask(device, 0x419e00, 0x00808080, 0x00808080); nvkm_mask(device, 0x419ccc, 0x80000000, 0x80000000); @@ -996,17 +996,8 @@ gm107_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) nvkm_mask(device, 0x419f88, 0x80000000, 0x80000000); } -struct nvkm_oclass * -gm107_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x08), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gm107_grctx = { .main = gm107_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gm107_grctx_pack_hub, @@ -1027,4 +1018,4 @@ gm107_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0xaa0, .alpha_nr_max = 0x1800, .alpha_nr = 0x1000, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c index f8c2432b7d7a..170cbfdbe1ae 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm204.c @@ -981,22 +981,22 @@ void gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; u32 tmp; int i; - gf100_gr_mmio(gr, oclass->hub); - gf100_gr_mmio(gr, oclass->gpc); - gf100_gr_mmio(gr, oclass->zcull); - gf100_gr_mmio(gr, oclass->tpc); - gf100_gr_mmio(gr, oclass->ppc); + gf100_gr_mmio(gr, grctx->hub); + gf100_gr_mmio(gr, grctx->gpc); + gf100_gr_mmio(gr, grctx->zcull); + gf100_gr_mmio(gr, grctx->tpc); + gf100_gr_mmio(gr, grctx->ppc); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->bundle(info); - oclass->pagepool(info); - oclass->attrib(info); - oclass->unkn(gr); + grctx->bundle(info); + grctx->pagepool(info); + grctx->attrib(info); + grctx->unkn(gr); gm204_grctx_generate_tpcid(gr); gf100_grctx_generate_r406028(gr); @@ -1016,25 +1016,16 @@ gm204_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gm204_grctx_generate_405b60(gr); - gf100_gr_icmd(gr, oclass->icmd); + gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000800); - gf100_gr_mthd(gr, oclass->mthd); + gf100_gr_mthd(gr, grctx->mthd); nvkm_mask(device, 0x418e94, 0xffffffff, 0xc4230000); nvkm_mask(device, 0x418e4c, 0xffffffff, 0x70000000); } -struct nvkm_oclass * -gm204_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x24), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gm204_grctx = { .main = gm204_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gm204_grctx_pack_hub, @@ -1055,4 +1046,4 @@ gm204_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x400, .alpha_nr_max = 0x1800, .alpha_nr = 0x1000, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c index 91ec41617943..d6be6034c2c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm206.c @@ -49,17 +49,8 @@ gm206_grctx_pack_gpc[] = { {} }; -struct nvkm_oclass * -gm206_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x26), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gm206_grctx = { .main = gm204_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .hub = gm204_grctx_pack_hub, @@ -80,4 +71,4 @@ gm206_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x400, .alpha_nr_max = 0x1800, .alpha_nr = 0x1000, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c index 5f5affc55fe0..670260402538 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.c @@ -39,7 +39,7 @@ static void gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) { struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_grctx_oclass *oclass = (void *)nv_engine(gr)->cclass; + const struct gf100_grctx_func *grctx = gr->func->grctx; int idle_timeout_save; int i, tmp; @@ -50,9 +50,9 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) idle_timeout_save = nvkm_rd32(device, 0x404154); nvkm_wr32(device, 0x404154, 0x00000000); - oclass->attrib(info); + grctx->attrib(info); - oclass->unkn(gr); + grctx->unkn(gr); gm204_grctx_generate_tpcid(gr); gm20b_grctx_generate_r406028(gr); @@ -81,21 +81,12 @@ gm20b_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_wait_idle(gr); gf100_gr_icmd(gr, gr->fuc_bundle); - oclass->pagepool(info); - oclass->bundle(info); + grctx->pagepool(info); + grctx->bundle(info); } -struct nvkm_oclass * -gm20b_grctx_oclass = &(struct gf100_grctx_oclass) { - .base.handle = NV_ENGCTX(GR, 0x2b), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_context_ctor, - .dtor = gf100_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +const struct gf100_grctx_func +gm20b_grctx = { .main = gm20b_grctx_generate_main, .unkn = gk104_grctx_generate_unkn, .bundle = gm107_grctx_generate_bundle, @@ -109,4 +100,4 @@ gm20b_grctx_oclass = &(struct gf100_grctx_oclass) { .attrib_nr = 0x400, .alpha_nr_max = 0xc00, .alpha_nr = 0x800, -}.base; +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c index 8ecdc94e3538..80a6b017af64 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c @@ -580,7 +580,6 @@ nv40_gr_construct_shader(struct nvkm_grctx *ctx) if (ctx->mode != NVKM_GRCTX_VALS) return; - nvkm_kmap(obj); offset += 0x0280/4; for (i = 0; i < 16; i++, offset += 2) nvkm_wo32(obj, offset * 4, 0x3f800000); @@ -591,7 +590,6 @@ nv40_gr_construct_shader(struct nvkm_grctx *ctx) for (i = 0; i < vs_nr_b1 * 4; i += 4) nvkm_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); } - nvkm_done(obj); } static void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h index 6170b21b50cc..50e808e9f926 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h @@ -125,8 +125,6 @@ gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) reg = (reg - 0x00400000) / 4; reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; - nvkm_kmap(ctx->data); nvkm_wo32(ctx->data, reg * 4, val); - nvkm_done(ctx->data); } #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index 5bdb112dc945..27fa96b222e3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -784,10 +784,8 @@ static void dd_emit(struct nvkm_grctx *ctx, int num, u32 val) { int i; if (val && ctx->mode == NVKM_GRCTX_VALS) { - nvkm_kmap(ctx->data); for (i = 0; i < num; i++) nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); - nvkm_done(ctx->data); } ctx->ctxvals_pos += num; } @@ -1159,10 +1157,8 @@ static void xf_emit(struct nvkm_grctx *ctx, int num, u32 val) { int i; if (val && ctx->mode == NVKM_GRCTX_VALS) { - nvkm_kmap(ctx->data); for (i = 0; i < num; i++) nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); - nvkm_done(ctx->data); } ctx->ctxvals_pos += num << 3; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index ebc9dee03beb..7917d141fcb0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -223,12 +223,8 @@ gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) return -EINVAL; } -struct nvkm_ofuncs -gf100_fermi_ofuncs = { - .ctor = _nvkm_object_ctor, - .dtor = nvkm_object_destroy, - .init = _nvkm_object_init, - .fini = _nvkm_object_fini, +const struct nvkm_object_func +gf100_fermi = { .mthd = gf100_fermi_mthd, }; @@ -259,40 +255,106 @@ gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data) return false; } -struct nvkm_oclass -gf100_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, - { FERMI_A, &gf100_fermi_ofuncs }, - { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, - {} -}; +static int +gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) +{ + struct gf100_gr *gr = gf100_gr(base); + int c = 0; + + while (gr->func->sclass[c].oclass) { + if (c++ == index) { + *sclass = gr->func->sclass[index]; + return index; + } + } + + return c; +} /******************************************************************************* * PGRAPH context ******************************************************************************/ -int -gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *args, u32 size, - struct nvkm_object **pobject) +static int +gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, + int align, struct nvkm_gpuobj **pgpuobj) { - struct nvkm_vm *vm = nvkm_client(parent)->vm; - struct gf100_gr *gr = (void *)engine; + struct gf100_gr_chan *chan = gf100_gr_chan(object); + struct gf100_gr *gr = chan->gr; + int ret, i; + + ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, + align, false, parent, pgpuobj); + if (ret) + return ret; + + nvkm_kmap(*pgpuobj); + for (i = 0; i < gr->size; i += 4) + nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); + + if (!gr->firmware) { + nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); + nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); + } else { + nvkm_wo32(*pgpuobj, 0xf4, 0); + nvkm_wo32(*pgpuobj, 0xf8, 0); + nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); + nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); + nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); + nvkm_wo32(*pgpuobj, 0x1c, 1); + nvkm_wo32(*pgpuobj, 0x20, 0); + nvkm_wo32(*pgpuobj, 0x28, 0); + nvkm_wo32(*pgpuobj, 0x2c, 0); + } + nvkm_done(*pgpuobj); + return 0; +} + +static void * +gf100_gr_chan_dtor(struct nvkm_object *object) +{ + struct gf100_gr_chan *chan = gf100_gr_chan(object); + int i; + + for (i = 0; i < ARRAY_SIZE(chan->data); i++) { + if (chan->data[i].vma.node) { + nvkm_vm_unmap(&chan->data[i].vma); + nvkm_vm_put(&chan->data[i].vma); + } + nvkm_memory_del(&chan->data[i].mem); + } + + if (chan->mmio_vma.node) { + nvkm_vm_unmap(&chan->mmio_vma); + nvkm_vm_put(&chan->mmio_vma); + } + nvkm_memory_del(&chan->mmio); + return chan; +} + +static const struct nvkm_object_func +gf100_gr_chan = { + .dtor = gf100_gr_chan_dtor, + .bind = gf100_gr_chan_bind, +}; + +static int +gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, + struct nvkm_object **pobject) +{ + struct gf100_gr *gr = gf100_gr(base); struct gf100_gr_data *data = gr->mmio_data; struct gf100_gr_mmio *mmio = gr->mmio_list; struct gf100_gr_chan *chan; struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_gpuobj *image; int ret, i; - /* allocate memory for context, and fill with default values */ - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, - gr->size, 0x100, - NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object); + chan->gr = gr; + *pobject = &chan->object; /* allocate memory for a "mmio list" buffer that's used by the HUB * fuc to modify some per-context register settings on first load @@ -303,7 +365,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_vm_get(vm, 0x1000, 12, NV_MEM_ACCESS_RW | + ret = nvkm_vm_get(fifoch->vm, 0x1000, 12, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, &chan->mmio_vma); if (ret) return ret; @@ -318,8 +380,9 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - ret = nvkm_vm_get(vm, nvkm_memory_size(chan->data[i].mem), - 12, data->access, &chan->data[i].vma); + ret = nvkm_vm_get(fifoch->vm, + nvkm_memory_size(chan->data[i].mem), 12, + data->access, &chan->data[i].vma); if (ret) return ret; @@ -343,53 +406,9 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, mmio++; } nvkm_done(chan->mmio); - - image = &chan->base.base.gpuobj; - nvkm_kmap(image); - for (i = 0; i < gr->size; i += 4) - nvkm_wo32(image, i, gr->data[i / 4]); - - if (!gr->firmware) { - nvkm_wo32(image, 0x00, chan->mmio_nr / 2); - nvkm_wo32(image, 0x04, chan->mmio_vma.offset >> 8); - } else { - nvkm_wo32(image, 0xf4, 0); - nvkm_wo32(image, 0xf8, 0); - nvkm_wo32(image, 0x10, chan->mmio_nr / 2); - nvkm_wo32(image, 0x14, lower_32_bits(chan->mmio_vma.offset)); - nvkm_wo32(image, 0x18, upper_32_bits(chan->mmio_vma.offset)); - nvkm_wo32(image, 0x1c, 1); - nvkm_wo32(image, 0x20, 0); - nvkm_wo32(image, 0x28, 0); - nvkm_wo32(image, 0x2c, 0); - } - nvkm_done(image); return 0; } -void -gf100_gr_context_dtor(struct nvkm_object *object) -{ - struct gf100_gr_chan *chan = (void *)object; - int i; - - for (i = 0; i < ARRAY_SIZE(chan->data); i++) { - if (chan->data[i].vma.node) { - nvkm_vm_unmap(&chan->data[i].vma); - nvkm_vm_put(&chan->data[i].vma); - } - nvkm_memory_del(&chan->data[i].mem); - } - - if (chan->mmio_vma.node) { - nvkm_vm_unmap(&chan->mmio_vma); - nvkm_vm_put(&chan->mmio_vma); - } - nvkm_memory_del(&chan->mmio); - - nvkm_gr_context_destroy(&chan->base); -} - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -1312,10 +1331,10 @@ gf100_gr_init_csdata(struct gf100_gr *gr, int gf100_gr_init_ctxctl(struct gf100_gr *gr) { + const struct gf100_grctx_func *grctx = gr->func->grctx; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; - struct gf100_grctx_oclass *cclass = (void *)nv_engine(gr)->cclass; int i; if (gr->firmware) { @@ -1446,10 +1465,10 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); /* load register lists */ - gf100_gr_init_csdata(gr, cclass->hub, 0x409000, 0x000, 0x000000); - gf100_gr_init_csdata(gr, cclass->gpc, 0x41a000, 0x000, 0x418000); - gf100_gr_init_csdata(gr, cclass->tpc, 0x41a000, 0x004, 0x419800); - gf100_gr_init_csdata(gr, cclass->ppc, 0x41a000, 0x008, 0x41be00); + gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); + gf100_gr_init_csdata(gr, grctx->gpc, 0x41a000, 0x000, 0x418000); + gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800); + gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00); /* start HUB ucode running, it'll init the GPCs */ nvkm_wr32(device, 0x40910c, 0x00000000); @@ -1646,6 +1665,12 @@ gf100_gr_dtor(struct nvkm_object *object) nvkm_gr_destroy(&gr->base); } +static const struct nvkm_gr_func +gf100_gr_ = { + .chan_new = gf100_gr_chan_new, + .object_get = gf100_gr_object_get, +}; + int gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *bclass, void *data, u32 size, @@ -1666,6 +1691,8 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->func = oclass->func; + gr->base.func = &gf100_gr_; nv_subdev(gr)->unit = 0x08001000; nv_subdev(gr)->intr = gf100_gr_intr; @@ -1752,8 +1779,6 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, break; } - nv_engine(gr)->cclass = *oclass->cclass; - nv_engine(gr)->sclass = oclass->sclass; return 0; } @@ -1777,6 +1802,18 @@ gf100_gr_gpccs_ucode = { .data.size = sizeof(gf100_grgpc_data), }; +static const struct gf100_gr_func +gf100_gr = { + .grctx = &gf100_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, + { -1, -1, FERMI_A, &gf100_fermi }, + { -1, -1, FERMI_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gf100_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc0), @@ -1786,8 +1823,7 @@ gf100_gr_oclass = &(struct gf100_gr_oclass) { .init = gf100_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gf100_grctx_oclass, - .sclass = gf100_gr_sclass, + .func = &gf100_gr, .mmio = gf100_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 612d5346eae9..43e9897ac883 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -23,9 +23,12 @@ */ #ifndef __NVC0_GR_H__ #define __NVC0_GR_H__ -#include +#define gf100_gr(p) container_of((p), struct gf100_gr, base) +#include "priv.h" +#include #include +#include #define GPC_MAX 32 #define TPC_MAX (GPC_MAX * 8) @@ -69,6 +72,7 @@ struct gf100_gr_zbc_depth { struct gf100_gr { struct nvkm_gr base; + const struct gf100_gr_func *func; struct gf100_gr_fuc fuc409c; struct gf100_gr_fuc fuc409d; @@ -106,23 +110,27 @@ struct gf100_gr { u8 magic_not_rop_nr; }; +struct gf100_gr_func { + const struct gf100_grctx_func *grctx; + struct nvkm_sclass sclass[]; +}; + +#define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object) + struct gf100_gr_chan { - struct nvkm_gr_chan base; + struct nvkm_object object; + struct gf100_gr *gr; struct nvkm_memory *mmio; struct nvkm_vma mmio_vma; int mmio_nr; + struct { struct nvkm_memory *mem; struct nvkm_vma vma; } data[4]; }; -int gf100_gr_context_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void gf100_gr_context_dtor(struct nvkm_object *); - void gf100_gr_ctxctl_debug(struct gf100_gr *); void gf100_gr_dtor_fw(struct gf100_gr_fuc *); @@ -149,7 +157,7 @@ int gk20a_gr_init(struct nvkm_object *); int gm204_gr_init(struct nvkm_object *); -extern struct nvkm_ofuncs gf100_fermi_ofuncs; +extern const struct nvkm_object_func gf100_fermi; extern struct nvkm_oclass gf100_gr_sclass[]; extern struct nvkm_oclass gf110_gr_sclass[]; @@ -185,8 +193,7 @@ extern struct gf100_gr_ucode gk110_gr_gpccs_ucode; struct gf100_gr_oclass { struct nvkm_oclass base; - struct nvkm_oclass **cclass; - struct nvkm_oclass *sclass; + const struct gf100_gr_func *func; const struct gf100_gr_pack *mmio; struct { struct gf100_gr_ucode *ucode; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c index 20d3b85db3b5..aa529b5c0daa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c @@ -24,6 +24,8 @@ #include "gf100.h" #include "ctxgf100.h" +#include + /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -110,6 +112,18 @@ gf104_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct gf100_gr_func +gf104_gr = { + .grctx = &gf104_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, + { -1, -1, FERMI_A, &gf100_fermi }, + { -1, -1, FERMI_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gf104_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc3), @@ -119,8 +133,7 @@ gf104_gr_oclass = &(struct gf100_gr_oclass) { .init = gf100_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gf104_grctx_oclass, - .sclass = gf100_gr_sclass, + .func = &gf104_gr, .mmio = gf104_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 1e8290ab1d37..971c897d59be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -26,20 +26,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nvkm_oclass -gf108_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, - { FERMI_A, &gf100_fermi_ofuncs }, - { FERMI_B, &gf100_fermi_ofuncs }, - { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -117,6 +103,19 @@ gf108_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct gf100_gr_func +gf108_gr = { + .grctx = &gf108_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, + { -1, -1, FERMI_A, &gf100_fermi }, + { -1, -1, FERMI_B, &gf100_fermi }, + { -1, -1, FERMI_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gf108_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc1), @@ -126,8 +125,7 @@ gf108_gr_oclass = &(struct gf100_gr_oclass) { .init = gf100_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gf108_grctx_oclass, - .sclass = gf108_gr_sclass, + .func = &gf108_gr, .mmio = gf108_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index 4fe0f969de82..f832a8bd454c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -26,21 +26,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -struct nvkm_oclass -gf110_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { FERMI_MEMORY_TO_MEMORY_FORMAT_A, &nvkm_object_ofuncs }, - { FERMI_A, &gf100_fermi_ofuncs }, - { FERMI_B, &gf100_fermi_ofuncs }, - { FERMI_C, &gf100_fermi_ofuncs }, - { FERMI_COMPUTE_A, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -99,6 +84,20 @@ gf110_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct gf100_gr_func +gf110_gr = { + .grctx = &gf110_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, + { -1, -1, FERMI_A, &gf100_fermi }, + { -1, -1, FERMI_B, &gf100_fermi }, + { -1, -1, FERMI_C, &gf100_fermi }, + { -1, -1, FERMI_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gf110_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xc8), @@ -108,8 +107,7 @@ gf110_gr_oclass = &(struct gf100_gr_oclass) { .init = gf100_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gf110_grctx_oclass, - .sclass = gf110_gr_sclass, + .func = &gf110_gr, .mmio = gf110_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index 871ac5f806f6..909b5a6fa8d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -24,6 +24,8 @@ #include "gf100.h" #include "ctxgf100.h" +#include + /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -118,6 +120,20 @@ gf117_gr_gpccs_ucode = { .data.size = sizeof(gf117_grgpc_data), }; +static const struct gf100_gr_func +gf117_gr = { + .grctx = &gf117_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, + { -1, -1, FERMI_A, &gf100_fermi }, + { -1, -1, FERMI_B, &gf100_fermi }, + { -1, -1, FERMI_C, &gf100_fermi }, + { -1, -1, FERMI_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gf117_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xd7), @@ -127,8 +143,7 @@ gf117_gr_oclass = &(struct gf100_gr_oclass) { .init = gf100_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gf117_grctx_oclass, - .sclass = gf110_gr_sclass, + .func = &gf117_gr, .mmio = gf117_gr_pack_mmio, .fecs.ucode = &gf117_gr_fecs_ucode, .gpccs.ucode = &gf117_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index e6dd651e2636..01c2dcc4e873 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -24,6 +24,8 @@ #include "gf100.h" #include "ctxgf100.h" +#include + /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -173,6 +175,20 @@ gf119_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct gf100_gr_func +gf119_gr = { + .grctx = &gf119_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A }, + { -1, -1, FERMI_A, &gf100_fermi }, + { -1, -1, FERMI_B, &gf100_fermi }, + { -1, -1, FERMI_C, &gf100_fermi }, + { -1, -1, FERMI_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gf119_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xd9), @@ -182,8 +198,7 @@ gf119_gr_oclass = &(struct gf100_gr_oclass) { .init = gf100_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gf119_grctx_oclass, - .sclass = gf110_gr_sclass, + .func = &gf119_gr, .mmio = gf119_gr_pack_mmio, .fecs.ucode = &gf100_gr_fecs_ucode, .gpccs.ucode = &gf100_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index a00731979698..956e5926afe5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -28,19 +28,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nvkm_oclass -gk104_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs }, - { KEPLER_A, &gf100_fermi_ofuncs }, - { KEPLER_COMPUTE_A, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -311,6 +298,18 @@ gk104_gr_init(struct nvkm_object *object) return gf100_gr_init_ctxctl(gr); } +static const struct gf100_gr_func +gk104_gr = { + .grctx = &gk104_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_A }, + { -1, -1, KEPLER_A, &gf100_fermi }, + { -1, -1, KEPLER_COMPUTE_A }, + {} + } +}; + int gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -351,8 +350,7 @@ gk104_gr_oclass = &(struct gf100_gr_oclass) { .init = gk104_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gk104_grctx_oclass, - .sclass = gk104_gr_sclass, + .func = &gk104_gr, .mmio = gk104_gr_pack_mmio, .fecs.ucode = &gk104_gr_fecs_ucode, .gpccs.ucode = &gk104_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index ec21f62e7248..fb513ea8bbd2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -28,19 +28,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -struct nvkm_oclass -gk110_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { KEPLER_B, &gf100_fermi_ofuncs }, - { KEPLER_COMPUTE_B, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -193,6 +180,18 @@ gk110_gr_gpccs_ucode = { .data.size = sizeof(gk110_grgpc_data), }; +static const struct gf100_gr_func +gk110_gr = { + .grctx = &gk110_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, KEPLER_B, &gf100_fermi }, + { -1, -1, KEPLER_COMPUTE_B }, + {} + } +}; + struct nvkm_oclass * gk110_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xf0), @@ -202,8 +201,7 @@ gk110_gr_oclass = &(struct gf100_gr_oclass) { .init = gk104_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gk110_grctx_oclass, - .sclass = gk110_gr_sclass, + .func = &gk110_gr, .mmio = gk110_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index 9ff9eab0ccaf..b3da907b2b70 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -24,6 +24,8 @@ #include "gf100.h" #include "ctxgf100.h" +#include + /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -98,6 +100,18 @@ gk110b_gr_pack_mmio[] = { * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct gf100_gr_func +gk110b_gr = { + .grctx = &gk110b_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, KEPLER_B, &gf100_fermi }, + { -1, -1, KEPLER_COMPUTE_B }, + {} + } +}; + struct nvkm_oclass * gk110b_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0xf1), @@ -107,8 +121,7 @@ gk110b_gr_oclass = &(struct gf100_gr_oclass) { .init = gk104_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gk110b_grctx_oclass, - .sclass = gk110_gr_sclass, + .func = &gk110b_gr, .mmio = gk110b_gr_pack_mmio, .fecs.ucode = &gk110_gr_fecs_ucode, .gpccs.ucode = &gk110_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index 85f44a3d5d11..243b0a3f67c2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -28,19 +28,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nvkm_oclass -gk208_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { KEPLER_B, &gf100_fermi_ofuncs }, - { KEPLER_COMPUTE_B, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -172,6 +159,18 @@ gk208_gr_gpccs_ucode = { .data.size = sizeof(gk208_grgpc_data), }; +static const struct gf100_gr_func +gk208_gr = { + .grctx = &gk208_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, KEPLER_B, &gf100_fermi }, + { -1, -1, KEPLER_COMPUTE_B }, + {} + } +}; + struct nvkm_oclass * gk208_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x08), @@ -181,8 +180,7 @@ gk208_gr_oclass = &(struct gf100_gr_oclass) { .init = gk104_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gk208_grctx_oclass, - .sclass = gk208_gr_sclass, + .func = &gk208_gr, .mmio = gk208_gr_pack_mmio, .fecs.ucode = &gk208_gr_fecs_ucode, .gpccs.ucode = &gk208_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index c213e9a005c6..a8100c4f5785 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -22,17 +22,9 @@ #include "gk20a.h" #include "ctxgf100.h" -#include #include -static struct nvkm_oclass -gk20a_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_A, &nvkm_object_ofuncs }, - { KEPLER_C, &gf100_fermi_ofuncs }, - { KEPLER_COMPUTE_A, &nvkm_object_ofuncs }, - {} -}; +#include static void gk20a_gr_init_dtor(struct gf100_gr_pack *pack) @@ -350,6 +342,18 @@ gk20a_gr_init(struct nvkm_object *object) return gf100_gr_init_ctxctl(gr); } +static const struct gf100_gr_func +gk20a_gr = { + .grctx = &gk20a_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_A }, + { -1, -1, KEPLER_C, &gf100_fermi }, + { -1, -1, KEPLER_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gk20a_gr_oclass = &(struct gk20a_gr_oclass) { .gf100 = { @@ -360,8 +364,7 @@ gk20a_gr_oclass = &(struct gk20a_gr_oclass) { .init = gk20a_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gk20a_grctx_oclass, - .sclass = gk20a_gr_sclass, + .func = &gk20a_gr, .ppc_nr = 1, }, .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index aad5fdb29c60..b3036cb61080 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -29,19 +29,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nvkm_oclass -gm107_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { MAXWELL_A, &gf100_fermi_ofuncs }, - { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -454,6 +441,18 @@ gm107_gr_gpccs_ucode = { .data.size = sizeof(gm107_grgpc_data), }; +static const struct gf100_gr_func +gm107_gr = { + .grctx = &gm107_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, MAXWELL_A, &gf100_fermi }, + { -1, -1, MAXWELL_COMPUTE_A }, + {} + } +}; + struct nvkm_oclass * gm107_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x07), @@ -463,8 +462,7 @@ gm107_gr_oclass = &(struct gf100_gr_oclass) { .init = gm107_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gm107_grctx_oclass, - .sclass = gm107_gr_sclass, + .func = &gm107_gr, .mmio = gm107_gr_pack_mmio, .fecs.ucode = &gm107_gr_fecs_ucode, .gpccs.ucode = &gm107_gr_gpccs_ucode, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c index 39f42a1c2b78..ff41232a8a53 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c @@ -26,19 +26,6 @@ #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -struct nvkm_oclass -gm204_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { MAXWELL_B, &gf100_fermi_ofuncs }, - { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs }, - {} -}; - /******************************************************************************* * PGRAPH register lists ******************************************************************************/ @@ -371,6 +358,18 @@ gm204_gr_init(struct nvkm_object *object) return gm204_gr_init_ctxctl(gr); } +static const struct gf100_gr_func +gm204_gr = { + .grctx = &gm204_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, MAXWELL_B, &gf100_fermi }, + { -1, -1, MAXWELL_COMPUTE_B }, + {} + } +}; + struct nvkm_oclass * gm204_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x24), @@ -380,8 +379,7 @@ gm204_gr_oclass = &(struct gf100_gr_oclass) { .init = gm204_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gm204_grctx_oclass, - .sclass = gm204_gr_sclass, + .func = &gm204_gr, .mmio = gm204_gr_pack_mmio, .ppc_nr = 2, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c index 04b9733d146a..4350b08f8dd2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c @@ -24,6 +24,20 @@ #include "gf100.h" #include "ctxgf100.h" +#include + +static const struct gf100_gr_func +gm206_gr = { + .grctx = &gm206_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, MAXWELL_B, &gf100_fermi }, + { -1, -1, MAXWELL_COMPUTE_B }, + {} + } +}; + struct nvkm_oclass * gm206_gr_oclass = &(struct gf100_gr_oclass) { .base.handle = NV_ENGINE(GR, 0x26), @@ -33,8 +47,7 @@ gm206_gr_oclass = &(struct gf100_gr_oclass) { .init = gm204_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gm206_grctx_oclass, - .sclass = gm204_gr_sclass, + .func = &gm206_gr, .mmio = gm204_gr_pack_mmio, .ppc_nr = 2, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 87388926efa6..7a663654543b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -22,17 +22,9 @@ #include "gk20a.h" #include "ctxgf100.h" -#include #include -static struct nvkm_oclass -gm20b_gr_sclass[] = { - { FERMI_TWOD_A, &nvkm_object_ofuncs }, - { KEPLER_INLINE_TO_MEMORY_B, &nvkm_object_ofuncs }, - { MAXWELL_B, &gf100_fermi_ofuncs }, - { MAXWELL_COMPUTE_B, &nvkm_object_ofuncs }, - {} -}; +#include static void gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) @@ -67,6 +59,18 @@ gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) nvkm_wr32(device, 0x419e4c, 0x5); } +static const struct gf100_gr_func +gm20b_gr = { + .grctx = &gm20b_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, + { -1, -1, MAXWELL_B, &gf100_fermi }, + { -1, -1, MAXWELL_COMPUTE_B }, + {} + } +}; + struct nvkm_oclass * gm20b_gr_oclass = &(struct gk20a_gr_oclass) { .gf100 = { @@ -77,8 +81,7 @@ gm20b_gr_oclass = &(struct gk20a_gr_oclass) { .init = gk20a_gr_init, .fini = _nvkm_gr_fini, }, - .cclass = &gm20b_grctx_oclass, - .sclass = gm20b_gr_sclass, + .func = &gm20b_gr, .ppc_nr = 1, }, .init_gpc_mmu = gm20b_gr_init_gpc_mmu, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index e2d3d79ee37b..f06c16f61a98 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -21,7 +21,7 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include +#include "priv.h" #include "regs.h" #include @@ -345,25 +345,23 @@ nv04_gr_ctx_regs[] = { NV04_PGRAPH_DEBUG_3 }; +#define nv04_gr(p) container_of((p), struct nv04_gr, base) + struct nv04_gr { struct nvkm_gr base; struct nv04_gr_chan *chan[16]; spinlock_t lock; }; +#define nv04_gr_chan(p) container_of((p), struct nv04_gr_chan, object) + struct nv04_gr_chan { - struct nvkm_object base; + struct nvkm_object object; + struct nv04_gr *gr; int chid; u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)]; }; - -static inline struct nv04_gr * -nv04_gr(struct nv04_gr_chan *chan) -{ - return (void *)nv_object(chan)->engine; -} - /******************************************************************************* * Graphics object classes ******************************************************************************/ @@ -1041,85 +1039,28 @@ nv04_gr_mthd(struct nvkm_device *device, u32 inst, u32 mthd, u32 data) } static int -nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, + int align, struct nvkm_gpuobj **pgpuobj) { - struct nvkm_gpuobj *obj; - int ret; - - ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); - *pobject = nv_object(obj); - if (ret) - return ret; - - nvkm_kmap(obj); - nvkm_wo32(obj, 0x00, nv_mclass(obj)); + int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, align, + false, parent, pgpuobj); + if (ret == 0) { + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x04, 0x00000000); + nvkm_wo32(*pgpuobj, 0x08, 0x00000000); #ifdef __BIG_ENDIAN - nvkm_mo32(obj, 0x00, 0x00080000, 0x00080000); + nvkm_mo32(*pgpuobj, 0x08, 0x00080000, 0x00080000); #endif - nvkm_wo32(obj, 0x04, 0x00000000); - nvkm_wo32(obj, 0x08, 0x00000000); - nvkm_wo32(obj, 0x0c, 0x00000000); - nvkm_done(obj); - return 0; + nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); + nvkm_done(*pgpuobj); + } + return ret; } -struct nvkm_ofuncs -nv04_gr_ofuncs = { - .ctor = nv04_gr_object_ctor, - .dtor = _nvkm_gpuobj_dtor, - .init = _nvkm_gpuobj_init, - .fini = _nvkm_gpuobj_fini, - .rd32 = _nvkm_gpuobj_rd32, - .wr32 = _nvkm_gpuobj_wr32, -}; - -static struct nvkm_oclass -nv04_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ - { 0x0017, &nv04_gr_ofuncs }, /* chroma */ - { 0x0018, &nv04_gr_ofuncs }, /* pattern (nv01) */ - { 0x0019, &nv04_gr_ofuncs }, /* clip */ - { 0x001c, &nv04_gr_ofuncs }, /* line */ - { 0x001d, &nv04_gr_ofuncs }, /* tri */ - { 0x001e, &nv04_gr_ofuncs }, /* rect */ - { 0x001f, &nv04_gr_ofuncs }, - { 0x0021, &nv04_gr_ofuncs }, - { 0x0030, &nv04_gr_ofuncs }, /* null */ - { 0x0036, &nv04_gr_ofuncs }, - { 0x0037, &nv04_gr_ofuncs }, - { 0x0038, &nv04_gr_ofuncs }, /* dvd subpicture */ - { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ - { 0x0042, &nv04_gr_ofuncs }, /* surf2d */ - { 0x0043, &nv04_gr_ofuncs }, /* rop */ - { 0x0044, &nv04_gr_ofuncs }, /* pattern */ - { 0x0048, &nv04_gr_ofuncs }, - { 0x004a, &nv04_gr_ofuncs }, - { 0x004b, &nv04_gr_ofuncs }, - { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ - { 0x0053, &nv04_gr_ofuncs }, - { 0x0054, &nv04_gr_ofuncs }, /* ttri */ - { 0x0055, &nv04_gr_ofuncs }, /* mtri */ - { 0x0057, &nv04_gr_ofuncs }, /* chroma */ - { 0x0058, &nv04_gr_ofuncs }, /* surf_dst */ - { 0x0059, &nv04_gr_ofuncs }, /* surf_src */ - { 0x005a, &nv04_gr_ofuncs }, /* surf_color */ - { 0x005b, &nv04_gr_ofuncs }, /* surf_zeta */ - { 0x005c, &nv04_gr_ofuncs }, /* line */ - { 0x005d, &nv04_gr_ofuncs }, /* tri */ - { 0x005e, &nv04_gr_ofuncs }, /* rect */ - { 0x005f, &nv04_gr_ofuncs }, - { 0x0060, &nv04_gr_ofuncs }, - { 0x0061, &nv04_gr_ofuncs }, - { 0x0064, &nv04_gr_ofuncs }, /* iifc (nv05) */ - { 0x0065, &nv04_gr_ofuncs }, /* ifc (nv05) */ - { 0x0066, &nv04_gr_ofuncs }, /* sifc (nv05) */ - { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ - { 0x0076, &nv04_gr_ofuncs }, - { 0x0077, &nv04_gr_ofuncs }, - {}, +const struct nvkm_object_func +nv04_gr_object = { + .bind = nv04_gr_object_bind, }; /******************************************************************************* @@ -1142,8 +1083,7 @@ nv04_gr_channel(struct nv04_gr *gr) static int nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) { - struct nv04_gr *gr = nv04_gr(chan); - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_device *device = chan->gr->base.engine.subdev.device; int i; for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) @@ -1158,8 +1098,7 @@ nv04_gr_load_context(struct nv04_gr_chan *chan, int chid) static int nv04_gr_unload_context(struct nv04_gr_chan *chan) { - struct nv04_gr *gr = nv04_gr(chan); - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_device *device = chan->gr->base.engine.subdev.device; int i; for (i = 0; i < ARRAY_SIZE(nv04_gr_ctx_regs); i++) @@ -1178,7 +1117,7 @@ nv04_gr_context_switch(struct nv04_gr *gr) struct nv04_gr_chan *next = NULL; int chid; - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); /* If previous context is valid, we need to save it */ prev = nv04_gr_channel(gr); @@ -1204,59 +1143,24 @@ static u32 *ctx_reg(struct nv04_gr_chan *chan, u32 reg) return NULL; } -static int -nv04_gr_context_ctor(struct nvkm_object *parent, - struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_fifo_chan *fifo = (void *)parent; - struct nv04_gr *gr = (void *)engine; - struct nv04_gr_chan *chan; - unsigned long flags; - int ret; - - ret = nvkm_object_create(parent, engine, oclass, 0, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - spin_lock_irqsave(&gr->lock, flags); - if (gr->chan[fifo->chid]) { - *pobject = nv_object(gr->chan[fifo->chid]); - atomic_inc(&(*pobject)->refcount); - spin_unlock_irqrestore(&gr->lock, flags); - nvkm_object_destroy(&chan->base); - return 1; - } - - *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; - - gr->chan[fifo->chid] = chan; - chan->chid = fifo->chid; - spin_unlock_irqrestore(&gr->lock, flags); - return 0; -} - -static void -nv04_gr_context_dtor(struct nvkm_object *object) +static void * +nv04_gr_chan_dtor(struct nvkm_object *object) { - struct nv04_gr *gr = (void *)object->engine; - struct nv04_gr_chan *chan = (void *)object; + struct nv04_gr_chan *chan = nv04_gr_chan(object); + struct nv04_gr *gr = chan->gr; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); gr->chan[chan->chid] = NULL; spin_unlock_irqrestore(&gr->lock, flags); - - nvkm_object_destroy(&chan->base); + return chan; } static int -nv04_gr_context_fini(struct nvkm_object *object, bool suspend) +nv04_gr_chan_fini(struct nvkm_object *object, bool suspend) { - struct nv04_gr *gr = (void *)object->engine; - struct nv04_gr_chan *chan = (void *)object; + struct nv04_gr_chan *chan = nv04_gr_chan(object); + struct nv04_gr *gr = chan->gr; struct nvkm_device *device = gr->base.engine.subdev.device; unsigned long flags; @@ -1266,34 +1170,50 @@ nv04_gr_context_fini(struct nvkm_object *object, bool suspend) nv04_gr_unload_context(chan); nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); spin_unlock_irqrestore(&gr->lock, flags); - - return _nvkm_object_fini(&chan->base, suspend); + return 0; } -static struct nvkm_oclass -nv04_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_gr_context_ctor, - .dtor = nv04_gr_context_dtor, - .init = _nvkm_object_init, - .fini = nv04_gr_context_fini, - }, +static const struct nvkm_object_func +nv04_gr_chan = { + .dtor = nv04_gr_chan_dtor, + .fini = nv04_gr_chan_fini, }; +static int +nv04_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) +{ + struct nv04_gr *gr = nv04_gr(base); + struct nv04_gr_chan *chan; + unsigned long flags; + + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv04_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; + + spin_lock_irqsave(&gr->lock, flags); + gr->chan[chan->chid] = chan; + spin_unlock_irqrestore(&gr->lock, flags); + return 0; +} + /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ bool -nv04_gr_idle(void *obj) +nv04_gr_idle(struct nvkm_gr *gr) { - struct nvkm_gr *gr = nvkm_gr(obj); struct nvkm_subdev *subdev = &gr->engine.subdev; struct nvkm_device *device = subdev->device; u32 mask = 0xffffffff; - if (nv_device(obj)->card_type == NV_40) + if (device->card_type == NV_40) mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; if (nvkm_msec(device, 2000, @@ -1395,12 +1315,62 @@ nv04_gr_intr(struct nvkm_subdev *subdev) "nstatus %08x [%s] ch %d [%s] subc %d " "class %04x mthd %04x data %08x\n", show, msg, nsource, src, nstatus, sta, chid, - nvkm_client_name(chan), subc, class, mthd, data); + chan ? chan->object.client->name : "unknown", + subc, class, mthd, data); } spin_unlock_irqrestore(&gr->lock, flags); } +static const struct nvkm_gr_func +nv04_gr = { + .chan_new = nv04_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0017, &nv04_gr_object }, /* chroma */ + { -1, -1, 0x0018, &nv04_gr_object }, /* pattern (nv01) */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x001c, &nv04_gr_object }, /* line */ + { -1, -1, 0x001d, &nv04_gr_object }, /* tri */ + { -1, -1, 0x001e, &nv04_gr_object }, /* rect */ + { -1, -1, 0x001f, &nv04_gr_object }, + { -1, -1, 0x0021, &nv04_gr_object }, + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0036, &nv04_gr_object }, + { -1, -1, 0x0037, &nv04_gr_object }, + { -1, -1, 0x0038, &nv04_gr_object }, /* dvd subpicture */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0042, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x0048, &nv04_gr_object }, + { -1, -1, 0x004a, &nv04_gr_object }, + { -1, -1, 0x004b, &nv04_gr_object }, + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x0053, &nv04_gr_object }, + { -1, -1, 0x0054, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0055, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0057, &nv04_gr_object }, /* chroma */ + { -1, -1, 0x0058, &nv04_gr_object }, /* surf_dst */ + { -1, -1, 0x0059, &nv04_gr_object }, /* surf_src */ + { -1, -1, 0x005a, &nv04_gr_object }, /* surf_color */ + { -1, -1, 0x005b, &nv04_gr_object }, /* surf_zeta */ + { -1, -1, 0x005c, &nv04_gr_object }, /* line */ + { -1, -1, 0x005d, &nv04_gr_object }, /* tri */ + { -1, -1, 0x005e, &nv04_gr_object }, /* rect */ + { -1, -1, 0x005f, &nv04_gr_object }, + { -1, -1, 0x0060, &nv04_gr_object }, + { -1, -1, 0x0061, &nv04_gr_object }, + { -1, -1, 0x0064, &nv04_gr_object }, /* iifc (nv05) */ + { -1, -1, 0x0065, &nv04_gr_object }, /* ifc (nv05) */ + { -1, -1, 0x0066, &nv04_gr_object }, /* sifc (nv05) */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0076, &nv04_gr_object }, + { -1, -1, 0x0077, &nv04_gr_object }, + {} + } +}; + static int nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -1414,10 +1384,9 @@ nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv04_gr; nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv04_gr_intr; - nv_engine(gr)->cclass = &nv04_gr_cclass; - nv_engine(gr)->sclass = nv04_gr_sclass; spin_lock_init(&gr->lock); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 761aaa451e21..98fb9e6efb97 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -21,7 +21,7 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include +#include "priv.h" #include "regs.h" #include @@ -385,14 +385,19 @@ static int nv17_gr_ctx_regs[] = { 0x00400a04, }; +#define nv10_gr(p) container_of((p), struct nv10_gr, base) + struct nv10_gr { struct nvkm_gr base; struct nv10_gr_chan *chan[32]; spinlock_t lock; }; +#define nv10_gr_chan(p) container_of((p), struct nv10_gr_chan, object) + struct nv10_gr_chan { - struct nvkm_object base; + struct nvkm_object object; + struct nv10_gr *gr; int chid; int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)]; int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)]; @@ -401,12 +406,6 @@ struct nv10_gr_chan { }; -static inline struct nv10_gr * -nv10_gr(struct nv10_gr_chan *chan) -{ - return (void *)nv_object(chan)->engine; -} - /******************************************************************************* * Graphics object classes ******************************************************************************/ @@ -427,57 +426,11 @@ nv10_gr(struct nv10_gr_chan *chan) nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \ } while (0) -static struct nvkm_oclass -nv10_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs }, /* clip */ - { 0x0030, &nv04_gr_ofuncs }, /* null */ - { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs }, /* rop */ - { 0x0044, &nv04_gr_ofuncs }, /* pattern */ - { 0x004a, &nv04_gr_ofuncs }, /* gdi */ - { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_gr_ofuncs }, /* blit */ - { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs }, /* ifc */ - { 0x009f, &nv04_gr_ofuncs }, /* blit */ - { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ - { 0x0094, &nv04_gr_ofuncs }, /* ttri */ - { 0x0095, &nv04_gr_ofuncs }, /* mtri */ - { 0x0056, &nv04_gr_ofuncs }, /* celcius */ - {}, -}; - -static struct nvkm_oclass -nv15_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs }, /* clip */ - { 0x0030, &nv04_gr_ofuncs }, /* null */ - { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs }, /* rop */ - { 0x0044, &nv04_gr_ofuncs }, /* pattern */ - { 0x004a, &nv04_gr_ofuncs }, /* gdi */ - { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_gr_ofuncs }, /* blit */ - { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs }, /* ifc */ - { 0x009f, &nv04_gr_ofuncs }, /* blit */ - { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ - { 0x0094, &nv04_gr_ofuncs }, /* ttri */ - { 0x0095, &nv04_gr_ofuncs }, /* mtri */ - { 0x0096, &nv04_gr_ofuncs }, /* celcius */ - {}, -}; - static void nv17_gr_mthd_lma_window(struct nv10_gr_chan *chan, u32 mthd, u32 data) { - struct nvkm_device *device = chan->base.engine->subdev.device; - struct nvkm_gr *gr = nvkm_gr(chan); + struct nvkm_device *device = chan->object.engine->subdev.device; + struct nvkm_gr *gr = &chan->gr->base; struct pipe_state *pipe = &chan->pipe_state; u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; u32 xfmode0, xfmode1; @@ -549,8 +502,8 @@ nv17_gr_mthd_lma_window(struct nv10_gr_chan *chan, u32 mthd, u32 data) static void nv17_gr_mthd_lma_enable(struct nv10_gr_chan *chan, u32 mthd, u32 data) { - struct nvkm_device *device = chan->base.engine->subdev.device; - struct nvkm_gr *gr = nvkm_gr(chan); + struct nvkm_device *device = chan->object.engine->subdev.device; + struct nvkm_gr *gr = &chan->gr->base; nv04_gr_idle(gr); @@ -585,29 +538,6 @@ nv10_gr_mthd(struct nv10_gr_chan *chan, u8 class, u32 mthd, u32 data) return func(chan, mthd, data); } -static struct nvkm_oclass -nv17_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs }, /* clip */ - { 0x0030, &nv04_gr_ofuncs }, /* null */ - { 0x0039, &nv04_gr_ofuncs }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs }, /* rop */ - { 0x0044, &nv04_gr_ofuncs }, /* pattern */ - { 0x004a, &nv04_gr_ofuncs }, /* gdi */ - { 0x0052, &nv04_gr_ofuncs }, /* swzsurf */ - { 0x005f, &nv04_gr_ofuncs }, /* blit */ - { 0x0062, &nv04_gr_ofuncs }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs }, /* ifc */ - { 0x009f, &nv04_gr_ofuncs }, /* blit */ - { 0x0093, &nv04_gr_ofuncs }, /* surf3d */ - { 0x0094, &nv04_gr_ofuncs }, /* ttri */ - { 0x0095, &nv04_gr_ofuncs }, /* mtri */ - { 0x0099, &nv04_gr_ofuncs }, - {}, -}; - /******************************************************************************* * PGRAPH context ******************************************************************************/ @@ -628,7 +558,7 @@ nv10_gr_channel(struct nv10_gr *gr) static void nv10_gr_save_pipe(struct nv10_gr_chan *chan) { - struct nv10_gr *gr = nv10_gr(chan); + struct nv10_gr *gr = chan->gr; struct pipe_state *pipe = &chan->pipe_state; struct nvkm_device *device = gr->base.engine.subdev.device; @@ -647,13 +577,13 @@ nv10_gr_save_pipe(struct nv10_gr_chan *chan) static void nv10_gr_load_pipe(struct nv10_gr_chan *chan) { - struct nv10_gr *gr = nv10_gr(chan); + struct nv10_gr *gr = chan->gr; struct pipe_state *pipe = &chan->pipe_state; struct nvkm_device *device = gr->base.engine.subdev.device; u32 xfmode0, xfmode1; int i; - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); /* XXX check haiku comments */ xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); @@ -678,7 +608,7 @@ nv10_gr_load_pipe(struct nv10_gr_chan *chan) PIPE_RESTORE(gr, pipe->pipe_0x0200, 0x0200); - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); /* restore XFMODE */ nvkm_wr32(device, NV10_PGRAPH_XFMODE0, xfmode0); @@ -692,13 +622,13 @@ nv10_gr_load_pipe(struct nv10_gr_chan *chan) PIPE_RESTORE(gr, pipe->pipe_0x4400, 0x4400); PIPE_RESTORE(gr, pipe->pipe_0x0000, 0x0000); PIPE_RESTORE(gr, pipe->pipe_0x0040, 0x0040); - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); } static void nv10_gr_create_pipe(struct nv10_gr_chan *chan) { - struct nv10_gr *gr = nv10_gr(chan); + struct nv10_gr *gr = chan->gr; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct pipe_state *pipe_state = &chan->pipe_state; u32 *pipe_state_addr; @@ -880,7 +810,7 @@ nv17_gr_ctx_regs_find_offset(struct nv10_gr *gr, int reg) static void nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) { - struct nv10_gr *gr = nv10_gr(chan); + struct nv10_gr *gr = chan->gr; struct nvkm_device *device = gr->base.engine.subdev.device; u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; u32 ctx_user, ctx_switch[5]; @@ -951,7 +881,7 @@ nv10_gr_load_dma_vtxbuf(struct nv10_gr_chan *chan, int chid, u32 inst) static int nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) { - struct nv10_gr *gr = nv10_gr(chan); + struct nv10_gr *gr = chan->gr; struct nvkm_device *device = gr->base.engine.subdev.device; u32 inst; int i; @@ -979,7 +909,7 @@ nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) static int nv10_gr_unload_context(struct nv10_gr_chan *chan) { - struct nv10_gr *gr = nv10_gr(chan); + struct nv10_gr *gr = chan->gr; struct nvkm_device *device = gr->base.engine.subdev.device; int i; @@ -1007,7 +937,7 @@ nv10_gr_context_switch(struct nv10_gr *gr) struct nv10_gr_chan *next = NULL; int chid; - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); /* If previous context is valid, we need to save it */ prev = nv10_gr_channel(gr); @@ -1021,6 +951,42 @@ nv10_gr_context_switch(struct nv10_gr *gr) nv10_gr_load_context(next, chid); } +static int +nv10_gr_chan_fini(struct nvkm_object *object, bool suspend) +{ + struct nv10_gr_chan *chan = nv10_gr_chan(object); + struct nv10_gr *gr = chan->gr; + struct nvkm_device *device = gr->base.engine.subdev.device; + unsigned long flags; + + spin_lock_irqsave(&gr->lock, flags); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); + if (nv10_gr_channel(gr) == chan) + nv10_gr_unload_context(chan); + nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&gr->lock, flags); + return 0; +} + +static void * +nv10_gr_chan_dtor(struct nvkm_object *object) +{ + struct nv10_gr_chan *chan = nv10_gr_chan(object); + struct nv10_gr *gr = chan->gr; + unsigned long flags; + + spin_lock_irqsave(&gr->lock, flags); + gr->chan[chan->chid] = NULL; + spin_unlock_irqrestore(&gr->lock, flags); + return chan; +} + +static const struct nvkm_object_func +nv10_gr_chan = { + .dtor = nv10_gr_chan_dtor, + .fini = nv10_gr_chan_fini, +}; + #define NV_WRITE_CTX(reg, val) do { \ int offset = nv10_gr_ctx_regs_find_offset(gr, reg); \ if (offset > 0) \ @@ -1034,30 +1000,20 @@ nv10_gr_context_switch(struct nv10_gr *gr) } while (0) static int -nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv10_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { - struct nvkm_fifo_chan *fifo = (void *)parent; - struct nv10_gr *gr = (void *)engine; + struct nv10_gr *gr = nv10_gr(base); struct nv10_gr_chan *chan; struct nvkm_device *device = gr->base.engine.subdev.device; unsigned long flags; - int ret; - - ret = nvkm_object_create(parent, engine, oclass, 0, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - spin_lock_irqsave(&gr->lock, flags); - if (gr->chan[fifo->chid]) { - *pobject = nv_object(gr->chan[fifo->chid]); - atomic_inc(&(*pobject)->refcount); - spin_unlock_irqrestore(&gr->lock, flags); - nvkm_object_destroy(&chan->base); - return 1; - } + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv10_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; NV_WRITE_CTX(0x00400e88, 0x08000000); NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); @@ -1066,11 +1022,10 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, NV_WRITE_CTX(0x00400e14, 0x00001000); NV_WRITE_CTX(0x00400e30, 0x00080008); NV_WRITE_CTX(0x00400e34, 0x00080008); - if (nv_device(gr)->card_type >= NV_11 && - nv_device(gr)->chipset >= 0x17) { + if (device->card_type >= NV_11 && device->chipset >= 0x17) { /* is it really needed ??? */ NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, - nvkm_rd32(device, NV10_PGRAPH_DEBUG_4)); + nvkm_rd32(device, NV10_PGRAPH_DEBUG_4)); NV17_WRITE_CTX(0x004006b0, nvkm_rd32(device, 0x004006b0)); NV17_WRITE_CTX(0x00400eac, 0x0fff0000); NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); @@ -1081,55 +1036,12 @@ nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_gr_create_pipe(chan); - gr->chan[fifo->chid] = chan; - chan->chid = fifo->chid; - spin_unlock_irqrestore(&gr->lock, flags); - return 0; -} - -static void -nv10_gr_context_dtor(struct nvkm_object *object) -{ - struct nv10_gr *gr = (void *)object->engine; - struct nv10_gr_chan *chan = (void *)object; - unsigned long flags; - spin_lock_irqsave(&gr->lock, flags); - gr->chan[chan->chid] = NULL; + gr->chan[chan->chid] = chan; spin_unlock_irqrestore(&gr->lock, flags); - - nvkm_object_destroy(&chan->base); -} - -static int -nv10_gr_context_fini(struct nvkm_object *object, bool suspend) -{ - struct nv10_gr *gr = (void *)object->engine; - struct nv10_gr_chan *chan = (void *)object; - struct nvkm_device *device = gr->base.engine.subdev.device; - unsigned long flags; - - spin_lock_irqsave(&gr->lock, flags); - nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); - if (nv10_gr_channel(gr) == chan) - nv10_gr_unload_context(chan); - nvkm_mask(device, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&gr->lock, flags); - - return _nvkm_object_fini(&chan->base, suspend); + return 0; } -static struct nvkm_oclass -nv10_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x10), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv10_gr_context_ctor, - .dtor = nv10_gr_context_dtor, - .init = _nvkm_object_init, - .fini = nv10_gr_context_fini, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ @@ -1144,7 +1056,7 @@ nv10_gr_tile_prog(struct nvkm_engine *engine, int i) unsigned long flags; fifo->pause(fifo, &flags); - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); @@ -1214,12 +1126,92 @@ nv10_gr_intr(struct nvkm_subdev *subdev) "nstatus %08x [%s] ch %d [%s] subc %d " "class %04x mthd %04x data %08x\n", show, msg, nsource, src, nstatus, sta, chid, - nvkm_client_name(chan), subc, class, mthd, data); + chan ? chan->object.client->name : "unknown", + subc, class, mthd, data); } spin_unlock_irqrestore(&gr->lock, flags); } +static const struct nvkm_gr_func +nv10_gr = { + .chan_new = nv10_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ + { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0056, &nv04_gr_object }, /* celcius */ + {} + } +}; + +static const struct nvkm_gr_func +nv15_gr = { + .chan_new = nv10_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ + { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + {} + } +}; + + +static const struct nvkm_gr_func +nv17_gr = { + .chan_new = nv10_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ + { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0099, &nv04_gr_object }, + {} + } +}; + static int nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -1235,16 +1227,15 @@ nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv10_gr_intr; - nv_engine(gr)->cclass = &nv10_gr_cclass; if (nv_device(gr)->chipset <= 0x10) - nv_engine(gr)->sclass = nv10_gr_sclass; + gr->base.func = &nv10_gr; else if (nv_device(gr)->chipset < 0x17 || nv_device(gr)->card_type < NV_11) - nv_engine(gr)->sclass = nv15_gr_sclass; + gr->base.func = &nv15_gr; else - nv_engine(gr)->sclass = nv17_gr_sclass; + gr->base.func = &nv17_gr; nv_engine(gr)->tile_prog = nv10_gr_tile_prog; spin_lock_init(&gr->lock); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 29feab391fe4..554f2e3f7e5b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -7,131 +7,37 @@ #include #include -/******************************************************************************* - * Graphics object classes - ******************************************************************************/ - -static struct nvkm_oclass -nv20_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ - { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ - { 0x0097, &nv04_gr_ofuncs, NULL }, /* kelvin */ - { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ - { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ - {}, -}; - /******************************************************************************* * PGRAPH context ******************************************************************************/ -static int -nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; - int ret, i; - - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x033c, 0xffff0000); - nvkm_wo32(image, 0x03a0, 0x0fff0000); - nvkm_wo32(image, 0x03a4, 0x0fff0000); - nvkm_wo32(image, 0x047c, 0x00000101); - nvkm_wo32(image, 0x0490, 0x00000111); - nvkm_wo32(image, 0x04a8, 0x44400000); - for (i = 0x04d4; i <= 0x04e0; i += 4) - nvkm_wo32(image, i, 0x00030303); - for (i = 0x04f4; i <= 0x0500; i += 4) - nvkm_wo32(image, i, 0x00080000); - for (i = 0x050c; i <= 0x0518; i += 4) - nvkm_wo32(image, i, 0x01012000); - for (i = 0x051c; i <= 0x0528; i += 4) - nvkm_wo32(image, i, 0x000105b8); - for (i = 0x052c; i <= 0x0538; i += 4) - nvkm_wo32(image, i, 0x00080008); - for (i = 0x055c; i <= 0x0598; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x05a4, 0x4b7fffff); - nvkm_wo32(image, 0x05fc, 0x00000001); - nvkm_wo32(image, 0x0604, 0x00004000); - nvkm_wo32(image, 0x0610, 0x00000001); - nvkm_wo32(image, 0x0618, 0x00040000); - nvkm_wo32(image, 0x061c, 0x00010000); - for (i = 0x1c1c; i <= 0x248c; i += 16) { - nvkm_wo32(image, (i + 0), 0x10700ff9); - nvkm_wo32(image, (i + 4), 0x0436086c); - nvkm_wo32(image, (i + 8), 0x000c001b); - } - nvkm_wo32(image, 0x281c, 0x3f800000); - nvkm_wo32(image, 0x2830, 0x3f800000); - nvkm_wo32(image, 0x285c, 0x40000000); - nvkm_wo32(image, 0x2860, 0x3f800000); - nvkm_wo32(image, 0x2864, 0x3f000000); - nvkm_wo32(image, 0x286c, 0x40000000); - nvkm_wo32(image, 0x2870, 0x3f800000); - nvkm_wo32(image, 0x2878, 0xbf800000); - nvkm_wo32(image, 0x2880, 0xbf800000); - nvkm_wo32(image, 0x34a4, 0x000fe000); - nvkm_wo32(image, 0x3530, 0x000003f8); - nvkm_wo32(image, 0x3540, 0x002fe000); - for (i = 0x355c; i <= 0x3578; i += 4) - nvkm_wo32(image, i, 0x001c527c); - nvkm_done(image); - return 0; -} - int -nv20_gr_context_init(struct nvkm_object *object) +nv20_gr_chan_init(struct nvkm_object *object) { - struct nv20_gr *gr = (void *)object->engine; - struct nv20_gr_chan *chan = (void *)object; - int ret; - - ret = nvkm_gr_context_init(&chan->base); - if (ret) - return ret; + struct nv20_gr_chan *chan = nv20_gr_chan(object); + struct nv20_gr *gr = chan->gr; + u32 inst = nvkm_memory_addr(chan->inst); nvkm_kmap(gr->ctxtab); - nvkm_wo32(gr->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); + nvkm_wo32(gr->ctxtab, chan->chid * 4, inst >> 4); nvkm_done(gr->ctxtab); return 0; } int -nv20_gr_context_fini(struct nvkm_object *object, bool suspend) +nv20_gr_chan_fini(struct nvkm_object *object, bool suspend) { - struct nv20_gr *gr = (void *)object->engine; - struct nv20_gr_chan *chan = (void *)object; + struct nv20_gr_chan *chan = nv20_gr_chan(object); + struct nv20_gr *gr = chan->gr; struct nvkm_device *device = gr->base.engine.subdev.device; + u32 inst = nvkm_memory_addr(chan->inst); int chid = -1; nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); if (nvkm_rd32(device, 0x400144) & 0x00010000) chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; if (chan->chid == chid) { - nvkm_wr32(device, 0x400784, nv_gpuobj(chan)->addr >> 4); + nvkm_wr32(device, 0x400784, inst >> 4); nvkm_wr32(device, 0x400788, 0x00000002); nvkm_msec(device, 2000, if (!nvkm_rd32(device, 0x400700)) @@ -145,23 +51,94 @@ nv20_gr_context_fini(struct nvkm_object *object, bool suspend) nvkm_kmap(gr->ctxtab); nvkm_wo32(gr->ctxtab, chan->chid * 4, 0x00000000); nvkm_done(gr->ctxtab); + return 0; +} - return nvkm_gr_context_fini(&chan->base, suspend); +void * +nv20_gr_chan_dtor(struct nvkm_object *object) +{ + struct nv20_gr_chan *chan = nv20_gr_chan(object); + nvkm_memory_del(&chan->inst); + return chan; } -static struct nvkm_oclass -nv20_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x20), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv20_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +static const struct nvkm_object_func +nv20_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, }; +static int +nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) +{ + struct nv20_gr *gr = nv20_gr(base); + struct nv20_gr_chan *chan; + int ret, i; + + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv20_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x37f0, 16, true, + &chan->inst); + if (ret) + return ret; + + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x033c, 0xffff0000); + nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); + nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); + nvkm_wo32(chan->inst, 0x047c, 0x00000101); + nvkm_wo32(chan->inst, 0x0490, 0x00000111); + nvkm_wo32(chan->inst, 0x04a8, 0x44400000); + for (i = 0x04d4; i <= 0x04e0; i += 4) + nvkm_wo32(chan->inst, i, 0x00030303); + for (i = 0x04f4; i <= 0x0500; i += 4) + nvkm_wo32(chan->inst, i, 0x00080000); + for (i = 0x050c; i <= 0x0518; i += 4) + nvkm_wo32(chan->inst, i, 0x01012000); + for (i = 0x051c; i <= 0x0528; i += 4) + nvkm_wo32(chan->inst, i, 0x000105b8); + for (i = 0x052c; i <= 0x0538; i += 4) + nvkm_wo32(chan->inst, i, 0x00080008); + for (i = 0x055c; i <= 0x0598; i += 4) + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x05fc, 0x00000001); + nvkm_wo32(chan->inst, 0x0604, 0x00004000); + nvkm_wo32(chan->inst, 0x0610, 0x00000001); + nvkm_wo32(chan->inst, 0x0618, 0x00040000); + nvkm_wo32(chan->inst, 0x061c, 0x00010000); + for (i = 0x1c1c; i <= 0x248c; i += 16) { + nvkm_wo32(chan->inst, (i + 0), 0x10700ff9); + nvkm_wo32(chan->inst, (i + 4), 0x0436086c); + nvkm_wo32(chan->inst, (i + 8), 0x000c001b); + } + nvkm_wo32(chan->inst, 0x281c, 0x3f800000); + nvkm_wo32(chan->inst, 0x2830, 0x3f800000); + nvkm_wo32(chan->inst, 0x285c, 0x40000000); + nvkm_wo32(chan->inst, 0x2860, 0x3f800000); + nvkm_wo32(chan->inst, 0x2864, 0x3f000000); + nvkm_wo32(chan->inst, 0x286c, 0x40000000); + nvkm_wo32(chan->inst, 0x2870, 0x3f800000); + nvkm_wo32(chan->inst, 0x2878, 0xbf800000); + nvkm_wo32(chan->inst, 0x2880, 0xbf800000); + nvkm_wo32(chan->inst, 0x34a4, 0x000fe000); + nvkm_wo32(chan->inst, 0x3530, 0x000003f8); + nvkm_wo32(chan->inst, 0x3540, 0x002fe000); + for (i = 0x355c; i <= 0x3578; i += 4) + nvkm_wo32(chan->inst, i, 0x001c527c); + nvkm_done(chan->inst); + return 0; +} + /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ @@ -176,7 +153,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) unsigned long flags; fifo->pause(fifo, &flags); - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); @@ -237,6 +214,29 @@ nv20_gr_intr(struct nvkm_subdev *subdev) nvkm_fifo_chan_put(device->fifo, flags, &chan); } +static const struct nvkm_gr_func +nv20_gr = { + .chan_new = nv20_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + { -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */ + { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + {} + } +}; + static int nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -251,6 +251,8 @@ nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv20_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -258,8 +260,6 @@ nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv20_gr_cclass; - nv_engine(gr)->sclass = nv20_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index bffbba075b4d..1ae4f2acc612 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -1,20 +1,25 @@ #ifndef __NV20_GR_H__ #define __NV20_GR_H__ -#include +#define nv20_gr(p) container_of((p), struct nv20_gr, base) +#include "priv.h" struct nv20_gr { struct nvkm_gr base; struct nvkm_memory *ctxtab; }; +#define nv20_gr_chan(p) container_of((p), struct nv20_gr_chan, object) + struct nv20_gr_chan { - struct nvkm_gr_chan base; + struct nvkm_object object; + struct nv20_gr *gr; int chid; + struct nvkm_memory *inst; }; -extern struct nvkm_oclass nv25_gr_sclass[]; -int nv20_gr_context_init(struct nvkm_object *); -int nv20_gr_context_fini(struct nvkm_object *, bool); +void *nv20_gr_chan_dtor(struct nvkm_object *); +int nv20_gr_chan_init(struct nvkm_object *); +int nv20_gr_chan_fini(struct nvkm_object *, bool); void nv20_gr_tile_prog(struct nvkm_engine *, int); void nv20_gr_intr(struct nvkm_subdev *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index 9cb5a90dde51..7fb53d53426c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -5,126 +5,122 @@ #include /******************************************************************************* - * Graphics object classes + * PGRAPH context ******************************************************************************/ -struct nvkm_oclass -nv25_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ - { 0x0096, &nv04_gr_ofuncs, NULL }, /* celcius */ - { 0x009e, &nv04_gr_ofuncs, NULL }, /* swzsurf */ - { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ - { 0x0597, &nv04_gr_ofuncs, NULL }, /* kelvin */ - {}, +static const struct nvkm_object_func +nv25_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, }; -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - static int -nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv25_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { + struct nv20_gr *gr = nv20_gr(base); struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; int ret, i; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv25_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x3724, 16, true, + &chan->inst); if (ret) return ret; - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x035c, 0xffff0000); - nvkm_wo32(image, 0x03c0, 0x0fff0000); - nvkm_wo32(image, 0x03c4, 0x0fff0000); - nvkm_wo32(image, 0x049c, 0x00000101); - nvkm_wo32(image, 0x04b0, 0x00000111); - nvkm_wo32(image, 0x04c8, 0x00000080); - nvkm_wo32(image, 0x04cc, 0xffff0000); - nvkm_wo32(image, 0x04d0, 0x00000001); - nvkm_wo32(image, 0x04e4, 0x44400000); - nvkm_wo32(image, 0x04fc, 0x4b800000); + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x035c, 0xffff0000); + nvkm_wo32(chan->inst, 0x03c0, 0x0fff0000); + nvkm_wo32(chan->inst, 0x03c4, 0x0fff0000); + nvkm_wo32(chan->inst, 0x049c, 0x00000101); + nvkm_wo32(chan->inst, 0x04b0, 0x00000111); + nvkm_wo32(chan->inst, 0x04c8, 0x00000080); + nvkm_wo32(chan->inst, 0x04cc, 0xffff0000); + nvkm_wo32(chan->inst, 0x04d0, 0x00000001); + nvkm_wo32(chan->inst, 0x04e4, 0x44400000); + nvkm_wo32(chan->inst, 0x04fc, 0x4b800000); for (i = 0x0510; i <= 0x051c; i += 4) - nvkm_wo32(image, i, 0x00030303); + nvkm_wo32(chan->inst, i, 0x00030303); for (i = 0x0530; i <= 0x053c; i += 4) - nvkm_wo32(image, i, 0x00080000); + nvkm_wo32(chan->inst, i, 0x00080000); for (i = 0x0548; i <= 0x0554; i += 4) - nvkm_wo32(image, i, 0x01012000); + nvkm_wo32(chan->inst, i, 0x01012000); for (i = 0x0558; i <= 0x0564; i += 4) - nvkm_wo32(image, i, 0x000105b8); + nvkm_wo32(chan->inst, i, 0x000105b8); for (i = 0x0568; i <= 0x0574; i += 4) - nvkm_wo32(image, i, 0x00080008); + nvkm_wo32(chan->inst, i, 0x00080008); for (i = 0x0598; i <= 0x05d4; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x05e0, 0x4b7fffff); - nvkm_wo32(image, 0x0620, 0x00000080); - nvkm_wo32(image, 0x0624, 0x30201000); - nvkm_wo32(image, 0x0628, 0x70605040); - nvkm_wo32(image, 0x062c, 0xb0a09080); - nvkm_wo32(image, 0x0630, 0xf0e0d0c0); - nvkm_wo32(image, 0x0664, 0x00000001); - nvkm_wo32(image, 0x066c, 0x00004000); - nvkm_wo32(image, 0x0678, 0x00000001); - nvkm_wo32(image, 0x0680, 0x00040000); - nvkm_wo32(image, 0x0684, 0x00010000); + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x05e0, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x0620, 0x00000080); + nvkm_wo32(chan->inst, 0x0624, 0x30201000); + nvkm_wo32(chan->inst, 0x0628, 0x70605040); + nvkm_wo32(chan->inst, 0x062c, 0xb0a09080); + nvkm_wo32(chan->inst, 0x0630, 0xf0e0d0c0); + nvkm_wo32(chan->inst, 0x0664, 0x00000001); + nvkm_wo32(chan->inst, 0x066c, 0x00004000); + nvkm_wo32(chan->inst, 0x0678, 0x00000001); + nvkm_wo32(chan->inst, 0x0680, 0x00040000); + nvkm_wo32(chan->inst, 0x0684, 0x00010000); for (i = 0x1b04; i <= 0x2374; i += 16) { - nvkm_wo32(image, (i + 0), 0x10700ff9); - nvkm_wo32(image, (i + 4), 0x0436086c); - nvkm_wo32(image, (i + 8), 0x000c001b); + nvkm_wo32(chan->inst, (i + 0), 0x10700ff9); + nvkm_wo32(chan->inst, (i + 4), 0x0436086c); + nvkm_wo32(chan->inst, (i + 8), 0x000c001b); } - nvkm_wo32(image, 0x2704, 0x3f800000); - nvkm_wo32(image, 0x2718, 0x3f800000); - nvkm_wo32(image, 0x2744, 0x40000000); - nvkm_wo32(image, 0x2748, 0x3f800000); - nvkm_wo32(image, 0x274c, 0x3f000000); - nvkm_wo32(image, 0x2754, 0x40000000); - nvkm_wo32(image, 0x2758, 0x3f800000); - nvkm_wo32(image, 0x2760, 0xbf800000); - nvkm_wo32(image, 0x2768, 0xbf800000); - nvkm_wo32(image, 0x308c, 0x000fe000); - nvkm_wo32(image, 0x3108, 0x000003f8); - nvkm_wo32(image, 0x3468, 0x002fe000); + nvkm_wo32(chan->inst, 0x2704, 0x3f800000); + nvkm_wo32(chan->inst, 0x2718, 0x3f800000); + nvkm_wo32(chan->inst, 0x2744, 0x40000000); + nvkm_wo32(chan->inst, 0x2748, 0x3f800000); + nvkm_wo32(chan->inst, 0x274c, 0x3f000000); + nvkm_wo32(chan->inst, 0x2754, 0x40000000); + nvkm_wo32(chan->inst, 0x2758, 0x3f800000); + nvkm_wo32(chan->inst, 0x2760, 0xbf800000); + nvkm_wo32(chan->inst, 0x2768, 0xbf800000); + nvkm_wo32(chan->inst, 0x308c, 0x000fe000); + nvkm_wo32(chan->inst, 0x3108, 0x000003f8); + nvkm_wo32(chan->inst, 0x3468, 0x002fe000); for (i = 0x3484; i <= 0x34a0; i += 4) - nvkm_wo32(image, i, 0x001c527c); - nvkm_done(image); + nvkm_wo32(chan->inst, i, 0x001c527c); + nvkm_done(chan->inst); return 0; } -static struct nvkm_oclass -nv25_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x25), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv25_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct nvkm_gr_func +nv25_gr = { + .chan_new = nv25_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */ + {} + } +}; + static int nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -139,6 +135,8 @@ nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv25_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -146,8 +144,6 @@ nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv25_gr_cclass; - nv_engine(gr)->sclass = nv25_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index c5d8cd6d66c0..2fabdc586651 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -8,90 +8,110 @@ * PGRAPH context ******************************************************************************/ +static const struct nvkm_object_func +nv2a_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, +}; + static int -nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { + struct nv20_gr *gr = nv20_gr(base); struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; int ret, i; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv2a_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x36b0, 16, true, + &chan->inst); if (ret) return ret; - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0000, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x033c, 0xffff0000); - nvkm_wo32(image, 0x03a0, 0x0fff0000); - nvkm_wo32(image, 0x03a4, 0x0fff0000); - nvkm_wo32(image, 0x047c, 0x00000101); - nvkm_wo32(image, 0x0490, 0x00000111); - nvkm_wo32(image, 0x04a8, 0x44400000); + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0000, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x033c, 0xffff0000); + nvkm_wo32(chan->inst, 0x03a0, 0x0fff0000); + nvkm_wo32(chan->inst, 0x03a4, 0x0fff0000); + nvkm_wo32(chan->inst, 0x047c, 0x00000101); + nvkm_wo32(chan->inst, 0x0490, 0x00000111); + nvkm_wo32(chan->inst, 0x04a8, 0x44400000); for (i = 0x04d4; i <= 0x04e0; i += 4) - nvkm_wo32(image, i, 0x00030303); + nvkm_wo32(chan->inst, i, 0x00030303); for (i = 0x04f4; i <= 0x0500; i += 4) - nvkm_wo32(image, i, 0x00080000); + nvkm_wo32(chan->inst, i, 0x00080000); for (i = 0x050c; i <= 0x0518; i += 4) - nvkm_wo32(image, i, 0x01012000); + nvkm_wo32(chan->inst, i, 0x01012000); for (i = 0x051c; i <= 0x0528; i += 4) - nvkm_wo32(image, i, 0x000105b8); + nvkm_wo32(chan->inst, i, 0x000105b8); for (i = 0x052c; i <= 0x0538; i += 4) - nvkm_wo32(image, i, 0x00080008); + nvkm_wo32(chan->inst, i, 0x00080008); for (i = 0x055c; i <= 0x0598; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x05a4, 0x4b7fffff); - nvkm_wo32(image, 0x05fc, 0x00000001); - nvkm_wo32(image, 0x0604, 0x00004000); - nvkm_wo32(image, 0x0610, 0x00000001); - nvkm_wo32(image, 0x0618, 0x00040000); - nvkm_wo32(image, 0x061c, 0x00010000); + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x05a4, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x05fc, 0x00000001); + nvkm_wo32(chan->inst, 0x0604, 0x00004000); + nvkm_wo32(chan->inst, 0x0610, 0x00000001); + nvkm_wo32(chan->inst, 0x0618, 0x00040000); + nvkm_wo32(chan->inst, 0x061c, 0x00010000); for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ - nvkm_wo32(image, (i + 0), 0x10700ff9); - nvkm_wo32(image, (i + 4), 0x0436086c); - nvkm_wo32(image, (i + 8), 0x000c001b); + nvkm_wo32(chan->inst, (i + 0), 0x10700ff9); + nvkm_wo32(chan->inst, (i + 4), 0x0436086c); + nvkm_wo32(chan->inst, (i + 8), 0x000c001b); } - nvkm_wo32(image, 0x269c, 0x3f800000); - nvkm_wo32(image, 0x26b0, 0x3f800000); - nvkm_wo32(image, 0x26dc, 0x40000000); - nvkm_wo32(image, 0x26e0, 0x3f800000); - nvkm_wo32(image, 0x26e4, 0x3f000000); - nvkm_wo32(image, 0x26ec, 0x40000000); - nvkm_wo32(image, 0x26f0, 0x3f800000); - nvkm_wo32(image, 0x26f8, 0xbf800000); - nvkm_wo32(image, 0x2700, 0xbf800000); - nvkm_wo32(image, 0x3024, 0x000fe000); - nvkm_wo32(image, 0x30a0, 0x000003f8); - nvkm_wo32(image, 0x33fc, 0x002fe000); + nvkm_wo32(chan->inst, 0x269c, 0x3f800000); + nvkm_wo32(chan->inst, 0x26b0, 0x3f800000); + nvkm_wo32(chan->inst, 0x26dc, 0x40000000); + nvkm_wo32(chan->inst, 0x26e0, 0x3f800000); + nvkm_wo32(chan->inst, 0x26e4, 0x3f000000); + nvkm_wo32(chan->inst, 0x26ec, 0x40000000); + nvkm_wo32(chan->inst, 0x26f0, 0x3f800000); + nvkm_wo32(chan->inst, 0x26f8, 0xbf800000); + nvkm_wo32(chan->inst, 0x2700, 0xbf800000); + nvkm_wo32(chan->inst, 0x3024, 0x000fe000); + nvkm_wo32(chan->inst, 0x30a0, 0x000003f8); + nvkm_wo32(chan->inst, 0x33fc, 0x002fe000); for (i = 0x341c; i <= 0x3438; i += 4) - nvkm_wo32(image, i, 0x001c527c); - nvkm_done(image); + nvkm_wo32(chan->inst, i, 0x001c527c); + nvkm_done(chan->inst); return 0; } -static struct nvkm_oclass -nv2a_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x2a), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv2a_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct nvkm_gr_func +nv2a_gr = { + .chan_new = nv2a_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0597, &nv04_gr_object }, /* kelvin */ + {} + } +}; + static int nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -106,6 +126,8 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv2a_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -113,8 +135,6 @@ nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv2a_gr_cclass; - nv_engine(gr)->sclass = nv25_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 733de46a30dc..8f5bfe3aa487 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -6,127 +6,123 @@ #include /******************************************************************************* - * Graphics object classes + * PGRAPH context ******************************************************************************/ -static struct nvkm_oclass -nv30_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0397, &nv04_gr_ofuncs, NULL }, /* rankine */ - {}, +static const struct nvkm_object_func +nv30_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, }; -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - static int -nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { + struct nv20_gr *gr = nv20_gr(base); struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; int ret, i; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv30_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x5f48, 16, true, + &chan->inst); if (ret) return ret; - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x0410, 0x00000101); - nvkm_wo32(image, 0x0424, 0x00000111); - nvkm_wo32(image, 0x0428, 0x00000060); - nvkm_wo32(image, 0x0444, 0x00000080); - nvkm_wo32(image, 0x0448, 0xffff0000); - nvkm_wo32(image, 0x044c, 0x00000001); - nvkm_wo32(image, 0x0460, 0x44400000); - nvkm_wo32(image, 0x048c, 0xffff0000); + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x0410, 0x00000101); + nvkm_wo32(chan->inst, 0x0424, 0x00000111); + nvkm_wo32(chan->inst, 0x0428, 0x00000060); + nvkm_wo32(chan->inst, 0x0444, 0x00000080); + nvkm_wo32(chan->inst, 0x0448, 0xffff0000); + nvkm_wo32(chan->inst, 0x044c, 0x00000001); + nvkm_wo32(chan->inst, 0x0460, 0x44400000); + nvkm_wo32(chan->inst, 0x048c, 0xffff0000); for (i = 0x04e0; i < 0x04e8; i += 4) - nvkm_wo32(image, i, 0x0fff0000); - nvkm_wo32(image, 0x04ec, 0x00011100); + nvkm_wo32(chan->inst, i, 0x0fff0000); + nvkm_wo32(chan->inst, 0x04ec, 0x00011100); for (i = 0x0508; i < 0x0548; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x0550, 0x4b7fffff); - nvkm_wo32(image, 0x058c, 0x00000080); - nvkm_wo32(image, 0x0590, 0x30201000); - nvkm_wo32(image, 0x0594, 0x70605040); - nvkm_wo32(image, 0x0598, 0xb8a89888); - nvkm_wo32(image, 0x059c, 0xf8e8d8c8); - nvkm_wo32(image, 0x05b0, 0xb0000000); + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x0550, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x058c, 0x00000080); + nvkm_wo32(chan->inst, 0x0590, 0x30201000); + nvkm_wo32(chan->inst, 0x0594, 0x70605040); + nvkm_wo32(chan->inst, 0x0598, 0xb8a89888); + nvkm_wo32(chan->inst, 0x059c, 0xf8e8d8c8); + nvkm_wo32(chan->inst, 0x05b0, 0xb0000000); for (i = 0x0600; i < 0x0640; i += 4) - nvkm_wo32(image, i, 0x00010588); + nvkm_wo32(chan->inst, i, 0x00010588); for (i = 0x0640; i < 0x0680; i += 4) - nvkm_wo32(image, i, 0x00030303); + nvkm_wo32(chan->inst, i, 0x00030303); for (i = 0x06c0; i < 0x0700; i += 4) - nvkm_wo32(image, i, 0x0008aae4); + nvkm_wo32(chan->inst, i, 0x0008aae4); for (i = 0x0700; i < 0x0740; i += 4) - nvkm_wo32(image, i, 0x01012000); + nvkm_wo32(chan->inst, i, 0x01012000); for (i = 0x0740; i < 0x0780; i += 4) - nvkm_wo32(image, i, 0x00080008); - nvkm_wo32(image, 0x085c, 0x00040000); - nvkm_wo32(image, 0x0860, 0x00010000); + nvkm_wo32(chan->inst, i, 0x00080008); + nvkm_wo32(chan->inst, 0x085c, 0x00040000); + nvkm_wo32(chan->inst, 0x0860, 0x00010000); for (i = 0x0864; i < 0x0874; i += 4) - nvkm_wo32(image, i, 0x00040004); + nvkm_wo32(chan->inst, i, 0x00040004); for (i = 0x1f18; i <= 0x3088 ; i += 16) { - nvkm_wo32(image, i + 0, 0x10700ff9); - nvkm_wo32(image, i + 1, 0x0436086c); - nvkm_wo32(image, i + 2, 0x000c001b); + nvkm_wo32(chan->inst, i + 0, 0x10700ff9); + nvkm_wo32(chan->inst, i + 1, 0x0436086c); + nvkm_wo32(chan->inst, i + 2, 0x000c001b); } for (i = 0x30b8; i < 0x30c8; i += 4) - nvkm_wo32(image, i, 0x0000ffff); - nvkm_wo32(image, 0x344c, 0x3f800000); - nvkm_wo32(image, 0x3808, 0x3f800000); - nvkm_wo32(image, 0x381c, 0x3f800000); - nvkm_wo32(image, 0x3848, 0x40000000); - nvkm_wo32(image, 0x384c, 0x3f800000); - nvkm_wo32(image, 0x3850, 0x3f000000); - nvkm_wo32(image, 0x3858, 0x40000000); - nvkm_wo32(image, 0x385c, 0x3f800000); - nvkm_wo32(image, 0x3864, 0xbf800000); - nvkm_wo32(image, 0x386c, 0xbf800000); - nvkm_done(image); + nvkm_wo32(chan->inst, i, 0x0000ffff); + nvkm_wo32(chan->inst, 0x344c, 0x3f800000); + nvkm_wo32(chan->inst, 0x3808, 0x3f800000); + nvkm_wo32(chan->inst, 0x381c, 0x3f800000); + nvkm_wo32(chan->inst, 0x3848, 0x40000000); + nvkm_wo32(chan->inst, 0x384c, 0x3f800000); + nvkm_wo32(chan->inst, 0x3850, 0x3f000000); + nvkm_wo32(chan->inst, 0x3858, 0x40000000); + nvkm_wo32(chan->inst, 0x385c, 0x3f800000); + nvkm_wo32(chan->inst, 0x3864, 0xbf800000); + nvkm_wo32(chan->inst, 0x386c, 0xbf800000); + nvkm_done(chan->inst); return 0; } -static struct nvkm_oclass -nv30_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x30), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv30_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct nvkm_gr_func +nv30_gr = { + .chan_new = nv30_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ + { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ + { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ + { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ + { -1, -1, 0x0397, &nv04_gr_object }, /* rankine */ + {} + } +}; + static int nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -141,6 +137,8 @@ nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv30_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -148,8 +146,6 @@ nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv30_gr_cclass; - nv_engine(gr)->sclass = nv30_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 368c0cff35fb..3781a5b311fb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -5,127 +5,123 @@ #include /******************************************************************************* - * Graphics object classes + * PGRAPH context ******************************************************************************/ -static struct nvkm_oclass -nv34_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0697, &nv04_gr_ofuncs, NULL }, /* rankine */ - {}, +static const struct nvkm_object_func +nv34_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, }; -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - static int -nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { + struct nv20_gr *gr = nv20_gr(base); struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; int ret, i; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv34_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x46dc, 16, true, + &chan->inst); if (ret) return ret; - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x040c, 0x01000101); - nvkm_wo32(image, 0x0420, 0x00000111); - nvkm_wo32(image, 0x0424, 0x00000060); - nvkm_wo32(image, 0x0440, 0x00000080); - nvkm_wo32(image, 0x0444, 0xffff0000); - nvkm_wo32(image, 0x0448, 0x00000001); - nvkm_wo32(image, 0x045c, 0x44400000); - nvkm_wo32(image, 0x0480, 0xffff0000); + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x040c, 0x01000101); + nvkm_wo32(chan->inst, 0x0420, 0x00000111); + nvkm_wo32(chan->inst, 0x0424, 0x00000060); + nvkm_wo32(chan->inst, 0x0440, 0x00000080); + nvkm_wo32(chan->inst, 0x0444, 0xffff0000); + nvkm_wo32(chan->inst, 0x0448, 0x00000001); + nvkm_wo32(chan->inst, 0x045c, 0x44400000); + nvkm_wo32(chan->inst, 0x0480, 0xffff0000); for (i = 0x04d4; i < 0x04dc; i += 4) - nvkm_wo32(image, i, 0x0fff0000); - nvkm_wo32(image, 0x04e0, 0x00011100); + nvkm_wo32(chan->inst, i, 0x0fff0000); + nvkm_wo32(chan->inst, 0x04e0, 0x00011100); for (i = 0x04fc; i < 0x053c; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x0544, 0x4b7fffff); - nvkm_wo32(image, 0x057c, 0x00000080); - nvkm_wo32(image, 0x0580, 0x30201000); - nvkm_wo32(image, 0x0584, 0x70605040); - nvkm_wo32(image, 0x0588, 0xb8a89888); - nvkm_wo32(image, 0x058c, 0xf8e8d8c8); - nvkm_wo32(image, 0x05a0, 0xb0000000); + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x0544, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x057c, 0x00000080); + nvkm_wo32(chan->inst, 0x0580, 0x30201000); + nvkm_wo32(chan->inst, 0x0584, 0x70605040); + nvkm_wo32(chan->inst, 0x0588, 0xb8a89888); + nvkm_wo32(chan->inst, 0x058c, 0xf8e8d8c8); + nvkm_wo32(chan->inst, 0x05a0, 0xb0000000); for (i = 0x05f0; i < 0x0630; i += 4) - nvkm_wo32(image, i, 0x00010588); + nvkm_wo32(chan->inst, i, 0x00010588); for (i = 0x0630; i < 0x0670; i += 4) - nvkm_wo32(image, i, 0x00030303); + nvkm_wo32(chan->inst, i, 0x00030303); for (i = 0x06b0; i < 0x06f0; i += 4) - nvkm_wo32(image, i, 0x0008aae4); + nvkm_wo32(chan->inst, i, 0x0008aae4); for (i = 0x06f0; i < 0x0730; i += 4) - nvkm_wo32(image, i, 0x01012000); + nvkm_wo32(chan->inst, i, 0x01012000); for (i = 0x0730; i < 0x0770; i += 4) - nvkm_wo32(image, i, 0x00080008); - nvkm_wo32(image, 0x0850, 0x00040000); - nvkm_wo32(image, 0x0854, 0x00010000); + nvkm_wo32(chan->inst, i, 0x00080008); + nvkm_wo32(chan->inst, 0x0850, 0x00040000); + nvkm_wo32(chan->inst, 0x0854, 0x00010000); for (i = 0x0858; i < 0x0868; i += 4) - nvkm_wo32(image, i, 0x00040004); + nvkm_wo32(chan->inst, i, 0x00040004); for (i = 0x15ac; i <= 0x271c ; i += 16) { - nvkm_wo32(image, i + 0, 0x10700ff9); - nvkm_wo32(image, i + 1, 0x0436086c); - nvkm_wo32(image, i + 2, 0x000c001b); + nvkm_wo32(chan->inst, i + 0, 0x10700ff9); + nvkm_wo32(chan->inst, i + 1, 0x0436086c); + nvkm_wo32(chan->inst, i + 2, 0x000c001b); } for (i = 0x274c; i < 0x275c; i += 4) - nvkm_wo32(image, i, 0x0000ffff); - nvkm_wo32(image, 0x2ae0, 0x3f800000); - nvkm_wo32(image, 0x2e9c, 0x3f800000); - nvkm_wo32(image, 0x2eb0, 0x3f800000); - nvkm_wo32(image, 0x2edc, 0x40000000); - nvkm_wo32(image, 0x2ee0, 0x3f800000); - nvkm_wo32(image, 0x2ee4, 0x3f000000); - nvkm_wo32(image, 0x2eec, 0x40000000); - nvkm_wo32(image, 0x2ef0, 0x3f800000); - nvkm_wo32(image, 0x2ef8, 0xbf800000); - nvkm_wo32(image, 0x2f00, 0xbf800000); - nvkm_done(image); + nvkm_wo32(chan->inst, i, 0x0000ffff); + nvkm_wo32(chan->inst, 0x2ae0, 0x3f800000); + nvkm_wo32(chan->inst, 0x2e9c, 0x3f800000); + nvkm_wo32(chan->inst, 0x2eb0, 0x3f800000); + nvkm_wo32(chan->inst, 0x2edc, 0x40000000); + nvkm_wo32(chan->inst, 0x2ee0, 0x3f800000); + nvkm_wo32(chan->inst, 0x2ee4, 0x3f000000); + nvkm_wo32(chan->inst, 0x2eec, 0x40000000); + nvkm_wo32(chan->inst, 0x2ef0, 0x3f800000); + nvkm_wo32(chan->inst, 0x2ef8, 0xbf800000); + nvkm_wo32(chan->inst, 0x2f00, 0xbf800000); + nvkm_done(chan->inst); return 0; } -static struct nvkm_oclass -nv34_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x34), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv34_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct nvkm_gr_func +nv34_gr = { + .chan_new = nv34_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ + { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ + { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ + { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ + { -1, -1, 0x0697, &nv04_gr_object }, /* rankine */ + {} + } +}; + static int nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -140,6 +136,8 @@ nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv34_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -147,8 +145,6 @@ nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv34_gr_cclass; - nv_engine(gr)->sclass = nv34_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 676234d28e50..285c4eff2e5b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -5,127 +5,123 @@ #include /******************************************************************************* - * Graphics object classes + * PGRAPH context ******************************************************************************/ -static struct nvkm_oclass -nv35_gr_sclass[] = { - { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */ - { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */ - { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */ - { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */ - { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */ - { 0x0497, &nv04_gr_ofuncs, NULL }, /* rankine */ - {}, +static const struct nvkm_object_func +nv35_gr_chan = { + .dtor = nv20_gr_chan_dtor, + .init = nv20_gr_chan_init, + .fini = nv20_gr_chan_fini, }; -/******************************************************************************* - * PGRAPH context - ******************************************************************************/ - static int -nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { + struct nv20_gr *gr = nv20_gr(base); struct nv20_gr_chan *chan; - struct nvkm_gpuobj *image; int ret, i; - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv35_gr_chan, oclass, &chan->object); + chan->gr = gr; + chan->chid = fifoch->chid; + *pobject = &chan->object; + + ret = nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 0x577c, 16, true, + &chan->inst); if (ret) return ret; - chan->chid = nvkm_fifo_chan(parent)->chid; - image = &chan->base.base.gpuobj; - - nvkm_kmap(image); - nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24)); - nvkm_wo32(image, 0x040c, 0x00000101); - nvkm_wo32(image, 0x0420, 0x00000111); - nvkm_wo32(image, 0x0424, 0x00000060); - nvkm_wo32(image, 0x0440, 0x00000080); - nvkm_wo32(image, 0x0444, 0xffff0000); - nvkm_wo32(image, 0x0448, 0x00000001); - nvkm_wo32(image, 0x045c, 0x44400000); - nvkm_wo32(image, 0x0488, 0xffff0000); + nvkm_kmap(chan->inst); + nvkm_wo32(chan->inst, 0x0028, 0x00000001 | (chan->chid << 24)); + nvkm_wo32(chan->inst, 0x040c, 0x00000101); + nvkm_wo32(chan->inst, 0x0420, 0x00000111); + nvkm_wo32(chan->inst, 0x0424, 0x00000060); + nvkm_wo32(chan->inst, 0x0440, 0x00000080); + nvkm_wo32(chan->inst, 0x0444, 0xffff0000); + nvkm_wo32(chan->inst, 0x0448, 0x00000001); + nvkm_wo32(chan->inst, 0x045c, 0x44400000); + nvkm_wo32(chan->inst, 0x0488, 0xffff0000); for (i = 0x04dc; i < 0x04e4; i += 4) - nvkm_wo32(image, i, 0x0fff0000); - nvkm_wo32(image, 0x04e8, 0x00011100); + nvkm_wo32(chan->inst, i, 0x0fff0000); + nvkm_wo32(chan->inst, 0x04e8, 0x00011100); for (i = 0x0504; i < 0x0544; i += 4) - nvkm_wo32(image, i, 0x07ff0000); - nvkm_wo32(image, 0x054c, 0x4b7fffff); - nvkm_wo32(image, 0x0588, 0x00000080); - nvkm_wo32(image, 0x058c, 0x30201000); - nvkm_wo32(image, 0x0590, 0x70605040); - nvkm_wo32(image, 0x0594, 0xb8a89888); - nvkm_wo32(image, 0x0598, 0xf8e8d8c8); - nvkm_wo32(image, 0x05ac, 0xb0000000); + nvkm_wo32(chan->inst, i, 0x07ff0000); + nvkm_wo32(chan->inst, 0x054c, 0x4b7fffff); + nvkm_wo32(chan->inst, 0x0588, 0x00000080); + nvkm_wo32(chan->inst, 0x058c, 0x30201000); + nvkm_wo32(chan->inst, 0x0590, 0x70605040); + nvkm_wo32(chan->inst, 0x0594, 0xb8a89888); + nvkm_wo32(chan->inst, 0x0598, 0xf8e8d8c8); + nvkm_wo32(chan->inst, 0x05ac, 0xb0000000); for (i = 0x0604; i < 0x0644; i += 4) - nvkm_wo32(image, i, 0x00010588); + nvkm_wo32(chan->inst, i, 0x00010588); for (i = 0x0644; i < 0x0684; i += 4) - nvkm_wo32(image, i, 0x00030303); + nvkm_wo32(chan->inst, i, 0x00030303); for (i = 0x06c4; i < 0x0704; i += 4) - nvkm_wo32(image, i, 0x0008aae4); + nvkm_wo32(chan->inst, i, 0x0008aae4); for (i = 0x0704; i < 0x0744; i += 4) - nvkm_wo32(image, i, 0x01012000); + nvkm_wo32(chan->inst, i, 0x01012000); for (i = 0x0744; i < 0x0784; i += 4) - nvkm_wo32(image, i, 0x00080008); - nvkm_wo32(image, 0x0860, 0x00040000); - nvkm_wo32(image, 0x0864, 0x00010000); + nvkm_wo32(chan->inst, i, 0x00080008); + nvkm_wo32(chan->inst, 0x0860, 0x00040000); + nvkm_wo32(chan->inst, 0x0864, 0x00010000); for (i = 0x0868; i < 0x0878; i += 4) - nvkm_wo32(image, i, 0x00040004); + nvkm_wo32(chan->inst, i, 0x00040004); for (i = 0x1f1c; i <= 0x308c ; i += 16) { - nvkm_wo32(image, i + 0, 0x10700ff9); - nvkm_wo32(image, i + 4, 0x0436086c); - nvkm_wo32(image, i + 8, 0x000c001b); + nvkm_wo32(chan->inst, i + 0, 0x10700ff9); + nvkm_wo32(chan->inst, i + 4, 0x0436086c); + nvkm_wo32(chan->inst, i + 8, 0x000c001b); } for (i = 0x30bc; i < 0x30cc; i += 4) - nvkm_wo32(image, i, 0x0000ffff); - nvkm_wo32(image, 0x3450, 0x3f800000); - nvkm_wo32(image, 0x380c, 0x3f800000); - nvkm_wo32(image, 0x3820, 0x3f800000); - nvkm_wo32(image, 0x384c, 0x40000000); - nvkm_wo32(image, 0x3850, 0x3f800000); - nvkm_wo32(image, 0x3854, 0x3f000000); - nvkm_wo32(image, 0x385c, 0x40000000); - nvkm_wo32(image, 0x3860, 0x3f800000); - nvkm_wo32(image, 0x3868, 0xbf800000); - nvkm_wo32(image, 0x3870, 0xbf800000); - nvkm_done(image); + nvkm_wo32(chan->inst, i, 0x0000ffff); + nvkm_wo32(chan->inst, 0x3450, 0x3f800000); + nvkm_wo32(chan->inst, 0x380c, 0x3f800000); + nvkm_wo32(chan->inst, 0x3820, 0x3f800000); + nvkm_wo32(chan->inst, 0x384c, 0x40000000); + nvkm_wo32(chan->inst, 0x3850, 0x3f800000); + nvkm_wo32(chan->inst, 0x3854, 0x3f000000); + nvkm_wo32(chan->inst, 0x385c, 0x40000000); + nvkm_wo32(chan->inst, 0x3860, 0x3f800000); + nvkm_wo32(chan->inst, 0x3868, 0xbf800000); + nvkm_wo32(chan->inst, 0x3870, 0xbf800000); + nvkm_done(chan->inst); return 0; } -static struct nvkm_oclass -nv35_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x35), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv35_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = nv20_gr_context_init, - .fini = nv20_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ +static const struct nvkm_gr_func +nv35_gr = { + .chan_new = nv35_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ + { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ + { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ + { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ + { -1, -1, 0x0497, &nv04_gr_object }, /* rankine */ + {} + } +}; + static int nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -140,6 +136,8 @@ nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; + gr->base.func = &nv35_gr; + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, &gr->ctxtab); if (ret) @@ -147,8 +145,6 @@ nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->cclass = &nv35_gr_cclass; - nv_engine(gr)->sclass = nv35_gr_sclass; nv_engine(gr)->tile_prog = nv20_gr_tile_prog; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index e716ae12b55c..0103337f55d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -29,19 +29,6 @@ #include #include -struct nv40_gr { - struct nvkm_gr base; - u32 size; - struct list_head chan; -}; - -struct nv40_gr_chan { - struct nvkm_gr_chan base; - struct nvkm_fifo_chan *fifo; - u32 inst; - struct list_head head; -}; - static u64 nv40_gr_units(struct nvkm_gr *gr) { @@ -53,133 +40,61 @@ nv40_gr_units(struct nvkm_gr *gr) ******************************************************************************/ static int -nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, + int align, struct nvkm_gpuobj **pgpuobj) { - struct nvkm_gpuobj *obj; - int ret; - - ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, - 20, 16, 0, &obj); - *pobject = nv_object(obj); - if (ret) - return ret; - - nvkm_kmap(obj); - nvkm_wo32(obj, 0x00, nv_mclass(obj)); - nvkm_wo32(obj, 0x04, 0x00000000); - nvkm_wo32(obj, 0x08, 0x00000000); + int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align, + false, parent, pgpuobj); + if (ret == 0) { + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x04, 0x00000000); + nvkm_wo32(*pgpuobj, 0x08, 0x00000000); #ifdef __BIG_ENDIAN - nvkm_mo32(obj, 0x08, 0x01000000, 0x01000000); + nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000); #endif - nvkm_wo32(obj, 0x0c, 0x00000000); - nvkm_wo32(obj, 0x10, 0x00000000); - nvkm_done(obj); - return 0; + nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); + nvkm_wo32(*pgpuobj, 0x10, 0x00000000); + nvkm_done(*pgpuobj); + } + return ret; } -static struct nvkm_ofuncs -nv40_gr_ofuncs = { - .ctor = nv40_gr_object_ctor, - .dtor = _nvkm_gpuobj_dtor, - .init = _nvkm_gpuobj_init, - .fini = _nvkm_gpuobj_fini, - .rd32 = _nvkm_gpuobj_rd32, - .wr32 = _nvkm_gpuobj_wr32, -}; - -static struct nvkm_oclass -nv40_gr_sclass[] = { - { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */ - { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */ - { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */ - { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */ - { 0x4097, &nv40_gr_ofuncs, NULL }, /* curie */ - {}, -}; - -static struct nvkm_oclass -nv44_gr_sclass[] = { - { 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */ - { 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */ - { 0x0030, &nv40_gr_ofuncs, NULL }, /* null */ - { 0x0039, &nv40_gr_ofuncs, NULL }, /* m2mf */ - { 0x0043, &nv40_gr_ofuncs, NULL }, /* rop */ - { 0x0044, &nv40_gr_ofuncs, NULL }, /* patt */ - { 0x004a, &nv40_gr_ofuncs, NULL }, /* gdi */ - { 0x0062, &nv40_gr_ofuncs, NULL }, /* surf2d */ - { 0x0072, &nv40_gr_ofuncs, NULL }, /* beta4 */ - { 0x0089, &nv40_gr_ofuncs, NULL }, /* sifm */ - { 0x008a, &nv40_gr_ofuncs, NULL }, /* ifc */ - { 0x009f, &nv40_gr_ofuncs, NULL }, /* imageblit */ - { 0x3062, &nv40_gr_ofuncs, NULL }, /* surf2d (nv40) */ - { 0x3089, &nv40_gr_ofuncs, NULL }, /* sifm (nv40) */ - { 0x309e, &nv40_gr_ofuncs, NULL }, /* swzsurf (nv40) */ - { 0x4497, &nv40_gr_ofuncs, NULL }, /* curie */ - {}, +static const struct nvkm_object_func +nv40_gr_object = { + .bind = nv40_gr_object_bind, }; /******************************************************************************* * PGRAPH context ******************************************************************************/ -static void -nv40_gr_context_dtor(struct nvkm_object *object) -{ - struct nv40_gr_chan *chan = (void *)object; - unsigned long flags; - spin_lock_irqsave(&object->engine->lock, flags); - list_del(&chan->head); - spin_unlock_irqrestore(&object->engine->lock, flags); -} - static int -nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv40_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, + int align, struct nvkm_gpuobj **pgpuobj) { - struct nv40_gr *gr = (void *)engine; - struct nv40_gr_chan *chan; - unsigned long flags; - int ret; - - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size, - 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; - - nv40_grctx_fill(nv_device(gr), nv_gpuobj(chan)); - nvkm_wo32(&chan->base.base.gpuobj, 0x00000, nv_gpuobj(chan)->addr >> 4); - - spin_lock_irqsave(&gr->base.engine.lock, flags); - chan->fifo = (void *)parent; - chan->inst = chan->base.base.gpuobj.addr; - list_add(&chan->head, &gr->chan); - spin_unlock_irqrestore(&gr->base.engine.lock, flags); - return 0; + struct nv40_gr_chan *chan = nv40_gr_chan(object); + struct nv40_gr *gr = chan->gr; + int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, + align, true, parent, pgpuobj); + if (ret == 0) { + chan->inst = (*pgpuobj)->addr; + nvkm_kmap(*pgpuobj); + nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); + nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4); + nvkm_done(*pgpuobj); + } + return ret; } static int -nv40_gr_context_fini(struct nvkm_object *object, bool suspend) +nv40_gr_chan_fini(struct nvkm_object *object, bool suspend) { - struct nv40_gr *gr = (void *)object->engine; - struct nv40_gr_chan *chan = (void *)object; + struct nv40_gr_chan *chan = nv40_gr_chan(object); + struct nv40_gr *gr = chan->gr; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; - u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; + u32 inst = 0x01000000 | chan->inst >> 4; int ret = 0; nvkm_mask(device, 0x400720, 0x00000001, 0x00000000); @@ -210,19 +125,44 @@ nv40_gr_context_fini(struct nvkm_object *object, bool suspend) return ret; } -static struct nvkm_oclass -nv40_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x40), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv40_gr_context_ctor, - .dtor = nv40_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = nv40_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, +static void * +nv40_gr_chan_dtor(struct nvkm_object *object) +{ + struct nv40_gr_chan *chan = nv40_gr_chan(object); + unsigned long flags; + spin_lock_irqsave(&chan->gr->base.engine.lock, flags); + list_del(&chan->head); + spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); + return chan; +} + +static const struct nvkm_object_func +nv40_gr_chan = { + .dtor = nv40_gr_chan_dtor, + .fini = nv40_gr_chan_fini, + .bind = nv40_gr_chan_bind, }; +static int +nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) +{ + struct nv40_gr *gr = nv40_gr(base); + struct nv40_gr_chan *chan; + unsigned long flags; + + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv40_gr_chan, oclass, &chan->object); + chan->gr = gr; + *pobject = &chan->object; + + spin_lock_irqsave(&chan->gr->base.engine.lock, flags); + list_add(&chan->head, &gr->chan); + spin_unlock_irqrestore(&chan->gr->base.engine.lock, flags); + return 0; +} + /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ @@ -237,7 +177,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) unsigned long flags; fifo->pause(fifo, &flags); - nv04_gr_idle(gr); + nv04_gr_idle(&gr->base); switch (nv_device(gr)->chipset) { case 0x40: @@ -360,6 +300,54 @@ nv40_gr_intr(struct nvkm_subdev *subdev) spin_unlock_irqrestore(&gr->base.engine.lock, flags); } +static const struct nvkm_gr_func +nv40_gr = { + .chan_new = nv40_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv40_gr_object }, /* null */ + { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ + { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ + { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ + { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ + { -1, -1, 0x4097, &nv40_gr_object }, /* curie */ + {} + } +}; + +static const struct nvkm_gr_func +nv44_gr = { + .chan_new = nv40_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv40_gr_object }, /* null */ + { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ + { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ + { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ + { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ + { -1, -1, 0x4497, &nv40_gr_object }, /* curie */ + {} + } +}; + static int nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -377,11 +365,10 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv40_gr_intr; - nv_engine(gr)->cclass = &nv40_gr_cclass; if (nv44_gr_class(gr)) - nv_engine(gr)->sclass = nv44_gr_sclass; + gr->base.func = &nv44_gr; else - nv_engine(gr)->sclass = nv40_gr_sclass; + gr->base.func = &nv40_gr; nv_engine(gr)->tile_prog = nv40_gr_tile_prog; gr->base.units = nv40_gr_units; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index 01d9f73a024c..eefb36cbeeea 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -1,8 +1,23 @@ #ifndef __NV40_GR_H__ #define __NV40_GR_H__ -#include +#define nv40_gr(p) container_of((p), struct nv40_gr, base) +#include "priv.h" -struct nvkm_gpuobj; +struct nv40_gr { + struct nvkm_gr base; + u32 size; + struct list_head chan; +}; + +#define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object) + +struct nv40_gr_chan { + struct nvkm_object object; + struct nv40_gr *gr; + struct nvkm_fifo_chan *fifo; + u32 inst; + struct list_head head; +}; /* returns 1 if device is one of the nv4x using the 0x4497 object class, * helpful to determine a number of other hardware features diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 5f22dd3c788c..403d2c9aff3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -27,16 +27,6 @@ #include #include -struct nv50_gr { - struct nvkm_gr base; - spinlock_t lock; - u32 size; -}; - -struct nv50_gr_chan { - struct nvkm_gr_chan base; -}; - static u64 nv50_gr_units(struct nvkm_gr *gr) { @@ -48,126 +38,82 @@ nv50_gr_units(struct nvkm_gr *gr) ******************************************************************************/ static int -nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv50_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, + int align, struct nvkm_gpuobj **pgpuobj) { - struct nvkm_gpuobj *obj; - int ret; - - ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, - 16, 16, 0, &obj); - *pobject = nv_object(obj); - if (ret) - return ret; - - nvkm_kmap(obj); - nvkm_wo32(obj, 0x00, nv_mclass(obj)); - nvkm_wo32(obj, 0x04, 0x00000000); - nvkm_wo32(obj, 0x08, 0x00000000); - nvkm_wo32(obj, 0x0c, 0x00000000); - nvkm_done(obj); - return 0; + int ret = nvkm_gpuobj_new(object->engine->subdev.device, 16, + align, false, parent, pgpuobj); + if (ret == 0) { + nvkm_kmap(*pgpuobj); + nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x04, 0x00000000); + nvkm_wo32(*pgpuobj, 0x08, 0x00000000); + nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); + nvkm_done(*pgpuobj); + } + return ret; } -static struct nvkm_ofuncs -nv50_gr_ofuncs = { - .ctor = nv50_gr_object_ctor, - .dtor = _nvkm_gpuobj_dtor, - .init = _nvkm_gpuobj_init, - .fini = _nvkm_gpuobj_fini, - .rd32 = _nvkm_gpuobj_rd32, - .wr32 = _nvkm_gpuobj_wr32, -}; - -static struct nvkm_oclass -nv50_gr_sclass[] = { - { 0x0030, &nv50_gr_ofuncs }, - { 0x502d, &nv50_gr_ofuncs }, - { 0x5039, &nv50_gr_ofuncs }, - { 0x5097, &nv50_gr_ofuncs }, - { 0x50c0, &nv50_gr_ofuncs }, - {} +static const struct nvkm_object_func +nv50_gr_object = { + .bind = nv50_gr_object_bind, }; -static struct nvkm_oclass -g84_gr_sclass[] = { - { 0x0030, &nv50_gr_ofuncs }, - { 0x502d, &nv50_gr_ofuncs }, - { 0x5039, &nv50_gr_ofuncs }, - { 0x50c0, &nv50_gr_ofuncs }, - { 0x8297, &nv50_gr_ofuncs }, - {} -}; - -static struct nvkm_oclass -gt200_gr_sclass[] = { - { 0x0030, &nv50_gr_ofuncs }, - { 0x502d, &nv50_gr_ofuncs }, - { 0x5039, &nv50_gr_ofuncs }, - { 0x50c0, &nv50_gr_ofuncs }, - { 0x8397, &nv50_gr_ofuncs }, - {} -}; +static int +nv50_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) +{ + struct nv50_gr *gr = nv50_gr(base); + int c = 0; -static struct nvkm_oclass -gt215_gr_sclass[] = { - { 0x0030, &nv50_gr_ofuncs }, - { 0x502d, &nv50_gr_ofuncs }, - { 0x5039, &nv50_gr_ofuncs }, - { 0x50c0, &nv50_gr_ofuncs }, - { 0x8597, &nv50_gr_ofuncs }, - { 0x85c0, &nv50_gr_ofuncs }, - {} -}; + while (gr->func->sclass[c].oclass) { + if (c++ == index) { + *sclass = gr->func->sclass[index]; + return index; + } + } -static struct nvkm_oclass -mcp89_gr_sclass[] = { - { 0x0030, &nv50_gr_ofuncs }, - { 0x502d, &nv50_gr_ofuncs }, - { 0x5039, &nv50_gr_ofuncs }, - { 0x50c0, &nv50_gr_ofuncs }, - { 0x85c0, &nv50_gr_ofuncs }, - { 0x8697, &nv50_gr_ofuncs }, - {} -}; + return c; +} /******************************************************************************* * PGRAPH context ******************************************************************************/ static int -nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv50_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, + int align, struct nvkm_gpuobj **pgpuobj) { - struct nv50_gr *gr = (void *)engine; - struct nv50_gr_chan *chan; - int ret; + struct nv50_gr *gr = nv50_gr_chan(object)->gr; + int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size, + align, true, parent, pgpuobj); + if (ret == 0) { + nvkm_kmap(*pgpuobj); + nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); + nvkm_done(*pgpuobj); + } + return ret; +} - ret = nvkm_gr_context_create(parent, engine, oclass, NULL, gr->size, - 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); - *pobject = nv_object(chan); - if (ret) - return ret; +static const struct nvkm_object_func +nv50_gr_chan = { + .bind = nv50_gr_chan_bind, +}; + +static int +nv50_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, + const struct nvkm_oclass *oclass, struct nvkm_object **pobject) +{ + struct nv50_gr *gr = nv50_gr(base); + struct nv50_gr_chan *chan; - nv50_grctx_fill(nv_device(gr), nv_gpuobj(chan)); + if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL))) + return -ENOMEM; + nvkm_object_ctor(&nv50_gr_chan, oclass, &chan->object); + chan->gr = gr; + *pobject = &chan->object; return 0; } -static struct nvkm_oclass -nv50_gr_cclass = { - .handle = NV_ENGCTX(GR, 0x50), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_gr_context_ctor, - .dtor = _nvkm_gr_context_dtor, - .init = _nvkm_gr_context_init, - .fini = _nvkm_gr_context_fini, - .rd32 = _nvkm_gr_context_rd32, - .wr32 = _nvkm_gr_context_wr32, - }, -}; - /******************************************************************************* * PGRAPH engine/subdev functions ******************************************************************************/ @@ -889,6 +835,74 @@ nv50_gr_intr(struct nvkm_subdev *subdev) nvkm_fifo_chan_put(device->fifo, flags, &chan); } +static const struct nv50_gr_func +nv50_gr = { + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x5097, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + {} + } +}; + +static const struct nv50_gr_func +g84_gr = { + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8297, &nv50_gr_object }, + {} + } +}; + +static const struct nv50_gr_func +gt200_gr = { + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8397, &nv50_gr_object }, + {} + } +}; + +static const struct nv50_gr_func +gt215_gr = { + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8597, &nv50_gr_object }, + { -1, -1, 0x85c0, &nv50_gr_object }, + {} + } +}; + +static const struct nv50_gr_func +mcp89_gr = { + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x85c0, &nv50_gr_object }, + { -1, -1, 0x8697, &nv50_gr_object }, + {} + } +}; + +static const struct nvkm_gr_func +nv50_gr_ = { + .chan_new = nv50_gr_chan_new, + .object_get = nv50_gr_object_get, +}; + static int nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, @@ -904,13 +918,13 @@ nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00201000; nv_subdev(gr)->intr = nv50_gr_intr; - nv_engine(gr)->cclass = &nv50_gr_cclass; + gr->base.func = &nv50_gr_; gr->base.units = nv50_gr_units; switch (nv_device(gr)->chipset) { case 0x50: - nv_engine(gr)->sclass = nv50_gr_sclass; + gr->func = &nv50_gr; break; case 0x84: case 0x86: @@ -918,22 +932,21 @@ nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, case 0x94: case 0x96: case 0x98: - nv_engine(gr)->sclass = g84_gr_sclass; + gr->func = &g84_gr; break; case 0xa0: case 0xaa: case 0xac: - nv_engine(gr)->sclass = gt200_gr_sclass; + gr->func = >200_gr; break; case 0xa3: case 0xa5: case 0xa8: - nv_engine(gr)->sclass = gt215_gr_sclass; + gr->func = >215_gr; break; case 0xaf: - nv_engine(gr)->sclass = mcp89_gr_sclass; + gr->func = &mcp89_gr; break; - } /* unfortunate hw bug workaround... */ diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h index bcf786f6b731..145ea5026a8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -1,8 +1,26 @@ #ifndef __NV50_GR_H__ #define __NV50_GR_H__ -#include -struct nvkm_device; -struct nvkm_gpuobj; +#define nv50_gr(p) container_of((p), struct nv50_gr, base) +#include "priv.h" + +struct nv50_gr { + struct nvkm_gr base; + const struct nv50_gr_func *func; + spinlock_t lock; + u32 size; +}; + +struct nv50_gr_func { + void *(*dtor)(struct nv50_gr *); + struct nvkm_sclass sclass[]; +}; + +#define nv50_gr_chan(p) container_of((p), struct nv50_gr_chan, object) + +struct nv50_gr_chan { + struct nvkm_object object; + struct nv50_gr *gr; +}; int nv50_grctx_init(struct nvkm_device *, u32 *size); void nv50_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h new file mode 100644 index 000000000000..f7fd617b6fe5 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -0,0 +1,15 @@ +#ifndef __NVKM_GR_PRIV_H__ +#define __NVKM_GR_PRIV_H__ +#define nvkm_gr(p) container_of((p), struct nvkm_gr, engine) +#include +struct nvkm_fifo_chan; + +struct nvkm_gr_func { + int (*chan_new)(struct nvkm_gr *, struct nvkm_fifo_chan *, + const struct nvkm_oclass *, struct nvkm_object **); + int (*object_get)(struct nvkm_gr *, int, struct nvkm_sclass *); + struct nvkm_sclass sclass[]; +}; + +extern const struct nvkm_object_func nv04_gr_object; +#endif -- cgit v1.2.3 From 03c8952fb36b58e451b8a93a1a2abd59e09ddf7b Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:20 +1000 Subject: drm/nouveau/fb: convert to new-style nvkm_subdev Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 2 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h | 74 +++++------ drivers/gpu/drm/nouveau/nouveau_bo.c | 12 +- drivers/gpu/drm/nouveau/nouveau_gem.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 138 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 --- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c | 134 +++++++++++++------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 68 +++++----- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c | 24 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c | 48 ++----- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c | 24 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c | 54 ++------ drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h | 49 -------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c | 25 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c | 25 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c | 27 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c | 25 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 47 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c | 41 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c | 41 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c | 38 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c | 26 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 127 ++++++++++--------- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h | 14 +-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h | 77 ++++++++---- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h | 9 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 5 +- 47 files changed, 648 insertions(+), 812 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 230ee81f3f60..2b17b13b9dba 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -51,7 +51,7 @@ u64 nvif_device_time(struct nvif_device *); nv_device(_device->object.priv); \ }) #define nvxx_bios(a) nvxx_device(a)->bios -#define nvxx_fb(a) nvkm_fb(nvxx_device(a)) +#define nvxx_fb(a) nvxx_device(a)->fb #define nvxx_mmu(a) nvkm_mmu(nvxx_device(a)) #define nvxx_bar(a) nvxx_device(a)->bar #define nvxx_gpio(a) nvkm_gpio(nvxx_device(a)) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index f102cf97bb93..85ab72c7f821 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -46,59 +46,47 @@ struct nvkm_fb_tile { }; struct nvkm_fb { + const struct nvkm_fb_func *func; struct nvkm_subdev subdev; - bool (*memtype_valid)(struct nvkm_fb *, u32 memtype); - struct nvkm_ram *ram; struct { struct nvkm_fb_tile region[16]; int regions; - void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nvkm_fb_tile *); - void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, - struct nvkm_fb_tile *); - void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); - void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); } tile; }; -static inline struct nvkm_fb * -nvkm_fb(void *obj) -{ - /* fbram uses this before device subdev pointer is valid */ - if (nv_iclass(obj, NV_SUBDEV_CLASS) && - nv_subidx(obj) == NVDEV_SUBDEV_FB) - return obj; - - return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB); -} - -extern struct nvkm_oclass *nv04_fb_oclass; -extern struct nvkm_oclass *nv10_fb_oclass; -extern struct nvkm_oclass *nv1a_fb_oclass; -extern struct nvkm_oclass *nv20_fb_oclass; -extern struct nvkm_oclass *nv25_fb_oclass; -extern struct nvkm_oclass *nv30_fb_oclass; -extern struct nvkm_oclass *nv35_fb_oclass; -extern struct nvkm_oclass *nv36_fb_oclass; -extern struct nvkm_oclass *nv40_fb_oclass; -extern struct nvkm_oclass *nv41_fb_oclass; -extern struct nvkm_oclass *nv44_fb_oclass; -extern struct nvkm_oclass *nv46_fb_oclass; -extern struct nvkm_oclass *nv47_fb_oclass; -extern struct nvkm_oclass *nv49_fb_oclass; -extern struct nvkm_oclass *nv4e_fb_oclass; -extern struct nvkm_oclass *nv50_fb_oclass; -extern struct nvkm_oclass *g84_fb_oclass; -extern struct nvkm_oclass *gt215_fb_oclass; -extern struct nvkm_oclass *mcp77_fb_oclass; -extern struct nvkm_oclass *mcp89_fb_oclass; -extern struct nvkm_oclass *gf100_fb_oclass; -extern struct nvkm_oclass *gk104_fb_oclass; -extern struct nvkm_oclass *gk20a_fb_oclass; -extern struct nvkm_oclass *gm107_fb_oclass; +bool nvkm_fb_memtype_valid(struct nvkm_fb *, u32 memtype); +void nvkm_fb_tile_init(struct nvkm_fb *, int region, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nvkm_fb_tile_fini(struct nvkm_fb *, int region, struct nvkm_fb_tile *); +void nvkm_fb_tile_prog(struct nvkm_fb *, int region, struct nvkm_fb_tile *); + +int nv04_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv10_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv1a_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv20_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv25_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv30_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv35_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv36_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv40_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv41_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv44_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv46_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv47_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv49_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv4e_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int nv50_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int g84_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int gt215_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int mcp77_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int mcp89_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int gf100_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int gk104_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int gk20a_fb_new(struct nvkm_device *, int, struct nvkm_fb **); +int gm107_fb_new(struct nvkm_device *, int, struct nvkm_fb **); #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 79d2ba167fba..140a1eb9c49e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -50,22 +50,16 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, int i = reg - drm->tile.reg; struct nvkm_fb *fb = nvxx_fb(&drm->device); struct nvkm_fb_tile *tile = &fb->tile.region[i]; - struct nvkm_engine *engine; nouveau_fence_unref(®->fence); if (tile->pitch) - fb->tile.fini(fb, i, tile); + nvkm_fb_tile_fini(fb, i, tile); if (pitch) - fb->tile.init(fb, i, addr, size, pitch, flags, tile); + nvkm_fb_tile_init(fb, i, addr, size, pitch, flags, tile); - fb->tile.prog(fb, i, tile); - - if ((engine = nvkm_engine(fb, NVDEV_ENGINE_GR))) - engine->tile_prog(engine, i); - if ((engine = nvkm_engine(fb, NVDEV_ENGINE_MPEG))) - engine->tile_prog(engine, i); + nvkm_fb_tile_prog(fb, i, tile); } static struct nouveau_drm_tile * diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index dc2378c01b6d..2c9981512d27 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -259,7 +259,7 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data, struct nouveau_bo *nvbo = NULL; int ret = 0; - if (!fb->memtype_valid(fb, req->info.tile_flags)) { + if (!nvkm_fb_memtype_valid(fb, req->info.tile_flags)) { NV_PRINTK(err, cli, "bad page flags: 0x%08x\n", req->info.tile_flags); return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 7bd8c39649d4..b34c22ff8803 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -80,7 +80,7 @@ nv4_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv04_devinit_new, -// .fb = nv04_fb_new, + .fb = nv04_fb_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, // .mc = nv04_mc_new, @@ -100,7 +100,7 @@ nv5_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv05_devinit_new, -// .fb = nv04_fb_new, + .fb = nv04_fb_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, // .mc = nv04_mc_new, @@ -120,7 +120,7 @@ nv10_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv10_devinit_new, -// .fb = nv10_fb_new, + .fb = nv10_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -139,7 +139,7 @@ nv11_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv10_devinit_new, -// .fb = nv10_fb_new, + .fb = nv10_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -160,7 +160,7 @@ nv15_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv10_devinit_new, -// .fb = nv10_fb_new, + .fb = nv10_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -181,7 +181,7 @@ nv17_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv10_devinit_new, -// .fb = nv10_fb_new, + .fb = nv10_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -202,7 +202,7 @@ nv18_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv10_devinit_new, -// .fb = nv10_fb_new, + .fb = nv10_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -223,7 +223,7 @@ nv1a_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv1a_fb_new, + .fb = nv1a_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -244,7 +244,7 @@ nv1f_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv1a_fb_new, + .fb = nv1a_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -265,7 +265,7 @@ nv20_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv20_fb_new, + .fb = nv20_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -286,7 +286,7 @@ nv25_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv25_fb_new, + .fb = nv25_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -307,7 +307,7 @@ nv28_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv25_fb_new, + .fb = nv25_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -328,7 +328,7 @@ nv2a_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv25_fb_new, + .fb = nv25_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -349,7 +349,7 @@ nv30_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv30_fb_new, + .fb = nv30_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -370,7 +370,7 @@ nv31_chipset = { .bus = nv31_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv30_fb_new, + .fb = nv30_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -392,7 +392,7 @@ nv34_chipset = { .bus = nv31_bus_new, .clk = nv04_clk_new, .devinit = nv10_devinit_new, -// .fb = nv10_fb_new, + .fb = nv10_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -414,7 +414,7 @@ nv35_chipset = { .bus = nv04_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv35_fb_new, + .fb = nv35_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -435,7 +435,7 @@ nv36_chipset = { .bus = nv31_bus_new, .clk = nv04_clk_new, .devinit = nv20_devinit_new, -// .fb = nv36_fb_new, + .fb = nv36_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv04_instmem_new, @@ -457,7 +457,7 @@ nv40_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv40_fb_new, + .fb = nv40_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -482,7 +482,7 @@ nv41_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv41_fb_new, + .fb = nv41_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -507,7 +507,7 @@ nv42_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv41_fb_new, + .fb = nv41_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -532,7 +532,7 @@ nv43_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv41_fb_new, + .fb = nv41_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -557,7 +557,7 @@ nv44_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv44_fb_new, + .fb = nv44_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -582,7 +582,7 @@ nv45_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv40_fb_new, + .fb = nv40_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -607,7 +607,7 @@ nv46_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv46_fb_new, + .fb = nv46_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -632,7 +632,7 @@ nv47_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv47_fb_new, + .fb = nv47_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -657,7 +657,7 @@ nv49_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv49_fb_new, + .fb = nv49_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -682,7 +682,7 @@ nv4a_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv44_fb_new, + .fb = nv44_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -707,7 +707,7 @@ nv4b_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv49_fb_new, + .fb = nv49_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -732,7 +732,7 @@ nv4c_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv46_fb_new, + .fb = nv46_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -757,7 +757,7 @@ nv4e_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv4e_fb_new, + .fb = nv4e_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv4e_i2c_new, // .imem = nv40_instmem_new, @@ -783,7 +783,7 @@ nv50_chipset = { .bus = nv50_bus_new, .clk = nv50_clk_new, .devinit = nv50_devinit_new, -// .fb = nv50_fb_new, + .fb = nv50_fb_new, // .fuse = nv50_fuse_new, // .gpio = nv50_gpio_new, // .i2c = nv50_i2c_new, @@ -810,7 +810,7 @@ nv63_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv46_fb_new, + .fb = nv46_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -835,7 +835,7 @@ nv67_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv46_fb_new, + .fb = nv46_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -860,7 +860,7 @@ nv68_chipset = { .bus = nv31_bus_new, .clk = nv40_clk_new, .devinit = nv1a_devinit_new, -// .fb = nv46_fb_new, + .fb = nv46_fb_new, // .gpio = nv10_gpio_new, // .i2c = nv04_i2c_new, // .imem = nv40_instmem_new, @@ -886,7 +886,7 @@ nv84_chipset = { .bus = nv50_bus_new, .clk = g84_clk_new, .devinit = g84_devinit_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .fuse = nv50_fuse_new, // .gpio = nv50_gpio_new, // .i2c = nv50_i2c_new, @@ -917,7 +917,7 @@ nv86_chipset = { .bus = nv50_bus_new, .clk = g84_clk_new, .devinit = g84_devinit_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .fuse = nv50_fuse_new, // .gpio = nv50_gpio_new, // .i2c = nv50_i2c_new, @@ -948,7 +948,7 @@ nv92_chipset = { .bus = nv50_bus_new, .clk = g84_clk_new, .devinit = g84_devinit_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .fuse = nv50_fuse_new, // .gpio = nv50_gpio_new, // .i2c = nv50_i2c_new, @@ -979,7 +979,7 @@ nv94_chipset = { .bus = g94_bus_new, .clk = g84_clk_new, .devinit = g84_devinit_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1016,7 +1016,7 @@ nv96_chipset = { // .mc = g94_mc_new, .bus = g94_bus_new, // .timer = nv04_timer_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .imem = nv50_instmem_new, // .mmu = nv50_mmu_new, .bar = g84_bar_new, @@ -1047,7 +1047,7 @@ nv98_chipset = { // .mc = g98_mc_new, .bus = g94_bus_new, // .timer = nv04_timer_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .imem = nv50_instmem_new, // .mmu = nv50_mmu_new, .bar = g84_bar_new, @@ -1072,7 +1072,7 @@ nva0_chipset = { .bus = g94_bus_new, .clk = g84_clk_new, .devinit = g84_devinit_new, -// .fb = g84_fb_new, + .fb = g84_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = nv50_i2c_new, @@ -1103,7 +1103,7 @@ nva3_chipset = { .bus = g94_bus_new, .clk = gt215_clk_new, .devinit = gt215_devinit_new, -// .fb = gt215_fb_new, + .fb = gt215_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1136,7 +1136,7 @@ nva5_chipset = { .bus = g94_bus_new, .clk = gt215_clk_new, .devinit = gt215_devinit_new, -// .fb = gt215_fb_new, + .fb = gt215_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1168,7 +1168,7 @@ nva8_chipset = { .bus = g94_bus_new, .clk = gt215_clk_new, .devinit = gt215_devinit_new, -// .fb = gt215_fb_new, + .fb = gt215_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1200,7 +1200,7 @@ nvaa_chipset = { .bus = g94_bus_new, .clk = mcp77_clk_new, .devinit = g98_devinit_new, -// .fb = mcp77_fb_new, + .fb = mcp77_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1231,7 +1231,7 @@ nvac_chipset = { .bus = g94_bus_new, .clk = mcp77_clk_new, .devinit = g98_devinit_new, -// .fb = mcp77_fb_new, + .fb = mcp77_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1262,7 +1262,7 @@ nvaf_chipset = { .bus = g94_bus_new, .clk = gt215_clk_new, .devinit = mcp89_devinit_new, -// .fb = mcp89_fb_new, + .fb = mcp89_fb_new, // .fuse = nv50_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1294,7 +1294,7 @@ nvc0_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1329,7 +1329,7 @@ nvc1_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1363,7 +1363,7 @@ nvc3_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1397,7 +1397,7 @@ nvc4_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1432,7 +1432,7 @@ nvc8_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1467,7 +1467,7 @@ nvce_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1502,7 +1502,7 @@ nvcf_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = g94_gpio_new, // .i2c = g94_i2c_new, @@ -1536,7 +1536,7 @@ nvd7_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = gf110_gpio_new, // .i2c = gf117_i2c_new, @@ -1568,7 +1568,7 @@ nvd9_chipset = { .bus = gf100_bus_new, .clk = gf100_clk_new, .devinit = gf100_devinit_new, -// .fb = gf100_fb_new, + .fb = gf100_fb_new, // .fuse = gf100_fuse_new, // .gpio = gf110_gpio_new, // .i2c = gf110_i2c_new, @@ -1602,7 +1602,7 @@ nve4_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gk104_i2c_new, @@ -1638,7 +1638,7 @@ nve6_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gk104_i2c_new, @@ -1674,7 +1674,7 @@ nve7_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gk104_i2c_new, @@ -1708,7 +1708,7 @@ nvea_chipset = { .bar = gk20a_bar_new, .bus = gf100_bus_new, .clk = gk20a_clk_new, -// .fb = gk20a_fb_new, + .fb = gk20a_fb_new, // .fuse = gf100_fuse_new, // .ibus = gk20a_ibus_new, // .imem = gk20a_instmem_new, @@ -1734,7 +1734,7 @@ nvf0_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gk104_i2c_new, @@ -1770,7 +1770,7 @@ nvf1_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gf110_i2c_new, @@ -1806,7 +1806,7 @@ nv106_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gk104_i2c_new, @@ -1841,7 +1841,7 @@ nv108_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gf100_devinit_new, -// .fb = gk104_fb_new, + .fb = gk104_fb_new, // .fuse = gf100_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gk104_i2c_new, @@ -1876,7 +1876,7 @@ nv117_chipset = { .bus = gf100_bus_new, .clk = gk104_clk_new, .devinit = gm107_devinit_new, -// .fb = gm107_fb_new, + .fb = gm107_fb_new, // .fuse = gm107_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gf110_i2c_new, @@ -1905,7 +1905,7 @@ nv124_chipset = { .bios = nvkm_bios_new, .bus = gf100_bus_new, .devinit = gm204_devinit_new, -// .fb = gm107_fb_new, + .fb = gm107_fb_new, // .fuse = gm107_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gm204_i2c_new, @@ -1934,7 +1934,7 @@ nv126_chipset = { .bios = nvkm_bios_new, .bus = gf100_bus_new, .devinit = gm204_devinit_new, -// .fb = gm107_fb_new, + .fb = gm107_fb_new, // .fuse = gm107_fuse_new, // .gpio = gk104_gpio_new, // .i2c = gm204_i2c_new, @@ -1961,7 +1961,7 @@ nv12b_chipset = { .name = "GM20B", .bar = gk20a_bar_new, .bus = gf100_bus_new, -// .fb = gk20a_fb_new, + .fb = gk20a_fb_new, // .fuse = gm107_fuse_new, // .ibus = gk20a_ibus_new, // .imem = gk20a_instmem_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index 87a9cdb42bd6..dbc9f52f9e59 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -35,7 +35,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -62,7 +61,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -89,7 +87,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -115,7 +112,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -142,7 +138,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -168,7 +163,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -194,7 +188,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -221,7 +214,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -247,7 +239,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 67c7b6386a4c..af4368784ac9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -35,7 +35,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -63,7 +62,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -91,7 +89,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -115,7 +112,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; @@ -137,7 +133,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -165,7 +160,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -193,7 +187,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -220,7 +213,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index f9f0663f2206..6723b9eba100 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -35,7 +35,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -73,7 +72,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -108,7 +106,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -137,7 +134,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 0cabcfa8b63e..d65d2943d776 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -31,7 +31,6 @@ nv04_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -44,7 +43,6 @@ nv04_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 09eedfecfb36..dd42f9e64f76 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -32,7 +32,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -44,7 +43,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -58,7 +56,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -72,7 +69,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -86,7 +82,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -100,7 +95,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -114,7 +108,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -128,7 +121,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index 9ea12b6426c6..3e79a02ac687 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -32,7 +32,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -46,7 +45,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -60,7 +58,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -74,7 +71,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 48b927bd104b..b045515a4903 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -32,7 +32,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -46,7 +45,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -60,7 +58,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -75,7 +72,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -90,7 +86,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index ef660d958f6b..430707755ffa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -33,7 +33,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -51,7 +50,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -69,7 +67,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -87,7 +84,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -105,7 +101,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -123,7 +118,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -141,7 +135,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -159,7 +152,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -177,7 +169,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -195,7 +186,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -213,7 +203,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -231,7 +220,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -249,7 +237,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -267,7 +254,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -285,7 +271,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -303,7 +288,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 7b942dfa7f4c..3b22a2e3459e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -35,7 +35,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -55,7 +54,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -78,7 +76,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -101,7 +98,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -124,7 +120,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -147,7 +142,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -170,7 +164,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -193,7 +186,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -216,7 +208,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -239,7 +230,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -262,7 +252,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; @@ -287,7 +276,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; @@ -311,7 +299,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; @@ -335,7 +322,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index 27fa96b222e3..1e13278cf306 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -569,7 +569,7 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx) else if (device->chipset < 0xa0) gr_def(ctx, 0x407d08, 0x00390040); else { - if (nvkm_fb(device)->ram->type != NVKM_RAM_TYPE_GDDR5) + if (device->fb->ram->type != NVKM_RAM_TYPE_GDDR5) gr_def(ctx, 0x407d08, 0x003d0040); else gr_def(ctx, 0x407d08, 0x003c0040); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index d435bd155684..0f39ff883ec0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -26,6 +26,38 @@ #include #include +#include +#include + +bool +nvkm_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype) +{ + return fb->func->memtype_valid(fb, memtype); +} + +void +nvkm_fb_tile_fini(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) +{ + fb->func->tile.fini(fb, region, tile); +} + +void +nvkm_fb_tile_init(struct nvkm_fb *fb, int region, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *tile) +{ + fb->func->tile.init(fb, region, addr, size, pitch, flags, tile); +} + +void +nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) +{ + struct nvkm_device *device = fb->subdev.device; + fb->func->tile.prog(fb, region, tile); + if (likely(device->gr)) + device->gr->engine.tile_prog(&device->gr->engine, region); + if (likely(device->mpeg)) + device->mpeg->tile_prog(device->mpeg, region); +} int nvkm_fb_bios_memtype(struct nvkm_bios *bios) @@ -52,69 +84,87 @@ nvkm_fb_bios_memtype(struct nvkm_bios *bios) return NVKM_RAM_TYPE_UNKNOWN; } -int -_nvkm_fb_fini(struct nvkm_object *object, bool suspend) +static void +nvkm_fb_intr(struct nvkm_subdev *subdev) { - struct nvkm_fb *fb = (void *)object; - return nvkm_subdev_fini_old(&fb->subdev, suspend); + struct nvkm_fb *fb = nvkm_fb(subdev); + if (fb->func->intr) + fb->func->intr(fb); } -int -_nvkm_fb_init(struct nvkm_object *object) +static int +nvkm_fb_oneinit(struct nvkm_subdev *subdev) { - struct nvkm_fb *fb = (void *)object; - int ret, i; + struct nvkm_fb *fb = nvkm_fb(subdev); + if (fb->func->ram_new) { + int ret = fb->func->ram_new(fb, &fb->ram); + if (ret) { + nvkm_error(subdev, "vram setup failed, %d\n", ret); + return ret; + } + } + return 0; +} - ret = nvkm_subdev_init_old(&fb->subdev); - if (ret) - return ret; +static int +nvkm_fb_init(struct nvkm_subdev *subdev) +{ + struct nvkm_fb *fb = nvkm_fb(subdev); + int ret, i; - if (fb->ram) - nvkm_ram_init(fb->ram); + if (fb->ram) { + ret = nvkm_ram_init(fb->ram); + if (ret) + return ret; + } for (i = 0; i < fb->tile.regions; i++) - fb->tile.prog(fb, i, &fb->tile.region[i]); + fb->func->tile.prog(fb, i, &fb->tile.region[i]); + if (fb->func->init) + fb->func->init(fb); return 0; } -void -_nvkm_fb_dtor(struct nvkm_object *object) +static void * +nvkm_fb_dtor(struct nvkm_subdev *subdev) { - struct nvkm_fb *fb = (void *)object; + struct nvkm_fb *fb = nvkm_fb(subdev); int i; for (i = 0; i < fb->tile.regions; i++) - fb->tile.fini(fb, i, &fb->tile.region[i]); + fb->func->tile.fini(fb, i, &fb->tile.region[i]); nvkm_ram_del(&fb->ram); - nvkm_subdev_destroy(&fb->subdev); -} -int -nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) -{ - struct nvkm_fb_impl *impl = (void *)oclass; - struct nvkm_fb *fb; - int ret; - - ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", - length, pobject); - fb = *pobject; - if (ret) - return ret; - - fb->memtype_valid = impl->memtype; + if (fb->func->dtor) + return fb->func->dtor(fb); + return fb; +} - if (!impl->ram_new) - return 0; +static const struct nvkm_subdev_func +nvkm_fb = { + .dtor = nvkm_fb_dtor, + .oneinit = nvkm_fb_oneinit, + .init = nvkm_fb_init, + .intr = nvkm_fb_intr, +}; - ret = impl->ram_new(fb, &fb->ram); - if (ret) { - nvkm_error(&fb->subdev, "vram init failed, %d\n", ret); - return ret; - } +void +nvkm_fb_ctor(const struct nvkm_fb_func *func, struct nvkm_device *device, + int index, struct nvkm_fb *fb) +{ + nvkm_subdev_ctor(&nvkm_fb, device, index, 0, &fb->subdev); + fb->func = func; + fb->tile.regions = fb->func->tile.regions; +} +int +nvkm_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, + int index, struct nvkm_fb **pfb) +{ + if (!(*pfb = kzalloc(sizeof(**pfb), GFP_KERNEL))) + return -ENOMEM; + nvkm_fb_ctor(func, device, index, *pfb); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c index 1fdb6c3493c6..9c28392d07e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c @@ -24,16 +24,14 @@ #include "nv50.h" #include "ram.h" -struct nvkm_oclass * -g84_fb_oclass = &(struct nv50_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x84), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fb_ctor, - .dtor = nv50_fb_dtor, - .init = nv50_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv50_fb_memtype_valid, - .base.ram_new = nv50_ram_new, +static const struct nv50_fb_func +g84_fb = { + .ram_new = nv50_ram_new, .trap = 0x001d07ff, -}.base.base; +}; + +int +g84_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nv50_fb_new_(&g84_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index b269f8f67eea..ef3149aa5124 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -33,9 +33,11 @@ gf100_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags) return likely((gf100_pte_storage_type_map[memtype] != 0xff)); } -static void -gf100_fb_intr(struct nvkm_subdev *subdev) +void +gf100_fb_intr(struct nvkm_fb *base) { + struct gf100_fb *fb = gf100_fb(base); + struct nvkm_subdev *subdev = &fb->base.subdev; struct nvkm_device *device = subdev->device; u32 intr = nvkm_rd32(device, 0x000100); if (intr & 0x08000000) @@ -44,29 +46,23 @@ gf100_fb_intr(struct nvkm_subdev *subdev) nvkm_debug(subdev, "PBFB intr\n"); } -int -gf100_fb_init(struct nvkm_object *object) +void +gf100_fb_init(struct nvkm_fb *base) { - struct gf100_fb *fb = (void *)object; + struct gf100_fb *fb = gf100_fb(base); struct nvkm_device *device = fb->base.subdev.device; - int ret; - - ret = nvkm_fb_init(&fb->base); - if (ret) - return ret; if (fb->r100c10_page) nvkm_wr32(device, 0x100c10, fb->r100c10 >> 8); nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ - return 0; } -void -gf100_fb_dtor(struct nvkm_object *object) +void * +gf100_fb_dtor(struct nvkm_fb *base) { - struct nvkm_device *device = nv_device(object); - struct gf100_fb *fb = (void *)object; + struct gf100_fb *fb = gf100_fb(base); + struct nvkm_device *device = fb->base.subdev.device; if (fb->r100c10_page) { dma_unmap_page(nv_device_base(device), fb->r100c10, PAGE_SIZE, @@ -74,22 +70,19 @@ gf100_fb_dtor(struct nvkm_object *object) __free_page(fb->r100c10_page); } - nvkm_fb_destroy(&fb->base); + return fb; } int -gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, + int index, struct nvkm_fb **pfb) { - struct nvkm_device *device = nv_device(parent); struct gf100_fb *fb; - int ret; - ret = nvkm_fb_create(parent, engine, oclass, &fb); - *pobject = nv_object(fb); - if (ret) - return ret; + if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL))) + return -ENOMEM; + nvkm_fb_ctor(func, device, index, &fb->base); + *pfb = &fb->base; fb->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (fb->r100c10_page) { @@ -100,19 +93,20 @@ gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return -EFAULT; } - nv_subdev(fb)->intr = gf100_fb_intr; return 0; } -struct nvkm_oclass * -gf100_fb_oclass = &(struct nvkm_fb_impl) { - .base.handle = NV_SUBDEV(FB, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_fb_ctor, - .dtor = gf100_fb_dtor, - .init = gf100_fb_init, - .fini = _nvkm_fb_fini, - }, - .memtype = gf100_fb_memtype_valid, +static const struct nvkm_fb_func +gf100_fb = { + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .intr = gf100_fb_intr, .ram_new = gf100_ram_new, -}.base; + .memtype_valid = gf100_fb_memtype_valid, +}; + +int +gf100_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return gf100_fb_new_(&gf100_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h index a0f6497d7a3f..2160e5a39c9a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -1,5 +1,6 @@ #ifndef __NVKM_RAM_NVC0_H__ #define __NVKM_RAM_NVC0_H__ +#define gf100_fb(p) container_of((p), struct gf100_fb, base) #include "priv.h" struct gf100_fb { @@ -8,10 +9,9 @@ struct gf100_fb { dma_addr_t r100c10; }; -int gf100_fb_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void gf100_fb_dtor(struct nvkm_object *); -int gf100_fb_init(struct nvkm_object *); -bool gf100_fb_memtype_valid(struct nvkm_fb *, u32); +int gf100_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *, + int index, struct nvkm_fb **); +void *gf100_fb_dtor(struct nvkm_fb *); +void gf100_fb_init(struct nvkm_fb *); +void gf100_fb_intr(struct nvkm_fb *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c index 6ed6181a7b34..0edb3c316f5c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c @@ -24,15 +24,17 @@ #include "gf100.h" #include "ram.h" -struct nvkm_oclass * -gk104_fb_oclass = &(struct nvkm_fb_impl) { - .base.handle = NV_SUBDEV(FB, 0xe0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_fb_ctor, - .dtor = gf100_fb_dtor, - .init = gf100_fb_init, - .fini = _nvkm_fb_fini, - }, - .memtype = gf100_fb_memtype_valid, +static const struct nvkm_fb_func +gk104_fb = { + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .intr = gf100_fb_intr, .ram_new = gk104_ram_new, -}.base; + .memtype_valid = gf100_fb_memtype_valid, +}; + +int +gk104_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return gf100_fb_new_(&gk104_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c index 24cbe90afec1..81447eb4c948 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c @@ -19,47 +19,23 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include "gf100.h" +#include "priv.h" -static int -gk20a_fb_init(struct nvkm_object *object) +static void +gk20a_fb_init(struct nvkm_fb *fb) { - struct nvkm_fb *fb = (void *)object; struct nvkm_device *device = fb->subdev.device; - int ret; - - ret = nvkm_fb_init(fb); - if (ret) - return ret; - nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ - return 0; } -static int -gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_fb *fb; - int ret; - - ret = nvkm_fb_create(parent, engine, oclass, &fb); - *pobject = nv_object(fb); - if (ret) - return ret; +static const struct nvkm_fb_func +gk20a_fb = { + .init = gk20a_fb_init, + .memtype_valid = gf100_fb_memtype_valid, +}; - return 0; +int +gk20a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&gk20a_fb, device, index, pfb); } - -struct nvkm_oclass * -gk20a_fb_oclass = &(struct nvkm_fb_impl) { - .base.handle = NV_SUBDEV(FB, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk20a_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = gk20a_fb_init, - .fini = _nvkm_fb_fini, - }, - .memtype = gf100_fb_memtype_valid, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c index 71e3bd50848a..2a91df8655dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -24,15 +24,17 @@ #include "gf100.h" #include "ram.h" -struct nvkm_oclass * -gm107_fb_oclass = &(struct nvkm_fb_impl) { - .base.handle = NV_SUBDEV(FB, 0x07), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_fb_ctor, - .dtor = gf100_fb_dtor, - .init = gf100_fb_init, - .fini = _nvkm_fb_fini, - }, - .memtype = gf100_fb_memtype_valid, +static const struct nvkm_fb_func +gm107_fb = { + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .intr = gf100_fb_intr, .ram_new = gm107_ram_new, -}.base; + .memtype_valid = gf100_fb_memtype_valid, +}; + +int +gm107_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return gf100_fb_new_(&gm107_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c index 425d289d4acc..ebb30608d5ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c @@ -24,16 +24,14 @@ #include "nv50.h" #include "ram.h" -struct nvkm_oclass * -gt215_fb_oclass = &(struct nv50_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0xa3), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fb_ctor, - .dtor = nv50_fb_dtor, - .init = nv50_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv50_fb_memtype_valid, - .base.ram_new = gt215_ram_new, +static const struct nv50_fb_func +gt215_fb = { + .ram_new = gt215_ram_new, .trap = 0x000d0fff, -}.base.base; +}; + +int +gt215_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nv50_fb_new_(>215_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c index 3caed0f12a77..73b3b86a2826 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c @@ -24,16 +24,14 @@ #include "nv50.h" #include "ram.h" -struct nvkm_oclass * -mcp77_fb_oclass = &(struct nv50_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0xaa), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fb_ctor, - .dtor = nv50_fb_dtor, - .init = nv50_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv50_fb_memtype_valid, - .base.ram_new = mcp77_ram_new, +static const struct nv50_fb_func +mcp77_fb = { + .ram_new = mcp77_ram_new, .trap = 0x001d07ff, -}.base.base; +}; + +int +mcp77_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nv50_fb_new_(&mcp77_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c index 3ff0bf9cefd2..6d11e32ec7ad 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c @@ -24,16 +24,14 @@ #include "nv50.h" #include "ram.h" -struct nvkm_oclass * -mcp89_fb_oclass = &(struct nv50_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0xaf), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fb_ctor, - .dtor = nv50_fb_dtor, - .init = nv50_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv50_fb_memtype_valid, - .base.ram_new = mcp77_ram_new, +static const struct nv50_fb_func +mcp89_fb = { + .ram_new = mcp77_ram_new, .trap = 0x089d1fff, -}.base.base; +}; + +int +mcp89_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nv50_fb_new_(&mcp89_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index 8c8b4b35930d..8ff2e5db4571 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" #include "ram.h" #include "regsnv04.h" @@ -30,60 +30,30 @@ nv04_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags) { if (!(tile_flags & 0xff00)) return true; - return false; } -static int -nv04_fb_init(struct nvkm_object *object) +static void +nv04_fb_init(struct nvkm_fb *fb) { - struct nvkm_fb *fb = (void *)object; struct nvkm_device *device = fb->subdev.device; - int ret; - - ret = nvkm_fb_init(fb); - if (ret) - return ret; /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows * nvidia reading PFB_CFG_0, then writing back its original value. * (which was 0x701114 in this case) */ nvkm_wr32(device, NV04_PFB_CFG0, 0x1114); - return 0; } +static const struct nvkm_fb_func +nv04_fb = { + .init = nv04_fb_init, + .ram_new = nv04_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + int -nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) { - struct nv04_fb_impl *impl = (void *)oclass; - struct nvkm_fb *fb; - int ret; - - ret = nvkm_fb_create(parent, engine, oclass, &fb); - *pobject = nv_object(fb); - if (ret) - return ret; - - fb->tile.regions = impl->tile.regions; - fb->tile.init = impl->tile.init; - fb->tile.comp = impl->tile.comp; - fb->tile.fini = impl->tile.fini; - fb->tile.prog = impl->tile.prog; - return 0; + return nvkm_fb_new_(&nv04_fb, device, index, pfb); } - -struct nvkm_oclass * -nv04_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x04), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv04_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv04_ram_new, -}.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h deleted file mode 100644 index b85ef3983539..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h +++ /dev/null @@ -1,49 +0,0 @@ -#ifndef __NVKM_FB_NV04_H__ -#define __NVKM_FB_NV04_H__ -#include "priv.h" - -int nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); - -struct nv04_fb_impl { - struct nvkm_fb_impl base; - struct { - int regions; - void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nvkm_fb_tile *); - void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, - struct nvkm_fb_tile *); - void (*fini)(struct nvkm_fb *, int i, - struct nvkm_fb_tile *); - void (*prog)(struct nvkm_fb *, int i, - struct nvkm_fb_tile *); - } tile; -}; - -void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nvkm_fb_tile *); -void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); -void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); - -void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nvkm_fb_tile *); -void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); -void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); - -int nv30_fb_init(struct nvkm_object *); -void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nvkm_fb_tile *); - -void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags, - struct nvkm_fb_tile *); - -int nv41_fb_init(struct nvkm_object *); -void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); - -int nv44_fb_init(struct nvkm_object *); -void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); - -void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nvkm_fb_tile *); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index a51c094df579..e8c44f5a3d84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" void @@ -54,19 +54,18 @@ nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) nvkm_rd32(device, 0x100240 + (i * 0x10)); } -struct nvkm_oclass * -nv10_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x10), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = _nvkm_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv10_ram_new, +static const struct nvkm_fb_func +nv10_fb = { .tile.regions = 8, .tile.init = nv10_fb_tile_init, .tile.fini = nv10_fb_tile_fini, .tile.prog = nv10_fb_tile_prog, -}.base.base; + .ram_new = nv10_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv10_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv10_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c index e56b93d593c5..2ae0beb87567 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c @@ -23,22 +23,21 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" -struct nvkm_oclass * -nv1a_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x1a), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = _nvkm_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv1a_ram_new, +static const struct nvkm_fb_func +nv1a_fb = { .tile.regions = 8, .tile.init = nv10_fb_tile_init, .tile.fini = nv10_fb_tile_fini, .tile.prog = nv10_fb_tile_prog, -}.base.base; + .ram_new = nv1a_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv1a_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv1a_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index ada818ac1735..126865dfe777 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" void @@ -34,7 +34,7 @@ nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, tile->limit = max(1u, addr + size) - 1; tile->pitch = pitch; if (flags & 4) { - fb->tile.comp(fb, i, size, flags, tile); + fb->func->tile.comp(fb, i, size, flags, tile); tile->addr |= 2; } } @@ -77,20 +77,19 @@ nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) nvkm_wr32(device, 0x100300 + (i * 0x04), tile->zcomp); } -struct nvkm_oclass * -nv20_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x20), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = _nvkm_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv20_ram_new, +static const struct nvkm_fb_func +nv20_fb = { .tile.regions = 8, .tile.init = nv20_fb_tile_init, .tile.comp = nv20_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv20_fb_tile_prog, -}.base.base; + .ram_new = nv20_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv20_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv20_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index 31dc7cf3aa0c..c56746d2a502 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" static void @@ -42,20 +42,19 @@ nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, } } -struct nvkm_oclass * -nv25_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x25), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = _nvkm_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv20_ram_new, +static const struct nvkm_fb_func +nv25_fb = { .tile.regions = 8, .tile.init = nv20_fb_tile_init, .tile.comp = nv25_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv20_fb_tile_prog, -}.base.base; + .ram_new = nv20_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv25_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv25_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 6bddaac59ad8..2a7c4831b821 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" void @@ -34,8 +34,8 @@ nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, if (!(flags & 4)) { tile->addr = (0 << 4); } else { - if (fb->tile.comp) /* z compression */ - fb->tile.comp(fb, i, size, flags, tile); + if (fb->func->tile.comp) /* z compression */ + fb->func->tile.comp(fb, i, size, flags, tile); tile->addr = (1 << 4); } @@ -65,7 +65,7 @@ nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, static int calc_bias(struct nvkm_fb *fb, int k, int i, int j) { - struct nvkm_device *device = nv_device(fb); + struct nvkm_device *device = fb->subdev.device; int b = (device->chipset > 0x30 ? nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : @@ -88,16 +88,11 @@ calc_ref(struct nvkm_fb *fb, int l, int k, int i) return x; } -int -nv30_fb_init(struct nvkm_object *object) +void +nv30_fb_init(struct nvkm_fb *fb) { - struct nvkm_device *device = nv_device(object); - struct nvkm_fb *fb = (void *)object; - int ret, i, j; - - ret = nvkm_fb_init(fb); - if (ret) - return ret; + struct nvkm_device *device = fb->subdev.device; + int i, j; /* Init the memory timing regs at 0x10037c/0x1003ac */ if (device->chipset == 0x30 || @@ -117,24 +112,22 @@ nv30_fb_init(struct nvkm_object *object) calc_ref(fb, l, 1, j)); } } - - return 0; } -struct nvkm_oclass * -nv30_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x30), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv30_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv20_ram_new, +static const struct nvkm_fb_func +nv30_fb = { + .init = nv30_fb_init, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv30_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv20_fb_tile_prog, -}.base.base; + .ram_new = nv20_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv30_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv30_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index e4fd94d003aa..1604b3789ad1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" static void @@ -43,20 +43,20 @@ nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, } } -struct nvkm_oclass * -nv35_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x35), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv30_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv20_ram_new, +static const struct nvkm_fb_func +nv35_fb = { + .init = nv30_fb_init, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv35_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv20_fb_tile_prog, -}.base.base; + .ram_new = nv20_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv35_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv35_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index 51b9b4a58930..80cc0a6e3416 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" static void @@ -43,20 +43,20 @@ nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, } } -struct nvkm_oclass * -nv36_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x36), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv30_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv20_ram_new, +static const struct nvkm_fb_func +nv36_fb = { + .init = nv30_fb_init, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv36_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv20_fb_tile_prog, -}.base.base; + .ram_new = nv20_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv36_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv36_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index fa1f8047714e..deec46a310f8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" void @@ -43,35 +43,26 @@ nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, } } -static int -nv40_fb_init(struct nvkm_object *object) +static void +nv40_fb_init(struct nvkm_fb *fb) { - struct nvkm_fb *fb = (void *)object; - struct nvkm_device *device = fb->subdev.device; - int ret; - - ret = nvkm_fb_init(fb); - if (ret) - return ret; - - nvkm_mask(device, 0x10033c, 0x00008000, 0x00000000); - return 0; + nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); } -struct nvkm_oclass * -nv40_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x40), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv40_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv40_ram_new, +static const struct nvkm_fb_func +nv40_fb = { + .init = nv40_fb_init, .tile.regions = 8, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv20_fb_tile_prog, -}.base.base; + .ram_new = nv40_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv40_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv40_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index 5e11dd8ab5c6..79e57dd5a00f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" void @@ -37,35 +37,26 @@ nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); } -int -nv41_fb_init(struct nvkm_object *object) +void +nv41_fb_init(struct nvkm_fb *fb) { - struct nvkm_fb *fb = (void *)object; - struct nvkm_device *device = fb->subdev.device; - int ret; - - ret = nvkm_fb_init(fb); - if (ret) - return ret; - - nvkm_wr32(device, 0x100800, 0x00000001); - return 0; + nvkm_wr32(fb->subdev.device, 0x100800, 0x00000001); } -struct nvkm_oclass * -nv41_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x41), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv41_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv41_ram_new, +static const struct nvkm_fb_func +nv41_fb = { + .init = nv41_fb_init, .tile.regions = 12, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv41_fb_tile_prog, -}.base.base; + .ram_new = nv41_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv41_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv41_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index ffdf74b698a7..06246cce5ec4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" static void @@ -46,35 +46,27 @@ nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) nvkm_rd32(device, 0x100600 + (i * 0x10)); } -int -nv44_fb_init(struct nvkm_object *object) +void +nv44_fb_init(struct nvkm_fb *fb) { - struct nvkm_fb *fb = (void *)object; struct nvkm_device *device = fb->subdev.device; - int ret; - - ret = nvkm_fb_init(fb); - if (ret) - return ret; - nvkm_wr32(device, 0x100850, 0x80000000); nvkm_wr32(device, 0x100800, 0x00000001); - return 0; } -struct nvkm_oclass * -nv44_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x44), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv44_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv44_ram_new, +static const struct nvkm_fb_func +nv44_fb = { + .init = nv44_fb_init, .tile.regions = 12, .tile.init = nv44_fb_tile_init, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv44_fb_tile_prog, -}.base.base; + .ram_new = nv44_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv44_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv44_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index c9685991042a..3598a1aa65be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -23,7 +23,7 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" void @@ -40,19 +40,19 @@ nv46_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, tile->pitch = pitch; } -struct nvkm_oclass * -nv46_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x46), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv44_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv44_ram_new, +static const struct nvkm_fb_func +nv46_fb = { + .init = nv44_fb_init, .tile.regions = 15, .tile.init = nv46_fb_tile_init, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv44_fb_tile_prog, -}.base.base; + .ram_new = nv44_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv46_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv46_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c index f150f2df16dc..c505e4429314 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c @@ -23,23 +23,23 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" -struct nvkm_oclass * -nv47_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x47), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv41_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv41_ram_new, +static const struct nvkm_fb_func +nv47_fb = { + .init = nv41_fb_init, .tile.regions = 15, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv41_fb_tile_prog, -}.base.base; + .ram_new = nv41_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv47_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv47_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c index 806c7851a164..7b91b9f170e5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c @@ -23,23 +23,23 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" -struct nvkm_oclass * -nv49_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x49), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv41_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv49_ram_new, +static const struct nvkm_fb_func +nv49_fb = { + .init = nv41_fb_init, .tile.regions = 15, .tile.init = nv30_fb_tile_init, .tile.comp = nv40_fb_tile_comp, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv41_fb_tile_prog, -}.base.base; + .ram_new = nv49_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv49_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv49_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c index 6f24565c9774..4e98210c1b1c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c @@ -23,22 +23,22 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ -#include "nv04.h" +#include "priv.h" #include "ram.h" -struct nvkm_oclass * -nv4e_fb_oclass = &(struct nv04_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x4e), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fb_ctor, - .dtor = _nvkm_fb_dtor, - .init = nv44_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv04_fb_memtype_valid, - .base.ram_new = nv4e_ram_new, +static const struct nvkm_fb_func +nv4e_fb = { + .init = nv44_fb_init, .tile.regions = 12, .tile.init = nv46_fb_tile_init, .tile.fini = nv20_fb_tile_fini, .tile.prog = nv44_fb_tile_prog, -}.base.base; + .ram_new = nv44_ram_new, + .memtype_valid = nv04_fb_memtype_valid, +}; + +int +nv4e_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nvkm_fb_new_(&nv4e_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 711ea96bcd36..c2b6ccde7473 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -40,7 +40,14 @@ nv50_fb_memtype[0x80] = { 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0 }; -bool +static int +nv50_fb_ram_new(struct nvkm_fb *base, struct nvkm_ram **pram) +{ + struct nv50_fb *fb = nv50_fb(base); + return fb->func->ram_new(&fb->base, pram); +} + +static bool nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype) { return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0; @@ -143,10 +150,11 @@ static const struct nvkm_enum vm_fault[] = { }; static void -nv50_fb_intr(struct nvkm_subdev *subdev) +nv50_fb_intr(struct nvkm_fb *base) { - struct nv50_fb *fb = (void *)subdev; - struct nvkm_device *device = fb->base.subdev.device; + struct nv50_fb *fb = nv50_fb(base); + struct nvkm_subdev *subdev = &fb->base.subdev; + struct nvkm_device *device = subdev->device; struct nvkm_fifo *fifo = device->fifo; struct nvkm_fifo_chan *chan; const struct nvkm_enum *en, *re, *cl, *sc; @@ -202,40 +210,28 @@ nv50_fb_intr(struct nvkm_subdev *subdev) nvkm_fifo_chan_put(fifo, flags, &chan); } -int -nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static void +nv50_fb_init(struct nvkm_fb *base) { - struct nvkm_device *device = nv_device(parent); - struct nv50_fb *fb; - int ret; - - ret = nvkm_fb_create(parent, engine, oclass, &fb); - *pobject = nv_object(fb); - if (ret) - return ret; + struct nv50_fb *fb = nv50_fb(base); + struct nvkm_device *device = fb->base.subdev.device; - fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); - if (fb->r100c08_page) { - fb->r100c08 = dma_map_page(nv_device_base(device), - fb->r100c08_page, 0, PAGE_SIZE, - DMA_BIDIRECTIONAL); - if (dma_mapping_error(nv_device_base(device), fb->r100c08)) - return -EFAULT; - } else { - nvkm_warn(&fb->base.subdev, "failed 100c08 page alloc\n"); - } + /* Not a clue what this is exactly. Without pointing it at a + * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) + * cause IOMMU "read from address 0" errors (rh#561267) + */ + nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8); - nv_subdev(fb)->intr = nv50_fb_intr; - return 0; + /* This is needed to get meaningful information from 100c90 + * on traps. No idea what these values mean exactly. */ + nvkm_wr32(device, 0x100c90, fb->func->trap); } -void -nv50_fb_dtor(struct nvkm_object *object) +static void * +nv50_fb_dtor(struct nvkm_fb *base) { - struct nvkm_device *device = nv_device(object); - struct nv50_fb *fb = (void *)object; + struct nv50_fb *fb = nv50_fb(base); + struct nvkm_device *device = fb->base.subdev.device; if (fb->r100c08_page) { dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE, @@ -243,43 +239,52 @@ nv50_fb_dtor(struct nvkm_object *object) __free_page(fb->r100c08_page); } - nvkm_fb_destroy(&fb->base); + return fb; } +static const struct nvkm_fb_func +nv50_fb_ = { + .dtor = nv50_fb_dtor, + .init = nv50_fb_init, + .intr = nv50_fb_intr, + .ram_new = nv50_fb_ram_new, + .memtype_valid = nv50_fb_memtype_valid, +}; + int -nv50_fb_init(struct nvkm_object *object) +nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device, + int index, struct nvkm_fb **pfb) { - struct nv50_fb_impl *impl = (void *)object->oclass; - struct nv50_fb *fb = (void *)object; - struct nvkm_device *device = fb->base.subdev.device; - int ret; + struct nv50_fb *fb; - ret = nvkm_fb_init(&fb->base); - if (ret) - return ret; + if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL))) + return -ENOMEM; + nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base); + fb->func = func; + *pfb = &fb->base; - /* Not a clue what this is exactly. Without pointing it at a - * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) - * cause IOMMU "read from address 0" errors (rh#561267) - */ - nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8); + fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); + if (fb->r100c08_page) { + fb->r100c08 = dma_map_page(nv_device_base(device), + fb->r100c08_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(nv_device_base(device), fb->r100c08)) + return -EFAULT; + } else { + nvkm_warn(&fb->base.subdev, "failed 100c08 page alloc\n"); + } - /* This is needed to get meaningful information from 100c90 - * on traps. No idea what these values mean exactly. */ - nvkm_wr32(device, 0x100c90, impl->trap); return 0; } -struct nvkm_oclass * -nv50_fb_oclass = &(struct nv50_fb_impl) { - .base.base.handle = NV_SUBDEV(FB, 0x50), - .base.base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fb_ctor, - .dtor = nv50_fb_dtor, - .init = nv50_fb_init, - .fini = _nvkm_fb_fini, - }, - .base.memtype = nv50_fb_memtype_valid, - .base.ram_new = nv50_ram_new, +static const struct nv50_fb_func +nv50_fb = { + .ram_new = nv50_ram_new, .trap = 0x000707ff, -}.base.base; +}; + +int +nv50_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb) +{ + return nv50_fb_new_(&nv50_fb, device, index, pfb); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index 92bfc3b9bb6d..faa88c8c66fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -1,23 +1,21 @@ #ifndef __NVKM_FB_NV50_H__ #define __NVKM_FB_NV50_H__ +#define nv50_fb(p) container_of((p), struct nv50_fb, base) #include "priv.h" struct nv50_fb { + const struct nv50_fb_func *func; struct nvkm_fb base; struct page *r100c08_page; dma_addr_t r100c08; }; -int nv50_fb_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void nv50_fb_dtor(struct nvkm_object *); -int nv50_fb_init(struct nvkm_object *); - -struct nv50_fb_impl { - struct nvkm_fb_impl base; +struct nv50_fb_func { + int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **); u32 trap; }; +int nv50_fb_new_(const struct nv50_fb_func *, struct nvkm_device *, int index, + struct nvkm_fb **pfb); extern int nv50_fb_memtype[0x80]; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index f206152a3e63..62b9feb531dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -1,37 +1,62 @@ #ifndef __NVKM_FB_PRIV_H__ #define __NVKM_FB_PRIV_H__ +#define nvkm_fb(p) container_of((p), struct nvkm_fb, subdev) #include struct nvkm_bios; -#define nvkm_fb_create(p,e,c,d) \ - nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d) -#define nvkm_fb_destroy(p) ({ \ - struct nvkm_fb *_fb = (p); \ - _nvkm_fb_dtor(nv_object(_fb)); \ -}) -#define nvkm_fb_init(p) ({ \ - struct nvkm_fb *_fb = (p); \ - _nvkm_fb_init(nv_object(_fb)); \ -}) -#define nvkm_fb_fini(p,s) ({ \ - struct nvkm_fb *_fb = (p); \ - _nvkm_fb_fini(nv_object(_fb), (s)); \ -}) - -int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); -void _nvkm_fb_dtor(struct nvkm_object *); -int _nvkm_fb_init(struct nvkm_object *); -int _nvkm_fb_fini(struct nvkm_object *, bool); - -struct nvkm_fb_impl { - struct nvkm_oclass base; +struct nvkm_fb_func { + void *(*dtor)(struct nvkm_fb *); + void (*init)(struct nvkm_fb *); + void (*intr)(struct nvkm_fb *); + + struct { + int regions; + void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + } tile; + int (*ram_new)(struct nvkm_fb *, struct nvkm_ram **); - bool (*memtype)(struct nvkm_fb *, u32); + + bool (*memtype_valid)(struct nvkm_fb *, u32 memtype); }; +void nvkm_fb_ctor(const struct nvkm_fb_func *, struct nvkm_device *device, + int index, struct nvkm_fb *); +int nvkm_fb_new_(const struct nvkm_fb_func *, struct nvkm_device *device, + int index, struct nvkm_fb **); +int nvkm_fb_bios_memtype(struct nvkm_bios *); + bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype); -bool nv50_fb_memtype_valid(struct nvkm_fb *, u32 memtype); -int nvkm_fb_bios_memtype(struct nvkm_bios *); +void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); +void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); +void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +void nv30_fb_init(struct nvkm_fb *); +void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + +void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + +void nv41_fb_init(struct nvkm_fb *); +void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +void nv44_fb_init(struct nvkm_fb *); +void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); + +void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + +bool gf100_fb_memtype_valid(struct nvkm_fb *, u32); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h index 60d8ed4b78b2..9ef9d6aa3721 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h @@ -57,10 +57,7 @@ ramfuc_reg(u32 addr) static inline int ramfuc_init(struct ramfuc *ram, struct nvkm_fb *fb) { - struct nvkm_pmu *pmu = nvkm_pmu(fb); - int ret; - - ret = nvkm_memx_init(pmu, &ram->memx); + int ret = nvkm_memx_init(fb->subdev.device->pmu, &ram->memx); if (ret) return ret; @@ -148,9 +145,7 @@ ramfuc_train(struct ramfuc *ram) static inline int ramfuc_train_result(struct nvkm_fb *fb, u32 *result, u32 rsize) { - struct nvkm_pmu *pmu = nvkm_pmu(fb); - - return nvkm_memx_train_result(pmu, result, rsize); + return nvkm_memx_train_result(fb->subdev.device->pmu, result, rsize); } static inline void diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 0f07309da71d..b4306824f7a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -1457,7 +1457,7 @@ gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) struct dcb_gpio_func func; struct gk104_ram *ram; int ret, i; - u8 ramcfg = nvbios_ramcfg_index(nv_subdev(fb)); + u8 ramcfg = nvbios_ramcfg_index(subdev); u32 tmp; if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index c08ac609cbe7..f1f62a217e91 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -77,14 +77,15 @@ static void nv50_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt, struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) { + struct nvkm_ram *ram = vma->vm->mmu->subdev.device->fb->ram; u32 comp = (mem->memtype & 0x180) >> 7; u32 block, target; int i; /* IGPs don't have real VRAM, re-target to stolen system memory */ target = 0; - if (nvkm_fb(vma->vm->mmu)->ram->stolen) { - phys += nvkm_fb(vma->vm->mmu)->ram->stolen; + if (ram->stolen) { + phys += ram->stolen; target = 3; } -- cgit v1.2.3 From b7a2bc1886d00f5f1358079e1e6f4979006a4ed6 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:20 +1000 Subject: drm/nouveau/imem: convert to new-style nvkm_subdev Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/instmem.h | 35 ++---- drivers/gpu/drm/nouveau/nvkm/core/memory.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 138 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 --- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 --- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c | 91 +++++++++----- .../gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 54 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c | 75 ++++++----- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c | 122 +++++++++--------- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 47 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h | 29 ++--- 21 files changed, 285 insertions(+), 391 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h index a4b943ee7a9a..28bc202f9753 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h @@ -4,14 +4,11 @@ struct nvkm_memory; struct nvkm_instmem { + const struct nvkm_instmem_func *func; struct nvkm_subdev subdev; - struct list_head list; + struct list_head list; u32 reserved; - int (*alloc)(struct nvkm_instmem *, u32 size, u32 align, bool zero, - struct nvkm_memory **); - - const struct nvkm_instmem_func *func; struct nvkm_memory *vbios; struct nvkm_ramht *ramht; @@ -19,26 +16,14 @@ struct nvkm_instmem { struct nvkm_memory *ramfc; }; -struct nvkm_instmem_func { - u32 (*rd32)(struct nvkm_instmem *, u32 addr); - void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data); -}; - -static inline struct nvkm_instmem * -nvkm_instmem(void *obj) -{ - /* nv04/nv40 impls need to create objects in their constructor, - * which is before the subdev pointer is valid - */ - if (nv_iclass(obj, NV_SUBDEV_CLASS) && - nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM) - return obj; +u32 nvkm_instmem_rd32(struct nvkm_instmem *, u32 addr); +void nvkm_instmem_wr32(struct nvkm_instmem *, u32 addr, u32 data); +int nvkm_instobj_new(struct nvkm_instmem *, u32 size, u32 align, bool zero, + struct nvkm_memory **); - return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM); -} -extern struct nvkm_oclass *nv04_instmem_oclass; -extern struct nvkm_oclass *nv40_instmem_oclass; -extern struct nvkm_oclass *nv50_instmem_oclass; -extern struct nvkm_oclass *gk20a_instmem_oclass; +int nv04_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); +int nv40_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); +int nv50_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); +int gk20a_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/core/memory.c b/drivers/gpu/drm/nouveau/nvkm/core/memory.c index 0b88faa845f3..8903c04c977e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/memory.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/memory.c @@ -55,7 +55,7 @@ nvkm_memory_new(struct nvkm_device *device, enum nvkm_memory_target target, if (unlikely(target != NVKM_MEM_TARGET_INST || !imem)) return -ENOSYS; - ret = imem->alloc(imem, size, align, zero, &memory); + ret = nvkm_instobj_new(imem, size, align, zero, &memory); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 99a07694a298..3b83f17b3a23 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -82,7 +82,7 @@ nv4_chipset = { .devinit = nv04_devinit_new, .fb = nv04_fb_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -102,7 +102,7 @@ nv5_chipset = { .devinit = nv05_devinit_new, .fb = nv04_fb_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -123,7 +123,7 @@ nv10_chipset = { .fb = nv10_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -142,7 +142,7 @@ nv11_chipset = { .fb = nv10_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -163,7 +163,7 @@ nv15_chipset = { .fb = nv10_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -184,7 +184,7 @@ nv17_chipset = { .fb = nv10_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -205,7 +205,7 @@ nv18_chipset = { .fb = nv10_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -226,7 +226,7 @@ nv1a_chipset = { .fb = nv1a_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -247,7 +247,7 @@ nv1f_chipset = { .fb = nv1a_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -268,7 +268,7 @@ nv20_chipset = { .fb = nv20_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -289,7 +289,7 @@ nv25_chipset = { .fb = nv25_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -310,7 +310,7 @@ nv28_chipset = { .fb = nv25_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -331,7 +331,7 @@ nv2a_chipset = { .fb = nv25_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -352,7 +352,7 @@ nv30_chipset = { .fb = nv30_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -373,7 +373,7 @@ nv31_chipset = { .fb = nv30_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -395,7 +395,7 @@ nv34_chipset = { .fb = nv10_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -417,7 +417,7 @@ nv35_chipset = { .fb = nv35_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -438,7 +438,7 @@ nv36_chipset = { .fb = nv36_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv04_instmem_new, + .imem = nv04_instmem_new, // .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, @@ -460,7 +460,7 @@ nv40_chipset = { .fb = nv40_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv04_mmu_new, // .therm = nv40_therm_new, @@ -485,7 +485,7 @@ nv41_chipset = { .fb = nv41_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, @@ -510,7 +510,7 @@ nv42_chipset = { .fb = nv41_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, @@ -535,7 +535,7 @@ nv43_chipset = { .fb = nv41_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, @@ -560,7 +560,7 @@ nv44_chipset = { .fb = nv44_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv44_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -585,7 +585,7 @@ nv45_chipset = { .fb = nv40_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv04_mmu_new, // .therm = nv40_therm_new, @@ -610,7 +610,7 @@ nv46_chipset = { .fb = nv46_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv44_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -635,7 +635,7 @@ nv47_chipset = { .fb = nv47_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, @@ -660,7 +660,7 @@ nv49_chipset = { .fb = nv49_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, @@ -685,7 +685,7 @@ nv4a_chipset = { .fb = nv44_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv44_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -710,7 +710,7 @@ nv4b_chipset = { .fb = nv49_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, @@ -735,7 +735,7 @@ nv4c_chipset = { .fb = nv46_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -760,7 +760,7 @@ nv4e_chipset = { .fb = nv4e_fb_new, .gpio = nv10_gpio_new, .i2c = nv4e_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -787,7 +787,7 @@ nv50_chipset = { .fuse = nv50_fuse_new, .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -813,7 +813,7 @@ nv63_chipset = { .fb = nv46_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -838,7 +838,7 @@ nv67_chipset = { .fb = nv46_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -863,7 +863,7 @@ nv68_chipset = { .fb = nv46_fb_new, .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, -// .imem = nv40_instmem_new, + .imem = nv40_instmem_new, // .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, @@ -890,7 +890,7 @@ nv84_chipset = { .fuse = nv50_fuse_new, .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -921,7 +921,7 @@ nv86_chipset = { .fuse = nv50_fuse_new, .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -952,7 +952,7 @@ nv92_chipset = { .fuse = nv50_fuse_new, .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -983,7 +983,7 @@ nv94_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g94_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1017,7 +1017,7 @@ nv96_chipset = { .bus = g94_bus_new, // .timer = nv04_timer_new, .fb = g84_fb_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mmu = nv50_mmu_new, .bar = g84_bar_new, // .volt = nv40_volt_new, @@ -1048,7 +1048,7 @@ nv98_chipset = { .bus = g94_bus_new, // .timer = nv04_timer_new, .fb = g84_fb_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mmu = nv50_mmu_new, .bar = g84_bar_new, // .volt = nv40_volt_new, @@ -1076,7 +1076,7 @@ nva0_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = nv50_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1107,7 +1107,7 @@ nva3_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1140,7 +1140,7 @@ nva5_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1172,7 +1172,7 @@ nva8_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1204,7 +1204,7 @@ nvaa_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1235,7 +1235,7 @@ nvac_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1266,7 +1266,7 @@ nvaf_chipset = { .fuse = nv50_fuse_new, .gpio = g94_gpio_new, .i2c = g94_i2c_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, @@ -1299,7 +1299,7 @@ nvc0_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, @@ -1334,7 +1334,7 @@ nvc1_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1368,7 +1368,7 @@ nvc3_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1402,7 +1402,7 @@ nvc4_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, @@ -1437,7 +1437,7 @@ nvc8_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, @@ -1472,7 +1472,7 @@ nvce_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, @@ -1507,7 +1507,7 @@ nvcf_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1541,7 +1541,7 @@ nvd7_chipset = { .gpio = gf119_gpio_new, .i2c = gf117_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1573,7 +1573,7 @@ nvd9_chipset = { .gpio = gf119_gpio_new, .i2c = gf119_i2c_new, .ibus = gf100_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1607,7 +1607,7 @@ nve4_chipset = { .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1643,7 +1643,7 @@ nve6_chipset = { .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1679,7 +1679,7 @@ nve7_chipset = { .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1711,7 +1711,7 @@ nvea_chipset = { .fb = gk20a_fb_new, .fuse = gf100_fuse_new, .ibus = gk20a_ibus_new, -// .imem = gk20a_instmem_new, + .imem = gk20a_instmem_new, // .ltc = gk104_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, @@ -1739,7 +1739,7 @@ nvf0_chipset = { .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1775,7 +1775,7 @@ nvf1_chipset = { .gpio = gk104_gpio_new, .i2c = gf119_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, @@ -1811,7 +1811,7 @@ nv106_chipset = { .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, @@ -1846,7 +1846,7 @@ nv108_chipset = { .gpio = gk104_gpio_new, .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gk104_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, @@ -1881,7 +1881,7 @@ nv117_chipset = { .gpio = gk104_gpio_new, .i2c = gf119_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, @@ -1910,7 +1910,7 @@ nv124_chipset = { .gpio = gk104_gpio_new, .i2c = gm204_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, @@ -1939,7 +1939,7 @@ nv126_chipset = { .gpio = gk104_gpio_new, .i2c = gm204_i2c_new, .ibus = gk104_ibus_new, -// .imem = nv50_instmem_new, + .imem = nv50_instmem_new, // .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, @@ -1964,7 +1964,7 @@ nv12b_chipset = { .fb = gk20a_fb_new, .fuse = gm107_fuse_new, .ibus = gk20a_ibus_new, -// .imem = gk20a_instmem_new, + .imem = gk20a_instmem_new, // .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index a0f54fd80810..8f9d871b545f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -33,7 +33,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -55,7 +54,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -77,7 +75,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -98,7 +95,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -120,7 +116,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -141,7 +136,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -162,7 +156,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -184,7 +177,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -205,7 +197,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index f2f524b21950..dcb0f6db213d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -33,7 +33,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -56,7 +55,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -79,7 +77,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -100,7 +97,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; @@ -117,7 +113,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -140,7 +135,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -163,7 +157,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -185,7 +178,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 9c0306279de8..158af1f8799e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -33,7 +33,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; @@ -66,7 +65,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 @@ -96,7 +94,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 @@ -122,7 +119,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index de456b2d44b3..dc90bad93869 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -30,7 +30,6 @@ nv04_identify(struct nvkm_device *device) case 0x04: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; @@ -41,7 +40,6 @@ nv04_identify(struct nvkm_device *device) case 0x05: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 6e58a0e20ba2..b1db20f4a15c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -30,7 +30,6 @@ nv10_identify(struct nvkm_device *device) case 0x10: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; @@ -39,7 +38,6 @@ nv10_identify(struct nvkm_device *device) case 0x15: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; @@ -50,7 +48,6 @@ nv10_identify(struct nvkm_device *device) case 0x16: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; @@ -61,7 +58,6 @@ nv10_identify(struct nvkm_device *device) case 0x1a: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; @@ -72,7 +68,6 @@ nv10_identify(struct nvkm_device *device) case 0x11: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; @@ -83,7 +78,6 @@ nv10_identify(struct nvkm_device *device) case 0x17: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -94,7 +88,6 @@ nv10_identify(struct nvkm_device *device) case 0x1f: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -105,7 +98,6 @@ nv10_identify(struct nvkm_device *device) case 0x18: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index 146773775922..f11b7d01f34a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -30,7 +30,6 @@ nv20_identify(struct nvkm_device *device) case 0x20: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -41,7 +40,6 @@ nv20_identify(struct nvkm_device *device) case 0x25: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -52,7 +50,6 @@ nv20_identify(struct nvkm_device *device) case 0x28: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -63,7 +60,6 @@ nv20_identify(struct nvkm_device *device) case 0x2a: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index e4d5fc697f49..780dd1019666 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -30,7 +30,6 @@ nv30_identify(struct nvkm_device *device) case 0x30: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -41,7 +40,6 @@ nv30_identify(struct nvkm_device *device) case 0x35: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -52,7 +50,6 @@ nv30_identify(struct nvkm_device *device) case 0x31: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -64,7 +61,6 @@ nv30_identify(struct nvkm_device *device) case 0x36: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; @@ -76,7 +72,6 @@ nv30_identify(struct nvkm_device *device) case 0x34: device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 0bf4fcefcf88..a5d874a2c297 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -31,7 +31,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -46,7 +45,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -61,7 +59,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -76,7 +73,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -91,7 +87,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -106,7 +101,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -121,7 +115,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -136,7 +129,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -151,7 +143,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -166,7 +157,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -181,7 +171,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -196,7 +185,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -211,7 +199,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -226,7 +213,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -241,7 +227,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -256,7 +241,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 956ea9c02f45..2507559e5894 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -32,7 +32,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -48,7 +47,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -67,7 +65,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -86,7 +83,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -105,7 +101,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -124,7 +119,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -143,7 +137,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -162,7 +155,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -181,7 +173,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -200,7 +191,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; @@ -219,7 +209,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -240,7 +229,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -260,7 +248,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -280,7 +267,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 0103337f55d2..0e4e1152eeec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -353,6 +353,7 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { + struct nvkm_device *device = (void *)parent; struct nv40_gr *gr; int ret; @@ -365,7 +366,7 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv_subdev(gr)->unit = 0x00001000; nv_subdev(gr)->intr = nv40_gr_intr; - if (nv44_gr_class(gr)) + if (nv44_gr_class(device)) gr->base.func = &nv44_gr; else gr->base.func = &nv40_gr; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index eefb36cbeeea..42cc409a8df2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -23,10 +23,8 @@ struct nv40_gr_chan { * helpful to determine a number of other hardware features */ static inline int -nv44_gr_class(void *priv) +nv44_gr_class(struct nvkm_device *device) { - struct nvkm_device *device = nv_device(priv); - if ((device->chipset & 0xf0) == 0x60) return 1; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c index b4ef1ebd38ab..97529c4f0a25 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c @@ -32,9 +32,9 @@ nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data) { struct nvkm_instmem *imem = device->imem; u32 inst = data << 4; - u32 dma0 = imem->func->rd32(imem, inst + 0); - u32 dma1 = imem->func->rd32(imem, inst + 4); - u32 dma2 = imem->func->rd32(imem, inst + 8); + u32 dma0 = nvkm_instmem_rd32(imem, inst + 0); + u32 dma1 = nvkm_instmem_rd32(imem, inst + 4); + u32 dma2 = nvkm_instmem_rd32(imem, inst + 8); u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); u32 size = dma1 + 1; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c index 6a356f348c58..895ba74057d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c @@ -168,21 +168,20 @@ nvkm_instobj_func_slow = { .map = nvkm_instobj_map, }; -static int +int nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero, struct nvkm_memory **pmemory) { - struct nvkm_instmem_impl *impl = (void *)imem->subdev.object.oclass; - struct nvkm_memory *memory; + struct nvkm_memory *memory = NULL; struct nvkm_instobj *iobj; u32 offset; int ret; - ret = impl->memory_new(imem, size, align, zero, &memory); + ret = imem->func->memory_new(imem, size, align, zero, &memory); if (ret) goto done; - if (!impl->persistent) { + if (!imem->func->persistent) { if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) { ret = -ENOMEM; goto done; @@ -195,7 +194,7 @@ nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero, memory = &iobj->memory; } - if (!impl->zero && zero) { + if (!imem->func->zero && zero) { void __iomem *map = nvkm_kmap(memory); if (unlikely(!map)) { for (offset = 0; offset < size; offset += 4) @@ -217,13 +216,28 @@ done: * instmem subdev base implementation *****************************************************************************/ -int -_nvkm_instmem_fini(struct nvkm_object *object, bool suspend) +u32 +nvkm_instmem_rd32(struct nvkm_instmem *imem, u32 addr) +{ + return imem->func->rd32(imem, addr); +} + +void +nvkm_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data) +{ + return imem->func->wr32(imem, addr, data); +} + +static int +nvkm_instmem_fini(struct nvkm_subdev *subdev, bool suspend) { - struct nvkm_instmem *imem = (void *)object; + struct nvkm_instmem *imem = nvkm_instmem(subdev); struct nvkm_instobj *iobj; int i; + if (imem->func->fini) + imem->func->fini(imem); + if (suspend) { list_for_each_entry(iobj, &imem->list, head) { struct nvkm_memory *memory = iobj->parent; @@ -238,19 +252,24 @@ _nvkm_instmem_fini(struct nvkm_object *object, bool suspend) } } - return nvkm_subdev_fini_old(&imem->subdev, suspend); + return 0; } -int -_nvkm_instmem_init(struct nvkm_object *object) +static int +nvkm_instmem_oneinit(struct nvkm_subdev *subdev) { - struct nvkm_instmem *imem = (void *)object; - struct nvkm_instobj *iobj; - int ret, i; + struct nvkm_instmem *imem = nvkm_instmem(subdev); + if (imem->func->oneinit) + return imem->func->oneinit(imem); + return 0; +} - ret = nvkm_subdev_init_old(&imem->subdev); - if (ret) - return ret; +static int +nvkm_instmem_init(struct nvkm_subdev *subdev) +{ + struct nvkm_instmem *imem = nvkm_instmem(subdev); + struct nvkm_instobj *iobj; + int i; list_for_each_entry(iobj, &imem->list, head) { if (iobj->suspend) { @@ -266,23 +285,29 @@ _nvkm_instmem_init(struct nvkm_object *object) return 0; } -int -nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) +static void * +nvkm_instmem_dtor(struct nvkm_subdev *subdev) { - struct nvkm_device *device = (void *)parent; - struct nvkm_instmem *imem; - int ret; - - ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM", - "instmem", length, pobject); - imem = *pobject; - if (ret) - return ret; + struct nvkm_instmem *imem = nvkm_instmem(subdev); + if (imem->func->dtor) + return imem->func->dtor(imem); + return imem; +} - device->imem = imem; +static const struct nvkm_subdev_func +nvkm_instmem = { + .dtor = nvkm_instmem_dtor, + .oneinit = nvkm_instmem_oneinit, + .init = nvkm_instmem_init, + .fini = nvkm_instmem_fini, +}; +void +nvkm_instmem_ctor(const struct nvkm_instmem_func *func, + struct nvkm_device *device, int index, + struct nvkm_instmem *imem) +{ + nvkm_subdev_ctor(&nvkm_instmem, device, index, 0, &imem->subdev); + imem->func = func; INIT_LIST_HEAD(&imem->list); - imem->alloc = nvkm_instobj_new; - return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index a64c3f9bfc3d..ab01989c3430 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -186,7 +186,7 @@ gk20a_instobj_dtor_dma(struct gk20a_instobj *_node) { struct gk20a_instobj_dma *node = (void *)_node; struct gk20a_instmem *imem = _node->imem; - struct device *dev = nv_device_base(nv_device(imem)); + struct device *dev = nv_device_base(imem->base.subdev.device); if (unlikely(!node->cpuaddr)) return; @@ -372,7 +372,7 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, struct nvkm_memory **pmemory) { struct gk20a_instmem *imem = gk20a_instmem(base); - struct gk20a_instobj *node; + struct gk20a_instobj *node = NULL; struct nvkm_subdev *subdev = &imem->base.subdev; int ret; @@ -389,9 +389,9 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, else ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT, align, &node); + *pmemory = node ? &node->memory : NULL; if (ret) return ret; - *pmemory = &node->memory; nvkm_memory_ctor(&gk20a_instobj_func, &node->memory); node->imem = imem; @@ -407,29 +407,31 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, return 0; } -static int -gk20a_instmem_fini(struct nvkm_object *object, bool suspend) +static void +gk20a_instmem_fini(struct nvkm_instmem *base) { - struct gk20a_instmem *imem = (void *)object; - imem->addr = ~0ULL; - return nvkm_instmem_fini(&imem->base, suspend); + gk20a_instmem(base)->addr = ~0ULL; } -static int -gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_instmem_func +gk20a_instmem = { + .fini = gk20a_instmem_fini, + .memory_new = gk20a_instobj_new, + .persistent = true, + .zero = false, +}; + +int +gk20a_instmem_new(struct nvkm_device *device, int index, + struct nvkm_instmem **pimem) { - struct nvkm_device *device = (void *)parent; struct gk20a_instmem *imem; - int ret; - - ret = nvkm_instmem_create(parent, engine, oclass, &imem); - *pobject = nv_object(imem); - if (ret) - return ret; + if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) + return -ENOMEM; + nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base); spin_lock_init(&imem->lock); + *pimem = &imem->base; if (device->gpu->iommu.domain) { imem->domain = device->gpu->iommu.domain; @@ -454,17 +456,3 @@ gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } - -struct nvkm_oclass * -gk20a_instmem_oclass = &(struct nvkm_instmem_impl) { - .base.handle = NV_SUBDEV(INSTMEM, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk20a_instmem_ctor, - .dtor = _nvkm_instmem_dtor, - .init = _nvkm_instmem_init, - .fini = gk20a_instmem_fini, - }, - .memory_new = gk20a_instobj_new, - .persistent = true, - .zero = false, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c index 1df45273bff7..6133c8bb2d42 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c @@ -150,40 +150,13 @@ nv04_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data) nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); } -static void -nv04_instmem_dtor(struct nvkm_object *object) -{ - struct nv04_instmem *imem = (void *)object; - nvkm_memory_del(&imem->base.ramfc); - nvkm_memory_del(&imem->base.ramro); - nvkm_ramht_del(&imem->base.ramht); - nvkm_memory_del(&imem->base.vbios); - nvkm_mm_fini(&imem->heap); - nvkm_instmem_destroy(&imem->base); -} - -static const struct nvkm_instmem_func -nv04_instmem_func = { - .rd32 = nv04_instmem_rd32, - .wr32 = nv04_instmem_wr32, -}; - static int -nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_instmem_oneinit(struct nvkm_instmem *base) { - struct nvkm_device *device = (void *)parent; - struct nv04_instmem *imem; + struct nv04_instmem *imem = nv04_instmem(base); + struct nvkm_device *device = imem->base.subdev.device; int ret; - ret = nvkm_instmem_create(parent, engine, oclass, &imem); - *pobject = nv_object(imem); - if (ret) - return ret; - - imem->base.func = &nv04_instmem_func; - /* PRAMIN aperture maps over the end of VRAM, reserve it */ imem->base.reserved = 512 * 1024; @@ -217,16 +190,38 @@ nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } -struct nvkm_oclass * -nv04_instmem_oclass = &(struct nvkm_instmem_impl) { - .base.handle = NV_SUBDEV(INSTMEM, 0x04), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_instmem_ctor, - .dtor = nv04_instmem_dtor, - .init = _nvkm_instmem_init, - .fini = _nvkm_instmem_fini, - }, +static void * +nv04_instmem_dtor(struct nvkm_instmem *base) +{ + struct nv04_instmem *imem = nv04_instmem(base); + nvkm_memory_del(&imem->base.ramfc); + nvkm_memory_del(&imem->base.ramro); + nvkm_ramht_del(&imem->base.ramht); + nvkm_memory_del(&imem->base.vbios); + nvkm_mm_fini(&imem->heap); + return imem; +} + +static const struct nvkm_instmem_func +nv04_instmem = { + .dtor = nv04_instmem_dtor, + .oneinit = nv04_instmem_oneinit, + .rd32 = nv04_instmem_rd32, + .wr32 = nv04_instmem_wr32, .memory_new = nv04_instobj_new, .persistent = false, .zero = false, -}.base; +}; + +int +nv04_instmem_new(struct nvkm_device *device, int index, + struct nvkm_instmem **pimem) +{ + struct nv04_instmem *imem; + + if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) + return -ENOMEM; + nvkm_instmem_ctor(&nv04_instmem, device, index, &imem->base); + *pimem = &imem->base; + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index 8e7a11503c09..a170ff9b32e7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -138,67 +138,23 @@ nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, *****************************************************************************/ static u32 -nv40_instmem_rd32(struct nvkm_instmem *obj, u32 addr) +nv40_instmem_rd32(struct nvkm_instmem *base, u32 addr) { - struct nv40_instmem *imem = container_of(obj, typeof(*imem), base); - return ioread32_native(imem->iomem + addr); + return ioread32_native(nv40_instmem(base)->iomem + addr); } static void -nv40_instmem_wr32(struct nvkm_instmem *obj, u32 addr, u32 data) +nv40_instmem_wr32(struct nvkm_instmem *base, u32 addr, u32 data) { - struct nv40_instmem *imem = container_of(obj, typeof(*imem), base); - iowrite32_native(data, imem->iomem + addr); + iowrite32_native(data, nv40_instmem(base)->iomem + addr); } -static void -nv40_instmem_dtor(struct nvkm_object *object) -{ - struct nv40_instmem *imem = (void *)object; - nvkm_memory_del(&imem->base.ramfc); - nvkm_memory_del(&imem->base.ramro); - nvkm_ramht_del(&imem->base.ramht); - nvkm_memory_del(&imem->base.vbios); - nvkm_mm_fini(&imem->heap); - if (imem->iomem) - iounmap(imem->iomem); - nvkm_instmem_destroy(&imem->base); -} - -static const struct nvkm_instmem_func -nv40_instmem_func = { - .rd32 = nv40_instmem_rd32, - .wr32 = nv40_instmem_wr32, -}; - static int -nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv40_instmem_oneinit(struct nvkm_instmem *base) { - struct nvkm_device *device = (void *)parent; - struct nv40_instmem *imem; - int ret, bar, vs; - - ret = nvkm_instmem_create(parent, engine, oclass, &imem); - *pobject = nv_object(imem); - if (ret) - return ret; - - imem->base.func = &nv40_instmem_func; - - /* map bar */ - if (nv_device_resource_len(device, 2)) - bar = 2; - else - bar = 3; - - imem->iomem = ioremap(nv_device_resource_start(device, bar), - nv_device_resource_len(device, bar)); - if (!imem->iomem) { - nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n"); - return -EFAULT; - } + struct nv40_instmem *imem = nv40_instmem(base); + struct nvkm_device *device = imem->base.subdev.device; + int ret, vs; /* PRAMIN aperture maps over the end of vram, reserve enough space * to fit graphics contexts for every channel, the magics come @@ -207,13 +163,12 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8); if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs; else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs; - else if (nv44_gr_class(imem)) imem->base.reserved = 0x4980 * vs; + else if (nv44_gr_class(device)) imem->base.reserved = 0x4980 * vs; else imem->base.reserved = 0x4a40 * vs; imem->base.reserved += 16 * 1024; imem->base.reserved *= 32; /* per-channel */ imem->base.reserved += 512 * 1024; /* pci(e)gart table */ imem->base.reserved += 512 * 1024; /* object storage */ - imem->base.reserved = round_up(imem->base.reserved, 4096); ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1); @@ -250,16 +205,55 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, return 0; } -struct nvkm_oclass * -nv40_instmem_oclass = &(struct nvkm_instmem_impl) { - .base.handle = NV_SUBDEV(INSTMEM, 0x40), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv40_instmem_ctor, - .dtor = nv40_instmem_dtor, - .init = _nvkm_instmem_init, - .fini = _nvkm_instmem_fini, - }, +static void * +nv40_instmem_dtor(struct nvkm_instmem *base) +{ + struct nv40_instmem *imem = nv40_instmem(base); + nvkm_memory_del(&imem->base.ramfc); + nvkm_memory_del(&imem->base.ramro); + nvkm_ramht_del(&imem->base.ramht); + nvkm_memory_del(&imem->base.vbios); + nvkm_mm_fini(&imem->heap); + if (imem->iomem) + iounmap(imem->iomem); + return imem; +} + +static const struct nvkm_instmem_func +nv40_instmem = { + .dtor = nv40_instmem_dtor, + .oneinit = nv40_instmem_oneinit, + .rd32 = nv40_instmem_rd32, + .wr32 = nv40_instmem_wr32, .memory_new = nv40_instobj_new, .persistent = false, .zero = false, -}.base; +}; + +int +nv40_instmem_new(struct nvkm_device *device, int index, + struct nvkm_instmem **pimem) +{ + struct nv40_instmem *imem; + int bar; + + if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) + return -ENOMEM; + nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base); + *pimem = &imem->base; + + /* map bar */ + if (nv_device_resource_len(device, 2)) + bar = 2; + else + bar = 3; + + imem->iomem = ioremap(nv_device_resource_start(device, bar), + nv_device_resource_len(device, bar)); + if (!imem->iomem) { + nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n"); + return -EFAULT; + } + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index af236f8e4ddc..ec5020e3fc42 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -220,41 +220,30 @@ nv50_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, * instmem subdev implementation *****************************************************************************/ -static int -nv50_instmem_fini(struct nvkm_object *object, bool suspend) +static void +nv50_instmem_fini(struct nvkm_instmem *base) { - struct nv50_instmem *imem = (void *)object; - imem->addr = ~0ULL; - return nvkm_instmem_fini(&imem->base, suspend); + nv50_instmem(base)->addr = ~0ULL; } -static int -nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_instmem_func +nv50_instmem = { + .fini = nv50_instmem_fini, + .memory_new = nv50_instobj_new, + .persistent = false, + .zero = false, +}; + +int +nv50_instmem_new(struct nvkm_device *device, int index, + struct nvkm_instmem **pimem) { struct nv50_instmem *imem; - int ret; - - ret = nvkm_instmem_create(parent, engine, oclass, &imem); - *pobject = nv_object(imem); - if (ret) - return ret; + if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL))) + return -ENOMEM; + nvkm_instmem_ctor(&nv50_instmem, device, index, &imem->base); spin_lock_init(&imem->lock); + *pimem = &imem->base; return 0; } - -struct nvkm_oclass * -nv50_instmem_oclass = &(struct nvkm_instmem_impl) { - .base.handle = NV_SUBDEV(INSTMEM, 0x50), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_instmem_ctor, - .dtor = _nvkm_instmem_dtor, - .init = _nvkm_instmem_init, - .fini = nv50_instmem_fini, - }, - .memory_new = nv50_instobj_new, - .persistent = false, - .zero = false, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h index 2b6d73005767..ace4471864a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h @@ -1,31 +1,20 @@ #ifndef __NVKM_INSTMEM_PRIV_H__ #define __NVKM_INSTMEM_PRIV_H__ +#define nvkm_instmem(p) container_of((p), struct nvkm_instmem, subdev) #include -struct nvkm_instmem_impl { - struct nvkm_oclass base; +struct nvkm_instmem_func { + void *(*dtor)(struct nvkm_instmem *); + int (*oneinit)(struct nvkm_instmem *); + void (*fini)(struct nvkm_instmem *); + u32 (*rd32)(struct nvkm_instmem *, u32 addr); + void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data); int (*memory_new)(struct nvkm_instmem *, u32 size, u32 align, bool zero, struct nvkm_memory **); bool persistent; bool zero; }; -#define nvkm_instmem_create(p,e,o,d) \ - nvkm_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nvkm_instmem_destroy(p) \ - nvkm_subdev_destroy(&(p)->subdev) -#define nvkm_instmem_init(p) ({ \ - struct nvkm_instmem *_imem = (p); \ - _nvkm_instmem_init(nv_object(_imem)); \ -}) -#define nvkm_instmem_fini(p,s) ({ \ - struct nvkm_instmem *_imem = (p); \ - _nvkm_instmem_fini(nv_object(_imem), (s)); \ -}) - -int nvkm_instmem_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); -#define _nvkm_instmem_dtor _nvkm_subdev_dtor -int _nvkm_instmem_init(struct nvkm_object *); -int _nvkm_instmem_fini(struct nvkm_object *, bool); +void nvkm_instmem_ctor(const struct nvkm_instmem_func *, struct nvkm_device *, + int index, struct nvkm_instmem *); #endif -- cgit v1.2.3 From 70bc7182cbf1bb07e414bbb553890ddf1b540264 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:21 +1000 Subject: drm/nouveau/ltc: convert to new-style nvkm_subdev Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h | 35 +++--- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 42 +++---- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 10 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c | 126 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c | 124 ++++++++------------ drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c | 34 +++--- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c | 101 +++++++---------- drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h | 76 +++---------- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c | 4 +- 13 files changed, 235 insertions(+), 342 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index e8234e5b735c..c773b5e958b4 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -1,31 +1,36 @@ #ifndef __NVKM_LTC_H__ #define __NVKM_LTC_H__ #include -struct nvkm_mm_node; +#include #define NVKM_LTC_MAX_ZBC_CNT 16 struct nvkm_ltc { + const struct nvkm_ltc_func *func; struct nvkm_subdev subdev; - int (*tags_alloc)(struct nvkm_ltc *, u32 count, - struct nvkm_mm_node **); - void (*tags_free)(struct nvkm_ltc *, struct nvkm_mm_node **); - void (*tags_clear)(struct nvkm_ltc *, u32 first, u32 count); + u32 ltc_nr; + u32 lts_nr; + + u32 num_tags; + u32 tag_base; + struct nvkm_mm tags; + struct nvkm_mm_node *tag_ram; int zbc_min; int zbc_max; - int (*zbc_color_get)(struct nvkm_ltc *, int index, const u32[4]); - int (*zbc_depth_get)(struct nvkm_ltc *, int index, const u32); + u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4]; + u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT]; }; -static inline struct nvkm_ltc * -nvkm_ltc(void *obj) -{ - return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_LTC); -} +int nvkm_ltc_tags_alloc(struct nvkm_ltc *, u32 count, struct nvkm_mm_node **); +void nvkm_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **); +void nvkm_ltc_tags_clear(struct nvkm_ltc *, u32 first, u32 count); + +int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]); +int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32); -extern struct nvkm_oclass *gf100_ltc_oclass; -extern struct nvkm_oclass *gk104_ltc_oclass; -extern struct nvkm_oclass *gm107_ltc_oclass; +int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 3b83f17b3a23..d1ee594dff56 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1300,7 +1300,7 @@ nvc0_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1335,7 +1335,7 @@ nvc1_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1369,7 +1369,7 @@ nvc3_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1403,7 +1403,7 @@ nvc4_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1438,7 +1438,7 @@ nvc8_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1473,7 +1473,7 @@ nvce_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1508,7 +1508,7 @@ nvcf_chipset = { .i2c = g94_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1542,7 +1542,7 @@ nvd7_chipset = { .i2c = gf117_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1574,7 +1574,7 @@ nvd9_chipset = { .i2c = gf119_i2c_new, .ibus = gf100_ibus_new, .imem = nv50_instmem_new, -// .ltc = gf100_ltc_new, + .ltc = gf100_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1608,7 +1608,7 @@ nve4_chipset = { .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1644,7 +1644,7 @@ nve6_chipset = { .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1680,7 +1680,7 @@ nve7_chipset = { .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1712,7 +1712,7 @@ nvea_chipset = { .fuse = gf100_fuse_new, .ibus = gk20a_ibus_new, .imem = gk20a_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .pmu = gk20a_pmu_new, @@ -1740,7 +1740,7 @@ nvf0_chipset = { .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1776,7 +1776,7 @@ nvf1_chipset = { .i2c = gf119_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1812,7 +1812,7 @@ nv106_chipset = { .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1847,7 +1847,7 @@ nv108_chipset = { .i2c = gk104_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gk104_ltc_new, + .ltc = gk104_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1882,7 +1882,7 @@ nv117_chipset = { .i2c = gf119_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gm107_ltc_new, + .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1911,7 +1911,7 @@ nv124_chipset = { .i2c = gm204_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gm107_ltc_new, + .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1940,7 +1940,7 @@ nv126_chipset = { .i2c = gm204_i2c_new, .ibus = gk104_ibus_new, .imem = nv50_instmem_new, -// .ltc = gm107_ltc_new, + .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, @@ -1965,7 +1965,7 @@ nv12b_chipset = { .fuse = gm107_fuse_new, .ibus = gk20a_ibus_new, .imem = gk20a_instmem_new, -// .ltc = gm107_ltc_new, + .ltc = gm107_ltc_new, // .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index 8f9d871b545f..e0b57ed658f5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -32,7 +32,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -53,7 +52,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -74,7 +72,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -94,7 +91,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -115,7 +111,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -135,7 +130,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -155,7 +149,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -176,7 +169,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -196,7 +188,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index dcb0f6db213d..115931cfe18a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -32,7 +32,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -54,7 +53,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -76,7 +74,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -96,7 +93,6 @@ gk104_identify(struct nvkm_device *device) case 0xea: device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; @@ -112,7 +108,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -134,7 +129,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -156,7 +150,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -177,7 +170,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 158af1f8799e..a3c87b26dd9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -32,7 +32,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; @@ -64,7 +63,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 @@ -93,7 +91,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 @@ -118,7 +115,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 7917d141fcb0..2f22af2fb533 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -58,7 +58,7 @@ static int gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, const u32 ds[4], const u32 l2[4]) { - struct nvkm_ltc *ltc = nvkm_ltc(gr); + struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; int zbc = -ENOSPC, i; for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { @@ -85,7 +85,7 @@ gf100_gr_zbc_color_get(struct gf100_gr *gr, int format, memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); gr->zbc_color[zbc].format = format; - ltc->zbc_color_get(ltc, zbc, l2); + nvkm_ltc_zbc_color_get(ltc, zbc, l2); gf100_gr_zbc_clear_color(gr, zbc); return zbc; } @@ -105,7 +105,7 @@ static int gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, const u32 ds, const u32 l2) { - struct nvkm_ltc *ltc = nvkm_ltc(gr); + struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; int zbc = -ENOSPC, i; for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { @@ -130,7 +130,7 @@ gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format, gr->zbc_depth[zbc].format = format; gr->zbc_depth[zbc].ds = ds; gr->zbc_depth[zbc].l2 = l2; - ltc->zbc_depth_get(ltc, zbc, l2); + nvkm_ltc_zbc_depth_get(ltc, zbc, l2); gf100_gr_zbc_clear_depth(gr, zbc); return zbc; } @@ -680,7 +680,7 @@ gf100_gr_zbc_init(struct gf100_gr *gr) 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; - struct nvkm_ltc *ltc = nvkm_ltc(gr); + struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; int index; if (!gr->zbc_color[0].format) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index 71902b64ffbc..772425ca5a9e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -434,7 +434,7 @@ gf100_ram_put(struct nvkm_ram *ram, struct nvkm_mem **pmem) mutex_lock(&ram->fb->subdev.mutex); if (mem->tag) - ltc->tags_free(ltc, &mem->tag); + nvkm_ltc_tags_free(ltc, &mem->tag); __nv50_ram_put(ram, mem); mutex_unlock(&ram->fb->subdev.mutex); @@ -472,7 +472,7 @@ gf100_ram_get(struct nvkm_ram *ram, u64 size, u32 align, u32 ncmin, /* compression only works with lpages */ if (align == (1 << (17 - NVKM_RAM_MM_SHIFT))) { int n = size >> 5; - ltc->tags_alloc(ltc, n, &mem->tag); + nvkm_ltc_tags_alloc(ltc, n, &mem->tag); } if (unlikely(!mem->tag)) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c index d0af1aec0fc6..930d25b6e63c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c @@ -23,102 +23,110 @@ */ #include "priv.h" -static int -nvkm_ltc_tags_alloc(struct nvkm_ltc *obj, u32 n, struct nvkm_mm_node **pnode) -{ - struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base); - int ret; +#include - ret = nvkm_mm_head(<c->tags, 0, 1, n, n, 1, pnode); +int +nvkm_ltc_tags_alloc(struct nvkm_ltc *ltc, u32 n, struct nvkm_mm_node **pnode) +{ + int ret = nvkm_mm_head(<c->tags, 0, 1, n, n, 1, pnode); if (ret) *pnode = NULL; - return ret; } -static void -nvkm_ltc_tags_free(struct nvkm_ltc *obj, struct nvkm_mm_node **pnode) +void +nvkm_ltc_tags_free(struct nvkm_ltc *ltc, struct nvkm_mm_node **pnode) { - struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base); nvkm_mm_free(<c->tags, pnode); } -static void -nvkm_ltc_tags_clear(struct nvkm_ltc *obj, u32 first, u32 count) +void +nvkm_ltc_tags_clear(struct nvkm_ltc *ltc, u32 first, u32 count) { - struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base); - const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); const u32 limit = first + count - 1; BUG_ON((first > limit) || (limit >= ltc->num_tags)); - impl->cbc_clear(ltc, first, limit); - impl->cbc_wait(ltc); + ltc->func->cbc_clear(ltc, first, limit); + ltc->func->cbc_wait(ltc); } -static int -nvkm_ltc_zbc_color_get(struct nvkm_ltc *obj, int index, const u32 color[4]) +int +nvkm_ltc_zbc_color_get(struct nvkm_ltc *ltc, int index, const u32 color[4]) { - struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base); - const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); memcpy(ltc->zbc_color[index], color, sizeof(ltc->zbc_color[index])); - impl->zbc_clear_color(ltc, index, color); + ltc->func->zbc_clear_color(ltc, index, color); return index; } -static int -nvkm_ltc_zbc_depth_get(struct nvkm_ltc *obj, int index, const u32 depth) +int +nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth) { - struct nvkm_ltc_priv *ltc = container_of(obj, typeof(*ltc), base); - const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); ltc->zbc_depth[index] = depth; - impl->zbc_clear_depth(ltc, index, depth); + ltc->func->zbc_clear_depth(ltc, index, depth); return index; } -int -_nvkm_ltc_init(struct nvkm_object *object) +static void +nvkm_ltc_intr(struct nvkm_subdev *subdev) { - struct nvkm_ltc_priv *ltc = (void *)object; - const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object); - int ret, i; + struct nvkm_ltc *ltc = nvkm_ltc(subdev); + ltc->func->intr(ltc); +} - ret = nvkm_subdev_init_old(<c->base.subdev); - if (ret) - return ret; +static int +nvkm_ltc_oneinit(struct nvkm_subdev *subdev) +{ + struct nvkm_ltc *ltc = nvkm_ltc(subdev); + return ltc->func->oneinit(ltc); +} + +static int +nvkm_ltc_init(struct nvkm_subdev *subdev) +{ + struct nvkm_ltc *ltc = nvkm_ltc(subdev); + int i; - for (i = ltc->base.zbc_min; i <= ltc->base.zbc_max; i++) { - impl->zbc_clear_color(ltc, i, ltc->zbc_color[i]); - impl->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]); + for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { + ltc->func->zbc_clear_color(ltc, i, ltc->zbc_color[i]); + ltc->func->zbc_clear_depth(ltc, i, ltc->zbc_depth[i]); } + ltc->func->init(ltc); return 0; } +static void * +nvkm_ltc_dtor(struct nvkm_subdev *subdev) +{ + struct nvkm_ltc *ltc = nvkm_ltc(subdev); + struct nvkm_ram *ram = ltc->subdev.device->fb->ram; + nvkm_mm_fini(<c->tags); + if (ram) + nvkm_mm_free(&ram->vram, <c->tag_ram); + return ltc; +} + +static const struct nvkm_subdev_func +nvkm_ltc = { + .dtor = nvkm_ltc_dtor, + .oneinit = nvkm_ltc_oneinit, + .init = nvkm_ltc_init, + .intr = nvkm_ltc_intr, +}; + int -nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) +nvkm_ltc_new_(const struct nvkm_ltc_func *func, struct nvkm_device *device, + int index, struct nvkm_ltc **pltc) { - const struct nvkm_ltc_impl *impl = (void *)oclass; - struct nvkm_ltc_priv *ltc; - int ret; + struct nvkm_ltc *ltc; - ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG", - "l2c", length, pobject); - ltc = *pobject; - if (ret) - return ret; - - memset(ltc->zbc_color, 0x00, sizeof(ltc->zbc_color)); - memset(ltc->zbc_depth, 0x00, sizeof(ltc->zbc_depth)); - - ltc->base.subdev.intr = impl->intr; - ltc->base.tags_alloc = nvkm_ltc_tags_alloc; - ltc->base.tags_free = nvkm_ltc_tags_free; - ltc->base.tags_clear = nvkm_ltc_tags_clear; - ltc->base.zbc_min = 1; /* reserve 0 for disabled */ - ltc->base.zbc_max = min(impl->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1; - ltc->base.zbc_color_get = nvkm_ltc_zbc_color_get; - ltc->base.zbc_depth_get = nvkm_ltc_zbc_depth_get; + if (!(ltc = *pltc = kzalloc(sizeof(*ltc), GFP_KERNEL))) + return -ENOMEM; + + nvkm_subdev_ctor(&nvkm_ltc, device, index, 0, <c->subdev); + ltc->func = func; + ltc->zbc_min = 1; /* reserve 0 for disabled */ + ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index 5cb7604beeb6..45ac765b753e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -28,18 +28,18 @@ #include void -gf100_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit) +gf100_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; nvkm_wr32(device, 0x17e8cc, start); nvkm_wr32(device, 0x17e8d0, limit); nvkm_wr32(device, 0x17e8c8, 0x00000004); } void -gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) +gf100_ltc_cbc_wait(struct nvkm_ltc *ltc) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; int c, s; for (c = 0; c < ltc->ltc_nr; c++) { for (s = 0; s < ltc->lts_nr; s++) { @@ -53,9 +53,9 @@ gf100_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) } void -gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) +gf100_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4]) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; nvkm_mask(device, 0x17ea44, 0x0000000f, i); nvkm_wr32(device, 0x17ea48, color[0]); nvkm_wr32(device, 0x17ea4c, color[1]); @@ -64,9 +64,9 @@ gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) } void -gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth) +gf100_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; nvkm_mask(device, 0x17ea44, 0x0000000f, i); nvkm_wr32(device, 0x17ea58, depth); } @@ -90,9 +90,9 @@ gf100_ltc_lts_intr_name[] = { }; static void -gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s) +gf100_ltc_lts_intr(struct nvkm_ltc *ltc, int c, int s) { - struct nvkm_subdev *subdev = <c->base.subdev; + struct nvkm_subdev *subdev = <c->subdev; struct nvkm_device *device = subdev->device; u32 base = 0x141000 + (c * 0x2000) + (s * 0x400); u32 intr = nvkm_rd32(device, base + 0x020); @@ -108,10 +108,9 @@ gf100_ltc_lts_intr(struct nvkm_ltc_priv *ltc, int c, int s) } void -gf100_ltc_intr(struct nvkm_subdev *subdev) +gf100_ltc_intr(struct nvkm_ltc *ltc) { - struct nvkm_ltc_priv *ltc = (void *)subdev; - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; u32 mask; mask = nvkm_rd32(device, 0x00017c); @@ -123,44 +122,12 @@ gf100_ltc_intr(struct nvkm_subdev *subdev) } } -static int -gf100_ltc_init(struct nvkm_object *object) -{ - struct nvkm_ltc_priv *ltc = (void *)object; - struct nvkm_device *device = ltc->base.subdev.device; - u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); - int ret; - - ret = nvkm_ltc_init(ltc); - if (ret) - return ret; - - nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ - nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr); - nvkm_wr32(device, 0x17e8d4, ltc->tag_base); - nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); - return 0; -} - -void -gf100_ltc_dtor(struct nvkm_object *object) -{ - struct nvkm_ltc_priv *ltc = (void *)object; - struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram; - - nvkm_mm_fini(<c->tags); - if (ram) - nvkm_mm_free(&ram->vram, <c->tag_ram); - - nvkm_ltc_destroy(ltc); -} - /* TODO: Figure out tag memory details and drop the over-cautious allocation. */ int -gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *ltc) +gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *ltc) { - struct nvkm_ram *ram = ltc->base.subdev.device->fb->ram; + struct nvkm_ram *ram = ltc->subdev.device->fb->ram; u32 tag_size, tag_margin, tag_align; int ret; @@ -205,54 +172,53 @@ gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *ltc) } mm_init: - ret = nvkm_mm_init(<c->tags, 0, ltc->num_tags, 1); - return ret; + return nvkm_mm_init(<c->tags, 0, ltc->num_tags, 1); } int -gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +gf100_ltc_oneinit(struct nvkm_ltc *ltc) { - struct nvkm_device *device = (void *)parent; - struct nvkm_ltc_priv *ltc; - u32 parts, mask; - int ret, i; - - ret = nvkm_ltc_create(parent, engine, oclass, <c); - *pobject = nv_object(ltc); - if (ret) - return ret; + struct nvkm_device *device = ltc->subdev.device; + const u32 parts = nvkm_rd32(device, 0x022438); + const u32 mask = nvkm_rd32(device, 0x022554); + const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28; + int i; - parts = nvkm_rd32(device, 0x022438); - mask = nvkm_rd32(device, 0x022554); for (i = 0; i < parts; i++) { if (!(mask & (1 << i))) ltc->ltc_nr++; } - ltc->lts_nr = nvkm_rd32(device, 0x17e8dc) >> 28; + ltc->lts_nr = slice; + + return gf100_ltc_oneinit_tag_ram(ltc); +} - ret = gf100_ltc_init_tag_ram(ltc); - if (ret) - return ret; +static void +gf100_ltc_init(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); - nv_subdev(ltc)->intr = gf100_ltc_intr; - return 0; + nvkm_mask(device, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ + nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr); + nvkm_wr32(device, 0x17e8d4, ltc->tag_base); + nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); } -struct nvkm_oclass * -gf100_ltc_oclass = &(struct nvkm_ltc_impl) { - .base.handle = NV_SUBDEV(LTC, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_ltc_ctor, - .dtor = gf100_ltc_dtor, - .init = gf100_ltc_init, - .fini = _nvkm_ltc_fini, - }, +static const struct nvkm_ltc_func +gf100_ltc = { + .oneinit = gf100_ltc_oneinit, + .init = gf100_ltc_init, .intr = gf100_ltc_intr, .cbc_clear = gf100_ltc_cbc_clear, .cbc_wait = gf100_ltc_cbc_wait, .zbc = 16, .zbc_clear_color = gf100_ltc_zbc_clear_color, .zbc_clear_depth = gf100_ltc_zbc_clear_depth, -}.base; +}; + +int +gf100_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +{ + return nvkm_ltc_new_(&gf100_ltc, device, index, pltc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c index a1f97d2ec36f..839e6b4c597b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c @@ -23,38 +23,32 @@ */ #include "priv.h" -static int -gk104_ltc_init(struct nvkm_object *object) +static void +gk104_ltc_init(struct nvkm_ltc *ltc) { - struct nvkm_ltc_priv *ltc = (void *)object; - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); - int ret; - - ret = nvkm_ltc_init(ltc); - if (ret) - return ret; nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr); nvkm_wr32(device, 0x17e000, ltc->ltc_nr); nvkm_wr32(device, 0x17e8d4, ltc->tag_base); nvkm_mask(device, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); - return 0; } -struct nvkm_oclass * -gk104_ltc_oclass = &(struct nvkm_ltc_impl) { - .base.handle = NV_SUBDEV(LTC, 0xe4), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_ltc_ctor, - .dtor = gf100_ltc_dtor, - .init = gk104_ltc_init, - .fini = _nvkm_ltc_fini, - }, +static const struct nvkm_ltc_func +gk104_ltc = { + .oneinit = gf100_ltc_oneinit, + .init = gk104_ltc_init, .intr = gf100_ltc_intr, .cbc_clear = gf100_ltc_cbc_clear, .cbc_wait = gf100_ltc_cbc_wait, .zbc = 16, .zbc_clear_color = gf100_ltc_zbc_clear_color, .zbc_clear_depth = gf100_ltc_zbc_clear_depth, -}.base; +}; + +int +gk104_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +{ + return nvkm_ltc_new_(&gk104_ltc, device, index, pltc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index 431acbef6bb7..389331bb63ba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -27,18 +27,18 @@ #include static void -gm107_ltc_cbc_clear(struct nvkm_ltc_priv *ltc, u32 start, u32 limit) +gm107_ltc_cbc_clear(struct nvkm_ltc *ltc, u32 start, u32 limit) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; nvkm_wr32(device, 0x17e270, start); nvkm_wr32(device, 0x17e274, limit); nvkm_wr32(device, 0x17e26c, 0x00000004); } static void -gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) +gm107_ltc_cbc_wait(struct nvkm_ltc *ltc) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; int c, s; for (c = 0; c < ltc->ltc_nr; c++) { for (s = 0; s < ltc->lts_nr; s++) { @@ -52,9 +52,9 @@ gm107_ltc_cbc_wait(struct nvkm_ltc_priv *ltc) } static void -gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) +gm107_ltc_zbc_clear_color(struct nvkm_ltc *ltc, int i, const u32 color[4]) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; nvkm_mask(device, 0x17e338, 0x0000000f, i); nvkm_wr32(device, 0x17e33c, color[0]); nvkm_wr32(device, 0x17e340, color[1]); @@ -63,17 +63,17 @@ gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *ltc, int i, const u32 color[4]) } static void -gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *ltc, int i, const u32 depth) +gm107_ltc_zbc_clear_depth(struct nvkm_ltc *ltc, int i, const u32 depth) { - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; nvkm_mask(device, 0x17e338, 0x0000000f, i); nvkm_wr32(device, 0x17e34c, depth); } static void -gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s) +gm107_ltc_lts_isr(struct nvkm_ltc *ltc, int c, int s) { - struct nvkm_subdev *subdev = <c->base.subdev; + struct nvkm_subdev *subdev = <c->subdev; struct nvkm_device *device = subdev->device; u32 base = 0x140000 + (c * 0x2000) + (s * 0x400); u32 stat = nvkm_rd32(device, base + 0x00c); @@ -85,10 +85,9 @@ gm107_ltc_lts_isr(struct nvkm_ltc_priv *ltc, int c, int s) } static void -gm107_ltc_intr(struct nvkm_subdev *subdev) +gm107_ltc_intr(struct nvkm_ltc *ltc) { - struct nvkm_ltc_priv *ltc = (void *)subdev; - struct nvkm_device *device = ltc->base.subdev.device; + struct nvkm_device *device = ltc->subdev.device; u32 mask; mask = nvkm_rd32(device, 0x00017c); @@ -101,66 +100,48 @@ gm107_ltc_intr(struct nvkm_subdev *subdev) } static int -gm107_ltc_init(struct nvkm_object *object) +gm107_ltc_oneinit(struct nvkm_ltc *ltc) { - struct nvkm_ltc_priv *ltc = (void *)object; - struct nvkm_device *device = ltc->base.subdev.device; - u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); - int ret; - - ret = nvkm_ltc_init(ltc); - if (ret) - return ret; - - nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); - nvkm_wr32(device, 0x17e278, ltc->tag_base); - nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); - return 0; -} + struct nvkm_device *device = ltc->subdev.device; + const u32 parts = nvkm_rd32(device, 0x022438); + const u32 mask = nvkm_rd32(device, 0x021c14); + const u32 slice = nvkm_rd32(device, 0x17e280) >> 28; + int i; -static int -gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = (void *)parent; - struct nvkm_ltc_priv *ltc; - u32 parts, mask; - int ret, i; - - ret = nvkm_ltc_create(parent, engine, oclass, <c); - *pobject = nv_object(ltc); - if (ret) - return ret; - - parts = nvkm_rd32(device, 0x022438); - mask = nvkm_rd32(device, 0x021c14); for (i = 0; i < parts; i++) { if (!(mask & (1 << i))) ltc->ltc_nr++; } - ltc->lts_nr = nvkm_rd32(device, 0x17e280) >> 28; + ltc->lts_nr = slice; + + return gf100_ltc_oneinit_tag_ram(ltc); +} - ret = gf100_ltc_init_tag_ram(ltc); - if (ret) - return ret; +static void +gm107_ltc_init(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + u32 lpg128 = !(nvkm_rd32(device, 0x100c80) & 0x00000001); - return 0; + nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); + nvkm_wr32(device, 0x17e278, ltc->tag_base); + nvkm_mask(device, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); } -struct nvkm_oclass * -gm107_ltc_oclass = &(struct nvkm_ltc_impl) { - .base.handle = NV_SUBDEV(LTC, 0xff), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gm107_ltc_ctor, - .dtor = gf100_ltc_dtor, - .init = gm107_ltc_init, - .fini = _nvkm_ltc_fini, - }, +static const struct nvkm_ltc_func +gm107_ltc = { + .oneinit = gm107_ltc_oneinit, + .init = gm107_ltc_init, .intr = gm107_ltc_intr, .cbc_clear = gm107_ltc_cbc_clear, .cbc_wait = gm107_ltc_cbc_wait, .zbc = 16, .zbc_clear_color = gm107_ltc_zbc_clear_color, .zbc_clear_depth = gm107_ltc_zbc_clear_depth, -}.base; +}; + +int +gm107_ltc_new(struct nvkm_device *device, int index, struct nvkm_ltc **pltc) +{ + return nvkm_ltc_new_(&gm107_ltc, device, index, pltc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 0544288b0d1d..4e05037cc99f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -1,69 +1,29 @@ #ifndef __NVKM_LTC_PRIV_H__ #define __NVKM_LTC_PRIV_H__ +#define nvkm_ltc(p) container_of((p), struct nvkm_ltc, subdev) #include -#include -struct nvkm_fb; +int nvkm_ltc_new_(const struct nvkm_ltc_func *, struct nvkm_device *, + int index, struct nvkm_ltc **); -struct nvkm_ltc_priv { - struct nvkm_ltc base; - u32 ltc_nr; - u32 lts_nr; +struct nvkm_ltc_func { + int (*oneinit)(struct nvkm_ltc *); + void (*init)(struct nvkm_ltc *); + void (*intr)(struct nvkm_ltc *); - u32 num_tags; - u32 tag_base; - struct nvkm_mm tags; - struct nvkm_mm_node *tag_ram; - - u32 zbc_color[NVKM_LTC_MAX_ZBC_CNT][4]; - u32 zbc_depth[NVKM_LTC_MAX_ZBC_CNT]; -}; - -#define nvkm_ltc_create(p,e,o,d) \ - nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nvkm_ltc_destroy(p) ({ \ - struct nvkm_ltc_priv *_priv = (p); \ - _nvkm_ltc_dtor(nv_object(_priv)); \ -}) -#define nvkm_ltc_init(p) ({ \ - struct nvkm_ltc_priv *_priv = (p); \ - _nvkm_ltc_init(nv_object(_priv)); \ -}) -#define nvkm_ltc_fini(p,s) ({ \ - struct nvkm_ltc_priv *_priv = (p); \ - _nvkm_ltc_fini(nv_object(_priv), (s)); \ -}) - -int nvkm_ltc_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); - -#define _nvkm_ltc_dtor _nvkm_subdev_dtor -int _nvkm_ltc_init(struct nvkm_object *); -#define _nvkm_ltc_fini _nvkm_subdev_fini - -int gf100_ltc_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void gf100_ltc_dtor(struct nvkm_object *); -int gf100_ltc_init_tag_ram(struct nvkm_ltc_priv *); -int gf100_ltc_tags_alloc(struct nvkm_ltc *, u32, struct nvkm_mm_node **); -void gf100_ltc_tags_free(struct nvkm_ltc *, struct nvkm_mm_node **); - -struct nvkm_ltc_impl { - struct nvkm_oclass base; - void (*intr)(struct nvkm_subdev *); - - void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit); - void (*cbc_wait)(struct nvkm_ltc_priv *); + void (*cbc_clear)(struct nvkm_ltc *, u32 start, u32 limit); + void (*cbc_wait)(struct nvkm_ltc *); int zbc; - void (*zbc_clear_color)(struct nvkm_ltc_priv *, int, const u32[4]); - void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32); + void (*zbc_clear_color)(struct nvkm_ltc *, int, const u32[4]); + void (*zbc_clear_depth)(struct nvkm_ltc *, int, const u32); }; -void gf100_ltc_intr(struct nvkm_subdev *); -void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32); -void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *); -void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]); -void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32); +int gf100_ltc_oneinit(struct nvkm_ltc *); +int gf100_ltc_oneinit_tag_ram(struct nvkm_ltc *); +void gf100_ltc_intr(struct nvkm_ltc *); +void gf100_ltc_cbc_clear(struct nvkm_ltc *, u32, u32); +void gf100_ltc_cbc_wait(struct nvkm_ltc *); +void gf100_ltc_zbc_clear_color(struct nvkm_ltc *, int, const u32[4]); +void gf100_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index e1374a01463a..6a2a2d575f16 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -108,11 +108,11 @@ gf100_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt, pte <<= 3; if (mem->tag) { - struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu); + struct nvkm_ltc *ltc = vma->vm->mmu->subdev.device->ltc; u32 tag = mem->tag->offset + (delta >> 17); phys |= (u64)tag << (32 + 12); next |= (u64)1 << (32 + 12); - ltc->tags_clear(ltc, tag, cnt); + nvkm_ltc_tags_clear(ltc, tag, cnt); } nvkm_kmap(pgt); -- cgit v1.2.3 From 54dcadd5b65e12f851ff80af4afef606040ad8b9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:21 +1000 Subject: drm/nouveau/mc: convert to new-style nvkm_subdev Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h | 31 +++-- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 138 ++++++++++----------- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 8 -- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 --- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 8 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c | 83 +++++++------ drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c | 42 ++----- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h | 16 --- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c | 29 ++--- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c | 22 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 28 ++--- drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h | 35 +++--- 28 files changed, 265 insertions(+), 381 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h index 726e3f02e3ec..bafafa643e7f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mc.h @@ -3,26 +3,23 @@ #include struct nvkm_mc { + const struct nvkm_mc_func *func; struct nvkm_subdev subdev; - bool use_msi; + unsigned int irq; - void (*unk260)(struct nvkm_mc *, u32); + bool use_msi; }; -static inline struct nvkm_mc * -nvkm_mc(void *obj) -{ - return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MC); -} +void nvkm_mc_unk260(struct nvkm_mc *, u32 data); -extern struct nvkm_oclass *nv04_mc_oclass; -extern struct nvkm_oclass *nv40_mc_oclass; -extern struct nvkm_oclass *nv44_mc_oclass; -extern struct nvkm_oclass *nv4c_mc_oclass; -extern struct nvkm_oclass *nv50_mc_oclass; -extern struct nvkm_oclass *g94_mc_oclass; -extern struct nvkm_oclass *g98_mc_oclass; -extern struct nvkm_oclass *gf100_mc_oclass; -extern struct nvkm_oclass *gf106_mc_oclass; -extern struct nvkm_oclass *gk20a_mc_oclass; +int nv04_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int nv40_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int nv44_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int nv4c_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int nv50_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int g94_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int g98_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int gf100_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int gf106_mc_new(struct nvkm_device *, int, struct nvkm_mc **); +int gk20a_mc_new(struct nvkm_device *, int, struct nvkm_mc **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index d1ee594dff56..96ac8804ce33 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -83,7 +83,7 @@ nv4_chipset = { .fb = nv04_fb_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -103,7 +103,7 @@ nv5_chipset = { .fb = nv04_fb_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -124,7 +124,7 @@ nv10_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -143,7 +143,7 @@ nv11_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -164,7 +164,7 @@ nv15_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -185,7 +185,7 @@ nv17_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -206,7 +206,7 @@ nv18_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -227,7 +227,7 @@ nv1a_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -248,7 +248,7 @@ nv1f_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -269,7 +269,7 @@ nv20_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -290,7 +290,7 @@ nv25_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -311,7 +311,7 @@ nv28_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -332,7 +332,7 @@ nv2a_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -353,7 +353,7 @@ nv30_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -374,7 +374,7 @@ nv31_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -396,7 +396,7 @@ nv34_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -418,7 +418,7 @@ nv35_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -439,7 +439,7 @@ nv36_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv04_instmem_new, -// .mc = nv04_mc_new, + .mc = nv04_mc_new, // .mmu = nv04_mmu_new, // .timer = nv04_timer_new, // .disp = nv04_disp_new, @@ -461,7 +461,7 @@ nv40_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv04_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -486,7 +486,7 @@ nv41_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -511,7 +511,7 @@ nv42_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -536,7 +536,7 @@ nv43_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -561,7 +561,7 @@ nv44_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv44_mc_new, + .mc = nv44_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -586,7 +586,7 @@ nv45_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv04_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -611,7 +611,7 @@ nv46_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv44_mc_new, + .mc = nv44_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -636,7 +636,7 @@ nv47_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -661,7 +661,7 @@ nv49_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -686,7 +686,7 @@ nv4a_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv44_mc_new, + .mc = nv44_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -711,7 +711,7 @@ nv4b_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv40_mc_new, + .mc = nv40_mc_new, // .mmu = nv41_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -736,7 +736,7 @@ nv4c_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv4c_mc_new, + .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -761,7 +761,7 @@ nv4e_chipset = { .gpio = nv10_gpio_new, .i2c = nv4e_i2c_new, .imem = nv40_instmem_new, -// .mc = nv4c_mc_new, + .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -788,7 +788,7 @@ nv50_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, -// .mc = nv50_mc_new, + .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = nv50_therm_new, @@ -814,7 +814,7 @@ nv63_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv4c_mc_new, + .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -839,7 +839,7 @@ nv67_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv4c_mc_new, + .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -864,7 +864,7 @@ nv68_chipset = { .gpio = nv10_gpio_new, .i2c = nv04_i2c_new, .imem = nv40_instmem_new, -// .mc = nv4c_mc_new, + .mc = nv4c_mc_new, // .mmu = nv44_mmu_new, // .therm = nv40_therm_new, // .timer = nv04_timer_new, @@ -891,7 +891,7 @@ nv84_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, -// .mc = nv50_mc_new, + .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -922,7 +922,7 @@ nv86_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, -// .mc = nv50_mc_new, + .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -953,7 +953,7 @@ nv92_chipset = { .gpio = nv50_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, -// .mc = nv50_mc_new, + .mc = nv50_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -984,7 +984,7 @@ nv94_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g94_mc_new, + .mc = g94_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -1013,7 +1013,7 @@ nv96_chipset = { // .therm = g84_therm_new, // .mxm = nv50_mxm_new, .devinit = g84_devinit_new, -// .mc = g94_mc_new, + .mc = g94_mc_new, .bus = g94_bus_new, // .timer = nv04_timer_new, .fb = g84_fb_new, @@ -1044,7 +1044,7 @@ nv98_chipset = { // .therm = g84_therm_new, // .mxm = nv50_mxm_new, .devinit = g98_devinit_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, .bus = g94_bus_new, // .timer = nv04_timer_new, .fb = g84_fb_new, @@ -1077,7 +1077,7 @@ nva0_chipset = { .gpio = g94_gpio_new, .i2c = nv50_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -1108,7 +1108,7 @@ nva3_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, @@ -1141,7 +1141,7 @@ nva5_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, @@ -1173,7 +1173,7 @@ nva8_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, @@ -1205,7 +1205,7 @@ nvaa_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -1236,7 +1236,7 @@ nvac_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .therm = g84_therm_new, @@ -1267,7 +1267,7 @@ nvaf_chipset = { .gpio = g94_gpio_new, .i2c = g94_i2c_new, .imem = nv50_instmem_new, -// .mc = g98_mc_new, + .mc = g98_mc_new, // .mmu = nv50_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, @@ -1301,7 +1301,7 @@ nvc0_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf100_mc_new, + .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1336,7 +1336,7 @@ nvc1_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1370,7 +1370,7 @@ nvc3_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1404,7 +1404,7 @@ nvc4_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf100_mc_new, + .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1439,7 +1439,7 @@ nvc8_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf100_mc_new, + .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1474,7 +1474,7 @@ nvce_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf100_mc_new, + .mc = gf100_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1509,7 +1509,7 @@ nvcf_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, @@ -1543,7 +1543,7 @@ nvd7_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .therm = gf110_therm_new, @@ -1575,7 +1575,7 @@ nvd9_chipset = { .ibus = gf100_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, @@ -1609,7 +1609,7 @@ nve4_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, @@ -1645,7 +1645,7 @@ nve6_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, @@ -1681,7 +1681,7 @@ nve7_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, @@ -1713,7 +1713,7 @@ nvea_chipset = { .ibus = gk20a_ibus_new, .imem = gk20a_instmem_new, .ltc = gk104_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .pmu = gk20a_pmu_new, // .timer = gk20a_timer_new, @@ -1741,7 +1741,7 @@ nvf0_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, @@ -1777,7 +1777,7 @@ nvf1_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gf106_mc_new, + .mc = gf106_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, @@ -1813,7 +1813,7 @@ nv106_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, @@ -1848,7 +1848,7 @@ nv108_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gk104_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, @@ -1883,7 +1883,7 @@ nv117_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gm107_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, @@ -1912,7 +1912,7 @@ nv124_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gm107_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, @@ -1941,7 +1941,7 @@ nv126_chipset = { .ibus = gk104_ibus_new, .imem = nv50_instmem_new, .ltc = gm107_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, @@ -1966,7 +1966,7 @@ nv12b_chipset = { .ibus = gk20a_ibus_new, .imem = gk20a_instmem_new, .ltc = gm107_ltc_new, -// .mc = gk20a_mc_new, + .mc = gk20a_mc_new, // .mmu = gf100_mmu_new, // .mmu = gf100_mmu_new, // .timer = gk20a_timer_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index e0b57ed658f5..c9f8589c410e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device) case 0xc0: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -50,7 +49,6 @@ gf100_identify(struct nvkm_device *device) case 0xc4: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -70,7 +68,6 @@ gf100_identify(struct nvkm_device *device) case 0xc3: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -89,7 +86,6 @@ gf100_identify(struct nvkm_device *device) case 0xce: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -109,7 +105,6 @@ gf100_identify(struct nvkm_device *device) case 0xcf: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -128,7 +123,6 @@ gf100_identify(struct nvkm_device *device) case 0xc1: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -147,7 +141,6 @@ gf100_identify(struct nvkm_device *device) case 0xc8: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; @@ -167,7 +160,6 @@ gf100_identify(struct nvkm_device *device) case 0xd9: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; @@ -186,7 +178,6 @@ gf100_identify(struct nvkm_device *device) case 0xd7: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 115931cfe18a..11a72fe23583 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device) case 0xe4: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; @@ -51,7 +50,6 @@ gk104_identify(struct nvkm_device *device) case 0xe7: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; @@ -72,7 +70,6 @@ gk104_identify(struct nvkm_device *device) case 0xe6: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; @@ -91,7 +88,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; @@ -106,7 +102,6 @@ gk104_identify(struct nvkm_device *device) case 0xf0: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; @@ -127,7 +122,6 @@ gk104_identify(struct nvkm_device *device) case 0xf1: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; @@ -148,7 +142,6 @@ gk104_identify(struct nvkm_device *device) case 0x106: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; @@ -168,7 +161,6 @@ gk104_identify(struct nvkm_device *device) case 0x108: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index a3c87b26dd9f..cc1209bdd30d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device) case 0x117: device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; @@ -61,7 +60,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; @@ -89,7 +87,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; @@ -112,7 +109,6 @@ gm100_identify(struct nvkm_device *device) break; case 0x12b: - device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index dc90bad93869..19a7a3be7cd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -38,7 +37,6 @@ nv04_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index b1db20f4a15c..a5b222095f59 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -28,7 +28,6 @@ nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -36,7 +35,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -46,7 +44,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -56,7 +53,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -66,7 +62,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -76,7 +71,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -86,7 +80,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -96,7 +89,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index f11b7d01f34a..ad94aeb784b9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -38,7 +37,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -48,7 +46,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -58,7 +55,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index 780dd1019666..61ca82736dda 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -38,7 +37,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -48,7 +46,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -59,7 +56,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x36: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; @@ -70,7 +66,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x34: - device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index a5d874a2c297..05a259cf3a8b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -29,7 +29,6 @@ nv40_identify(struct nvkm_device *device) switch (device->chipset) { case 0x40: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -43,7 +42,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x41: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -57,7 +55,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x42: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -71,7 +68,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x43: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -85,7 +81,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x45: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -99,7 +94,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x47: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -113,7 +107,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x49: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -127,7 +120,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x4b: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -141,7 +133,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x44: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -155,7 +146,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x46: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -169,7 +159,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x4a: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -183,7 +172,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x4c: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -197,7 +185,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x4e: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -211,7 +198,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x63: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -225,7 +211,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x67: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -239,7 +224,6 @@ nv40_identify(struct nvkm_device *device) break; case 0x68: device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 2507559e5894..d72074f98d6f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -30,7 +30,6 @@ nv50_identify(struct nvkm_device *device) case 0x50: device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -45,7 +44,6 @@ nv50_identify(struct nvkm_device *device) case 0x84: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -63,7 +61,6 @@ nv50_identify(struct nvkm_device *device) case 0x86: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -81,7 +78,6 @@ nv50_identify(struct nvkm_device *device) case 0x92: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -99,7 +95,6 @@ nv50_identify(struct nvkm_device *device) case 0x94: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -117,7 +112,6 @@ nv50_identify(struct nvkm_device *device) case 0x96: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -135,7 +129,6 @@ nv50_identify(struct nvkm_device *device) case 0x98: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -153,7 +146,6 @@ nv50_identify(struct nvkm_device *device) case 0xa0: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -171,7 +163,6 @@ nv50_identify(struct nvkm_device *device) case 0xaa: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -189,7 +180,6 @@ nv50_identify(struct nvkm_device *device) case 0xac: device->oclass[NVDEV_SUBDEV_THERM ] = &g84_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -207,7 +197,6 @@ nv50_identify(struct nvkm_device *device) case 0xa3: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; @@ -227,7 +216,6 @@ nv50_identify(struct nvkm_device *device) case 0xa5: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; @@ -246,7 +234,6 @@ nv50_identify(struct nvkm_device *device) case 0xa8: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; @@ -265,7 +252,6 @@ nv50_identify(struct nvkm_device *device) case 0xaf: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; - device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c index 96525b49e686..56f392d3d4fd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c @@ -1239,7 +1239,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) struct nvkm_device *device = gr->base.engine.subdev.device; const struct gf100_grctx_func *grctx = gr->func->grctx; - nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + nvkm_mc_unk260(device->mc, 0); gf100_gr_mmio(gr, grctx->hub); gf100_gr_mmio(gr, grctx->gpc); @@ -1263,7 +1263,7 @@ gf100_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, grctx->mthd); - nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); + nvkm_mc_unk260(device->mc, 1); } int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c index 6a3833b7cc4f..b5b875928aba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c @@ -223,7 +223,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) const struct gf100_grctx_func *grctx = gr->func->grctx; int i; - nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + nvkm_mc_unk260(device->mc, 0); gf100_gr_mmio(gr, grctx->hub); gf100_gr_mmio(gr, grctx->gpc); @@ -250,7 +250,7 @@ gf117_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, grctx->mthd); - nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); + nvkm_mc_unk260(device->mc, 1); } const struct gf100_grctx_func diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index 77110ea019ea..a843e3689c3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -958,7 +958,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) const struct gf100_grctx_func *grctx = gr->func->grctx; int i; - nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + nvkm_mc_unk260(device->mc, 0); gf100_gr_mmio(gr, grctx->hub); gf100_gr_mmio(gr, grctx->gpc); @@ -988,7 +988,7 @@ gk104_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) gf100_gr_icmd(gr, grctx->icmd); nvkm_wr32(device, 0x404154, 0x00000400); gf100_gr_mthd(gr, grctx->mthd); - nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); + nvkm_mc_unk260(device->mc, 1); nvkm_mask(device, 0x418800, 0x00200000, 0x00200000); nvkm_mask(device, 0x41be10, 0x00800000, 0x00800000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 2f22af2fb533..8fd26fa03c2e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1339,12 +1339,12 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) if (gr->firmware) { /* load fuc microcode */ - nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + nvkm_mc_unk260(device->mc, 0); gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); - nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); + nvkm_mc_unk260(device->mc, 1); /* start both of them running */ nvkm_wr32(device, 0x409840, 0xffffffff); @@ -1439,7 +1439,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) } /* load HUB microcode */ - nvkm_mc(gr)->unk260(nvkm_mc(gr), 0); + nvkm_mc_unk260(device->mc, 0); nvkm_wr32(device, 0x4091c0, 0x01000000); for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); @@ -1462,7 +1462,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) nvkm_wr32(device, 0x41a188, i >> 6); nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); } - nvkm_mc(gr)->unk260(nvkm_mc(gr), 1); + nvkm_mc_unk260(device->mc, 1); /* load register lists */ gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c index ee4c34f4b9c4..8d0f5aca3d53 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.c @@ -25,12 +25,11 @@ #include -static inline void +void nvkm_mc_unk260(struct nvkm_mc *mc, u32 data) { - const struct nvkm_mc_oclass *impl = (void *)nv_oclass(mc); - if (impl->unk260) - impl->unk260(mc, data); + if (mc->func->unk260) + mc->func->unk260(mc, data); } static inline u32 @@ -49,8 +48,7 @@ nvkm_mc_intr(int irq, void *arg) struct nvkm_mc *mc = arg; struct nvkm_subdev *subdev = &mc->subdev; struct nvkm_device *device = subdev->device; - const struct nvkm_mc_oclass *oclass = (void *)nv_object(mc)->oclass; - const struct nvkm_mc_intr *map = oclass->intr; + const struct nvkm_mc_intr *map = mc->func->intr; struct nvkm_subdev *unit; u32 intr; @@ -58,13 +56,13 @@ nvkm_mc_intr(int irq, void *arg) nvkm_rd32(device, 0x000140); intr = nvkm_mc_intr_mask(mc); if (mc->use_msi) - oclass->msi_rearm(mc); + mc->func->msi_rearm(mc); if (intr) { u32 stat = intr = nvkm_mc_intr_mask(mc); while (map->stat) { if (intr & map->stat) { - unit = nvkm_subdev(mc, map->unit); + unit = nvkm_device_subdev(device, map->unit); if (unit) nvkm_subdev_intr(unit); stat &= ~map->stat; @@ -80,54 +78,62 @@ nvkm_mc_intr(int irq, void *arg) return intr ? IRQ_HANDLED : IRQ_NONE; } -int -_nvkm_mc_fini(struct nvkm_object *object, bool suspend) +static int +nvkm_mc_fini(struct nvkm_subdev *subdev, bool suspend) { - struct nvkm_mc *mc = (void *)object; - struct nvkm_device *device = mc->subdev.device; - nvkm_wr32(device, 0x000140, 0x00000000); - return nvkm_subdev_fini_old(&mc->subdev, suspend); + nvkm_wr32(subdev->device, 0x000140, 0x00000000); + return 0; } -int -_nvkm_mc_init(struct nvkm_object *object) +static int +nvkm_mc_oneinit(struct nvkm_subdev *subdev) +{ + struct nvkm_mc *mc = nvkm_mc(subdev); + return request_irq(mc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", mc); +} + +static int +nvkm_mc_init(struct nvkm_subdev *subdev) { - struct nvkm_mc *mc = (void *)object; + struct nvkm_mc *mc = nvkm_mc(subdev); struct nvkm_device *device = mc->subdev.device; - int ret = nvkm_subdev_init_old(&mc->subdev); - if (ret) - return ret; + if (mc->func->init) + mc->func->init(mc); nvkm_wr32(device, 0x000140, 0x00000001); return 0; } -void -_nvkm_mc_dtor(struct nvkm_object *object) +static void * +nvkm_mc_dtor(struct nvkm_subdev *subdev) { - struct nvkm_mc *mc = (void *)object; + struct nvkm_mc *mc = nvkm_mc(subdev); struct nvkm_device *device = mc->subdev.device; free_irq(mc->irq, mc); if (mc->use_msi) pci_disable_msi(device->pdev); - nvkm_subdev_destroy(&mc->subdev); + return mc; } +static const struct nvkm_subdev_func +nvkm_mc = { + .dtor = nvkm_mc_dtor, + .oneinit = nvkm_mc_oneinit, + .init = nvkm_mc_init, + .fini = nvkm_mc_fini, +}; + int -nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *bclass, int length, void **pobject) +nvkm_mc_new_(const struct nvkm_mc_func *func, struct nvkm_device *device, + int index, struct nvkm_mc **pmc) { - const struct nvkm_mc_oclass *oclass = (void *)bclass; - struct nvkm_device *device = (void *)parent; struct nvkm_mc *mc; int ret; - ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC", - "master", length, pobject); - mc = *pobject; - if (ret) - return ret; + if (!(mc = *pmc = kzalloc(sizeof(*mc), GFP_KERNEL))) + return -ENOMEM; - mc->unk260 = nvkm_mc_unk260; + nvkm_subdev_ctor(&nvkm_mc, device, index, 0, &mc->subdev); + mc->func = func; if (nv_device_is_pci(device)) { switch (device->pdev->device & 0x0ff0) { @@ -149,11 +155,11 @@ nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine, mc->use_msi = nvkm_boolopt(device->cfgopt, "NvMSI", mc->use_msi); - if (mc->use_msi && oclass->msi_rearm) { + if (mc->use_msi && mc->func->msi_rearm) { mc->use_msi = pci_enable_msi(device->pdev) == 0; if (mc->use_msi) { nvkm_debug(&mc->subdev, "MSI enabled\n"); - oclass->msi_rearm(mc); + mc->func->msi_rearm(mc); } } else { mc->use_msi = false; @@ -164,10 +170,5 @@ nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine, if (ret < 0) return ret; mc->irq = ret; - - ret = request_irq(mc->irq, nvkm_mc_intr, IRQF_SHARED, "nvkm", mc); - if (ret < 0) - return ret; - return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c index f042e7d8321d..36720f25f952 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g94.c @@ -21,17 +21,17 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" -struct nvkm_oclass * -g94_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x94), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv50_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +g94_mc = { + .init = nv50_mc_init, .intr = nv50_mc_intr, .msi_rearm = nv40_mc_msi_rearm, -}.base; +}; + +int +g94_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&g94_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c index 8ab7f1272a14..44286a4bb356 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" static const struct nvkm_mc_intr g98_mc_intr[] = { @@ -44,15 +44,15 @@ g98_mc_intr[] = { {}, }; -struct nvkm_oclass * -g98_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x98), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv50_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +g98_mc = { + .init = nv50_mc_init, .intr = g98_mc_intr, .msi_rearm = nv40_mc_msi_rearm, -}.base; +}; + +int +g98_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&g98_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index f6989cc802c4..26f68d7e7ccc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" const struct nvkm_mc_intr gf100_mc_intr[] = { @@ -60,16 +60,16 @@ gf100_mc_unk260(struct nvkm_mc *mc, u32 data) nvkm_wr32(mc->subdev.device, 0x000260, data); } -struct nvkm_oclass * -gf100_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv50_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +gf100_mc = { + .init = nv50_mc_init, .intr = gf100_mc_intr, .msi_rearm = gf100_mc_msi_rearm, .unk260 = gf100_mc_unk260, -}.base; +}; + +int +gf100_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&gf100_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c index 8d2a8f457778..3515cff5ae48 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf106.c @@ -21,18 +21,18 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" -struct nvkm_oclass * -gf106_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0xc3), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv50_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +gf106_mc = { + .init = nv50_mc_init, .intr = gf100_mc_intr, .msi_rearm = nv40_mc_msi_rearm, .unk260 = gf100_mc_unk260, -}.base; +}; + +int +gf106_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&gf106_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c index 43b27742956d..aa812fe19750 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.c @@ -21,17 +21,17 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" -struct nvkm_oclass * -gk20a_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv50_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +gk20a_mc = { + .init = nv50_mc_init, .intr = gf100_mc_intr, .msi_rearm = nv40_mc_msi_rearm, -}.base; +}; + +int +gk20a_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&gk20a_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c index 6e2fb94b6f84..bcba7bc9737b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" const struct nvkm_mc_intr nv04_mc_intr[] = { @@ -38,42 +38,22 @@ nv04_mc_intr[] = { {} }; -int -nv04_mc_init(struct nvkm_object *object) +void +nv04_mc_init(struct nvkm_mc *mc) { - struct nvkm_mc *mc = (void *)object; struct nvkm_device *device = mc->subdev.device; - nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */ nvkm_wr32(device, 0x001850, 0x00000001); /* disable rom access */ - - return nvkm_mc_init(mc); } +static const struct nvkm_mc_func +nv04_mc = { + .init = nv04_mc_init, + .intr = nv04_mc_intr, +}; + int -nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) { - struct nvkm_mc *mc; - int ret; - - ret = nvkm_mc_create(parent, engine, oclass, &mc); - *pobject = nv_object(mc); - if (ret) - return ret; - - return 0; + return nvkm_mc_new_(&nv04_mc, device, index, pmc); } - -struct nvkm_oclass * -nv04_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x04), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv04_mc_init, - .fini = _nvkm_mc_fini, - }, - .intr = nv04_mc_intr, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h deleted file mode 100644 index aa2e58fa69f0..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef __NVKM_MC_NV04_H__ -#define __NVKM_MC_NV04_H__ -#include "priv.h" - -int nv04_mc_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); - -extern const struct nvkm_mc_intr nv04_mc_intr[]; -int nv04_mc_init(struct nvkm_object *); -void nv40_mc_msi_rearm(struct nvkm_mc *); -int nv44_mc_init(struct nvkm_object *object); -int nv50_mc_init(struct nvkm_object *); -extern const struct nvkm_mc_intr nv50_mc_intr[]; -extern const struct nvkm_mc_intr gf100_mc_intr[]; -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c index 8b46ee26440d..1e75445f84de 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv40.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" void nv40_mc_msi_rearm(struct nvkm_mc *mc) @@ -29,15 +29,15 @@ nv40_mc_msi_rearm(struct nvkm_mc *mc) nvkm_wr08(mc->subdev.device, 0x088068, 0xff); } -struct nvkm_oclass * -nv40_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x40), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv04_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +nv40_mc = { + .init = nv04_mc_init, .intr = nv04_mc_intr, .msi_rearm = nv40_mc_msi_rearm, -}.base; +}; + +int +nv40_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&nv40_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c index 36b3caaa088e..e6795d1aa60d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.c @@ -21,12 +21,11 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" -int -nv44_mc_init(struct nvkm_object *object) +void +nv44_mc_init(struct nvkm_mc *mc) { - struct nvkm_mc *mc = (void *)object; struct nvkm_device *device = mc->subdev.device; u32 tmp = nvkm_rd32(device, 0x10020c); @@ -36,19 +35,17 @@ nv44_mc_init(struct nvkm_object *object) nvkm_wr32(device, 0x001704, 0); nvkm_wr32(device, 0x001708, 0); nvkm_wr32(device, 0x00170c, tmp); - - return nvkm_mc_init(mc); } -struct nvkm_oclass * -nv44_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x44), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv44_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +nv44_mc = { + .init = nv44_mc_init, .intr = nv04_mc_intr, .msi_rearm = nv40_mc_msi_rearm, -}.base; +}; + +int +nv44_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&nv44_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c index c0aac7e20d45..61ab2547af85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv4c.c @@ -21,16 +21,16 @@ * * Authors: Ilia Mirkin */ -#include "nv04.h" +#include "priv.h" -struct nvkm_oclass * -nv4c_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x4c), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv44_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +nv4c_mc = { + .init = nv44_mc_init, .intr = nv04_mc_intr, -}.base; +}; + +int +nv4c_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&nv4c_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index 4ef1c735a542..b5a36c97e771 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" const struct nvkm_mc_intr nv50_mc_intr[] = { @@ -48,24 +48,22 @@ nv50_mc_msi_rearm(struct nvkm_mc *mc) pci_write_config_byte(device->pdev, 0x68, 0xff); } -int -nv50_mc_init(struct nvkm_object *object) +void +nv50_mc_init(struct nvkm_mc *mc) { - struct nvkm_mc *mc = (void *)object; struct nvkm_device *device = mc->subdev.device; nvkm_wr32(device, 0x000200, 0xffffffff); /* everything on */ - return nvkm_mc_init(mc); } -struct nvkm_oclass * -nv50_mc_oclass = &(struct nvkm_mc_oclass) { - .base.handle = NV_SUBDEV(MC, 0x50), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_mc_ctor, - .dtor = _nvkm_mc_dtor, - .init = nv50_mc_init, - .fini = _nvkm_mc_fini, - }, +static const struct nvkm_mc_func +nv50_mc = { + .init = nv50_mc_init, .intr = nv50_mc_intr, .msi_rearm = nv50_mc_msi_rearm, -}.base; +}; + +int +nv50_mc_new(struct nvkm_device *device, int index, struct nvkm_mc **pmc) +{ + return nvkm_mc_new_(&nv50_mc, device, index, pmc); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h index d2cad07afd1a..ca2249b18998 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/priv.h @@ -1,36 +1,33 @@ #ifndef __NVKM_MC_PRIV_H__ #define __NVKM_MC_PRIV_H__ +#define nvkm_mc(p) container_of((p), struct nvkm_mc, subdev) #include -#define nvkm_mc_create(p,e,o,d) \ - nvkm_mc_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nvkm_mc_destroy(p) ({ \ - struct nvkm_mc *pmc = (p); _nvkm_mc_dtor(nv_object(pmc)); \ -}) -#define nvkm_mc_init(p) ({ \ - struct nvkm_mc *pmc = (p); _nvkm_mc_init(nv_object(pmc)); \ -}) -#define nvkm_mc_fini(p,s) ({ \ - struct nvkm_mc *pmc = (p); _nvkm_mc_fini(nv_object(pmc), (s)); \ -}) - -int nvkm_mc_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); -void _nvkm_mc_dtor(struct nvkm_object *); -int _nvkm_mc_init(struct nvkm_object *); -int _nvkm_mc_fini(struct nvkm_object *, bool); +int nvkm_mc_new_(const struct nvkm_mc_func *, struct nvkm_device *, + int index, struct nvkm_mc **); struct nvkm_mc_intr { u32 stat; u32 unit; }; -struct nvkm_mc_oclass { - struct nvkm_oclass base; +struct nvkm_mc_func { + void (*init)(struct nvkm_mc *); const struct nvkm_mc_intr *intr; void (*msi_rearm)(struct nvkm_mc *); void (*unk260)(struct nvkm_mc *, u32); }; +void nv04_mc_init(struct nvkm_mc *); +extern const struct nvkm_mc_intr nv04_mc_intr[]; + +void nv40_mc_msi_rearm(struct nvkm_mc *); + +void nv44_mc_init(struct nvkm_mc *); + +void nv50_mc_init(struct nvkm_mc *); +extern const struct nvkm_mc_intr nv50_mc_intr[]; + +extern const struct nvkm_mc_intr gf100_mc_intr[]; void gf100_mc_unk260(struct nvkm_mc *, u32); #endif -- cgit v1.2.3 From e2ca4e7d6e56cb73a068708f0b0c9bd62ab9e02c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:21 +1000 Subject: drm/nouveau/pmu: convert to new-style nvkm_subdev Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 29 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 46 +- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 3 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 9 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild | 3 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 84 +- .../gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 | 70 - .../drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h | 1795 -------------------- .../gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4 | 70 + .../drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h | 1795 ++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c | 19 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c | 40 - drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c | 39 + drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c | 25 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c | 25 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c | 19 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 62 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c | 41 + drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c | 26 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h | 30 +- 24 files changed, 2115 insertions(+), 2147 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4 create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index 64b3a177bf88..e61923d5e49c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -3,6 +3,7 @@ #include struct nvkm_pmu { + const struct nvkm_pmu_func *func; struct nvkm_subdev subdev; struct { @@ -20,24 +21,20 @@ struct nvkm_pmu { u32 message; u32 data[2]; } recv; - - int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); - void (*pgob)(struct nvkm_pmu *, bool); }; -static inline struct nvkm_pmu * -nvkm_pmu(void *obj) -{ - return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU); -} - -extern struct nvkm_oclass *gt215_pmu_oclass; -extern struct nvkm_oclass *gf100_pmu_oclass; -extern struct nvkm_oclass *gf110_pmu_oclass; -extern struct nvkm_oclass *gk104_pmu_oclass; -extern struct nvkm_oclass *gk110_pmu_oclass; -extern struct nvkm_oclass *gk208_pmu_oclass; -extern struct nvkm_oclass *gk20a_pmu_oclass; +int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, + u32 message, u32 data0, u32 data1); +void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); + +int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); +int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); /* interface to MEMX process running on PMU */ struct nvkm_memx; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 350daa3c630c..8f201022377f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1111,7 +1111,7 @@ nva3_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gt215_pmu_new, + .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1144,7 +1144,7 @@ nva5_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gt215_pmu_new, + .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1176,7 +1176,7 @@ nva8_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gt215_pmu_new, + .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1270,7 +1270,7 @@ nvaf_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gt215_pmu_new, + .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1304,7 +1304,7 @@ nvc0_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1339,7 +1339,7 @@ nvc1_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1373,7 +1373,7 @@ nvc3_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1407,7 +1407,7 @@ nvc4_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1442,7 +1442,7 @@ nvc8_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1477,7 +1477,7 @@ nvce_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1512,7 +1512,7 @@ nvcf_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf100_pmu_new, + .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1578,7 +1578,7 @@ nvd9_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf110_pmu_new, + .pmu = gf119_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1612,7 +1612,7 @@ nve4_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk104_pmu_new, + .pmu = gk104_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1648,7 +1648,7 @@ nve6_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk104_pmu_new, + .pmu = gk104_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1684,7 +1684,7 @@ nve7_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gf110_pmu_new, + .pmu = gf119_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1715,7 +1715,7 @@ nvea_chipset = { .ltc = gk104_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, -// .pmu = gk20a_pmu_new, + .pmu = gk20a_pmu_new, // .timer = gk20a_timer_new, // .volt = gk20a_volt_new, // .ce[2] = gk104_ce2_new, @@ -1744,7 +1744,7 @@ nvf0_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk110_pmu_new, + .pmu = gk110_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1780,7 +1780,7 @@ nvf1_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk110_pmu_new, + .pmu = gk110_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1816,7 +1816,7 @@ nv106_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk208_pmu_new, + .pmu = gk208_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1851,7 +1851,7 @@ nv108_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk208_pmu_new, + .pmu = gk208_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, @@ -1886,7 +1886,7 @@ nv117_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk208_pmu_new, + .pmu = gm107_pmu_new, // .therm = gm107_therm_new, // .timer = gk20a_timer_new, // .ce[0] = gk104_ce0_new, @@ -1915,7 +1915,7 @@ nv124_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk208_pmu_new, + .pmu = gm107_pmu_new, // .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, @@ -1944,7 +1944,7 @@ nv126_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, -// .pmu = gk208_pmu_new, + .pmu = gm107_pmu_new, // .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index ef161ef6be55..556447727342 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device) case 0xc0: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -47,7 +46,6 @@ gf100_identify(struct nvkm_device *device) case 0xc4: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -64,7 +62,6 @@ gf100_identify(struct nvkm_device *device) case 0xc3: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -80,7 +77,6 @@ gf100_identify(struct nvkm_device *device) case 0xce: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -97,7 +93,6 @@ gf100_identify(struct nvkm_device *device) case 0xcf: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -113,7 +108,6 @@ gf100_identify(struct nvkm_device *device) case 0xc1: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -129,7 +123,6 @@ gf100_identify(struct nvkm_device *device) case 0xc8: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -146,7 +139,6 @@ gf100_identify(struct nvkm_device *device) case 0xd9: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index e649e38a11b5..9e05f8bbabc9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device) case 0xe4: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -48,7 +47,6 @@ gk104_identify(struct nvkm_device *device) case 0xe7: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -66,7 +64,6 @@ gk104_identify(struct nvkm_device *device) case 0xe6: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -90,12 +87,10 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; break; case 0xf0: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -113,7 +108,6 @@ gk104_identify(struct nvkm_device *device) case 0xf1: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -131,7 +125,6 @@ gk104_identify(struct nvkm_device *device) case 0x106: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; @@ -148,7 +141,6 @@ gk104_identify(struct nvkm_device *device) case 0x108: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index e1dfea9764de..76c6b104a99a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device) case 0x117: device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -58,7 +57,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif @@ -83,7 +81,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index fad8e6819dca..f2956d45d32e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -177,7 +177,6 @@ nv50_identify(struct nvkm_device *device) case 0xa3: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -194,7 +193,6 @@ nv50_identify(struct nvkm_device *device) case 0xa5: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -210,7 +208,6 @@ nv50_identify(struct nvkm_device *device) case 0xa8: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -226,7 +223,6 @@ nv50_identify(struct nvkm_device *device) case 0xaf: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index 956e5926afe5..efd5ebd1fa04 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -185,15 +185,13 @@ gk104_gr_init(struct nvkm_object *object) struct gf100_gr_oclass *oclass = (void *)object->oclass; struct gf100_gr *gr = (void *)object; struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_pmu *pmu = device->pmu; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; int ret, i; - if (pmu) - pmu->pgob(pmu, false); + nvkm_pmu_pgob(device->pmu, false); ret = nvkm_gr_init(&gr->base); if (ret) @@ -315,9 +313,8 @@ gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_pmu *pmu = nvkm_pmu(parent); - if (pmu) - pmu->pgob(pmu, false); + struct nvkm_device *device = (void *)parent; + nvkm_pmu_pgob(device->pmu, false); return gf100_gr_ctor(parent, engine, oclass, data, size, pobject); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild index 7081d6a9b95f..88b643b8664e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/Kbuild @@ -2,8 +2,9 @@ nvkm-y += nvkm/subdev/pmu/base.o nvkm-y += nvkm/subdev/pmu/memx.o nvkm-y += nvkm/subdev/pmu/gt215.o nvkm-y += nvkm/subdev/pmu/gf100.o -nvkm-y += nvkm/subdev/pmu/gf110.o +nvkm-y += nvkm/subdev/pmu/gf119.o nvkm-y += nvkm/subdev/pmu/gk104.o nvkm-y += nvkm/subdev/pmu/gk110.o nvkm-y += nvkm/subdev/pmu/gk208.o nvkm-y += nvkm/subdev/pmu/gk20a.o +nvkm-y += nvkm/subdev/pmu/gm107.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index c700d3d956e8..27a79c0c3888 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -28,12 +28,11 @@ void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { - const struct nvkm_pmu_impl *impl = (void *)nv_oclass(pmu); - if (impl->pgob) - impl->pgob(pmu, enable); + if (pmu->func->pgob) + pmu->func->pgob(pmu, enable); } -static int +int nvkm_pmu_send(struct nvkm_pmu *pmu, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1) { @@ -144,7 +143,7 @@ nvkm_pmu_recv(struct work_struct *work) static void nvkm_pmu_intr(struct nvkm_subdev *subdev) { - struct nvkm_pmu *pmu = container_of(subdev, typeof(*pmu), subdev); + struct nvkm_pmu *pmu = nvkm_pmu(subdev); struct nvkm_device *device = pmu->subdev.device; u32 disp = nvkm_rd32(device, 0x10a01c); u32 intr = nvkm_rd32(device, 0x10a008) & disp & ~(disp >> 16); @@ -180,33 +179,23 @@ nvkm_pmu_intr(struct nvkm_subdev *subdev) } } -int -_nvkm_pmu_fini(struct nvkm_object *object, bool suspend) +static int +nvkm_pmu_fini(struct nvkm_subdev *subdev, bool suspend) { - struct nvkm_pmu *pmu = (void *)object; + struct nvkm_pmu *pmu = nvkm_pmu(subdev); struct nvkm_device *device = pmu->subdev.device; nvkm_wr32(device, 0x10a014, 0x00000060); flush_work(&pmu->recv.work); - - return nvkm_subdev_fini_old(&pmu->subdev, suspend); + return 0; } -int -_nvkm_pmu_init(struct nvkm_object *object) +static int +nvkm_pmu_init(struct nvkm_subdev *subdev) { - const struct nvkm_pmu_impl *impl = (void *)object->oclass; - struct nvkm_pmu *pmu = (void *)object; + struct nvkm_pmu *pmu = nvkm_pmu(subdev); struct nvkm_device *device = pmu->subdev.device; - int ret, i; - - ret = nvkm_subdev_init_old(&pmu->subdev); - if (ret) - return ret; - - nv_subdev(pmu)->intr = nvkm_pmu_intr; - pmu->message = nvkm_pmu_send; - pmu->pgob = nvkm_pmu_pgob; + int i; /* prevent previous ucode from running, wait for idle, reset */ nvkm_wr32(device, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ @@ -224,15 +213,15 @@ _nvkm_pmu_init(struct nvkm_object *object) /* upload data segment */ nvkm_wr32(device, 0x10a1c0, 0x01000000); - for (i = 0; i < impl->data.size / 4; i++) - nvkm_wr32(device, 0x10a1c4, impl->data.data[i]); + for (i = 0; i < pmu->func->data.size / 4; i++) + nvkm_wr32(device, 0x10a1c4, pmu->func->data.data[i]); /* upload code segment */ nvkm_wr32(device, 0x10a180, 0x01000000); - for (i = 0; i < impl->code.size / 4; i++) { + for (i = 0; i < pmu->func->code.size / 4; i++) { if ((i & 0x3f) == 0) nvkm_wr32(device, 0x10a188, i >> 6); - nvkm_wr32(device, 0x10a184, impl->code.data[i]); + nvkm_wr32(device, 0x10a184, pmu->func->code.data[i]); } /* start it running */ @@ -262,31 +251,30 @@ _nvkm_pmu_init(struct nvkm_object *object) return 0; } -int -nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, int length, void **pobject) +static void * +nvkm_pmu_dtor(struct nvkm_subdev *subdev) { - struct nvkm_pmu *pmu; - int ret; - - ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU", - "pmu", length, pobject); - pmu = *pobject; - if (ret) - return ret; - - INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); - init_waitqueue_head(&pmu->recv.wait); - return 0; + return nvkm_pmu(subdev); } +static const struct nvkm_subdev_func +nvkm_pmu = { + .dtor = nvkm_pmu_dtor, + .init = nvkm_pmu_init, + .fini = nvkm_pmu_fini, + .intr = nvkm_pmu_intr, +}; + int -_nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nvkm_pmu_new_(const struct nvkm_pmu_func *func, struct nvkm_device *device, + int index, struct nvkm_pmu **ppmu) { struct nvkm_pmu *pmu; - int ret = nvkm_pmu_create(parent, engine, oclass, &pmu); - *pobject = nv_object(pmu); - return ret; + if (!(pmu = *ppmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) + return -ENOMEM; + nvkm_subdev_ctor(&nvkm_pmu, device, index, 0, &pmu->subdev); + pmu->func = func; + INIT_WORK(&pmu->recv.work, nvkm_pmu_recv); + init_waitqueue_head(&pmu->recv.wait); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 deleted file mode 100644 index ae9c3f18ae01..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4 +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#define NVKM_PPWR_CHIPSET GF119 -#define HW_TICKS_PER_US 324 - -//#define NVKM_FALCON_PC24 -#define NVKM_FALCON_UNSHIFTED_IO -//#define NVKM_FALCON_MMIO_UAS -//#define NVKM_FALCON_MMIO_TRAP - -#include "macros.fuc" - -.section #gf110_pmu_data -#define INCLUDE_PROC -#include "kernel.fuc" -#include "arith.fuc" -#include "host.fuc" -#include "memx.fuc" -#include "perf.fuc" -#include "i2c_.fuc" -#include "test.fuc" -#include "idle.fuc" -#undef INCLUDE_PROC - -#define INCLUDE_DATA -#include "kernel.fuc" -#include "arith.fuc" -#include "host.fuc" -#include "memx.fuc" -#include "perf.fuc" -#include "i2c_.fuc" -#include "test.fuc" -#include "idle.fuc" -#undef INCLUDE_DATA -.align 256 - -.section #gf110_pmu_code -#define INCLUDE_CODE -#include "kernel.fuc" -#include "arith.fuc" -#include "host.fuc" -#include "memx.fuc" -#include "perf.fuc" -#include "i2c_.fuc" -#include "test.fuc" -#include "idle.fuc" -#undef INCLUDE_CODE -.align 256 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h deleted file mode 100644 index a0c499e4543c..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf110.fuc4.h +++ /dev/null @@ -1,1795 +0,0 @@ -uint32_t gf110_pmu_data[] = { -/* 0x0000: proc_kern */ - 0x52544e49, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0058: proc_list_head */ - 0x54534f48, - 0x0000049d, - 0x00000446, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x584d454d, - 0x0000068b, - 0x0000067d, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x46524550, - 0x0000068f, - 0x0000068d, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x5f433249, - 0x00000aaa, - 0x0000094d, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x54534554, - 0x00000acd, - 0x00000aac, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x454c4449, - 0x00000ad9, - 0x00000ad7, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0268: proc_list_tail */ -/* 0x0268: time_prev */ - 0x00000000, -/* 0x026c: time_next */ - 0x00000000, -/* 0x0270: fifo_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x02f0: rfifo_queue */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0370: memx_func_head */ - 0x00000001, - 0x00000000, - 0x000004d3, -/* 0x037c: memx_func_next */ - 0x00000002, - 0x00000000, - 0x00000554, - 0x00000003, - 0x00000002, - 0x000005d8, - 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0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0bcc: memx_data_tail */ -/* 0x0bcc: memx_train_head */ - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -/* 0x0ccc: memx_train_tail */ -/* 0x0ccc: i2c_scl_map */ - 0x00000400, - 0x00000800, - 0x00001000, - 0x00002000, - 0x00004000, - 0x00008000, - 0x00010000, - 0x00020000, - 0x00040000, - 0x00080000, -/* 0x0cf4: i2c_sda_map */ - 0x00100000, - 0x00200000, - 0x00400000, - 0x00800000, - 0x01000000, - 0x02000000, - 0x04000000, - 0x08000000, - 0x10000000, - 0x20000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -uint32_t gf110_pmu_code[] = { - 0x034d0ef5, -/* 0x0004: rd32 */ - 0x07a007f1, - 0xbd000ed0, - 0x01d7f004, - 0xf101d3f0, - 0xd007ac07, - 0x04bd000d, -/* 0x001c: rd32_wait */ - 0x07acd7f1, - 0xf100ddcf, - 0xf47000d4, - 0xd7f1f51b, - 0xddcf07a4, -/* 0x0033: wr32 */ - 0xf100f800, - 0xd007a007, - 0x04bd000e, - 0x07a407f1, - 0xbd000dd0, - 0x02d7f004, - 0xf0f0d5f0, - 0x07f101d3, - 0x0dd007ac, -/* 0x0057: wr32_wait */ - 0xf104bd00, - 0xcf07acd7, - 0xd4f100dd, - 0x1bf47000, -/* 0x0067: nsec */ - 0xf900f8f5, - 0xf080f990, - 0x88cf2c87, -/* 0x0071: nsec_loop */ - 0x2c97f000, - 0xbb0099cf, - 0x9eb80298, - 0xf41ef406, - 0x90fc80fc, -/* 0x0086: wait */ - 0x90f900f8, - 0x87f080f9, - 0x0088cf2c, -/* 0x0090: wait_loop */ - 0xf402eeb9, - 0xdab90421, - 0x04adfd02, - 0xf406acb8, - 0x97f0120b, - 0x0099cf2c, - 0xb80298bb, - 0x1ef4069b, -/* 0x00b1: wait_done */ - 0xfc80fce2, -/* 0x00b7: intr_watchdog */ - 0x9800f890, - 0x96b003e9, - 0x2a0bf400, - 0xbb9a0a98, - 0x1cf4029a, - 0x01d7f00f, - 0x028c21f5, - 0x0ef494bd, -/* 0x00d5: intr_watchdog_next_time */ - 0x9b0a9815, - 0xf400a6b0, - 0x9ab8090b, - 0x061cf406, -/* 0x00e4: intr_watchdog_next_time_set */ -/* 0x00e7: intr_watchdog_next_proc */ - 0x809b0980, - 0xe0b603e9, - 0x68e6b158, - 0xc61bf402, -/* 0x00f6: intr */ - 0x00f900f8, - 0x80f904bd, - 0xa0f990f9, - 0xc0f9b0f9, - 0xe0f9d0f9, - 0xf7f0f0f9, - 0x0188fe00, - 0x87f180f9, - 0x88cf05d0, - 0x0180b600, - 0x05d007f1, - 0xbd0008d0, - 0x0887f004, - 0xc40088cf, - 0x0bf40289, - 0x9b008020, - 0xf458e7f0, - 0x0998b721, - 0x0096b09b, - 0xf00e0bf4, - 0x09d03407, - 0x8004bd00, -/* 0x014e: intr_skip_watchdog */ - 0x89e49a09, - 0x0bf40800, - 0x8897f13c, - 0x0099cf06, - 0xf4029ac4, - 0xc7f1260b, - 0xcccf04c0, - 0xf1c0f900, - 0xf14f48e7, - 0xf05453e3, - 0x21f500d7, - 0xc0fc02f1, - 0x04c007f1, - 0xbd000cd0, -/* 0x0185: intr_subintr_skip_fifo */ - 0x8807f104, - 0x0009d006, -/* 0x018e: intr_skip_subintr */ - 0x89c404bd, - 0x070bf420, - 0xffbfa4f1, -/* 0x0198: intr_skip_pause */ - 0xf44089c4, - 0xa4f1070b, -/* 0x01a2: intr_skip_user0 */ - 0x07f0ffbf, - 0x0008d004, - 0x80fc04bd, - 0xfc0088fe, - 0xfce0fcf0, - 0xfcc0fcd0, - 0xfca0fcb0, - 0xfc80fc90, - 0x0032f400, -/* 0x01c6: ticks_from_ns */ - 0xc0f901f8, - 0xd7f1b0f9, - 0xd3f00144, - 0xb321f500, - 0xe8ccec03, - 0x00b4b003, - 0xec120bf4, - 0xf103e8ee, - 0xf00144d7, - 0x21f500d3, -/* 0x01ee: ticks_from_ns_quit */ - 0xceb903b3, - 0xfcb0fc02, -/* 0x01f7: ticks_from_us */ - 0xf900f8c0, - 0xf1b0f9c0, - 0xf00144d7, - 0x21f500d3, - 0xceb903b3, - 0x00b4b002, - 0xbd050bf4, -/* 0x0211: ticks_from_us_quit */ - 0xfcb0fce4, -/* 0x0217: ticks_to_us */ - 0xf100f8c0, - 0xf00144d7, - 0xedff00d3, -/* 0x0223: timer */ - 0xf900f8ec, - 0xf480f990, - 0xf8981032, - 0x0086b003, - 0xbd531cf4, - 0x3807f084, - 0xbd0008d0, - 0x3487f004, - 0x980088cf, - 0x98bb9a09, - 0x00e9bb02, - 0xf003fe80, - 0x88cf0887, - 0x0284f000, - 0xf0201bf4, - 0x88cf3487, - 0x06e0b800, - 0xb8090bf4, - 0x1cf406e8, -/* 0x026d: timer_reset */ - 0x3407f00e, - 0xbd000ed0, - 0x9a0e8004, -/* 0x0278: timer_enable */ - 0xf00187f0, - 0x08d03807, -/* 0x0283: timer_done */ - 0xf404bd00, - 0x80fc1031, - 0x00f890fc, -/* 0x028c: send_proc */ - 0x90f980f9, - 0x9805e898, - 0x86f004e9, - 0x0689b804, - 0xc42a0bf4, - 0x88940398, - 0x1880b604, - 0x98008ebb, - 0x8a8000fa, - 0x018d8000, - 0x80028c80, - 0x90b6038b, - 0x0794f001, - 0xf404e980, -/* 0x02c6: send_done */ - 0x90fc0231, - 0x00f880fc, -/* 0x02cc: find */ - 0x87f080f9, - 0x0131f458, -/* 0x02d4: find_loop */ - 0xb8008a98, - 0x0bf406ae, - 0x5880b610, - 0x026886b1, - 0xf4f01bf4, -/* 0x02ea: find_done */ - 0x8eb90132, - 0xf880fc02, -/* 0x02f1: send */ - 0xcc21f500, - 0x9701f402, -/* 0x02fa: recv */ - 0x90f900f8, - 0xe89880f9, - 0x04e99805, - 0xb80132f4, - 0x0bf40689, - 0x0389c43d, - 0xf00180b6, - 0xe8800784, - 0x02ea9805, - 0x8ffef0f9, - 0xb9f0f901, - 0x999402ef, - 0x00e9bb04, - 0x9818e0b6, - 0xec9803eb, - 0x01ed9802, - 0xf900ee98, - 0xfef0fca5, - 0x31f400f8, -/* 0x0347: recv_done */ - 0xfcf0fc01, - 0xf890fc80, -/* 0x034d: init */ - 0x0817f100, - 0x0011cf01, - 0x010911e7, - 0xfe0814b6, - 0x17f10014, - 0x13f000e0, - 0x1c07f000, - 0xbd0001d0, - 0xff17f004, - 0xd01407f0, - 0x04bd0001, - 0xf10217f0, - 0xf0080015, - 0x01d01007, - 0xf104bd00, - 0xf000f617, - 0x10fe0013, - 0x1031f400, - 0xf00117f0, - 0x01d03807, - 0xf004bd00, -/* 0x03a2: init_proc */ - 0xf19858f7, - 0x0016b001, - 0xf9fa0bf4, - 0x58f0b615, -/* 0x03b3: mulu32_32_64 */ - 0xf9f20ef4, - 0xf920f910, - 0x9540f930, - 0xd29510e1, - 0xbdc4bd10, - 0xc0edffb4, - 0xb9301dff, - 0x34f10234, - 0x34b6ffff, - 0x1045b610, - 0xbb00c3bb, - 0xe2ff01b4, - 0x0234b930, - 0xffff34f1, - 0xb61034b6, - 0xc3bb1045, - 0x01b4bb00, - 0xbb3012ff, - 0x40fc00b3, - 0x20fc30fc, - 0x00f810fc, -/* 0x0404: host_send */ - 0x04b017f1, - 0xf10011cf, - 0xcf04a027, - 0x12b80022, - 0x2f0bf406, - 0x94071ec4, - 0xe0b704ee, - 0xeb980270, - 0x02ec9803, - 0x9801ed98, - 0x21f500ee, - 0x10b602f1, - 0x0f1ec401, - 0x04b007f1, - 0xbd000ed0, - 0xc30ef404, -/* 0x0444: host_send_done */ -/* 0x0446: host_recv */ - 0x17f100f8, - 0x13f14e49, - 0xe1b85254, - 0xb30bf406, -/* 0x0454: host_recv_wait */ - 0x04cc17f1, - 0xf10011cf, - 0xcf04c827, - 0x16f00022, - 0x0612b808, - 0xc4ec0bf4, - 0x34b60723, - 0xf030b704, - 0x033b8002, - 0x80023c80, - 0x3e80013d, - 0x0120b600, - 0xf10f24f0, - 0xd004c807, - 0x04bd0002, - 0xf04027f0, - 0x02d00007, - 0xf804bd00, -/* 0x049d: host_init */ - 0x8017f100, - 0x1014b600, - 0x027015f1, - 0x04d007f1, - 0xbd0001d0, - 0x8017f104, - 0x1014b600, - 0x02f015f1, - 0x04dc07f1, - 0xbd0001d0, - 0x0117f004, - 0x04c407f1, - 0xbd0001d0, -/* 0x04d3: memx_func_enter */ - 0xf100f804, - 0xf1162067, - 0xf1f55d77, - 0xb9ffff73, - 0x21f4026e, - 0x02d8b904, - 0xf90487fd, - 0xfc80f960, - 0xf4e0fcd0, - 0x77f13321, - 0x73f1fffe, - 0x6eb9ffff, - 0x0421f402, - 0xfd02d8b9, - 0x60f90487, - 0xd0fc80f9, - 0x21f4e0fc, - 0xf067f133, - 0x026eb926, - 0xb90421f4, - 0x87fd02d8, - 0xf960f904, - 0xfcd0fc80, - 0x3321f4e0, - 0xf10467f0, - 0xd007e007, - 0x04bd0006, -/* 0x053c: memx_func_enter_wait */ - 0x07c067f1, - 0xf00066cf, - 0x0bf40464, - 0x2c67f0f6, - 0x800066cf, - 0x00f8f106, -/* 0x0554: memx_func_leave */ - 0xcf2c67f0, - 0x06800066, - 0x0467f0f2, - 0x07e407f1, - 0xbd0006d0, -/* 0x0569: memx_func_leave_wait */ - 0xc067f104, - 0x0066cf07, - 0xf40464f0, - 0x67f1f61b, - 0x77f126f0, - 0x73f00001, - 0x026eb900, - 0xb90421f4, - 0x87fd02d8, - 0xf960f905, - 0xfcd0fc80, - 0x3321f4e0, - 0x162067f1, - 0xf4026eb9, - 0xd8b90421, - 0x0587fd02, - 0x80f960f9, - 0xe0fcd0fc, - 0xf13321f4, - 0xf00aa277, - 0x6eb90073, - 0x0421f402, - 0xfd02d8b9, - 0x60f90587, - 0xd0fc80f9, - 0x21f4e0fc, -/* 0x05d3: memx_func_wait_vblank */ - 0xb600f833, - 0x00f80410, -/* 0x05d8: memx_func_wr32 */ - 0x98001698, - 0x10b60115, - 0xf960f908, - 0xfcd0fc50, - 0x3321f4e0, - 0xf40242b6, - 0x00f8e91b, -/* 0x05f4: memx_func_wait */ - 0xcf2c87f0, - 0x1e980088, - 0x011d9800, - 0x98021c98, - 0x10b6031b, - 0x8621f410, -/* 0x060e: memx_func_delay */ - 0x1e9800f8, - 0x0410b600, - 0xf86721f4, -/* 0x0619: memx_func_train */ -/* 0x061b: memx_exec */ - 0xf900f800, - 0xb9d0f9e0, - 0xb2b902c1, -/* 0x0625: memx_exec_next */ - 0x00139802, - 0xe70410b6, - 0xe701f034, - 0xb601e033, - 0x30f00132, - 0xde35980c, - 0x12b855f9, - 0xe41ef406, - 0x98f10b98, - 0xcbbbf20c, - 0xc4b7f102, - 0x00bbcf07, - 0xe0fcd0fc, - 0x02f121f5, -/* 0x065e: memx_info */ - 0xc67000f8, - 0x0e0bf401, -/* 0x0664: memx_info_data */ - 0x03ccc7f1, - 0x0800b7f1, -/* 0x066f: memx_info_train */ - 0xf10b0ef4, - 0xf10bccc7, -/* 0x0677: memx_info_send */ - 0xf50100b7, - 0xf802f121, -/* 0x067d: memx_recv */ - 0x01d6b000, - 0xb09b0bf4, - 0x0bf400d6, -/* 0x068b: memx_init */ - 0xf800f8d8, -/* 0x068d: perf_recv */ -/* 0x068f: perf_init */ - 0xf800f800, -/* 0x0691: i2c_drive_scl */ - 0x0036b000, - 0xf10e0bf4, - 0xd007e007, - 0x04bd0001, -/* 0x06a2: i2c_drive_scl_lo */ - 0x07f100f8, - 0x01d007e4, - 0xf804bd00, -/* 0x06ad: i2c_drive_sda */ - 0x0036b000, - 0xf10e0bf4, - 0xd007e007, - 0x04bd0002, -/* 0x06be: i2c_drive_sda_lo */ - 0x07f100f8, - 0x02d007e4, - 0xf804bd00, -/* 0x06c9: i2c_sense_scl */ - 0x0132f400, - 0x07c437f1, - 0xfd0033cf, - 0x0bf40431, - 0x0131f406, -/* 0x06dc: i2c_sense_scl_done */ -/* 0x06de: i2c_sense_sda */ - 0x32f400f8, - 0xc437f101, - 0x0033cf07, - 0xf40432fd, - 0x31f4060b, -/* 0x06f1: i2c_sense_sda_done */ -/* 0x06f3: i2c_raise_scl */ - 0xf900f801, - 0x9847f140, - 0x0137f008, - 0x069121f5, -/* 0x0700: i2c_raise_scl_wait */ - 0x03e8e7f1, - 0xf56721f4, - 0xf406c921, - 0x42b60901, - 0xef1bf401, -/* 0x0714: i2c_raise_scl_done */ - 0x00f840fc, -/* 0x0718: i2c_start */ - 0x06c921f5, - 0xf50d11f4, - 0xf406de21, - 0x0ef40611, -/* 0x0729: i2c_start_rep */ - 0x0037f030, - 0x069121f5, - 0xf50137f0, - 0xbb06ad21, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x06f321f5, - 0xf40464b6, -/* 0x0756: i2c_start_send */ - 0x37f01f11, - 0xad21f500, - 0x88e7f106, - 0x6721f413, - 0xf50037f0, - 0xf1069121, - 0xf41388e7, -/* 0x0772: i2c_start_out */ - 0x00f86721, -/* 0x0774: i2c_stop */ - 0xf50037f0, - 0xf0069121, - 0x21f50037, - 0xe7f106ad, - 0x21f403e8, - 0x0137f067, - 0x069121f5, - 0x1388e7f1, - 0xf06721f4, - 0x21f50137, - 0xe7f106ad, - 0x21f41388, -/* 0x07a7: i2c_bitw */ - 0xf500f867, - 0xf106ad21, - 0xf403e8e7, - 0x76bb6721, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb606f321, - 0x11f40464, - 0x88e7f118, - 0x6721f413, - 0xf50037f0, - 0xf1069121, - 0xf41388e7, -/* 0x07e6: i2c_bitw_out */ - 0x00f86721, -/* 0x07e8: i2c_bitr */ - 0xf50137f0, - 0xf106ad21, - 0xf403e8e7, - 0x76bb6721, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb606f321, - 0x11f40464, - 0xde21f51b, - 0x0037f006, - 0x069121f5, - 0x1388e7f1, - 0xf06721f4, - 0x31f4013c, -/* 0x082d: i2c_bitr_done */ -/* 0x082f: i2c_get_byte */ - 0xf000f801, - 0x47f00057, -/* 0x0835: i2c_get_byte_next */ - 0x0154b608, - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0xe821f550, - 0x0464b607, - 0xfd2b11f4, - 0x42b60553, - 0xd81bf401, - 0xbb0137f0, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x07a721f5, -/* 0x087f: i2c_get_byte_done */ - 0xf80464b6, -/* 0x0881: i2c_put_byte */ - 0x0847f000, -/* 0x0884: i2c_put_byte_next */ - 0xff0142b6, - 0x76bb3854, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb607a721, - 0x11f40464, - 0x0046b034, - 0xbbd81bf4, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x07e821f5, - 0xf40464b6, - 0x76bb0f11, - 0x0136b000, - 0xf4061bf4, -/* 0x08da: i2c_put_byte_done */ - 0x00f80132, -/* 0x08dc: i2c_addr */ - 0xb60076bb, - 0x50f90465, - 0xbb046594, - 0x50bd0256, - 0xfc0475fd, - 0x1821f550, - 0x0464b607, - 0xe72911f4, - 0xb6012ec3, - 0x53fd0134, - 0x0076bb05, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b60881, -/* 0x0921: i2c_addr_done */ -/* 0x0923: i2c_acquire_addr */ - 0xc700f804, - 0xe4b6f8ce, - 0x14e0b705, -/* 0x092f: i2c_acquire */ - 0xf500f8d0, - 0xf4092321, - 0xd9f00421, - 0x3321f403, -/* 0x093e: i2c_release */ - 0x21f500f8, - 0x21f40923, - 0x03daf004, - 0xf83321f4, -/* 0x094d: i2c_recv */ - 0x0132f400, - 0xb6f8c1c7, - 0x16b00214, - 0x3a1ff528, - 0xf413a001, - 0x0032980c, - 0x0ccc13a0, - 0xf4003198, - 0xd0f90231, - 0xd0f9e0f9, - 0x000067f1, - 0x100063f1, - 0xbb016792, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x092f21f5, - 0xfc0464b6, - 0x00d6b0d0, - 0x00b31bf5, - 0xbb0057f0, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x08dc21f5, - 0xf50464b6, - 0xc700d011, - 0x76bbe0c5, - 0x0465b600, - 0x659450f9, - 0x0256bb04, - 0x75fd50bd, - 0xf550fc04, - 0xb6088121, - 0x11f50464, - 0x57f000ad, - 0x0076bb01, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b608dc, - 0x8a11f504, - 0x0076bb00, - 0xf90465b6, - 0x04659450, - 0xbd0256bb, - 0x0475fd50, - 0x21f550fc, - 0x64b6082f, - 0x6a11f404, - 0xbbe05bcb, - 0x65b60076, - 0x9450f904, - 0x56bb0465, - 0xfd50bd02, - 0x50fc0475, - 0x077421f5, - 0xb90464b6, - 0x74bd025b, -/* 0x0a53: i2c_recv_not_rd08 */ - 0xb0430ef4, - 0x1bf401d6, - 0x0057f03d, - 0x08dc21f5, - 0xc73311f4, - 0x21f5e0c5, - 0x11f40881, - 0x0057f029, - 0x08dc21f5, - 0xc71f11f4, - 0x21f5e0b5, - 0x11f40881, - 0x7421f515, - 0xc774bd07, - 0x1bf408c5, - 0x0232f409, -/* 0x0a93: i2c_recv_not_wr08 */ -/* 0x0a93: i2c_recv_done */ - 0xc7030ef4, - 0x21f5f8ce, - 0xe0fc093e, - 0x12f4d0fc, - 0x027cb90a, - 0x02f121f5, -/* 0x0aa8: i2c_recv_exit */ -/* 0x0aaa: i2c_init */ - 0x00f800f8, -/* 0x0aac: test_recv */ - 0x05d817f1, - 0xb60011cf, - 0x07f10110, - 0x01d005d8, - 0xf104bd00, - 0xf1d900e7, - 0xf5134fe3, - 0xf8022321, -/* 0x0acd: test_init */ - 0x00e7f100, - 0x2321f508, -/* 0x0ad7: idle_recv */ - 0xf800f802, -/* 0x0ad9: idle */ - 0x0031f400, - 0x05d417f1, - 0xb60011cf, - 0x07f10110, - 0x01d005d4, -/* 0x0aef: idle_loop */ - 0xf004bd00, - 0x32f45817, -/* 0x0af5: idle_proc */ -/* 0x0af5: idle_proc_exec */ - 0xb910f902, - 0x21f5021e, - 0x10fc02fa, - 0xf40911f4, - 0x0ef40231, -/* 0x0b09: idle_proc_next */ - 0x5810b6ef, - 0xf4061fb8, - 0x02f4e61b, - 0x0028f4dd, - 0x00c10ef4, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4 b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4 new file mode 100644 index 000000000000..2f28c7e26a14 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4 @@ -0,0 +1,70 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ + +#define NVKM_PPWR_CHIPSET GF119 +#define HW_TICKS_PER_US 324 + +//#define NVKM_FALCON_PC24 +#define NVKM_FALCON_UNSHIFTED_IO +//#define NVKM_FALCON_MMIO_UAS +//#define NVKM_FALCON_MMIO_TRAP + +#include "macros.fuc" + +.section #gf119_pmu_data +#define INCLUDE_PROC +#include "kernel.fuc" +#include "arith.fuc" +#include "host.fuc" +#include "memx.fuc" +#include "perf.fuc" +#include "i2c_.fuc" +#include "test.fuc" +#include "idle.fuc" +#undef INCLUDE_PROC + +#define INCLUDE_DATA +#include "kernel.fuc" +#include "arith.fuc" +#include "host.fuc" +#include "memx.fuc" +#include "perf.fuc" +#include "i2c_.fuc" +#include "test.fuc" +#include "idle.fuc" +#undef INCLUDE_DATA +.align 256 + +.section #gf119_pmu_code +#define INCLUDE_CODE +#include "kernel.fuc" +#include "arith.fuc" +#include "host.fuc" +#include "memx.fuc" +#include "perf.fuc" +#include "i2c_.fuc" +#include "test.fuc" +#include "idle.fuc" +#undef INCLUDE_CODE +.align 256 diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h new file mode 100644 index 000000000000..31552af9b06e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/gf119.fuc4.h @@ -0,0 +1,1795 @@ +uint32_t gf119_pmu_data[] = { +/* 0x0000: proc_kern */ + 0x52544e49, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0058: proc_list_head */ + 0x54534f48, + 0x0000049d, + 0x00000446, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x584d454d, + 0x0000068b, + 0x0000067d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x46524550, + 0x0000068f, + 0x0000068d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x5f433249, + 0x00000aaa, + 0x0000094d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x54534554, + 0x00000acd, + 0x00000aac, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x454c4449, + 0x00000ad9, + 0x00000ad7, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0268: proc_list_tail */ +/* 0x0268: time_prev */ + 0x00000000, +/* 0x026c: time_next */ + 0x00000000, +/* 0x0270: fifo_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x02f0: rfifo_queue */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0370: memx_func_head */ + 0x00000001, + 0x00000000, + 0x000004d3, +/* 0x037c: memx_func_next */ + 0x00000002, + 0x00000000, + 0x00000554, + 0x00000003, + 0x00000002, + 0x000005d8, + 0x00040004, + 0x00000000, + 0x000005f4, + 0x00010005, + 0x00000000, + 0x0000060e, + 0x00010006, + 0x00000000, + 0x000005d3, + 0x00000007, + 0x00000000, + 0x00000619, +/* 0x03c4: memx_func_tail */ +/* 0x03c4: memx_ts_start */ + 0x00000000, +/* 0x03c8: memx_ts_end */ + 0x00000000, +/* 0x03cc: memx_data_head */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0bcc: memx_data_tail */ +/* 0x0bcc: memx_train_head */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +/* 0x0ccc: memx_train_tail */ +/* 0x0ccc: i2c_scl_map */ + 0x00000400, + 0x00000800, + 0x00001000, + 0x00002000, + 0x00004000, + 0x00008000, + 0x00010000, + 0x00020000, + 0x00040000, + 0x00080000, +/* 0x0cf4: i2c_sda_map */ + 0x00100000, + 0x00200000, + 0x00400000, + 0x00800000, + 0x01000000, + 0x02000000, + 0x04000000, + 0x08000000, + 0x10000000, + 0x20000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +uint32_t gf119_pmu_code[] = { + 0x034d0ef5, +/* 0x0004: rd32 */ + 0x07a007f1, + 0xbd000ed0, + 0x01d7f004, + 0xf101d3f0, + 0xd007ac07, + 0x04bd000d, +/* 0x001c: rd32_wait */ + 0x07acd7f1, + 0xf100ddcf, + 0xf47000d4, + 0xd7f1f51b, + 0xddcf07a4, +/* 0x0033: wr32 */ + 0xf100f800, + 0xd007a007, + 0x04bd000e, + 0x07a407f1, + 0xbd000dd0, + 0x02d7f004, + 0xf0f0d5f0, + 0x07f101d3, + 0x0dd007ac, +/* 0x0057: wr32_wait */ + 0xf104bd00, + 0xcf07acd7, + 0xd4f100dd, + 0x1bf47000, +/* 0x0067: nsec */ + 0xf900f8f5, + 0xf080f990, + 0x88cf2c87, +/* 0x0071: nsec_loop */ + 0x2c97f000, + 0xbb0099cf, + 0x9eb80298, + 0xf41ef406, + 0x90fc80fc, +/* 0x0086: wait */ + 0x90f900f8, + 0x87f080f9, + 0x0088cf2c, +/* 0x0090: wait_loop */ + 0xf402eeb9, + 0xdab90421, + 0x04adfd02, + 0xf406acb8, + 0x97f0120b, + 0x0099cf2c, + 0xb80298bb, + 0x1ef4069b, +/* 0x00b1: wait_done */ + 0xfc80fce2, +/* 0x00b7: intr_watchdog */ + 0x9800f890, + 0x96b003e9, + 0x2a0bf400, + 0xbb9a0a98, + 0x1cf4029a, + 0x01d7f00f, + 0x028c21f5, + 0x0ef494bd, +/* 0x00d5: intr_watchdog_next_time */ + 0x9b0a9815, + 0xf400a6b0, + 0x9ab8090b, + 0x061cf406, +/* 0x00e4: intr_watchdog_next_time_set */ +/* 0x00e7: intr_watchdog_next_proc */ + 0x809b0980, + 0xe0b603e9, + 0x68e6b158, + 0xc61bf402, +/* 0x00f6: intr */ + 0x00f900f8, + 0x80f904bd, + 0xa0f990f9, + 0xc0f9b0f9, + 0xe0f9d0f9, + 0xf7f0f0f9, + 0x0188fe00, + 0x87f180f9, + 0x88cf05d0, + 0x0180b600, + 0x05d007f1, + 0xbd0008d0, + 0x0887f004, + 0xc40088cf, + 0x0bf40289, + 0x9b008020, + 0xf458e7f0, + 0x0998b721, + 0x0096b09b, + 0xf00e0bf4, + 0x09d03407, + 0x8004bd00, +/* 0x014e: intr_skip_watchdog */ + 0x89e49a09, + 0x0bf40800, + 0x8897f13c, + 0x0099cf06, + 0xf4029ac4, + 0xc7f1260b, + 0xcccf04c0, + 0xf1c0f900, + 0xf14f48e7, + 0xf05453e3, + 0x21f500d7, + 0xc0fc02f1, + 0x04c007f1, + 0xbd000cd0, +/* 0x0185: intr_subintr_skip_fifo */ + 0x8807f104, + 0x0009d006, +/* 0x018e: intr_skip_subintr */ + 0x89c404bd, + 0x070bf420, + 0xffbfa4f1, +/* 0x0198: intr_skip_pause */ + 0xf44089c4, + 0xa4f1070b, +/* 0x01a2: intr_skip_user0 */ + 0x07f0ffbf, + 0x0008d004, + 0x80fc04bd, + 0xfc0088fe, + 0xfce0fcf0, + 0xfcc0fcd0, + 0xfca0fcb0, + 0xfc80fc90, + 0x0032f400, +/* 0x01c6: ticks_from_ns */ + 0xc0f901f8, + 0xd7f1b0f9, + 0xd3f00144, + 0xb321f500, + 0xe8ccec03, + 0x00b4b003, + 0xec120bf4, + 0xf103e8ee, + 0xf00144d7, + 0x21f500d3, +/* 0x01ee: ticks_from_ns_quit */ + 0xceb903b3, + 0xfcb0fc02, +/* 0x01f7: ticks_from_us */ + 0xf900f8c0, + 0xf1b0f9c0, + 0xf00144d7, + 0x21f500d3, + 0xceb903b3, + 0x00b4b002, + 0xbd050bf4, +/* 0x0211: ticks_from_us_quit */ + 0xfcb0fce4, +/* 0x0217: ticks_to_us */ + 0xf100f8c0, + 0xf00144d7, + 0xedff00d3, +/* 0x0223: timer */ + 0xf900f8ec, + 0xf480f990, + 0xf8981032, + 0x0086b003, + 0xbd531cf4, + 0x3807f084, + 0xbd0008d0, + 0x3487f004, + 0x980088cf, + 0x98bb9a09, + 0x00e9bb02, + 0xf003fe80, + 0x88cf0887, + 0x0284f000, + 0xf0201bf4, + 0x88cf3487, + 0x06e0b800, + 0xb8090bf4, + 0x1cf406e8, +/* 0x026d: timer_reset */ + 0x3407f00e, + 0xbd000ed0, + 0x9a0e8004, +/* 0x0278: timer_enable */ + 0xf00187f0, + 0x08d03807, +/* 0x0283: timer_done */ + 0xf404bd00, + 0x80fc1031, + 0x00f890fc, +/* 0x028c: send_proc */ + 0x90f980f9, + 0x9805e898, + 0x86f004e9, + 0x0689b804, + 0xc42a0bf4, + 0x88940398, + 0x1880b604, + 0x98008ebb, + 0x8a8000fa, + 0x018d8000, + 0x80028c80, + 0x90b6038b, + 0x0794f001, + 0xf404e980, +/* 0x02c6: send_done */ + 0x90fc0231, + 0x00f880fc, +/* 0x02cc: find */ + 0x87f080f9, + 0x0131f458, +/* 0x02d4: find_loop */ + 0xb8008a98, + 0x0bf406ae, + 0x5880b610, + 0x026886b1, + 0xf4f01bf4, +/* 0x02ea: find_done */ + 0x8eb90132, + 0xf880fc02, +/* 0x02f1: send */ + 0xcc21f500, + 0x9701f402, +/* 0x02fa: recv */ + 0x90f900f8, + 0xe89880f9, + 0x04e99805, + 0xb80132f4, + 0x0bf40689, + 0x0389c43d, + 0xf00180b6, + 0xe8800784, + 0x02ea9805, + 0x8ffef0f9, + 0xb9f0f901, + 0x999402ef, + 0x00e9bb04, + 0x9818e0b6, + 0xec9803eb, + 0x01ed9802, + 0xf900ee98, + 0xfef0fca5, + 0x31f400f8, +/* 0x0347: recv_done */ + 0xfcf0fc01, + 0xf890fc80, +/* 0x034d: init */ + 0x0817f100, + 0x0011cf01, + 0x010911e7, + 0xfe0814b6, + 0x17f10014, + 0x13f000e0, + 0x1c07f000, + 0xbd0001d0, + 0xff17f004, + 0xd01407f0, + 0x04bd0001, + 0xf10217f0, + 0xf0080015, + 0x01d01007, + 0xf104bd00, + 0xf000f617, + 0x10fe0013, + 0x1031f400, + 0xf00117f0, + 0x01d03807, + 0xf004bd00, +/* 0x03a2: init_proc */ + 0xf19858f7, + 0x0016b001, + 0xf9fa0bf4, + 0x58f0b615, +/* 0x03b3: mulu32_32_64 */ + 0xf9f20ef4, + 0xf920f910, + 0x9540f930, + 0xd29510e1, + 0xbdc4bd10, + 0xc0edffb4, + 0xb9301dff, + 0x34f10234, + 0x34b6ffff, + 0x1045b610, + 0xbb00c3bb, + 0xe2ff01b4, + 0x0234b930, + 0xffff34f1, + 0xb61034b6, + 0xc3bb1045, + 0x01b4bb00, + 0xbb3012ff, + 0x40fc00b3, + 0x20fc30fc, + 0x00f810fc, +/* 0x0404: host_send */ + 0x04b017f1, + 0xf10011cf, + 0xcf04a027, + 0x12b80022, + 0x2f0bf406, + 0x94071ec4, + 0xe0b704ee, + 0xeb980270, + 0x02ec9803, + 0x9801ed98, + 0x21f500ee, + 0x10b602f1, + 0x0f1ec401, + 0x04b007f1, + 0xbd000ed0, + 0xc30ef404, +/* 0x0444: host_send_done */ +/* 0x0446: host_recv */ + 0x17f100f8, + 0x13f14e49, + 0xe1b85254, + 0xb30bf406, +/* 0x0454: host_recv_wait */ + 0x04cc17f1, + 0xf10011cf, + 0xcf04c827, + 0x16f00022, + 0x0612b808, + 0xc4ec0bf4, + 0x34b60723, + 0xf030b704, + 0x033b8002, + 0x80023c80, + 0x3e80013d, + 0x0120b600, + 0xf10f24f0, + 0xd004c807, + 0x04bd0002, + 0xf04027f0, + 0x02d00007, + 0xf804bd00, +/* 0x049d: host_init */ + 0x8017f100, + 0x1014b600, + 0x027015f1, + 0x04d007f1, + 0xbd0001d0, + 0x8017f104, + 0x1014b600, + 0x02f015f1, + 0x04dc07f1, + 0xbd0001d0, + 0x0117f004, + 0x04c407f1, + 0xbd0001d0, +/* 0x04d3: memx_func_enter */ + 0xf100f804, + 0xf1162067, + 0xf1f55d77, + 0xb9ffff73, + 0x21f4026e, + 0x02d8b904, + 0xf90487fd, + 0xfc80f960, + 0xf4e0fcd0, + 0x77f13321, + 0x73f1fffe, + 0x6eb9ffff, + 0x0421f402, + 0xfd02d8b9, + 0x60f90487, + 0xd0fc80f9, + 0x21f4e0fc, + 0xf067f133, + 0x026eb926, + 0xb90421f4, + 0x87fd02d8, + 0xf960f904, + 0xfcd0fc80, + 0x3321f4e0, + 0xf10467f0, + 0xd007e007, + 0x04bd0006, +/* 0x053c: memx_func_enter_wait */ + 0x07c067f1, + 0xf00066cf, + 0x0bf40464, + 0x2c67f0f6, + 0x800066cf, + 0x00f8f106, +/* 0x0554: memx_func_leave */ + 0xcf2c67f0, + 0x06800066, + 0x0467f0f2, + 0x07e407f1, + 0xbd0006d0, +/* 0x0569: memx_func_leave_wait */ + 0xc067f104, + 0x0066cf07, + 0xf40464f0, + 0x67f1f61b, + 0x77f126f0, + 0x73f00001, + 0x026eb900, + 0xb90421f4, + 0x87fd02d8, + 0xf960f905, + 0xfcd0fc80, + 0x3321f4e0, + 0x162067f1, + 0xf4026eb9, + 0xd8b90421, + 0x0587fd02, + 0x80f960f9, + 0xe0fcd0fc, + 0xf13321f4, + 0xf00aa277, + 0x6eb90073, + 0x0421f402, + 0xfd02d8b9, + 0x60f90587, + 0xd0fc80f9, + 0x21f4e0fc, +/* 0x05d3: memx_func_wait_vblank */ + 0xb600f833, + 0x00f80410, +/* 0x05d8: memx_func_wr32 */ + 0x98001698, + 0x10b60115, + 0xf960f908, + 0xfcd0fc50, + 0x3321f4e0, + 0xf40242b6, + 0x00f8e91b, +/* 0x05f4: memx_func_wait */ + 0xcf2c87f0, + 0x1e980088, + 0x011d9800, + 0x98021c98, + 0x10b6031b, + 0x8621f410, +/* 0x060e: memx_func_delay */ + 0x1e9800f8, + 0x0410b600, + 0xf86721f4, +/* 0x0619: memx_func_train */ +/* 0x061b: memx_exec */ + 0xf900f800, + 0xb9d0f9e0, + 0xb2b902c1, +/* 0x0625: memx_exec_next */ + 0x00139802, + 0xe70410b6, + 0xe701f034, + 0xb601e033, + 0x30f00132, + 0xde35980c, + 0x12b855f9, + 0xe41ef406, + 0x98f10b98, + 0xcbbbf20c, + 0xc4b7f102, + 0x00bbcf07, + 0xe0fcd0fc, + 0x02f121f5, +/* 0x065e: memx_info */ + 0xc67000f8, + 0x0e0bf401, +/* 0x0664: memx_info_data */ + 0x03ccc7f1, + 0x0800b7f1, +/* 0x066f: memx_info_train */ + 0xf10b0ef4, + 0xf10bccc7, +/* 0x0677: memx_info_send */ + 0xf50100b7, + 0xf802f121, +/* 0x067d: memx_recv */ + 0x01d6b000, + 0xb09b0bf4, + 0x0bf400d6, +/* 0x068b: memx_init */ + 0xf800f8d8, +/* 0x068d: perf_recv */ +/* 0x068f: perf_init */ + 0xf800f800, +/* 0x0691: i2c_drive_scl */ + 0x0036b000, + 0xf10e0bf4, + 0xd007e007, + 0x04bd0001, +/* 0x06a2: i2c_drive_scl_lo */ + 0x07f100f8, + 0x01d007e4, + 0xf804bd00, +/* 0x06ad: i2c_drive_sda */ + 0x0036b000, + 0xf10e0bf4, + 0xd007e007, + 0x04bd0002, +/* 0x06be: i2c_drive_sda_lo */ + 0x07f100f8, + 0x02d007e4, + 0xf804bd00, +/* 0x06c9: i2c_sense_scl */ + 0x0132f400, + 0x07c437f1, + 0xfd0033cf, + 0x0bf40431, + 0x0131f406, +/* 0x06dc: i2c_sense_scl_done */ +/* 0x06de: i2c_sense_sda */ + 0x32f400f8, + 0xc437f101, + 0x0033cf07, + 0xf40432fd, + 0x31f4060b, +/* 0x06f1: i2c_sense_sda_done */ +/* 0x06f3: i2c_raise_scl */ + 0xf900f801, + 0x9847f140, + 0x0137f008, + 0x069121f5, +/* 0x0700: i2c_raise_scl_wait */ + 0x03e8e7f1, + 0xf56721f4, + 0xf406c921, + 0x42b60901, + 0xef1bf401, +/* 0x0714: i2c_raise_scl_done */ + 0x00f840fc, +/* 0x0718: i2c_start */ + 0x06c921f5, + 0xf50d11f4, + 0xf406de21, + 0x0ef40611, +/* 0x0729: i2c_start_rep */ + 0x0037f030, + 0x069121f5, + 0xf50137f0, + 0xbb06ad21, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x06f321f5, + 0xf40464b6, +/* 0x0756: i2c_start_send */ + 0x37f01f11, + 0xad21f500, + 0x88e7f106, + 0x6721f413, + 0xf50037f0, + 0xf1069121, + 0xf41388e7, +/* 0x0772: i2c_start_out */ + 0x00f86721, +/* 0x0774: i2c_stop */ + 0xf50037f0, + 0xf0069121, + 0x21f50037, + 0xe7f106ad, + 0x21f403e8, + 0x0137f067, + 0x069121f5, + 0x1388e7f1, + 0xf06721f4, + 0x21f50137, + 0xe7f106ad, + 0x21f41388, +/* 0x07a7: i2c_bitw */ + 0xf500f867, + 0xf106ad21, + 0xf403e8e7, + 0x76bb6721, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb606f321, + 0x11f40464, + 0x88e7f118, + 0x6721f413, + 0xf50037f0, + 0xf1069121, + 0xf41388e7, +/* 0x07e6: i2c_bitw_out */ + 0x00f86721, +/* 0x07e8: i2c_bitr */ + 0xf50137f0, + 0xf106ad21, + 0xf403e8e7, + 0x76bb6721, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb606f321, + 0x11f40464, + 0xde21f51b, + 0x0037f006, + 0x069121f5, + 0x1388e7f1, + 0xf06721f4, + 0x31f4013c, +/* 0x082d: i2c_bitr_done */ +/* 0x082f: i2c_get_byte */ + 0xf000f801, + 0x47f00057, +/* 0x0835: i2c_get_byte_next */ + 0x0154b608, + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0xe821f550, + 0x0464b607, + 0xfd2b11f4, + 0x42b60553, + 0xd81bf401, + 0xbb0137f0, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x07a721f5, +/* 0x087f: i2c_get_byte_done */ + 0xf80464b6, +/* 0x0881: i2c_put_byte */ + 0x0847f000, +/* 0x0884: i2c_put_byte_next */ + 0xff0142b6, + 0x76bb3854, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb607a721, + 0x11f40464, + 0x0046b034, + 0xbbd81bf4, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x07e821f5, + 0xf40464b6, + 0x76bb0f11, + 0x0136b000, + 0xf4061bf4, +/* 0x08da: i2c_put_byte_done */ + 0x00f80132, +/* 0x08dc: i2c_addr */ + 0xb60076bb, + 0x50f90465, + 0xbb046594, + 0x50bd0256, + 0xfc0475fd, + 0x1821f550, + 0x0464b607, + 0xe72911f4, + 0xb6012ec3, + 0x53fd0134, + 0x0076bb05, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b60881, +/* 0x0921: i2c_addr_done */ +/* 0x0923: i2c_acquire_addr */ + 0xc700f804, + 0xe4b6f8ce, + 0x14e0b705, +/* 0x092f: i2c_acquire */ + 0xf500f8d0, + 0xf4092321, + 0xd9f00421, + 0x3321f403, +/* 0x093e: i2c_release */ + 0x21f500f8, + 0x21f40923, + 0x03daf004, + 0xf83321f4, +/* 0x094d: i2c_recv */ + 0x0132f400, + 0xb6f8c1c7, + 0x16b00214, + 0x3a1ff528, + 0xf413a001, + 0x0032980c, + 0x0ccc13a0, + 0xf4003198, + 0xd0f90231, + 0xd0f9e0f9, + 0x000067f1, + 0x100063f1, + 0xbb016792, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x092f21f5, + 0xfc0464b6, + 0x00d6b0d0, + 0x00b31bf5, + 0xbb0057f0, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x08dc21f5, + 0xf50464b6, + 0xc700d011, + 0x76bbe0c5, + 0x0465b600, + 0x659450f9, + 0x0256bb04, + 0x75fd50bd, + 0xf550fc04, + 0xb6088121, + 0x11f50464, + 0x57f000ad, + 0x0076bb01, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b608dc, + 0x8a11f504, + 0x0076bb00, + 0xf90465b6, + 0x04659450, + 0xbd0256bb, + 0x0475fd50, + 0x21f550fc, + 0x64b6082f, + 0x6a11f404, + 0xbbe05bcb, + 0x65b60076, + 0x9450f904, + 0x56bb0465, + 0xfd50bd02, + 0x50fc0475, + 0x077421f5, + 0xb90464b6, + 0x74bd025b, +/* 0x0a53: i2c_recv_not_rd08 */ + 0xb0430ef4, + 0x1bf401d6, + 0x0057f03d, + 0x08dc21f5, + 0xc73311f4, + 0x21f5e0c5, + 0x11f40881, + 0x0057f029, + 0x08dc21f5, + 0xc71f11f4, + 0x21f5e0b5, + 0x11f40881, + 0x7421f515, + 0xc774bd07, + 0x1bf408c5, + 0x0232f409, +/* 0x0a93: i2c_recv_not_wr08 */ +/* 0x0a93: i2c_recv_done */ + 0xc7030ef4, + 0x21f5f8ce, + 0xe0fc093e, + 0x12f4d0fc, + 0x027cb90a, + 0x02f121f5, +/* 0x0aa8: i2c_recv_exit */ +/* 0x0aaa: i2c_init */ + 0x00f800f8, +/* 0x0aac: test_recv */ + 0x05d817f1, + 0xb60011cf, + 0x07f10110, + 0x01d005d8, + 0xf104bd00, + 0xf1d900e7, + 0xf5134fe3, + 0xf8022321, +/* 0x0acd: test_init */ + 0x00e7f100, + 0x2321f508, +/* 0x0ad7: idle_recv */ + 0xf800f802, +/* 0x0ad9: idle */ + 0x0031f400, + 0x05d417f1, + 0xb60011cf, + 0x07f10110, + 0x01d005d4, +/* 0x0aef: idle_loop */ + 0xf004bd00, + 0x32f45817, +/* 0x0af5: idle_proc */ +/* 0x0af5: idle_proc_exec */ + 0xb910f902, + 0x21f5021e, + 0x10fc02fa, + 0xf40911f4, + 0x0ef40231, +/* 0x0b09: idle_proc_next */ + 0x5810b6ef, + 0xf4061fb8, + 0x02f4e61b, + 0x0028f4dd, + 0x00c10ef4, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c index 78a4ea0101f1..aeb8ccd891fc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.c @@ -24,17 +24,16 @@ #include "priv.h" #include "fuc/gf100.fuc3.h" -struct nvkm_oclass * -gf100_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = _nvkm_pmu_init, - .fini = _nvkm_pmu_fini, - }, +static const struct nvkm_pmu_func +gf100_pmu = { .code.data = gf100_pmu_code, .code.size = sizeof(gf100_pmu_code), .data.data = gf100_pmu_data, .data.size = sizeof(gf100_pmu_data), -}.base; +}; + +int +gf100_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gf100_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c deleted file mode 100644 index 6b3a23839ff0..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf110.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright 2013 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" -#include "fuc/gf110.fuc4.h" - -struct nvkm_oclass * -gf110_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0xd0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = _nvkm_pmu_init, - .fini = _nvkm_pmu_fini, - }, - .code.data = gf110_pmu_code, - .code.size = sizeof(gf110_pmu_code), - .data.data = gf110_pmu_data, - .data.size = sizeof(gf110_pmu_data), -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c new file mode 100644 index 000000000000..fbc88d8ecd4d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.c @@ -0,0 +1,39 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" +#include "fuc/gf119.fuc4.h" + +static const struct nvkm_pmu_func +gf119_pmu = { + .code.data = gf119_pmu_code, + .code.size = sizeof(gf119_pmu_code), + .data.data = gf119_pmu_data, + .data.size = sizeof(gf119_pmu_data), +}; + +int +gf119_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gf119_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index bea283314240..584299737658 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -21,10 +21,10 @@ * * Authors: Ben Skeggs */ -#define gf110_pmu_code gk104_pmu_code -#define gf110_pmu_data gk104_pmu_data +#define gf119_pmu_code gk104_pmu_code +#define gf119_pmu_data gk104_pmu_data #include "priv.h" -#include "fuc/gf110.fuc4.h" +#include "fuc/gf119.fuc4.h" #include #include @@ -103,18 +103,17 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable) } } -struct nvkm_oclass * -gk104_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0xe4), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = _nvkm_pmu_init, - .fini = _nvkm_pmu_fini, - }, +static const struct nvkm_pmu_func +gk104_pmu = { .code.data = gk104_pmu_code, .code.size = sizeof(gk104_pmu_code), .data.data = gk104_pmu_data, .data.size = sizeof(gk104_pmu_data), .pgob = gk104_pmu_pgob, -}.base; +}; + +int +gk104_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gk104_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c index 162c007d49c8..ae255247c9d1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c @@ -21,10 +21,10 @@ * * Authors: Ben Skeggs */ -#define gf110_pmu_code gk110_pmu_code -#define gf110_pmu_data gk110_pmu_data +#define gf119_pmu_code gk110_pmu_code +#define gf119_pmu_data gk110_pmu_data #include "priv.h" -#include "fuc/gf110.fuc4.h" +#include "fuc/gf119.fuc4.h" #include @@ -82,18 +82,17 @@ gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable) nvkm_rd32(device, 0x000200); } -struct nvkm_oclass * -gk110_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0xf0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = _nvkm_pmu_init, - .fini = _nvkm_pmu_fini, - }, +static const struct nvkm_pmu_func +gk110_pmu = { .code.data = gk110_pmu_code, .code.size = sizeof(gk110_pmu_code), .data.data = gk110_pmu_data, .data.size = sizeof(gk110_pmu_data), .pgob = gk110_pmu_pgob, -}.base; +}; + +int +gk110_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gk110_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c index b14134ef9ea5..3b4917637902 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.c @@ -24,18 +24,17 @@ #include "priv.h" #include "fuc/gk208.fuc5.h" -struct nvkm_oclass * -gk208_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0x00), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = _nvkm_pmu_init, - .fini = _nvkm_pmu_fini, - }, +static const struct nvkm_pmu_func +gk208_pmu = { .code.data = gk208_pmu_code, .code.size = sizeof(gk208_pmu_code), .data.data = gk208_pmu_data, .data.size = sizeof(gk208_pmu_data), .pgob = gk110_pmu_pgob, -}.base; +}; + +int +gk208_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gk208_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index bf3c53851352..860c8bc2b422 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -19,6 +19,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ +#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base.subdev) #include "priv.h" #include @@ -165,27 +166,24 @@ resched: } static int -gk20a_pmu_fini(struct nvkm_object *object, bool suspend) +gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend) { - struct gk20a_pmu *pmu = (void *)object; - + struct gk20a_pmu *pmu = gk20a_pmu(subdev); nvkm_timer_alarm_cancel(pmu, &pmu->alarm); + return 0; +} - return nvkm_subdev_fini_old(&pmu->base.subdev, suspend); +static void * +gk20a_pmu_dtor(struct nvkm_subdev *subdev) +{ + return gk20a_pmu(subdev); } static int -gk20a_pmu_init(struct nvkm_object *object) +gk20a_pmu_init(struct nvkm_subdev *subdev) { - struct gk20a_pmu *pmu = (void *)object; + struct gk20a_pmu *pmu = gk20a_pmu(subdev); struct nvkm_device *device = pmu->base.subdev.device; - int ret; - - ret = nvkm_subdev_init_old(&pmu->base.subdev); - if (ret) - return ret; - - pmu->base.pgob = nvkm_pmu_pgob; /* init pwr perf counter */ nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); @@ -193,7 +191,7 @@ gk20a_pmu_init(struct nvkm_object *object) nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm); - return ret; + return 0; } static struct gk20a_pmu_dvfs_data @@ -203,32 +201,26 @@ gk20a_dvfs_data= { .p_smooth = 1, }; -static int -gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +static const struct nvkm_subdev_func +gk20a_pmu = { + .init = gk20a_pmu_init, + .fini = gk20a_pmu_fini, + .dtor = gk20a_pmu_dtor, +}; + +int +gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) { + static const struct nvkm_pmu_func func = {}; struct gk20a_pmu *pmu; - int ret; - ret = nvkm_pmu_create(parent, engine, oclass, &pmu); - *pobject = nv_object(pmu); - if (ret) - return ret; + if (!(pmu = kzalloc(sizeof(*pmu), GFP_KERNEL))) + return -ENOMEM; + pmu->base.func = &func; + *ppmu = &pmu->base; + nvkm_subdev_ctor(&gk20a_pmu, device, index, 0, &pmu->base.subdev); pmu->data = &gk20a_dvfs_data; - nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work); return 0; } - -struct nvkm_oclass * -gk20a_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk20a_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = gk20a_pmu_init, - .fini = gk20a_pmu_fini, - }, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c new file mode 100644 index 000000000000..31b8692b4641 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.c @@ -0,0 +1,41 @@ +/* + * Copyright 2013 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" +#define gk208_pmu_code gm107_pmu_code +#define gk208_pmu_data gm107_pmu_data +#include "fuc/gk208.fuc5.h" + +static const struct nvkm_pmu_func +gm107_pmu = { + .code.data = gm107_pmu_code, + .code.size = sizeof(gm107_pmu_code), + .data.data = gm107_pmu_data, + .data.size = sizeof(gm107_pmu_data), +}; + +int +gm107_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(&gm107_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c index 223f9fb9f44f..8ba7fa4ca75b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c @@ -24,27 +24,25 @@ #include "priv.h" #include "fuc/gt215.fuc3.h" -static int -gt215_pmu_init(struct nvkm_object *object) +static void +gt215_pmu_reset(struct nvkm_pmu *pmu) { - struct nvkm_pmu *pmu = (void *)object; struct nvkm_device *device = pmu->subdev.device; nvkm_mask(device, 0x022210, 0x00000001, 0x00000000); nvkm_mask(device, 0x022210, 0x00000001, 0x00000001); - return nvkm_pmu_init(pmu); } -struct nvkm_oclass * -gt215_pmu_oclass = &(struct nvkm_pmu_impl) { - .base.handle = NV_SUBDEV(PMU, 0xa3), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = _nvkm_pmu_ctor, - .dtor = _nvkm_pmu_dtor, - .init = gt215_pmu_init, - .fini = _nvkm_pmu_fini, - }, +static const struct nvkm_pmu_func +gt215_pmu = { + .reset = gt215_pmu_reset, .code.data = gt215_pmu_code, .code.size = sizeof(gt215_pmu_code), .data.data = gt215_pmu_data, .data.size = sizeof(gt215_pmu_data), -}.base; +}; + +int +gt215_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu) +{ + return nvkm_pmu_new_(>215_pmu, device, index, ppmu); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c index 556aefe3614f..e6f74168238c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.c @@ -47,8 +47,8 @@ nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx) u32 reply[2]; int ret; - ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, - MEMX_INFO_DATA, 0); + ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, + MEMX_INFO_DATA, 0); if (ret) return ret; @@ -85,8 +85,8 @@ nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec) /* call MEMX process to execute the script, and wait for reply */ if (exec) { - pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC, - memx->base, finish); + nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC, + memx->base, finish); } nvkm_debug(subdev, "Exec took %uns, PMU_IN %08x\n", @@ -168,8 +168,8 @@ nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize) u32 reply[2], base, size, i; int ret; - ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, - MEMX_INFO_TRAIN, 0); + ret = nvkm_pmu_send(pmu, reply, PROC_MEMX, MEMX_MSG_INFO, + MEMX_INFO_TRAIN, 0); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h index 799e7c8b88f5..f38c88fae3d6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/priv.h @@ -1,38 +1,20 @@ #ifndef __NVKM_PMU_PRIV_H__ #define __NVKM_PMU_PRIV_H__ +#define nvkm_pmu(p) container_of((p), struct nvkm_pmu, subdev) #include #include -#define nvkm_pmu_create(p, e, o, d) \ - nvkm_pmu_create_((p), (e), (o), sizeof(**d), (void **)d) -#define nvkm_pmu_destroy(p) \ - nvkm_subdev_destroy(&(p)->base) -#define nvkm_pmu_init(p) ({ \ - struct nvkm_pmu *_pmu = (p); \ - _nvkm_pmu_init(nv_object(_pmu)); \ -}) -#define nvkm_pmu_fini(p,s) ({ \ - struct nvkm_pmu *_pmu = (p); \ - _nvkm_pmu_fini(nv_object(_pmu), (s)); \ -}) +int nvkm_pmu_new_(const struct nvkm_pmu_func *, struct nvkm_device *, + int index, struct nvkm_pmu **); -int nvkm_pmu_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int, void **); +struct nvkm_pmu_func { + void (*reset)(struct nvkm_pmu *); -int _nvkm_pmu_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -#define _nvkm_pmu_dtor _nvkm_subdev_dtor -int _nvkm_pmu_init(struct nvkm_object *); -int _nvkm_pmu_fini(struct nvkm_object *, bool); -void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable); - -struct nvkm_pmu_impl { - struct nvkm_oclass base; struct { u32 *data; u32 size; } code; + struct { u32 *data; u32 size; -- cgit v1.2.3 From 31649ecf47a44e02e73bffc5680c8f56d6cf587a Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:21 +1000 Subject: drm/nouveau/tmr: convert to new-style nvkm_subdev Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/include/nvkm/subdev/timer.h | 54 ++--- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 138 ++++++------- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 - drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 -- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 -- drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c | 7 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c | 127 +++++++++++- drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c | 45 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c | 227 ++++++--------------- drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h | 25 --- drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c | 88 ++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c | 85 ++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h | 22 ++ .../gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h | 7 + 27 files changed, 501 insertions(+), 427 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index f818adcc7467..62ed0880b0e1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -9,15 +9,23 @@ struct nvkm_alarm { }; static inline void -nvkm_alarm_init(struct nvkm_alarm *alarm, - void (*func)(struct nvkm_alarm *)) +nvkm_alarm_init(struct nvkm_alarm *alarm, void (*func)(struct nvkm_alarm *)) { INIT_LIST_HEAD(&alarm->head); alarm->func = func; } -void nvkm_timer_alarm(void *, u32 nsec, struct nvkm_alarm *); -void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); +struct nvkm_timer { + const struct nvkm_timer_func *func; + struct nvkm_subdev subdev; + + struct list_head alarms; + spinlock_t lock; +}; + +u64 nvkm_timer_read(struct nvkm_timer *); +void nvkm_timer_alarm(struct nvkm_timer *, u32 nsec, struct nvkm_alarm *); +void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *); /* Delay based on GPU time (ie. PTIMER). * @@ -31,13 +39,13 @@ void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); #define nvkm_nsec(d,n,cond...) ({ \ struct nvkm_device *_device = (d); \ struct nvkm_timer *_tmr = _device->timer; \ - u64 _nsecs = (n), _time0 = _tmr->read(_tmr); \ + u64 _nsecs = (n), _time0 = nvkm_timer_read(_tmr); \ s64 _taken = 0; \ - bool _warn = true; \ + bool _warn = true; \ \ do { \ cond \ - } while (_taken = _tmr->read(_tmr) - _time0, _taken < _nsecs); \ + } while (_taken = nvkm_timer_read(_tmr) - _time0, _taken < _nsecs); \ \ if (_taken >= _nsecs) { \ if (_warn) { \ @@ -51,32 +59,8 @@ void nvkm_timer_alarm_cancel(void *, struct nvkm_alarm *); #define nvkm_usec(d,u,cond...) nvkm_nsec((d), (u) * 1000, ##cond) #define nvkm_msec(d,m,cond...) nvkm_usec((d), (m) * 1000, ##cond) -struct nvkm_timer { - struct nvkm_subdev subdev; - u64 (*read)(struct nvkm_timer *); - void (*alarm)(struct nvkm_timer *, u64 time, struct nvkm_alarm *); - void (*alarm_cancel)(struct nvkm_timer *, struct nvkm_alarm *); -}; - -static inline struct nvkm_timer * -nvkm_timer(void *obj) -{ - return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_TIMER); -} - -#define nvkm_timer_create(p,e,o,d) \ - nvkm_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \ - sizeof(**d), (void **)d) -#define nvkm_timer_destroy(p) \ - nvkm_subdev_destroy(&(p)->subdev) -#define nvkm_timer_init(p) \ - nvkm_subdev_init_old(&(p)->subdev) -#define nvkm_timer_fini(p,s) \ - nvkm_subdev_fini_old(&(p)->subdev, (s)) - -int nvkm_timer_create_(struct nvkm_object *, struct nvkm_engine *, - struct nvkm_oclass *, int size, void **); - -extern struct nvkm_oclass nv04_timer_oclass; -extern struct nvkm_oclass gk20a_timer_oclass; +int nv04_timer_new(struct nvkm_device *, int, struct nvkm_timer **); +int nv40_timer_new(struct nvkm_device *, int, struct nvkm_timer **); +int nv41_timer_new(struct nvkm_device *, int, struct nvkm_timer **); +int gk20a_timer_new(struct nvkm_device *, int, struct nvkm_timer **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 3734d1fb7756..04895322d371 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -85,7 +85,7 @@ nv4_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv04_fifo_new, @@ -105,7 +105,7 @@ nv5_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv04_fifo_new, @@ -126,7 +126,7 @@ nv10_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .gr = nv10_gr_new, @@ -145,7 +145,7 @@ nv11_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv10_fifo_new, @@ -166,7 +166,7 @@ nv15_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv10_fifo_new, @@ -187,7 +187,7 @@ nv17_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -208,7 +208,7 @@ nv18_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -229,7 +229,7 @@ nv1a_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv10_fifo_new, @@ -250,7 +250,7 @@ nv1f_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -271,7 +271,7 @@ nv20_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -292,7 +292,7 @@ nv25_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -313,7 +313,7 @@ nv28_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -334,7 +334,7 @@ nv2a_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -355,7 +355,7 @@ nv30_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -376,7 +376,7 @@ nv31_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -398,7 +398,7 @@ nv34_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -420,7 +420,7 @@ nv35_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -441,7 +441,7 @@ nv36_chipset = { .imem = nv04_instmem_new, .mc = nv04_mc_new, .mmu = nv04_mmu_new, -// .timer = nv04_timer_new, + .timer = nv04_timer_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, // .fifo = nv17_fifo_new, @@ -464,7 +464,7 @@ nv40_chipset = { .mc = nv40_mc_new, .mmu = nv04_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv40_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -489,7 +489,7 @@ nv41_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -514,7 +514,7 @@ nv42_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -539,7 +539,7 @@ nv43_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -564,7 +564,7 @@ nv44_chipset = { .mc = nv44_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -589,7 +589,7 @@ nv45_chipset = { .mc = nv40_mc_new, .mmu = nv04_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -614,7 +614,7 @@ nv46_chipset = { .mc = nv44_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -639,7 +639,7 @@ nv47_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -664,7 +664,7 @@ nv49_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -689,7 +689,7 @@ nv4a_chipset = { .mc = nv44_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -714,7 +714,7 @@ nv4b_chipset = { .mc = nv40_mc_new, .mmu = nv41_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -739,7 +739,7 @@ nv4c_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -764,7 +764,7 @@ nv4e_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -792,7 +792,7 @@ nv50_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = nv50_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv50_disp_new, // .dma = nv50_dma_new, @@ -817,7 +817,7 @@ nv63_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -842,7 +842,7 @@ nv67_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -867,7 +867,7 @@ nv68_chipset = { .mc = nv4c_mc_new, .mmu = nv44_mmu_new, .therm = nv40_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = nv04_disp_new, // .dma = nv04_dma_new, @@ -895,7 +895,7 @@ nv84_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -926,7 +926,7 @@ nv86_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -957,7 +957,7 @@ nv92_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -988,7 +988,7 @@ nv94_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -1015,7 +1015,7 @@ nv96_chipset = { .devinit = g84_devinit_new, .mc = g94_mc_new, .bus = g94_bus_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, .fb = g84_fb_new, .imem = nv50_instmem_new, .mmu = nv50_mmu_new, @@ -1046,7 +1046,7 @@ nv98_chipset = { .devinit = g98_devinit_new, .mc = g98_mc_new, .bus = g94_bus_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, .fb = g84_fb_new, .imem = nv50_instmem_new, .mmu = nv50_mmu_new, @@ -1081,7 +1081,7 @@ nva0_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .bsp = g84_bsp_new, // .cipher = g84_cipher_new, @@ -1113,7 +1113,7 @@ nva3_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1146,7 +1146,7 @@ nva5_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1178,7 +1178,7 @@ nva8_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1209,7 +1209,7 @@ nvaa_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = g94_disp_new, // .dma = nv50_dma_new, @@ -1240,7 +1240,7 @@ nvac_chipset = { .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, .therm = g84_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .disp = g94_disp_new, // .dma = nv50_dma_new, @@ -1272,7 +1272,7 @@ nvaf_chipset = { .mxm = nv50_mxm_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gt215_ce_new, // .disp = gt215_disp_new, @@ -1306,7 +1306,7 @@ nvc0_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1341,7 +1341,7 @@ nvc1_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gt215_disp_new, @@ -1375,7 +1375,7 @@ nvc3_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gt215_disp_new, @@ -1409,7 +1409,7 @@ nvc4_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1444,7 +1444,7 @@ nvc8_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1479,7 +1479,7 @@ nvce_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .ce[1] = gf100_ce1_new, @@ -1514,7 +1514,7 @@ nvcf_chipset = { .mxm = nv50_mxm_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gt215_disp_new, @@ -1547,7 +1547,7 @@ nvd7_chipset = { .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .ce[0] = gf100_ce0_new, // .disp = gf119_disp_new, // .dma = gf119_dma_new, @@ -1580,7 +1580,7 @@ nvd9_chipset = { .mxm = nv50_mxm_new, .pmu = gf119_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gf100_ce0_new, // .disp = gf119_disp_new, @@ -1614,7 +1614,7 @@ nve4_chipset = { .mxm = nv50_mxm_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1650,7 +1650,7 @@ nve6_chipset = { .mxm = nv50_mxm_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1686,7 +1686,7 @@ nve7_chipset = { .mxm = nv50_mxm_new, .pmu = gf119_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1716,7 +1716,7 @@ nvea_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .pmu = gk20a_pmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .volt = gk20a_volt_new, // .ce[2] = gk104_ce2_new, // .dma = gf119_dma_new, @@ -1746,7 +1746,7 @@ nvf0_chipset = { .mxm = nv50_mxm_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1782,7 +1782,7 @@ nvf1_chipset = { .mxm = nv50_mxm_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1818,7 +1818,7 @@ nv106_chipset = { .mxm = nv50_mxm_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1853,7 +1853,7 @@ nv108_chipset = { .mxm = nv50_mxm_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, -// .timer = nv04_timer_new, + .timer = nv41_timer_new, // .volt = nv40_volt_new, // .ce[0] = gk104_ce0_new, // .ce[1] = gk104_ce1_new, @@ -1888,7 +1888,7 @@ nv117_chipset = { .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, .therm = gm107_therm_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[0] = gk104_ce0_new, // .ce[2] = gk104_ce2_new, // .disp = gm107_disp_new, @@ -1916,7 +1916,7 @@ nv124_chipset = { .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, // .ce[2] = gm204_ce2_new, @@ -1945,7 +1945,7 @@ nv126_chipset = { .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, .pmu = gm107_pmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, // .ce[2] = gm204_ce2_new, @@ -1969,7 +1969,7 @@ nv12b_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mmu = gf100_mmu_new, -// .timer = gk20a_timer_new, + .timer = gk20a_timer_new, // .ce[2] = gm204_ce2_new, // .dma = gf119_dma_new, // .fifo = gm20b_fifo_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index dcaa480cd310..28421e6f1f26 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xc0: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -43,7 +42,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc4: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -58,7 +56,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc3: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -72,7 +69,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xce: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -87,7 +83,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xcf: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -101,7 +96,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc1: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -115,7 +109,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; case 0xc8: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -130,7 +123,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xd9: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; @@ -144,7 +136,6 @@ gf100_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; case 0xd7: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index 048f1beab81d..25d9092455aa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -28,7 +28,6 @@ gk104_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xe4: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -44,7 +43,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -60,7 +58,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -76,7 +73,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; @@ -86,7 +82,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; break; case 0xf0: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -102,7 +97,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; @@ -118,7 +112,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; @@ -133,7 +126,6 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass; break; case 0x108: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index e2d00b465b80..4b570a27e13a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -28,7 +28,6 @@ gm100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x117: - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -54,7 +53,6 @@ gm100_identify(struct nvkm_device *device) /* looks to be some non-trivial changes */ /* priv ring says no to 0x10eb14 writes */ #endif - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif @@ -77,7 +75,6 @@ gm100_identify(struct nvkm_device *device) /* looks to be some non-trivial changes */ /* priv ring says no to 0x10eb14 writes */ #endif - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif @@ -97,7 +94,6 @@ gm100_identify(struct nvkm_device *device) break; case 0x12b: - device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 99e837f4879e..1b2ebda82c1f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -28,7 +28,6 @@ nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; @@ -36,7 +35,6 @@ nv04_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x05: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 6f106f632e63..c5ecdddfbce3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -28,13 +28,11 @@ nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x15: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -42,7 +40,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x16: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -50,7 +47,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1a: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -58,7 +54,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x11: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -66,7 +61,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x17: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -74,7 +68,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x1f: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -82,7 +75,6 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x18: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index 2a84c3ff8538..104ed4f093b5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -28,7 +28,6 @@ nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -36,7 +35,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x25: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -44,7 +42,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x28: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -52,7 +49,6 @@ nv20_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x2a: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index b03249099bb5..5ea263c85043 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -28,7 +28,6 @@ nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -36,7 +35,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x35: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -44,7 +42,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x31: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -53,7 +50,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x36: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; @@ -62,7 +58,6 @@ nv30_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; break; case 0x34: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 5aa4cac00402..31df1b8ae705 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -28,7 +28,6 @@ nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -39,7 +38,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -50,7 +48,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -61,7 +58,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -72,7 +68,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -83,7 +78,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -94,7 +88,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -105,7 +98,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -116,7 +108,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -127,7 +118,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -138,7 +128,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -149,7 +138,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -160,7 +148,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -171,7 +158,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -182,7 +168,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; @@ -193,7 +178,6 @@ nv40_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 8cc924046b78..e01add48ceb3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -28,7 +28,6 @@ nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; @@ -39,7 +38,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -53,7 +51,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x86: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -67,7 +64,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x92: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -81,7 +77,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x94: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -95,7 +90,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x96: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -109,7 +103,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x98: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -123,7 +116,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa0: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -137,7 +129,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; break; case 0xaa: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -151,7 +142,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xac: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -165,7 +155,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa3: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -180,7 +169,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa5: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -194,7 +182,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa8: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; @@ -208,7 +195,6 @@ nv50_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xaf: - device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index c5da091c058c..a9df61bf3780 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -118,14 +118,13 @@ static int nvkm_udevice_time(struct nvkm_udevice *udev, void *data, u32 size) { struct nvkm_device *device = udev->device; - struct nvkm_timer *tmr = device->timer; union { struct nv_device_time_v0 v0; } *args = data; int ret; if (nvif_unpack(args->v0, 0, 0, false)) { - args->v0.time = tmr->read(tmr); + args->v0.time = nvkm_timer_read(device->timer); } return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 403d2c9aff3b..2a5bc9270fb9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -218,7 +218,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) spin_lock_irqsave(&gr->lock, flags); nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); - start = tmr->read(tmr); + start = nvkm_timer_read(tmr); do { idle = true; @@ -237,7 +237,7 @@ g84_gr_tlb_flush(struct nvkm_engine *engine) idle = false; } } while (!idle && - !(timeout = tmr->read(tmr) - start > 2000000000)); + !(timeout = nvkm_timer_read(tmr) - start > 2000000000)); if (timeout) { nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c index 860c8bc2b422..6689d0290a7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c @@ -124,6 +124,7 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) struct nvkm_subdev *subdev = &pmu->base.subdev; struct nvkm_device *device = subdev->device; struct nvkm_clk *clk = device->clk; + struct nvkm_timer *tmr = device->timer; struct nvkm_volt *volt = device->volt; u32 utilization = 0; int state, ret; @@ -162,14 +163,14 @@ gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm) resched: gk20a_pmu_dvfs_reset_dev_status(pmu); - nvkm_timer_alarm(pmu, 100000000, alarm); + nvkm_timer_alarm(tmr, 100000000, alarm); } static int gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend) { struct gk20a_pmu *pmu = gk20a_pmu(subdev); - nvkm_timer_alarm_cancel(pmu, &pmu->alarm); + nvkm_timer_alarm_cancel(subdev->device->timer, &pmu->alarm); return 0; } @@ -190,7 +191,7 @@ gk20a_pmu_init(struct nvkm_subdev *subdev) nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); - nvkm_timer_alarm(pmu, 2000000000, &pmu->alarm); + nvkm_timer_alarm(device->timer, 2000000000, &pmu->alarm); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index 304bdfc54445..949dc6101a58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -102,7 +102,7 @@ nvkm_therm_update(struct nvkm_therm *therm, int mode) switch (mode) { case NVKM_THERM_CTRL_MANUAL: - tmr->alarm_cancel(tmr, &therm->alarm); + nvkm_timer_alarm_cancel(tmr, &therm->alarm); duty = nvkm_therm_fan_get(therm); if (duty < 0) duty = 100; @@ -126,12 +126,12 @@ nvkm_therm_update(struct nvkm_therm *therm, int mode) break; case NVKM_THERM_CTRL_NONE: default: - tmr->alarm_cancel(tmr, &therm->alarm); + nvkm_timer_alarm_cancel(tmr, &therm->alarm); poll = false; } if (list_empty(&therm->alarm.head) && poll) - tmr->alarm(tmr, 1000000000ULL, &therm->alarm); + nvkm_timer_alarm(tmr, 1000000000ULL, &therm->alarm); spin_unlock_irqrestore(&therm->lock, flags); if (duty >= 0) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c index a2be18167770..91198d79393a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.c @@ -95,7 +95,7 @@ nvkm_fan_update(struct nvkm_fan *fan, bool immediate, int target) else delay = bump_period; - tmr->alarm(tmr, delay * 1000 * 1000, &fan->alarm); + nvkm_timer_alarm(tmr, delay * 1000 * 1000, &fan->alarm); } return ret; @@ -139,7 +139,7 @@ nvkm_therm_fan_sense(struct nvkm_therm *therm) * When the fan spins, it changes the value of GPIO FAN_SENSE. * We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation. */ - start = tmr->read(tmr); + start = nvkm_timer_read(tmr); prev = nvkm_gpio_get(gpio, 0, therm->fan->tach.func, therm->fan->tach.line); cycles = 0; @@ -150,12 +150,12 @@ nvkm_therm_fan_sense(struct nvkm_therm *therm) therm->fan->tach.line); if (prev != cur) { if (!start) - start = tmr->read(tmr); + start = nvkm_timer_read(tmr); cycles++; prev = cur; } - } while (cycles < 5 && tmr->read(tmr) - start < 250000000); - end = tmr->read(tmr); + } while (cycles < 5 && nvkm_timer_read(tmr) - start < 250000000); + end = nvkm_timer_read(tmr); if (cycles == 5) { tach = (u64)60000000000ULL; @@ -215,7 +215,7 @@ nvkm_therm_fan_fini(struct nvkm_therm *therm, bool suspend) { struct nvkm_timer *tmr = therm->subdev.device->timer; if (suspend) - tmr->alarm_cancel(tmr, &therm->fan->alarm); + nvkm_timer_alarm_cancel(tmr, &therm->fan->alarm); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c index 64fe8f22336c..59701b7a6597 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.c @@ -57,7 +57,7 @@ nvkm_fantog_update(struct nvkm_fantog *fan, int percent) u64 next_change = (percent * fan->period_us) / 100; if (!duty) next_change = fan->period_us - next_change; - tmr->alarm(tmr, next_change * 1000, &fan->alarm); + nvkm_timer_alarm(tmr, next_change * 1000, &fan->alarm); } spin_unlock_irqrestore(&fan->lock, flags); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c index 4ab7ef7da254..b9703c02d8ca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.c @@ -186,7 +186,7 @@ alarm_timer_callback(struct nvkm_alarm *alarm) /* schedule the next poll in one second */ if (therm->func->temp_get(therm) >= 0 && list_empty(&alarm->head)) - tmr->alarm(tmr, 1000000000ULL, alarm); + nvkm_timer_alarm(tmr, 1000000000ULL, alarm); } void @@ -220,7 +220,7 @@ nvkm_therm_sensor_fini(struct nvkm_therm *therm, bool suspend) { struct nvkm_timer *tmr = therm->subdev.device->timer; if (suspend) - tmr->alarm_cancel(tmr, &therm->sensor.therm_poll_alarm); + nvkm_timer_alarm_cancel(tmr, &therm->sensor.therm_poll_alarm); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild index d1d38b4ba30a..e436f0ffe3f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/Kbuild @@ -1,3 +1,5 @@ nvkm-y += nvkm/subdev/timer/base.o nvkm-y += nvkm/subdev/timer/nv04.o +nvkm-y += nvkm/subdev/timer/nv40.o +nvkm-y += nvkm/subdev/timer/nv41.o nvkm-y += nvkm/subdev/timer/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c index 4c34e2bd0487..d4dae1f12d62 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.c @@ -21,18 +21,131 @@ * * Authors: Ben Skeggs */ -#include +#include "priv.h" + +u64 +nvkm_timer_read(struct nvkm_timer *tmr) +{ + return tmr->func->read(tmr); +} + +void +nvkm_timer_alarm_trigger(struct nvkm_timer *tmr) +{ + struct nvkm_alarm *alarm, *atemp; + unsigned long flags; + LIST_HEAD(exec); + + /* move any due alarms off the pending list */ + spin_lock_irqsave(&tmr->lock, flags); + list_for_each_entry_safe(alarm, atemp, &tmr->alarms, head) { + if (alarm->timestamp <= nvkm_timer_read(tmr)) + list_move_tail(&alarm->head, &exec); + } + + /* reschedule interrupt for next alarm time */ + if (!list_empty(&tmr->alarms)) { + alarm = list_first_entry(&tmr->alarms, typeof(*alarm), head); + tmr->func->alarm_init(tmr, alarm->timestamp); + } else { + tmr->func->alarm_fini(tmr); + } + spin_unlock_irqrestore(&tmr->lock, flags); + + /* execute any pending alarm handlers */ + list_for_each_entry_safe(alarm, atemp, &exec, head) { + list_del_init(&alarm->head); + alarm->func(alarm); + } +} void -nvkm_timer_alarm(void *obj, u32 nsec, struct nvkm_alarm *alarm) +nvkm_timer_alarm(struct nvkm_timer *tmr, u32 nsec, struct nvkm_alarm *alarm) { - struct nvkm_timer *tmr = nvkm_timer(obj); - tmr->alarm(tmr, nsec, alarm); + struct nvkm_alarm *list; + unsigned long flags; + + alarm->timestamp = nvkm_timer_read(tmr) + nsec; + + /* append new alarm to list, in soonest-alarm-first order */ + spin_lock_irqsave(&tmr->lock, flags); + if (!nsec) { + if (!list_empty(&alarm->head)) + list_del(&alarm->head); + } else { + list_for_each_entry(list, &tmr->alarms, head) { + if (list->timestamp > alarm->timestamp) + break; + } + list_add_tail(&alarm->head, &list->head); + } + spin_unlock_irqrestore(&tmr->lock, flags); + + /* process pending alarms */ + nvkm_timer_alarm_trigger(tmr); } void -nvkm_timer_alarm_cancel(void *obj, struct nvkm_alarm *alarm) +nvkm_timer_alarm_cancel(struct nvkm_timer *tmr, struct nvkm_alarm *alarm) +{ + unsigned long flags; + spin_lock_irqsave(&tmr->lock, flags); + list_del_init(&alarm->head); + spin_unlock_irqrestore(&tmr->lock, flags); +} + +static void +nvkm_timer_intr(struct nvkm_subdev *subdev) { - struct nvkm_timer *tmr = nvkm_timer(obj); - tmr->alarm_cancel(tmr, alarm); + struct nvkm_timer *tmr = nvkm_timer(subdev); + tmr->func->intr(tmr); +} + +static int +nvkm_timer_fini(struct nvkm_subdev *subdev, bool suspend) +{ + struct nvkm_timer *tmr = nvkm_timer(subdev); + tmr->func->alarm_fini(tmr); + return 0; +} + +static int +nvkm_timer_init(struct nvkm_subdev *subdev) +{ + struct nvkm_timer *tmr = nvkm_timer(subdev); + if (tmr->func->init) + tmr->func->init(tmr); + tmr->func->time(tmr, ktime_to_ns(ktime_get())); + nvkm_timer_alarm_trigger(tmr); + return 0; +} + +static void * +nvkm_timer_dtor(struct nvkm_subdev *subdev) +{ + return nvkm_timer(subdev); +} + +static const struct nvkm_subdev_func +nvkm_timer = { + .dtor = nvkm_timer_dtor, + .init = nvkm_timer_init, + .fini = nvkm_timer_fini, + .intr = nvkm_timer_intr, +}; + +int +nvkm_timer_new_(const struct nvkm_timer_func *func, struct nvkm_device *device, + int index, struct nvkm_timer **ptmr) +{ + struct nvkm_timer *tmr; + + if (!(tmr = *ptmr = kzalloc(sizeof(*tmr), GFP_KERNEL))) + return -ENOMEM; + + nvkm_subdev_ctor(&nvkm_timer, device, index, 0, &tmr->subdev); + tmr->func = func; + INIT_LIST_HEAD(&tmr->alarms); + spin_lock_init(&tmr->lock); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c index 46bfa10b5b97..9ed5f64912d0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.c @@ -21,38 +21,19 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" -static int -gk20a_timer_init(struct nvkm_object *object) -{ - struct nv04_timer *tmr = (void *)object; - struct nvkm_subdev *subdev = &tmr->base.subdev; - struct nvkm_device *device = subdev->device; - u32 hi = upper_32_bits(tmr->suspend_time); - u32 lo = lower_32_bits(tmr->suspend_time); - int ret; - - ret = nvkm_timer_init(&tmr->base); - if (ret) - return ret; - - nvkm_debug(subdev, "time low : %08x\n", lo); - nvkm_debug(subdev, "time high : %08x\n", hi); +static const struct nvkm_timer_func +gk20a_timer = { + .intr = nv04_timer_intr, + .read = nv04_timer_read, + .time = nv04_timer_time, + .alarm_init = nv04_timer_alarm_init, + .alarm_fini = nv04_timer_alarm_fini, +}; - /* restore the time before suspend */ - nvkm_wr32(device, NV04_PTIMER_TIME_1, hi); - nvkm_wr32(device, NV04_PTIMER_TIME_0, lo); - return 0; +int +gk20a_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +{ + return nvkm_timer_new_(&gk20a_timer, device, index, ptmr); } - -struct nvkm_oclass -gk20a_timer_oclass = { - .handle = NV_SUBDEV(TIMER, 0xff), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_timer_ctor, - .dtor = nv04_timer_dtor, - .init = gk20a_timer_init, - .fini = nv04_timer_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c index 8d45753f65ac..7b9ce87f0617 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.c @@ -21,9 +21,25 @@ * * Authors: Ben Skeggs */ -#include "nv04.h" +#include "priv.h" +#include "regsnv04.h" -static u64 +void +nv04_timer_time(struct nvkm_timer *tmr, u64 time) +{ + struct nvkm_subdev *subdev = &tmr->subdev; + struct nvkm_device *device = subdev->device; + u32 hi = upper_32_bits(time); + u32 lo = lower_32_bits(time); + + nvkm_debug(subdev, "time low : %08x\n", lo); + nvkm_debug(subdev, "time high : %08x\n", hi); + + nvkm_wr32(device, NV04_PTIMER_TIME_1, hi); + nvkm_wr32(device, NV04_PTIMER_TIME_0, lo); +} + +u64 nv04_timer_read(struct nvkm_timer *tmr) { struct nvkm_device *device = tmr->subdev.device; @@ -37,85 +53,30 @@ nv04_timer_read(struct nvkm_timer *tmr) return ((u64)hi << 32 | lo); } -static void -nv04_timer_alarm_trigger(struct nvkm_timer *obj) -{ - struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); - struct nvkm_device *device = tmr->base.subdev.device; - struct nvkm_alarm *alarm, *atemp; - unsigned long flags; - LIST_HEAD(exec); - - /* move any due alarms off the pending list */ - spin_lock_irqsave(&tmr->lock, flags); - list_for_each_entry_safe(alarm, atemp, &tmr->alarms, head) { - if (alarm->timestamp <= tmr->base.read(&tmr->base)) - list_move_tail(&alarm->head, &exec); - } - - /* reschedule interrupt for next alarm time */ - if (!list_empty(&tmr->alarms)) { - alarm = list_first_entry(&tmr->alarms, typeof(*alarm), head); - nvkm_wr32(device, NV04_PTIMER_ALARM_0, alarm->timestamp); - nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000001); - } else { - nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000); - } - spin_unlock_irqrestore(&tmr->lock, flags); - - /* execute any pending alarm handlers */ - list_for_each_entry_safe(alarm, atemp, &exec, head) { - list_del_init(&alarm->head); - alarm->func(alarm); - } -} - -static void -nv04_timer_alarm(struct nvkm_timer *obj, u64 time, struct nvkm_alarm *alarm) +void +nv04_timer_alarm_fini(struct nvkm_timer *tmr) { - struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); - struct nvkm_alarm *list; - unsigned long flags; - - alarm->timestamp = tmr->base.read(&tmr->base) + time; - - /* append new alarm to list, in soonest-alarm-first order */ - spin_lock_irqsave(&tmr->lock, flags); - if (!time) { - if (!list_empty(&alarm->head)) - list_del(&alarm->head); - } else { - list_for_each_entry(list, &tmr->alarms, head) { - if (list->timestamp > alarm->timestamp) - break; - } - list_add_tail(&alarm->head, &list->head); - } - spin_unlock_irqrestore(&tmr->lock, flags); - - /* process pending alarms */ - nv04_timer_alarm_trigger(&tmr->base); + struct nvkm_device *device = tmr->subdev.device; + nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000); } -static void -nv04_timer_alarm_cancel(struct nvkm_timer *obj, struct nvkm_alarm *alarm) +void +nv04_timer_alarm_init(struct nvkm_timer *tmr, u32 time) { - struct nv04_timer *tmr = container_of(obj, typeof(*tmr), base); - unsigned long flags; - spin_lock_irqsave(&tmr->lock, flags); - list_del_init(&alarm->head); - spin_unlock_irqrestore(&tmr->lock, flags); + struct nvkm_device *device = tmr->subdev.device; + nvkm_wr32(device, NV04_PTIMER_ALARM_0, time); + nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000001); } -static void -nv04_timer_intr(struct nvkm_subdev *subdev) +void +nv04_timer_intr(struct nvkm_timer *tmr) { - struct nv04_timer *tmr = (void *)subdev; - struct nvkm_device *device = tmr->base.subdev.device; + struct nvkm_subdev *subdev = &tmr->subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, NV04_PTIMER_INTR_0); if (stat & 0x00000001) { - nv04_timer_alarm_trigger(&tmr->base); + nvkm_timer_alarm_trigger(tmr); nvkm_wr32(device, NV04_PTIMER_INTR_0, 0x00000001); stat &= ~0x00000001; } @@ -126,62 +87,26 @@ nv04_timer_intr(struct nvkm_subdev *subdev) } } -int -nv04_timer_fini(struct nvkm_object *object, bool suspend) -{ - struct nv04_timer *tmr = (void *)object; - struct nvkm_device *device = tmr->base.subdev.device; - if (suspend) - tmr->suspend_time = nv04_timer_read(&tmr->base); - nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000); - return nvkm_timer_fini(&tmr->base, suspend); -} - -static int -nv04_timer_init(struct nvkm_object *object) +static void +nv04_timer_init(struct nvkm_timer *tmr) { - struct nv04_timer *tmr = (void *)object; - struct nvkm_subdev *subdev = &tmr->base.subdev; + struct nvkm_subdev *subdev = &tmr->subdev; struct nvkm_device *device = subdev->device; - u32 m = 1, f, n, d, lo, hi; - int ret; - - ret = nvkm_timer_init(&tmr->base); - if (ret) - return ret; + u32 f = 0; /*XXX: nvclk */ + u32 n, d; /* aim for 31.25MHz, which gives us nanosecond timestamps */ d = 1000000 / 32; - - /* determine base clock for timer source */ -#if 0 /*XXX*/ - if (device->chipset < 0x40) { - n = nvkm_hw_get_clock(device, PLL_CORE); - } else -#endif - if (device->chipset <= 0x40) { - /*XXX: figure this out */ - f = -1; - n = 0; - } else { - f = device->crystal; - n = f; - while (n < (d * 2)) { - n += (n / m); - m++; + n = f; + + if (!f) { + n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR); + d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR); + if (!n || !d) { + n = 1; + d = 1; } - - nvkm_wr32(device, 0x009220, m - 1); - } - - if (!n) { nvkm_warn(subdev, "unknown input clock freq\n"); - if (!nvkm_rd32(device, NV04_PTIMER_NUMERATOR) || - !nvkm_rd32(device, NV04_PTIMER_DENOMINATOR)) { - nvkm_wr32(device, NV04_PTIMER_NUMERATOR, 1); - nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, 1); - } - return 0; } /* reduce ratio to acceptable values */ @@ -200,65 +125,27 @@ nv04_timer_init(struct nvkm_object *object) d >>= 1; } - /* restore the time before suspend */ - lo = tmr->suspend_time; - hi = (tmr->suspend_time >> 32); - nvkm_debug(subdev, "input frequency : %dHz\n", f); - nvkm_debug(subdev, "input multiplier: %d\n", m); nvkm_debug(subdev, "numerator : %08x\n", n); nvkm_debug(subdev, "denominator : %08x\n", d); - nvkm_debug(subdev, "timer frequency : %dHz\n", (f * m) * d / n); - nvkm_debug(subdev, "time low : %08x\n", lo); - nvkm_debug(subdev, "time high : %08x\n", hi); + nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n); nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); - nvkm_wr32(device, NV04_PTIMER_INTR_0, 0xffffffff); - nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000); - nvkm_wr32(device, NV04_PTIMER_TIME_1, hi); - nvkm_wr32(device, NV04_PTIMER_TIME_0, lo); - return 0; } -void -nv04_timer_dtor(struct nvkm_object *object) -{ - struct nv04_timer *tmr = (void *)object; - return nvkm_timer_destroy(&tmr->base); -} +static const struct nvkm_timer_func +nv04_timer = { + .init = nv04_timer_init, + .intr = nv04_timer_intr, + .read = nv04_timer_read, + .time = nv04_timer_time, + .alarm_init = nv04_timer_alarm_init, + .alarm_fini = nv04_timer_alarm_fini, +}; int -nv04_timer_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +nv04_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) { - struct nv04_timer *tmr; - int ret; - - ret = nvkm_timer_create(parent, engine, oclass, &tmr); - *pobject = nv_object(tmr); - if (ret) - return ret; - - tmr->base.subdev.intr = nv04_timer_intr; - tmr->base.read = nv04_timer_read; - tmr->base.alarm = nv04_timer_alarm; - tmr->base.alarm_cancel = nv04_timer_alarm_cancel; - tmr->suspend_time = 0; - - INIT_LIST_HEAD(&tmr->alarms); - spin_lock_init(&tmr->lock); - return 0; + return nvkm_timer_new_(&nv04_timer, device, index, ptmr); } - -struct nvkm_oclass -nv04_timer_oclass = { - .handle = NV_SUBDEV(TIMER, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_timer_ctor, - .dtor = nv04_timer_dtor, - .init = nv04_timer_init, - .fini = nv04_timer_fini, - } -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h deleted file mode 100644 index 1bc0d7c073ef..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __NVKM_TIMER_NV04_H__ -#define __NVKM_TIMER_NV04_H__ -#include "priv.h" - -#define NV04_PTIMER_INTR_0 0x009100 -#define NV04_PTIMER_INTR_EN_0 0x009140 -#define NV04_PTIMER_NUMERATOR 0x009200 -#define NV04_PTIMER_DENOMINATOR 0x009210 -#define NV04_PTIMER_TIME_0 0x009400 -#define NV04_PTIMER_TIME_1 0x009410 -#define NV04_PTIMER_ALARM_0 0x009420 - -struct nv04_timer { - struct nvkm_timer base; - struct list_head alarms; - spinlock_t lock; - u64 suspend_time; -}; - -int nv04_timer_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void nv04_timer_dtor(struct nvkm_object *); -int nv04_timer_fini(struct nvkm_object *, bool); -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c new file mode 100644 index 000000000000..bb99a152f26e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.c @@ -0,0 +1,88 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" +#include "regsnv04.h" + +static void +nv40_timer_init(struct nvkm_timer *tmr) +{ + struct nvkm_subdev *subdev = &tmr->subdev; + struct nvkm_device *device = subdev->device; + u32 f = 0; /*XXX: figure this out */ + u32 n, d; + + /* aim for 31.25MHz, which gives us nanosecond timestamps */ + d = 1000000 / 32; + n = f; + + if (!f) { + n = nvkm_rd32(device, NV04_PTIMER_NUMERATOR); + d = nvkm_rd32(device, NV04_PTIMER_DENOMINATOR); + if (!n || !d) { + n = 1; + d = 1; + } + nvkm_warn(subdev, "unknown input clock freq\n"); + } + + /* reduce ratio to acceptable values */ + while (((n % 5) == 0) && ((d % 5) == 0)) { + n /= 5; + d /= 5; + } + + while (((n % 2) == 0) && ((d % 2) == 0)) { + n /= 2; + d /= 2; + } + + while (n > 0xffff || d > 0xffff) { + n >>= 1; + d >>= 1; + } + + nvkm_debug(subdev, "input frequency : %dHz\n", f); + nvkm_debug(subdev, "numerator : %08x\n", n); + nvkm_debug(subdev, "denominator : %08x\n", d); + nvkm_debug(subdev, "timer frequency : %dHz\n", f * d / n); + + nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); + nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); +} + +static const struct nvkm_timer_func +nv40_timer = { + .init = nv40_timer_init, + .intr = nv04_timer_intr, + .read = nv04_timer_read, + .time = nv04_timer_time, + .alarm_init = nv04_timer_alarm_init, + .alarm_fini = nv04_timer_alarm_fini, +}; + +int +nv40_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +{ + return nvkm_timer_new_(&nv40_timer, device, index, ptmr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c new file mode 100644 index 000000000000..3cf9ec1b1b57 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.c @@ -0,0 +1,85 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "priv.h" +#include "regsnv04.h" + +static void +nv41_timer_init(struct nvkm_timer *tmr) +{ + struct nvkm_subdev *subdev = &tmr->subdev; + struct nvkm_device *device = subdev->device; + u32 f = device->crystal; + u32 m = 1, n, d; + + /* aim for 31.25MHz, which gives us nanosecond timestamps */ + d = 1000000 / 32; + n = f; + + while (n < (d * 2)) { + n += (n / m); + m++; + } + + /* reduce ratio to acceptable values */ + while (((n % 5) == 0) && ((d % 5) == 0)) { + n /= 5; + d /= 5; + } + + while (((n % 2) == 0) && ((d % 2) == 0)) { + n /= 2; + d /= 2; + } + + while (n > 0xffff || d > 0xffff) { + n >>= 1; + d >>= 1; + } + + nvkm_debug(subdev, "input frequency : %dHz\n", f); + nvkm_debug(subdev, "input multiplier: %d\n", m); + nvkm_debug(subdev, "numerator : %08x\n", n); + nvkm_debug(subdev, "denominator : %08x\n", d); + nvkm_debug(subdev, "timer frequency : %dHz\n", (f * m) * d / n); + + nvkm_wr32(device, 0x009220, m - 1); + nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); + nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); +} + +static const struct nvkm_timer_func +nv41_timer = { + .init = nv41_timer_init, + .intr = nv04_timer_intr, + .read = nv04_timer_read, + .time = nv04_timer_time, + .alarm_init = nv04_timer_alarm_init, + .alarm_fini = nv04_timer_alarm_fini, +}; + +int +nv41_timer_new(struct nvkm_device *device, int index, struct nvkm_timer **ptmr) +{ + return nvkm_timer_new_(&nv41_timer, device, index, ptmr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h index 08e29a3da188..f820ca2aeda4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/priv.h @@ -1,4 +1,26 @@ #ifndef __NVKM_TIMER_PRIV_H__ #define __NVKM_TIMER_PRIV_H__ +#define nvkm_timer(p) container_of((p), struct nvkm_timer, subdev) #include + +int nvkm_timer_new_(const struct nvkm_timer_func *, struct nvkm_device *, + int index, struct nvkm_timer **); + +struct nvkm_timer_func { + void (*init)(struct nvkm_timer *); + void (*intr)(struct nvkm_timer *); + u64 (*read)(struct nvkm_timer *); + void (*time)(struct nvkm_timer *, u64 time); + void (*alarm_init)(struct nvkm_timer *, u32 time); + void (*alarm_fini)(struct nvkm_timer *); +}; + +void nvkm_timer_alarm_trigger(struct nvkm_timer *); + +void nv04_timer_fini(struct nvkm_timer *); +void nv04_timer_intr(struct nvkm_timer *); +void nv04_timer_time(struct nvkm_timer *, u64); +u64 nv04_timer_read(struct nvkm_timer *); +void nv04_timer_alarm_init(struct nvkm_timer *, u32); +void nv04_timer_alarm_fini(struct nvkm_timer *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h new file mode 100644 index 000000000000..10bef85b485e --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/timer/regsnv04.h @@ -0,0 +1,7 @@ +#define NV04_PTIMER_INTR_0 0x009100 +#define NV04_PTIMER_INTR_EN_0 0x009140 +#define NV04_PTIMER_NUMERATOR 0x009200 +#define NV04_PTIMER_DENOMINATOR 0x009210 +#define NV04_PTIMER_TIME_0 0x009400 +#define NV04_PTIMER_TIME_1 0x009410 +#define NV04_PTIMER_ALARM_0 0x009420 -- cgit v1.2.3 From 13de7f462902d1a452d501cdb2d06ef02cabbfff Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:22 +1000 Subject: drm/nouveau/fifo: convert to new-style nvkm_engine Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 83 ++------- drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 136 +++++++------- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 - drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 7 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 -- drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 -- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c | 128 ++++++++++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c | 71 ++------ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 162 ++++++++--------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 198 +++++++++------------ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 24 +-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c | 30 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c | 30 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c | 32 ++-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c | 30 ++-- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c | 1 + .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 92 ++++------ drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h | 10 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c | 45 ++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c | 57 ++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 59 ++---- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c | 103 ++++++----- drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 19 ++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 5 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 4 +- 56 files changed, 640 insertions(+), 801 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index d9e494ba5033..84cc3e9cfed7 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -1,7 +1,5 @@ #ifndef __NVKM_FIFO_H__ #define __NVKM_FIFO_H__ -#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object) -#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine) #include #include @@ -33,46 +31,21 @@ struct nvkm_fifo_chan { extern const struct nvkm_object_func nvkm_fifo_chan_func; -#include -struct nvkm_fifo_base { - struct nvkm_gpuobj gpuobj; -}; - -#define nvkm_fifo_context_create(p,e,c,g,s,a,f,d) \ - nvkm_gpuobj_create((p), (e), (c), NV_ENGCTX_CLASS, (g), (s), (a), (f), (d)) -#define nvkm_fifo_context_destroy(p) \ - nvkm_gpuobj_destroy(&(p)->gpuobj) -#define nvkm_fifo_context_init(p) \ - nvkm_gpuobj_init(&(p)->gpuobj) -#define nvkm_fifo_context_fini(p,s) \ - nvkm_gpuobj_fini(&(p)->gpuobj, (s)) - -#define _nvkm_fifo_context_dtor _nvkm_gpuobj_dtor -#define _nvkm_fifo_context_init _nvkm_gpuobj_init -#define _nvkm_fifo_context_fini _nvkm_gpuobj_fini -#define _nvkm_fifo_context_rd32 _nvkm_gpuobj_rd32 -#define _nvkm_fifo_context_wr32 _nvkm_gpuobj_wr32 - struct nvkm_fifo { - struct nvkm_engine engine; const struct nvkm_fifo_func *func; - - struct nvkm_event cevent; /* channel creation event */ - struct nvkm_event uevent; /* async user trigger */ + struct nvkm_engine engine; DECLARE_BITMAP(mask, NVKM_FIFO_CHID_NR); int nr; struct list_head chan; spinlock_t lock; - void (*pause)(struct nvkm_fifo *, unsigned long *); - void (*start)(struct nvkm_fifo *, unsigned long *); + struct nvkm_event uevent; /* async user trigger */ + struct nvkm_event cevent; /* channel creation event */ }; -struct nvkm_fifo_func { - void *(*dtor)(struct nvkm_fifo *); - const struct nvkm_fifo_chan_oclass *chan[]; -}; +void nvkm_fifo_pause(struct nvkm_fifo *, unsigned long *); +void nvkm_fifo_start(struct nvkm_fifo *, unsigned long *); void nvkm_fifo_chan_put(struct nvkm_fifo *, unsigned long flags, struct nvkm_fifo_chan **); @@ -81,38 +54,16 @@ nvkm_fifo_chan_inst(struct nvkm_fifo *, u64 inst, unsigned long *flags); struct nvkm_fifo_chan * nvkm_fifo_chan_chid(struct nvkm_fifo *, int chid, unsigned long *flags); -#define nvkm_fifo_create(o,e,c,fc,lc,d) \ - nvkm_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) -#define nvkm_fifo_init(p) \ - nvkm_engine_init_old(&(p)->engine) -#define nvkm_fifo_fini(p,s) \ - nvkm_engine_fini_old(&(p)->engine, (s)) - -int nvkm_fifo_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, int min, int max, - int size, void **); -void nvkm_fifo_destroy(struct nvkm_fifo *); - -#define _nvkm_fifo_init _nvkm_engine_init -#define _nvkm_fifo_fini _nvkm_engine_fini - -extern struct nvkm_oclass *nv04_fifo_oclass; -extern struct nvkm_oclass *nv10_fifo_oclass; -extern struct nvkm_oclass *nv17_fifo_oclass; -extern struct nvkm_oclass *nv40_fifo_oclass; -extern struct nvkm_oclass *nv50_fifo_oclass; -extern struct nvkm_oclass *g84_fifo_oclass; -extern struct nvkm_oclass *gf100_fifo_oclass; -extern struct nvkm_oclass *gk104_fifo_oclass; -extern struct nvkm_oclass *gk20a_fifo_oclass; -extern struct nvkm_oclass *gk208_fifo_oclass; -extern struct nvkm_oclass *gm204_fifo_oclass; -extern struct nvkm_oclass *gm20b_fifo_oclass; - -int nvkm_fifo_uevent_ctor(struct nvkm_object *, void *, u32, - struct nvkm_notify *); -void nvkm_fifo_uevent(struct nvkm_fifo *); - -void nv04_fifo_intr(struct nvkm_subdev *); -int nv04_fifo_context_attach(struct nvkm_object *, struct nvkm_object *); +int nv04_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int nv10_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int nv17_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int nv40_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int nv50_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int g84_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int gf100_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int gk104_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int gk208_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int gk20a_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int gm204_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); +int gm20b_fifo_new(struct nvkm_device *, int, struct nvkm_fifo **); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index e056f7afc35c..b8fc539e0a99 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -231,7 +231,7 @@ nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) nvkm_object_destroy(&gpuobj->object); } -#include +#include int nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 764b46751eb9..03763268248f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -26,6 +26,7 @@ #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index ea3e8902f458..62395ab742c5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -88,7 +88,7 @@ nv4_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv04_fifo_new, + .fifo = nv04_fifo_new, // .gr = nv04_gr_new, // .sw = nv04_sw_new, }; @@ -108,7 +108,7 @@ nv5_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv04_fifo_new, + .fifo = nv04_fifo_new, // .gr = nv04_gr_new, // .sw = nv04_sw_new, }; @@ -148,7 +148,7 @@ nv11_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv10_fifo_new, + .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -169,7 +169,7 @@ nv15_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv10_fifo_new, + .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -190,7 +190,7 @@ nv17_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -211,7 +211,7 @@ nv18_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -232,7 +232,7 @@ nv1a_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv10_fifo_new, + .fifo = nv10_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -253,7 +253,7 @@ nv1f_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv10_gr_new, // .sw = nv10_sw_new, }; @@ -274,7 +274,7 @@ nv20_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv20_gr_new, // .sw = nv10_sw_new, }; @@ -295,7 +295,7 @@ nv25_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv25_gr_new, // .sw = nv10_sw_new, }; @@ -316,7 +316,7 @@ nv28_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv25_gr_new, // .sw = nv10_sw_new, }; @@ -337,7 +337,7 @@ nv2a_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv2a_gr_new, // .sw = nv10_sw_new, }; @@ -358,7 +358,7 @@ nv30_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv30_gr_new, // .sw = nv10_sw_new, }; @@ -379,7 +379,7 @@ nv31_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv30_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, @@ -401,7 +401,7 @@ nv34_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv34_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, @@ -423,7 +423,7 @@ nv35_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv35_gr_new, // .sw = nv10_sw_new, }; @@ -444,7 +444,7 @@ nv36_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv17_fifo_new, + .fifo = nv17_fifo_new, // .gr = nv35_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, @@ -468,7 +468,7 @@ nv40_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -493,7 +493,7 @@ nv41_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -518,7 +518,7 @@ nv42_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -543,7 +543,7 @@ nv43_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, @@ -568,7 +568,7 @@ nv44_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -593,7 +593,7 @@ nv45_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -618,7 +618,7 @@ nv46_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -643,7 +643,7 @@ nv47_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -668,7 +668,7 @@ nv49_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -693,7 +693,7 @@ nv4a_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -718,7 +718,7 @@ nv4b_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -743,7 +743,7 @@ nv4c_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -768,7 +768,7 @@ nv4e_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -796,7 +796,7 @@ nv50_chipset = { .volt = nv40_volt_new, .disp = nv50_disp_new, .dma = nv50_dma_new, -// .fifo = nv50_fifo_new, + .fifo = nv50_fifo_new, // .gr = nv50_gr_new, // .mpeg = nv50_mpeg_new, // .pm = nv50_pm_new, @@ -821,7 +821,7 @@ nv63_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -846,7 +846,7 @@ nv67_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -871,7 +871,7 @@ nv68_chipset = { .volt = nv40_volt_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .fifo = nv40_fifo_new, + .fifo = nv40_fifo_new, // .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, @@ -901,7 +901,7 @@ nv84_chipset = { .cipher = g84_cipher_new, .disp = g84_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -932,7 +932,7 @@ nv86_chipset = { .cipher = g84_cipher_new, .disp = g84_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -963,7 +963,7 @@ nv92_chipset = { .cipher = g84_cipher_new, .disp = g84_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -994,7 +994,7 @@ nv94_chipset = { .cipher = g84_cipher_new, .disp = g94_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, @@ -1022,7 +1022,7 @@ nv96_chipset = { .bar = g84_bar_new, .volt = nv40_volt_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, @@ -1053,7 +1053,7 @@ nv98_chipset = { .bar = g84_bar_new, .volt = nv40_volt_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .sw = nv50_sw_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, @@ -1087,7 +1087,7 @@ nva0_chipset = { .cipher = g84_cipher_new, .disp = gt200_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, // .pm = gt200_pm_new, @@ -1118,7 +1118,7 @@ nva3_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, // .mpeg = g84_mpeg_new, .mspdec = gt215_mspdec_new, @@ -1151,7 +1151,7 @@ nva5_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1183,7 +1183,7 @@ nva8_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1213,7 +1213,7 @@ nvaa_chipset = { .volt = nv40_volt_new, .disp = g94_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, @@ -1244,7 +1244,7 @@ nvac_chipset = { .volt = nv40_volt_new, .disp = g94_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, @@ -1277,7 +1277,7 @@ nvaf_chipset = { .ce[0] = gt215_ce_new, .disp = gt215_disp_new, .dma = nv50_dma_new, -// .fifo = g84_fifo_new, + .fifo = g84_fifo_new, // .gr = nv50_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1312,7 +1312,7 @@ nvc0_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf100_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1346,7 +1346,7 @@ nvc1_chipset = { .ce[0] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf108_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1380,7 +1380,7 @@ nvc3_chipset = { .ce[0] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1415,7 +1415,7 @@ nvc4_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1450,7 +1450,7 @@ nvc8_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf110_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1485,7 +1485,7 @@ nvce_chipset = { .ce[1] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1519,7 +1519,7 @@ nvcf_chipset = { .ce[0] = gf100_ce_new, .disp = gt215_disp_new, .dma = gf100_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1551,7 +1551,7 @@ nvd7_chipset = { .ce[0] = gf100_ce_new, .disp = gf119_disp_new, .dma = gf119_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf117_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1585,7 +1585,7 @@ nvd9_chipset = { .ce[0] = gf100_ce_new, .disp = gf119_disp_new, .dma = gf119_dma_new, -// .fifo = gf100_fifo_new, + .fifo = gf100_fifo_new, // .gr = gf119_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, @@ -1621,7 +1621,7 @@ nve4_chipset = { .ce[2] = gk104_ce_new, .disp = gk104_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1657,7 +1657,7 @@ nve6_chipset = { .ce[2] = gk104_ce_new, .disp = gk104_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1693,7 +1693,7 @@ nve7_chipset = { .ce[2] = gk104_ce_new, .disp = gk104_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1720,7 +1720,7 @@ nvea_chipset = { .volt = gk20a_volt_new, .ce[2] = gk104_ce_new, .dma = gf119_dma_new, -// .fifo = gk20a_fifo_new, + .fifo = gk20a_fifo_new, // .gr = gk20a_gr_new, // .pm = gk104_pm_new, // .sw = gf100_sw_new, @@ -1753,7 +1753,7 @@ nvf0_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk110_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1789,7 +1789,7 @@ nvf1_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk104_fifo_new, + .fifo = gk104_fifo_new, // .gr = gk110b_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1825,7 +1825,7 @@ nv106_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk208_fifo_new, + .fifo = gk208_fifo_new, // .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1860,7 +1860,7 @@ nv108_chipset = { .ce[2] = gk104_ce_new, .disp = gk110_disp_new, .dma = gf119_dma_new, -// .fifo = gk208_fifo_new, + .fifo = gk208_fifo_new, // .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, @@ -1893,7 +1893,7 @@ nv117_chipset = { .ce[2] = gk104_ce_new, .disp = gm107_disp_new, .dma = gf119_dma_new, -// .fifo = gk208_fifo_new, + .fifo = gk208_fifo_new, // .gr = gm107_gr_new, // .sw = gf100_sw_new, }; @@ -1922,7 +1922,7 @@ nv124_chipset = { .ce[2] = gm204_ce_new, .disp = gm204_disp_new, .dma = gf119_dma_new, -// .fifo = gm204_fifo_new, + .fifo = gm204_fifo_new, // .gr = gm204_gr_new, // .sw = gf100_sw_new, }; @@ -1951,7 +1951,7 @@ nv126_chipset = { .ce[2] = gm204_ce_new, .disp = gm204_disp_new, .dma = gf119_dma_new, -// .fifo = gm204_fifo_new, + .fifo = gm204_fifo_new, // .gr = gm206_gr_new, // .sw = gf100_sw_new, }; @@ -1972,7 +1972,7 @@ nv12b_chipset = { .timer = gk20a_timer_new, .ce[2] = gm204_ce_new, .dma = gf119_dma_new, -// .fifo = gm20b_fifo_new, + .fifo = gm20b_fifo_new, // .gr = gm20b_gr_new, // .sw = gf100_sw_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index 09a1fe1604a2..d319f5680f44 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -28,55 +28,46 @@ gf100_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xc0: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc4: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc3: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xce: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xcf: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc1: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; case 0xc8: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xd9: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; case 0xd7: - device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index b3d25aad22f7..fe8298e02e9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -28,48 +28,40 @@ gk104_identify(struct nvkm_device *device) { switch (device->chipset) { case 0xe4: - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: - device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xf0: - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: - device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: - device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; break; case 0x108: - device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index c0c1bd3989d6..2362a634462c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device) #if 0 #endif - device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #if 0 @@ -46,7 +45,6 @@ gm100_identify(struct nvkm_device *device) #endif #if 0 #endif - device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; #if 0 @@ -59,7 +57,6 @@ gm100_identify(struct nvkm_device *device) #endif #if 0 #endif - device->oclass[NVDEV_ENGINE_FIFO ] = gm204_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; #if 0 @@ -67,7 +64,6 @@ gm100_identify(struct nvkm_device *device) break; case 0x12b: - device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index 7a71d0c1d22f..edddbaa41b43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -28,12 +28,10 @@ nv04_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x04: - device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; break; case 0x05: - device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index 2b59c02fe734..f1ebb9bcda3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -31,37 +31,30 @@ nv10_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x15: - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x16: - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x1a: - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x11: - device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x17: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x1f: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x18: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index b4f8c479f3d7..f9c4dad1f8ff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -28,22 +28,18 @@ nv20_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x20: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; break; case 0x25: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; break; case 0x28: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; break; case 0x2a: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index fec9e3f38a5c..b8e1e43723a3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -28,29 +28,24 @@ nv30_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x30: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; break; case 0x35: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; break; case 0x31: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; case 0x36: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; case 0x34: - device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 553923ab0376..158ed5e395df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -28,112 +28,96 @@ nv40_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x40: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: - device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index f4c4ded9193f..688b3e2d61ff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -28,93 +28,79 @@ nv50_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x50: - device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x86: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x92: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x94: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x96: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x98: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa0: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; break; case 0xaa: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xac: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa3: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa5: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa8: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xaf: - device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass; device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index e51372bdbf54..2d11b328bee1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -20,9 +20,10 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include -#include +#include #include +#include static int nvkm_falcon_oclass_get(struct nvkm_oclass *oclass, int index) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild index 4525b01598a9..74993c144a84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild @@ -7,8 +7,8 @@ nvkm-y += nvkm/engine/fifo/nv50.o nvkm-y += nvkm/engine/fifo/g84.o nvkm-y += nvkm/engine/fifo/gf100.o nvkm-y += nvkm/engine/fifo/gk104.o -nvkm-y += nvkm/engine/fifo/gk20a.o nvkm-y += nvkm/engine/fifo/gk208.o +nvkm-y += nvkm/engine/fifo/gk20a.o nvkm-y += nvkm/engine/fifo/gm204.o nvkm-y += nvkm/engine/fifo/gm20b.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c index b693127d80e1..1fbbfbe6ca9c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.c @@ -25,11 +25,24 @@ #include "chan.h" #include +#include #include #include #include +void +nvkm_fifo_pause(struct nvkm_fifo *fifo, unsigned long *flags) +{ + return fifo->func->pause(fifo, flags); +} + +void +nvkm_fifo_start(struct nvkm_fifo *fifo, unsigned long *flags) +{ + return fifo->func->start(fifo, flags); +} + void nvkm_fifo_chan_put(struct nvkm_fifo *fifo, unsigned long flags, struct nvkm_fifo_chan **pchan) @@ -95,7 +108,21 @@ nvkm_fifo_event_func = { .ctor = nvkm_fifo_event_ctor, }; -int +static void +nvkm_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +{ + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); + fifo->func->uevent_fini(fifo); +} + +static void +nvkm_fifo_uevent_init(struct nvkm_event *event, int type, int index) +{ + struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); + fifo->func->uevent_init(fifo); +} + +static int nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) { @@ -113,6 +140,13 @@ nvkm_fifo_uevent_ctor(struct nvkm_object *object, void *data, u32 size, return ret; } +static const struct nvkm_event_func +nvkm_fifo_uevent_func = { + .ctor = nvkm_fifo_uevent_ctor, + .init = nvkm_fifo_uevent_init, + .fini = nvkm_fifo_uevent_fini, +}; + void nvkm_fifo_uevent(struct nvkm_fifo *fifo) { @@ -156,50 +190,88 @@ nvkm_fifo_class_get(struct nvkm_oclass *oclass, int index, return c; } -void -nvkm_fifo_destroy(struct nvkm_fifo *fifo) +static void +nvkm_fifo_intr(struct nvkm_engine *engine) { - nvkm_event_fini(&fifo->uevent); + struct nvkm_fifo *fifo = nvkm_fifo(engine); + fifo->func->intr(fifo); +} + +static int +nvkm_fifo_fini(struct nvkm_engine *engine, bool suspend) +{ + struct nvkm_fifo *fifo = nvkm_fifo(engine); + if (fifo->func->fini) + fifo->func->fini(fifo); + return 0; +} + +static int +nvkm_fifo_oneinit(struct nvkm_engine *engine) +{ + struct nvkm_fifo *fifo = nvkm_fifo(engine); + if (fifo->func->oneinit) + return fifo->func->oneinit(fifo); + return 0; +} + +static int +nvkm_fifo_init(struct nvkm_engine *engine) +{ + struct nvkm_fifo *fifo = nvkm_fifo(engine); + fifo->func->init(fifo); + return 0; +} + +static void * +nvkm_fifo_dtor(struct nvkm_engine *engine) +{ + struct nvkm_fifo *fifo = nvkm_fifo(engine); + void *data = fifo; + if (fifo->func->dtor) + data = fifo->func->dtor(fifo); nvkm_event_fini(&fifo->cevent); - nvkm_engine_destroy(&fifo->engine); + nvkm_event_fini(&fifo->uevent); + return data; } static const struct nvkm_engine_func -nvkm_fifo_func = { +nvkm_fifo = { + .dtor = nvkm_fifo_dtor, + .oneinit = nvkm_fifo_oneinit, + .init = nvkm_fifo_init, + .fini = nvkm_fifo_fini, + .intr = nvkm_fifo_intr, .base.sclass = nvkm_fifo_class_get, }; int -nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, - int min, int max, int length, void **pobject) +nvkm_fifo_ctor(const struct nvkm_fifo_func *func, struct nvkm_device *device, + int index, int nr, struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo; - int nr = max + 1; - int cnt = nr - min; int ret; - ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", - "fifo", length, pobject); - fifo = *pobject; - if (ret) - return ret; - - fifo->engine.func = &nvkm_fifo_func; + fifo->func = func; INIT_LIST_HEAD(&fifo->chan); + spin_lock_init(&fifo->lock); - fifo->nr = nr; - if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) { + if (WARN_ON(fifo->nr > NVKM_FIFO_CHID_NR)) fifo->nr = NVKM_FIFO_CHID_NR; - cnt = fifo->nr - min; - } - bitmap_fill(fifo->mask, NVKM_FIFO_CHID_NR); - bitmap_clear(fifo->mask, min, cnt); + else + fifo->nr = nr; + bitmap_clear(fifo->mask, 0, fifo->nr); - ret = nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent); + ret = nvkm_engine_ctor(&nvkm_fifo, device, index, 0x00000100, + true, &fifo->engine); if (ret) return ret; - spin_lock_init(&fifo->lock); - return 0; + if (func->uevent_init) { + ret = nvkm_event_init(&nvkm_fifo_uevent_func, 1, 1, + &fifo->uevent); + if (ret) + return ret; + } + + return nvkm_event_init(&nvkm_fifo_event_func, 1, 1, &fifo->cevent); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index a02c60f340c0..4ed06abdc917 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -24,6 +24,7 @@ #include "chan.h" #include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h index bfec12dbf492..55dc415c5c08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.h @@ -1,5 +1,6 @@ #ifndef __NVKM_FIFO_CHAN_H__ #define __NVKM_FIFO_CHAN_H__ +#define nvkm_fifo_chan(p) container_of((p), struct nvkm_fifo_chan, object) #include "priv.h" struct nvkm_fifo_chan_func { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c index eafa87886643..52cbc4b47b2c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -73,7 +73,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) struct nv04_fifo *fifo = chan->fifo; struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_memory *fctx = device->imem->ramfc; - struct ramfc_desc *c; + const struct nv04_fifo_ramfc *c; unsigned long flags; u32 mask = fifo->base.nr - 1; u32 data = chan->ramfc; @@ -90,7 +90,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); - c = fifo->ramfc_desc; + c = fifo->ramfc; do { u32 rm = ((1ULL << c->bits) - 1) << c->regs; u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; @@ -99,7 +99,7 @@ nv04_fifo_dma_fini(struct nvkm_fifo_chan *base) nvkm_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); } while ((++c)->bits); - c = fifo->ramfc_desc; + c = fifo->ramfc; do { nvkm_wr32(device, c->regp, 0x00000000); } while ((++c)->bits); @@ -136,7 +136,7 @@ nv04_fifo_dma_dtor(struct nvkm_fifo_chan *base) struct nv04_fifo_chan *chan = nv04_fifo_chan(base); struct nv04_fifo *fifo = chan->fifo; struct nvkm_instmem *imem = fifo->base.engine.subdev.device->imem; - struct ramfc_desc *c = fifo->ramfc_desc; + const struct nv04_fifo_ramfc *c = fifo->ramfc; nvkm_kmap(imem->ramfc); do { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c index 1ad16205305f..d8e4d55704d1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -25,6 +25,7 @@ #include "regsnv04.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c index 2fbb9d4f0900..1424dd9b6299 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -25,6 +25,7 @@ #include "regsnv04.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c index 00fa9d3eff7a..ff7b529764fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c @@ -25,30 +25,29 @@ #include "channv50.h" static void -g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_fini(struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x40000000, 0x00000000); } static void -g84_fifo_uevent_init(struct nvkm_event *event, int type, int index) +g84_fifo_uevent_init(struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x40000000, 0x40000000); } -static const struct nvkm_event_func -g84_fifo_uevent_func = { - .ctor = nvkm_fifo_uevent_ctor, - .init = g84_fifo_uevent_init, - .fini = g84_fifo_uevent_fini, -}; - static const struct nvkm_fifo_func -g84_fifo_func = { +g84_fifo = { + .dtor = nv50_fifo_dtor, + .oneinit = nv50_fifo_oneinit, + .init = nv50_fifo_init, + .intr = nv04_fifo_intr, + .pause = nv04_fifo_pause, + .start = nv04_fifo_start, + .uevent_init = g84_fifo_uevent_init, + .uevent_fini = g84_fifo_uevent_fini, .chan = { &g84_fifo_dma_oclass, &g84_fifo_gpfifo_oclass, @@ -56,50 +55,8 @@ g84_fifo_func = { }, }; -static int -g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +g84_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - struct nvkm_device *device = (void *)parent; - struct nv50_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &g84_fifo_func; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->runlist[0]); - if (ret) - return ret; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->runlist[1]); - if (ret) - return ret; - - ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent); - if (ret) - return ret; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - return 0; + return nv50_fifo_new_(&g84_fifo, device, index, pfifo); } - -struct nvkm_oclass * -g84_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0x84), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = g84_fifo_ctor, - .dtor = nv50_fifo_dtor, - .init = nv50_fifo_init, - .fini = _nvkm_fifo_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index e8598fc44796..bc094223f687 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -33,28 +34,19 @@ #include static void -gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) +gf100_fifo_uevent_init(struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); } static void -gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +gf100_fifo_uevent_fini(struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); } -static const struct nvkm_event_func -gf100_fifo_uevent_func = { - .ctor = nvkm_fifo_uevent_ctor, - .init = gf100_fifo_uevent_init, - .fini = gf100_fifo_uevent_fini, -}; - void gf100_fifo_runlist_update(struct gf100_fifo *fifo) { @@ -64,7 +56,7 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo) struct nvkm_memory *cur; int nr = 0; - mutex_lock(&nv_subdev(fifo)->mutex); + mutex_lock(&subdev->mutex); cur = fifo->runlist.mem[fifo->runlist.active]; fifo->runlist.active = !fifo->runlist.active; @@ -83,7 +75,7 @@ gf100_fifo_runlist_update(struct gf100_fifo *fifo) !(nvkm_rd32(device, 0x00227c) & 0x00100000), msecs_to_jiffies(2000)) == 0) nvkm_error(subdev, "runlist update timeout\n"); - mutex_unlock(&nv_subdev(fifo)->mutex); + mutex_unlock(&subdev->mutex); } static inline int @@ -106,6 +98,8 @@ gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) static inline struct nvkm_engine * gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) { + struct nvkm_device *device = fifo->base.engine.subdev.device; + switch (engn) { case 0: engn = NVDEV_ENGINE_GR; break; case 1: engn = NVDEV_ENGINE_MSVLD; break; @@ -117,7 +111,7 @@ gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) return NULL; } - return nvkm_engine(fifo, engn); + return nvkm_device_engine(device, engn); } static void @@ -167,7 +161,7 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, list_del_init(&chan->head); chan->killed = true; - fifo->mask |= 1ULL << nv_engidx(engine); + fifo->mask |= 1ULL << engine->subdev.index; schedule_work(&fifo->fault); } @@ -333,7 +327,7 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_engine(fifo, eu->data2); + engine = nvkm_device_engine(device, eu->data2); break; } } @@ -457,10 +451,11 @@ gf100_fifo_intr_engine(struct gf100_fifo *fifo) } static void -gf100_fifo_intr(struct nvkm_subdev *subdev) +gf100_fifo_intr(struct nvkm_fifo *base) { - struct gf100_fifo *fifo = (void *)subdev; - struct nvkm_device *device = fifo->base.engine.subdev.device; + struct gf100_fifo *fifo = gf100_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 mask = nvkm_rd32(device, 0x002140); u32 stat = nvkm_rd32(device, 0x002100) & mask; @@ -531,17 +526,52 @@ gf100_fifo_intr(struct nvkm_subdev *subdev) } static int -gf100_fifo_init(struct nvkm_object *object) +gf100_fifo_oneinit(struct nvkm_fifo *base) { - struct gf100_fifo *fifo = (void *)object; - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - int ret, i; + struct gf100_fifo *fifo = gf100_fifo(base); + struct nvkm_device *device = fifo->base.engine.subdev.device; + int ret; - ret = nvkm_fifo_init(&fifo->base); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, + false, &fifo->runlist.mem[0]); + if (ret) + return ret; + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, + false, &fifo->runlist.mem[1]); if (ret) return ret; + init_waitqueue_head(&fifo->runlist.wait); + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000, + 0x1000, false, &fifo->user.mem); + if (ret) + return ret; + + ret = nvkm_bar_umap(device->bar, 128 * 0x1000, 12, &fifo->user.bar); + if (ret) + return ret; + + nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); + return 0; +} + +static void +gf100_fifo_fini(struct nvkm_fifo *base) +{ + struct gf100_fifo *fifo = gf100_fifo(base); + flush_work(&fifo->fault); +} + +static void +gf100_fifo_init(struct nvkm_fifo *base) +{ + struct gf100_fifo *fifo = gf100_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + int i; + nvkm_wr32(device, 0x000204, 0xffffffff); nvkm_wr32(device, 0x002204, 0xffffffff); @@ -571,90 +601,44 @@ gf100_fifo_init(struct nvkm_object *object) nvkm_wr32(device, 0x002100, 0xffffffff); nvkm_wr32(device, 0x002140, 0x7fffffff); nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ - return 0; } -static void -gf100_fifo_dtor(struct nvkm_object *object) +static void * +gf100_fifo_dtor(struct nvkm_fifo *base) { - struct gf100_fifo *fifo = (void *)object; - + struct gf100_fifo *fifo = gf100_fifo(base); nvkm_vm_put(&fifo->user.bar); nvkm_memory_del(&fifo->user.mem); nvkm_memory_del(&fifo->runlist.mem[0]); nvkm_memory_del(&fifo->runlist.mem[1]); - - nvkm_fifo_destroy(&fifo->base); + return fifo; } static const struct nvkm_fifo_func -gf100_fifo_func = { +gf100_fifo = { + .dtor = gf100_fifo_dtor, + .oneinit = gf100_fifo_oneinit, + .init = gf100_fifo_init, + .fini = gf100_fifo_fini, + .intr = gf100_fifo_intr, + .uevent_init = gf100_fifo_uevent_init, + .uevent_fini = gf100_fifo_uevent_fini, .chan = { &gf100_fifo_gpfifo_oclass, NULL }, }; -static int -gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +gf100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - struct nvkm_device *device = (void *)parent; - struct nvkm_bar *bar = device->bar; struct gf100_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &gf100_fifo_func; + if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) + return -ENOMEM; INIT_LIST_HEAD(&fifo->chan); INIT_WORK(&fifo->fault, gf100_fifo_recover_work); + *pfifo = &fifo->base; - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, - false, &fifo->runlist.mem[0]); - if (ret) - return ret; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x1000, - false, &fifo->runlist.mem[1]); - if (ret) - return ret; - - init_waitqueue_head(&fifo->runlist.wait); - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 0x1000, - 0x1000, false, &fifo->user.mem); - if (ret) - return ret; - - ret = nvkm_bar_umap(bar, 128 * 0x1000, 12, &fifo->user.bar); - if (ret) - return ret; - - nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); - - ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent); - if (ret) - return ret; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = gf100_fifo_intr; - return 0; + return nvkm_fifo_ctor(&gf100_fifo, device, index, 128, &fifo->base); } - - -struct nvkm_oclass * -gf100_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0xc0), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_fifo_ctor, - .dtor = gf100_fifo_dtor, - .init = gf100_fifo_init, - .fini = _nvkm_fifo_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index a69f61f3ecac..465b52dee277 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -26,35 +26,27 @@ #include #include +#include #include #include #include #include -static void -gk104_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +void +gk104_fifo_uevent_fini(struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); } -static void -gk104_fifo_uevent_init(struct nvkm_event *event, int type, int index) +void +gk104_fifo_uevent_init(struct nvkm_fifo *fifo) { - struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); struct nvkm_device *device = fifo->engine.subdev.device; nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); } -static const struct nvkm_event_func -gk104_fifo_uevent_func = { - .ctor = nvkm_fifo_uevent_ctor, - .init = gk104_fifo_uevent_init, - .fini = gk104_fifo_uevent_fini, -}; - void gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) { @@ -65,7 +57,7 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) struct nvkm_memory *cur; int nr = 0; - mutex_lock(&nv_subdev(fifo)->mutex); + mutex_lock(&subdev->mutex); cur = engn->runlist[engn->cur_runlist]; engn->cur_runlist = !engn->cur_runlist; @@ -84,15 +76,16 @@ gk104_fifo_runlist_update(struct gk104_fifo *fifo, u32 engine) (engine * 0x08)) & 0x00100000), msecs_to_jiffies(2000)) == 0) nvkm_error(subdev, "runlist %d update timeout\n", engine); - mutex_unlock(&nv_subdev(fifo)->mutex); + mutex_unlock(&subdev->mutex); } static inline struct nvkm_engine * gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn) { + struct nvkm_device *device = fifo->base.engine.subdev.device; u64 subdevs = gk104_fifo_engine_subdev(engn); if (subdevs) - return nvkm_engine(fifo, __ffs(subdevs)); + return nvkm_device_engine(device, __ffs(subdevs)); return NULL; } @@ -136,14 +129,14 @@ gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine, u32 chid = chan->base.chid; nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", - nvkm_subdev_name[nv_subdev(engine)->index], chid); + nvkm_subdev_name[engine->subdev.index], chid); assert_spin_locked(&fifo->base.lock); nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); list_del_init(&chan->head); chan->killed = true; - fifo->mask |= 1ULL << nv_engidx(engine); + fifo->mask |= 1ULL << engine->subdev.index; schedule_work(&fifo->fault); } @@ -399,7 +392,7 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: - engine = nvkm_engine(fifo, eu->data2); + engine = nvkm_device_engine(device, eu->data2); break; } } @@ -542,11 +535,12 @@ gk104_fifo_intr_engine(struct gk104_fifo *fifo) nvkm_fifo_uevent(&fifo->base); } -static void -gk104_fifo_intr(struct nvkm_subdev *subdev) +void +gk104_fifo_intr(struct nvkm_fifo *base) { - struct gk104_fifo *fifo = (void *)subdev; - struct nvkm_device *device = fifo->base.engine.subdev.device; + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 mask = nvkm_rd32(device, 0x002140); u32 stat = nvkm_rd32(device, 0x002100) & mask; @@ -633,33 +627,62 @@ gk104_fifo_intr(struct nvkm_subdev *subdev) } } +void +gk104_fifo_fini(struct nvkm_fifo *base) +{ + struct gk104_fifo *fifo = gk104_fifo(base); + struct nvkm_device *device = fifo->base.engine.subdev.device; + flush_work(&fifo->fault); + /* allow mmu fault interrupts, even when we're not using fifo */ + nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); +} + int -gk104_fifo_fini(struct nvkm_object *object, bool suspend) +gk104_fifo_oneinit(struct nvkm_fifo *base) { - struct gk104_fifo *fifo = (void *)object; + struct gk104_fifo *fifo = gk104_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; - int ret; + int ret, i; - ret = nvkm_fifo_fini(&fifo->base, suspend); + for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) { + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, + 0x8000, 0x1000, false, + &fifo->engine[i].runlist[0]); + if (ret) + return ret; + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, + 0x8000, 0x1000, false, + &fifo->engine[i].runlist[1]); + if (ret) + return ret; + + init_waitqueue_head(&fifo->engine[i].wait); + INIT_LIST_HEAD(&fifo->engine[i].chan); + } + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, + fifo->base.nr * 0x200, 0x1000, true, + &fifo->user.mem); if (ret) return ret; - /* allow mmu fault interrupts, even when we're not using fifo */ - nvkm_mask(device, 0x002140, 0x10000000, 0x10000000); + ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12, + &fifo->user.bar); + if (ret) + return ret; + + nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); return 0; } -int -gk104_fifo_init(struct nvkm_object *object) +void +gk104_fifo_init(struct nvkm_fifo *base) { - struct gk104_fifo *fifo = (void *)object; + struct gk104_fifo *fifo = gk104_fifo(base); struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - int ret, i; - - ret = nvkm_fifo_init(&fifo->base); - if (ret) - return ret; + int i; /* enable all available PBDMA units */ nvkm_wr32(device, 0x000204, 0xffffffff); @@ -683,13 +706,12 @@ gk104_fifo_init(struct nvkm_object *object) nvkm_wr32(device, 0x002100, 0xffffffff); nvkm_wr32(device, 0x002140, 0x7fffffff); - return 0; } -void -gk104_fifo_dtor(struct nvkm_object *object) +void * +gk104_fifo_dtor(struct nvkm_fifo *base) { - struct gk104_fifo *fifo = (void *)object; + struct gk104_fifo *fifo = gk104_fifo(base); int i; nvkm_vm_put(&fifo->user.bar); @@ -700,11 +722,32 @@ gk104_fifo_dtor(struct nvkm_object *object) nvkm_memory_del(&fifo->engine[i].runlist[0]); } - nvkm_fifo_destroy(&fifo->base); + return fifo; +} + +int +gk104_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, + int index, int nr, struct nvkm_fifo **pfifo) +{ + struct gk104_fifo *fifo; + + if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) + return -ENOMEM; + INIT_WORK(&fifo->fault, gk104_fifo_recover_work); + *pfifo = &fifo->base; + + return nvkm_fifo_ctor(func, device, index, nr, &fifo->base); } static const struct nvkm_fifo_func -gk104_fifo_func = { +gk104_fifo = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = gk104_fifo_intr, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, .chan = { &gk104_fifo_gpfifo_oclass, NULL @@ -712,72 +755,7 @@ gk104_fifo_func = { }; int -gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - struct nvkm_device *device = (void *)parent; - struct nvkm_bar *bar = device->bar; - struct gk104_fifo_impl *impl = (void *)oclass; - struct gk104_fifo *fifo; - int ret, i; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, - impl->channels - 1, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &gk104_fifo_func; - - INIT_WORK(&fifo->fault, gk104_fifo_recover_work); - - for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) { - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, - 0x8000, 0x1000, false, - &fifo->engine[i].runlist[0]); - if (ret) - return ret; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, - 0x8000, 0x1000, false, - &fifo->engine[i].runlist[1]); - if (ret) - return ret; - - init_waitqueue_head(&fifo->engine[i].wait); - INIT_LIST_HEAD(&fifo->engine[i].chan); - } - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, - impl->channels * 0x200, 0x1000, - true, &fifo->user.mem); - if (ret) - return ret; - - ret = nvkm_bar_umap(bar, impl->channels * 0x200, 12, &fifo->user.bar); - if (ret) - return ret; - - nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0); - - ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &fifo->base.uevent); - if (ret) - return ret; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = gk104_fifo_intr; - return 0; + return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo); } - -struct nvkm_oclass * -gk104_fifo_oclass = &(struct gk104_fifo_impl) { - .base.handle = NV_ENGINE(FIFO, 0xe0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_fifo_ctor, - .dtor = gk104_fifo_dtor, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, - }, - .channels = 4096, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index 1103e6b1ee5a..7a5c544a5ffb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -26,23 +26,17 @@ struct gk104_fifo { int spoon_nr; }; -struct gk104_fifo_impl { - struct nvkm_oclass base; - u32 channels; -}; - -int gk104_fifo_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); -void gk104_fifo_dtor(struct nvkm_object *); -int gk104_fifo_init(struct nvkm_object *); -int gk104_fifo_fini(struct nvkm_object *, bool); +int gk104_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, + int index, int nr, struct nvkm_fifo **); +void *gk104_fifo_dtor(struct nvkm_fifo *); +int gk104_fifo_oneinit(struct nvkm_fifo *); +void gk104_fifo_init(struct nvkm_fifo *); +void gk104_fifo_fini(struct nvkm_fifo *); +void gk104_fifo_intr(struct nvkm_fifo *); +void gk104_fifo_uevent_init(struct nvkm_fifo *); +void gk104_fifo_uevent_fini(struct nvkm_fifo *); void gk104_fifo_runlist_update(struct gk104_fifo *, u32 engine); -int gm204_fifo_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); - static inline u64 gk104_fifo_engine_subdev(int engine) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index 927092217a06..ce01c1a7d41c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -22,15 +22,25 @@ * Authors: Ben Skeggs */ #include "gk104.h" +#include "changk104.h" -struct nvkm_oclass * -gk208_fifo_oclass = &(struct gk104_fifo_impl) { - .base.handle = NV_ENGINE(FIFO, 0x08), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_fifo_ctor, - .dtor = gk104_fifo_dtor, - .init = gk104_fifo_init, - .fini = _nvkm_fifo_fini, +static const struct nvkm_fifo_func +gk208_fifo = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = gk104_fifo_intr, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, + .chan = { + &gk104_fifo_gpfifo_oclass, + NULL }, - .channels = 1024, -}.base; +}; + +int +gk208_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +{ + return gk104_fifo_new_(&gk208_fifo, device, index, 1024, pfifo); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index b30dc87a1357..b47fe98f4181 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -20,15 +20,25 @@ * DEALINGS IN THE SOFTWARE. */ #include "gk104.h" +#include "changk104.h" -struct nvkm_oclass * -gk20a_fifo_oclass = &(struct gk104_fifo_impl) { - .base.handle = NV_ENGINE(FIFO, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_fifo_ctor, - .dtor = gk104_fifo_dtor, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, +static const struct nvkm_fifo_func +gk20a_fifo = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = gk104_fifo_intr, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, + .chan = { + &gk104_fifo_gpfifo_oclass, + NULL }, - .channels = 128, -}.base; +}; + +int +gk20a_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +{ + return gk104_fifo_new_(&gk20a_fifo, device, index, 128, pfifo); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c index 18c68ac741a0..2db629f1bf7e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm204.c @@ -25,7 +25,14 @@ #include "changk104.h" static const struct nvkm_fifo_func -gm204_fifo_func = { +gm204_fifo = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = gk104_fifo_intr, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, .chan = { &gm204_fifo_gpfifo_oclass, NULL @@ -33,26 +40,7 @@ gm204_fifo_func = { }; int -gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +gm204_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); - if (ret == 0) { - struct gk104_fifo *fifo = (void *)*pobject; - fifo->base.func = &gm204_fifo_func; - } - return ret; + return gk104_fifo_new_(&gm204_fifo, device, index, 4096, pfifo); } - -struct nvkm_oclass * -gm204_fifo_oclass = &(struct gk104_fifo_impl) { - .base.handle = NV_ENGINE(FIFO, 0x24), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gm204_fifo_ctor, - .dtor = gk104_fifo_dtor, - .init = gk104_fifo_init, - .fini = _nvkm_fifo_fini, - }, - .channels = 4096, -}.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c index 4abf547c34e6..ae6375d9760f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c @@ -20,15 +20,25 @@ * DEALINGS IN THE SOFTWARE. */ #include "gk104.h" +#include "changk104.h" -struct nvkm_oclass * -gm20b_fifo_oclass = &(struct gk104_fifo_impl) { - .base.handle = NV_ENGINE(FIFO, 0x2b), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gm204_fifo_ctor, - .dtor = gk104_fifo_dtor, - .init = gk104_fifo_init, - .fini = gk104_fifo_fini, +static const struct nvkm_fifo_func +gm20b_fifo = { + .dtor = gk104_fifo_dtor, + .oneinit = gk104_fifo_oneinit, + .init = gk104_fifo_init, + .fini = gk104_fifo_fini, + .intr = gk104_fifo_intr, + .uevent_init = gk104_fifo_uevent_init, + .uevent_fini = gk104_fifo_uevent_fini, + .chan = { + &gm204_fifo_gpfifo_oclass, + NULL }, - .channels = 512, -}.base; +}; + +int +gm20b_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +{ + return gk104_fifo_new_(&gm20b_fifo, device, index, 512, pfifo); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index eb9195a6f375..5d76c3013a80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -24,6 +24,7 @@ #include "changf100.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index 2595cf92ff80..fe39981915b6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -24,6 +24,7 @@ #include "changk104.h" #include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index d1ad3fa72c34..e6f04e87139a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c @@ -32,8 +32,8 @@ #include #include -static struct ramfc_desc -nv04_ramfc[] = { +static const struct nv04_fifo_ramfc +nv04_fifo_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, @@ -46,10 +46,10 @@ nv04_ramfc[] = { }; void -nv04_fifo_pause(struct nvkm_fifo *obj, unsigned long *pflags) +nv04_fifo_pause(struct nvkm_fifo *base, unsigned long *pflags) __acquires(fifo->base.lock) { - struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base); + struct nv04_fifo *fifo = nv04_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; unsigned long flags; @@ -82,10 +82,10 @@ __acquires(fifo->base.lock) } void -nv04_fifo_start(struct nvkm_fifo *obj, unsigned long *pflags) +nv04_fifo_start(struct nvkm_fifo *base, unsigned long *pflags) __releases(fifo->base.lock) { - struct nv04_fifo *fifo = container_of(obj, typeof(*fifo), base); + struct nv04_fifo *fifo = nv04_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; unsigned long flags = *pflags; @@ -236,10 +236,11 @@ nv04_fifo_dma_pusher(struct nv04_fifo *fifo, u32 chid) } void -nv04_fifo_intr(struct nvkm_subdev *subdev) +nv04_fifo_intr(struct nvkm_fifo *base) { + struct nv04_fifo *fifo = nv04_fifo(base); + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct nv04_fifo *fifo = (void *)subdev; u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; u32 reassign, chid, get, sem; @@ -293,20 +294,15 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); } -int -nv04_fifo_init(struct nvkm_object *object) +void +nv04_fifo_init(struct nvkm_fifo *base) { - struct nv04_fifo *fifo = (void *)object; + struct nv04_fifo *fifo = nv04_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; struct nvkm_ramht *ramht = imem->ramht; struct nvkm_memory *ramro = imem->ramro; struct nvkm_memory *ramfc = imem->ramfc; - int ret; - - ret = nvkm_fifo_init(&fifo->base); - if (ret) - return ret; nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); @@ -325,54 +321,44 @@ nv04_fifo_init(struct nvkm_object *object) nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); nvkm_wr32(device, NV03_PFIFO_CACHES, 1); - return 0; } -void -nv04_fifo_dtor(struct nvkm_object *object) -{ - struct nv04_fifo *fifo = (void *)object; - nvkm_fifo_destroy(&fifo->base); -} - -static const struct nvkm_fifo_func -nv04_fifo_func = { - .chan = { - &nv04_fifo_dma_oclass, - NULL - }, -}; - -static int -nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, + int index, int nr, const struct nv04_fifo_ramfc *ramfc, + struct nvkm_fifo **pfifo) { struct nv04_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &fifo); - *pobject = nv_object(fifo); + if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) + return -ENOMEM; + fifo->ramfc = ramfc; + *pfifo = &fifo->base; + + ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base); if (ret) return ret; - fifo->base.func = &nv04_fifo_func; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv04_ramfc; + set_bit(nr - 1, fifo->base.mask); /* inactive channel */ return 0; } -struct nvkm_oclass * -nv04_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_fifo_ctor, - .dtor = nv04_fifo_dtor, - .init = nv04_fifo_init, - .fini = _nvkm_fifo_fini, +static const struct nvkm_fifo_func +nv04_fifo = { + .init = nv04_fifo_init, + .intr = nv04_fifo_intr, + .pause = nv04_fifo_pause, + .start = nv04_fifo_start, + .chan = { + &nv04_fifo_dma_oclass, + NULL }, }; + +int +nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +{ + return nv04_fifo_new_(&nv04_fifo, device, index, 16, + nv04_fifo_ramfc, pfifo); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h index c33dc56f8e02..03f60004bf7c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h @@ -3,7 +3,7 @@ #define nv04_fifo(p) container_of((p), struct nv04_fifo, base) #include "priv.h" -struct ramfc_desc { +struct nv04_fifo_ramfc { unsigned bits:6; unsigned ctxs:5; unsigned ctxp:8; @@ -13,9 +13,11 @@ struct ramfc_desc { struct nv04_fifo { struct nvkm_fifo base; - struct ramfc_desc *ramfc_desc; + const struct nv04_fifo_ramfc *ramfc; }; -void nv04_fifo_dtor(struct nvkm_object *); -int nv04_fifo_init(struct nvkm_object *); +int nv04_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, + int index, int nr, const struct nv04_fifo_ramfc *, + struct nvkm_fifo **); +void nv04_fifo_init(struct nvkm_fifo *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c index d7fab9598fb0..f9a87deb2b3d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.c @@ -25,8 +25,8 @@ #include "channv04.h" #include "regsnv04.h" -static struct ramfc_desc -nv10_ramfc[] = { +static const struct nv04_fifo_ramfc +nv10_fifo_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, @@ -40,43 +40,20 @@ nv10_ramfc[] = { }; static const struct nvkm_fifo_func -nv10_fifo_func = { +nv10_fifo = { + .init = nv04_fifo_init, + .intr = nv04_fifo_intr, + .pause = nv04_fifo_pause, + .start = nv04_fifo_start, .chan = { &nv10_fifo_dma_oclass, NULL }, }; -static int -nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv10_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - struct nv04_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &nv10_fifo_func; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv10_ramfc; - return 0; + return nv04_fifo_new_(&nv10_fifo, device, index, 32, + nv10_fifo_ramfc, pfifo); } - -struct nvkm_oclass * -nv10_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0x10), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv10_fifo_ctor, - .dtor = nv04_fifo_dtor, - .init = nv04_fifo_init, - .fini = _nvkm_fifo_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c index a8e28fc24e75..f6d383a21222 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c @@ -28,8 +28,8 @@ #include #include -static struct ramfc_desc -nv17_ramfc[] = { +static const struct nv04_fifo_ramfc +nv17_fifo_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, @@ -47,20 +47,15 @@ nv17_ramfc[] = { {} }; -static int -nv17_fifo_init(struct nvkm_object *object) +static void +nv17_fifo_init(struct nvkm_fifo *base) { - struct nv04_fifo *fifo = (void *)object; + struct nv04_fifo *fifo = nv04_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_instmem *imem = device->imem; struct nvkm_ramht *ramht = imem->ramht; struct nvkm_memory *ramro = imem->ramro; struct nvkm_memory *ramfc = imem->ramfc; - int ret; - - ret = nvkm_fifo_init(&fifo->base); - if (ret) - return ret; nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); @@ -80,47 +75,23 @@ nv17_fifo_init(struct nvkm_object *object) nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); nvkm_wr32(device, NV03_PFIFO_CACHES, 1); - return 0; } static const struct nvkm_fifo_func -nv17_fifo_func = { +nv17_fifo = { + .init = nv17_fifo_init, + .intr = nv04_fifo_intr, + .pause = nv04_fifo_pause, + .start = nv04_fifo_start, .chan = { &nv17_fifo_dma_oclass, NULL }, }; -static int -nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - struct nv04_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &nv17_fifo_func; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv17_ramfc; - return 0; + return nv04_fifo_new_(&nv17_fifo, device, index, 32, + nv17_fifo_ramfc, pfifo); } - -struct nvkm_oclass * -nv17_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0x17), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv17_fifo_ctor, - .dtor = nv04_fifo_dtor, - .init = nv17_fifo_init, - .fini = _nvkm_fifo_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index aca146377d36..8c7ba32763c4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -29,8 +29,8 @@ #include #include -static struct ramfc_desc -nv40_ramfc[] = { +static const struct nv04_fifo_ramfc +nv40_fifo_ramfc[] = { { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, @@ -56,21 +56,16 @@ nv40_ramfc[] = { {} }; -static int -nv40_fifo_init(struct nvkm_object *object) +static void +nv40_fifo_init(struct nvkm_fifo *base) { - struct nv04_fifo *fifo = (void *)object; + struct nv04_fifo *fifo = nv04_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; struct nvkm_fb *fb = device->fb; struct nvkm_instmem *imem = device->imem; struct nvkm_ramht *ramht = imem->ramht; struct nvkm_memory *ramro = imem->ramro; struct nvkm_memory *ramfc = imem->ramfc; - int ret; - - ret = nvkm_fifo_init(&fifo->base); - if (ret) - return ret; nvkm_wr32(device, 0x002040, 0x000000ff); nvkm_wr32(device, 0x002044, 0x2101ffff); @@ -81,7 +76,7 @@ nv40_fifo_init(struct nvkm_object *object) (ramht->gpuobj->addr >> 8)); nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); - switch (nv_device(fifo)->chipset) { + switch (device->chipset) { case 0x47: case 0x49: case 0x4b: @@ -110,47 +105,23 @@ nv40_fifo_init(struct nvkm_object *object) nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); nvkm_wr32(device, NV03_PFIFO_CACHES, 1); - return 0; } static const struct nvkm_fifo_func -nv40_fifo_func = { +nv40_fifo = { + .init = nv40_fifo_init, + .intr = nv04_fifo_intr, + .pause = nv04_fifo_pause, + .start = nv04_fifo_start, .chan = { &nv40_fifo_dma_oclass, NULL }, }; -static int -nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) { - struct nv04_fifo *fifo; - int ret; - - ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &nv40_fifo_func; - - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; - fifo->ramfc_desc = nv40_ramfc; - return 0; + return nv04_fifo_new_(&nv40_fifo, device, index, 32, + nv40_fifo_ramfc, pfifo); } - -struct nvkm_oclass * -nv40_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0x40), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv40_fifo_ctor, - .dtor = nv04_fifo_dtor, - .init = nv40_fifo_init, - .fini = _nvkm_fifo_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c index ad653e9c461a..66eb12c2b5ba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.c @@ -24,6 +24,8 @@ #include "nv50.h" #include "channv50.h" +#include + static void nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) { @@ -49,22 +51,34 @@ nv50_fifo_runlist_update_locked(struct nv50_fifo *fifo) void nv50_fifo_runlist_update(struct nv50_fifo *fifo) { - mutex_lock(&nv_subdev(fifo)->mutex); + mutex_lock(&fifo->base.engine.subdev.mutex); nv50_fifo_runlist_update_locked(fifo); - mutex_unlock(&nv_subdev(fifo)->mutex); + mutex_unlock(&fifo->base.engine.subdev.mutex); } int -nv50_fifo_init(struct nvkm_object *object) +nv50_fifo_oneinit(struct nvkm_fifo *base) { - struct nv50_fifo *fifo = (void *)object; + struct nv50_fifo *fifo = nv50_fifo(base); struct nvkm_device *device = fifo->base.engine.subdev.device; - int ret, i; + int ret; - ret = nvkm_fifo_init(&fifo->base); + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, + false, &fifo->runlist[0]); if (ret) return ret; + return nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, + false, &fifo->runlist[1]); +} + +void +nv50_fifo_init(struct nvkm_fifo *base) +{ + struct nv50_fifo *fifo = nv50_fifo(base); + struct nvkm_device *device = fifo->base.engine.subdev.device; + int i; + nvkm_mask(device, 0x000200, 0x00000100, 0x00000000); nvkm_mask(device, 0x000200, 0x00000100, 0x00000100); nvkm_wr32(device, 0x00250c, 0x6f3cfc34); @@ -80,69 +94,54 @@ nv50_fifo_init(struct nvkm_object *object) nvkm_wr32(device, 0x003200, 0x00000001); nvkm_wr32(device, 0x003250, 0x00000001); nvkm_wr32(device, 0x002500, 0x00000001); - return 0; } -void -nv50_fifo_dtor(struct nvkm_object *object) +void * +nv50_fifo_dtor(struct nvkm_fifo *base) { - struct nv50_fifo *fifo = (void *)object; - + struct nv50_fifo *fifo = nv50_fifo(base); nvkm_memory_del(&fifo->runlist[1]); nvkm_memory_del(&fifo->runlist[0]); - - nvkm_fifo_destroy(&fifo->base); + return fifo; } -static const struct nvkm_fifo_func -nv50_fifo_func = { - .chan = { - &nv50_fifo_dma_oclass, - &nv50_fifo_gpfifo_oclass, - NULL - }, -}; - -static int -nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv50_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, + int index, struct nvkm_fifo **pfifo) { - struct nvkm_device *device = (void *)parent; struct nv50_fifo *fifo; int ret; - ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo); - *pobject = nv_object(fifo); - if (ret) - return ret; - - fifo->base.func = &nv50_fifo_func; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->runlist[0]); - if (ret) - return ret; + if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL))) + return -ENOMEM; + *pfifo = &fifo->base; - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 128 * 4, 0x1000, - false, &fifo->runlist[1]); + ret = nvkm_fifo_ctor(func, device, index, 128, &fifo->base); if (ret) return ret; - nv_subdev(fifo)->unit = 0x00000100; - nv_subdev(fifo)->intr = nv04_fifo_intr; - fifo->base.pause = nv04_fifo_pause; - fifo->base.start = nv04_fifo_start; + set_bit(0, fifo->base.mask); /* PIO channel */ + set_bit(127, fifo->base.mask); /* inactive channel */ return 0; } -struct nvkm_oclass * -nv50_fifo_oclass = &(struct nvkm_oclass) { - .handle = NV_ENGINE(FIFO, 0x50), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_fifo_ctor, - .dtor = nv50_fifo_dtor, - .init = nv50_fifo_init, - .fini = _nvkm_fifo_fini, +static const struct nvkm_fifo_func +nv50_fifo = { + .dtor = nv50_fifo_dtor, + .oneinit = nv50_fifo_oneinit, + .init = nv50_fifo_init, + .intr = nv04_fifo_intr, + .pause = nv04_fifo_pause, + .start = nv04_fifo_start, + .chan = { + &nv50_fifo_dma_oclass, + &nv50_fifo_gpfifo_oclass, + NULL }, }; + +int +nv50_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) +{ + return nv50_fifo_new_(&nv50_fifo, device, index, pfifo); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h index a7d5dba12fb8..8ab53948cbb4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.h @@ -9,7 +9,11 @@ struct nv50_fifo { int cur_runlist; }; -void nv50_fifo_dtor(struct nvkm_object *); -int nv50_fifo_init(struct nvkm_object *); +int nv50_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *, + int index, struct nvkm_fifo **); + +void *nv50_fifo_dtor(struct nvkm_fifo *); +int nv50_fifo_oneinit(struct nvkm_fifo *); +void nv50_fifo_init(struct nvkm_fifo *); void nv50_fifo_runlist_update(struct nv50_fifo *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index a30d160f30db..cb1432e9be08 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -1,7 +1,26 @@ #ifndef __NVKM_FIFO_PRIV_H__ #define __NVKM_FIFO_PRIV_H__ +#define nvkm_fifo(p) container_of((p), struct nvkm_fifo, engine) #include +int nvkm_fifo_ctor(const struct nvkm_fifo_func *, struct nvkm_device *, + int index, int nr, struct nvkm_fifo *); +void nvkm_fifo_uevent(struct nvkm_fifo *); + +struct nvkm_fifo_func { + void *(*dtor)(struct nvkm_fifo *); + int (*oneinit)(struct nvkm_fifo *); + void (*init)(struct nvkm_fifo *); + void (*fini)(struct nvkm_fifo *); + void (*intr)(struct nvkm_fifo *); + void (*pause)(struct nvkm_fifo *, unsigned long *); + void (*start)(struct nvkm_fifo *, unsigned long *); + void (*uevent_init)(struct nvkm_fifo *); + void (*uevent_fini)(struct nvkm_fifo *); + const struct nvkm_fifo_chan_oclass *chan[]; +}; + +void nv04_fifo_intr(struct nvkm_fifo *); void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index f06c16f61a98..a5a4bdd9863e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -25,6 +25,7 @@ #include "regs.h" #include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 98fb9e6efb97..d5e44a7332eb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -25,6 +25,7 @@ #include "regs.h" #include +#include #include #include #include @@ -1055,14 +1056,14 @@ nv10_gr_tile_prog(struct nvkm_engine *engine, int i) struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; - fifo->pause(fifo, &flags); + nvkm_fifo_pause(fifo, &flags); nv04_gr_idle(&gr->base); nvkm_wr32(device, NV10_PGRAPH_TLIMIT(i), tile->limit); nvkm_wr32(device, NV10_PGRAPH_TSIZE(i), tile->pitch); nvkm_wr32(device, NV10_PGRAPH_TILE(i), tile->addr); - fifo->start(fifo, &flags); + nvkm_fifo_start(fifo, &flags); } const struct nvkm_bitfield nv10_gr_intr_name[] = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 554f2e3f7e5b..ce4f9925ea9b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -2,6 +2,7 @@ #include "regs.h" #include +#include #include #include #include @@ -152,7 +153,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; - fifo->pause(fifo, &flags); + nvkm_fifo_pause(fifo, &flags); nv04_gr_idle(&gr->base); nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); @@ -172,7 +173,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); } - fifo->start(fifo, &flags); + nvkm_fifo_start(fifo, &flags); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index 7fb53d53426c..cc56ca9505f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -1,6 +1,7 @@ #include "nv20.h" #include "regs.h" +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index 2fabdc586651..4e4cd93d686d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -1,6 +1,7 @@ #include "nv20.h" #include "regs.h" +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index 8f5bfe3aa487..ea46b16c31e6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -1,6 +1,7 @@ #include "nv20.h" #include "regs.h" +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 3781a5b311fb..0667e9d14b42 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -1,6 +1,7 @@ #include "nv20.h" #include "regs.h" +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 285c4eff2e5b..745d0e133d9a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -1,6 +1,7 @@ #include "nv20.h" #include "regs.h" +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 0e4e1152eeec..be954500b4d8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -25,6 +25,7 @@ #include "regs.h" #include +#include #include #include #include @@ -176,7 +177,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; - fifo->pause(fifo, &flags); + nvkm_fifo_pause(fifo, &flags); nv04_gr_idle(&gr->base); switch (nv_device(gr)->chipset) { @@ -243,7 +244,7 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) break; } - fifo->start(fifo, &flags); + nvkm_fifo_start(fifo, &flags); } static void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 2a5bc9270fb9..11c4c8838937 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -24,6 +24,7 @@ #include "nv50.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 417cc31a12ef..f79749946b72 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -24,6 +24,7 @@ #include "nv31.h" #include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c index 0f9ef18bf18d..d1b914b43cee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c @@ -25,6 +25,7 @@ #include "priv.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c index 1ec4f4fde1c2..995c2c5ec150 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.c @@ -27,6 +27,7 @@ #include #include +#include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c index 4ca6b88e9a7f..5cd7844f1d5f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.c @@ -23,6 +23,7 @@ */ #include "nv50.h" +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 6c93a20295a4..a00d9a55e53b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -23,6 +23,7 @@ */ #include "nv50.h" +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index fa36233a71dd..d6a2b9593538 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -20,6 +20,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include + +#include #include static int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index e5258ba19834..07feae620c8d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -317,7 +317,7 @@ gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) return -EBUSY; if (fifo) - fifo->pause(fifo, flags); + nvkm_fifo_pause(fifo, flags); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x002504) & 0x00000010) @@ -342,7 +342,7 @@ gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) struct nvkm_fifo *fifo = device->fifo; if (fifo && flags) - fifo->start(fifo, flags); + nvkm_fifo_start(fifo, flags); nvkm_mask(device, 0x002504, 0x00000001, 0x00000000); nvkm_mask(device, 0x020060, 0x00070000, 0x00040000); -- cgit v1.2.3 From c85ee6ca79590cd51356bf24fb8936bc352138cf Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:22 +1000 Subject: drm/nouveau/gr: convert to new-style nvkm_engine Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/engine.h | 4 +- drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h | 94 ++--- drivers/gpu/drm/nouveau/nouveau_abi16.c | 2 +- drivers/gpu/drm/nouveau/nouveau_bo.c | 3 +- drivers/gpu/drm/nouveau/nvkm/core/engine.c | 15 +- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 138 +++---- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 9 - drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 2 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 8 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 4 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 5 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 16 - drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 14 - drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild | 16 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c | 82 +++- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c | 3 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c | 196 +++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 455 +++++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h | 71 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c | 23 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c | 23 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c | 23 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c | 23 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c | 67 +-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c | 25 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c | 165 ++++---- drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h | 35 -- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c | 37 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c | 36 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c | 21 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c | 28 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c | 47 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c | 48 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c | 46 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c | 48 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 122 +++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 221 +++------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h | 13 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c | 59 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c | 59 +++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 159 ++++--- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h | 22 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c | 43 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c | 43 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c | 115 ++---- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c | 43 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c | 43 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 210 ++++------ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h | 13 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c | 108 +++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 372 +++-------------- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h | 16 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h | 23 ++ drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 14 +- 60 files changed, 1763 insertions(+), 1866 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index 9d9c0e779f3f..9c8c39324715 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -3,6 +3,7 @@ #include struct nvkm_device_oclass; /*XXX: DEV!ENG */ struct nvkm_fifo_chan; +struct nvkm_fb_tile; #define NV_ENGINE_(eng,var) (((var) << 8) | (eng)) #define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var)) @@ -20,7 +21,6 @@ struct nvkm_engine { spinlock_t lock; void (*tile_prog)(struct nvkm_engine *, int region); - int (*tlb_flush)(struct nvkm_engine *); }; struct nvkm_engine_func { @@ -29,6 +29,7 @@ struct nvkm_engine_func { int (*init)(struct nvkm_engine *); int (*fini)(struct nvkm_engine *, bool suspend); void (*intr)(struct nvkm_engine *); + void (*tile)(struct nvkm_engine *, int region, struct nvkm_fb_tile *); struct { int (*sclass)(struct nvkm_oclass *, int index, @@ -54,6 +55,7 @@ int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *, struct nvkm_engine **); struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *); void nvkm_engine_unref(struct nvkm_engine **); +void nvkm_engine_tile(struct nvkm_engine *, int region); static inline struct nvkm_engine * nv_engine(void *obj) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h index f09f1521e6ad..f126e54d2e30 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h @@ -3,64 +3,44 @@ #include struct nvkm_gr { - struct nvkm_engine engine; const struct nvkm_gr_func *func; - - /* Returns chipset-specific counts of units packed into an u64. - */ - u64 (*units)(struct nvkm_gr *); + struct nvkm_engine engine; }; -#define nvkm_gr_create(p,e,c,y,d) \ - nvkm_gr_create_((p), (e), (c), (y), sizeof(**d), (void **)(d)) -int -nvkm_gr_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, bool enable, - int length, void **pobject); -#define nvkm_gr_destroy(d) \ - nvkm_engine_destroy(&(d)->engine) -#define nvkm_gr_init(d) \ - nvkm_engine_init_old(&(d)->engine) -#define nvkm_gr_fini(d,s) \ - nvkm_engine_fini_old(&(d)->engine, (s)) - -#define _nvkm_gr_dtor _nvkm_engine_dtor -#define _nvkm_gr_init _nvkm_engine_init -#define _nvkm_gr_fini _nvkm_engine_fini - -extern struct nvkm_oclass nv04_gr_oclass; -extern struct nvkm_oclass nv10_gr_oclass; -extern struct nvkm_oclass nv20_gr_oclass; -extern struct nvkm_oclass nv25_gr_oclass; -extern struct nvkm_oclass nv2a_gr_oclass; -extern struct nvkm_oclass nv30_gr_oclass; -extern struct nvkm_oclass nv34_gr_oclass; -extern struct nvkm_oclass nv35_gr_oclass; -extern struct nvkm_oclass nv40_gr_oclass; -extern struct nvkm_oclass nv50_gr_oclass; -extern struct nvkm_oclass *gf100_gr_oclass; -extern struct nvkm_oclass *gf108_gr_oclass; -extern struct nvkm_oclass *gf104_gr_oclass; -extern struct nvkm_oclass *gf110_gr_oclass; -extern struct nvkm_oclass *gf117_gr_oclass; -extern struct nvkm_oclass *gf119_gr_oclass; -extern struct nvkm_oclass *gk104_gr_oclass; -extern struct nvkm_oclass *gk20a_gr_oclass; -extern struct nvkm_oclass *gk110_gr_oclass; -extern struct nvkm_oclass *gk110b_gr_oclass; -extern struct nvkm_oclass *gk208_gr_oclass; -extern struct nvkm_oclass *gm107_gr_oclass; -extern struct nvkm_oclass *gm204_gr_oclass; -extern struct nvkm_oclass *gm206_gr_oclass; -extern struct nvkm_oclass *gm20b_gr_oclass; - -#include - -extern const struct nvkm_bitfield nv04_gr_nsource[]; -bool nv04_gr_idle(struct nvkm_gr *); - -extern const struct nvkm_bitfield nv10_gr_intr_name[]; -extern const struct nvkm_bitfield nv10_gr_nstatus[]; - -extern const struct nvkm_enum nv50_data_error_names[]; +u64 nvkm_gr_units(struct nvkm_gr *); +int nvkm_gr_tlb_flush(struct nvkm_gr *); + +int nv04_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv10_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv15_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv17_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv20_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv25_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv2a_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv30_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv34_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv35_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv40_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv44_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int nv50_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int g84_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gt200_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int mcp79_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gt215_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int mcp89_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gf100_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gf104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gf108_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gf110_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gf117_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gf119_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gk104_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gk110_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gk110b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gk208_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gk20a_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gm107_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gm204_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gm206_gr_new(struct nvkm_device *, int, struct nvkm_gr **); +int gm20b_gr_new(struct nvkm_device *, int, struct nvkm_gr **); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 98c74985e27d..6634f420ded3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -215,7 +215,7 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) getparam->value = 1; break; case NOUVEAU_GETPARAM_GRAPH_UNITS: - getparam->value = gr->units ? gr->units(gr) : 0; + getparam->value = nvkm_gr_units(gr); break; default: NV_PRINTK(dbg, cli, "unknown parameter %lld\n", getparam->param); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 140a1eb9c49e..bd33d547d574 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -48,7 +48,8 @@ nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, { struct nouveau_drm *drm = nouveau_drm(dev); int i = reg - drm->tile.reg; - struct nvkm_fb *fb = nvxx_fb(&drm->device); + struct nvkm_device *device = nvxx_device(&drm->device); + struct nvkm_fb *fb = device->fb; struct nvkm_fb_tile *tile = &fb->tile.region[i]; nouveau_fence_unref(®->fence); diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index eabd271f68b3..3fef9cc34345 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -25,6 +25,8 @@ #include #include +#include + void nvkm_engine_unref(struct nvkm_engine **pengine) { @@ -56,6 +58,14 @@ nvkm_engine_ref(struct nvkm_engine *engine) return engine; } +void +nvkm_engine_tile(struct nvkm_engine *engine, int region) +{ + struct nvkm_fb *fb = engine->subdev.device->fb; + if (engine->func->tile) + engine->func->tile(engine, region, &fb->tile.region[region]); +} + static void nvkm_engine_intr(struct nvkm_subdev *obj) { @@ -80,7 +90,8 @@ nvkm_engine_init(struct nvkm_subdev *obj) { struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); struct nvkm_subdev *subdev = &engine->subdev; - int ret = 0; + struct nvkm_fb *fb = subdev->device->fb; + int ret = 0, i; s64 time; if (!engine->usecount) { @@ -108,6 +119,8 @@ nvkm_engine_init(struct nvkm_subdev *obj) if (engine->func->init) ret = engine->func->init(engine); + for (i = 0; fb && i < fb->tile.regions; i++) + nvkm_engine_tile(engine, i); return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 62395ab742c5..3cf15d46f9d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -89,7 +89,7 @@ nv4_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv04_fifo_new, -// .gr = nv04_gr_new, + .gr = nv04_gr_new, // .sw = nv04_sw_new, }; @@ -109,7 +109,7 @@ nv5_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv04_fifo_new, -// .gr = nv04_gr_new, + .gr = nv04_gr_new, // .sw = nv04_sw_new, }; @@ -129,7 +129,7 @@ nv10_chipset = { .timer = nv04_timer_new, .disp = nv04_disp_new, .dma = nv04_dma_new, -// .gr = nv10_gr_new, + .gr = nv10_gr_new, }; static const struct nvkm_device_chip @@ -149,7 +149,7 @@ nv11_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv10_fifo_new, -// .gr = nv10_gr_new, + .gr = nv15_gr_new, // .sw = nv10_sw_new, }; @@ -170,7 +170,7 @@ nv15_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv10_fifo_new, -// .gr = nv10_gr_new, + .gr = nv15_gr_new, // .sw = nv10_sw_new, }; @@ -191,7 +191,7 @@ nv17_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv10_gr_new, + .gr = nv17_gr_new, // .sw = nv10_sw_new, }; @@ -212,7 +212,7 @@ nv18_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv10_gr_new, + .gr = nv17_gr_new, // .sw = nv10_sw_new, }; @@ -233,7 +233,7 @@ nv1a_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv10_fifo_new, -// .gr = nv10_gr_new, + .gr = nv15_gr_new, // .sw = nv10_sw_new, }; @@ -254,7 +254,7 @@ nv1f_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv10_gr_new, + .gr = nv17_gr_new, // .sw = nv10_sw_new, }; @@ -275,7 +275,7 @@ nv20_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv20_gr_new, + .gr = nv20_gr_new, // .sw = nv10_sw_new, }; @@ -296,7 +296,7 @@ nv25_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv25_gr_new, + .gr = nv25_gr_new, // .sw = nv10_sw_new, }; @@ -317,7 +317,7 @@ nv28_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv25_gr_new, + .gr = nv25_gr_new, // .sw = nv10_sw_new, }; @@ -338,7 +338,7 @@ nv2a_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv2a_gr_new, + .gr = nv2a_gr_new, // .sw = nv10_sw_new, }; @@ -359,7 +359,7 @@ nv30_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv30_gr_new, + .gr = nv30_gr_new, // .sw = nv10_sw_new, }; @@ -380,7 +380,7 @@ nv31_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv30_gr_new, + .gr = nv30_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, }; @@ -402,7 +402,7 @@ nv34_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv34_gr_new, + .gr = nv34_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, }; @@ -424,7 +424,7 @@ nv35_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv35_gr_new, + .gr = nv35_gr_new, // .sw = nv10_sw_new, }; @@ -445,7 +445,7 @@ nv36_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv17_fifo_new, -// .gr = nv35_gr_new, + .gr = nv35_gr_new, // .mpeg = nv31_mpeg_new, // .sw = nv10_sw_new, }; @@ -469,7 +469,7 @@ nv40_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -494,7 +494,7 @@ nv41_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -519,7 +519,7 @@ nv42_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -544,7 +544,7 @@ nv43_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv40_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -569,7 +569,7 @@ nv44_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -594,7 +594,7 @@ nv45_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -619,7 +619,7 @@ nv46_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -644,7 +644,7 @@ nv47_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -669,7 +669,7 @@ nv49_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -694,7 +694,7 @@ nv4a_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -719,7 +719,7 @@ nv4b_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv40_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -744,7 +744,7 @@ nv4c_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -769,7 +769,7 @@ nv4e_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -797,7 +797,7 @@ nv50_chipset = { .disp = nv50_disp_new, .dma = nv50_dma_new, .fifo = nv50_fifo_new, -// .gr = nv50_gr_new, + .gr = nv50_gr_new, // .mpeg = nv50_mpeg_new, // .pm = nv50_pm_new, // .sw = nv50_sw_new, @@ -822,7 +822,7 @@ nv63_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -847,7 +847,7 @@ nv67_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -872,7 +872,7 @@ nv68_chipset = { .disp = nv04_disp_new, .dma = nv04_dma_new, .fifo = nv40_fifo_new, -// .gr = nv40_gr_new, + .gr = nv44_gr_new, // .mpeg = nv44_mpeg_new, // .pm = nv40_pm_new, // .sw = nv10_sw_new, @@ -902,7 +902,7 @@ nv84_chipset = { .disp = g84_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = g84_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, @@ -933,7 +933,7 @@ nv86_chipset = { .disp = g84_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = g84_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, @@ -964,7 +964,7 @@ nv92_chipset = { .disp = g84_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = g84_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, @@ -995,7 +995,7 @@ nv94_chipset = { .disp = g94_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = g84_gr_new, // .mpeg = g84_mpeg_new, // .pm = g84_pm_new, // .sw = nv50_sw_new, @@ -1024,7 +1024,7 @@ nv96_chipset = { .dma = nv50_dma_new, .fifo = g84_fifo_new, // .sw = nv50_sw_new, -// .gr = nv50_gr_new, + .gr = g84_gr_new, // .mpeg = g84_mpeg_new, .vp = g84_vp_new, .cipher = g84_cipher_new, @@ -1055,7 +1055,7 @@ nv98_chipset = { .dma = nv50_dma_new, .fifo = g84_fifo_new, // .sw = nv50_sw_new, -// .gr = nv50_gr_new, + .gr = g84_gr_new, .mspdec = g98_mspdec_new, .sec = g98_sec_new, .msvld = g98_msvld_new, @@ -1088,7 +1088,7 @@ nva0_chipset = { .disp = gt200_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = gt200_gr_new, // .mpeg = g84_mpeg_new, // .pm = gt200_pm_new, // .sw = nv50_sw_new, @@ -1119,7 +1119,7 @@ nva3_chipset = { .disp = gt215_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = gt215_gr_new, // .mpeg = g84_mpeg_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, @@ -1152,7 +1152,7 @@ nva5_chipset = { .disp = gt215_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = gt215_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, @@ -1184,7 +1184,7 @@ nva8_chipset = { .disp = gt215_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = gt215_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, .msvld = gt215_msvld_new, @@ -1214,7 +1214,7 @@ nvaa_chipset = { .disp = g94_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = gt200_gr_new, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, .msvld = g98_msvld_new, @@ -1245,7 +1245,7 @@ nvac_chipset = { .disp = g94_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = mcp79_gr_new, .mspdec = g98_mspdec_new, .msppp = g98_msppp_new, .msvld = g98_msvld_new, @@ -1278,7 +1278,7 @@ nvaf_chipset = { .disp = gt215_disp_new, .dma = nv50_dma_new, .fifo = g84_fifo_new, -// .gr = nv50_gr_new, + .gr = mcp89_gr_new, .mspdec = gt215_mspdec_new, .msppp = gt215_msppp_new, .msvld = mcp89_msvld_new, @@ -1313,7 +1313,7 @@ nvc0_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf100_gr_new, + .gr = gf100_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1347,7 +1347,7 @@ nvc1_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf108_gr_new, + .gr = gf108_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1381,7 +1381,7 @@ nvc3_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf104_gr_new, + .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1416,7 +1416,7 @@ nvc4_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf104_gr_new, + .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1451,7 +1451,7 @@ nvc8_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf110_gr_new, + .gr = gf110_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1486,7 +1486,7 @@ nvce_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf104_gr_new, + .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1520,7 +1520,7 @@ nvcf_chipset = { .disp = gt215_disp_new, .dma = gf100_dma_new, .fifo = gf100_fifo_new, -// .gr = gf104_gr_new, + .gr = gf104_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1552,7 +1552,7 @@ nvd7_chipset = { .disp = gf119_disp_new, .dma = gf119_dma_new, .fifo = gf100_fifo_new, -// .gr = gf117_gr_new, + .gr = gf117_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1586,7 +1586,7 @@ nvd9_chipset = { .disp = gf119_disp_new, .dma = gf119_dma_new, .fifo = gf100_fifo_new, -// .gr = gf119_gr_new, + .gr = gf119_gr_new, .mspdec = gf100_mspdec_new, .msppp = gf100_msppp_new, .msvld = gf100_msvld_new, @@ -1622,7 +1622,7 @@ nve4_chipset = { .disp = gk104_disp_new, .dma = gf119_dma_new, .fifo = gk104_fifo_new, -// .gr = gk104_gr_new, + .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1658,7 +1658,7 @@ nve6_chipset = { .disp = gk104_disp_new, .dma = gf119_dma_new, .fifo = gk104_fifo_new, -// .gr = gk104_gr_new, + .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1694,7 +1694,7 @@ nve7_chipset = { .disp = gk104_disp_new, .dma = gf119_dma_new, .fifo = gk104_fifo_new, -// .gr = gk104_gr_new, + .gr = gk104_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1721,7 +1721,7 @@ nvea_chipset = { .ce[2] = gk104_ce_new, .dma = gf119_dma_new, .fifo = gk20a_fifo_new, -// .gr = gk20a_gr_new, + .gr = gk20a_gr_new, // .pm = gk104_pm_new, // .sw = gf100_sw_new, }; @@ -1754,7 +1754,7 @@ nvf0_chipset = { .disp = gk110_disp_new, .dma = gf119_dma_new, .fifo = gk104_fifo_new, -// .gr = gk110_gr_new, + .gr = gk110_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1790,7 +1790,7 @@ nvf1_chipset = { .disp = gk110_disp_new, .dma = gf119_dma_new, .fifo = gk104_fifo_new, -// .gr = gk110b_gr_new, + .gr = gk110b_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1826,7 +1826,7 @@ nv106_chipset = { .disp = gk110_disp_new, .dma = gf119_dma_new, .fifo = gk208_fifo_new, -// .gr = gk208_gr_new, + .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1861,7 +1861,7 @@ nv108_chipset = { .disp = gk110_disp_new, .dma = gf119_dma_new, .fifo = gk208_fifo_new, -// .gr = gk208_gr_new, + .gr = gk208_gr_new, .mspdec = gk104_mspdec_new, .msppp = gf100_msppp_new, .msvld = gk104_msvld_new, @@ -1894,7 +1894,7 @@ nv117_chipset = { .disp = gm107_disp_new, .dma = gf119_dma_new, .fifo = gk208_fifo_new, -// .gr = gm107_gr_new, + .gr = gm107_gr_new, // .sw = gf100_sw_new, }; @@ -1923,7 +1923,7 @@ nv124_chipset = { .disp = gm204_disp_new, .dma = gf119_dma_new, .fifo = gm204_fifo_new, -// .gr = gm204_gr_new, + .gr = gm204_gr_new, // .sw = gf100_sw_new, }; @@ -1952,7 +1952,7 @@ nv126_chipset = { .disp = gm204_disp_new, .dma = gf119_dma_new, .fifo = gm204_fifo_new, -// .gr = gm206_gr_new, + .gr = gm206_gr_new, // .sw = gf100_sw_new, }; @@ -1973,7 +1973,7 @@ nv12b_chipset = { .ce[2] = gm204_ce_new, .dma = gf119_dma_new, .fifo = gm20b_fifo_new, -// .gr = gm20b_gr_new, + .gr = gm20b_gr_new, // .sw = gf100_sw_new, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c index d319f5680f44..b88aceb343c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c @@ -29,47 +29,38 @@ gf100_identify(struct nvkm_device *device) switch (device->chipset) { case 0xc0: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc4: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc3: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xce: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xcf: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xc1: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf108_pm_oclass; break; case 0xc8: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf100_pm_oclass; break; case 0xd9: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; case 0xd7: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gf117_pm_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c index fe8298e02e9f..1ad7b217e2b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c @@ -29,41 +29,33 @@ gk104_identify(struct nvkm_device *device) switch (device->chipset) { case 0xe4: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe7: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xe6: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xea: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk20a_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; break; case 0xf0: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0xf1: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk110b_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = &gk110_pm_oclass; break; case 0x106: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; break; case 0x108: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 2362a634462c..71e088abb620 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -32,7 +32,6 @@ gm100_identify(struct nvkm_device *device) #if 0 #endif device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm107_gr_oclass; #if 0 #endif #if 0 @@ -46,7 +45,6 @@ gm100_identify(struct nvkm_device *device) #if 0 #endif device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm204_gr_oclass; #if 0 #endif break; @@ -58,14 +56,12 @@ gm100_identify(struct nvkm_device *device) #if 0 #endif device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm206_gr_oclass; #if 0 #endif break; case 0x12b: device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = gm20b_gr_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c index edddbaa41b43..7a8071be7ed0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c @@ -29,11 +29,9 @@ nv04_identify(struct nvkm_device *device) switch (device->chipset) { case 0x04: device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; break; case 0x05: device->oclass[NVDEV_ENGINE_SW ] = nv04_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv04_gr_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c index f1ebb9bcda3b..15dbd71ebabf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c @@ -28,35 +28,27 @@ nv10_identify(struct nvkm_device *device) { switch (device->chipset) { case 0x10: - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x15: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x16: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x1a: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x11: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x17: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x1f: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; case 0x18: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c index f9c4dad1f8ff..158efa44054f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c @@ -29,19 +29,15 @@ nv20_identify(struct nvkm_device *device) switch (device->chipset) { case 0x20: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv20_gr_oclass; break; case 0x25: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; break; case 0x28: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv25_gr_oclass; break; case 0x2a: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv2a_gr_oclass; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c index b8e1e43723a3..5a8fd485467a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c @@ -29,25 +29,20 @@ nv30_identify(struct nvkm_device *device) switch (device->chipset) { case 0x30: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; break; case 0x35: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; break; case 0x31: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv30_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; case 0x36: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv35_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; case 0x34: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv34_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c index 158ed5e395df..e3fdbf6ba871 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c @@ -29,97 +29,81 @@ nv40_identify(struct nvkm_device *device) switch (device->chipset) { case 0x40: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x41: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x42: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x43: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x45: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x47: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x49: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4b: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x44: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x46: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4a: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4c: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x4e: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x63: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x67: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; case 0x68: device->oclass[NVDEV_ENGINE_SW ] = nv10_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv40_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv40_pm_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index 688b3e2d61ff..912bd8070db7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -29,80 +29,66 @@ nv50_identify(struct nvkm_device *device) switch (device->chipset) { case 0x50: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = nv50_pm_oclass; break; case 0x84: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x86: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x92: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x94: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x96: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0x98: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa0: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt200_pm_oclass; break; case 0xaa: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xac: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = g84_pm_oclass; break; case 0xa3: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &g84_mpeg_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa5: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xa8: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; case 0xaf: device->oclass[NVDEV_ENGINE_SW ] = nv50_sw_oclass; - device->oclass[NVDEV_ENGINE_GR ] = &nv50_gr_oclass; device->oclass[NVDEV_ENGINE_PM ] = gt215_pm_oclass; break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild index 79eceaac3c1d..9ad0d0e78a96 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild @@ -1,6 +1,8 @@ nvkm-y += nvkm/engine/gr/base.o nvkm-y += nvkm/engine/gr/nv04.o nvkm-y += nvkm/engine/gr/nv10.o +nvkm-y += nvkm/engine/gr/nv15.o +nvkm-y += nvkm/engine/gr/nv17.o nvkm-y += nvkm/engine/gr/nv20.o nvkm-y += nvkm/engine/gr/nv25.o nvkm-y += nvkm/engine/gr/nv2a.o @@ -8,18 +10,24 @@ nvkm-y += nvkm/engine/gr/nv30.o nvkm-y += nvkm/engine/gr/nv34.o nvkm-y += nvkm/engine/gr/nv35.o nvkm-y += nvkm/engine/gr/nv40.o +nvkm-y += nvkm/engine/gr/nv44.o nvkm-y += nvkm/engine/gr/nv50.o +nvkm-y += nvkm/engine/gr/g84.o +nvkm-y += nvkm/engine/gr/gt200.o +nvkm-y += nvkm/engine/gr/mcp79.o +nvkm-y += nvkm/engine/gr/gt215.o +nvkm-y += nvkm/engine/gr/mcp89.o nvkm-y += nvkm/engine/gr/gf100.o -nvkm-y += nvkm/engine/gr/gf108.o nvkm-y += nvkm/engine/gr/gf104.o +nvkm-y += nvkm/engine/gr/gf108.o nvkm-y += nvkm/engine/gr/gf110.o nvkm-y += nvkm/engine/gr/gf117.o nvkm-y += nvkm/engine/gr/gf119.o nvkm-y += nvkm/engine/gr/gk104.o -nvkm-y += nvkm/engine/gr/gk20a.o nvkm-y += nvkm/engine/gr/gk110.o nvkm-y += nvkm/engine/gr/gk110b.o nvkm-y += nvkm/engine/gr/gk208.o +nvkm-y += nvkm/engine/gr/gk20a.o nvkm-y += nvkm/engine/gr/gm107.o nvkm-y += nvkm/engine/gr/gm204.o nvkm-y += nvkm/engine/gr/gm206.o @@ -28,16 +36,16 @@ nvkm-y += nvkm/engine/gr/gm20b.o nvkm-y += nvkm/engine/gr/ctxnv40.o nvkm-y += nvkm/engine/gr/ctxnv50.o nvkm-y += nvkm/engine/gr/ctxgf100.o -nvkm-y += nvkm/engine/gr/ctxgf108.o nvkm-y += nvkm/engine/gr/ctxgf104.o +nvkm-y += nvkm/engine/gr/ctxgf108.o nvkm-y += nvkm/engine/gr/ctxgf110.o nvkm-y += nvkm/engine/gr/ctxgf117.o nvkm-y += nvkm/engine/gr/ctxgf119.o nvkm-y += nvkm/engine/gr/ctxgk104.o -nvkm-y += nvkm/engine/gr/ctxgk20a.o nvkm-y += nvkm/engine/gr/ctxgk110.o nvkm-y += nvkm/engine/gr/ctxgk110b.o nvkm-y += nvkm/engine/gr/ctxgk208.o +nvkm-y += nvkm/engine/gr/ctxgk20a.o nvkm-y += nvkm/engine/gr/ctxgm107.o nvkm-y += nvkm/engine/gr/ctxgm204.o nvkm-y += nvkm/engine/gr/ctxgm206.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c index c6fb25847b89..090765ff070d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/base.c @@ -25,6 +25,30 @@ #include +static void +nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + if (gr->func->tile) + gr->func->tile(gr, region, tile); +} + +u64 +nvkm_gr_units(struct nvkm_gr *gr) +{ + if (gr->func->units) + return gr->func->units(gr); + return 0; +} + +int +nvkm_gr_tlb_flush(struct nvkm_gr *gr) +{ + if (gr->func->tlb_flush) + return gr->func->tlb_flush(gr); + return -ENODEV; +} + static int nvkm_gr_oclass_get(struct nvkm_oclass *oclass, int index) { @@ -59,26 +83,54 @@ nvkm_gr_cclass_new(struct nvkm_fifo_chan *chan, return 0; } -struct nvkm_engine_func +static void +nvkm_gr_intr(struct nvkm_engine *engine) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + gr->func->intr(gr); +} + +static int +nvkm_gr_oneinit(struct nvkm_engine *engine) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + if (gr->func->oneinit) + return gr->func->oneinit(gr); + return 0; +} + +static int +nvkm_gr_init(struct nvkm_engine *engine) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + return gr->func->init(gr); +} + +static void * +nvkm_gr_dtor(struct nvkm_engine *engine) +{ + struct nvkm_gr *gr = nvkm_gr(engine); + if (gr->func->dtor) + return gr->func->dtor(gr); + return gr; +} + +static const struct nvkm_engine_func nvkm_gr = { + .dtor = nvkm_gr_dtor, + .oneinit = nvkm_gr_oneinit, + .init = nvkm_gr_init, + .intr = nvkm_gr_intr, + .tile = nvkm_gr_tile, .fifo.cclass = nvkm_gr_cclass_new, .fifo.sclass = nvkm_gr_oclass_get, }; int -nvkm_gr_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, bool enable, - int length, void **pobject) +nvkm_gr_ctor(const struct nvkm_gr_func *func, struct nvkm_device *device, + int index, u32 pmc_enable, bool enable, struct nvkm_gr *gr) { - struct nvkm_gr *gr; - int ret; - - ret = nvkm_engine_create_(parent, engine, oclass, enable, - "gr", "gr", length, pobject); - gr = *pobject; - if (ret) - return ret; - - gr->engine.func = &nvkm_gr; - return 0; + gr->func = func; + return nvkm_engine_ctor(&nvkm_gr, device, index, pmc_enable, + enable, &gr->engine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c index 43d9ce227668..ddaa16a71c84 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c @@ -19,9 +19,8 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - #include "ctxgf100.h" -#include "gk20a.h" +#include "gf100.h" #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c new file mode 100644 index 000000000000..ce913300539f --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.c @@ -0,0 +1,196 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv50.h" + +#include + +static const struct nvkm_bitfield nv50_gr_status[] = { + { 0x00000001, "BUSY" }, /* set when any bit is set */ + { 0x00000002, "DISPATCH" }, + { 0x00000004, "UNK2" }, + { 0x00000008, "UNK3" }, + { 0x00000010, "UNK4" }, + { 0x00000020, "UNK5" }, + { 0x00000040, "M2MF" }, + { 0x00000080, "UNK7" }, + { 0x00000100, "CTXPROG" }, + { 0x00000200, "VFETCH" }, + { 0x00000400, "CCACHE_PREGEOM" }, + { 0x00000800, "STRMOUT_VATTR_POSTGEOM" }, + { 0x00001000, "VCLIP" }, + { 0x00002000, "RATTR_APLANE" }, + { 0x00004000, "TRAST" }, + { 0x00008000, "CLIPID" }, + { 0x00010000, "ZCULL" }, + { 0x00020000, "ENG2D" }, + { 0x00040000, "RMASK" }, + { 0x00080000, "TPC_RAST" }, + { 0x00100000, "TPC_PROP" }, + { 0x00200000, "TPC_TEX" }, + { 0x00400000, "TPC_GEOM" }, + { 0x00800000, "TPC_MP" }, + { 0x01000000, "ROP" }, + {} +}; + +static const struct nvkm_bitfield +nv50_gr_vstatus_0[] = { + { 0x01, "VFETCH" }, + { 0x02, "CCACHE" }, + { 0x04, "PREGEOM" }, + { 0x08, "POSTGEOM" }, + { 0x10, "VATTR" }, + { 0x20, "STRMOUT" }, + { 0x40, "VCLIP" }, + {} +}; + +static const struct nvkm_bitfield +nv50_gr_vstatus_1[] = { + { 0x01, "TPC_RAST" }, + { 0x02, "TPC_PROP" }, + { 0x04, "TPC_TEX" }, + { 0x08, "TPC_GEOM" }, + { 0x10, "TPC_MP" }, + {} +}; + +static const struct nvkm_bitfield +nv50_gr_vstatus_2[] = { + { 0x01, "RATTR" }, + { 0x02, "APLANE" }, + { 0x04, "TRAST" }, + { 0x08, "CLIPID" }, + { 0x10, "ZCULL" }, + { 0x20, "ENG2D" }, + { 0x40, "RMASK" }, + { 0x80, "ROP" }, + {} +}; + +static void +nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, + const struct nvkm_bitfield *units, u32 status) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + u32 stat = status; + u8 mask = 0x00; + char msg[64]; + int i; + + for (i = 0; units[i].name && status; i++) { + if ((status & 7) == 1) + mask |= (1 << i); + status >>= 3; + } + + nvkm_snprintbf(msg, sizeof(msg), units, mask); + nvkm_error(subdev, "PGRAPH_VSTATUS%d: %08x [%s]\n", r, stat, msg); +} + +int +g84_gr_tlb_flush(struct nvkm_gr *base) +{ + struct nv50_gr *gr = nv50_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + struct nvkm_timer *tmr = device->timer; + bool idle, timeout = false; + unsigned long flags; + char status[128]; + u64 start; + u32 tmp; + + spin_lock_irqsave(&gr->lock, flags); + nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); + + start = nvkm_timer_read(tmr); + do { + idle = true; + + for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { + if ((tmp & 7) == 1) + idle = false; + } + + for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { + if ((tmp & 7) == 1) + idle = false; + } + + for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { + if ((tmp & 7) == 1) + idle = false; + } + } while (!idle && + !(timeout = nvkm_timer_read(tmr) - start > 2000000000)); + + if (timeout) { + nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n"); + + tmp = nvkm_rd32(device, 0x400700); + nvkm_snprintbf(status, sizeof(status), nv50_gr_status, tmp); + nvkm_error(subdev, "PGRAPH_STATUS %08x [%s]\n", tmp, status); + + nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, + nvkm_rd32(device, 0x400380)); + nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1, + nvkm_rd32(device, 0x400384)); + nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2, + nvkm_rd32(device, 0x400388)); + } + + + nvkm_wr32(device, 0x100c80, 0x00000001); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) + break; + ); + nvkm_mask(device, 0x400500, 0x00000001, 0x00000001); + spin_unlock_irqrestore(&gr->lock, flags); + return timeout ? -EBUSY : 0; +} + +static const struct nvkm_gr_func +g84_gr = { + .init = nv50_gr_init, + .intr = nv50_gr_intr, + .chan_new = nv50_gr_chan_new, + .tlb_flush = g84_gr_tlb_flush, + .units = nv50_gr_units, + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8297, &nv50_gr_object }, + {} + } +}; + +int +g84_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv50_gr_new_(&g84_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 8fd26fa03c2e..1ad6785683f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -813,9 +814,9 @@ gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p) } u64 -gf100_gr_units(struct nvkm_gr *obj) +gf100_gr_units(struct nvkm_gr *base) { - struct gf100_gr *gr = container_of(obj, typeof(*gr), base); + struct gf100_gr *gr = gf100_gr(base); u64 cfg; cfg = (u32)gr->gpc_nr; @@ -1173,10 +1174,11 @@ gf100_gr_ctxctl_isr(struct gf100_gr *gr) } static void -gf100_gr_intr(struct nvkm_subdev *subdev) +gf100_gr_intr(struct nvkm_gr *base) { - struct gf100_gr *gr = (void *)subdev; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct gf100_gr *gr = gf100_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; struct nvkm_fifo_chan *chan; unsigned long flags; u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff; @@ -1196,7 +1198,7 @@ gf100_gr_intr(struct nvkm_subdev *subdev) chid = chan->chid; } - if (nv_device(gr)->card_type < NV_E0 || subc < 4) + if (device->card_type < NV_E0 || subc < 4) class = nvkm_rd32(device, 0x404200 + (subc * 4)); else class = 0x0000; @@ -1334,16 +1336,13 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) const struct gf100_grctx_func *grctx = gr->func->grctx; struct nvkm_subdev *subdev = &gr->base.engine.subdev; struct nvkm_device *device = subdev->device; - struct gf100_gr_oclass *oclass = (void *)nv_object(gr)->oclass; int i; if (gr->firmware) { /* load fuc microcode */ nvkm_mc_unk260(device->mc, 0); - gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, - &gr->fuc409d); - gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, - &gr->fuc41ad); + gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); + gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); nvkm_mc_unk260(device->mc, 1); /* start both of them running */ @@ -1389,7 +1388,7 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) ) < 0) return -EBUSY; - if (nv_device(gr)->chipset >= 0xe0) { + if (device->chipset >= 0xe0) { nvkm_wr32(device, 0x409800, 0x00000000); nvkm_wr32(device, 0x409500, 0x00000001); nvkm_wr32(device, 0x409504, 0x00000030); @@ -1434,33 +1433,33 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) return 0; } else - if (!oclass->fecs.ucode) { + if (!gr->func->fecs.ucode) { return -ENOSYS; } /* load HUB microcode */ nvkm_mc_unk260(device->mc, 0); nvkm_wr32(device, 0x4091c0, 0x01000000); - for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) - nvkm_wr32(device, 0x4091c4, oclass->fecs.ucode->data.data[i]); + for (i = 0; i < gr->func->fecs.ucode->data.size / 4; i++) + nvkm_wr32(device, 0x4091c4, gr->func->fecs.ucode->data.data[i]); nvkm_wr32(device, 0x409180, 0x01000000); - for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { + for (i = 0; i < gr->func->fecs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) nvkm_wr32(device, 0x409188, i >> 6); - nvkm_wr32(device, 0x409184, oclass->fecs.ucode->code.data[i]); + nvkm_wr32(device, 0x409184, gr->func->fecs.ucode->code.data[i]); } /* load GPC microcode */ nvkm_wr32(device, 0x41a1c0, 0x01000000); - for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) - nvkm_wr32(device, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); + for (i = 0; i < gr->func->gpccs.ucode->data.size / 4; i++) + nvkm_wr32(device, 0x41a1c4, gr->func->gpccs.ucode->data.data[i]); nvkm_wr32(device, 0x41a180, 0x01000000); - for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { + for (i = 0; i < gr->func->gpccs.ucode->code.size / 4; i++) { if ((i & 0x3f) == 0) nvkm_wr32(device, 0x41a188, i >> 6); - nvkm_wr32(device, 0x41a184, oclass->gpccs.ucode->code.data[i]); + nvkm_wr32(device, 0x41a184, gr->func->gpccs.ucode->code.data[i]); } nvkm_mc_unk260(device->mc, 1); @@ -1493,21 +1492,216 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) return 0; } +static int +gf100_gr_oneinit(struct nvkm_gr *base) +{ + struct gf100_gr *gr = gf100_gr(base); + struct nvkm_device *device = gr->base.engine.subdev.device; + int ret, i, j; + + nvkm_pmu_pgob(device->pmu, false); + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, + &gr->unk4188b4); + if (ret) + return ret; + + ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, + &gr->unk4188b8); + if (ret) + return ret; + + nvkm_kmap(gr->unk4188b4); + for (i = 0; i < 0x1000; i += 4) + nvkm_wo32(gr->unk4188b4, i, 0x00000010); + nvkm_done(gr->unk4188b4); + + nvkm_kmap(gr->unk4188b8); + for (i = 0; i < 0x1000; i += 4) + nvkm_wo32(gr->unk4188b8, i, 0x00000010); + nvkm_done(gr->unk4188b8); + + gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; + gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; + for (i = 0; i < gr->gpc_nr; i++) { + gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); + gr->tpc_total += gr->tpc_nr[i]; + gr->ppc_nr[i] = gr->func->ppc_nr; + for (j = 0; j < gr->ppc_nr[i]; j++) { + u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); + gr->ppc_tpc_nr[i][j] = hweight8(mask); + } + } + + /*XXX: these need figuring out... though it might not even matter */ + switch (device->chipset) { + case 0xc0: + if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ + gr->magic_not_rop_nr = 0x07; + } else + if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ + gr->magic_not_rop_nr = 0x05; + } else + if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ + gr->magic_not_rop_nr = 0x06; + } + break; + case 0xc3: /* 450, 4/0/0/0, 2 */ + gr->magic_not_rop_nr = 0x03; + break; + case 0xc4: /* 460, 3/4/0/0, 4 */ + gr->magic_not_rop_nr = 0x01; + break; + case 0xc1: /* 2/0/0/0, 1 */ + gr->magic_not_rop_nr = 0x01; + break; + case 0xc8: /* 4/4/3/4, 5 */ + gr->magic_not_rop_nr = 0x06; + break; + case 0xce: /* 4/4/0/0, 4 */ + gr->magic_not_rop_nr = 0x03; + break; + case 0xcf: /* 4/0/0/0, 3 */ + gr->magic_not_rop_nr = 0x03; + break; + case 0xd7: + case 0xd9: /* 1/0/0/0, 1 */ + case 0xea: /* gk20a */ + case 0x12b: /* gm20b */ + gr->magic_not_rop_nr = 0x01; + break; + } + + return 0; +} + +int +gf100_gr_init_(struct nvkm_gr *base) +{ + struct gf100_gr *gr = gf100_gr(base); + nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false); + return gr->func->init(gr); +} + +void +gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) +{ + kfree(fuc->data); + fuc->data = NULL; +} + +void * +gf100_gr_dtor(struct nvkm_gr *base) +{ + struct gf100_gr *gr = gf100_gr(base); + + if (gr->func->dtor) + gr->func->dtor(gr); + kfree(gr->data); + + gf100_gr_dtor_fw(&gr->fuc409c); + gf100_gr_dtor_fw(&gr->fuc409d); + gf100_gr_dtor_fw(&gr->fuc41ac); + gf100_gr_dtor_fw(&gr->fuc41ad); + + nvkm_memory_del(&gr->unk4188b8); + nvkm_memory_del(&gr->unk4188b4); + return gr; +} + +static const struct nvkm_gr_func +gf100_gr_ = { + .dtor = gf100_gr_dtor, + .oneinit = gf100_gr_oneinit, + .init = gf100_gr_init_, + .intr = gf100_gr_intr, + .units = gf100_gr_units, + .chan_new = gf100_gr_chan_new, + .object_get = gf100_gr_object_get, +}; + +int +gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, + struct gf100_gr_fuc *fuc) +{ + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; + const struct firmware *fw; + char f[64]; + char cname[16]; + int ret; + int i; + + /* Convert device name to lowercase */ + strncpy(cname, device->chip->name, sizeof(cname)); + cname[sizeof(cname) - 1] = '\0'; + i = strlen(cname); + while (i) { + --i; + cname[i] = tolower(cname[i]); + } + + snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); + ret = request_firmware(&fw, f, nv_device_base(device)); + if (ret) { + nvkm_error(subdev, "failed to load %s\n", fwname); + return ret; + } + + fuc->size = fw->size; + fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); + release_firmware(fw); + return (fuc->data != NULL) ? 0 : -ENOMEM; +} + +int +gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, + int index, struct gf100_gr *gr) +{ + int ret; + + gr->func = func; + gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW", + func->fecs.ucode == NULL); + + ret = nvkm_gr_ctor(&gf100_gr_, device, index, 0x08001000, + gr->firmware || func->fecs.ucode != NULL, + &gr->base); + if (ret) + return ret; + + if (gr->firmware) { + nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); + if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || + gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || + gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || + gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) + return -ENODEV; + } + + return 0; +} + int -gf100_gr_init(struct nvkm_object *object) +gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, + int index, struct nvkm_gr **pgr) +{ + struct gf100_gr *gr; + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; + *pgr = &gr->base; + return gf100_gr_ctor(func, device, index, gr); +} + +int +gf100_gr_init(struct gf100_gr *gr) { - struct gf100_gr *gr = (void *)object; struct nvkm_device *device = gr->base.engine.subdev.device; - struct gf100_gr_oclass *oclass = (void *)object->oclass; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; - int ret, i; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; + int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); @@ -1518,7 +1712,7 @@ gf100_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); - gf100_gr_mmio(gr, oclass->mmio); + gf100_gr_mmio(gr, gr->func->mmio); memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr)); for (i = 0, gpc = -1; i < gr->tpc_total; i++) { @@ -1543,7 +1737,7 @@ gf100_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); } - if (nv_device(gr)->chipset != 0xd7) + if (device->chipset != 0xd7) nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918); else nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918); @@ -1606,182 +1800,6 @@ gf100_gr_init(struct nvkm_object *object) return gf100_gr_init_ctxctl(gr); } -void -gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc) -{ - kfree(fuc->data); - fuc->data = NULL; -} - -int -gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, - struct gf100_gr_fuc *fuc) -{ - struct nvkm_subdev *subdev = &gr->base.engine.subdev; - struct nvkm_device *device = subdev->device; - const struct firmware *fw; - char f[64]; - char cname[16]; - int ret; - int i; - - /* Convert device name to lowercase */ - strncpy(cname, device->chip->name, sizeof(cname)); - cname[sizeof(cname) - 1] = '\0'; - i = strlen(cname); - while (i) { - --i; - cname[i] = tolower(cname[i]); - } - - snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); - ret = request_firmware(&fw, f, nv_device_base(device)); - if (ret) { - nvkm_error(subdev, "failed to load %s\n", fwname); - return ret; - } - - fuc->size = fw->size; - fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); - release_firmware(fw); - return (fuc->data != NULL) ? 0 : -ENOMEM; -} - -void -gf100_gr_dtor(struct nvkm_object *object) -{ - struct gf100_gr *gr = (void *)object; - - kfree(gr->data); - - gf100_gr_dtor_fw(&gr->fuc409c); - gf100_gr_dtor_fw(&gr->fuc409d); - gf100_gr_dtor_fw(&gr->fuc41ac); - gf100_gr_dtor_fw(&gr->fuc41ad); - - nvkm_memory_del(&gr->unk4188b8); - nvkm_memory_del(&gr->unk4188b4); - - nvkm_gr_destroy(&gr->base); -} - -static const struct nvkm_gr_func -gf100_gr_ = { - .chan_new = gf100_gr_chan_new, - .object_get = gf100_gr_object_get, -}; - -int -gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *bclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct gf100_gr_oclass *oclass = (void *)bclass; - struct nvkm_device *device = (void *)parent; - struct gf100_gr *gr; - bool use_ext_fw, enable; - int ret, i, j; - - use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW", - oclass->fecs.ucode == NULL); - enable = use_ext_fw || oclass->fecs.ucode != NULL; - - ret = nvkm_gr_create(parent, engine, bclass, enable, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->func = oclass->func; - gr->base.func = &gf100_gr_; - nv_subdev(gr)->unit = 0x08001000; - nv_subdev(gr)->intr = gf100_gr_intr; - - gr->base.units = gf100_gr_units; - - if (use_ext_fw) { - nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); - if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || - gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || - gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || - gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) - return -ENODEV; - gr->firmware = true; - } - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, - &gr->unk4188b4); - if (ret) - return ret; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 256, false, - &gr->unk4188b8); - if (ret) - return ret; - - nvkm_kmap(gr->unk4188b4); - for (i = 0; i < 0x1000; i += 4) - nvkm_wo32(gr->unk4188b4, i, 0x00000010); - nvkm_done(gr->unk4188b4); - - nvkm_kmap(gr->unk4188b8); - for (i = 0; i < 0x1000; i += 4) - nvkm_wo32(gr->unk4188b8, i, 0x00000010); - nvkm_done(gr->unk4188b8); - - gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16; - gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f; - for (i = 0; i < gr->gpc_nr; i++) { - gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608)); - gr->tpc_total += gr->tpc_nr[i]; - gr->ppc_nr[i] = oclass->ppc_nr; - for (j = 0; j < gr->ppc_nr[i]; j++) { - u8 mask = nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4))); - gr->ppc_tpc_nr[i][j] = hweight8(mask); - } - } - - /*XXX: these need figuring out... though it might not even matter */ - switch (nv_device(gr)->chipset) { - case 0xc0: - if (gr->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ - gr->magic_not_rop_nr = 0x07; - } else - if (gr->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ - gr->magic_not_rop_nr = 0x05; - } else - if (gr->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ - gr->magic_not_rop_nr = 0x06; - } - break; - case 0xc3: /* 450, 4/0/0/0, 2 */ - gr->magic_not_rop_nr = 0x03; - break; - case 0xc4: /* 460, 3/4/0/0, 4 */ - gr->magic_not_rop_nr = 0x01; - break; - case 0xc1: /* 2/0/0/0, 1 */ - gr->magic_not_rop_nr = 0x01; - break; - case 0xc8: /* 4/4/3/4, 5 */ - gr->magic_not_rop_nr = 0x06; - break; - case 0xce: /* 4/4/0/0, 4 */ - gr->magic_not_rop_nr = 0x03; - break; - case 0xcf: /* 4/0/0/0, 3 */ - gr->magic_not_rop_nr = 0x03; - break; - case 0xd7: - case 0xd9: /* 1/0/0/0, 1 */ - case 0xea: /* gk20a */ - case 0x12b: /* gm20b */ - gr->magic_not_rop_nr = 0x01; - break; - } - - return 0; -} - #include "fuc/hubgf100.fuc3.h" struct gf100_gr_ucode @@ -1804,6 +1822,10 @@ gf100_gr_gpccs_ucode = { static const struct gf100_gr_func gf100_gr = { + .init = gf100_gr_init, + .mmio = gf100_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, .grctx = &gf100_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -1814,17 +1836,8 @@ gf100_gr = { } }; -struct nvkm_oclass * -gf100_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xc0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gf100_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gf100_gr, - .mmio = gf100_gr_pack_mmio, - .fecs.ucode = &gf100_gr_fecs_ucode, - .gpccs.ucode = &gf100_gr_gpccs_ucode, -}.base; +int +gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gf100_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h index 43e9897ac883..4611961b1187 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h @@ -21,8 +21,8 @@ * * Authors: Ben Skeggs */ -#ifndef __NVC0_GR_H__ -#define __NVC0_GR_H__ +#ifndef __GF100_GR_H__ +#define __GF100_GR_H__ #define gf100_gr(p) container_of((p), struct gf100_gr, base) #include "priv.h" @@ -71,8 +71,8 @@ struct gf100_gr_zbc_depth { }; struct gf100_gr { - struct nvkm_gr base; const struct gf100_gr_func *func; + struct nvkm_gr base; struct gf100_gr_fuc fuc409c; struct gf100_gr_fuc fuc409d; @@ -110,11 +110,40 @@ struct gf100_gr { u8 magic_not_rop_nr; }; +int gf100_gr_ctor(const struct gf100_gr_func *, struct nvkm_device *, + int, struct gf100_gr *); +int gf100_gr_new_(const struct gf100_gr_func *, struct nvkm_device *, + int, struct nvkm_gr **); +void *gf100_gr_dtor(struct nvkm_gr *); + struct gf100_gr_func { + void (*dtor)(struct gf100_gr *); + int (*init)(struct gf100_gr *); + void (*init_gpc_mmu)(struct gf100_gr *); + void (*set_hww_esr_report_mask)(struct gf100_gr *); + const struct gf100_gr_pack *mmio; + struct { + struct gf100_gr_ucode *ucode; + } fecs; + struct { + struct gf100_gr_ucode *ucode; + } gpccs; + int ppc_nr; const struct gf100_grctx_func *grctx; struct nvkm_sclass sclass[]; }; +int gf100_gr_init(struct gf100_gr *); + +int gk104_gr_init(struct gf100_gr *); + +int gk20a_gr_new_(const struct gf100_gr_func *, struct nvkm_device *, + int, struct nvkm_gr **); +void gk20a_gr_dtor(struct gf100_gr *); +int gk20a_gr_init(struct gf100_gr *); + +int gm204_gr_init(struct gf100_gr *); + #define gf100_gr_chan(p) container_of((p), struct gf100_gr_chan, object) struct gf100_gr_chan { @@ -137,33 +166,10 @@ void gf100_gr_dtor_fw(struct gf100_gr_fuc *); int gf100_gr_ctor_fw(struct gf100_gr *, const char *, struct gf100_gr_fuc *); u64 gf100_gr_units(struct nvkm_gr *); -int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *data, u32 size, - struct nvkm_object **); -void gf100_gr_dtor(struct nvkm_object *); -int gf100_gr_init(struct nvkm_object *); void gf100_gr_zbc_init(struct gf100_gr *); -int gk104_gr_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *data, u32 size, - struct nvkm_object **); -int gk104_gr_init(struct nvkm_object *); - -int gk20a_gr_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *data, u32 size, - struct nvkm_object **); -void gk20a_gr_dtor(struct nvkm_object *); -int gk20a_gr_init(struct nvkm_object *); - -int gm204_gr_init(struct nvkm_object *); - extern const struct nvkm_object_func gf100_fermi; -extern struct nvkm_oclass gf100_gr_sclass[]; -extern struct nvkm_oclass gf110_gr_sclass[]; -extern struct nvkm_oclass gk110_gr_sclass[]; -extern struct nvkm_oclass gm204_gr_sclass[]; - struct gf100_gr_init { u32 addr; u8 count; @@ -191,19 +197,6 @@ extern struct gf100_gr_ucode gf100_gr_gpccs_ucode; extern struct gf100_gr_ucode gk110_gr_fecs_ucode; extern struct gf100_gr_ucode gk110_gr_gpccs_ucode; -struct gf100_gr_oclass { - struct nvkm_oclass base; - const struct gf100_gr_func *func; - const struct gf100_gr_pack *mmio; - struct { - struct gf100_gr_ucode *ucode; - } fecs; - struct { - struct gf100_gr_ucode *ucode; - } gpccs; - int ppc_nr; -}; - int gf100_gr_wait_idle(struct gf100_gr *); void gf100_gr_mmio(struct gf100_gr *, const struct gf100_gr_pack *); void gf100_gr_icmd(struct gf100_gr *, const struct gf100_gr_pack *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c index aa529b5c0daa..8f253e0a22f4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c @@ -114,6 +114,10 @@ gf104_gr_pack_mmio[] = { static const struct gf100_gr_func gf104_gr = { + .init = gf100_gr_init, + .mmio = gf104_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, .grctx = &gf104_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -124,17 +128,8 @@ gf104_gr = { } }; -struct nvkm_oclass * -gf104_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xc3), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gf100_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gf104_gr, - .mmio = gf104_gr_pack_mmio, - .fecs.ucode = &gf100_gr_fecs_ucode, - .gpccs.ucode = &gf100_gr_gpccs_ucode, -}.base; +int +gf104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gf104_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c index 971c897d59be..815a5aafa245 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c @@ -105,6 +105,10 @@ gf108_gr_pack_mmio[] = { static const struct gf100_gr_func gf108_gr = { + .init = gf100_gr_init, + .mmio = gf108_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, .grctx = &gf108_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -116,17 +120,8 @@ gf108_gr = { } }; -struct nvkm_oclass * -gf108_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xc1), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gf100_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gf108_gr, - .mmio = gf108_gr_pack_mmio, - .fecs.ucode = &gf100_gr_fecs_ucode, - .gpccs.ucode = &gf100_gr_gpccs_ucode, -}.base; +int +gf108_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gf108_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index f832a8bd454c..d13187409d68 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -86,6 +86,10 @@ gf110_gr_pack_mmio[] = { static const struct gf100_gr_func gf110_gr = { + .init = gf100_gr_init, + .mmio = gf110_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, .grctx = &gf110_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -98,17 +102,8 @@ gf110_gr = { } }; -struct nvkm_oclass * -gf110_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xc8), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gf100_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gf110_gr, - .mmio = gf110_gr_pack_mmio, - .fecs.ucode = &gf100_gr_fecs_ucode, - .gpccs.ucode = &gf100_gr_gpccs_ucode, -}.base; +int +gf110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gf110_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index 909b5a6fa8d2..28483d8bf3d2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -122,6 +122,11 @@ gf117_gr_gpccs_ucode = { static const struct gf100_gr_func gf117_gr = { + .init = gf100_gr_init, + .mmio = gf117_gr_pack_mmio, + .fecs.ucode = &gf117_gr_fecs_ucode, + .gpccs.ucode = &gf117_gr_gpccs_ucode, + .ppc_nr = 1, .grctx = &gf117_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -134,18 +139,8 @@ gf117_gr = { } }; -struct nvkm_oclass * -gf117_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xd7), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gf100_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gf117_gr, - .mmio = gf117_gr_pack_mmio, - .fecs.ucode = &gf117_gr_fecs_ucode, - .gpccs.ucode = &gf117_gr_gpccs_ucode, - .ppc_nr = 1, -}.base; +int +gf117_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gf117_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index 01c2dcc4e873..9811a72e0313 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -177,6 +177,10 @@ gf119_gr_pack_mmio[] = { static const struct gf100_gr_func gf119_gr = { + .init = gf100_gr_init, + .mmio = gf119_gr_pack_mmio, + .fecs.ucode = &gf100_gr_fecs_ucode, + .gpccs.ucode = &gf100_gr_gpccs_ucode, .grctx = &gf119_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -189,17 +193,8 @@ gf119_gr = { } }; -struct nvkm_oclass * -gf119_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xd9), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gf100_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gf119_gr, - .mmio = gf119_gr_pack_mmio, - .fecs.ucode = &gf100_gr_fecs_ucode, - .gpccs.ucode = &gf100_gr_gpccs_ucode, -}.base; +int +gf119_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gf119_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c index efd5ebd1fa04..abf54928a1a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c @@ -24,8 +24,6 @@ #include "gf100.h" #include "ctxgf100.h" -#include - #include /******************************************************************************* @@ -180,22 +178,14 @@ gk104_gr_pack_mmio[] = { ******************************************************************************/ int -gk104_gr_init(struct nvkm_object *object) +gk104_gr_init(struct gf100_gr *gr) { - struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr *gr = (void *)object; struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, rop; - int ret, i; - - nvkm_pmu_pgob(device->pmu, false); - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; + int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); @@ -206,7 +196,7 @@ gk104_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); - gf100_gr_mmio(gr, oclass->mmio); + gf100_gr_mmio(gr, gr->func->mmio); nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); @@ -296,28 +286,6 @@ gk104_gr_init(struct nvkm_object *object) return gf100_gr_init_ctxctl(gr); } -static const struct gf100_gr_func -gk104_gr = { - .grctx = &gk104_grctx, - .sclass = { - { -1, -1, FERMI_TWOD_A }, - { -1, -1, KEPLER_INLINE_TO_MEMORY_A }, - { -1, -1, KEPLER_A, &gf100_fermi }, - { -1, -1, KEPLER_COMPUTE_A }, - {} - } -}; - -int -gk104_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = (void *)parent; - nvkm_pmu_pgob(device->pmu, false); - return gf100_gr_ctor(parent, engine, oclass, data, size, pobject); -} - #include "fuc/hubgk104.fuc3.h" static struct gf100_gr_ucode @@ -338,18 +306,25 @@ gk104_gr_gpccs_ucode = { .data.size = sizeof(gk104_grgpc_data), }; -struct nvkm_oclass * -gk104_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xe4), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gk104_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gk104_gr, +static const struct gf100_gr_func +gk104_gr = { + .init = gk104_gr_init, .mmio = gk104_gr_pack_mmio, .fecs.ucode = &gk104_gr_fecs_ucode, .gpccs.ucode = &gk104_gr_gpccs_ucode, .ppc_nr = 1, -}.base; + .grctx = &gk104_grctx, + .sclass = { + { -1, -1, FERMI_TWOD_A }, + { -1, -1, KEPLER_INLINE_TO_MEMORY_A }, + { -1, -1, KEPLER_A, &gf100_fermi }, + { -1, -1, KEPLER_COMPUTE_A }, + {} + } +}; + +int +gk104_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gk104_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index fb513ea8bbd2..32aa2946e7b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -182,6 +182,11 @@ gk110_gr_gpccs_ucode = { static const struct gf100_gr_func gk110_gr = { + .init = gk104_gr_init, + .mmio = gk110_gr_pack_mmio, + .fecs.ucode = &gk110_gr_fecs_ucode, + .gpccs.ucode = &gk110_gr_gpccs_ucode, + .ppc_nr = 2, .grctx = &gk110_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -192,18 +197,8 @@ gk110_gr = { } }; -struct nvkm_oclass * -gk110_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xf0), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gk104_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gk110_gr, - .mmio = gk110_gr_pack_mmio, - .fecs.ucode = &gk110_gr_fecs_ucode, - .gpccs.ucode = &gk110_gr_gpccs_ucode, - .ppc_nr = 2, -}.base; +int +gk110_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gk110_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c index b3da907b2b70..22f88afbf35f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c @@ -102,6 +102,11 @@ gk110b_gr_pack_mmio[] = { static const struct gf100_gr_func gk110b_gr = { + .init = gk104_gr_init, + .mmio = gk110b_gr_pack_mmio, + .fecs.ucode = &gk110_gr_fecs_ucode, + .gpccs.ucode = &gk110_gr_gpccs_ucode, + .ppc_nr = 2, .grctx = &gk110b_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -112,18 +117,8 @@ gk110b_gr = { } }; -struct nvkm_oclass * -gk110b_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0xf1), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gk104_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gk110b_gr, - .mmio = gk110b_gr_pack_mmio, - .fecs.ucode = &gk110_gr_fecs_ucode, - .gpccs.ucode = &gk110_gr_gpccs_ucode, - .ppc_nr = 2, -}.base; +int +gk110b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gk110b_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c index 243b0a3f67c2..ee7554fc87dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c @@ -161,6 +161,11 @@ gk208_gr_gpccs_ucode = { static const struct gf100_gr_func gk208_gr = { + .init = gk104_gr_init, + .mmio = gk208_gr_pack_mmio, + .fecs.ucode = &gk208_gr_fecs_ucode, + .gpccs.ucode = &gk208_gr_gpccs_ucode, + .ppc_nr = 1, .grctx = &gk208_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -171,18 +176,8 @@ gk208_gr = { } }; -struct nvkm_oclass * -gk208_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0x08), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk104_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gk104_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gk208_gr, - .mmio = gk208_gr_pack_mmio, - .fecs.ucode = &gk208_gr_fecs_ucode, - .gpccs.ucode = &gk208_gr_gpccs_ucode, - .ppc_nr = 1, -}.base; +int +gk208_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gk208_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index a8100c4f5785..b8758d3b8b51 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -19,7 +19,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include "gk20a.h" +#include "gf100.h" #include "ctxgf100.h" #include @@ -146,69 +146,6 @@ gk20a_gr_av_to_method(struct gf100_gr_fuc *fuc) return pack; } -int -gk20a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - int err; - struct gf100_gr *gr; - struct gf100_gr_fuc fuc; - - err = gf100_gr_ctor(parent, engine, oclass, data, size, pobject); - if (err) - return err; - - gr = (void *)*pobject; - - err = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc); - if (err) - return err; - gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc); - gf100_gr_dtor_fw(&fuc); - if (IS_ERR(gr->fuc_sw_nonctx)) - return PTR_ERR(gr->fuc_sw_nonctx); - - err = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc); - if (err) - return err; - gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc); - gf100_gr_dtor_fw(&fuc); - if (IS_ERR(gr->fuc_sw_ctx)) - return PTR_ERR(gr->fuc_sw_ctx); - - err = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc); - if (err) - return err; - gr->fuc_bundle = gk20a_gr_av_to_init(&fuc); - gf100_gr_dtor_fw(&fuc); - if (IS_ERR(gr->fuc_bundle)) - return PTR_ERR(gr->fuc_bundle); - - err = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc); - if (err) - return err; - gr->fuc_method = gk20a_gr_av_to_method(&fuc); - gf100_gr_dtor_fw(&fuc); - if (IS_ERR(gr->fuc_method)) - return PTR_ERR(gr->fuc_method); - - return 0; -} - -void -gk20a_gr_dtor(struct nvkm_object *object) -{ - struct gf100_gr *gr = (void *)object; - - gk20a_gr_init_dtor(gr->fuc_method); - gk20a_gr_init_dtor(gr->fuc_bundle); - gk20a_gr_init_dtor(gr->fuc_sw_ctx); - gk20a_gr_init_dtor(gr->fuc_sw_nonctx); - - gf100_gr_dtor(object); -} - static int gk20a_gr_wait_mem_scrubbing(struct gf100_gr *gr) { @@ -243,10 +180,8 @@ gk20a_gr_set_hww_esr_report_mask(struct gf100_gr *gr) } int -gk20a_gr_init(struct nvkm_object *object) +gk20a_gr_init(struct gf100_gr *gr) { - struct gk20a_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr *gr = (void *)object; struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; @@ -254,10 +189,6 @@ gk20a_gr_init(struct nvkm_object *object) int gpc, tpc; int ret, i; - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; - /* Clear SCC RAM */ nvkm_wr32(device, 0x40802c, 0x1); @@ -275,8 +206,8 @@ gk20a_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); - if (oclass->init_gpc_mmu) - oclass->init_gpc_mmu(gr); + if (gr->func->init_gpc_mmu) + gr->func->init_gpc_mmu(gr); /* Set the PE as stream master */ nvkm_mask(device, 0x503018, 0x1, 0x1); @@ -322,8 +253,8 @@ gk20a_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x404000, 0xc0000000); nvkm_wr32(device, 0x404600, 0xc0000000); - if (oclass->set_hww_esr_report_mask) - oclass->set_hww_esr_report_mask(gr); + if (gr->func->set_hww_esr_report_mask) + gr->func->set_hww_esr_report_mask(gr); /* Enable TPC exceptions per GPC */ nvkm_wr32(device, 0x419d0c, 0x2); @@ -342,8 +273,72 @@ gk20a_gr_init(struct nvkm_object *object) return gf100_gr_init_ctxctl(gr); } +void +gk20a_gr_dtor(struct gf100_gr *gr) +{ + gk20a_gr_init_dtor(gr->fuc_method); + gk20a_gr_init_dtor(gr->fuc_bundle); + gk20a_gr_init_dtor(gr->fuc_sw_ctx); + gk20a_gr_init_dtor(gr->fuc_sw_nonctx); +} + +int +gk20a_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device, + int index, struct nvkm_gr **pgr) +{ + struct gf100_gr_fuc fuc; + struct gf100_gr *gr; + int ret; + + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; + *pgr = &gr->base; + + ret = gf100_gr_ctor(func, device, index, gr); + if (ret) + return ret; + + ret = gf100_gr_ctor_fw(gr, "sw_nonctx", &fuc); + if (ret) + return ret; + gr->fuc_sw_nonctx = gk20a_gr_av_to_init(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(gr->fuc_sw_nonctx)) + return PTR_ERR(gr->fuc_sw_nonctx); + + ret = gf100_gr_ctor_fw(gr, "sw_ctx", &fuc); + if (ret) + return ret; + gr->fuc_sw_ctx = gk20a_gr_aiv_to_init(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(gr->fuc_sw_ctx)) + return PTR_ERR(gr->fuc_sw_ctx); + + ret = gf100_gr_ctor_fw(gr, "sw_bundle_init", &fuc); + if (ret) + return ret; + gr->fuc_bundle = gk20a_gr_av_to_init(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(gr->fuc_bundle)) + return PTR_ERR(gr->fuc_bundle); + + ret = gf100_gr_ctor_fw(gr, "sw_method_init", &fuc); + if (ret) + return ret; + gr->fuc_method = gk20a_gr_av_to_method(&fuc); + gf100_gr_dtor_fw(&fuc); + if (IS_ERR(gr->fuc_method)) + return PTR_ERR(gr->fuc_method); + + return 0; +} + static const struct gf100_gr_func gk20a_gr = { + .dtor = gk20a_gr_dtor, + .init = gk20a_gr_init, + .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, + .ppc_nr = 1, .grctx = &gk20a_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -354,18 +349,8 @@ gk20a_gr = { } }; -struct nvkm_oclass * -gk20a_gr_oclass = &(struct gk20a_gr_oclass) { - .gf100 = { - .base.handle = NV_ENGINE(GR, 0xea), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk20a_gr_ctor, - .dtor = gk20a_gr_dtor, - .init = gk20a_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gk20a_gr, - .ppc_nr = 1, - }, - .set_hww_esr_report_mask = gk20a_gr_set_hww_esr_report_mask, -}.gf100.base; +int +gk20a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gk20a_gr_new_(&gk20a_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h deleted file mode 100644 index 411099d222d4..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef __GK20A_GR_H__ -#define __GK20A_GR_H__ - -#include "gf100.h" - -struct gk20a_gr_oclass { - struct gf100_gr_oclass gf100; - - void (*init_gpc_mmu)(struct gf100_gr *); - void (*set_hww_esr_report_mask)(struct gf100_gr *); -}; - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c index b3036cb61080..56e960212e5d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c @@ -308,20 +308,14 @@ gm107_gr_init_bios(struct gf100_gr *gr) } int -gm107_gr_init(struct nvkm_object *object) +gm107_gr_init(struct gf100_gr *gr) { - struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr *gr = (void *)object; struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); u32 data[TPC_MAX / 8] = {}; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; - int ret, i; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; + int i; nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); @@ -329,7 +323,7 @@ gm107_gr_init(struct nvkm_object *object) nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); - gf100_gr_mmio(gr, oclass->mmio); + gf100_gr_mmio(gr, gr->func->mmio); gm107_gr_init_bios(gr); @@ -443,6 +437,11 @@ gm107_gr_gpccs_ucode = { static const struct gf100_gr_func gm107_gr = { + .init = gm107_gr_init, + .mmio = gm107_gr_pack_mmio, + .fecs.ucode = &gm107_gr_fecs_ucode, + .gpccs.ucode = &gm107_gr_gpccs_ucode, + .ppc_nr = 2, .grctx = &gm107_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -453,18 +452,8 @@ gm107_gr = { } }; -struct nvkm_oclass * -gm107_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0x07), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gm107_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gm107_gr, - .mmio = gm107_gr_pack_mmio, - .fecs.ucode = &gm107_gr_fecs_ucode, - .gpccs.ucode = &gm107_gr_gpccs_ucode, - .ppc_nr = 2, -}.base; +int +gm107_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gm107_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c index ff41232a8a53..90381dde451a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm204.c @@ -236,21 +236,14 @@ gm204_gr_init_ctxctl(struct gf100_gr *gr) } int -gm204_gr_init(struct nvkm_object *object) +gm204_gr_init(struct gf100_gr *gr) { - struct gf100_gr_oclass *oclass = (void *)object->oclass; - struct gf100_gr *gr = (void *)object; struct nvkm_device *device = gr->base.engine.subdev.device; const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total); - u32 data[TPC_MAX / 8] = {}; + u32 data[TPC_MAX / 8] = {}, tmp; u8 tpcnr[GPC_MAX]; int gpc, tpc, ppc, rop; - int ret, i; - u32 tmp; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; + int i; tmp = nvkm_rd32(device, 0x100c80); /*XXX: mask? */ nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff)); @@ -265,7 +258,7 @@ gm204_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); nvkm_mask(device, 0x100cc4, 0x00040000, 0x00040000); - gf100_gr_mmio(gr, oclass->mmio); + gf100_gr_mmio(gr, gr->func->mmio); gm107_gr_init_bios(gr); @@ -360,6 +353,9 @@ gm204_gr_init(struct nvkm_object *object) static const struct gf100_gr_func gm204_gr = { + .init = gm204_gr_init, + .mmio = gm204_gr_pack_mmio, + .ppc_nr = 2, .grctx = &gm204_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -370,16 +366,8 @@ gm204_gr = { } }; -struct nvkm_oclass * -gm204_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0x24), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gm204_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gm204_gr, - .mmio = gm204_gr_pack_mmio, - .ppc_nr = 2, -}.base; +int +gm204_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gm204_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c index 4350b08f8dd2..341dc560acbb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm206.c @@ -28,6 +28,9 @@ static const struct gf100_gr_func gm206_gr = { + .init = gm204_gr_init, + .mmio = gm204_gr_pack_mmio, + .ppc_nr = 2, .grctx = &gm206_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -38,16 +41,8 @@ gm206_gr = { } }; -struct nvkm_oclass * -gm206_gr_oclass = &(struct gf100_gr_oclass) { - .base.handle = NV_ENGINE(GR, 0x26), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gf100_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gm204_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gm206_gr, - .mmio = gm204_gr_pack_mmio, - .ppc_nr = 2, -}.base; +int +gm206_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(&gm206_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c index 7a663654543b..65b6e3d1e90d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -19,7 +19,7 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include "gk20a.h" +#include "gf100.h" #include "ctxgf100.h" #include @@ -61,6 +61,11 @@ gm20b_gr_set_hww_esr_report_mask(struct gf100_gr *gr) static const struct gf100_gr_func gm20b_gr = { + .dtor = gk20a_gr_dtor, + .init = gk20a_gr_init, + .init_gpc_mmu = gm20b_gr_init_gpc_mmu, + .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, + .ppc_nr = 1, .grctx = &gm20b_grctx, .sclass = { { -1, -1, FERMI_TWOD_A }, @@ -71,19 +76,8 @@ gm20b_gr = { } }; -struct nvkm_oclass * -gm20b_gr_oclass = &(struct gk20a_gr_oclass) { - .gf100 = { - .base.handle = NV_ENGINE(GR, 0x2b), - .base.ofuncs = &(struct nvkm_ofuncs) { - .ctor = gk20a_gr_ctor, - .dtor = gf100_gr_dtor, - .init = gk20a_gr_init, - .fini = _nvkm_gr_fini, - }, - .func = &gm20b_gr, - .ppc_nr = 1, - }, - .init_gpc_mmu = gm20b_gr_init_gpc_mmu, - .set_hww_esr_report_mask = gm20b_gr_set_hww_esr_report_mask, -}.gf100.base; +int +gm20b_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gk20a_gr_new_(&gm20b_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c new file mode 100644 index 000000000000..2e68919f00b2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.c @@ -0,0 +1,47 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv50.h" + +static const struct nvkm_gr_func +gt200_gr = { + .init = nv50_gr_init, + .intr = nv50_gr_intr, + .chan_new = nv50_gr_chan_new, + .tlb_flush = g84_gr_tlb_flush, + .units = nv50_gr_units, + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8397, &nv50_gr_object }, + {} + } +}; + +int +gt200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv50_gr_new_(>200_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c new file mode 100644 index 000000000000..2bf7aac360cc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.c @@ -0,0 +1,48 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv50.h" + +static const struct nvkm_gr_func +gt215_gr = { + .init = nv50_gr_init, + .intr = nv50_gr_intr, + .chan_new = nv50_gr_chan_new, + .tlb_flush = g84_gr_tlb_flush, + .units = nv50_gr_units, + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8597, &nv50_gr_object }, + { -1, -1, 0x85c0, &nv50_gr_object }, + {} + } +}; + +int +gt215_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv50_gr_new_(>215_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c new file mode 100644 index 000000000000..95d5219faf93 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.c @@ -0,0 +1,46 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv50.h" + +static const struct nvkm_gr_func +mcp79_gr = { + .init = nv50_gr_init, + .intr = nv50_gr_intr, + .chan_new = nv50_gr_chan_new, + .units = nv50_gr_units, + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x8397, &nv50_gr_object }, + {} + } +}; + +int +mcp79_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv50_gr_new_(&mcp79_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c new file mode 100644 index 000000000000..027b58e5976b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.c @@ -0,0 +1,48 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv50.h" + +static const struct nvkm_gr_func +mcp89_gr = { + .init = nv50_gr_init, + .intr = nv50_gr_intr, + .chan_new = nv50_gr_chan_new, + .tlb_flush = g84_gr_tlb_flush, + .units = nv50_gr_units, + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + { -1, -1, 0x85c0, &nv50_gr_object }, + { -1, -1, 0x8697, &nv50_gr_object }, + {} + } +}; + +int +mcp89_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv50_gr_new_(&mcp89_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index a5a4bdd9863e..7b4317ab8f02 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1269,11 +1269,11 @@ nv04_gr_nsource[] = { }; static void -nv04_gr_intr(struct nvkm_subdev *subdev) +nv04_gr_intr(struct nvkm_gr *base) { - struct nv04_gr *gr = (void *)subdev; - struct nv04_gr_chan *chan = NULL; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nv04_gr *gr = nv04_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); @@ -1286,6 +1286,7 @@ nv04_gr_intr(struct nvkm_subdev *subdev) u32 inst = (nvkm_rd32(device, 0x40016c) & 0xffff) << 4; u32 show = stat; char msg[128], src[128], sta[128]; + struct nv04_gr_chan *chan; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); @@ -1323,8 +1324,47 @@ nv04_gr_intr(struct nvkm_subdev *subdev) spin_unlock_irqrestore(&gr->lock, flags); } +static int +nv04_gr_init(struct nvkm_gr *base) +{ + struct nv04_gr *gr = nv04_gr(base); + struct nvkm_device *device = gr->base.engine.subdev.device; + + /* Enable PGRAPH interrupts */ + nvkm_wr32(device, NV03_PGRAPH_INTR, 0xFFFFFFFF); + nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); + + nvkm_wr32(device, NV04_PGRAPH_VALID1, 0); + nvkm_wr32(device, NV04_PGRAPH_VALID2, 0); + /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x000001FF); + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x1231c000); + /*1231C000 blob, 001 haiku*/ + /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x72111100); + /*0x72111100 blob , 01 haiku*/ + /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f071); + /*haiku same*/ + + /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ + nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); + /*haiku and blob 10d4*/ + + nvkm_wr32(device, NV04_PGRAPH_STATE , 0xFFFFFFFF); + nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL , 0x10000100); + nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); + + /* These don't belong here, they're part of a per-channel context */ + nvkm_wr32(device, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); + nvkm_wr32(device, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); + return 0; +} + static const struct nvkm_gr_func nv04_gr = { + .init = nv04_gr_init, + .intr = nv04_gr_intr, .chan_new = nv04_gr_chan_new, .sclass = { { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ @@ -1372,76 +1412,16 @@ nv04_gr = { } }; -static int -nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv04_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) { struct nv04_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - gr->base.func = &nv04_gr; - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv04_gr_intr; + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; spin_lock_init(&gr->lock); - return 0; -} + *pgr = &gr->base; -static int -nv04_gr_init(struct nvkm_object *object) -{ - struct nvkm_engine *engine = nv_engine(object); - struct nv04_gr *gr = (void *)engine; - struct nvkm_device *device = gr->base.engine.subdev.device; - int ret; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; - - /* Enable PGRAPH interrupts */ - nvkm_wr32(device, NV03_PGRAPH_INTR, 0xFFFFFFFF); - nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); - - nvkm_wr32(device, NV04_PGRAPH_VALID1, 0); - nvkm_wr32(device, NV04_PGRAPH_VALID2, 0); - /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x000001FF); - nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ - nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x1231c000); - /*1231C000 blob, 001 haiku*/ - /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ - nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x72111100); - /*0x72111100 blob , 01 haiku*/ - /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ - nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x11d5f071); - /*haiku same*/ - - /*nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ - nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); - /*haiku and blob 10d4*/ - - nvkm_wr32(device, NV04_PGRAPH_STATE , 0xFFFFFFFF); - nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL , 0x10000100); - nvkm_mask(device, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); - - /* These don't belong here, they're part of a per-channel context */ - nvkm_wr32(device, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); - nvkm_wr32(device, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); - return 0; + return nvkm_gr_ctor(&nv04_gr, device, index, 0x00001000, + true, &gr->base); } - -struct nvkm_oclass -nv04_gr_oclass = { - .handle = NV_ENGINE(GR, 0x04), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv04_gr_ctor, - .dtor = _nvkm_gr_dtor, - .init = nv04_gr_init, - .fini = _nvkm_gr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index d5e44a7332eb..9436ada62cba 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -21,7 +21,7 @@ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include "priv.h" +#include "nv10.h" #include "regs.h" #include @@ -890,8 +890,7 @@ nv10_gr_load_context(struct nv10_gr_chan *chan, int chid) for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) nvkm_wr32(device, nv10_gr_ctx_regs[i], chan->nv10[i]); - if (nv_device(gr)->card_type >= NV_11 && - nv_device(gr)->chipset >= 0x17) { + if (device->card_type >= NV_11 && device->chipset >= 0x17) { for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) nvkm_wr32(device, nv17_gr_ctx_regs[i], chan->nv17[i]); } @@ -917,8 +916,7 @@ nv10_gr_unload_context(struct nv10_gr_chan *chan) for (i = 0; i < ARRAY_SIZE(nv10_gr_ctx_regs); i++) chan->nv10[i] = nvkm_rd32(device, nv10_gr_ctx_regs[i]); - if (nv_device(gr)->card_type >= NV_11 && - nv_device(gr)->chipset >= 0x17) { + if (device->card_type >= NV_11 && device->chipset >= 0x17) { for (i = 0; i < ARRAY_SIZE(nv17_gr_ctx_regs); i++) chan->nv17[i] = nvkm_rd32(device, nv17_gr_ctx_regs[i]); } @@ -1000,7 +998,7 @@ nv10_gr_chan = { chan->nv17[offset] = val; \ } while (0) -static int +int nv10_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { @@ -1047,13 +1045,12 @@ nv10_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, * PGRAPH engine/subdev functions ******************************************************************************/ -static void -nv10_gr_tile_prog(struct nvkm_engine *engine, int i) +void +nv10_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) { - struct nv10_gr *gr = (void *)engine; + struct nv10_gr *gr = nv10_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_fifo *fifo = device->fifo; - struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; nvkm_fifo_pause(fifo, &flags); @@ -1080,12 +1077,12 @@ const struct nvkm_bitfield nv10_gr_nstatus[] = { {} }; -static void -nv10_gr_intr(struct nvkm_subdev *subdev) +void +nv10_gr_intr(struct nvkm_gr *base) { - struct nv10_gr *gr = (void *)subdev; - struct nv10_gr_chan *chan = NULL; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nv10_gr *gr = nv10_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); @@ -1097,6 +1094,7 @@ nv10_gr_intr(struct nvkm_subdev *subdev) u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; u32 show = stat; char msg[128], src[128], sta[128]; + struct nv10_gr_chan *chan; unsigned long flags; spin_lock_irqsave(&gr->lock, flags); @@ -1134,134 +1132,11 @@ nv10_gr_intr(struct nvkm_subdev *subdev) spin_unlock_irqrestore(&gr->lock, flags); } -static const struct nvkm_gr_func -nv10_gr = { - .chan_new = nv10_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv04_gr_object }, /* null */ - { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ - { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ - { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ - { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ - { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ - { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ - { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ - { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ - { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ - { -1, -1, 0x0056, &nv04_gr_object }, /* celcius */ - {} - } -}; - -static const struct nvkm_gr_func -nv15_gr = { - .chan_new = nv10_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv04_gr_object }, /* null */ - { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ - { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ - { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ - { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ - { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ - { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ - { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ - { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ - { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ - { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ - {} - } -}; - - -static const struct nvkm_gr_func -nv17_gr = { - .chan_new = nv10_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv04_gr_object }, /* null */ - { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ - { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ - { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ - { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ - { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ - { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ - { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ - { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ - { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ - { -1, -1, 0x0099, &nv04_gr_object }, - {} - } -}; - -static int -nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv10_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv10_gr_intr; - - if (nv_device(gr)->chipset <= 0x10) - gr->base.func = &nv10_gr; - else - if (nv_device(gr)->chipset < 0x17 || - nv_device(gr)->card_type < NV_11) - gr->base.func = &nv15_gr; - else - gr->base.func = &nv17_gr; - - nv_engine(gr)->tile_prog = nv10_gr_tile_prog; - spin_lock_init(&gr->lock); - return 0; -} - -static void -nv10_gr_dtor(struct nvkm_object *object) +int +nv10_gr_init(struct nvkm_gr *base) { - struct nv10_gr *gr = (void *)object; - nvkm_gr_destroy(&gr->base); -} - -static int -nv10_gr_init(struct nvkm_object *object) -{ - struct nvkm_engine *engine = nv_engine(object); - struct nv10_gr *gr = (void *)engine; + struct nv10_gr *gr = nv10_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_fb *fb = device->fb; - int ret, i; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); @@ -1273,8 +1148,7 @@ nv10_gr_init(struct nvkm_object *object) nvkm_wr32(device, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); - if (nv_device(gr)->card_type >= NV_11 && - nv_device(gr)->chipset >= 0x17) { + if (device->card_type >= NV_11 && device->chipset >= 0x17) { nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x1f000000); nvkm_wr32(device, 0x400a10, 0x03ff3fb6); nvkm_wr32(device, 0x400838, 0x002f8684); @@ -1284,10 +1158,6 @@ nv10_gr_init(struct nvkm_object *object) nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); } - /* Turn all the tiling regions off. */ - for (i = 0; i < fb->tile.regions; i++) - engine->tile_prog(engine, i); - nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); nvkm_wr32(device, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); @@ -1301,20 +1171,51 @@ nv10_gr_init(struct nvkm_object *object) return 0; } -static int -nv10_gr_fini(struct nvkm_object *object, bool suspend) +int +nv10_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, + int index, struct nvkm_gr **pgr) { - struct nv10_gr *gr = (void *)object; - return nvkm_gr_fini(&gr->base, suspend); + struct nv10_gr *gr; + + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; + spin_lock_init(&gr->lock); + *pgr = &gr->base; + + return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); } -struct nvkm_oclass -nv10_gr_oclass = { - .handle = NV_ENGINE(GR, 0x10), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv10_gr_ctor, - .dtor = nv10_gr_dtor, - .init = nv10_gr_init, - .fini = nv10_gr_fini, - }, +static const struct nvkm_gr_func +nv10_gr = { + .init = nv10_gr_init, + .intr = nv10_gr_intr, + .tile = nv10_gr_tile, + .chan_new = nv10_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ + { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0056, &nv04_gr_object }, /* celcius */ + {} + } }; + +int +nv10_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv10_gr_new_(&nv10_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h new file mode 100644 index 000000000000..d7c3d86cc99d --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.h @@ -0,0 +1,13 @@ +#ifndef __NV10_GR_H__ +#define __NV10_GR_H__ +#include "priv.h" + +int nv10_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, + struct nvkm_gr **); +int nv10_gr_init(struct nvkm_gr *); +void nv10_gr_intr(struct nvkm_gr *); +void nv10_gr_tile(struct nvkm_gr *, int, struct nvkm_fb_tile *); + +int nv10_gr_chan_new(struct nvkm_gr *, struct nvkm_fifo_chan *, + const struct nvkm_oclass *, struct nvkm_object **); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c new file mode 100644 index 000000000000..3e2c6856b4c4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.c @@ -0,0 +1,59 @@ +/* + * Copyright 2007 Matthieu CASTET + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragr) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "nv10.h" + +static const struct nvkm_gr_func +nv15_gr = { + .init = nv10_gr_init, + .intr = nv10_gr_intr, + .tile = nv10_gr_tile, + .chan_new = nv10_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ + { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + {} + } +}; + +int +nv15_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv10_gr_new_(&nv15_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c new file mode 100644 index 000000000000..12437d085a73 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.c @@ -0,0 +1,59 @@ +/* + * Copyright 2007 Matthieu CASTET + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragr) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "nv10.h" + +static const struct nvkm_gr_func +nv17_gr = { + .init = nv10_gr_init, + .intr = nv10_gr_intr, + .tile = nv10_gr_tile, + .chan_new = nv10_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* pattern */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0052, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x005f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* blit */ + { -1, -1, 0x0093, &nv04_gr_object }, /* surf3d */ + { -1, -1, 0x0094, &nv04_gr_object }, /* ttri */ + { -1, -1, 0x0095, &nv04_gr_object }, /* mtri */ + { -1, -1, 0x0099, &nv04_gr_object }, + {} + } +}; + +int +nv17_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv10_gr_new_(&nv17_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index ce4f9925ea9b..32ea28a71a41 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -145,12 +145,11 @@ nv20_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, ******************************************************************************/ void -nv20_gr_tile_prog(struct nvkm_engine *engine, int i) +nv20_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) { - struct nv20_gr *gr = (void *)engine; + struct nv20_gr *gr = nv20_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_fifo *fifo = device->fifo; - struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; nvkm_fifo_pause(fifo, &flags); @@ -167,7 +166,7 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr); - if (nv_device(engine)->chipset != 0x34) { + if (device->chipset != 0x34) { nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp); @@ -177,10 +176,11 @@ nv20_gr_tile_prog(struct nvkm_engine *engine, int i) } void -nv20_gr_intr(struct nvkm_subdev *subdev) +nv20_gr_intr(struct nvkm_gr *base) { - struct nv20_gr *gr = (void *)subdev; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nv20_gr *gr = nv20_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; struct nvkm_fifo_chan *chan; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); @@ -215,82 +215,27 @@ nv20_gr_intr(struct nvkm_subdev *subdev) nvkm_fifo_chan_put(device->fifo, flags, &chan); } -static const struct nvkm_gr_func -nv20_gr = { - .chan_new = nv20_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv04_gr_object }, /* null */ - { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ - { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ - { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ - { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ - { -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */ - { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ - { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ - {} - } -}; - -static int -nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = (void *)parent; - struct nv20_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->base.func = &nv20_gr; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, - &gr->ctxtab); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->tile_prog = nv20_gr_tile_prog; - return 0; -} - -void -nv20_gr_dtor(struct nvkm_object *object) +int +nv20_gr_oneinit(struct nvkm_gr *base) { - struct nv20_gr *gr = (void *)object; - nvkm_memory_del(&gr->ctxtab); - nvkm_gr_destroy(&gr->base); + struct nv20_gr *gr = nv20_gr(base); + return nvkm_memory_new(gr->base.engine.subdev.device, + NVKM_MEM_TARGET_INST, 32 * 4, 16, + true, &gr->ctxtab); } int -nv20_gr_init(struct nvkm_object *object) +nv20_gr_init(struct nvkm_gr *base) { - struct nvkm_engine *engine = nv_engine(object); - struct nv20_gr *gr = (void *)engine; + struct nv20_gr *gr = nv20_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_fb *fb = device->fb; u32 tmp, vramsz; - int ret, i; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; + int i; nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, nvkm_memory_addr(gr->ctxtab) >> 4); - if (nv_device(gr)->chipset == 0x20) { + if (device->chipset == 0x20) { nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000); for (i = 0; i < 15; i++) nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000); @@ -318,7 +263,7 @@ nv20_gr_init(struct nvkm_object *object) nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000); nvkm_wr32(device, 0x40009C , 0x00000040); - if (nv_device(gr)->chipset >= 0x25) { + if (device->chipset >= 0x25) { nvkm_wr32(device, 0x400890, 0x00a8cfff); nvkm_wr32(device, 0x400610, 0x304B1FB6); nvkm_wr32(device, 0x400B80, 0x1cbd3883); @@ -338,10 +283,6 @@ nv20_gr_init(struct nvkm_object *object) nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030); } - /* Turn all the tiling regions off. */ - for (i = 0; i < fb->tile.regions; i++) - engine->tile_prog(engine, i); - nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324)); nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324)); @@ -355,7 +296,7 @@ nv20_gr_init(struct nvkm_object *object) nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp); /* begin RAM config */ - vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; + vramsz = nv_device_resource_len(device, 1) - 1; nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); @@ -378,13 +319,57 @@ nv20_gr_init(struct nvkm_object *object) return 0; } -struct nvkm_oclass -nv20_gr_oclass = { - .handle = NV_ENGINE(GR, 0x20), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv20_gr_ctor, - .dtor = nv20_gr_dtor, - .init = nv20_gr_init, - .fini = _nvkm_gr_fini, - }, +void * +nv20_gr_dtor(struct nvkm_gr *base) +{ + struct nv20_gr *gr = nv20_gr(base); + nvkm_memory_del(&gr->ctxtab); + return gr; +} + +int +nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, + int index, struct nvkm_gr **pgr) +{ + struct nv20_gr *gr; + + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; + *pgr = &gr->base; + + return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); +} + +static const struct nvkm_gr_func +nv20_gr = { + .dtor = nv20_gr_dtor, + .oneinit = nv20_gr_oneinit, + .init = nv20_gr_init, + .intr = nv20_gr_intr, + .tile = nv20_gr_tile, + .chan_new = nv20_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x0096, &nv04_gr_object }, /* celcius */ + { -1, -1, 0x0097, &nv04_gr_object }, /* kelvin */ + { -1, -1, 0x009e, &nv04_gr_object }, /* swzsurf */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + {} + } }; + +int +nv20_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv20_gr_new_(&nv20_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h index 1ae4f2acc612..cdf4501e3798 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h @@ -8,6 +8,16 @@ struct nv20_gr { struct nvkm_memory *ctxtab; }; +int nv20_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, + int, struct nvkm_gr **); +void *nv20_gr_dtor(struct nvkm_gr *); +int nv20_gr_oneinit(struct nvkm_gr *); +int nv20_gr_init(struct nvkm_gr *); +void nv20_gr_intr(struct nvkm_gr *); +void nv20_gr_tile(struct nvkm_gr *, int, struct nvkm_fb_tile *); + +int nv30_gr_init(struct nvkm_gr *); + #define nv20_gr_chan(p) container_of((p), struct nv20_gr_chan, object) struct nv20_gr_chan { @@ -18,14 +28,6 @@ struct nv20_gr_chan { }; void *nv20_gr_chan_dtor(struct nvkm_object *); -int nv20_gr_chan_init(struct nvkm_object *); -int nv20_gr_chan_fini(struct nvkm_object *, bool); - -void nv20_gr_tile_prog(struct nvkm_engine *, int); -void nv20_gr_intr(struct nvkm_subdev *); - -void nv20_gr_dtor(struct nvkm_object *); -int nv20_gr_init(struct nvkm_object *); - -int nv30_gr_init(struct nvkm_object *); +int nv20_gr_chan_init(struct nvkm_object *); +int nv20_gr_chan_fini(struct nvkm_object *, bool); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c index cc56ca9505f4..6c4a00819b4b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c @@ -101,6 +101,11 @@ nv25_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, static const struct nvkm_gr_func nv25_gr = { + .dtor = nv20_gr_dtor, + .oneinit = nv20_gr_oneinit, + .init = nv20_gr_init, + .intr = nv20_gr_intr, + .tile = nv20_gr_tile, .chan_new = nv25_gr_chan_new, .sclass = { { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ @@ -122,40 +127,8 @@ nv25_gr = { } }; -static int -nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv25_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) { - struct nvkm_device *device = (void *)parent; - struct nv20_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->base.func = &nv25_gr; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, - &gr->ctxtab); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->tile_prog = nv20_gr_tile_prog; - return 0; + return nv20_gr_new_(&nv25_gr, device, index, pgr); } - -struct nvkm_oclass -nv25_gr_oclass = { - .handle = NV_ENGINE(GR, 0x25), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv25_gr_ctor, - .dtor = nv20_gr_dtor, - .init = nv20_gr_init, - .fini = _nvkm_gr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c index 4e4cd93d686d..3cad26dbc2b1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c @@ -92,6 +92,11 @@ nv2a_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, static const struct nvkm_gr_func nv2a_gr = { + .dtor = nv20_gr_dtor, + .oneinit = nv20_gr_oneinit, + .init = nv20_gr_init, + .intr = nv20_gr_intr, + .tile = nv20_gr_tile, .chan_new = nv2a_gr_chan_new, .sclass = { { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ @@ -113,40 +118,8 @@ nv2a_gr = { } }; -static int -nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv2a_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) { - struct nvkm_device *device = (void *)parent; - struct nv20_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->base.func = &nv2a_gr; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, - &gr->ctxtab); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->tile_prog = nv20_gr_tile_prog; - return 0; + return nv20_gr_new_(&nv2a_gr, device, index, pgr); } - -struct nvkm_oclass -nv2a_gr_oclass = { - .handle = NV_ENGINE(GR, 0x2a), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv2a_gr_ctor, - .dtor = nv20_gr_dtor, - .init = nv20_gr_init, - .fini = _nvkm_gr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c index ea46b16c31e6..69de8c6259fe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c @@ -99,70 +99,11 @@ nv30_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, * PGRAPH engine/subdev functions ******************************************************************************/ -static const struct nvkm_gr_func -nv30_gr = { - .chan_new = nv30_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv04_gr_object }, /* null */ - { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ - { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ - { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ - { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ - { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ - { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ - { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ - { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ - { -1, -1, 0x0397, &nv04_gr_object }, /* rankine */ - {} - } -}; - -static int -nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = (void *)parent; - struct nv20_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->base.func = &nv30_gr; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, - &gr->ctxtab); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->tile_prog = nv20_gr_tile_prog; - return 0; -} - int -nv30_gr_init(struct nvkm_object *object) +nv30_gr_init(struct nvkm_gr *base) { - struct nvkm_engine *engine = nv_engine(object); - struct nv20_gr *gr = (void *)engine; + struct nv20_gr *gr = nv20_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_fb *fb = device->fb; - int ret, i; - - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, nvkm_memory_addr(gr->ctxtab) >> 4); @@ -189,7 +130,7 @@ nv30_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x400ba4, 0x00231f3f); nvkm_wr32(device, 0x4008a4, 0x40000020); - if (nv_device(gr)->chipset == 0x34) { + if (device->chipset == 0x34) { nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00200201); nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); @@ -202,10 +143,6 @@ nv30_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x4000c0, 0x00000016); - /* Turn all the tiling regions off. */ - for (i = 0; i < fb->tile.regions; i++) - engine->tile_prog(engine, i); - nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100); nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF); nvkm_wr32(device, 0x0040075c , 0x00000001); @@ -214,22 +151,48 @@ nv30_gr_init(struct nvkm_object *object) /* vramsz = pci_resource_len(gr->dev->pdev, 1) - 1; */ nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); - if (nv_device(gr)->chipset != 0x34) { + if (device->chipset != 0x34) { nvkm_wr32(device, 0x400750, 0x00EA0000); nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100200)); nvkm_wr32(device, 0x400750, 0x00EA0004); nvkm_wr32(device, 0x400754, nvkm_rd32(device, 0x100204)); } + return 0; } -struct nvkm_oclass -nv30_gr_oclass = { - .handle = NV_ENGINE(GR, 0x30), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv30_gr_ctor, - .dtor = nv20_gr_dtor, - .init = nv30_gr_init, - .fini = _nvkm_gr_fini, - }, +static const struct nvkm_gr_func +nv30_gr = { + .dtor = nv20_gr_dtor, + .oneinit = nv20_gr_oneinit, + .init = nv30_gr_init, + .intr = nv20_gr_intr, + .tile = nv20_gr_tile, + .chan_new = nv30_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv04_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv04_gr_object }, /* null */ + { -1, -1, 0x0039, &nv04_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv04_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv04_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv04_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv04_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv04_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv04_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv04_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv04_gr_object }, /* imageblit */ + { -1, -1, 0x0362, &nv04_gr_object }, /* surf2d (nv30) */ + { -1, -1, 0x0389, &nv04_gr_object }, /* sifm (nv30) */ + { -1, -1, 0x038a, &nv04_gr_object }, /* ifc (nv30) */ + { -1, -1, 0x039e, &nv04_gr_object }, /* swzsurf (nv30) */ + { -1, -1, 0x0397, &nv04_gr_object }, /* rankine */ + {} + } }; + +int +nv30_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv20_gr_new_(&nv30_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c index 0667e9d14b42..2207dac23981 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c @@ -100,6 +100,11 @@ nv34_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, static const struct nvkm_gr_func nv34_gr = { + .dtor = nv20_gr_dtor, + .oneinit = nv20_gr_oneinit, + .init = nv30_gr_init, + .intr = nv20_gr_intr, + .tile = nv20_gr_tile, .chan_new = nv34_gr_chan_new, .sclass = { { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ @@ -123,40 +128,8 @@ nv34_gr = { } }; -static int -nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv34_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) { - struct nvkm_device *device = (void *)parent; - struct nv20_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->base.func = &nv34_gr; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, - &gr->ctxtab); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->tile_prog = nv20_gr_tile_prog; - return 0; + return nv20_gr_new_(&nv34_gr, device, index, pgr); } - -struct nvkm_oclass -nv34_gr_oclass = { - .handle = NV_ENGINE(GR, 0x34), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv34_gr_ctor, - .dtor = nv20_gr_dtor, - .init = nv30_gr_init, - .fini = _nvkm_gr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c index 745d0e133d9a..740df0f52c38 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c @@ -100,6 +100,11 @@ nv35_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, static const struct nvkm_gr_func nv35_gr = { + .dtor = nv20_gr_dtor, + .oneinit = nv20_gr_oneinit, + .init = nv30_gr_init, + .intr = nv20_gr_intr, + .tile = nv20_gr_tile, .chan_new = nv35_gr_chan_new, .sclass = { { -1, -1, 0x0012, &nv04_gr_object }, /* beta1 */ @@ -123,40 +128,8 @@ nv35_gr = { } }; -static int -nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) +int +nv35_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) { - struct nvkm_device *device = (void *)parent; - struct nv20_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - gr->base.func = &nv35_gr; - - ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 32 * 4, 16, true, - &gr->ctxtab); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv20_gr_intr; - nv_engine(gr)->tile_prog = nv20_gr_tile_prog; - return 0; + return nv20_gr_new_(&nv35_gr, device, index, pgr); } - -struct nvkm_oclass -nv35_gr_oclass = { - .handle = NV_ENGINE(GR, 0x35), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv35_gr_ctor, - .dtor = nv20_gr_dtor, - .init = nv30_gr_init, - .fini = _nvkm_gr_fini, - }, -}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index be954500b4d8..127a36f5859e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -30,7 +30,7 @@ #include #include -static u64 +u64 nv40_gr_units(struct nvkm_gr *gr) { return nvkm_rd32(gr->engine.subdev.device, 0x1540); @@ -61,7 +61,7 @@ nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, return ret; } -static const struct nvkm_object_func +const struct nvkm_object_func nv40_gr_object = { .bind = nv40_gr_object_bind, }; @@ -144,7 +144,7 @@ nv40_gr_chan = { .bind = nv40_gr_chan_bind, }; -static int +int nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { @@ -169,31 +169,29 @@ nv40_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, ******************************************************************************/ static void -nv40_gr_tile_prog(struct nvkm_engine *engine, int i) +nv40_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) { - struct nv40_gr *gr = (void *)engine; + struct nv40_gr *gr = nv40_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; struct nvkm_fifo *fifo = device->fifo; - struct nvkm_fb_tile *tile = &device->fb->tile.region[i]; unsigned long flags; nvkm_fifo_pause(fifo, &flags); nv04_gr_idle(&gr->base); - switch (nv_device(gr)->chipset) { + switch (device->chipset) { case 0x40: case 0x41: case 0x42: case 0x43: case 0x45: - case 0x4e: nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); - switch (nv_device(gr)->chipset) { + switch (device->chipset) { case 0x40: case 0x45: nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); @@ -209,50 +207,33 @@ nv40_gr_tile_prog(struct nvkm_engine *engine, int i) break; } break; - case 0x44: - case 0x4a: - nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); - nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); - nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); - break; - case 0x46: - case 0x4c: case 0x47: case 0x49: case 0x4b: - case 0x63: - case 0x67: - case 0x68: nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); - switch (nv_device(gr)->chipset) { - case 0x47: - case 0x49: - case 0x4b: - nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); - nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); - break; - default: - break; - } + nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); + nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); break; default: + WARN_ON(1); break; } nvkm_fifo_start(fifo, &flags); } -static void -nv40_gr_intr(struct nvkm_subdev *subdev) +void +nv40_gr_intr(struct nvkm_gr *base) { - struct nv40_gr *gr = (void *)subdev; + struct nv40_gr *gr = nv40_gr(base); struct nv40_gr_chan *temp, *chan = NULL; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); @@ -301,98 +282,16 @@ nv40_gr_intr(struct nvkm_subdev *subdev) spin_unlock_irqrestore(&gr->base.engine.lock, flags); } -static const struct nvkm_gr_func -nv40_gr = { - .chan_new = nv40_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv40_gr_object }, /* null */ - { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ - { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ - { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ - { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ - { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ - { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ - { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ - { -1, -1, 0x4097, &nv40_gr_object }, /* curie */ - {} - } -}; - -static const struct nvkm_gr_func -nv44_gr = { - .chan_new = nv40_gr_chan_new, - .sclass = { - { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ - { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ - { -1, -1, 0x0030, &nv40_gr_object }, /* null */ - { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ - { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ - { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ - { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ - { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ - { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ - { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ - { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ - { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ - { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ - { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ - { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ - { -1, -1, 0x4497, &nv40_gr_object }, /* curie */ - {} - } -}; - -static int -nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_device *device = (void *)parent; - struct nv40_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - INIT_LIST_HEAD(&gr->chan); - - nv_subdev(gr)->unit = 0x00001000; - nv_subdev(gr)->intr = nv40_gr_intr; - if (nv44_gr_class(device)) - gr->base.func = &nv44_gr; - else - gr->base.func = &nv40_gr; - nv_engine(gr)->tile_prog = nv40_gr_tile_prog; - - gr->base.units = nv40_gr_units; - return 0; -} - -static int -nv40_gr_init(struct nvkm_object *object) +int +nv40_gr_init(struct nvkm_gr *base) { - struct nvkm_engine *engine = nv_engine(object); - struct nv40_gr *gr = (void *)engine; + struct nv40_gr *gr = nv40_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; - struct nvkm_fb *fb = device->fb; int ret, i, j; u32 vramsz; - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; - /* generate and upload context program */ - ret = nv40_grctx_init(nv_device(gr), &gr->size); + ret = nv40_grctx_init(device, &gr->size); if (ret) return ret; @@ -419,7 +318,7 @@ nv40_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x405000, i); } - if (nv_device(gr)->chipset == 0x40) { + if (device->chipset == 0x40) { nvkm_wr32(device, 0x4009b0, 0x83280fff); nvkm_wr32(device, 0x4009b4, 0x000000a0); } else { @@ -427,7 +326,7 @@ nv40_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x400824, 0x000000a0); } - switch (nv_device(gr)->chipset) { + switch (device->chipset) { case 0x40: case 0x45: nvkm_wr32(device, 0x4009b8, 0x0078e366); @@ -465,7 +364,7 @@ nv40_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x400b3c, 0x00006000); /* Tiling related stuff. */ - switch (nv_device(gr)->chipset) { + switch (device->chipset) { case 0x44: case 0x4a: nvkm_wr32(device, 0x400bc4, 0x1003d888); @@ -485,13 +384,9 @@ nv40_gr_init(struct nvkm_object *object) break; } - /* Turn all the tiling regions off. */ - for (i = 0; i < fb->tile.regions; i++) - engine->tile_prog(engine, i); - /* begin RAM config */ - vramsz = nv_device_resource_len(nv_device(gr), 1) - 1; - switch (nv_device(gr)->chipset) { + vramsz = nv_device_resource_len(device, 1) - 1; + switch (device->chipset) { case 0x40: nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); @@ -503,7 +398,7 @@ nv40_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x400868, vramsz); break; default: - switch (nv_device(gr)->chipset) { + switch (device->chipset) { case 0x41: case 0x42: case 0x43: @@ -531,13 +426,50 @@ nv40_gr_init(struct nvkm_object *object) return 0; } -struct nvkm_oclass -nv40_gr_oclass = { - .handle = NV_ENGINE(GR, 0x40), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv40_gr_ctor, - .dtor = _nvkm_gr_dtor, - .init = nv40_gr_init, - .fini = _nvkm_gr_fini, - }, +int +nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, + int index, struct nvkm_gr **pgr) +{ + struct nv40_gr *gr; + + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; + *pgr = &gr->base; + INIT_LIST_HEAD(&gr->chan); + + return nvkm_gr_ctor(func, device, index, 0x00001000, true, &gr->base); +} + +static const struct nvkm_gr_func +nv40_gr = { + .init = nv40_gr_init, + .intr = nv40_gr_intr, + .tile = nv40_gr_tile, + .units = nv40_gr_units, + .chan_new = nv40_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv40_gr_object }, /* null */ + { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ + { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ + { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ + { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ + { -1, -1, 0x4097, &nv40_gr_object }, /* curie */ + {} + } }; + +int +nv40_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv40_gr_new_(&nv40_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h index 42cc409a8df2..2812ed11f877 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h @@ -9,6 +9,12 @@ struct nv40_gr { struct list_head chan; }; +int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, + struct nvkm_gr **); +int nv40_gr_init(struct nvkm_gr *); +void nv40_gr_intr(struct nvkm_gr *); +u64 nv40_gr_units(struct nvkm_gr *); + #define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object) struct nv40_gr_chan { @@ -19,6 +25,11 @@ struct nv40_gr_chan { struct list_head head; }; +int nv40_gr_chan_new(struct nvkm_gr *, struct nvkm_fifo_chan *, + const struct nvkm_oclass *, struct nvkm_object **); + +extern const struct nvkm_object_func nv40_gr_object; + /* returns 1 if device is one of the nv4x using the 0x4497 object class, * helpful to determine a number of other hardware features */ @@ -28,7 +39,7 @@ nv44_gr_class(struct nvkm_device *device) if ((device->chipset & 0xf0) == 0x60) return 1; - return !(0x0baf & (1 << (device->chipset & 0x0f))); + return !(0x0aaf & (1 << (device->chipset & 0x0f))); } int nv40_grctx_init(struct nvkm_device *, u32 *size); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c new file mode 100644 index 000000000000..45ff80254eb4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.c @@ -0,0 +1,108 @@ +/* + * Copyright 2012 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs + */ +#include "nv40.h" +#include "regs.h" + +#include +#include + +static void +nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) +{ + struct nv40_gr *gr = nv40_gr(base); + struct nvkm_device *device = gr->base.engine.subdev.device; + struct nvkm_fifo *fifo = device->fifo; + unsigned long flags; + + nvkm_fifo_pause(fifo, &flags); + nv04_gr_idle(&gr->base); + + switch (device->chipset) { + case 0x44: + case 0x4a: + nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); + break; + case 0x46: + case 0x4c: + case 0x63: + case 0x67: + case 0x68: + nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); + break; + case 0x4e: + nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); + nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); + nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); + nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); + nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); + nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); + break; + default: + WARN_ON(1); + break; + } + + nvkm_fifo_start(fifo, &flags); +} + +static const struct nvkm_gr_func +nv44_gr = { + .init = nv40_gr_init, + .intr = nv40_gr_intr, + .tile = nv44_gr_tile, + .units = nv40_gr_units, + .chan_new = nv40_gr_chan_new, + .sclass = { + { -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */ + { -1, -1, 0x0019, &nv40_gr_object }, /* clip */ + { -1, -1, 0x0030, &nv40_gr_object }, /* null */ + { -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */ + { -1, -1, 0x0043, &nv40_gr_object }, /* rop */ + { -1, -1, 0x0044, &nv40_gr_object }, /* patt */ + { -1, -1, 0x004a, &nv40_gr_object }, /* gdi */ + { -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */ + { -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */ + { -1, -1, 0x0089, &nv40_gr_object }, /* sifm */ + { -1, -1, 0x008a, &nv40_gr_object }, /* ifc */ + { -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */ + { -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */ + { -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */ + { -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */ + { -1, -1, 0x4497, &nv40_gr_object }, /* curie */ + {} + } +}; + +int +nv44_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv40_gr_new_(&nv44_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 11c4c8838937..9992a919a6d9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -25,10 +25,9 @@ #include #include -#include #include -static u64 +u64 nv50_gr_units(struct nvkm_gr *gr) { return nvkm_rd32(gr->engine.subdev.device, 0x1540); @@ -55,27 +54,11 @@ nv50_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, return ret; } -static const struct nvkm_object_func +const struct nvkm_object_func nv50_gr_object = { .bind = nv50_gr_object_bind, }; -static int -nv50_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass) -{ - struct nv50_gr *gr = nv50_gr(base); - int c = 0; - - while (gr->func->sclass[c].oclass) { - if (c++ == index) { - *sclass = gr->func->sclass[index]; - return index; - } - } - - return c; -} - /******************************************************************************* * PGRAPH context ******************************************************************************/ @@ -100,7 +83,7 @@ nv50_gr_chan = { .bind = nv50_gr_chan_bind, }; -static int +int nv50_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, const struct nvkm_oclass *oclass, struct nvkm_object **pobject) { @@ -119,153 +102,6 @@ nv50_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch, * PGRAPH engine/subdev functions ******************************************************************************/ -static const struct nvkm_bitfield nv50_gr_status[] = { - { 0x00000001, "BUSY" }, /* set when any bit is set */ - { 0x00000002, "DISPATCH" }, - { 0x00000004, "UNK2" }, - { 0x00000008, "UNK3" }, - { 0x00000010, "UNK4" }, - { 0x00000020, "UNK5" }, - { 0x00000040, "M2MF" }, - { 0x00000080, "UNK7" }, - { 0x00000100, "CTXPROG" }, - { 0x00000200, "VFETCH" }, - { 0x00000400, "CCACHE_PREGEOM" }, - { 0x00000800, "STRMOUT_VATTR_POSTGEOM" }, - { 0x00001000, "VCLIP" }, - { 0x00002000, "RATTR_APLANE" }, - { 0x00004000, "TRAST" }, - { 0x00008000, "CLIPID" }, - { 0x00010000, "ZCULL" }, - { 0x00020000, "ENG2D" }, - { 0x00040000, "RMASK" }, - { 0x00080000, "TPC_RAST" }, - { 0x00100000, "TPC_PROP" }, - { 0x00200000, "TPC_TEX" }, - { 0x00400000, "TPC_GEOM" }, - { 0x00800000, "TPC_MP" }, - { 0x01000000, "ROP" }, - {} -}; - -static const struct nvkm_bitfield -nv50_gr_vstatus_0[] = { - { 0x01, "VFETCH" }, - { 0x02, "CCACHE" }, - { 0x04, "PREGEOM" }, - { 0x08, "POSTGEOM" }, - { 0x10, "VATTR" }, - { 0x20, "STRMOUT" }, - { 0x40, "VCLIP" }, - {} -}; - -static const struct nvkm_bitfield -nv50_gr_vstatus_1[] = { - { 0x01, "TPC_RAST" }, - { 0x02, "TPC_PROP" }, - { 0x04, "TPC_TEX" }, - { 0x08, "TPC_GEOM" }, - { 0x10, "TPC_MP" }, - {} -}; - -static const struct nvkm_bitfield -nv50_gr_vstatus_2[] = { - { 0x01, "RATTR" }, - { 0x02, "APLANE" }, - { 0x04, "TRAST" }, - { 0x08, "CLIPID" }, - { 0x10, "ZCULL" }, - { 0x20, "ENG2D" }, - { 0x40, "RMASK" }, - { 0x80, "ROP" }, - {} -}; - -static void -nvkm_gr_vstatus_print(struct nv50_gr *gr, int r, - const struct nvkm_bitfield *units, u32 status) -{ - struct nvkm_subdev *subdev = &gr->base.engine.subdev; - u32 stat = status; - u8 mask = 0x00; - char msg[64]; - int i; - - for (i = 0; units[i].name && status; i++) { - if ((status & 7) == 1) - mask |= (1 << i); - status >>= 3; - } - - nvkm_snprintbf(msg, sizeof(msg), units, mask); - nvkm_error(subdev, "PGRAPH_VSTATUS%d: %08x [%s]\n", r, stat, msg); -} - -static int -g84_gr_tlb_flush(struct nvkm_engine *engine) -{ - struct nv50_gr *gr = (void *)engine; - struct nvkm_subdev *subdev = &gr->base.engine.subdev; - struct nvkm_device *device = subdev->device; - struct nvkm_timer *tmr = device->timer; - bool idle, timeout = false; - unsigned long flags; - char status[128]; - u64 start; - u32 tmp; - - spin_lock_irqsave(&gr->lock, flags); - nvkm_mask(device, 0x400500, 0x00000001, 0x00000000); - - start = nvkm_timer_read(tmr); - do { - idle = true; - - for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { - if ((tmp & 7) == 1) - idle = false; - } - - for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { - if ((tmp & 7) == 1) - idle = false; - } - - for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { - if ((tmp & 7) == 1) - idle = false; - } - } while (!idle && - !(timeout = nvkm_timer_read(tmr) - start > 2000000000)); - - if (timeout) { - nvkm_error(subdev, "PGRAPH TLB flush idle timeout fail\n"); - - tmp = nvkm_rd32(device, 0x400700); - nvkm_snprintbf(status, sizeof(status), nv50_gr_status, tmp); - nvkm_error(subdev, "PGRAPH_STATUS %08x [%s]\n", tmp, status); - - nvkm_gr_vstatus_print(gr, 0, nv50_gr_vstatus_0, - nvkm_rd32(device, 0x400380)); - nvkm_gr_vstatus_print(gr, 1, nv50_gr_vstatus_1, - nvkm_rd32(device, 0x400384)); - nvkm_gr_vstatus_print(gr, 2, nv50_gr_vstatus_2, - nvkm_rd32(device, 0x400388)); - } - - - nvkm_wr32(device, 0x100c80, 0x00000001); - nvkm_msec(device, 2000, - if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) - break; - ); - nvkm_mask(device, 0x400500, 0x00000001, 0x00000001); - spin_unlock_irqrestore(&gr->lock, flags); - return timeout ? -EBUSY : 0; -} - static const struct nvkm_bitfield nv50_mp_exec_errors[] = { { 0x01, "STACK_UNDERFLOW" }, { 0x02, "STACK_MISMATCH" }, @@ -453,7 +289,7 @@ nv50_gr_mp_trap(struct nv50_gr *gr, int tpid, int display) for (i = 0; i < 4; i++) { if (!(units & 1 << (i+24))) continue; - if (nv_device(gr)->chipset < 0xa0) + if (device->chipset < 0xa0) addr = 0x408200 + (tpid << 12) + (i << 7); else addr = 0x408100 + (tpid << 11) + (i << 7); @@ -497,7 +333,7 @@ nv50_gr_tp_trap(struct nv50_gr *gr, int type, u32 ustatus_old, for (i = 0; i < 16; i++) { if (!(units & (1 << i))) continue; - if (nv_device(gr)->chipset < 0xa0) + if (device->chipset < 0xa0) ustatus_addr = ustatus_old + (i << 12); else ustatus_addr = ustatus_new + (i << 11); @@ -778,11 +614,12 @@ nv50_gr_trap_handler(struct nv50_gr *gr, u32 display, return 1; } -static void -nv50_gr_intr(struct nvkm_subdev *subdev) +void +nv50_gr_intr(struct nvkm_gr *base) { - struct nv50_gr *gr = (void *)subdev; - struct nvkm_device *device = gr->base.engine.subdev.device; + struct nv50_gr *gr = nv50_gr(base); + struct nvkm_subdev *subdev = &gr->base.engine.subdev; + struct nvkm_device *device = subdev->device; struct nvkm_fifo_chan *chan; u32 stat = nvkm_rd32(device, 0x400100); u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff; @@ -836,140 +673,13 @@ nv50_gr_intr(struct nvkm_subdev *subdev) nvkm_fifo_chan_put(device->fifo, flags, &chan); } -static const struct nv50_gr_func -nv50_gr = { - .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x5097, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - {} - } -}; - -static const struct nv50_gr_func -g84_gr = { - .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8297, &nv50_gr_object }, - {} - } -}; - -static const struct nv50_gr_func -gt200_gr = { - .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8397, &nv50_gr_object }, - {} - } -}; - -static const struct nv50_gr_func -gt215_gr = { - .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x8597, &nv50_gr_object }, - { -1, -1, 0x85c0, &nv50_gr_object }, - {} - } -}; - -static const struct nv50_gr_func -mcp89_gr = { - .sclass = { - { -1, -1, 0x0030, &nv50_gr_object }, - { -1, -1, 0x502d, &nv50_gr_object }, - { -1, -1, 0x5039, &nv50_gr_object }, - { -1, -1, 0x50c0, &nv50_gr_object }, - { -1, -1, 0x85c0, &nv50_gr_object }, - { -1, -1, 0x8697, &nv50_gr_object }, - {} - } -}; - -static const struct nvkm_gr_func -nv50_gr_ = { - .chan_new = nv50_gr_chan_new, - .object_get = nv50_gr_object_get, -}; - -static int -nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nv50_gr *gr; - int ret; - - ret = nvkm_gr_create(parent, engine, oclass, true, &gr); - *pobject = nv_object(gr); - if (ret) - return ret; - - nv_subdev(gr)->unit = 0x00201000; - nv_subdev(gr)->intr = nv50_gr_intr; - - gr->base.func = &nv50_gr_; - gr->base.units = nv50_gr_units; - - switch (nv_device(gr)->chipset) { - case 0x50: - gr->func = &nv50_gr; - break; - case 0x84: - case 0x86: - case 0x92: - case 0x94: - case 0x96: - case 0x98: - gr->func = &g84_gr; - break; - case 0xa0: - case 0xaa: - case 0xac: - gr->func = >200_gr; - break; - case 0xa3: - case 0xa5: - case 0xa8: - gr->func = >215_gr; - break; - case 0xaf: - gr->func = &mcp89_gr; - break; - } - - /* unfortunate hw bug workaround... */ - if (nv_device(gr)->chipset != 0x50 && - nv_device(gr)->chipset != 0xac) - nv_engine(gr)->tlb_flush = g84_gr_tlb_flush; - - spin_lock_init(&gr->lock); - return 0; -} - -static int -nv50_gr_init(struct nvkm_object *object) +int +nv50_gr_init(struct nvkm_gr *base) { - struct nv50_gr *gr = (void *)object; + struct nv50_gr *gr = nv50_gr(base); struct nvkm_device *device = gr->base.engine.subdev.device; int ret, units, i; - ret = nvkm_gr_init(&gr->base); - if (ret) - return ret; - /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ nvkm_wr32(device, 0x40008c, 0x00000004); @@ -986,7 +696,7 @@ nv50_gr_init(struct nvkm_object *object) if (!(units & (1 << i))) continue; - if (nv_device(gr)->chipset < 0xa0) { + if (device->chipset < 0xa0) { nvkm_wr32(device, 0x408900 + (i << 12), 0xc0000000); nvkm_wr32(device, 0x408e08 + (i << 12), 0xc0000000); nvkm_wr32(device, 0x408314 + (i << 12), 0xc0000000); @@ -1004,7 +714,7 @@ nv50_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x400500, 0x00010001); /* upload context program, initialise ctxctl defaults */ - ret = nv50_grctx_init(nv_device(gr), &gr->size); + ret = nv50_grctx_init(device, &gr->size); if (ret) return ret; @@ -1016,7 +726,7 @@ nv50_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x400330, 0x00000000); /* some unknown zcull magic */ - switch (nv_device(gr)->chipset & 0xf0) { + switch (device->chipset & 0xf0) { case 0x50: case 0x80: case 0x90: @@ -1024,9 +734,9 @@ nv50_gr_init(struct nvkm_object *object) break; case 0xa0: default: - if (nv_device(gr)->chipset == 0xa0 || - nv_device(gr)->chipset == 0xaa || - nv_device(gr)->chipset == 0xac) { + if (device->chipset == 0xa0 || + device->chipset == 0xaa || + device->chipset == 0xac) { nvkm_wr32(device, 0x402ca8, 0x00000802); } else { nvkm_wr32(device, 0x402cc0, 0x00000000); @@ -1043,16 +753,42 @@ nv50_gr_init(struct nvkm_object *object) nvkm_wr32(device, 0x402c28 + (i * 0x10), 0x00000000); nvkm_wr32(device, 0x402c2c + (i * 0x10), 0x00000000); } + return 0; } -struct nvkm_oclass -nv50_gr_oclass = { - .handle = NV_ENGINE(GR, 0x50), - .ofuncs = &(struct nvkm_ofuncs) { - .ctor = nv50_gr_ctor, - .dtor = _nvkm_gr_dtor, - .init = nv50_gr_init, - .fini = _nvkm_gr_fini, - }, +int +nv50_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device, + int index, struct nvkm_gr **pgr) +{ + struct nv50_gr *gr; + + if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL))) + return -ENOMEM; + spin_lock_init(&gr->lock); + *pgr = &gr->base; + + return nvkm_gr_ctor(func, device, index, 0x00201000, true, &gr->base); +} + +static const struct nvkm_gr_func +nv50_gr = { + .init = nv50_gr_init, + .intr = nv50_gr_intr, + .chan_new = nv50_gr_chan_new, + .units = nv50_gr_units, + .sclass = { + { -1, -1, 0x0030, &nv50_gr_object }, + { -1, -1, 0x502d, &nv50_gr_object }, + { -1, -1, 0x5039, &nv50_gr_object }, + { -1, -1, 0x5097, &nv50_gr_object }, + { -1, -1, 0x50c0, &nv50_gr_object }, + {} + } }; + +int +nv50_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return nv50_gr_new_(&nv50_gr, device, index, pgr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h index 145ea5026a8e..45eec83a5969 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h @@ -10,10 +10,13 @@ struct nv50_gr { u32 size; }; -struct nv50_gr_func { - void *(*dtor)(struct nv50_gr *); - struct nvkm_sclass sclass[]; -}; +int nv50_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index, + struct nvkm_gr **); +int nv50_gr_init(struct nvkm_gr *); +void nv50_gr_intr(struct nvkm_gr *); +u64 nv50_gr_units(struct nvkm_gr *); + +int g84_gr_tlb_flush(struct nvkm_gr *); #define nv50_gr_chan(p) container_of((p), struct nv50_gr_chan, object) @@ -22,6 +25,11 @@ struct nv50_gr_chan { struct nv50_gr *gr; }; +int nv50_gr_chan_new(struct nvkm_gr *, struct nvkm_fifo_chan *, + const struct nvkm_oclass *, struct nvkm_object **); + +extern const struct nvkm_object_func nv50_gr_object; + int nv50_grctx_init(struct nvkm_device *, u32 *size); void nv50_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h index f7fd617b6fe5..a234590be88e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/priv.h @@ -2,14 +2,37 @@ #define __NVKM_GR_PRIV_H__ #define nvkm_gr(p) container_of((p), struct nvkm_gr, engine) #include +#include +struct nvkm_fb_tile; struct nvkm_fifo_chan; +int nvkm_gr_ctor(const struct nvkm_gr_func *, struct nvkm_device *, + int index, u32 pmc_enable, bool enable, + struct nvkm_gr *); + +bool nv04_gr_idle(struct nvkm_gr *); + struct nvkm_gr_func { + void *(*dtor)(struct nvkm_gr *); + int (*oneinit)(struct nvkm_gr *); + int (*init)(struct nvkm_gr *); + void (*intr)(struct nvkm_gr *); + void (*tile)(struct nvkm_gr *, int region, struct nvkm_fb_tile *); + int (*tlb_flush)(struct nvkm_gr *); int (*chan_new)(struct nvkm_gr *, struct nvkm_fifo_chan *, const struct nvkm_oclass *, struct nvkm_object **); int (*object_get)(struct nvkm_gr *, int, struct nvkm_sclass *); + /* Returns chipset-specific counts of units packed into an u64. + */ + u64 (*units)(struct nvkm_gr *); struct nvkm_sclass sclass[]; }; +extern const struct nvkm_bitfield nv04_gr_nsource[]; extern const struct nvkm_object_func nv04_gr_object; + +extern const struct nvkm_bitfield nv10_gr_intr_name[]; +extern const struct nvkm_bitfield nv10_gr_nstatus[]; + +extern const struct nvkm_enum nv50_data_error_names[]; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index 0f39ff883ec0..1ca02f870095 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -52,11 +52,13 @@ void nvkm_fb_tile_prog(struct nvkm_fb *fb, int region, struct nvkm_fb_tile *tile) { struct nvkm_device *device = fb->subdev.device; - fb->func->tile.prog(fb, region, tile); - if (likely(device->gr)) - device->gr->engine.tile_prog(&device->gr->engine, region); - if (likely(device->mpeg)) - device->mpeg->tile_prog(device->mpeg, region); + if (fb->func->tile.prog) { + fb->func->tile.prog(fb, region, tile); + if (device->gr) + nvkm_engine_tile(&device->gr->engine, region); + if (likely(device->mpeg)) + device->mpeg->tile_prog(device->mpeg, region); + } } int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index 931f14094eb5..21a990c1ac8b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -23,11 +23,10 @@ */ #include "priv.h" +#include #include #include - -#include -#include +#include static void nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_memory *pgt[2]) @@ -167,13 +166,10 @@ nv50_vm_flush(struct nvkm_vm *vm) continue; /* unfortunate hw bug workaround... */ - if (i == NVDEV_ENGINE_GR) { - struct nvkm_engine *engine = - nvkm_device_engine(device, i); - if (engine && engine->tlb_flush) { - engine->tlb_flush(engine); + if (i == NVDEV_ENGINE_GR && device->gr) { + int ret = nvkm_gr_tlb_flush(device->gr); + if (ret != -ENODEV) continue; - } } switch (i) { -- cgit v1.2.3 From 68f3f702b6a430a8d1e909455a60d26c0f2da530 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:22 +1000 Subject: drm/nouveau/core: remove the remainder of the previous style Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/device.h | 6 +- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 110 ++++------ drivers/gpu/drm/nouveau/include/nvkm/core/engine.h | 52 +---- drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h | 37 +--- drivers/gpu/drm/nouveau/include/nvkm/core/object.h | 88 +------- drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h | 51 +---- drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h | 4 +- drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h | 2 +- drivers/gpu/drm/nouveau/nvkm/core/engine.c | 79 +------ drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 93 -------- drivers/gpu/drm/nouveau/nvkm/core/object.c | 167 +------------- drivers/gpu/drm/nouveau/nvkm/core/oproxy.c | 2 - drivers/gpu/drm/nouveau/nvkm/core/ramht.c | 45 ++-- drivers/gpu/drm/nouveau/nvkm/core/subdev.c | 223 ++++--------------- drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild | 10 - drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 241 +++++---------------- drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c | 53 ----- drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c | 51 ----- drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 67 ------ drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c | 39 ---- drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c | 51 ----- drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c | 43 ---- drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c | 45 ---- drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c | 67 ------ drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c | 63 ------ drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h | 10 - drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 8 +- .../gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c | 105 +++++---- .../gpu/drm/nouveau/nvkm/engine/fifo/changf100.h | 2 +- .../gpu/drm/nouveau/nvkm/engine/fifo/changk104.h | 2 +- .../gpu/drm/nouveau/nvkm/engine/fifo/channv04.h | 2 +- .../gpu/drm/nouveau/nvkm/engine/fifo/channv50.c | 34 +-- .../gpu/drm/nouveau/nvkm/engine/fifo/channv50.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c | 14 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c | 6 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c | 34 +-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 50 ++--- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 34 +-- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 36 +-- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c | 34 ++- .../gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c | 22 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c | 14 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c | 12 +- .../gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c | 14 +- .../gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c | 6 +- .../gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c | 10 +- .../gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c | 12 +- drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c | 4 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c | 32 +-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c | 40 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c | 20 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c | 26 +-- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 26 +-- 68 files changed, 496 insertions(+), 1856 deletions(-) delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c delete mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h index 572310223296..900e492549d1 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/device.h +++ b/drivers/gpu/drm/nouveau/include/nvif/device.h @@ -48,7 +48,11 @@ u64 nvif_device_time(struct nvif_device *); #define nvxx_device(a) ({ \ struct nvif_device *_device = (a); \ - nv_device(_device->object.priv); \ + struct { \ + struct nvkm_object object; \ + struct nvkm_device *device; \ + } *_udevice = _device->object.priv; \ + _udevice->device; \ }) #define nvxx_bios(a) nvxx_device(a)->bios #define nvxx_fb(a) nvxx_device(a)->fb diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 1d72d670bed2..8ef8058ed031 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -1,70 +1,55 @@ #ifndef __NVKM_DEVICE_H__ #define __NVKM_DEVICE_H__ -#include #include +#include enum nvkm_devidx { - NVDEV_SUBDEV_VBIOS, - - /* All subdevs from DEVINIT to DEVINIT_LAST will be created before - * *any* of them are initialised. This subdev category is used - * for any subdevs that the VBIOS init table parsing may call out - * to during POST. - */ - NVDEV_SUBDEV_DEVINIT, - NVDEV_SUBDEV_IBUS, - NVDEV_SUBDEV_GPIO, - NVDEV_SUBDEV_I2C, - NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C, - - /* This grouping of subdevs are initialised right after they've - * been created, and are allowed to assume any subdevs in the - * list above them exist and have been initialised. - */ - NVDEV_SUBDEV_FUSE, - NVDEV_SUBDEV_MXM, - NVDEV_SUBDEV_MC, - NVDEV_SUBDEV_BUS, - NVDEV_SUBDEV_TIMER, - NVDEV_SUBDEV_FB, - NVDEV_SUBDEV_LTC, - NVDEV_SUBDEV_INSTMEM, - NVDEV_SUBDEV_MMU, - NVDEV_SUBDEV_BAR, - NVDEV_SUBDEV_PMU, - NVDEV_SUBDEV_VOLT, - NVDEV_SUBDEV_THERM, - NVDEV_SUBDEV_CLK, - - NVDEV_ENGINE_FIRST, - NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, - NVDEV_ENGINE_IFB, - NVDEV_ENGINE_FIFO, - NVDEV_ENGINE_SW, - NVDEV_ENGINE_GR, - NVDEV_ENGINE_MPEG, - NVDEV_ENGINE_ME, - NVDEV_ENGINE_VP, - NVDEV_ENGINE_CIPHER, - NVDEV_ENGINE_BSP, - NVDEV_ENGINE_MSPPP, - NVDEV_ENGINE_CE0, - NVDEV_ENGINE_CE1, - NVDEV_ENGINE_CE2, - NVDEV_ENGINE_VIC, - NVDEV_ENGINE_MSENC, - NVDEV_ENGINE_DISP, - NVDEV_ENGINE_PM, - NVDEV_ENGINE_MSVLD, - NVDEV_ENGINE_SEC, - NVDEV_ENGINE_MSPDEC, - - NVDEV_SUBDEV_NR, + NVKM_SUBDEV_VBIOS, + NVKM_SUBDEV_DEVINIT, + NVKM_SUBDEV_IBUS, + NVKM_SUBDEV_GPIO, + NVKM_SUBDEV_I2C, + NVKM_SUBDEV_FUSE, + NVKM_SUBDEV_MXM, + NVKM_SUBDEV_MC, + NVKM_SUBDEV_BUS, + NVKM_SUBDEV_TIMER, + NVKM_SUBDEV_FB, + NVKM_SUBDEV_LTC, + NVKM_SUBDEV_INSTMEM, + NVKM_SUBDEV_MMU, + NVKM_SUBDEV_BAR, + NVKM_SUBDEV_PMU, + NVKM_SUBDEV_VOLT, + NVKM_SUBDEV_THERM, + NVKM_SUBDEV_CLK, + + NVKM_ENGINE_DMAOBJ, + NVKM_ENGINE_IFB, + NVKM_ENGINE_FIFO, + NVKM_ENGINE_SW, + NVKM_ENGINE_GR, + NVKM_ENGINE_MPEG, + NVKM_ENGINE_ME, + NVKM_ENGINE_VP, + NVKM_ENGINE_CIPHER, + NVKM_ENGINE_BSP, + NVKM_ENGINE_MSPPP, + NVKM_ENGINE_CE0, + NVKM_ENGINE_CE1, + NVKM_ENGINE_CE2, + NVKM_ENGINE_VIC, + NVKM_ENGINE_MSENC, + NVKM_ENGINE_DISP, + NVKM_ENGINE_PM, + NVKM_ENGINE_MSVLD, + NVKM_ENGINE_SEC, + NVKM_ENGINE_MSPDEC, + + NVKM_SUBDEV_NR, }; struct nvkm_device { - struct nvkm_engine engine; - const struct nvkm_device_func *func; const struct nvkm_device_quirk *quirk; struct device *dev; @@ -85,6 +70,7 @@ struct nvkm_device { struct nvkm_event event; u64 disable_mask; + u32 debug; const struct nvkm_device_chip *chip; enum { @@ -103,8 +89,6 @@ struct nvkm_device { u8 chiprev; u32 crystal; - struct nvkm_oclass *oclass[NVDEV_SUBDEV_NR]; - struct { struct notifier_block nb; } acpi; @@ -227,8 +211,6 @@ int nvkm_device_list(u64 *name, int size); _temp; \ }) -struct nvkm_device *nv_device(void *obj); - static inline bool nv_device_match(struct nvkm_device *device, u16 dev, u16 ven, u16 sub) { @@ -285,7 +267,7 @@ extern const struct nvkm_sclass nvkm_udevice_sclass; /* device logging */ #define nvdev_printk_(d,l,p,f,a...) do { \ struct nvkm_device *_device = (d); \ - if (_device->engine.subdev.debug >= (l)) \ + if (_device->debug >= (l)) \ dev_##p(_device->dev, f, ##a); \ } while(0) #define nvdev_printk(d,l,p,f,a...) nvdev_printk_((d), NV_DBG_##l, p, f, ##a) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h index 8c47ab210c06..48bf128456a1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/engine.h @@ -1,24 +1,16 @@ #ifndef __NVKM_ENGINE_H__ #define __NVKM_ENGINE_H__ +#define nvkm_engine(p) container_of((p), struct nvkm_engine, subdev) #include -struct nvkm_device_oclass; /*XXX: DEV!ENG */ struct nvkm_fifo_chan; struct nvkm_fb_tile; -#define NV_ENGINE_(eng,var) (((var) << 8) | (eng)) -#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var)) - struct nvkm_engine { - struct nvkm_subdev subdev; const struct nvkm_engine_func *func; + struct nvkm_subdev subdev; + spinlock_t lock; int usecount; - - struct nvkm_oclass *cclass; - struct nvkm_oclass *sclass; - - struct list_head contexts; - spinlock_t lock; }; struct nvkm_engine_func { @@ -54,42 +46,4 @@ int nvkm_engine_new_(const struct nvkm_engine_func *, struct nvkm_device *, struct nvkm_engine *nvkm_engine_ref(struct nvkm_engine *); void nvkm_engine_unref(struct nvkm_engine **); void nvkm_engine_tile(struct nvkm_engine *, int region); - -static inline struct nvkm_engine * -nv_engine(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - BUG_ON(!nv_iclass(obj, NV_ENGINE_CLASS)); -#endif - return obj; -} - -static inline int -nv_engidx(struct nvkm_engine *engine) -{ - return nv_subidx(&engine->subdev); -} - -struct nvkm_engine *nvkm_engine(void *obj, int idx); - -#define nvkm_engine_create(p,e,c,d,i,f,r) \ - nvkm_engine_create_((p), (e), (c), (d), (i), (f), \ - sizeof(**r),(void **)r) - -#define nvkm_engine_destroy(p) \ - nvkm_subdev_destroy(&(p)->subdev) -#define nvkm_engine_init_old(p) \ - nvkm_subdev_init_old(&(p)->subdev) -#define nvkm_engine_fini_old(p,s) \ - nvkm_subdev_fini_old(&(p)->subdev, (s)) - -int nvkm_engine_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, bool, const char *, - const char *, int, void **); - -#define _nvkm_engine_dtor _nvkm_subdev_dtor -#define _nvkm_engine_init _nvkm_subdev_init -#define _nvkm_engine_fini _nvkm_subdev_fini - -#include #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h index d171535b8eef..d4f56eafb073 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/gpuobj.h @@ -30,44 +30,11 @@ struct nvkm_gpuobj_func { void (*wr32)(struct nvkm_gpuobj *, u32 offset, u32 data); }; -int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero, - struct nvkm_gpuobj *parent, struct nvkm_gpuobj **); +int nvkm_gpuobj_new(struct nvkm_device *, u32 size, int align, bool zero, + struct nvkm_gpuobj *parent, struct nvkm_gpuobj **); void nvkm_gpuobj_del(struct nvkm_gpuobj **); - -static inline struct nvkm_gpuobj * -nv_gpuobj(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - BUG_ON(!nv_iclass(obj, NV_GPUOBJ_CLASS)); -#endif - return obj; -} - -#define nvkm_gpuobj_create(p,e,c,v,g,s,a,f,d) \ - nvkm_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \ - sizeof(**d), (void **)d) -#define nvkm_gpuobj_init(p) _nvkm_object_init(&(p)->object) -#define nvkm_gpuobj_fini(p,s) _nvkm_object_fini(&(p)->object, (s)) -int nvkm_gpuobj_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, u32 pclass, - struct nvkm_object *, u32 size, u32 align, - u32 flags, int length, void **); -void nvkm_gpuobj_destroy(struct nvkm_gpuobj *); - int nvkm_gpuobj_wrap(struct nvkm_memory *, struct nvkm_gpuobj **); int nvkm_gpuobj_map(struct nvkm_gpuobj *, struct nvkm_vm *, u32 access, struct nvkm_vma *); void nvkm_gpuobj_unmap(struct nvkm_vma *); - -static inline void -nvkm_gpuobj_ref(struct nvkm_gpuobj *obj, struct nvkm_gpuobj **ref) -{ - nvkm_object_ref(&obj->object, (struct nvkm_object **)ref); -} - -void _nvkm_gpuobj_dtor(struct nvkm_object *); -int _nvkm_gpuobj_init(struct nvkm_object *); -int _nvkm_gpuobj_fini(struct nvkm_object *, bool); -u32 _nvkm_gpuobj_rd32(struct nvkm_object *, u64); -void _nvkm_gpuobj_wr32(struct nvkm_object *, u64, u32); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h index 7befea315c98..b4b822f6155c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/object.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/object.h @@ -4,32 +4,18 @@ #include struct nvkm_event; struct nvkm_gpuobj; - -#define NV_PARENT_CLASS 0x80000000 -#define NV_NAMEDB_CLASS 0x40000000 -#define NV_CLIENT_CLASS 0x20000000 -#define NV_SUBDEV_CLASS 0x10000000 -#define NV_ENGINE_CLASS 0x08000000 -#define NV_MEMOBJ_CLASS 0x04000000 -#define NV_GPUOBJ_CLASS 0x02000000 -#define NV_ENGCTX_CLASS 0x01000000 +struct nvkm_oclass; struct nvkm_object { const struct nvkm_object_func *func; struct nvkm_client *client; struct nvkm_engine *engine; - u32 oclass_name; + u32 oclass; u32 handle; struct nvkm_object *parent; - struct nvkm_oclass *oclass; u32 pclass; atomic_t refcount; atomic_t usecount; -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA -#define NVKM_OBJECT_MAGIC 0x75ef0bad - struct list_head list; - u32 _magic; -#endif }; struct nvkm_object_func { @@ -71,32 +57,6 @@ int nvkm_object_wr32(struct nvkm_object *, u64 addr, u32 data); int nvkm_object_bind(struct nvkm_object *, struct nvkm_gpuobj *, int align, struct nvkm_gpuobj **); -static inline struct nvkm_object * -nv_object(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - if (likely(obj)) { - struct nvkm_object *object = obj; - BUG_ON(object->_magic != NVKM_OBJECT_MAGIC); - } -#endif - return obj; -} - -#define nvkm_object_create(p,e,c,s,d) \ - nvkm_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d) -int nvkm_object_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, u32, int size, void **); -void nvkm_object_destroy(struct nvkm_object *); -int _nvkm_object_init(struct nvkm_object *); -int _nvkm_object_fini(struct nvkm_object *, bool suspend); - -int _nvkm_object_ctor(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); - -extern struct nvkm_ofuncs nvkm_object_ofuncs; - struct nvkm_sclass { int minver; int maxver; @@ -107,60 +67,18 @@ struct nvkm_sclass { }; struct nvkm_oclass { - s32 handle; - struct nvkm_ofuncs * const ofuncs; - int (*ctor)(const struct nvkm_oclass *, void *data, u32 size, struct nvkm_object **); struct nvkm_sclass base; const void *priv; const void *engn; + s32 handle; u64 object; struct nvkm_client *client; struct nvkm_object *parent; struct nvkm_engine *engine; }; -#define nv_oclass(o) nv_object(o)->oclass -#define nv_hclass(o) nv_oclass(o)->handle -#define nv_iclass(o,i) (nv_object(o)->pclass & (i)) -#define nv_mclass(o) nv_oclass(o)->handle - -static inline struct nvkm_object * -nv_pclass(struct nvkm_object *parent, u32 oclass) -{ - while (parent && !nv_iclass(parent, oclass)) - parent = parent->parent; - return parent; -} - -struct nvkm_ofuncs { - int (*ctor)(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *data, u32 size, - struct nvkm_object **); - void (*dtor)(struct nvkm_object *); - int (*init)(struct nvkm_object *); - int (*fini)(struct nvkm_object *, bool suspend); - int (*mthd)(struct nvkm_object *, u32, void *, u32); - int (*ntfy)(struct nvkm_object *, u32, struct nvkm_event **); - int (* map)(struct nvkm_object *, u64 *, u32 *); - u8 (*rd08)(struct nvkm_object *, u64 offset); - u16 (*rd16)(struct nvkm_object *, u64 offset); - u32 (*rd32)(struct nvkm_object *, u64 offset); - void (*wr08)(struct nvkm_object *, u64 offset, u8 data); - void (*wr16)(struct nvkm_object *, u64 offset, u16 data); - void (*wr32)(struct nvkm_object *, u64 offset, u32 data); -}; - -static inline struct nvkm_ofuncs * -nv_ofuncs(void *obj) -{ - return nv_oclass(obj)->ofuncs; -} - -int nvkm_object_old(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, void *, u32, - struct nvkm_object **); void nvkm_object_ref(struct nvkm_object *, struct nvkm_object **); int nvkm_object_inc(struct nvkm_object *); int nvkm_object_dec(struct nvkm_object *, bool suspend); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h index 01f2f71e6112..3b5dc9c63069 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/subdev.h @@ -1,23 +1,16 @@ #ifndef __NVKM_SUBDEV_H__ #define __NVKM_SUBDEV_H__ -#include - -#define NV_SUBDEV_(sub,var) (((var) << 8) | (sub)) -#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var)) +#include struct nvkm_subdev { - struct nvkm_object object; const struct nvkm_subdev_func *func; struct nvkm_device *device; - int index; + enum nvkm_devidx index; u32 pmc_enable; - struct mutex mutex; u32 debug; - bool oneinit; - void (*intr)(struct nvkm_subdev *); - u32 unit; + bool oneinit; }; struct nvkm_subdev_func { @@ -29,7 +22,7 @@ struct nvkm_subdev_func { void (*intr)(struct nvkm_subdev *); }; -extern const char *nvkm_subdev_name[64]; +extern const char *nvkm_subdev_name[NVKM_SUBDEV_NR]; void nvkm_subdev_ctor(const struct nvkm_subdev_func *, struct nvkm_device *, int index, u32 pmc_enable, struct nvkm_subdev *); void nvkm_subdev_del(struct nvkm_subdev **); @@ -38,40 +31,6 @@ int nvkm_subdev_init(struct nvkm_subdev *); int nvkm_subdev_fini(struct nvkm_subdev *, bool suspend); void nvkm_subdev_intr(struct nvkm_subdev *); -static inline struct nvkm_subdev * -nv_subdev(void *obj) -{ -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - BUG_ON(!nv_iclass(obj, NV_SUBDEV_CLASS)); -#endif - return obj; -} - -static inline int -nv_subidx(struct nvkm_subdev *subdev) -{ - return nv_hclass(subdev) & 0xff; -} - -struct nvkm_subdev *nvkm_subdev(void *obj, int idx); - -#define nvkm_subdev_create(p,e,o,v,s,f,d) \ - nvkm_subdev_create_((p), (e), (o), (v), (s), (f), \ - sizeof(**d),(void **)d) - -int nvkm_subdev_create_(struct nvkm_object *, struct nvkm_object *, - struct nvkm_oclass *, u32 pclass, - const char *sname, const char *fname, - int size, void **); -void nvkm_subdev_destroy(struct nvkm_subdev *); -int nvkm_subdev_init_old(struct nvkm_subdev *); -int nvkm_subdev_fini_old(struct nvkm_subdev *, bool suspend); -void nvkm_subdev_reset(struct nvkm_object *); - -void _nvkm_subdev_dtor(struct nvkm_object *); -int _nvkm_subdev_init(struct nvkm_object *); -int _nvkm_subdev_fini(struct nvkm_object *, bool suspend); - /* subdev logging */ #define nvkm_printk_(s,l,p,f,a...) do { \ struct nvkm_subdev *_subdev = (s); \ @@ -88,6 +47,4 @@ int _nvkm_subdev_fini(struct nvkm_object *, bool suspend); #define nvkm_debug(s,f,a...) nvkm_printk((s), DEBUG, info, f, ##a) #define nvkm_trace(s,f,a...) nvkm_printk((s), TRACE, info, f, ##a) #define nvkm_spam(s,f,a...) nvkm_printk((s), SPAM, dbg, f, ##a) - -#include #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h index 84cc3e9cfed7..9e6644955d19 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/fifo.h @@ -26,11 +26,9 @@ struct nvkm_fifo_chan { u64 addr; u32 size; - struct nvkm_fifo_engn engn[NVDEV_SUBDEV_NR]; + struct nvkm_fifo_engn engn[NVKM_SUBDEV_NR]; }; -extern const struct nvkm_object_func nvkm_fifo_chan_func; - struct nvkm_fifo { const struct nvkm_fifo_func *func; struct nvkm_engine engine; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h index 26c77aac4be4..dcd3deff27a4 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -32,7 +32,7 @@ struct nvkm_vm { struct kref refcount; struct list_head pgd_list; - atomic_t engref[NVDEV_SUBDEV_NR]; + atomic_t engref[NVKM_SUBDEV_NR]; struct nvkm_vm_pgt *pgt; u32 fpde; diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engine.c b/drivers/gpu/drm/nouveau/nvkm/core/engine.c index 3fef9cc34345..8a7bae7bd995 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engine.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engine.c @@ -67,29 +67,26 @@ nvkm_engine_tile(struct nvkm_engine *engine, int region) } static void -nvkm_engine_intr(struct nvkm_subdev *obj) +nvkm_engine_intr(struct nvkm_subdev *subdev) { - struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); + struct nvkm_engine *engine = nvkm_engine(subdev); if (engine->func->intr) engine->func->intr(engine); } static int -nvkm_engine_fini(struct nvkm_subdev *obj, bool suspend) +nvkm_engine_fini(struct nvkm_subdev *subdev, bool suspend) { - struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); - if (engine->subdev.object.oclass) - return engine->subdev.object.oclass->ofuncs->fini(&engine->subdev.object, suspend); + struct nvkm_engine *engine = nvkm_engine(subdev); if (engine->func->fini) return engine->func->fini(engine, suspend); return 0; } static int -nvkm_engine_init(struct nvkm_subdev *obj) +nvkm_engine_init(struct nvkm_subdev *subdev) { - struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); - struct nvkm_subdev *subdev = &engine->subdev; + struct nvkm_engine *engine = nvkm_engine(subdev); struct nvkm_fb *fb = subdev->device->fb; int ret = 0, i; s64 time; @@ -99,9 +96,6 @@ nvkm_engine_init(struct nvkm_subdev *obj) return ret; } - if (engine->subdev.object.oclass) - return engine->subdev.object.oclass->ofuncs->init(&engine->subdev.object); - if (engine->func->oneinit && !engine->subdev.oneinit) { nvkm_trace(subdev, "one-time init running...\n"); time = ktime_to_us(ktime_get()); @@ -125,13 +119,9 @@ nvkm_engine_init(struct nvkm_subdev *obj) } static void * -nvkm_engine_dtor(struct nvkm_subdev *obj) +nvkm_engine_dtor(struct nvkm_subdev *subdev) { - struct nvkm_engine *engine = container_of(obj, typeof(*engine), subdev); - if (engine->subdev.object.oclass) { - engine->subdev.object.oclass->ofuncs->dtor(&engine->subdev.object); - return NULL; - } + struct nvkm_engine *engine = nvkm_engine(subdev); if (engine->func->dtor) return engine->func->dtor(engine); return engine; @@ -173,56 +163,3 @@ nvkm_engine_new_(const struct nvkm_engine_func *func, return nvkm_engine_ctor(func, device, index, pmc_enable, enable, *pengine); } - -struct nvkm_engine * -nvkm_engine(void *obj, int idx) -{ - obj = nvkm_subdev(obj, idx); - if (obj && nv_iclass(obj, NV_ENGINE_CLASS)) - return nv_engine(obj); - return NULL; -} - -int -nvkm_engine_create_(struct nvkm_object *parent, struct nvkm_object *engobj, - struct nvkm_oclass *oclass, bool enable, - const char *iname, const char *fname, - int length, void **pobject) -{ - struct nvkm_engine *engine; - int ret; - - ret = nvkm_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS, - iname, fname, length, pobject); - engine = *pobject; - if (ret) - return ret; - - if (parent) { - struct nvkm_device *device = nv_device(parent); - int engidx = nv_engidx(engine); - - if (device->disable_mask & (1ULL << engidx)) { - if (!nvkm_boolopt(device->cfgopt, iname, false)) { - nvkm_debug(&engine->subdev, - "engine disabled by hw/fw\n"); - return -ENODEV; - } - - nvkm_warn(&engine->subdev, - "ignoring hw/fw engine disable\n"); - } - - if (!nvkm_boolopt(device->cfgopt, iname, enable)) { - if (!enable) - nvkm_warn(&engine->subdev, - "disabled, %s=1 to enable\n", iname); - return -ENODEV; - } - } - - INIT_LIST_HEAD(&engine->contexts); - spin_lock_init(&engine->lock); - engine->subdev.func = &nvkm_engine_func; - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index b8fc539e0a99..c3a790eb8d6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -218,99 +218,6 @@ nvkm_gpuobj_new(struct nvkm_device *device, u32 size, int align, bool zero, return ret; } -void -nvkm_gpuobj_destroy(struct nvkm_gpuobj *gpuobj) -{ - if (gpuobj->node) - nvkm_mm_free(&gpuobj->parent->heap, &gpuobj->node); - - gpuobj->heap.block_size = 1; - nvkm_mm_fini(&gpuobj->heap); - - nvkm_memory_del(&gpuobj->memory); - nvkm_object_destroy(&gpuobj->object); -} - -#include - -int -nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 pclass, - struct nvkm_object *objgpu, u32 size, u32 align, u32 flags, - int length, void **pobject) -{ - struct nvkm_device *device = nv_device(parent); - struct nvkm_gpuobj *pargpu = NULL; - struct nvkm_gpuobj *gpuobj; - struct nvkm_object *object = objgpu; - const bool zero = (flags & NVOBJ_FLAG_ZERO_ALLOC); - int ret; - - *pobject = NULL; - - while (object && object->func != &nvkm_fifo_chan_func) - object = object->parent; - - if (object) { - struct nvkm_fifo_chan *chan = nvkm_fifo_chan(object); - pargpu = chan->inst; - } else - if (objgpu) { - while ((objgpu = nv_pclass(objgpu, NV_GPUOBJ_CLASS))) { - if (nv_gpuobj(objgpu)->heap.block_size) - break; - objgpu = objgpu->parent; - } - - if (WARN_ON(objgpu == NULL)) - return -EINVAL; - pargpu = nv_gpuobj(objgpu); - } - - ret = nvkm_object_create_(parent, engine, oclass, pclass | - NV_GPUOBJ_CLASS, length, pobject); - gpuobj = *pobject; - if (ret) - return ret; - - ret = nvkm_gpuobj_ctor(device, size, align, zero, pargpu, gpuobj); - if (!(flags & NVOBJ_FLAG_HEAP)) - gpuobj->heap.block_size = 0; - return ret; -} - -void -_nvkm_gpuobj_dtor(struct nvkm_object *object) -{ - nvkm_gpuobj_destroy(nv_gpuobj(object)); -} - -int -_nvkm_gpuobj_init(struct nvkm_object *object) -{ - return nvkm_gpuobj_init(nv_gpuobj(object)); -} - -int -_nvkm_gpuobj_fini(struct nvkm_object *object, bool suspend) -{ - return nvkm_gpuobj_fini(nv_gpuobj(object), suspend); -} - -u32 -_nvkm_gpuobj_rd32(struct nvkm_object *object, u64 addr) -{ - struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); - return nvkm_ro32(gpuobj, addr); -} - -void -_nvkm_gpuobj_wr32(struct nvkm_object *object, u64 addr, u32 data) -{ - struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); - nvkm_wo32(gpuobj, addr, data); -} - int nvkm_gpuobj_map(struct nvkm_gpuobj *gpuobj, struct nvkm_vm *vm, u32 access, struct nvkm_vma *vma) diff --git a/drivers/gpu/drm/nouveau/nvkm/core/object.c b/drivers/gpu/drm/nouveau/nvkm/core/object.c index 0680eae072cf..8976526b1c8f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/object.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/object.c @@ -27,11 +27,6 @@ int nvkm_object_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) { - if (object->oclass) { - if (object->oclass->ofuncs->mthd) - return object->oclass->ofuncs->mthd(object, mthd, data, size); - return -ENODEV; - } if (likely(object->func->mthd)) return object->func->mthd(object, mthd, data, size); return -ENODEV; @@ -41,11 +36,6 @@ int nvkm_object_ntfy(struct nvkm_object *object, u32 mthd, struct nvkm_event **pevent) { - if (object->oclass) { - if (object->oclass->ofuncs->ntfy) - return object->oclass->ofuncs->ntfy(object, mthd, pevent); - return -ENODEV; - } if (likely(object->func->ntfy)) return object->func->ntfy(object, mthd, pevent); return -ENODEV; @@ -54,11 +44,6 @@ nvkm_object_ntfy(struct nvkm_object *object, u32 mthd, int nvkm_object_map(struct nvkm_object *object, u64 *addr, u32 *size) { - if (object->oclass) { - if (object->oclass->ofuncs->map) - return object->oclass->ofuncs->map(object, addr, size); - return -ENODEV; - } if (likely(object->func->map)) return object->func->map(object, addr, size); return -ENODEV; @@ -67,14 +52,6 @@ nvkm_object_map(struct nvkm_object *object, u64 *addr, u32 *size) int nvkm_object_rd08(struct nvkm_object *object, u64 addr, u8 *data) { - if (object->oclass) { - if (object->oclass->ofuncs->rd08) { - *data = object->oclass->ofuncs->rd08(object, addr); - return 0; - } - *data = 0x00; - return -ENODEV; - } if (likely(object->func->rd08)) return object->func->rd08(object, addr, data); return -ENODEV; @@ -83,14 +60,6 @@ nvkm_object_rd08(struct nvkm_object *object, u64 addr, u8 *data) int nvkm_object_rd16(struct nvkm_object *object, u64 addr, u16 *data) { - if (object->oclass) { - if (object->oclass->ofuncs->rd16) { - *data = object->oclass->ofuncs->rd16(object, addr); - return 0; - } - *data = 0x0000; - return -ENODEV; - } if (likely(object->func->rd16)) return object->func->rd16(object, addr, data); return -ENODEV; @@ -99,14 +68,6 @@ nvkm_object_rd16(struct nvkm_object *object, u64 addr, u16 *data) int nvkm_object_rd32(struct nvkm_object *object, u64 addr, u32 *data) { - if (object->oclass) { - if (object->oclass->ofuncs->rd32) { - *data = object->oclass->ofuncs->rd32(object, addr); - return 0; - } - *data = 0x00000000; - return -ENODEV; - } if (likely(object->func->rd32)) return object->func->rd32(object, addr, data); return -ENODEV; @@ -115,13 +76,6 @@ nvkm_object_rd32(struct nvkm_object *object, u64 addr, u32 *data) int nvkm_object_wr08(struct nvkm_object *object, u64 addr, u8 data) { - if (object->oclass) { - if (object->oclass->ofuncs->wr08) { - object->oclass->ofuncs->wr08(object, addr, data); - return 0; - } - return -ENODEV; - } if (likely(object->func->wr08)) return object->func->wr08(object, addr, data); return -ENODEV; @@ -130,13 +84,6 @@ nvkm_object_wr08(struct nvkm_object *object, u64 addr, u8 data) int nvkm_object_wr16(struct nvkm_object *object, u64 addr, u16 data) { - if (object->oclass) { - if (object->oclass->ofuncs->wr16) { - object->oclass->ofuncs->wr16(object, addr, data); - return 0; - } - return -ENODEV; - } if (likely(object->func->wr16)) return object->func->wr16(object, addr, data); return -ENODEV; @@ -145,13 +92,6 @@ nvkm_object_wr16(struct nvkm_object *object, u64 addr, u16 data) int nvkm_object_wr32(struct nvkm_object *object, u64 addr, u32 data) { - if (object->oclass) { - if (object->oclass->ofuncs->wr32) { - object->oclass->ofuncs->wr32(object, addr, data); - return 0; - } - return -ENODEV; - } if (likely(object->func->wr32)) return object->func->wr32(object, addr, data); return -ENODEV; @@ -161,8 +101,6 @@ int nvkm_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *gpuobj, int align, struct nvkm_gpuobj **pgpuobj) { - if (object->oclass) - return -ENODEV; if (object->func->bind) return object->func->bind(object, gpuobj, align, pgpuobj); return -ENODEV; @@ -171,8 +109,6 @@ nvkm_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *gpuobj, int nvkm_object_fini(struct nvkm_object *object, bool suspend) { - if (object->oclass) - return object->oclass->ofuncs->fini(object, suspend); if (object->func->fini) return object->func->fini(object, suspend); return 0; @@ -181,8 +117,6 @@ nvkm_object_fini(struct nvkm_object *object, bool suspend) int nvkm_object_init(struct nvkm_object *object) { - if (object->oclass) - return object->oclass->ofuncs->init(object); if (object->func->init) return object->func->init(object); return 0; @@ -193,11 +127,6 @@ nvkm_object_del(struct nvkm_object **pobject) { struct nvkm_object *object = *pobject; - if (object && object->oclass) { - object->oclass->ofuncs->dtor(object); - return; - } - if (object && !WARN_ON(!object->func)) { if (object->func->dtor) *pobject = object->func->dtor(object); @@ -214,14 +143,11 @@ nvkm_object_ctor(const struct nvkm_object_func *func, object->func = func; object->client = oclass->client; object->engine = nvkm_engine_ref(oclass->engine); - object->oclass_name = oclass->base.oclass; + object->oclass = oclass->base.oclass; object->handle = oclass->handle; object->parent = oclass->parent; atomic_set(&object->refcount, 1); atomic_set(&object->usecount, 0); -#ifdef NVKM_OBJECT_MAGIC - object->_magic = NVKM_OBJECT_MAGIC; -#endif } int @@ -251,97 +177,6 @@ nvkm_object_new(const struct nvkm_oclass *oclass, void *data, u32 size, return nvkm_object_new_(func, oclass, data, size, pobject); } -int -nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engobj, - struct nvkm_oclass *oclass, u32 pclass, - int size, void **pobject) -{ - struct nvkm_engine *engine = engobj ? nv_engine(engobj) : NULL; - struct nvkm_object *object; - - object = *pobject = kzalloc(size, GFP_KERNEL); - if (!object) - return -ENOMEM; - - nvkm_object_ref(parent, &object->parent); - object->engine = nvkm_engine_ref(engine); - object->oclass = oclass; - object->pclass = pclass; - atomic_set(&object->refcount, 1); - atomic_set(&object->usecount, 0); - -#ifdef NVKM_OBJECT_MAGIC - object->_magic = NVKM_OBJECT_MAGIC; -#endif - return 0; -} - -int -_nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - if (size != 0) - return -ENOSYS; - return nvkm_object_create(parent, engine, oclass, 0, pobject); -} - -void -nvkm_object_destroy(struct nvkm_object *object) -{ - nvkm_engine_unref(&object->engine); - nvkm_object_ref(NULL, &object->parent); - kfree(object); -} - -int -_nvkm_object_init(struct nvkm_object *object) -{ - return 0; -} - -int -_nvkm_object_fini(struct nvkm_object *object, bool suspend) -{ - return 0; -} - -struct nvkm_ofuncs -nvkm_object_ofuncs = { - .ctor = _nvkm_object_ctor, - .dtor = nvkm_object_destroy, - .init = _nvkm_object_init, - .fini = _nvkm_object_fini, -}; - -int -nvkm_object_old(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, void *data, u32 size, - struct nvkm_object **pobject) -{ - struct nvkm_ofuncs *ofuncs = oclass->ofuncs; - struct nvkm_object *object = NULL; - int ret; - - ret = ofuncs->ctor(parent, engine, oclass, data, size, &object); - *pobject = object; - if (ret < 0) { - if (object) { - ofuncs->dtor(object); - *pobject = NULL; - } - - return ret; - } - - if (ret == 0) { - if (!nv_iclass(object, NV_SUBDEV_CLASS)) - atomic_set(&object->refcount, 1); - } - - return 0; -} - void nvkm_object_ref(struct nvkm_object *obj, struct nvkm_object **ref) { diff --git a/drivers/gpu/drm/nouveau/nvkm/core/oproxy.c b/drivers/gpu/drm/nouveau/nvkm/core/oproxy.c index b2b743587168..f32aa0dc425b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/oproxy.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/oproxy.c @@ -92,8 +92,6 @@ nvkm_oproxy_sclass(struct nvkm_object *object, int index, { struct nvkm_oproxy *oproxy = nvkm_oproxy(object); oclass->parent = oproxy->object; - if (oproxy->object->oclass) - return -ENOSYS; if (!oproxy->object->func->sclass) return -ENODEV; return oproxy->object->func->sclass(oproxy->object, index, oclass); diff --git a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c index 307d53269625..3216e157a8a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/ramht.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/ramht.c @@ -67,40 +67,27 @@ nvkm_ramht_update(struct nvkm_ramht *ramht, int co, struct nvkm_object *object, data->chid = chid; data->handle = handle; - if (!object) { - inst = 0; - goto done; - } - - if (nv_iclass(object, NV_GPUOBJ_CLASS)) { - struct nvkm_gpuobj *gpuobj = nv_gpuobj(object); - if (ramht->device->card_type >= NV_50) - inst = gpuobj->node->offset; - else - inst = gpuobj->addr; - goto done; - } + if (object) { + ret = nvkm_object_bind(object, ramht->parent, 16, &data->inst); + if (ret) { + if (ret != -ENODEV) { + data->chid = -1; + return ret; + } + data->inst = NULL; + } - ret = nvkm_object_bind(object, ramht->parent, 16, &data->inst); - if (ret) { - if (ret != -ENODEV) { - data->chid = -1; - return ret; + if (data->inst) { + if (ramht->device->card_type >= NV_50) + inst = data->inst->node->offset; + else + inst = data->inst->addr; } - data->inst = NULL; - } - if (data->inst) { - if (ramht->device->card_type >= NV_50) - inst = data->inst->node->offset; - else - inst = data->inst->addr; + if (addr < 0) context |= inst << -addr; + else context |= inst >> addr; } -done: - if (addr < 0) context |= inst << -addr; - else context |= inst >> addr; - nvkm_kmap(ramht->gpuobj); nvkm_wo32(ramht->gpuobj, (co << 3) + 0, handle); nvkm_wo32(ramht->gpuobj, (co << 3) + 4, context); diff --git a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c index b0647c233478..65e0cb35e1a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/subdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/subdev.c @@ -25,61 +25,55 @@ #include #include -static struct lock_class_key nvkm_subdev_lock_class[NVDEV_SUBDEV_NR]; +static struct lock_class_key nvkm_subdev_lock_class[NVKM_SUBDEV_NR]; const char * -nvkm_subdev_name[64] = { - [NVDEV_SUBDEV_BAR ] = "bar", - [NVDEV_SUBDEV_VBIOS ] = "bios", - [NVDEV_SUBDEV_BUS ] = "bus", - [NVDEV_SUBDEV_CLK ] = "clk", - [NVDEV_SUBDEV_DEVINIT] = "devinit", - [NVDEV_SUBDEV_FB ] = "fb", - [NVDEV_SUBDEV_FUSE ] = "fuse", - [NVDEV_SUBDEV_GPIO ] = "gpio", - [NVDEV_SUBDEV_I2C ] = "i2c", - [NVDEV_SUBDEV_IBUS ] = "priv", - [NVDEV_SUBDEV_INSTMEM] = "imem", - [NVDEV_SUBDEV_LTC ] = "ltc", - [NVDEV_SUBDEV_MC ] = "mc", - [NVDEV_SUBDEV_MMU ] = "mmu", - [NVDEV_SUBDEV_MXM ] = "mxm", - [NVDEV_SUBDEV_PMU ] = "pmu", - [NVDEV_SUBDEV_THERM ] = "therm", - [NVDEV_SUBDEV_TIMER ] = "tmr", - [NVDEV_SUBDEV_VOLT ] = "volt", - [NVDEV_ENGINE_BSP ] = "bsp", - [NVDEV_ENGINE_CE0 ] = "ce0", - [NVDEV_ENGINE_CE1 ] = "ce1", - [NVDEV_ENGINE_CE2 ] = "ce2", - [NVDEV_ENGINE_CIPHER ] = "cipher", - [NVDEV_ENGINE_DISP ] = "disp", - [NVDEV_ENGINE_DMAOBJ ] = "dma", - [NVDEV_ENGINE_FIFO ] = "fifo", - [NVDEV_ENGINE_GR ] = "gr", - [NVDEV_ENGINE_IFB ] = "ifb", - [NVDEV_ENGINE_ME ] = "me", - [NVDEV_ENGINE_MPEG ] = "mpeg", - [NVDEV_ENGINE_MSENC ] = "msenc", - [NVDEV_ENGINE_MSPDEC ] = "mspdec", - [NVDEV_ENGINE_MSPPP ] = "msppp", - [NVDEV_ENGINE_MSVLD ] = "msvld", - [NVDEV_ENGINE_PM ] = "pm", - [NVDEV_ENGINE_SEC ] = "sec", - [NVDEV_ENGINE_SW ] = "sw", - [NVDEV_ENGINE_VIC ] = "vic", - [NVDEV_ENGINE_VP ] = "vp", +nvkm_subdev_name[NVKM_SUBDEV_NR] = { + [NVKM_SUBDEV_BAR ] = "bar", + [NVKM_SUBDEV_VBIOS ] = "bios", + [NVKM_SUBDEV_BUS ] = "bus", + [NVKM_SUBDEV_CLK ] = "clk", + [NVKM_SUBDEV_DEVINIT] = "devinit", + [NVKM_SUBDEV_FB ] = "fb", + [NVKM_SUBDEV_FUSE ] = "fuse", + [NVKM_SUBDEV_GPIO ] = "gpio", + [NVKM_SUBDEV_I2C ] = "i2c", + [NVKM_SUBDEV_IBUS ] = "priv", + [NVKM_SUBDEV_INSTMEM] = "imem", + [NVKM_SUBDEV_LTC ] = "ltc", + [NVKM_SUBDEV_MC ] = "mc", + [NVKM_SUBDEV_MMU ] = "mmu", + [NVKM_SUBDEV_MXM ] = "mxm", + [NVKM_SUBDEV_PMU ] = "pmu", + [NVKM_SUBDEV_THERM ] = "therm", + [NVKM_SUBDEV_TIMER ] = "tmr", + [NVKM_SUBDEV_VOLT ] = "volt", + [NVKM_ENGINE_BSP ] = "bsp", + [NVKM_ENGINE_CE0 ] = "ce0", + [NVKM_ENGINE_CE1 ] = "ce1", + [NVKM_ENGINE_CE2 ] = "ce2", + [NVKM_ENGINE_CIPHER ] = "cipher", + [NVKM_ENGINE_DISP ] = "disp", + [NVKM_ENGINE_DMAOBJ ] = "dma", + [NVKM_ENGINE_FIFO ] = "fifo", + [NVKM_ENGINE_GR ] = "gr", + [NVKM_ENGINE_IFB ] = "ifb", + [NVKM_ENGINE_ME ] = "me", + [NVKM_ENGINE_MPEG ] = "mpeg", + [NVKM_ENGINE_MSENC ] = "msenc", + [NVKM_ENGINE_MSPDEC ] = "mspdec", + [NVKM_ENGINE_MSPPP ] = "msppp", + [NVKM_ENGINE_MSVLD ] = "msvld", + [NVKM_ENGINE_PM ] = "pm", + [NVKM_ENGINE_SEC ] = "sec", + [NVKM_ENGINE_SW ] = "sw", + [NVKM_ENGINE_VIC ] = "vic", + [NVKM_ENGINE_VP ] = "vp", }; void nvkm_subdev_intr(struct nvkm_subdev *subdev) { - if (subdev->object.oclass) { - if (subdev->intr) - subdev->intr(subdev); - return; - } - if (subdev->func->intr) subdev->func->intr(subdev); } @@ -91,18 +85,10 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) const char *action = suspend ? "suspend" : "fini"; u32 pmc_enable = subdev->pmc_enable; s64 time; - int ret; nvkm_trace(subdev, "%s running...\n", action); time = ktime_to_us(ktime_get()); - if (!subdev->func) { - ret = subdev->object.oclass->ofuncs->fini(&subdev->object, suspend); - if (ret) - return ret; - goto done; - } - if (subdev->func->fini) { int ret = subdev->func->fini(subdev, suspend); if (ret) { @@ -118,7 +104,6 @@ nvkm_subdev_fini(struct nvkm_subdev *subdev, bool suspend) nvkm_rd32(device, 0x000200); } -done: time = ktime_to_us(ktime_get()) - time; nvkm_trace(subdev, "%s completed in %lldus\n", action, time); return 0; @@ -132,7 +117,7 @@ nvkm_subdev_preinit(struct nvkm_subdev *subdev) nvkm_trace(subdev, "preinit running...\n"); time = ktime_to_us(ktime_get()); - if (!subdev->object.oclass && subdev->func->preinit) { + if (subdev->func->preinit) { int ret = subdev->func->preinit(subdev); if (ret) { nvkm_error(subdev, "preinit failed, %d\n", ret); @@ -154,13 +139,6 @@ nvkm_subdev_init(struct nvkm_subdev *subdev) nvkm_trace(subdev, "init running...\n"); time = ktime_to_us(ktime_get()); - if (!subdev->func) { - ret = subdev->object.oclass->ofuncs->init(&subdev->object); - if (ret) - return ret; - goto done; - } - if (subdev->func->oneinit && !subdev->oneinit) { s64 time; nvkm_trace(subdev, "one-time init running...\n"); @@ -184,7 +162,6 @@ nvkm_subdev_init(struct nvkm_subdev *subdev) } } -done: time = ktime_to_us(ktime_get()) - time; nvkm_trace(subdev, "init completed in %lldus\n", time); return 0; @@ -196,11 +173,6 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) struct nvkm_subdev *subdev = *psubdev; s64 time; - if (subdev && subdev->object.oclass) { - subdev->object.oclass->ofuncs->dtor(&subdev->object); - return; - } - if (subdev && !WARN_ON(!subdev->func)) { nvkm_trace(subdev, "destroy running...\n"); time = ktime_to_us(ktime_get()); @@ -213,18 +185,12 @@ nvkm_subdev_del(struct nvkm_subdev **psubdev) } } -static const struct nvkm_object_func -nvkm_subdev_func = { -}; - void nvkm_subdev_ctor(const struct nvkm_subdev_func *func, struct nvkm_device *device, int index, u32 pmc_enable, struct nvkm_subdev *subdev) { const char *name = nvkm_subdev_name[index]; - struct nvkm_oclass hack = {}; - nvkm_object_ctor(&nvkm_subdev_func, &hack, &subdev->object); subdev->func = func; subdev->device = device; subdev->index = index; @@ -233,106 +199,3 @@ nvkm_subdev_ctor(const struct nvkm_subdev_func *func, __mutex_init(&subdev->mutex, name, &nvkm_subdev_lock_class[index]); subdev->debug = nvkm_dbgopt(device->dbgopt, name); } - -struct nvkm_subdev * -nvkm_subdev(void *obj, int idx) -{ - struct nvkm_object *object = nv_object(obj); - while (object && !nv_iclass(object, NV_SUBDEV_CLASS)) - object = object->parent; - if (object == NULL || !object->parent || nv_subidx(nv_subdev(object)) != idx) { - struct nvkm_device *device = nv_device(obj); - return nvkm_device_subdev(device, idx); - } - return object ? nv_subdev(object) : NULL; -} - -void -nvkm_subdev_reset(struct nvkm_object *obj) -{ - struct nvkm_subdev *subdev = container_of(obj, typeof(*subdev), object); - nvkm_trace(subdev, "resetting...\n"); - nvkm_object_fini(&subdev->object, false); - nvkm_trace(subdev, "reset\n"); -} - -int -nvkm_subdev_init_old(struct nvkm_subdev *subdev) -{ - int ret = _nvkm_object_init(&subdev->object); - if (ret) - return ret; - - nvkm_subdev_reset(&subdev->object); - return 0; -} - -int -_nvkm_subdev_init(struct nvkm_object *object) -{ - struct nvkm_subdev *subdev = (void *)object; - return nvkm_subdev_init_old(subdev); -} - -int -nvkm_subdev_fini_old(struct nvkm_subdev *subdev, bool suspend) -{ - struct nvkm_device *device = subdev->device; - - if (subdev->unit) { - nvkm_mask(device, 0x000200, subdev->unit, 0x00000000); - nvkm_mask(device, 0x000200, subdev->unit, subdev->unit); - } - - return _nvkm_object_fini(&subdev->object, suspend); -} - -int -_nvkm_subdev_fini(struct nvkm_object *object, bool suspend) -{ - struct nvkm_subdev *subdev = (void *)object; - return nvkm_subdev_fini_old(subdev, suspend); -} - -void -nvkm_subdev_destroy(struct nvkm_subdev *subdev) -{ - nvkm_object_destroy(&subdev->object); -} - -void -_nvkm_subdev_dtor(struct nvkm_object *object) -{ - nvkm_subdev_destroy(nv_subdev(object)); -} - -int -nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine, - struct nvkm_oclass *oclass, u32 pclass, - const char *subname, const char *sysname, - int size, void **pobject) -{ - const int subidx = oclass->handle & 0xff; - const char *name = nvkm_subdev_name[subidx]; - struct nvkm_subdev *subdev; - int ret; - - ret = nvkm_object_create_(parent, engine, oclass, pclass | - NV_SUBDEV_CLASS, size, pobject); - subdev = *pobject; - if (ret) - return ret; - - __mutex_init(&subdev->mutex, name, &nvkm_subdev_lock_class[subidx]); - subdev->index = subidx; - - if (parent) { - struct nvkm_device *device = nv_device(parent); - subdev->debug = nvkm_dbgopt(device->dbgopt, name); - subdev->device = device; - } else { - subdev->device = nv_device(subdev); - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c index 6b36b86f858f..92a9f35df1a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.c @@ -30,7 +30,7 @@ static void gf100_ce_init(struct nvkm_falcon *ce) { struct nvkm_device *device = ce->engine.subdev.device; - const int index = ce->engine.subdev.index - NVDEV_ENGINE_CE0; + const int index = ce->engine.subdev.index - NVKM_ENGINE_CE0; nvkm_wr32(device, ce->addr + 0x084, index); } @@ -68,11 +68,11 @@ int gf100_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - if (index == NVDEV_ENGINE_CE0) { + if (index == NVKM_ENGINE_CE0) { return nvkm_falcon_new_(&gf100_ce0, device, index, true, 0x104000, pengine); } else - if (index == NVDEV_ENGINE_CE1) { + if (index == NVKM_ENGINE_CE1) { return nvkm_falcon_new_(&gf100_ce1, device, index, true, 0x105000, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c index 5de21a2ebb9a..c541a1c012dc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.c @@ -28,7 +28,7 @@ void gk104_ce_intr(struct nvkm_engine *ce) { - const u32 base = (ce->subdev.index - NVDEV_ENGINE_CE0) * 0x1000; + const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x1000; struct nvkm_subdev *subdev = &ce->subdev; struct nvkm_device *device = subdev->device; u32 stat = nvkm_rd32(device, 0x104908 + base); @@ -51,15 +51,15 @@ int gk104_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - if (index == NVDEV_ENGINE_CE0) { + if (index == NVKM_ENGINE_CE0) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00000040, true, pengine); } else - if (index == NVDEV_ENGINE_CE1) { + if (index == NVKM_ENGINE_CE1) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00000080, true, pengine); } else - if (index == NVDEV_ENGINE_CE2) { + if (index == NVKM_ENGINE_CE2) { return nvkm_engine_new_(&gk104_ce, device, index, 0x00200000, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c index e89c44cb23e1..8eaa72a59f40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gm204.c @@ -38,15 +38,15 @@ int gm204_ce_new(struct nvkm_device *device, int index, struct nvkm_engine **pengine) { - if (index == NVDEV_ENGINE_CE0) { + if (index == NVKM_ENGINE_CE0) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00000040, true, pengine); } else - if (index == NVDEV_ENGINE_CE1) { + if (index == NVKM_ENGINE_CE1) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00000080, true, pengine); } else - if (index == NVDEV_ENGINE_CE2) { + if (index == NVKM_ENGINE_CE2) { return nvkm_engine_new_(&gm204_ce, device, index, 0x00200000, true, pengine); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c index 03763268248f..402dcbcc2192 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.c @@ -44,7 +44,7 @@ gt215_ce_intr(struct nvkm_falcon *ce, struct nvkm_fifo_chan *chan) { struct nvkm_subdev *subdev = &ce->engine.subdev; struct nvkm_device *device = subdev->device; - const u32 base = (subdev->index - NVDEV_ENGINE_CE0) * 0x1000; + const u32 base = (subdev->index - NVKM_ENGINE_CE0) * 0x1000; u32 ssta = nvkm_rd32(device, 0x104040 + base) & 0x0000ffff; u32 addr = nvkm_rd32(device, 0x104040 + base) >> 16; u32 mthd = (addr & 0x07ff) << 2; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c index d3a35db85fba..bfd01625ec7f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c @@ -38,7 +38,7 @@ g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, align, false, parent, pgpuobj); if (ret == 0) { nvkm_kmap(*pgpuobj); - nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x00, object->oclass); nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild index 91110cd2562e..09032ba36000 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/Kbuild @@ -4,13 +4,3 @@ nvkm-y += nvkm/engine/device/ctrl.o nvkm-y += nvkm/engine/device/pci.o nvkm-y += nvkm/engine/device/tegra.o nvkm-y += nvkm/engine/device/user.o - -nvkm-y += nvkm/engine/device/nv04.o -nvkm-y += nvkm/engine/device/nv10.o -nvkm-y += nvkm/engine/device/nv20.o -nvkm-y += nvkm/engine/device/nv30.o -nvkm-y += nvkm/engine/device/nv40.o -nvkm-y += nvkm/engine/device/nv50.o -nvkm-y += nvkm/engine/device/gf100.o -nvkm-y += nvkm/engine/device/gk104.o -nvkm-y += nvkm/engine/device/gm100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 48cc06372c9c..b67cb3771948 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -1975,36 +1975,6 @@ nv12b_chipset = { .sw = gf100_sw_new, }; -#include - -struct nvkm_device * -nv_device(void *obj) -{ - struct nvkm_object *device = nv_object(obj); - - if (device->engine == NULL) { - while (device && device->parent) { - if (!nv_iclass(device, NV_SUBDEV_CLASS) && - device->parent == &nvkm_client(device)->object) { - struct { - struct nvkm_object base; - struct nvkm_device *device; - } *udevice = (void *)device; - return udevice->device; - } - device = device->parent; - } - } else { - device = &nv_object(obj)->engine->subdev.object; - if (device && device->parent) - device = device->parent; - } -#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA - BUG_ON(!device); -#endif - return (void *)device; -} - static int nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, struct nvkm_notify *notify) @@ -2032,7 +2002,7 @@ nvkm_device_subdev(struct nvkm_device *device, int index) return NULL; switch (index) { -#define _(n,p,m) case NVDEV_SUBDEV_##n: if (p) return (m); break +#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break _(BAR , device->bar , &device->bar->subdev); _(VBIOS , device->bios , &device->bios->subdev); _(BUS , device->bus , &device->bus->subdev); @@ -2069,7 +2039,7 @@ nvkm_device_engine(struct nvkm_device *device, int index) return NULL; switch (index) { -#define _(n,p,m) case NVDEV_ENGINE_##n: if (p) return (m); break +#define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break _(BSP , device->bsp , device->bsp); _(CE0 , device->ce[0] , device->ce[0]); _(CE1 , device->ce[1] , device->ce[1]); @@ -2112,7 +2082,7 @@ nvkm_device_fini(struct nvkm_device *device, bool suspend) nvkm_acpi_fini(device); - for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { + for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { if ((subdev = nvkm_device_subdev(device, i))) { ret = nvkm_subdev_fini(subdev, suspend); if (ret && suspend) @@ -2135,7 +2105,7 @@ fail: if (rret) nvkm_fatal(subdev, "failed restart, %d\n", ret); } - } while (++i < NVDEV_SUBDEV_NR); + } while (++i < NVKM_SUBDEV_NR); nvdev_trace(device, "%s failed with %d\n", action, ret); return ret; @@ -2157,7 +2127,7 @@ nvkm_device_preinit(struct nvkm_device *device) goto fail; } - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { + for (i = 0; i < NVKM_SUBDEV_NR; i++) { if ((subdev = nvkm_device_subdev(device, i))) { ret = nvkm_subdev_preinit(subdev); if (ret) @@ -2182,7 +2152,7 @@ int nvkm_device_init(struct nvkm_device *device) { struct nvkm_subdev *subdev; - int ret, i = 0, c; + int ret, i; s64 time; ret = nvkm_device_preinit(device); @@ -2194,80 +2164,11 @@ nvkm_device_init(struct nvkm_device *device) nvdev_trace(device, "init running...\n"); time = ktime_to_us(ktime_get()); - for (i = 0, c = 0; i < NVDEV_SUBDEV_NR; i++) { -#define _(s,m) case s: if (device->oclass[s] && !device->m) { \ - ret = nvkm_object_old(nv_object(device), NULL, \ - device->oclass[s], NULL, (s), \ - (struct nvkm_object **)&device->m); \ - if (ret == -ENODEV) { \ - device->oclass[s] = NULL; \ - continue; \ - } \ - if (ret) \ - goto fail; \ -} break - switch (i) { - _(NVDEV_SUBDEV_BAR , bar); - _(NVDEV_SUBDEV_VBIOS , bios); - _(NVDEV_SUBDEV_BUS , bus); - _(NVDEV_SUBDEV_CLK , clk); - _(NVDEV_SUBDEV_DEVINIT, devinit); - _(NVDEV_SUBDEV_FB , fb); - _(NVDEV_SUBDEV_FUSE , fuse); - _(NVDEV_SUBDEV_GPIO , gpio); - _(NVDEV_SUBDEV_I2C , i2c); - _(NVDEV_SUBDEV_IBUS , ibus); - _(NVDEV_SUBDEV_INSTMEM, imem); - _(NVDEV_SUBDEV_LTC , ltc); - _(NVDEV_SUBDEV_MC , mc); - _(NVDEV_SUBDEV_MMU , mmu); - _(NVDEV_SUBDEV_MXM , mxm); - _(NVDEV_SUBDEV_PMU , pmu); - _(NVDEV_SUBDEV_THERM , therm); - _(NVDEV_SUBDEV_TIMER , timer); - _(NVDEV_SUBDEV_VOLT , volt); - _(NVDEV_ENGINE_BSP , bsp); - _(NVDEV_ENGINE_CE0 , ce[0]); - _(NVDEV_ENGINE_CE1 , ce[1]); - _(NVDEV_ENGINE_CE2 , ce[2]); - _(NVDEV_ENGINE_CIPHER , cipher); - _(NVDEV_ENGINE_DISP , disp); - _(NVDEV_ENGINE_DMAOBJ , dma); - _(NVDEV_ENGINE_FIFO , fifo); - _(NVDEV_ENGINE_GR , gr); - _(NVDEV_ENGINE_IFB , ifb); - _(NVDEV_ENGINE_ME , me); - _(NVDEV_ENGINE_MPEG , mpeg); - _(NVDEV_ENGINE_MSENC , msenc); - _(NVDEV_ENGINE_MSPDEC , mspdec); - _(NVDEV_ENGINE_MSPPP , msppp); - _(NVDEV_ENGINE_MSVLD , msvld); - _(NVDEV_ENGINE_PM , pm); - _(NVDEV_ENGINE_SEC , sec); - _(NVDEV_ENGINE_SW , sw); - _(NVDEV_ENGINE_VIC , vic); - _(NVDEV_ENGINE_VP , vp); - default: - WARN_ON(1); - continue; - } -#undef _ - - /* note: can't init *any* subdevs until devinit has been run - * due to not knowing exactly what the vbios init tables will - * mess with. devinit also can't be run until all of its - * dependencies have been created. - * - * this code delays init of any subdev until all of devinit's - * dependencies have been created, and then initialises each - * subdev in turn as they're created. - */ - while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { - if ((subdev = nvkm_device_subdev(device, c++))) { - ret = nvkm_subdev_init(subdev); - if (ret) - goto fail; - } + for (i = 0; i < NVKM_SUBDEV_NR; i++) { + if ((subdev = nvkm_device_subdev(device, i))) { + ret = nvkm_subdev_init(subdev); + if (ret) + goto fail; } } @@ -2336,7 +2237,7 @@ nvkm_device_del(struct nvkm_device **pdevice) if (device) { mutex_lock(&nv_devices_mutex); device->disable_mask = 0; - for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { + for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { struct nvkm_subdev *subdev = nvkm_device_subdev(device, i); nvkm_subdev_del(&subdev); @@ -2357,10 +2258,6 @@ nvkm_device_del(struct nvkm_device **pdevice) } } -static const struct nvkm_engine_func -nvkm_device_func = { -}; - int nvkm_device_ctor(const struct nvkm_device_func *func, const struct nvkm_device_quirk *quirk, @@ -2397,12 +2294,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->dbgopt = dbg; device->name = name; list_add_tail(&device->head, &nv_devices); - - ret = nvkm_engine_ctor(&nvkm_device_func, device, 0, 0, - true, &device->engine); - device->engine.subdev.object.parent = NULL; - if (ret) - goto done; + device->debug = nvkm_dbgopt(device->dbgopt, "device"); ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); if (ret) @@ -2472,23 +2364,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->card_type = NV_04; } - switch (device->card_type) { - case NV_04: ret = nv04_identify(device); break; - case NV_10: - case NV_11: ret = nv10_identify(device); break; - case NV_20: ret = nv20_identify(device); break; - case NV_30: ret = nv30_identify(device); break; - case NV_40: ret = nv40_identify(device); break; - case NV_50: ret = nv50_identify(device); break; - case NV_C0: ret = gf100_identify(device); break; - case NV_E0: ret = gk104_identify(device); break; - case GM100: ret = gm100_identify(device); break; - default: - ret = -EINVAL; - break; - } - - switch (!ret * device->chipset) { + switch (device->chipset) { case 0x004: device->chip = &nv4_chipset; break; case 0x005: device->chip = &nv5_chipset; break; case 0x010: device->chip = &nv10_chipset; break; @@ -2594,16 +2470,9 @@ nvkm_device_ctor(const struct nvkm_device_func *func, } } - /* disable subdevs that aren't required (used by tools) */ - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { - if (!(subdev_mask & (1ULL << i))) - device->oclass[i] = NULL; - } - - atomic_set(&device->engine.subdev.object.usecount, 2); mutex_init(&device->mutex); - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { + for (i = 0; i < NVKM_SUBDEV_NR; i++) { #define _(s,m) case s: \ if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ ret = device->chip->m(device, (s), &device->m); \ @@ -2620,46 +2489,46 @@ nvkm_device_ctor(const struct nvkm_device_func *func, } \ break switch (i) { - _(NVDEV_SUBDEV_BAR , bar); - _(NVDEV_SUBDEV_VBIOS , bios); - _(NVDEV_SUBDEV_BUS , bus); - _(NVDEV_SUBDEV_CLK , clk); - _(NVDEV_SUBDEV_DEVINIT, devinit); - _(NVDEV_SUBDEV_FB , fb); - _(NVDEV_SUBDEV_FUSE , fuse); - _(NVDEV_SUBDEV_GPIO , gpio); - _(NVDEV_SUBDEV_I2C , i2c); - _(NVDEV_SUBDEV_IBUS , ibus); - _(NVDEV_SUBDEV_INSTMEM, imem); - _(NVDEV_SUBDEV_LTC , ltc); - _(NVDEV_SUBDEV_MC , mc); - _(NVDEV_SUBDEV_MMU , mmu); - _(NVDEV_SUBDEV_MXM , mxm); - _(NVDEV_SUBDEV_PMU , pmu); - _(NVDEV_SUBDEV_THERM , therm); - _(NVDEV_SUBDEV_TIMER , timer); - _(NVDEV_SUBDEV_VOLT , volt); - _(NVDEV_ENGINE_BSP , bsp); - _(NVDEV_ENGINE_CE0 , ce[0]); - _(NVDEV_ENGINE_CE1 , ce[1]); - _(NVDEV_ENGINE_CE2 , ce[2]); - _(NVDEV_ENGINE_CIPHER , cipher); - _(NVDEV_ENGINE_DISP , disp); - _(NVDEV_ENGINE_DMAOBJ , dma); - _(NVDEV_ENGINE_FIFO , fifo); - _(NVDEV_ENGINE_GR , gr); - _(NVDEV_ENGINE_IFB , ifb); - _(NVDEV_ENGINE_ME , me); - _(NVDEV_ENGINE_MPEG , mpeg); - _(NVDEV_ENGINE_MSENC , msenc); - _(NVDEV_ENGINE_MSPDEC , mspdec); - _(NVDEV_ENGINE_MSPPP , msppp); - _(NVDEV_ENGINE_MSVLD , msvld); - _(NVDEV_ENGINE_PM , pm); - _(NVDEV_ENGINE_SEC , sec); - _(NVDEV_ENGINE_SW , sw); - _(NVDEV_ENGINE_VIC , vic); - _(NVDEV_ENGINE_VP , vp); + _(NVKM_SUBDEV_BAR , bar); + _(NVKM_SUBDEV_VBIOS , bios); + _(NVKM_SUBDEV_BUS , bus); + _(NVKM_SUBDEV_CLK , clk); + _(NVKM_SUBDEV_DEVINIT, devinit); + _(NVKM_SUBDEV_FB , fb); + _(NVKM_SUBDEV_FUSE , fuse); + _(NVKM_SUBDEV_GPIO , gpio); + _(NVKM_SUBDEV_I2C , i2c); + _(NVKM_SUBDEV_IBUS , ibus); + _(NVKM_SUBDEV_INSTMEM, imem); + _(NVKM_SUBDEV_LTC , ltc); + _(NVKM_SUBDEV_MC , mc); + _(NVKM_SUBDEV_MMU , mmu); + _(NVKM_SUBDEV_MXM , mxm); + _(NVKM_SUBDEV_PMU , pmu); + _(NVKM_SUBDEV_THERM , therm); + _(NVKM_SUBDEV_TIMER , timer); + _(NVKM_SUBDEV_VOLT , volt); + _(NVKM_ENGINE_BSP , bsp); + _(NVKM_ENGINE_CE0 , ce[0]); + _(NVKM_ENGINE_CE1 , ce[1]); + _(NVKM_ENGINE_CE2 , ce[2]); + _(NVKM_ENGINE_CIPHER , cipher); + _(NVKM_ENGINE_DISP , disp); + _(NVKM_ENGINE_DMAOBJ , dma); + _(NVKM_ENGINE_FIFO , fifo); + _(NVKM_ENGINE_GR , gr); + _(NVKM_ENGINE_IFB , ifb); + _(NVKM_ENGINE_ME , me); + _(NVKM_ENGINE_MPEG , mpeg); + _(NVKM_ENGINE_MSENC , msenc); + _(NVKM_ENGINE_MSPDEC , mspdec); + _(NVKM_ENGINE_MSPPP , msppp); + _(NVKM_ENGINE_MSVLD , msvld); + _(NVKM_ENGINE_PM , pm); + _(NVKM_ENGINE_SEC , sec); + _(NVKM_ENGINE_SW , sw); + _(NVKM_ENGINE_VIC , vic); + _(NVKM_ENGINE_VP , vp); default: WARN_ON(1); continue; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c deleted file mode 100644 index 3c618162923d..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -gf100_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0xc0: - break; - case 0xc4: - break; - case 0xc3: - break; - case 0xce: - break; - case 0xcf: - break; - case 0xc1: - break; - case 0xc8: - break; - case 0xd9: - break; - case 0xd7: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c deleted file mode 100644 index 447659718709..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -gk104_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0xe4: - break; - case 0xe7: - break; - case 0xe6: - break; - case 0xea: - break; - case 0xf0: - break; - case 0xf1: - break; - case 0x106: - break; - case 0x108: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c deleted file mode 100644 index e0a214c0cb6e..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -gm100_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x117: - -#if 0 -#endif -#if 0 -#endif -#if 0 -#endif - break; - case 0x124: -#if 0 - /* looks to be some non-trivial changes */ - /* priv ring says no to 0x10eb14 writes */ -#endif -#if 0 -#endif -#if 0 -#endif - break; - case 0x126: -#if 0 - /* looks to be some non-trivial changes */ - /* priv ring says no to 0x10eb14 writes */ -#endif -#if 0 -#endif -#if 0 -#endif - break; - case 0x12b: - - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c deleted file mode 100644 index 369992ba9c36..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -nv04_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x04: - break; - case 0x05: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c deleted file mode 100644 index 233f9f9cfda9..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -nv10_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x10: - break; - case 0x15: - break; - case 0x16: - break; - case 0x1a: - break; - case 0x11: - break; - case 0x17: - break; - case 0x1f: - break; - case 0x18: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c deleted file mode 100644 index d6204a954cba..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -nv20_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x20: - break; - case 0x25: - break; - case 0x28: - break; - case 0x2a: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c deleted file mode 100644 index 1787f3558d71..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -nv30_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x30: - break; - case 0x35: - break; - case 0x31: - break; - case 0x36: - break; - case 0x34: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c deleted file mode 100644 index d40e18693a73..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -nv40_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x40: - break; - case 0x41: - break; - case 0x42: - break; - case 0x43: - break; - case 0x45: - break; - case 0x47: - break; - case 0x49: - break; - case 0x4b: - break; - case 0x44: - break; - case 0x46: - break; - case 0x4a: - break; - case 0x4c: - break; - case 0x4e: - break; - case 0x63: - break; - case 0x67: - break; - case 0x68: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c deleted file mode 100644 index 8ca1368e1068..000000000000 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright 2012 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ -#include "priv.h" - -int -nv50_identify(struct nvkm_device *device) -{ - switch (device->chipset) { - case 0x50: - break; - case 0x84: - break; - case 0x86: - break; - case 0x92: - break; - case 0x94: - break; - case 0x96: - break; - case 0x98: - break; - case 0xa0: - break; - case 0xaa: - break; - case 0xac: - break; - case 0xa3: - break; - case 0xa5: - break; - case 0xa8: - break; - case 0xaf: - break; - default: - return -EINVAL; - } - - return 0; -} diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index 4cf483894af0..adebf52578c1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -46,14 +46,4 @@ int nvkm_device_ctor(const struct nvkm_device_func *, struct nvkm_device *); int nvkm_device_init(struct nvkm_device *); int nvkm_device_fini(struct nvkm_device *, bool suspend); - -int nv04_identify(struct nvkm_device *); -int nv10_identify(struct nvkm_device *); -int nv20_identify(struct nvkm_device *); -int nv30_identify(struct nvkm_device *); -int nv40_identify(struct nvkm_device *); -int nv50_identify(struct nvkm_device *); -int gf100_identify(struct nvkm_device *); -int gk104_identify(struct nvkm_device *); -int gm100_identify(struct nvkm_device *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index a9df61bf3780..a948960cc056 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -261,10 +261,10 @@ nvkm_udevice_child_get(struct nvkm_object *object, int index, struct nvkm_udevice *udev = nvkm_udevice(object); struct nvkm_device *device = udev->device; struct nvkm_engine *engine; - u64 mask = (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_FIFO) | - (1ULL << NVDEV_ENGINE_DISP) | - (1ULL << NVDEV_ENGINE_PM); + u64 mask = (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_FIFO) | + (1ULL << NVKM_ENGINE_DISP) | + (1ULL << NVKM_ENGINE_PM); const struct nvkm_device_oclass *sclass = NULL; int i; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c index 9ad9512782a5..b05c04a209be 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c @@ -90,7 +90,7 @@ nv50_disp_dmac_child_get_(struct nv50_disp_chan *base, int index, struct nvkm_device *device = disp->base.engine.subdev.device; const struct nvkm_device_oclass *oclass = NULL; - sclass->engine = nvkm_device_engine(device, NVDEV_ENGINE_DMAOBJ); + sclass->engine = nvkm_device_engine(device, NVKM_ENGINE_DMAOBJ); if (sclass->engine && sclass->engine->func->base.sclass) { sclass->engine->func->base.sclass(sclass, index, &oclass); if (oclass) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index 4ed06abdc917..a56e56eed57b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -332,7 +332,7 @@ nvkm_fifo_chan_dtor(struct nvkm_object *object) return data; } -const struct nvkm_object_func +static const struct nvkm_object_func nvkm_fifo_chan_func = { .dtor = nvkm_fifo_chan_dtor, .init = nvkm_fifo_chan_init, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c index a7e5dfae3833..04305241ceed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c @@ -48,16 +48,16 @@ static int g84_fifo_chan_engine(struct nvkm_engine *engine) { switch (engine->subdev.index) { - case NVDEV_ENGINE_GR : return 0; - case NVDEV_ENGINE_MPEG : - case NVDEV_ENGINE_MSPPP : return 1; - case NVDEV_ENGINE_CE0 : return 2; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: return 3; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : return 4; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : return 5; + case NVKM_ENGINE_GR : return 0; + case NVKM_ENGINE_MPEG : + case NVKM_ENGINE_MSPPP : return 1; + case NVKM_ENGINE_CE0 : return 2; + case NVKM_ENGINE_VP : + case NVKM_ENGINE_MSPDEC: return 3; + case NVKM_ENGINE_CIPHER: + case NVKM_ENGINE_SEC : return 4; + case NVKM_ENGINE_BSP : + case NVKM_ENGINE_MSVLD : return 5; default: WARN_ON(1); return 0; @@ -68,18 +68,18 @@ static int g84_fifo_chan_engine_addr(struct nvkm_engine *engine) { switch (engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : return -1; - case NVDEV_ENGINE_GR : return 0x0020; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: return 0x0040; - case NVDEV_ENGINE_MPEG : - case NVDEV_ENGINE_MSPPP : return 0x0060; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : return 0x0080; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : return 0x00a0; - case NVDEV_ENGINE_CE0 : return 0x00c0; + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW : return -1; + case NVKM_ENGINE_GR : return 0x0020; + case NVKM_ENGINE_VP : + case NVKM_ENGINE_MSPDEC: return 0x0040; + case NVKM_ENGINE_MPEG : + case NVKM_ENGINE_MSPPP : return 0x0060; + case NVKM_ENGINE_BSP : + case NVKM_ENGINE_MSVLD : return 0x0080; + case NVKM_ENGINE_CIPHER: + case NVKM_ENGINE_SEC : return 0x00a0; + case NVKM_ENGINE_CE0 : return 0x00c0; default: WARN_ON(1); return -1; @@ -167,11 +167,6 @@ g84_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, if (g84_fifo_chan_engine_addr(engine) < 0) return 0; - if (nv_iclass(object, NV_GPUOBJ_CLASS)) { - chan->engn[engn] = nv_gpuobj(object); - return 0; - } - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); } @@ -184,20 +179,20 @@ g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, u32 context; switch (object->engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context = 0x00000000; break; - case NVDEV_ENGINE_GR : context = 0x00100000; break; - case NVDEV_ENGINE_MPEG : - case NVDEV_ENGINE_MSPPP : context = 0x00200000; break; - case NVDEV_ENGINE_ME : - case NVDEV_ENGINE_CE0 : context = 0x00300000; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: context = 0x00400000; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : - case NVDEV_ENGINE_VIC : context = 0x00500000; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : context = 0x00600000; break; + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW : context = 0x00000000; break; + case NVKM_ENGINE_GR : context = 0x00100000; break; + case NVKM_ENGINE_MPEG : + case NVKM_ENGINE_MSPPP : context = 0x00200000; break; + case NVKM_ENGINE_ME : + case NVKM_ENGINE_CE0 : context = 0x00300000; break; + case NVKM_ENGINE_VP : + case NVKM_ENGINE_MSPDEC: context = 0x00400000; break; + case NVKM_ENGINE_CIPHER: + case NVKM_ENGINE_SEC : + case NVKM_ENGINE_VIC : context = 0x00500000; break; + case NVKM_ENGINE_BSP : + case NVKM_ENGINE_MSVLD : context = 0x00600000; break; default: WARN_ON(1); return -EINVAL; @@ -243,20 +238,20 @@ g84_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push, ret = nvkm_fifo_chan_ctor(&g84_fifo_chan_func, &fifo->base, 0x10000, 0x1000, false, vm, push, - (1ULL << NVDEV_ENGINE_BSP) | - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_CIPHER) | - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_ME) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_SEC) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_VIC) | - (1ULL << NVDEV_ENGINE_VP), + (1ULL << NVKM_ENGINE_BSP) | + (1ULL << NVKM_ENGINE_CE0) | + (1ULL << NVKM_ENGINE_CIPHER) | + (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_ME) | + (1ULL << NVKM_ENGINE_MPEG) | + (1ULL << NVKM_ENGINE_MSPDEC) | + (1ULL << NVKM_ENGINE_MSPPP) | + (1ULL << NVKM_ENGINE_MSVLD) | + (1ULL << NVKM_ENGINE_SEC) | + (1ULL << NVKM_ENGINE_SW) | + (1ULL << NVKM_ENGINE_VIC) | + (1ULL << NVKM_ENGINE_VP), 0, 0xc00000, 0x2000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h index 413288597e04..7d697e2dce1a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changf100.h @@ -17,7 +17,7 @@ struct gf100_fifo_chan { struct { struct nvkm_gpuobj *inst; struct nvkm_vma vma; - } engn[NVDEV_SUBDEV_NR]; + } engn[NVKM_SUBDEV_NR]; }; extern const struct nvkm_fifo_chan_oclass gf100_fifo_gpfifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h index 2b9d8bfc7fd7..97bdddb7644a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/changk104.h @@ -18,7 +18,7 @@ struct gk104_fifo_chan { struct { struct nvkm_gpuobj *inst; struct nvkm_vma vma; - } engn[NVDEV_SUBDEV_NR]; + } engn[NVKM_SUBDEV_NR]; }; int gk104_fifo_gpfifo_new(struct nvkm_fifo *, const struct nvkm_oclass *, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h index ac62a6404f87..3361a1fd0343 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h @@ -8,7 +8,7 @@ struct nv04_fifo_chan { struct nvkm_fifo_chan base; struct nv04_fifo *fifo; u32 ramfc; - struct nvkm_gpuobj *engn[NVDEV_SUBDEV_NR]; + struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; }; extern const struct nvkm_fifo_chan_func nv04_fifo_dma_func; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c index 2a25019ce0f4..25b60aff40e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c @@ -32,10 +32,10 @@ static int nv50_fifo_chan_engine_addr(struct nvkm_engine *engine) { switch (engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : return -1; - case NVDEV_ENGINE_GR : return 0x0000; - case NVDEV_ENGINE_MPEG : return 0x0060; + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW : return -1; + case NVKM_ENGINE_GR : return 0x0000; + case NVKM_ENGINE_MPEG : return 0x0060; default: WARN_ON(1); return -1; @@ -130,11 +130,6 @@ nv50_fifo_chan_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv50_fifo_chan *chan = nv50_fifo_chan(base); - if (!chan->engn[engine->subdev.index] || - chan->engn[engine->subdev.index]->object.oclass) { - chan->engn[engine->subdev.index] = NULL; - return; - } nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); } @@ -149,11 +144,6 @@ nv50_fifo_chan_engine_ctor(struct nvkm_fifo_chan *base, if (nv50_fifo_chan_engine_addr(engine) < 0) return 0; - if (nv_iclass(object, NV_GPUOBJ_CLASS)) { - chan->engn[engn] = nv_gpuobj(object); - return 0; - } - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); } @@ -173,10 +163,10 @@ nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base, u32 context; switch (object->engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context = 0x00000000; break; - case NVDEV_ENGINE_GR : context = 0x00100000; break; - case NVDEV_ENGINE_MPEG : context = 0x00200000; break; + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW : context = 0x00000000; break; + case NVKM_ENGINE_GR : context = 0x00100000; break; + case NVKM_ENGINE_MPEG : context = 0x00200000; break; default: WARN_ON(1); return -EINVAL; @@ -248,10 +238,10 @@ nv50_fifo_chan_ctor(struct nv50_fifo *fifo, u64 vm, u64 push, ret = nvkm_fifo_chan_ctor(&nv50_fifo_chan_func, &fifo->base, 0x10000, 0x1000, false, vm, push, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG), + (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_SW) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_MPEG), 0, 0xc00000, 0x2000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h index 7ef6bc2e27ec..4b9da469b704 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h @@ -15,7 +15,7 @@ struct nv50_fifo_chan { struct nvkm_ramht *ramht; struct nvkm_vm *vm; - struct nvkm_gpuobj *engn[NVDEV_SUBDEV_NR]; + struct nvkm_gpuobj *engn[NVKM_SUBDEV_NR]; }; int nv50_fifo_chan_ctor(struct nv50_fifo *, u64 vm, u64 push, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c index 52cbc4b47b2c..bfcc6408a772 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c @@ -50,10 +50,10 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, int hash; switch (object->engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context |= 0x00000000; break; - case NVDEV_ENGINE_GR : context |= 0x00010000; break; - case NVDEV_ENGINE_MPEG : context |= 0x00020000; break; + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW : context |= 0x00000000; break; + case NVKM_ENGINE_GR : context |= 0x00010000; break; + case NVKM_ENGINE_MPEG : context |= 0x00020000; break; default: WARN_ON(1); return -EINVAL; @@ -185,9 +185,9 @@ nv04_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_SW), + (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_SW), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c index d8e4d55704d1..34f68e5bd040 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c @@ -61,9 +61,9 @@ nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_SW), + (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_SW), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c index 1424dd9b6299..ed7cc9f2b540 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c @@ -61,10 +61,10 @@ nv17_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | /* NV31- */ - (1ULL << NVDEV_ENGINE_SW), + (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_MPEG) | /* NV31- */ + (1ULL << NVKM_ENGINE_SW), 0, 0x800000, 0x10000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c index b46a3b3cd092..043b6c325949 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c @@ -35,14 +35,14 @@ static bool nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx) { switch (engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW: + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW: return false; - case NVDEV_ENGINE_GR: + case NVKM_ENGINE_GR: *reg = 0x0032e0; *ctx = 0x38; return true; - case NVDEV_ENGINE_MPEG: + case NVKM_ENGINE_MPEG: *reg = 0x00330c; *ctx = 0x54; return true; @@ -118,11 +118,6 @@ nv40_fifo_dma_engine_dtor(struct nvkm_fifo_chan *base, struct nvkm_engine *engine) { struct nv04_fifo_chan *chan = nv04_fifo_chan(base); - if (!chan->engn[engine->subdev.index] || - chan->engn[engine->subdev.index]->object.oclass) { - chan->engn[engine->subdev.index] = NULL; - return; - } nvkm_gpuobj_del(&chan->engn[engine->subdev.index]); } @@ -138,11 +133,6 @@ nv40_fifo_dma_engine_ctor(struct nvkm_fifo_chan *base, if (!nv40_fifo_dma_engine(engine, ®, &ctx)) return 0; - if (nv_iclass(object, NV_GPUOBJ_CLASS)) { - chan->engn[engn] = nv_gpuobj(object); - return 0; - } - return nvkm_object_bind(object, NULL, 0, &chan->engn[engn]); } @@ -157,10 +147,10 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base, int hash; switch (object->engine->subdev.index) { - case NVDEV_ENGINE_DMAOBJ: - case NVDEV_ENGINE_SW : context |= 0x00000000; break; - case NVDEV_ENGINE_GR : context |= 0x00100000; break; - case NVDEV_ENGINE_MPEG : context |= 0x00200000; break; + case NVKM_ENGINE_DMAOBJ: + case NVKM_ENGINE_SW : context |= 0x00000000; break; + case NVKM_ENGINE_GR : context |= 0x00100000; break; + case NVKM_ENGINE_MPEG : context |= 0x00200000; break; default: WARN_ON(1); return -EINVAL; @@ -216,10 +206,10 @@ nv40_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&nv40_fifo_dma_func, &fifo->base, 0x1000, 0x1000, false, 0, args->v0.pushbuf, - (1ULL << NVDEV_ENGINE_DMAOBJ) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MPEG) | - (1ULL << NVDEV_ENGINE_SW), + (1ULL << NVKM_ENGINE_DMAOBJ) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_MPEG) | + (1ULL << NVKM_ENGINE_SW), 0, 0xc00000, 0x1000, oclass, &chan->base); chan->fifo = fifo; if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index bc094223f687..172f24301113 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -82,12 +82,12 @@ static inline int gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) { switch (engn) { - case NVDEV_ENGINE_GR : engn = 0; break; - case NVDEV_ENGINE_MSVLD : engn = 1; break; - case NVDEV_ENGINE_MSPPP : engn = 2; break; - case NVDEV_ENGINE_MSPDEC: engn = 3; break; - case NVDEV_ENGINE_CE0 : engn = 4; break; - case NVDEV_ENGINE_CE1 : engn = 5; break; + case NVKM_ENGINE_GR : engn = 0; break; + case NVKM_ENGINE_MSVLD : engn = 1; break; + case NVKM_ENGINE_MSPPP : engn = 2; break; + case NVKM_ENGINE_MSPDEC: engn = 3; break; + case NVKM_ENGINE_CE0 : engn = 4; break; + case NVKM_ENGINE_CE1 : engn = 5; break; default: return -1; } @@ -101,12 +101,12 @@ gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) struct nvkm_device *device = fifo->base.engine.subdev.device; switch (engn) { - case 0: engn = NVDEV_ENGINE_GR; break; - case 1: engn = NVDEV_ENGINE_MSVLD; break; - case 2: engn = NVDEV_ENGINE_MSPPP; break; - case 3: engn = NVDEV_ENGINE_MSPDEC; break; - case 4: engn = NVDEV_ENGINE_CE0; break; - case 5: engn = NVDEV_ENGINE_CE1; break; + case 0: engn = NVKM_ENGINE_GR; break; + case 1: engn = NVKM_ENGINE_MSVLD; break; + case 2: engn = NVKM_ENGINE_MSPPP; break; + case 3: engn = NVKM_ENGINE_MSPDEC; break; + case 4: engn = NVKM_ENGINE_CE0; break; + case 5: engn = NVKM_ENGINE_CE1; break; default: return NULL; } @@ -229,17 +229,17 @@ gf100_fifo_intr_sched(struct gf100_fifo *fifo) static const struct nvkm_enum gf100_fifo_fault_engine[] = { - { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, - { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, - { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, - { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, - { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, - { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, - { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, + { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR }, + { 0x03, "PEEPHOLE", NULL, NVKM_ENGINE_IFB }, + { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, + { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM }, + { 0x07, "PFIFO", NULL, NVKM_ENGINE_FIFO }, + { 0x10, "PMSVLD", NULL, NVKM_ENGINE_MSVLD }, + { 0x11, "PMSPPP", NULL, NVKM_ENGINE_MSPPP }, { 0x13, "PCOUNTER" }, - { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, - { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, - { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, + { 0x14, "PMSPDEC", NULL, NVKM_ENGINE_MSPDEC }, + { 0x15, "PCE0", NULL, NVKM_ENGINE_CE0 }, + { 0x16, "PCE1", NULL, NVKM_ENGINE_CE1 }, { 0x17, "PDAEMON" }, {} }; @@ -317,13 +317,13 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) if (eu) { switch (eu->data2) { - case NVDEV_SUBDEV_BAR: + case NVKM_SUBDEV_BAR: nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); break; - case NVDEV_SUBDEV_INSTMEM: + case NVKM_SUBDEV_INSTMEM: nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); break; - case NVDEV_ENGINE_IFB: + case NVKM_ENGINE_IFB: nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 465b52dee277..fc0ff2d37d06 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -248,22 +248,22 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) static const struct nvkm_enum gk104_fifo_fault_engine[] = { - { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, - { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB }, - { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, - { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, - { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, - { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, - { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, - { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD }, - { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP }, + { 0x00, "GR", NULL, NVKM_ENGINE_GR }, + { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, + { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, + { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM }, + { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO }, + { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO }, + { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO }, + { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, + { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, { 0x13, "PERF" }, - { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, - { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 }, - { 0x16, "CE1", NULL, NVDEV_ENGINE_CE1 }, + { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC }, + { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 }, + { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 }, { 0x17, "PMU" }, - { 0x19, "MSENC", NULL, NVDEV_ENGINE_MSENC }, - { 0x1b, "CE2", NULL, NVDEV_ENGINE_CE2 }, + { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC }, + { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 }, {} }; @@ -382,13 +382,13 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) if (eu) { switch (eu->data2) { - case NVDEV_SUBDEV_BAR: + case NVKM_SUBDEV_BAR: nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); break; - case NVDEV_SUBDEV_INSTMEM: + case NVKM_SUBDEV_INSTMEM: nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); break; - case NVDEV_ENGINE_IFB: + case NVKM_ENGINE_IFB: nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index 7a5c544a5ffb..5afd9b5ec5d1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -41,15 +41,15 @@ static inline u64 gk104_fifo_engine_subdev(int engine) { switch (engine) { - case 0: return (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_SW) | - (1ULL << NVDEV_ENGINE_CE2); - case 1: return (1ULL << NVDEV_ENGINE_MSPDEC); - case 2: return (1ULL << NVDEV_ENGINE_MSPPP); - case 3: return (1ULL << NVDEV_ENGINE_MSVLD); - case 4: return (1ULL << NVDEV_ENGINE_CE0); - case 5: return (1ULL << NVDEV_ENGINE_CE1); - case 6: return (1ULL << NVDEV_ENGINE_MSENC); + case 0: return (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_SW) | + (1ULL << NVKM_ENGINE_CE2); + case 1: return (1ULL << NVKM_ENGINE_MSPDEC); + case 2: return (1ULL << NVKM_ENGINE_MSPPP); + case 3: return (1ULL << NVKM_ENGINE_MSVLD); + case 4: return (1ULL << NVKM_ENGINE_CE0); + case 5: return (1ULL << NVKM_ENGINE_CE1); + case 6: return (1ULL << NVKM_ENGINE_MSENC); default: WARN_ON(1); return 0; @@ -60,15 +60,15 @@ static inline int gk104_fifo_subdev_engine(int subdev) { switch (subdev) { - case NVDEV_ENGINE_GR: - case NVDEV_ENGINE_SW: - case NVDEV_ENGINE_CE2 : return 0; - case NVDEV_ENGINE_MSPDEC: return 1; - case NVDEV_ENGINE_MSPPP : return 2; - case NVDEV_ENGINE_MSVLD : return 3; - case NVDEV_ENGINE_CE0 : return 4; - case NVDEV_ENGINE_CE1 : return 5; - case NVDEV_ENGINE_MSENC : return 6; + case NVKM_ENGINE_GR: + case NVKM_ENGINE_SW: + case NVKM_ENGINE_CE2 : return 0; + case NVKM_ENGINE_MSPDEC: return 1; + case NVKM_ENGINE_MSPPP : return 2; + case NVKM_ENGINE_MSVLD : return 3; + case NVKM_ENGINE_CE0 : return 4; + case NVKM_ENGINE_CE1 : return 5; + case NVKM_ENGINE_MSENC : return 6; default: WARN_ON(1); return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c index 5d76c3013a80..e7cbc139c1d4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c @@ -35,13 +35,13 @@ static u32 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { switch (engine->subdev.index) { - case NVDEV_ENGINE_SW : return 0; - case NVDEV_ENGINE_GR : return 0x0210; - case NVDEV_ENGINE_CE0 : return 0x0230; - case NVDEV_ENGINE_CE1 : return 0x0240; - case NVDEV_ENGINE_MSPDEC: return 0x0250; - case NVDEV_ENGINE_MSPPP : return 0x0260; - case NVDEV_ENGINE_MSVLD : return 0x0270; + case NVKM_ENGINE_SW : return 0; + case NVKM_ENGINE_GR : return 0x0210; + case NVKM_ENGINE_CE0 : return 0x0230; + case NVKM_ENGINE_CE1 : return 0x0240; + case NVKM_ENGINE_MSPDEC: return 0x0250; + case NVKM_ENGINE_MSPPP : return 0x0260; + case NVKM_ENGINE_MSVLD : return 0x0270; default: WARN_ON(1); return 0; @@ -121,12 +121,6 @@ gf100_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, if (!gf100_fifo_gpfifo_engine_addr(engine)) return 0; - if (object->oclass) { - return nvkm_gpuobj_map(nv_gpuobj(object), chan->vm, - NV_MEM_ACCESS_RW, - &chan->engn[engn].vma); - } - ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); if (ret) return ret; @@ -225,13 +219,13 @@ gf100_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass, ret = nvkm_fifo_chan_ctor(&gf100_fifo_gpfifo_func, &fifo->base, 0x1000, 0x1000, true, args->v0.vm, 0, - (1ULL << NVDEV_ENGINE_CE0) | - (1ULL << NVDEV_ENGINE_CE1) | - (1ULL << NVDEV_ENGINE_GR) | - (1ULL << NVDEV_ENGINE_MSPDEC) | - (1ULL << NVDEV_ENGINE_MSPPP) | - (1ULL << NVDEV_ENGINE_MSVLD) | - (1ULL << NVDEV_ENGINE_SW), + (1ULL << NVKM_ENGINE_CE0) | + (1ULL << NVKM_ENGINE_CE1) | + (1ULL << NVKM_ENGINE_GR) | + (1ULL << NVKM_ENGINE_MSPDEC) | + (1ULL << NVKM_ENGINE_MSPPP) | + (1ULL << NVKM_ENGINE_MSVLD) | + (1ULL << NVKM_ENGINE_SW), 1, fifo->user.bar.offset, 0x1000, oclass, &chan->base); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c index fe39981915b6..0b817540a9e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c @@ -57,14 +57,14 @@ static u32 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine) { switch (engine->subdev.index) { - case NVDEV_ENGINE_SW : - case NVDEV_ENGINE_CE0 : - case NVDEV_ENGINE_CE1 : - case NVDEV_ENGINE_CE2 : return 0x0000; - case NVDEV_ENGINE_GR : return 0x0210; - case NVDEV_ENGINE_MSPDEC: return 0x0250; - case NVDEV_ENGINE_MSPPP : return 0x0260; - case NVDEV_ENGINE_MSVLD : return 0x0270; + case NVKM_ENGINE_SW : + case NVKM_ENGINE_CE0 : + case NVKM_ENGINE_CE1 : + case NVKM_ENGINE_CE2 : return 0x0000; + case NVKM_ENGINE_GR : return 0x0210; + case NVKM_ENGINE_MSPDEC: return 0x0250; + case NVKM_ENGINE_MSPPP : return 0x0260; + case NVKM_ENGINE_MSVLD : return 0x0270; default: WARN_ON(1); return 0; @@ -134,12 +134,6 @@ gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base, if (!gk104_fifo_gpfifo_engine_addr(engine)) return 0; - if (object->oclass) { - return nvkm_gpuobj_map(nv_gpuobj(object), chan->vm, - NV_MEM_ACCESS_RW, - &chan->engn[engn].vma); - } - ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c index 7b4317ab8f02..426ba0025a8d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c @@ -1047,7 +1047,7 @@ nv04_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, false, parent, pgpuobj); if (ret == 0) { nvkm_kmap(*pgpuobj); - nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x00, object->oclass); nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nvkm_wo32(*pgpuobj, 0x08, 0x00000000); #ifdef __BIG_ENDIAN diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 127a36f5859e..7987df18415b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -48,7 +48,7 @@ nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, false, parent, pgpuobj); if (ret == 0) { nvkm_kmap(*pgpuobj); - nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x00, object->oclass); nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nvkm_wo32(*pgpuobj, 0x08, 0x00000000); #ifdef __BIG_ENDIAN diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c index 9992a919a6d9..b19b912d5787 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c @@ -45,7 +45,7 @@ nv50_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, align, false, parent, pgpuobj); if (ret == 0) { nvkm_kmap(*pgpuobj); - nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x00, object->oclass); nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c index 87420b8329ac..d4d8942b1347 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c @@ -43,7 +43,7 @@ nv31_mpeg_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, false, parent, pgpuobj); if (ret == 0) { nvkm_kmap(*pgpuobj); - nvkm_wo32(*pgpuobj, 0x00, object->oclass_name); + nvkm_wo32(*pgpuobj, 0x00, object->oclass); nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 03ce10fcba4f..2eb0a370a3a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -64,7 +64,7 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, if (ret) return ret; - atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]); /* * Bootstrap page table lookup. diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index 65646fb917c1..fac54f97217e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -88,7 +88,7 @@ nv50_bar_oneinit(struct nvkm_bar *base) if (ret) return ret; - atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]); ret = nvkm_vm_boot(vm, limit-- - start); if (ret) @@ -121,7 +121,7 @@ nv50_bar_oneinit(struct nvkm_bar *base) if (ret) return ret; - atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); + atomic_inc(&vm->engref[NVKM_SUBDEV_BAR]); ret = nvkm_vm_ref(vm, &bar->bar1_vm, bar->pgd); nvkm_vm_ref(NULL, &vm, NULL); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c index 18871a3caa28..e895289bf3c1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.c @@ -35,18 +35,18 @@ g84_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_MPEG); - disable |= (1ULL << NVDEV_ENGINE_VP); - disable |= (1ULL << NVDEV_ENGINE_BSP); - disable |= (1ULL << NVDEV_ENGINE_CIPHER); + disable |= (1ULL << NVKM_ENGINE_MPEG); + disable |= (1ULL << NVKM_ENGINE_VP); + disable |= (1ULL << NVKM_ENGINE_BSP); + disable |= (1ULL << NVKM_ENGINE_CIPHER); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVDEV_ENGINE_DISP); + disable |= (1ULL << NVKM_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVKM_ENGINE_BSP); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_CIPHER); + disable |= (1ULL << NVKM_ENGINE_CIPHER); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c index a381efa9ae4a..a9d45844df5a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c @@ -35,17 +35,17 @@ g98_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_MSPDEC); - disable |= (1ULL << NVDEV_ENGINE_MSVLD); - disable |= (1ULL << NVDEV_ENGINE_MSPPP); + disable |= (1ULL << NVKM_ENGINE_MSPDEC); + disable |= (1ULL << NVKM_ENGINE_MSVLD); + disable |= (1ULL << NVKM_ENGINE_MSPPP); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVDEV_ENGINE_DISP); + disable |= (1ULL << NVKM_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_MSVLD); + disable |= (1ULL << NVKM_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_SEC); + disable |= (1ULL << NVKM_ENGINE_SEC); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c index a9f2d02b6e18..22b0140e28c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c @@ -71,21 +71,21 @@ gf100_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (r022500 & 0x00000001) - disable |= (1ULL << NVDEV_ENGINE_DISP); + disable |= (1ULL << NVKM_ENGINE_DISP); if (r022500 & 0x00000002) { - disable |= (1ULL << NVDEV_ENGINE_MSPDEC); - disable |= (1ULL << NVDEV_ENGINE_MSPPP); + disable |= (1ULL << NVKM_ENGINE_MSPDEC); + disable |= (1ULL << NVKM_ENGINE_MSPPP); } if (r022500 & 0x00000004) - disable |= (1ULL << NVDEV_ENGINE_MSVLD); + disable |= (1ULL << NVKM_ENGINE_MSVLD); if (r022500 & 0x00000008) - disable |= (1ULL << NVDEV_ENGINE_MSENC); + disable |= (1ULL << NVKM_ENGINE_MSENC); if (r022500 & 0x00000100) - disable |= (1ULL << NVDEV_ENGINE_CE0); + disable |= (1ULL << NVKM_ENGINE_CE0); if (r022500 & 0x00000200) - disable |= (1ULL << NVDEV_ENGINE_CE1); + disable |= (1ULL << NVKM_ENGINE_CE1); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c index f0f84fef2350..2be98bd78214 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.c @@ -35,11 +35,11 @@ gm107_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (r021c00 & 0x00000001) - disable |= (1ULL << NVDEV_ENGINE_CE0); + disable |= (1ULL << NVKM_ENGINE_CE0); if (r021c00 & 0x00000004) - disable |= (1ULL << NVDEV_ENGINE_CE2); + disable |= (1ULL << NVKM_ENGINE_CE2); if (r021c04 & 0x00000001) - disable |= (1ULL << NVDEV_ENGINE_DISP); + disable |= (1ULL << NVKM_ENGINE_DISP); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c index 38f9827902e9..9a8522fa9c65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c @@ -71,16 +71,16 @@ gt215_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_MSPDEC); - disable |= (1ULL << NVDEV_ENGINE_MSPPP); + disable |= (1ULL << NVKM_ENGINE_MSPDEC); + disable |= (1ULL << NVKM_ENGINE_MSPPP); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVDEV_ENGINE_DISP); + disable |= (1ULL << NVKM_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_MSVLD); + disable |= (1ULL << NVKM_ENGINE_MSVLD); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVDEV_ENGINE_CE0); + disable |= (1ULL << NVKM_ENGINE_CE0); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c index 892f5ea86d57..ce4f718e98a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c @@ -35,18 +35,18 @@ mcp89_devinit_disable(struct nvkm_devinit *init) u64 disable = 0; if (!(r001540 & 0x40000000)) { - disable |= (1ULL << NVDEV_ENGINE_MSPDEC); - disable |= (1ULL << NVDEV_ENGINE_MSPPP); + disable |= (1ULL << NVKM_ENGINE_MSPDEC); + disable |= (1ULL << NVKM_ENGINE_MSPPP); } if (!(r00154c & 0x00000004)) - disable |= (1ULL << NVDEV_ENGINE_DISP); + disable |= (1ULL << NVKM_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_MSVLD); + disable |= (1ULL << NVKM_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) - disable |= (1ULL << NVDEV_ENGINE_VIC); + disable |= (1ULL << NVKM_ENGINE_VIC); if (!(r00154c & 0x00000200)) - disable |= (1ULL << NVDEV_ENGINE_CE0); + disable |= (1ULL << NVKM_ENGINE_CE0); return disable; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c index e183729bfee0..337c2c692dc7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.c @@ -85,7 +85,7 @@ nv50_devinit_disable(struct nvkm_devinit *init) u64 disable = 0ULL; if (!(r001540 & 0x40000000)) - disable |= (1ULL << NVDEV_ENGINE_MPEG); + disable |= (1ULL << NVKM_ENGINE_MPEG); return disable; } @@ -103,7 +103,7 @@ nv50_devinit_preinit(struct nvkm_devinit *base) */ if (!init->base.post) { u64 disable = nvkm_devinit_disable(&init->base); - if (disable & (1ULL << NVDEV_ENGINE_DISP)) + if (disable & (1ULL << NVKM_ENGINE_DISP)) init->base.post = true; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c index 44286a4bb356..2936fabb7cf1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.c @@ -25,22 +25,22 @@ static const struct nvkm_mc_intr g98_mc_intr[] = { - { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ - { 0x00000001, NVDEV_ENGINE_MSPPP }, - { 0x00000100, NVDEV_ENGINE_FIFO }, - { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00004000, NVDEV_ENGINE_SEC }, /* NV84:NVA3 */ - { 0x00008000, NVDEV_ENGINE_MSVLD }, - { 0x00020000, NVDEV_ENGINE_MSPDEC }, - { 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */ - { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */ - { 0x00100000, NVDEV_SUBDEV_TIMER }, - { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ - { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ - { 0x00400000, NVDEV_ENGINE_CE0 }, /* NVA3- */ - { 0x10000000, NVDEV_SUBDEV_BUS }, - { 0x80000000, NVDEV_ENGINE_SW }, - { 0x0042d101, NVDEV_SUBDEV_FB }, + { 0x04000000, NVKM_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ + { 0x00000001, NVKM_ENGINE_MSPPP }, + { 0x00000100, NVKM_ENGINE_FIFO }, + { 0x00001000, NVKM_ENGINE_GR }, + { 0x00004000, NVKM_ENGINE_SEC }, /* NV84:NVA3 */ + { 0x00008000, NVKM_ENGINE_MSVLD }, + { 0x00020000, NVKM_ENGINE_MSPDEC }, + { 0x00040000, NVKM_SUBDEV_PMU }, /* NVA3:NVC0 */ + { 0x00080000, NVKM_SUBDEV_THERM }, /* NVA3:NVC0 */ + { 0x00100000, NVKM_SUBDEV_TIMER }, + { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */ + { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */ + { 0x00400000, NVKM_ENGINE_CE0 }, /* NVA3- */ + { 0x10000000, NVKM_SUBDEV_BUS }, + { 0x80000000, NVKM_ENGINE_SW }, + { 0x0042d101, NVKM_SUBDEV_FB }, {}, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c index 26f68d7e7ccc..6e7af483ccf3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.c @@ -25,26 +25,26 @@ const struct nvkm_mc_intr gf100_mc_intr[] = { - { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ - { 0x00000001, NVDEV_ENGINE_MSPPP }, - { 0x00000020, NVDEV_ENGINE_CE0 }, - { 0x00000040, NVDEV_ENGINE_CE1 }, - { 0x00000080, NVDEV_ENGINE_CE2 }, - { 0x00000100, NVDEV_ENGINE_FIFO }, - { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00002000, NVDEV_SUBDEV_FB }, - { 0x00008000, NVDEV_ENGINE_MSVLD }, - { 0x00040000, NVDEV_SUBDEV_THERM }, - { 0x00020000, NVDEV_ENGINE_MSPDEC }, - { 0x00100000, NVDEV_SUBDEV_TIMER }, - { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ - { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ - { 0x01000000, NVDEV_SUBDEV_PMU }, - { 0x02000000, NVDEV_SUBDEV_LTC }, - { 0x08000000, NVDEV_SUBDEV_FB }, - { 0x10000000, NVDEV_SUBDEV_BUS }, - { 0x40000000, NVDEV_SUBDEV_IBUS }, - { 0x80000000, NVDEV_ENGINE_SW }, + { 0x04000000, NVKM_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ + { 0x00000001, NVKM_ENGINE_MSPPP }, + { 0x00000020, NVKM_ENGINE_CE0 }, + { 0x00000040, NVKM_ENGINE_CE1 }, + { 0x00000080, NVKM_ENGINE_CE2 }, + { 0x00000100, NVKM_ENGINE_FIFO }, + { 0x00001000, NVKM_ENGINE_GR }, + { 0x00002000, NVKM_SUBDEV_FB }, + { 0x00008000, NVKM_ENGINE_MSVLD }, + { 0x00040000, NVKM_SUBDEV_THERM }, + { 0x00020000, NVKM_ENGINE_MSPDEC }, + { 0x00100000, NVKM_SUBDEV_TIMER }, + { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */ + { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */ + { 0x01000000, NVKM_SUBDEV_PMU }, + { 0x02000000, NVKM_SUBDEV_LTC }, + { 0x08000000, NVKM_SUBDEV_FB }, + { 0x10000000, NVKM_SUBDEV_BUS }, + { 0x40000000, NVKM_SUBDEV_IBUS }, + { 0x80000000, NVKM_ENGINE_SW }, {}, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c index bcba7bc9737b..09dc2ebae7bc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.c @@ -25,16 +25,16 @@ const struct nvkm_mc_intr nv04_mc_intr[] = { - { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ - { 0x00000100, NVDEV_ENGINE_FIFO }, - { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00010000, NVDEV_ENGINE_DISP }, - { 0x00020000, NVDEV_ENGINE_VP }, /* NV40- */ - { 0x00100000, NVDEV_SUBDEV_TIMER }, - { 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */ - { 0x02000000, NVDEV_ENGINE_DISP }, /* NV11- PCRTC1 */ - { 0x10000000, NVDEV_SUBDEV_BUS }, - { 0x80000000, NVDEV_ENGINE_SW }, + { 0x00000001, NVKM_ENGINE_MPEG }, /* NV17- MPEG/ME */ + { 0x00000100, NVKM_ENGINE_FIFO }, + { 0x00001000, NVKM_ENGINE_GR }, + { 0x00010000, NVKM_ENGINE_DISP }, + { 0x00020000, NVKM_ENGINE_VP }, /* NV40- */ + { 0x00100000, NVKM_SUBDEV_TIMER }, + { 0x01000000, NVKM_ENGINE_DISP }, /* NV04- PCRTC0 */ + { 0x02000000, NVKM_ENGINE_DISP }, /* NV11- PCRTC1 */ + { 0x10000000, NVKM_SUBDEV_BUS }, + { 0x80000000, NVKM_ENGINE_SW }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c index b5a36c97e771..071789927615 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.c @@ -25,19 +25,19 @@ const struct nvkm_mc_intr nv50_mc_intr[] = { - { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ - { 0x00000001, NVDEV_ENGINE_MPEG }, - { 0x00000100, NVDEV_ENGINE_FIFO }, - { 0x00001000, NVDEV_ENGINE_GR }, - { 0x00004000, NVDEV_ENGINE_CIPHER }, /* NV84- */ - { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */ - { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */ - { 0x00100000, NVDEV_SUBDEV_TIMER }, - { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ - { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ - { 0x10000000, NVDEV_SUBDEV_BUS }, - { 0x80000000, NVDEV_ENGINE_SW }, - { 0x0002d101, NVDEV_SUBDEV_FB }, + { 0x04000000, NVKM_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ + { 0x00000001, NVKM_ENGINE_MPEG }, + { 0x00000100, NVKM_ENGINE_FIFO }, + { 0x00001000, NVKM_ENGINE_GR }, + { 0x00004000, NVKM_ENGINE_CIPHER }, /* NV84- */ + { 0x00008000, NVKM_ENGINE_BSP }, /* NV84- */ + { 0x00020000, NVKM_ENGINE_VP }, /* NV84- */ + { 0x00100000, NVKM_SUBDEV_TIMER }, + { 0x00200000, NVKM_SUBDEV_GPIO }, /* PMGR->GPIO */ + { 0x00200000, NVKM_SUBDEV_I2C }, /* PMGR->I2C/AUX */ + { 0x10000000, NVKM_SUBDEV_BUS }, + { 0x80000000, NVKM_ENGINE_SW }, + { 0x0002d101, NVKM_SUBDEV_FB }, {}, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index 5f6c5df15a95..7ac507c927bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -167,7 +167,7 @@ gf100_vm_flush(struct nvkm_vm *vm) u32 type; type = 0x00000001; /* PAGE_ALL */ - if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR])) + if (atomic_read(&vm->engref[NVKM_SUBDEV_BAR])) type |= 0x00000004; /* HUB_ONLY */ mutex_lock(&mmu->subdev.mutex); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index 21a990c1ac8b..a1f8d65f0276 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -161,29 +161,29 @@ nv50_vm_flush(struct nvkm_vm *vm) int i, vme; mutex_lock(&subdev->mutex); - for (i = 0; i < NVDEV_SUBDEV_NR; i++) { + for (i = 0; i < NVKM_SUBDEV_NR; i++) { if (!atomic_read(&vm->engref[i])) continue; /* unfortunate hw bug workaround... */ - if (i == NVDEV_ENGINE_GR && device->gr) { + if (i == NVKM_ENGINE_GR && device->gr) { int ret = nvkm_gr_tlb_flush(device->gr); if (ret != -ENODEV) continue; } switch (i) { - case NVDEV_ENGINE_GR : vme = 0x00; break; - case NVDEV_ENGINE_VP : - case NVDEV_ENGINE_MSPDEC: vme = 0x01; break; - case NVDEV_SUBDEV_BAR : vme = 0x06; break; - case NVDEV_ENGINE_MSPPP : - case NVDEV_ENGINE_MPEG : vme = 0x08; break; - case NVDEV_ENGINE_BSP : - case NVDEV_ENGINE_MSVLD : vme = 0x09; break; - case NVDEV_ENGINE_CIPHER: - case NVDEV_ENGINE_SEC : vme = 0x0a; break; - case NVDEV_ENGINE_CE0 : vme = 0x0d; break; + case NVKM_ENGINE_GR : vme = 0x00; break; + case NVKM_ENGINE_VP : + case NVKM_ENGINE_MSPDEC: vme = 0x01; break; + case NVKM_SUBDEV_BAR : vme = 0x06; break; + case NVKM_ENGINE_MSPPP : + case NVKM_ENGINE_MPEG : vme = 0x08; break; + case NVKM_ENGINE_BSP : + case NVKM_ENGINE_MSVLD : vme = 0x09; break; + case NVKM_ENGINE_CIPHER: + case NVKM_ENGINE_SEC : vme = 0x0a; break; + case NVKM_ENGINE_CE0 : vme = 0x0d; break; default: continue; } -- cgit v1.2.3 From 7e8820fed712c6de1933dcc91edbf08dcec74925 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:23 +1000 Subject: drm/nouveau/device: cleaner abstraction for device resource functions Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 8 ++--- drivers/gpu/drm/nouveau/nouveau_bo.c | 7 +++-- drivers/gpu/drm/nouveau/nouveau_chan.c | 3 +- drivers/gpu/drm/nouveau/nouveau_display.c | 3 +- drivers/gpu/drm/nouveau/nouveau_ttm.c | 5 ++-- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 34 ++-------------------- drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 16 ++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 27 +++++++++++++++-- drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 4 +-- .../gpu/drm/nouveau/nvkm/engine/disp/channv50.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c | 4 +-- .../gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h | 4 +-- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c | 6 ++-- drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c | 2 +- 18 files changed, 71 insertions(+), 62 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index b4974505af05..1fd0a07faadc 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -148,6 +148,8 @@ struct nvkm_device_func { int (*preinit)(struct nvkm_device *); int (*init)(struct nvkm_device *); void (*fini)(struct nvkm_device *, bool suspend); + resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar); + resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar); }; struct nvkm_device_quirk { @@ -242,12 +244,6 @@ nv_device_base(struct nvkm_device *device) &device->platformdev->dev; } -resource_size_t -nv_device_resource_start(struct nvkm_device *device, unsigned int bar); - -resource_size_t -nv_device_resource_len(struct nvkm_device *device, unsigned int bar); - struct platform_device; enum nv_bus_type { diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index bd33d547d574..6024edf8529e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -1351,6 +1351,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) { struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; struct nouveau_drm *drm = nouveau_bdev(bdev); + struct nvkm_device *device = nvxx_device(&drm->device); struct nvkm_mem *node = mem->mm_node; int ret; @@ -1379,7 +1380,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) /* fallthrough, tiled memory */ case TTM_PL_VRAM: mem->bus.offset = mem->start << PAGE_SHIFT; - mem->bus.base = nv_device_resource_start(nvxx_device(&drm->device), 1); + mem->bus.base = device->func->resource_addr(device, 1); mem->bus.is_iomem = true; if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { struct nvkm_bar *bar = nvxx_bar(&drm->device); @@ -1419,8 +1420,8 @@ nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) { struct nouveau_drm *drm = nouveau_bdev(bo->bdev); struct nouveau_bo *nvbo = nouveau_bo(bo); - struct nvif_device *device = &drm->device; - u32 mappable = nv_device_resource_len(nvxx_device(device), 1) >> PAGE_SHIFT; + struct nvkm_device *device = nvxx_device(&drm->device); + u32 mappable = device->func->resource_size(device, 1) >> PAGE_SHIFT; int i, ret; /* as long as the bo isn't in vram, and isn't tiled, we've got diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index 8c88c5e5bf0b..f59c4f5716cc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -150,7 +150,8 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, */ args.target = NV_DMA_V0_TARGET_PCI; args.access = NV_DMA_V0_ACCESS_RDWR; - args.start = nv_device_resource_start(nvxx_device(device), 1); + args.start = nvxx_device(device)->func-> + resource_addr(nvxx_device(device), 1); args.limit = args.start + device->info.ram_user - 1; } else { args.target = NV_DMA_V0_TARGET_VRAM; diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 5553caa16b9c..cc6c228e11c8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -445,6 +445,7 @@ int nouveau_display_create(struct drm_device *dev) { struct nouveau_drm *drm = nouveau_drm(dev); + struct nvkm_device *device = nvxx_device(&drm->device); struct nouveau_display *disp; int ret; @@ -457,7 +458,7 @@ nouveau_display_create(struct drm_device *dev) drm_mode_create_dvi_i_properties(dev); dev->mode_config.funcs = &nouveau_mode_config_funcs; - dev->mode_config.fb_base = nv_device_resource_start(nvxx_device(&drm->device), 1); + dev->mode_config.fb_base = device->func->resource_addr(device, 1); dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index d8999f71a798..1fd70d6900cf 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -335,6 +335,7 @@ nouveau_ttm_global_release(struct nouveau_drm *drm) int nouveau_ttm_init(struct nouveau_drm *drm) { + struct nvkm_device *device = nvxx_device(&drm->device); struct drm_device *dev = drm->dev; u32 bits; int ret; @@ -381,8 +382,8 @@ nouveau_ttm_init(struct nouveau_drm *drm) return ret; } - drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvxx_device(&drm->device), 1), - nv_device_resource_len(nvxx_device(&drm->device), 1)); + drm->ttm.mtrr = arch_phys_wc_add(device->func->resource_addr(device, 1), + device->func->resource_size(device, 1)); /* GART init */ if (drm->agp.stat != ENABLED) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 5fab8384d1f4..b8d46144e68a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2262,36 +2262,6 @@ fail: return ret; } -resource_size_t -nv_device_resource_start(struct nvkm_device *device, unsigned int bar) -{ - if (nv_device_is_pci(device)) { - return pci_resource_start(device->pdev, bar); - } else { - struct resource *res; - res = platform_get_resource(device->platformdev, - IORESOURCE_MEM, bar); - if (!res) - return 0; - return res->start; - } -} - -resource_size_t -nv_device_resource_len(struct nvkm_device *device, unsigned int bar) -{ - if (nv_device_is_pci(device)) { - return pci_resource_len(device->pdev, bar); - } else { - struct resource *res; - res = platform_get_resource(device->platformdev, - IORESOURCE_MEM, bar); - if (!res) - return 0; - return resource_size(res); - } -} - void nvkm_device_del(struct nvkm_device **pdevice) { @@ -2363,8 +2333,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, if (ret) goto done; - mmio_base = nv_device_resource_start(device, 0); - mmio_size = nv_device_resource_len(device, 0); + mmio_base = device->func->resource_addr(device, 0); + mmio_size = device->func->resource_size(device, 0); /* identify the chipset, and determine classes of subdev/engines */ if (detect) { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index 1a1d1e584a7f..75612faaca2c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c @@ -30,6 +30,20 @@ nvkm_device_pci(struct nvkm_device *device) return container_of(device, struct nvkm_device_pci, device); } +static resource_size_t +nvkm_device_pci_resource_addr(struct nvkm_device *device, unsigned bar) +{ + struct nvkm_device_pci *pdev = nvkm_device_pci(device); + return pci_resource_start(pdev->pdev, bar); +} + +static resource_size_t +nvkm_device_pci_resource_size(struct nvkm_device *device, unsigned bar) +{ + struct nvkm_device_pci *pdev = nvkm_device_pci(device); + return pci_resource_len(pdev->pdev, bar); +} + static void nvkm_device_pci_fini(struct nvkm_device *device, bool suspend) { @@ -68,6 +82,8 @@ nvkm_device_pci_func = { .dtor = nvkm_device_pci_dtor, .preinit = nvkm_device_pci_preinit, .fini = nvkm_device_pci_fini, + .resource_addr = nvkm_device_pci_resource_addr, + .resource_size = nvkm_device_pci_resource_size, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index 2587a17981b2..f4bc11c1671f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -26,9 +26,30 @@ #include "priv.h" static struct nvkm_device_tegra * -nvkm_device_tegra(struct nvkm_device *obj) +nvkm_device_tegra(struct nvkm_device *device) { - return container_of(obj, struct nvkm_device_tegra, device); + return container_of(device, struct nvkm_device_tegra, device); +} + +static struct resource * +nvkm_device_tegra_resource(struct nvkm_device *device, unsigned bar) +{ + struct nvkm_device_tegra *tdev = nvkm_device_tegra(device); + return platform_get_resource(tdev->pdev, IORESOURCE_MEM, bar); +} + +static resource_size_t +nvkm_device_tegra_resource_addr(struct nvkm_device *device, unsigned bar) +{ + struct resource *res = nvkm_device_tegra_resource(device, bar); + return res ? res->start : 0; +} + +static resource_size_t +nvkm_device_tegra_resource_size(struct nvkm_device *device, unsigned bar) +{ + struct resource *res = nvkm_device_tegra_resource(device, bar); + return res ? resource_size(res) : 0; } static irqreturn_t @@ -79,6 +100,8 @@ nvkm_device_tegra_func = { .tegra = nvkm_device_tegra, .init = nvkm_device_tegra_init, .fini = nvkm_device_tegra_fini, + .resource_addr = nvkm_device_tegra_resource_addr, + .resource_size = nvkm_device_tegra_resource_size, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index a948960cc056..eddf9b1d3340 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -198,8 +198,8 @@ nvkm_udevice_map(struct nvkm_object *object, u64 *addr, u32 *size) { struct nvkm_udevice *udev = nvkm_udevice(object); struct nvkm_device *device = udev->device; - *addr = nv_device_resource_start(device, 0); - *size = nv_device_resource_len(device, 0); + *addr = device->func->resource_addr(device, 0); + *size = device->func->resource_size(device, 0); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index c9cbfbd2a1ae..01803c0679b6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c @@ -195,7 +195,7 @@ nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size) struct nv50_disp_chan *chan = nv50_disp_chan(object); struct nv50_disp *disp = chan->root->disp; struct nvkm_device *device = disp->base.engine.subdev.device; - *addr = nv_device_resource_start(device, 0) + + *addr = device->func->resource_addr(device, 0) + 0x640000 + (chan->chid * 0x1000); *size = 0x001000; return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c index 9921482fc162..dc6d4678f228 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.c @@ -406,7 +406,7 @@ nvkm_fifo_chan_ctor(const struct nvkm_fifo_chan_func *func, spin_unlock_irqrestore(&fifo->lock, flags); /* determine address of this channel's user registers */ - chan->addr = nv_device_resource_start(device, bar) + + chan->addr = device->func->resource_addr(device, bar) + base + user * chan->chid; chan->size = user; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c index 32ea28a71a41..5caef65d3c6e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c @@ -296,7 +296,7 @@ nv20_gr_init(struct nvkm_gr *base) nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp); /* begin RAM config */ - vramsz = nv_device_resource_len(device, 1) - 1; + vramsz = device->func->resource_size(device, 1) - 1; nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204)); nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c index 7987df18415b..ffa902ece872 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c @@ -385,7 +385,7 @@ nv40_gr_init(struct nvkm_gr *base) } /* begin RAM config */ - vramsz = nv_device_resource_len(device, 1) - 1; + vramsz = device->func->resource_size(device, 1) - 1; switch (device->chipset) { case 0x40: nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200)); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 2eb0a370a3a0..c794b2c2d21e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -58,7 +58,7 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm, if (ret) return ret; - bar_len = nv_device_resource_len(device, bar_nr); + bar_len = device->func->resource_size(device, bar_nr); ret = nvkm_vm_new(device, 0, bar_len, 0, key, &vm); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c index fac54f97217e..370dcd8ff7b5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.c @@ -82,7 +82,7 @@ nv50_bar_oneinit(struct nvkm_bar *base) /* BAR3 */ start = 0x0100000000ULL; - limit = start + nv_device_resource_len(device, 3); + limit = start + device->func->resource_size(device, 3); ret = nvkm_vm_new(device, start, limit, start, &bar3_lock, &vm); if (ret) @@ -115,7 +115,7 @@ nv50_bar_oneinit(struct nvkm_bar *base) /* BAR1 */ start = 0x0000000000ULL; - limit = start + nv_device_resource_len(device, 1); + limit = start + device->func->resource_size(device, 1); ret = nvkm_vm_new(device, start, limit--, start, &bar1_lock, &vm); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h index 4e484c40b5c6..6c5bbff12eb4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/fbmem.h @@ -47,8 +47,8 @@ static inline struct io_mapping * fbmem_init(struct nvkm_device *dev) { - return io_mapping_create_wc(nv_device_resource_start(dev, 1), - nv_device_resource_len(dev, 1)); + return io_mapping_create_wc(dev->func->resource_addr(dev, 1), + dev->func->resource_size(dev, 1)); } static inline void diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c index a170ff9b32e7..c0543875e490 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c @@ -243,13 +243,13 @@ nv40_instmem_new(struct nvkm_device *device, int index, *pimem = &imem->base; /* map bar */ - if (nv_device_resource_len(device, 2)) + if (device->func->resource_size(device, 2)) bar = 2; else bar = 3; - imem->iomem = ioremap(nv_device_resource_start(device, bar), - nv_device_resource_len(device, bar)); + imem->iomem = ioremap(device->func->resource_addr(device, bar), + device->func->resource_size(device, bar)); if (!imem->iomem) { nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n"); return -EFAULT; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c index ec5020e3fc42..6d512c062ae3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c @@ -81,7 +81,7 @@ nv50_instobj_boot(struct nvkm_memory *memory, struct nvkm_vm *vm) ret = nvkm_vm_get(vm, size, 12, NV_MEM_ACCESS_RW, &iobj->bar); if (ret == 0) { - map = ioremap(nv_device_resource_start(device, 3) + + map = ioremap(device->func->resource_addr(device, 3) + (u32)iobj->bar.offset, size); if (map) { nvkm_memory_map(memory, &iobj->bar, 0); -- cgit v1.2.3 From 26c9e8effebb9166eb1cfba2d164676e98c505c7 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:23 +1000 Subject: drm/nouveau/device: remove pci/platform_device from common struct Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/device.h | 40 ++++++---------------- drivers/gpu/drm/nouveau/nouveau_abi16.c | 6 ++-- drivers/gpu/drm/nouveau/nouveau_acpi.c | 4 +-- drivers/gpu/drm/nouveau/nouveau_acpi.h | 4 +-- drivers/gpu/drm/nouveau/nouveau_agp.c | 7 ++-- drivers/gpu/drm/nouveau/nouveau_bo.c | 18 +++++----- drivers/gpu/drm/nouveau/nouveau_sysfs.c | 4 +-- drivers/gpu/drm/nouveau/nouveau_ttm.c | 2 +- drivers/gpu/drm/nouveau/nv50_display.c | 8 ++--- drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 14 ++------ drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c | 7 ++-- drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c | 5 +-- drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 24 ++++++++----- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 6 ++-- drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c | 6 ++-- .../gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c | 18 ++++++++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 9 +++-- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 9 +++-- .../gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c | 4 +-- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 5 +-- drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c | 2 +- 27 files changed, 106 insertions(+), 108 deletions(-) (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/gr') diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 5741bf228762..773951bfd200 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -47,13 +47,21 @@ enum nvkm_devidx { NVKM_ENGINE_SEC, NVKM_ENGINE_MSPDEC, - NVKM_SUBDEV_NR, + NVKM_SUBDEV_NR +}; + +enum nvkm_device_type { + NVKM_DEVICE_PCI, + NVKM_DEVICE_AGP, + NVKM_DEVICE_PCIE, + NVKM_DEVICE_TEGRA, }; struct nvkm_device { const struct nvkm_device_func *func; const struct nvkm_device_quirk *quirk; struct device *dev; + enum nvkm_device_type type; u64 handle; const char *name; const char *cfgopt; @@ -63,9 +71,6 @@ struct nvkm_device { struct mutex mutex; int refcount; - struct pci_dev *pdev; - struct platform_device *platformdev; - void __iomem *pri; struct nvkm_event event; @@ -150,6 +155,7 @@ struct nvkm_device_func { void (*fini)(struct nvkm_device *, bool suspend); resource_size_t (*resource_addr)(struct nvkm_device *, unsigned bar); resource_size_t (*resource_size)(struct nvkm_device *, unsigned bar); + bool cpu_coherent; }; struct nvkm_device_quirk { @@ -220,32 +226,6 @@ int nvkm_device_list(u64 *name, int size); _temp; \ }) -static inline bool -nv_device_is_pci(struct nvkm_device *device) -{ - return device->pdev != NULL; -} - -static inline bool -nv_device_is_cpu_coherent(struct nvkm_device *device) -{ - return (!IS_ENABLED(CONFIG_ARM) && nv_device_is_pci(device)); -} - -static inline struct device * -nv_device_base(struct nvkm_device *device) -{ - return nv_device_is_pci(device) ? &device->pdev->dev : - &device->platformdev->dev; -} - -struct platform_device; - -enum nv_bus_type { - NVKM_BUS_PCI, - NVKM_BUS_PLATFORM, -}; - void nvkm_device_del(struct nvkm_device **); struct nvkm_device_oclass { diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index 40a903b79343..4252e7796c4c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -174,19 +174,19 @@ nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) getparam->value = device->info.chipset; break; case NOUVEAU_GETPARAM_PCI_VENDOR: - if (nv_device_is_pci(nvxx_device(device))) + if (nvxx_device(device)->func->pci) getparam->value = dev->pdev->vendor; else getparam->value = 0; break; case NOUVEAU_GETPARAM_PCI_DEVICE: - if (nv_device_is_pci(nvxx_device(device))) + if (nvxx_device(device)->func->pci) getparam->value = dev->pdev->device; else getparam->value = 0; break; case NOUVEAU_GETPARAM_BUS_TYPE: - if (!nv_device_is_pci(nvxx_device(device))) + if (!nvxx_device(device)->func->pci) getparam->value = 3; else if (drm_pci_device_is_agp(dev)) diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c index 622424692b3b..df2d9818aba3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.c +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c @@ -372,12 +372,12 @@ static int nouveau_rom_call(acpi_handle rom_handle, uint8_t *bios, return len; } -bool nouveau_acpi_rom_supported(struct pci_dev *pdev) +bool nouveau_acpi_rom_supported(struct device *dev) { acpi_status status; acpi_handle dhandle, rom_handle; - dhandle = ACPI_HANDLE(&pdev->dev); + dhandle = ACPI_HANDLE(dev); if (!dhandle) return false; diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.h b/drivers/gpu/drm/nouveau/nouveau_acpi.h index 74acf0f87785..2f03653aff86 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.h +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.h @@ -10,7 +10,7 @@ void nouveau_register_dsm_handler(void); void nouveau_unregister_dsm_handler(void); void nouveau_switcheroo_optimus_dsm(void); int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); -bool nouveau_acpi_rom_supported(struct pci_dev *pdev); +bool nouveau_acpi_rom_supported(struct device *); void *nouveau_acpi_edid(struct drm_device *, struct drm_connector *); #else static inline bool nouveau_is_optimus(void) { return false; }; @@ -18,7 +18,7 @@ static inline bool nouveau_is_v1_dsm(void) { return false; }; static inline void nouveau_register_dsm_handler(void) {} static inline void nouveau_unregister_dsm_handler(void) {} static inline void nouveau_switcheroo_optimus_dsm(void) {} -static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } +static inline bool nouveau_acpi_rom_supported(struct device *dev) { return false; } static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } static inline void *nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return NULL; } #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.c b/drivers/gpu/drm/nouveau/nouveau_agp.c index 320f48c41fe0..c3f3e49e5f8f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_agp.c +++ b/drivers/gpu/drm/nouveau/nouveau_agp.c @@ -4,6 +4,8 @@ #include "nouveau_agp.h" #include "nouveau_reg.h" +#include + #if __OS_HAS_AGP MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)"); static int nouveau_agpmode = -1; @@ -28,6 +30,7 @@ static unsigned long get_agp_mode(struct nouveau_drm *drm, const struct drm_agp_info *info) { struct nvif_device *device = &drm->device; + struct pci_dev *pdev = nvxx_device(device)->func->pci(nvxx_device(device))->pdev; struct nouveau_agpmode_quirk *quirk = nouveau_agpmode_quirk_list; int agpmode = nouveau_agpmode; unsigned long mode = info->mode; @@ -45,8 +48,8 @@ get_agp_mode(struct nouveau_drm *drm, const struct drm_agp_info *info) while (agpmode == -1 && quirk->hostbridge_vendor) { if (info->id_vendor == quirk->hostbridge_vendor && info->id_device == quirk->hostbridge_device && - nvxx_device(device)->pdev->vendor == quirk->chip_vendor && - nvxx_device(device)->pdev->device == quirk->chip_device) { + pdev->vendor == quirk->chip_vendor && + pdev->device == quirk->chip_device) { agpmode = quirk->mode; NV_INFO(drm, "Forcing agp mode to %dX. Use agpmode to override.\n", agpmode); diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 6024edf8529e..373fbd2d14ff 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -209,7 +209,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, nvbo->tile_flags = tile_flags; nvbo->bo.bdev = &drm->ttm.bdev; - if (!nv_device_is_cpu_coherent(nvxx_device(&drm->device))) + if (!nvxx_device(&drm->device)->func->cpu_coherent) nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED; nvbo->page_shift = 12; @@ -466,8 +466,8 @@ nouveau_bo_sync_for_device(struct nouveau_bo *nvbo) return; for (i = 0; i < ttm_dma->ttm.num_pages; i++) - dma_sync_single_for_device(nv_device_base(device), - ttm_dma->dma_address[i], PAGE_SIZE, DMA_TO_DEVICE); + dma_sync_single_for_device(device->dev, ttm_dma->dma_address[i], + PAGE_SIZE, DMA_TO_DEVICE); } void @@ -486,8 +486,8 @@ nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo) return; for (i = 0; i < ttm_dma->ttm.num_pages; i++) - dma_sync_single_for_cpu(nv_device_base(device), - ttm_dma->dma_address[i], PAGE_SIZE, DMA_FROM_DEVICE); + dma_sync_single_for_cpu(device->dev, ttm_dma->dma_address[i], + PAGE_SIZE, DMA_FROM_DEVICE); } int @@ -1487,13 +1487,13 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) drm = nouveau_bdev(ttm->bdev); device = nvxx_device(&drm->device); dev = drm->dev; - pdev = nv_device_base(device); + pdev = device->dev; /* * Objects matching this condition have been marked as force_coherent, * so use the DMA API for them. */ - if (!nv_device_is_cpu_coherent(device) && + if (!nvxx_device(&drm->device)->func->cpu_coherent && ttm->caching_state == tt_uncached) return ttm_dma_populate(ttm_dma, dev->dev); @@ -1552,13 +1552,13 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) drm = nouveau_bdev(ttm->bdev); device = nvxx_device(&drm->device); dev = drm->dev; - pdev = nv_device_base(device); + pdev = device->dev; /* * Objects matching this condition have been marked as force_coherent, * so use the DMA API for them. */ - if (!nv_device_is_cpu_coherent(device) && + if (!nvxx_device(&drm->device)->func->cpu_coherent && ttm->caching_state == tt_uncached) { ttm_dma_unpopulate(ttm_dma, dev->dev); return; diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c index ce612064fa6a..d12a5faee047 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_sysfs.c @@ -165,7 +165,7 @@ nouveau_sysfs_fini(struct drm_device *dev) struct nvif_device *device = &drm->device; if (sysfs && sysfs->ctrl.priv) { - device_remove_file(nv_device_base(nvxx_device(device)), &dev_attr_pstate); + device_remove_file(nvxx_device(device)->dev, &dev_attr_pstate); nvif_object_fini(&sysfs->ctrl); } @@ -192,7 +192,7 @@ nouveau_sysfs_init(struct drm_device *dev) NVIF_IOCTL_NEW_V0_CONTROL, NULL, 0, &sysfs->ctrl); if (ret == 0) - device_create_file(nv_device_base(nvxx_device(device)), &dev_attr_pstate); + device_create_file(nvxx_device(device)->dev, &dev_attr_pstate); return 0; } diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 1fd70d6900cf..ba9fd151bd28 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -341,7 +341,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) int ret; bits = nvxx_mmu(&drm->device)->dma_bits; - if (nv_device_is_pci(nvxx_device(&drm->device))) { + if (nvxx_device(&drm->device)->func->pci) { if (drm->agp.stat == ENABLED || !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) bits = 32; diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 57b13602b2c5..4ae87aed4505 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -210,8 +210,8 @@ nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) nv50_chan_destroy(&dmac->base); if (dmac->ptr) { - struct pci_dev *pdev = nvxx_device(device)->pdev; - pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); + struct device *dev = nvxx_device(device)->dev; + dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle); } } @@ -226,8 +226,8 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, mutex_init(&dmac->lock); - dmac->ptr = pci_alloc_consistent(nvxx_device(device)->pdev, - PAGE_SIZE, &dmac->handle); + dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE, + &dmac->handle, GFP_KERNEL); if (!dmac->ptr) return -ENOMEM; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index b8d46144e68a..94a906b8cb88 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -2294,7 +2294,7 @@ nvkm_device_del(struct nvkm_device **pdevice) int nvkm_device_ctor(const struct nvkm_device_func *func, const struct nvkm_device_quirk *quirk, - void *dev, enum nv_bus_type type, u64 handle, + struct device *dev, enum nvkm_device_type type, u64 handle, const char *name, const char *cfg, const char *dbg, bool detect, bool mmio, u64 subdev_mask, struct nvkm_device *device) @@ -2312,16 +2312,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func, device->func = func; device->quirk = quirk; - switch (type) { - case NVKM_BUS_PCI: - device->pdev = dev; - device->dev = &device->pdev->dev; - break; - case NVKM_BUS_PLATFORM: - device->platformdev = dev; - device->dev = &device->platformdev->dev; - break; - } + device->dev = dev; + device->type = type; device->handle = handle; device->cfgopt = cfg; device->dbgopt = dbg; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index 8702a9efc7b4..9dd1cac81e80 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c @@ -1621,6 +1621,7 @@ nvkm_device_pci_func = { .fini = nvkm_device_pci_fini, .resource_addr = nvkm_device_pci_resource_addr, .resource_size = nvkm_device_pci_resource_size, + .cpu_coherent = !IS_ENABLED(CONFIG_ARM), }; int @@ -1671,8 +1672,10 @@ nvkm_device_pci_new(struct pci_dev *pci_dev, const char *cfg, const char *dbg, *pdevice = &pdev->device; pdev->pdev = pci_dev; - return nvkm_device_ctor(&nvkm_device_pci_func, quirk, - pci_dev, NVKM_BUS_PCI, + return nvkm_device_ctor(&nvkm_device_pci_func, quirk, &pci_dev->dev, + pci_is_pcie(pci_dev) ? NVKM_DEVICE_PCIE : + pci_find_capability(pci_dev, PCI_CAP_ID_AGP) ? + NVKM_DEVICE_AGP : NVKM_DEVICE_PCI, (u64)pci_domain_nr(pci_dev->bus) << 32 | pci_dev->bus->number << 16 | PCI_SLOT(pci_dev->devfn) << 8 | diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h index 6dea6e8fc854..ed3ad2c30e17 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/priv.h @@ -41,7 +41,7 @@ int nvkm_device_ctor(const struct nvkm_device_func *, const struct nvkm_device_quirk *, - void *, enum nv_bus_type type, u64 handle, + struct device *, enum nvkm_device_type, u64 handle, const char *name, const char *cfg, const char *dbg, bool detect, bool mmio, u64 subdev_mask, struct nvkm_device *); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index f4bc11c1671f..ada73e13d1af 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -102,6 +102,7 @@ nvkm_device_tegra_func = { .fini = nvkm_device_tegra_fini, .resource_addr = nvkm_device_tegra_resource_addr, .resource_size = nvkm_device_tegra_resource_size, + .cpu_coherent = false, }; int @@ -118,8 +119,8 @@ nvkm_device_tegra_new(struct platform_device *pdev, tdev->pdev = pdev; tdev->irq = -1; - return nvkm_device_ctor(&nvkm_device_tegra_func, NULL, pdev, - NVKM_BUS_PLATFORM, pdev->id, NULL, + return nvkm_device_ctor(&nvkm_device_tegra_func, NULL, &pdev->dev, + NVKM_DEVICE_TEGRA, pdev->id, NULL, cfg, dbg, detect, mmio, subdev_mask, &tdev->device); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c index eddf9b1d3340..1ae48f27029d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c @@ -70,16 +70,22 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size) args->v0.platform = NV_DEVICE_INFO_V0_IGP; break; default: - if (device->pdev) { - if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP)) - args->v0.platform = NV_DEVICE_INFO_V0_AGP; - else - if (pci_is_pcie(device->pdev)) - args->v0.platform = NV_DEVICE_INFO_V0_PCIE; - else - args->v0.platform = NV_DEVICE_INFO_V0_PCI; - } else { + switch (device->type) { + case NVKM_DEVICE_PCI: + args->v0.platform = NV_DEVICE_INFO_V0_PCI; + break; + case NVKM_DEVICE_AGP: + args->v0.platform = NV_DEVICE_INFO_V0_AGP; + break; + case NVKM_DEVICE_PCIE: + args->v0.platform = NV_DEVICE_INFO_V0_PCIE; + break; + case NVKM_DEVICE_TEGRA: args->v0.platform = NV_DEVICE_INFO_V0_SOC; + break; + default: + WARN_ON(1); + break; } break; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 2d11b328bee1..74000602fbb1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c @@ -190,7 +190,7 @@ nvkm_falcon_init(struct nvkm_engine *engine) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", device->chipset, falcon->addr >> 12); - ret = request_firmware(&fw, name, nv_device_base(device)); + ret = request_firmware(&fw, name, device->dev); if (ret == 0) { falcon->code.data = vmemdup(fw->data, fw->size); falcon->code.size = fw->size; @@ -209,7 +209,7 @@ nvkm_falcon_init(struct nvkm_engine *engine) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd", device->chipset, falcon->addr >> 12); - ret = request_firmware(&fw, name, nv_device_base(device)); + ret = request_firmware(&fw, name, device->dev); if (ret) { nvkm_error(subdev, "unable to load firmware data\n"); return -ENODEV; @@ -224,7 +224,7 @@ nvkm_falcon_init(struct nvkm_engine *engine) snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc", device->chipset, falcon->addr >> 12); - ret = request_firmware(&fw, name, nv_device_base(device)); + ret = request_firmware(&fw, name, device->dev); if (ret) { nvkm_error(subdev, "unable to load firmware code\n"); return -ENODEV; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index 1ad6785683f2..f1358a564e3e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1642,7 +1642,7 @@ gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname, } snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); - ret = request_firmware(&fw, f, nv_device_base(device)); + ret = request_firmware(&fw, f, device->dev); if (ret) { nvkm_error(subdev, "failed to load %s\n", fwname); return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index d6a2b9593538..a3d4f5bcec7a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -107,7 +107,7 @@ nvkm_xtensa_init(struct nvkm_engine *engine) snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x", xtensa->addr >> 12); - ret = request_firmware(&fw, name, nv_device_base(device)); + ret = request_firmware(&fw, name, device->dev); if (ret) { nvkm_warn(subdev, "unable to load firmware %s\n", name); return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c index b089a11ba08c..792f017525f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c @@ -134,7 +134,7 @@ shadow_fw_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) static void * shadow_fw_init(struct nvkm_bios *bios, const char *name) { - struct device *dev = &bios->subdev.device->pdev->dev; + struct device *dev = bios->subdev.device->dev; const struct firmware *fw; int ret = request_firmware(&fw, name, dev); if (ret) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c index 468066817c75..8fecb5ff22a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.c @@ -24,10 +24,10 @@ #if defined(CONFIG_ACPI) && defined(CONFIG_X86) int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); -bool nouveau_acpi_rom_supported(struct pci_dev *pdev); +bool nouveau_acpi_rom_supported(struct device *); #else static inline bool -nouveau_acpi_rom_supported(struct pci_dev *pdev) +nouveau_acpi_rom_supported(struct device *dev) { return false; } @@ -88,7 +88,7 @@ acpi_read_slow(void *data, u32 offset, u32 length, struct nvkm_bios *bios) static void * acpi_init(struct nvkm_bios *bios, const char *name) { - if (!nouveau_acpi_rom_supported(bios->subdev.device->pdev)) + if (!nouveau_acpi_rom_supported(bios->subdev.device->dev)) return ERR_PTR(-ENODEV); return NULL; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c index 0979bc89eeab..9b91da09dc5f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c @@ -22,6 +22,8 @@ */ #include "priv.h" +#include + struct priv { struct pci_dev *pdev; void __iomem *rom; @@ -51,10 +53,16 @@ pcirom_fini(void *data) static void * pcirom_init(struct nvkm_bios *bios, const char *name) { - struct pci_dev *pdev = bios->subdev.device->pdev; + struct nvkm_device *device = bios->subdev.device; struct priv *priv = NULL; + struct pci_dev *pdev; int ret; + if (device->func->pci) + pdev = device->func->pci(device)->pdev; + else + return ERR_PTR(-ENODEV); + if (!(ret = pci_enable_rom(pdev))) { if (ret = -ENOMEM, (priv = kmalloc(sizeof(*priv), GFP_KERNEL))) { @@ -83,10 +91,16 @@ nvbios_pcirom = { static void * platform_init(struct nvkm_bios *bios, const char *name) { - struct pci_dev *pdev = bios->subdev.device->pdev; + struct nvkm_device *device = bios->subdev.device; + struct pci_dev *pdev; struct priv *priv; int ret = -ENOMEM; + if (device->func->pci) + pdev = device->func->pci(device)->pdev; + else + return ERR_PTR(-ENODEV); + if ((priv = kmalloc(sizeof(*priv), GFP_KERNEL))) { if (ret = -ENODEV, (priv->rom = pci_platform_rom(pdev, &priv->size))) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index ef3149aa5124..008bb9849f3b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -65,7 +65,7 @@ gf100_fb_dtor(struct nvkm_fb *base) struct nvkm_device *device = fb->base.subdev.device; if (fb->r100c10_page) { - dma_unmap_page(nv_device_base(device), fb->r100c10, PAGE_SIZE, + dma_unmap_page(device->dev, fb->r100c10, PAGE_SIZE, DMA_BIDIRECTIONAL); __free_page(fb->r100c10_page); } @@ -86,10 +86,9 @@ gf100_fb_new_(const struct nvkm_fb_func *func, struct nvkm_device *device, fb->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (fb->r100c10_page) { - fb->r100c10 = dma_map_page(nv_device_base(device), - fb->r100c10_page, 0, PAGE_SIZE, - DMA_BIDIRECTIONAL); - if (dma_mapping_error(nv_device_base(device), fb->r100c10)) + fb->r100c10 = dma_map_page(device->dev, fb->r100c10_page, 0, + PAGE_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(device->dev, fb->r100c10)) return -EFAULT; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index c2b6ccde7473..f5edfadb5b46 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -234,7 +234,7 @@ nv50_fb_dtor(struct nvkm_fb *base) struct nvkm_device *device = fb->base.subdev.device; if (fb->r100c08_page) { - dma_unmap_page(nv_device_base(device), fb->r100c08, PAGE_SIZE, + dma_unmap_page(device->dev, fb->r100c08, PAGE_SIZE, DMA_BIDIRECTIONAL); __free_page(fb->r100c08_page); } @@ -265,10 +265,9 @@ nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device, fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); if (fb->r100c08_page) { - fb->r100c08 = dma_map_page(nv_device_base(device), - fb->r100c08_page, 0, PAGE_SIZE, - DMA_BIDIRECTIONAL); - if (dma_mapping_error(nv_device_base(device), fb->r100c08)) + fb->r100c08 = dma_map_page(device->dev, fb->r100c08_page, 0, + PAGE_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(device->dev, fb->r100c08)) return -EFAULT; } else { nvkm_warn(&fb->base.subdev, "failed 100c08 page alloc\n"); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index ab01989c3430..5ef04b72a80a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -186,7 +186,7 @@ gk20a_instobj_dtor_dma(struct gk20a_instobj *_node) { struct gk20a_instobj_dma *node = (void *)_node; struct gk20a_instmem *imem = _node->imem; - struct device *dev = nv_device_base(imem->base.subdev.device); + struct device *dev = imem->base.subdev.device->dev; if (unlikely(!node->cpuaddr)) return; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c index 5def412f0467..37927c3fdc3e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -110,8 +110,8 @@ nv04_mmu_dtor(struct nvkm_mmu *base) nvkm_vm_ref(NULL, &mmu->vm, NULL); } if (mmu->nullp) { - pci_free_consistent(device->pdev, 16 * 1024, - mmu->nullp, mmu->null); + dma_free_coherent(device->dev, 16 * 1024, + mmu->nullp, mmu->null); } return mmu; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index f30c3b890626..c6a26f907009 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -133,7 +133,7 @@ nv41_mmu = { int nv41_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) { - if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || + if (device->type == NVKM_DEVICE_AGP || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) return nv04_mmu_new(device, index, pmmu); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index 7c37bd84b862..a648c2395545 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -165,7 +165,8 @@ nv44_mmu_oneinit(struct nvkm_mmu *base) struct nvkm_device *device = mmu->base.subdev.device; int ret; - mmu->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &mmu->null); + mmu->nullp = dma_alloc_coherent(device->dev, 16 * 1024, + &mmu->null, GFP_KERNEL); if (!mmu->nullp) { nvkm_warn(&mmu->base.subdev, "unable to allocate dummy pages\n"); mmu->null = 0; @@ -227,7 +228,7 @@ nv44_mmu = { int nv44_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu) { - if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || + if (device->type == NVKM_DEVICE_AGP || !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) return nv04_mmu_new(device, index, pmmu); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c index 442b5e200a77..9700a7625012 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.c @@ -95,7 +95,7 @@ mxm_shadow_dsm(struct nvkm_mxm *mxm, u8 version) acpi_handle handle; int rev; - handle = ACPI_HANDLE(nv_device_base(device)); + handle = ACPI_HANDLE(device->dev); if (!handle) return false; -- cgit v1.2.3