From dbb025757a30cd225c5587685ae0971ecf301718 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sat, 28 Jan 2012 14:49:23 +0100 Subject: drm/i915: don't allow interlaced pipeconf on gen2 gen2 doesn't support it, so be a bit more paranoid and add a check to ensure that we never ever set an unsupported interlaced bit. Ensure that userspace can't set an interlaced mode by resetting interlace_allowed for the crt on gen2. dvo and lvds are the only other encoders that gen2 supports and these already disallow interlaced modes. Reviewed-by: Eugeni Dodonov Reviewed-by: Paulo Zanoni Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/intel_display.c') diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d588aec47904..1fde35d53608 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5385,7 +5385,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, } pipeconf &= ~PIPECONF_INTERLACE_MASK; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { + if (!IS_GEN2(dev) && + adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; /* the chip adds 2 halflines automatically */ adjusted_mode->crtc_vtotal -= 1; -- cgit v1.2.3