From adb9d5a2cc77e8aefe98fe4c11656c5b7025c248 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Fri, 14 Jan 2022 12:45:33 +0100 Subject: drm/dp: Move DisplayPort helpers into separate helper module Move DisplayPort functions into a separate module to reduce the size of the KMS helpers. Select DRM_DP_HELPER for all users of the code. To avoid naming conflicts, rename drm_dp_helper.c to drm_dp.c This change can help to reduce the size of the kernel binary. Some numbers from a x86-64 test build: Before: drm_kms_helper.ko: 447480 bytes After: drm_dp_helper.ko: 216632 bytes drm_kms_helper.ko: 239424 bytes For early-boot graphics, generic DRM drivers, such as simpledrm, require DRM KMS helpers to be built into the kernel. Generic helper functions for DisplayPort take up a significant portion of DRM KMS helper library. These functions are not used by generic drivers and can be loaded as a module. v3: * fix include statement in DRM selftests v2: * move DP helper code into dp/ (Jani) Signed-off-by: Thomas Zimmermann Acked-by: Lyude Paul Acked-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20220114114535.29157-4-tzimmermann@suse.de --- drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c | 530 +++++++++++++++++++++++++++ 1 file changed, 530 insertions(+) create mode 100644 drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c (limited to 'drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c') diff --git a/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c b/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c new file mode 100644 index 000000000000..9faf49354cab --- /dev/null +++ b/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c @@ -0,0 +1,530 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** + * DOC: dp dual mode helpers + * + * Helper functions to deal with DP dual mode (aka. DP++) adaptors. + * + * Type 1: + * Adaptor registers (if any) and the sink DDC bus may be accessed via I2C. + * + * Type 2: + * Adaptor registers and sink DDC bus can be accessed either via I2C or + * I2C-over-AUX. Source devices may choose to implement either of these + * access methods. + */ + +#define DP_DUAL_MODE_SLAVE_ADDRESS 0x40 + +/** + * drm_dp_dual_mode_read - Read from the DP dual mode adaptor register(s) + * @adapter: I2C adapter for the DDC bus + * @offset: register offset + * @buffer: buffer for return data + * @size: sizo of the buffer + * + * Reads @size bytes from the DP dual mode adaptor registers + * starting at @offset. + * + * Returns: + * 0 on success, negative error code on failure + */ +ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter, + u8 offset, void *buffer, size_t size) +{ + struct i2c_msg msgs[] = { + { + .addr = DP_DUAL_MODE_SLAVE_ADDRESS, + .flags = 0, + .len = 1, + .buf = &offset, + }, + { + .addr = DP_DUAL_MODE_SLAVE_ADDRESS, + .flags = I2C_M_RD, + .len = size, + .buf = buffer, + }, + }; + int ret; + + ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); + if (ret < 0) + return ret; + if (ret != ARRAY_SIZE(msgs)) + return -EPROTO; + + return 0; +} +EXPORT_SYMBOL(drm_dp_dual_mode_read); + +/** + * drm_dp_dual_mode_write - Write to the DP dual mode adaptor register(s) + * @adapter: I2C adapter for the DDC bus + * @offset: register offset + * @buffer: buffer for write data + * @size: sizo of the buffer + * + * Writes @size bytes to the DP dual mode adaptor registers + * starting at @offset. + * + * Returns: + * 0 on success, negative error code on failure + */ +ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter, + u8 offset, const void *buffer, size_t size) +{ + struct i2c_msg msg = { + .addr = DP_DUAL_MODE_SLAVE_ADDRESS, + .flags = 0, + .len = 1 + size, + .buf = NULL, + }; + void *data; + int ret; + + data = kmalloc(msg.len, GFP_KERNEL); + if (!data) + return -ENOMEM; + + msg.buf = data; + + memcpy(data, &offset, 1); + memcpy(data + 1, buffer, size); + + ret = i2c_transfer(adapter, &msg, 1); + + kfree(data); + + if (ret < 0) + return ret; + if (ret != 1) + return -EPROTO; + + return 0; +} +EXPORT_SYMBOL(drm_dp_dual_mode_write); + +static bool is_hdmi_adaptor(const char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN]) +{ + static const char dp_dual_mode_hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN] = + "DP-HDMI ADAPTOR\x04"; + + return memcmp(hdmi_id, dp_dual_mode_hdmi_id, + sizeof(dp_dual_mode_hdmi_id)) == 0; +} + +static bool is_type1_adaptor(uint8_t adaptor_id) +{ + return adaptor_id == 0 || adaptor_id == 0xff; +} + +static bool is_type2_adaptor(uint8_t adaptor_id) +{ + return adaptor_id == (DP_DUAL_MODE_TYPE_TYPE2 | + DP_DUAL_MODE_REV_TYPE2); +} + +static bool is_lspcon_adaptor(const char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN], + const uint8_t adaptor_id) +{ + return is_hdmi_adaptor(hdmi_id) && + (adaptor_id == (DP_DUAL_MODE_TYPE_TYPE2 | + DP_DUAL_MODE_TYPE_HAS_DPCD)); +} + +/** + * drm_dp_dual_mode_detect - Identify the DP dual mode adaptor + * @dev: &drm_device to use + * @adapter: I2C adapter for the DDC bus + * + * Attempt to identify the type of the DP dual mode adaptor used. + * + * Note that when the answer is @DRM_DP_DUAL_MODE_UNKNOWN it's not + * certain whether we're dealing with a native HDMI port or + * a type 1 DVI dual mode adaptor. The driver will have to use + * some other hardware/driver specific mechanism to make that + * distinction. + * + * Returns: + * The type of the DP dual mode adaptor used + */ +enum drm_dp_dual_mode_type drm_dp_dual_mode_detect(const struct drm_device *dev, + struct i2c_adapter *adapter) +{ + char hdmi_id[DP_DUAL_MODE_HDMI_ID_LEN] = {}; + uint8_t adaptor_id = 0x00; + ssize_t ret; + + /* + * Let's see if the adaptor is there the by reading the + * HDMI ID registers. + * + * Note that type 1 DVI adaptors are not required to implemnt + * any registers, and that presents a problem for detection. + * If the i2c transfer is nacked, we may or may not be dealing + * with a type 1 DVI adaptor. Some other mechanism of detecting + * the presence of the adaptor is required. One way would be + * to check the state of the CONFIG1 pin, Another method would + * simply require the driver to know whether the port is a DP++ + * port or a native HDMI port. Both of these methods are entirely + * hardware/driver specific so we can't deal with them here. + */ + ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_HDMI_ID, + hdmi_id, sizeof(hdmi_id)); + drm_dbg_kms(dev, "DP dual mode HDMI ID: %*pE (err %zd)\n", + ret ? 0 : (int)sizeof(hdmi_id), hdmi_id, ret); + if (ret) + return DRM_DP_DUAL_MODE_UNKNOWN; + + /* + * Sigh. Some (maybe all?) type 1 adaptors are broken and ack + * the offset but ignore it, and instead they just always return + * data from the start of the HDMI ID buffer. So for a broken + * type 1 HDMI adaptor a single byte read will always give us + * 0x44, and for a type 1 DVI adaptor it should give 0x00 + * (assuming it implements any registers). Fortunately neither + * of those values will match the type 2 signature of the + * DP_DUAL_MODE_ADAPTOR_ID register so we can proceed with + * the type 2 adaptor detection safely even in the presence + * of broken type 1 adaptors. + */ + ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_ADAPTOR_ID, + &adaptor_id, sizeof(adaptor_id)); + drm_dbg_kms(dev, "DP dual mode adaptor ID: %02x (err %zd)\n", adaptor_id, ret); + if (ret == 0) { + if (is_lspcon_adaptor(hdmi_id, adaptor_id)) + return DRM_DP_DUAL_MODE_LSPCON; + if (is_type2_adaptor(adaptor_id)) { + if (is_hdmi_adaptor(hdmi_id)) + return DRM_DP_DUAL_MODE_TYPE2_HDMI; + else + return DRM_DP_DUAL_MODE_TYPE2_DVI; + } + /* + * If neither a proper type 1 ID nor a broken type 1 adaptor + * as described above, assume type 1, but let the user know + * that we may have misdetected the type. + */ + if (!is_type1_adaptor(adaptor_id) && adaptor_id != hdmi_id[0]) + drm_err(dev, "Unexpected DP dual mode adaptor ID %02x\n", adaptor_id); + + } + + if (is_hdmi_adaptor(hdmi_id)) + return DRM_DP_DUAL_MODE_TYPE1_HDMI; + else + return DRM_DP_DUAL_MODE_TYPE1_DVI; +} +EXPORT_SYMBOL(drm_dp_dual_mode_detect); + +/** + * drm_dp_dual_mode_max_tmds_clock - Max TMDS clock for DP dual mode adaptor + * @dev: &drm_device to use + * @type: DP dual mode adaptor type + * @adapter: I2C adapter for the DDC bus + * + * Determine the max TMDS clock the adaptor supports based on the + * type of the dual mode adaptor and the DP_DUAL_MODE_MAX_TMDS_CLOCK + * register (on type2 adaptors). As some type 1 adaptors have + * problems with registers (see comments in drm_dp_dual_mode_detect()) + * we don't read the register on those, instead we simply assume + * a 165 MHz limit based on the specification. + * + * Returns: + * Maximum supported TMDS clock rate for the DP dual mode adaptor in kHz. + */ +int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum drm_dp_dual_mode_type type, + struct i2c_adapter *adapter) +{ + uint8_t max_tmds_clock; + ssize_t ret; + + /* native HDMI so no limit */ + if (type == DRM_DP_DUAL_MODE_NONE) + return 0; + + /* + * Type 1 adaptors are limited to 165MHz + * Type 2 adaptors can tells us their limit + */ + if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) + return 165000; + + ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_MAX_TMDS_CLOCK, + &max_tmds_clock, sizeof(max_tmds_clock)); + if (ret || max_tmds_clock == 0x00 || max_tmds_clock == 0xff) { + drm_dbg_kms(dev, "Failed to query max TMDS clock\n"); + return 165000; + } + + return max_tmds_clock * 5000 / 2; +} +EXPORT_SYMBOL(drm_dp_dual_mode_max_tmds_clock); + +/** + * drm_dp_dual_mode_get_tmds_output - Get the state of the TMDS output buffers in the DP dual mode adaptor + * @dev: &drm_device to use + * @type: DP dual mode adaptor type + * @adapter: I2C adapter for the DDC bus + * @enabled: current state of the TMDS output buffers + * + * Get the state of the TMDS output buffers in the adaptor. For + * type2 adaptors this is queried from the DP_DUAL_MODE_TMDS_OEN + * register. As some type 1 adaptors have problems with registers + * (see comments in drm_dp_dual_mode_detect()) we don't read the + * register on those, instead we simply assume that the buffers + * are always enabled. + * + * Returns: + * 0 on success, negative error code on failure + */ +int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev, + enum drm_dp_dual_mode_type type, struct i2c_adapter *adapter, + bool *enabled) +{ + uint8_t tmds_oen; + ssize_t ret; + + if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) { + *enabled = true; + return 0; + } + + ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_TMDS_OEN, + &tmds_oen, sizeof(tmds_oen)); + if (ret) { + drm_dbg_kms(dev, "Failed to query state of TMDS output buffers\n"); + return ret; + } + + *enabled = !(tmds_oen & DP_DUAL_MODE_TMDS_DISABLE); + + return 0; +} +EXPORT_SYMBOL(drm_dp_dual_mode_get_tmds_output); + +/** + * drm_dp_dual_mode_set_tmds_output - Enable/disable TMDS output buffers in the DP dual mode adaptor + * @dev: &drm_device to use + * @type: DP dual mode adaptor type + * @adapter: I2C adapter for the DDC bus + * @enable: enable (as opposed to disable) the TMDS output buffers + * + * Set the state of the TMDS output buffers in the adaptor. For + * type2 this is set via the DP_DUAL_MODE_TMDS_OEN register. As + * some type 1 adaptors have problems with registers (see comments + * in drm_dp_dual_mode_detect()) we avoid touching the register, + * making this function a no-op on type 1 adaptors. + * + * Returns: + * 0 on success, negative error code on failure + */ +int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type, + struct i2c_adapter *adapter, bool enable) +{ + uint8_t tmds_oen = enable ? 0 : DP_DUAL_MODE_TMDS_DISABLE; + ssize_t ret; + int retry; + + if (type < DRM_DP_DUAL_MODE_TYPE2_DVI) + return 0; + + /* + * LSPCON adapters in low-power state may ignore the first write, so + * read back and verify the written value a few times. + */ + for (retry = 0; retry < 3; retry++) { + uint8_t tmp; + + ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_TMDS_OEN, + &tmds_oen, sizeof(tmds_oen)); + if (ret) { + drm_dbg_kms(dev, "Failed to %s TMDS output buffers (%d attempts)\n", + enable ? "enable" : "disable", retry + 1); + return ret; + } + + ret = drm_dp_dual_mode_read(adapter, DP_DUAL_MODE_TMDS_OEN, + &tmp, sizeof(tmp)); + if (ret) { + drm_dbg_kms(dev, + "I2C read failed during TMDS output buffer %s (%d attempts)\n", + enable ? "enabling" : "disabling", retry + 1); + return ret; + } + + if (tmp == tmds_oen) + return 0; + } + + drm_dbg_kms(dev, "I2C write value mismatch during TMDS output buffer %s\n", + enable ? "enabling" : "disabling"); + + return -EIO; +} +EXPORT_SYMBOL(drm_dp_dual_mode_set_tmds_output); + +/** + * drm_dp_get_dual_mode_type_name - Get the name of the DP dual mode adaptor type as a string + * @type: DP dual mode adaptor type + * + * Returns: + * String representation of the DP dual mode adaptor type + */ +const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type) +{ + switch (type) { + case DRM_DP_DUAL_MODE_NONE: + return "none"; + case DRM_DP_DUAL_MODE_TYPE1_DVI: + return "type 1 DVI"; + case DRM_DP_DUAL_MODE_TYPE1_HDMI: + return "type 1 HDMI"; + case DRM_DP_DUAL_MODE_TYPE2_DVI: + return "type 2 DVI"; + case DRM_DP_DUAL_MODE_TYPE2_HDMI: + return "type 2 HDMI"; + case DRM_DP_DUAL_MODE_LSPCON: + return "lspcon"; + default: + WARN_ON(type != DRM_DP_DUAL_MODE_UNKNOWN); + return "unknown"; + } +} +EXPORT_SYMBOL(drm_dp_get_dual_mode_type_name); + +/** + * drm_lspcon_get_mode: Get LSPCON's current mode of operation by + * reading offset (0x80, 0x41) + * @dev: &drm_device to use + * @adapter: I2C-over-aux adapter + * @mode: current lspcon mode of operation output variable + * + * Returns: + * 0 on success, sets the current_mode value to appropriate mode + * -error on failure + */ +int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter *adapter, + enum drm_lspcon_mode *mode) +{ + u8 data; + int ret = 0; + int retry; + + if (!mode) { + drm_err(dev, "NULL input\n"); + return -EINVAL; + } + + /* Read Status: i2c over aux */ + for (retry = 0; retry < 6; retry++) { + if (retry) + usleep_range(500, 1000); + + ret = drm_dp_dual_mode_read(adapter, + DP_DUAL_MODE_LSPCON_CURRENT_MODE, + &data, sizeof(data)); + if (!ret) + break; + } + + if (ret < 0) { + drm_dbg_kms(dev, "LSPCON read(0x80, 0x41) failed\n"); + return -EFAULT; + } + + if (data & DP_DUAL_MODE_LSPCON_MODE_PCON) + *mode = DRM_LSPCON_MODE_PCON; + else + *mode = DRM_LSPCON_MODE_LS; + return 0; +} +EXPORT_SYMBOL(drm_lspcon_get_mode); + +/** + * drm_lspcon_set_mode: Change LSPCON's mode of operation by + * writing offset (0x80, 0x40) + * @dev: &drm_device to use + * @adapter: I2C-over-aux adapter + * @mode: required mode of operation + * + * Returns: + * 0 on success, -error on failure/timeout + */ +int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter *adapter, + enum drm_lspcon_mode mode) +{ + u8 data = 0; + int ret; + int time_out = 200; + enum drm_lspcon_mode current_mode; + + if (mode == DRM_LSPCON_MODE_PCON) + data = DP_DUAL_MODE_LSPCON_MODE_PCON; + + /* Change mode */ + ret = drm_dp_dual_mode_write(adapter, DP_DUAL_MODE_LSPCON_MODE_CHANGE, + &data, sizeof(data)); + if (ret < 0) { + drm_err(dev, "LSPCON mode change failed\n"); + return ret; + } + + /* + * Confirm mode change by reading the status bit. + * Sometimes, it takes a while to change the mode, + * so wait and retry until time out or done. + */ + do { + ret = drm_lspcon_get_mode(dev, adapter, ¤t_mode); + if (ret) { + drm_err(dev, "can't confirm LSPCON mode change\n"); + return ret; + } else { + if (current_mode != mode) { + msleep(10); + time_out -= 10; + } else { + drm_dbg_kms(dev, "LSPCON mode changed to %s\n", + mode == DRM_LSPCON_MODE_LS ? "LS" : "PCON"); + return 0; + } + } + } while (time_out); + + drm_err(dev, "LSPCON mode change timed out\n"); + return -ETIMEDOUT; +} +EXPORT_SYMBOL(drm_lspcon_set_mode); -- cgit v1.2.3 From 5b529e8d9c387a34ca2b8008dc65f55d539b3ef6 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Fri, 14 Jan 2022 12:45:34 +0100 Subject: drm/dp: Move public DisplayPort headers into dp/ Move all public DisplayPort headers into dp/ and update users. No functional changes. v3: * rebased onto latest drm-tip Signed-off-by: Thomas Zimmermann Acked-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20220114114535.29157-5-tzimmermann@suse.de --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c | 2 +- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 +- drivers/gpu/drm/amd/display/dc/os_types.h | 2 +- drivers/gpu/drm/amd/display/include/dpcd_defs.h | 2 +- drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h | 2 +- drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 2 +- drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c | 2 +- .../gpu/drm/bridge/analogix/analogix-i2c-dptx.c | 2 +- drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +- drivers/gpu/drm/bridge/analogix/anx7625.c | 2 +- .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 2 +- .../gpu/drm/bridge/cadence/cdns-mhdp8546-core.h | 2 +- drivers/gpu/drm/bridge/parade-ps8640.c | 2 +- drivers/gpu/drm/bridge/tc358767.c | 2 +- drivers/gpu/drm/bridge/tc358775.c | 2 +- drivers/gpu/drm/bridge/ti-sn65dsi86.c | 2 +- drivers/gpu/drm/dp/drm_dp.c | 4 +- drivers/gpu/drm/dp/drm_dp_aux_dev.c | 4 +- drivers/gpu/drm/dp/drm_dp_cec.c | 2 +- drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c | 2 +- drivers/gpu/drm/dp/drm_dp_mst_topology.c | 2 +- drivers/gpu/drm/dp/drm_dp_mst_topology_internal.h | 2 +- drivers/gpu/drm/drm_dp_aux_bus.c | 2 +- drivers/gpu/drm/drm_dsc.c | 2 +- drivers/gpu/drm/gma500/cdv_intel_dp.c | 2 +- drivers/gpu/drm/gma500/intel_bios.c | 2 +- drivers/gpu/drm/i915/display/intel_bios.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 4 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 +- .../gpu/drm/i915/display/intel_dp_link_training.h | 2 +- drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +- drivers/gpu/drm/msm/dp/dp_audio.c | 2 +- drivers/gpu/drm/msm/dp/dp_aux.h | 2 +- drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +- drivers/gpu/drm/nouveau/nouveau_connector.h | 2 +- drivers/gpu/drm/nouveau/nouveau_dp.c | 2 +- drivers/gpu/drm/nouveau/nouveau_encoder.h | 4 +- drivers/gpu/drm/panel/panel-edp.c | 2 +- drivers/gpu/drm/panel/panel-samsung-atna33xc20.c | 2 +- drivers/gpu/drm/radeon/atombios_dp.c | 2 +- drivers/gpu/drm/radeon/radeon_connectors.c | 2 +- drivers/gpu/drm/radeon/radeon_dp_mst.c | 2 +- drivers/gpu/drm/radeon/radeon_mode.h | 4 +- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 2 +- drivers/gpu/drm/rockchip/cdn-dp-core.c | 2 +- drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +- drivers/gpu/drm/rockchip/rockchip_lvds.c | 2 +- drivers/gpu/drm/rockchip/rockchip_rgb.c | 2 +- drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c | 2 +- drivers/gpu/drm/tegra/dp.c | 2 +- drivers/gpu/drm/tegra/dpaux.c | 2 +- drivers/gpu/drm/tegra/sor.c | 2 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- include/drm/dp/drm_dp_dual_mode_helper.h | 121 + include/drm/dp/drm_dp_helper.h | 2358 ++++++++++++++++++++ include/drm/dp/drm_dp_mst_helper.h | 972 ++++++++ include/drm/drm_dp_dual_mode_helper.h | 121 - include/drm/drm_dp_helper.h | 2358 -------------------- include/drm/drm_dp_mst_helper.h | 972 -------- include/drm/drm_dsc.h | 2 +- 70 files changed, 3523 insertions(+), 3523 deletions(-) create mode 100644 include/drm/dp/drm_dp_dual_mode_helper.h create mode 100644 include/drm/dp/drm_dp_helper.h create mode 100644 include/drm/dp/drm_dp_mst_helper.h delete mode 100644 include/drm/drm_dp_dual_mode_helper.h delete mode 100644 include/drm/drm_dp_helper.h delete mode 100644 include/drm/drm_dp_mst_helper.h (limited to 'drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 0de66f59adb8..19c4d9225197 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include #include #include "amdgpu.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 6043bf6fd414..902235fae4cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #include #include @@ -44,7 +44,7 @@ #include #include "amdgpu_irq.h" -#include +#include #include "modules/inc/mod_freesync.h" #include "amdgpu_dm_irq_params.h" diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index f327becb022f..49a2f594fb2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -34,7 +34,7 @@ #include "atombios_dp.h" #include "amdgpu_connectors.h" #include "amdgpu_atombios.h" -#include +#include /* move these to drm_dp_helper.c/h */ #define DP_LINK_CONFIGURATION_SIZE 9 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 116a280d8a20..046506ff0532 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -76,7 +76,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index bb65f41d1a59..bec1de86e2ef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include /* diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index cc34a35d0bcb..35c944a8e74d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -25,8 +25,8 @@ #include #include -#include -#include +#include +#include #include "dm_services.h" #include "amdgpu.h" #include "amdgpu_dm.h" diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c index 7f25c11f4248..48a18766f002 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dpcd.c @@ -27,7 +27,7 @@ #include #include #include -#include "drm/drm_dp_helper.h" +#include #include #include "dm_helpers.h" diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 9c74564cbd8d..efc2339f1fa0 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -25,7 +25,7 @@ #include #include "dc_hw_types.h" #include "dsc.h" -#include +#include #include "dc.h" #include "rc_calc.h" #include "fixed31_32.h" diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h index 5df1d80c8341..17d05071b809 100644 --- a/drivers/gpu/drm/amd/display/dc/os_types.h +++ b/drivers/gpu/drm/amd/display/dc/os_types.h @@ -36,7 +36,7 @@ #include #include -#include +#include #include "cgs_common.h" diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index ffd0df1701e6..270260e82b61 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -26,7 +26,7 @@ #ifndef __DAL_DPCD_DEFS_H__ #define __DAL_DPCD_DEFS_H__ -#include +#include #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h #define DP_SINK_HW_REVISION_START 0x409 #endif diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h index 399fbca8947b..8502263d2968 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp.h @@ -30,7 +30,7 @@ #include "hdcp_log.h" #include -#include +#include enum mod_hdcp_trans_input_result { UNKNOWN = 0, diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c index e33cd077595a..94e56a2e91f2 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c index 5e6a0ed39199..2768b41c48e9 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c index fe40bab21530..e8297168bfef 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-i2c-dptx.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include #include "analogix-i2c-dptx.h" diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h index c051502d7fbf..32665203a6ae 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h @@ -10,7 +10,7 @@ #define _ANALOGIX_DP_CORE_H #include -#include +#include #define DP_TIMEOUT_LOOP_COUNT 100 #define MAX_CR_LOOP 5 diff --git a/drivers/gpu/drm/bridge/analogix/anx7625.c b/drivers/gpu/drm/bridge/analogix/anx7625.c index 33383f83255d..0528c3c6168d 100644 --- a/drivers/gpu/drm/bridge/analogix/anx7625.c +++ b/drivers/gpu/drm/bridge/analogix/anx7625.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index 5530fbf64f1e..ac9e64169c6f 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c @@ -41,7 +41,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h index c74439d0b1a7..fc77f987c835 100644 --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h @@ -17,7 +17,7 @@ #include #include -#include +#include struct clk; struct device; diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 54723f068884..3e0c7436f407 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 23a6f90b694b..c23e0abc65e8 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c index 4ad4fc251b93..695af3badcc7 100644 --- a/drivers/gpu/drm/bridge/tc358775.c +++ b/drivers/gpu/drm/bridge/tc358775.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c index dab8f76618f3..65d25ce30ce5 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index e995a0262ed7..6d43325acca5 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -29,10 +29,10 @@ #include #include -#include +#include #include #include -#include +#include #include #include "drm_dp_helper_internal.h" diff --git a/drivers/gpu/drm/dp/drm_dp_aux_dev.c b/drivers/gpu/drm/dp/drm_dp_aux_dev.c index 0618dfe16660..53ad4e72790b 100644 --- a/drivers/gpu/drm/dp/drm_dp_aux_dev.c +++ b/drivers/gpu/drm/dp/drm_dp_aux_dev.c @@ -36,8 +36,8 @@ #include #include -#include -#include +#include +#include #include #include "drm_dp_helper_internal.h" diff --git a/drivers/gpu/drm/dp/drm_dp_cec.c b/drivers/gpu/drm/dp/drm_dp_cec.c index 3ab2609f9ec7..f9e927355879 100644 --- a/drivers/gpu/drm/dp/drm_dp_cec.c +++ b/drivers/gpu/drm/dp/drm_dp_cec.c @@ -13,7 +13,7 @@ #include #include -#include +#include /* * Unfortunately it turns out that we have a chicken-and-egg situation diff --git a/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c b/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c index 9faf49354cab..2049cb0f7ed0 100644 --- a/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c +++ b/drivers/gpu/drm/dp/drm_dp_dual_mode_helper.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include /** diff --git a/drivers/gpu/drm/dp/drm_dp_mst_topology.c b/drivers/gpu/drm/dp/drm_dp_mst_topology.c index bc3237a09c06..ddb9aa051288 100644 --- a/drivers/gpu/drm/dp/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/dp/drm_dp_mst_topology.c @@ -38,9 +38,9 @@ #include #endif +#include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/dp/drm_dp_mst_topology_internal.h b/drivers/gpu/drm/dp/drm_dp_mst_topology_internal.h index eeda9a61c657..401953b59d45 100644 --- a/drivers/gpu/drm/dp/drm_dp_mst_topology_internal.h +++ b/drivers/gpu/drm/dp/drm_dp_mst_topology_internal.h @@ -10,7 +10,7 @@ #ifndef _DRM_DP_MST_HELPER_INTERNAL_H_ #define _DRM_DP_MST_HELPER_INTERNAL_H_ -#include +#include void drm_dp_encode_sideband_req(const struct drm_dp_sideband_msg_req_body *req, diff --git a/drivers/gpu/drm/drm_dp_aux_bus.c b/drivers/gpu/drm/drm_dp_aux_bus.c index 298ea7a49591..565edf6b1732 100644 --- a/drivers/gpu/drm/drm_dp_aux_bus.c +++ b/drivers/gpu/drm/drm_dp_aux_bus.c @@ -20,7 +20,7 @@ #include #include -#include +#include /** * dp_aux_ep_match() - The match function for the dp_aux_bus. diff --git a/drivers/gpu/drm/drm_dsc.c b/drivers/gpu/drm/drm_dsc.c index 46a3c1b62463..fdd8d5f42622 100644 --- a/drivers/gpu/drm/drm_dsc.c +++ b/drivers/gpu/drm/drm_dsc.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include /** diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c index 74e67679714e..f562e91337c7 100644 --- a/drivers/gpu/drm/gma500/cdv_intel_dp.c +++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c @@ -31,7 +31,7 @@ #include #include -#include +#include #include #include "gma_display.h" diff --git a/drivers/gpu/drm/gma500/intel_bios.c b/drivers/gpu/drm/gma500/intel_bios.c index d5ca5f241974..ea7c16f33a0e 100644 --- a/drivers/gpu/drm/gma500/intel_bios.c +++ b/drivers/gpu/drm/gma500/intel_bios.c @@ -6,7 +6,7 @@ * Eric Anholt */ #include -#include +#include #include "intel_bios.h" #include "psb_drv.h" diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 2b1423a43437..41d37a8c5c8f 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -25,7 +25,7 @@ * */ -#include +#include #include "display/intel_display.h" #include "display/intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index badf035efaeb..df4c1a17ba5f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index b9c967837872..0d68dec6ac83 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -32,10 +32,10 @@ #include #include +#include +#include #include #include -#include -#include #include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5a8206298691..d8a0f7a2b939 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -36,7 +36,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 540a669e01dd..82d024dafe7b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -6,8 +6,8 @@ * Sean Paul */ -#include -#include +#include +#include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 6a3a7b37349a..dbfb15705aaa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -6,7 +6,7 @@ #ifndef __INTEL_DP_LINK_TRAINING_H__ #define __INTEL_DP_LINK_TRAINING_H__ -#include +#include struct intel_crtc_state; struct intel_dp; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 05d2d750fa53..e879d36c31ad 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -24,7 +24,7 @@ */ #include -#include +#include #include #include "intel_de.h" diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index d7e4a39a904e..4553f4985434 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -8,7 +8,7 @@ #include -#include +#include #include #include "dp_catalog.h" diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index 0728cc09c9ec..82afc8d5210f 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -7,7 +7,7 @@ #define _DP_AUX_H_ #include "dp_catalog.h" -#include +#include int dp_aux_register(struct drm_dp_aux *dp_aux); void dp_aux_unregister(struct drm_dp_aux *dp_aux); diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 6ae9b29044b6..8a6d3ead3440 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include "dp_catalog.h" diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 62e75dc8afc6..ecf20458c75e 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include "dp_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index ae1f41205520..df58c6445c51 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -35,7 +35,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h index 40f90e353540..1b173191cc41 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.h +++ b/drivers/gpu/drm/nouveau/nouveau_connector.h @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include "nouveau_crtc.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index 3a288d0b848f..724d40ddd452 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -22,7 +22,7 @@ * Authors: Ben Skeggs */ -#include +#include #include "nouveau_drv.h" #include "nouveau_connector.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h index 77c2fed76e8b..65ed84f88cca 100644 --- a/drivers/gpu/drm/nouveau/nouveau_encoder.h +++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h @@ -30,8 +30,8 @@ #include #include -#include -#include +#include +#include #include "dispnv04/disp.h" struct nv50_head_atom; struct nouveau_connector; diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index 176ef0c3cc1d..6a6ca891ee2e 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -37,7 +37,7 @@ #include #include #include -#include +#include #include /** diff --git a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c b/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c index 221db6512859..bffeadaaf9a2 100644 --- a/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c +++ b/drivers/gpu/drm/panel/panel-samsung-atna33xc20.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 4c1e551d9714..4798cf23d251 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -30,7 +30,7 @@ #include "atom.h" #include "atom-bits.h" -#include +#include /* move these to drm_dp_helper.c/h */ #define DP_LINK_CONFIGURATION_SIZE 9 diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 607ad5620bd9..82d37a85bfc8 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -27,7 +27,7 @@ #include #include #include -#include +#include #include #include #include "radeon.h" diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 751c2c075e09..9f26baf7adb0 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT -#include +#include #include #include #include diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index fe16f140a6b4..5288dc7a4897 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -33,8 +33,8 @@ #include #include #include -#include -#include +#include +#include #include #include #include diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 8abb5ac26807..c61d37f02af7 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index 16497c31d9f9..4740cc14beb8 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.h b/drivers/gpu/drm/rockchip/cdn-dp-core.h index 81ac9b658a70..0d044146f4e9 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.h +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.h @@ -7,7 +7,7 @@ #ifndef _CDN_DP_CORE_H #define _CDN_DP_CORE_H -#include +#include #include #include diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index be74c87a8be4..0b972418067e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index 09be9678f2bd..2494b079489d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c index 784048cb3c61..4004e6dc14de 100644 --- a/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c +++ b/drivers/gpu/drm/selftests/test-drm_dp_mst_helper.c @@ -7,7 +7,7 @@ #include -#include +#include #include #include "../dp/drm_dp_mst_topology_internal.h" diff --git a/drivers/gpu/drm/tegra/dp.c b/drivers/gpu/drm/tegra/dp.c index 70dfb7d1dec5..e4369e5b2943 100644 --- a/drivers/gpu/drm/tegra/dp.c +++ b/drivers/gpu/drm/tegra/dp.c @@ -5,7 +5,7 @@ */ #include -#include +#include #include #include "dp.h" diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 1f96e416fa08..8ca500977a46 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include "dp.h" diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 0ea320c1092b..b125572feb84 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -18,7 +18,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 6f588dc09ba6..b1bbbb1d0a54 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/drm/dp/drm_dp_dual_mode_helper.h b/include/drm/dp/drm_dp_dual_mode_helper.h new file mode 100644 index 000000000000..7ee482265087 --- /dev/null +++ b/include/drm/dp/drm_dp_dual_mode_helper.h @@ -0,0 +1,121 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef DRM_DP_DUAL_MODE_HELPER_H +#define DRM_DP_DUAL_MODE_HELPER_H + +#include + +/* + * Optional for type 1 DVI adaptors + * Mandatory for type 1 HDMI and type 2 adaptors + */ +#define DP_DUAL_MODE_HDMI_ID 0x00 /* 00-0f */ +#define DP_DUAL_MODE_HDMI_ID_LEN 16 +/* + * Optional for type 1 adaptors + * Mandatory for type 2 adaptors + */ +#define DP_DUAL_MODE_ADAPTOR_ID 0x10 +#define DP_DUAL_MODE_REV_MASK 0x07 +#define DP_DUAL_MODE_REV_TYPE2 0x00 +#define DP_DUAL_MODE_TYPE_MASK 0xf0 +#define DP_DUAL_MODE_TYPE_TYPE2 0xa0 +/* This field is marked reserved in dual mode spec, used in LSPCON */ +#define DP_DUAL_MODE_TYPE_HAS_DPCD 0x08 +#define DP_DUAL_MODE_IEEE_OUI 0x11 /* 11-13*/ +#define DP_DUAL_IEEE_OUI_LEN 3 +#define DP_DUAL_DEVICE_ID 0x14 /* 14-19 */ +#define DP_DUAL_DEVICE_ID_LEN 6 +#define DP_DUAL_MODE_HARDWARE_REV 0x1a +#define DP_DUAL_MODE_FIRMWARE_MAJOR_REV 0x1b +#define DP_DUAL_MODE_FIRMWARE_MINOR_REV 0x1c +#define DP_DUAL_MODE_MAX_TMDS_CLOCK 0x1d +#define DP_DUAL_MODE_I2C_SPEED_CAP 0x1e +#define DP_DUAL_MODE_TMDS_OEN 0x20 +#define DP_DUAL_MODE_TMDS_DISABLE 0x01 +#define DP_DUAL_MODE_HDMI_PIN_CTRL 0x21 +#define DP_DUAL_MODE_CEC_ENABLE 0x01 +#define DP_DUAL_MODE_I2C_SPEED_CTRL 0x22 + +/* LSPCON specific registers, defined by MCA */ +#define DP_DUAL_MODE_LSPCON_MODE_CHANGE 0x40 +#define DP_DUAL_MODE_LSPCON_CURRENT_MODE 0x41 +#define DP_DUAL_MODE_LSPCON_MODE_PCON 0x1 + +struct drm_device; +struct i2c_adapter; + +ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter, + u8 offset, void *buffer, size_t size); +ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter, + u8 offset, const void *buffer, size_t size); + +/** + * enum drm_lspcon_mode + * @DRM_LSPCON_MODE_INVALID: No LSPCON. + * @DRM_LSPCON_MODE_LS: Level shifter mode of LSPCON + * which drives DP++ to HDMI 1.4 conversion. + * @DRM_LSPCON_MODE_PCON: Protocol converter mode of LSPCON + * which drives DP++ to HDMI 2.0 active conversion. + */ +enum drm_lspcon_mode { + DRM_LSPCON_MODE_INVALID, + DRM_LSPCON_MODE_LS, + DRM_LSPCON_MODE_PCON, +}; + +/** + * enum drm_dp_dual_mode_type - Type of the DP dual mode adaptor + * @DRM_DP_DUAL_MODE_NONE: No DP dual mode adaptor + * @DRM_DP_DUAL_MODE_UNKNOWN: Could be either none or type 1 DVI adaptor + * @DRM_DP_DUAL_MODE_TYPE1_DVI: Type 1 DVI adaptor + * @DRM_DP_DUAL_MODE_TYPE1_HDMI: Type 1 HDMI adaptor + * @DRM_DP_DUAL_MODE_TYPE2_DVI: Type 2 DVI adaptor + * @DRM_DP_DUAL_MODE_TYPE2_HDMI: Type 2 HDMI adaptor + * @DRM_DP_DUAL_MODE_LSPCON: Level shifter / protocol converter + */ +enum drm_dp_dual_mode_type { + DRM_DP_DUAL_MODE_NONE, + DRM_DP_DUAL_MODE_UNKNOWN, + DRM_DP_DUAL_MODE_TYPE1_DVI, + DRM_DP_DUAL_MODE_TYPE1_HDMI, + DRM_DP_DUAL_MODE_TYPE2_DVI, + DRM_DP_DUAL_MODE_TYPE2_HDMI, + DRM_DP_DUAL_MODE_LSPCON, +}; + +enum drm_dp_dual_mode_type +drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter *adapter); +int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum drm_dp_dual_mode_type type, + struct i2c_adapter *adapter); +int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type, + struct i2c_adapter *adapter, bool *enabled); +int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type, + struct i2c_adapter *adapter, bool enable); +const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type); + +int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter *adapter, + enum drm_lspcon_mode *current_mode); +int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter *adapter, + enum drm_lspcon_mode reqd_mode); +#endif diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h new file mode 100644 index 000000000000..16d6da3a129f --- /dev/null +++ b/include/drm/dp/drm_dp_helper.h @@ -0,0 +1,2358 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef _DRM_DP_HELPER_H_ +#define _DRM_DP_HELPER_H_ + +#include +#include +#include +#include + +struct drm_device; +struct drm_dp_aux; +struct drm_panel; + +/* + * Unless otherwise noted, all values are from the DP 1.1a spec. Note that + * DP and DPCD versions are independent. Differences from 1.0 are not noted, + * 1.0 devices basically don't exist in the wild. + * + * Abbreviations, in chronological order: + * + * eDP: Embedded DisplayPort version 1 + * DPI: DisplayPort Interoperability Guideline v1.1a + * 1.2: DisplayPort 1.2 + * MST: Multistream Transport - part of DP 1.2a + * + * 1.2 formally includes both eDP and DPI definitions. + */ + +/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ +#define DP_MSA_MISC_SYNC_CLOCK (1 << 0) +#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) +#define DP_MSA_MISC_STEREO_NO_3D (0 << 9) +#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) +#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) +/* bits per component for non-RAW */ +#define DP_MSA_MISC_6_BPC (0 << 5) +#define DP_MSA_MISC_8_BPC (1 << 5) +#define DP_MSA_MISC_10_BPC (2 << 5) +#define DP_MSA_MISC_12_BPC (3 << 5) +#define DP_MSA_MISC_16_BPC (4 << 5) +/* bits per component for RAW */ +#define DP_MSA_MISC_RAW_6_BPC (1 << 5) +#define DP_MSA_MISC_RAW_7_BPC (2 << 5) +#define DP_MSA_MISC_RAW_8_BPC (3 << 5) +#define DP_MSA_MISC_RAW_10_BPC (4 << 5) +#define DP_MSA_MISC_RAW_12_BPC (5 << 5) +#define DP_MSA_MISC_RAW_14_BPC (6 << 5) +#define DP_MSA_MISC_RAW_16_BPC (7 << 5) +/* pixel encoding/colorimetry format */ +#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ + ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) +#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) +#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) +#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) +#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) +#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) +#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) +#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) +#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) +#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) +#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) +#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) +#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) +#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) +#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) +#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) +#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) +#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) +#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) + +#define DP_AUX_MAX_PAYLOAD_BYTES 16 + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ 0x1 +#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE 0x8 +#define DP_AUX_NATIVE_READ 0x9 + +#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) +#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) +#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) +#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) + +#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) +#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) +#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) +#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) + +/* DPCD Field Address Mapping */ + +/* Receiver Capability */ +#define DP_DPCD_REV 0x000 +# define DP_DPCD_REV_10 0x10 +# define DP_DPCD_REV_11 0x11 +# define DP_DPCD_REV_12 0x12 +# define DP_DPCD_REV_13 0x13 +# define DP_DPCD_REV_14 0x14 + +#define DP_MAX_LINK_RATE 0x001 + +#define DP_MAX_LANE_COUNT 0x002 +# define DP_MAX_LANE_COUNT_MASK 0x1f +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +# define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DP_MAX_DOWNSPREAD 0x003 +# define DP_MAX_DOWNSPREAD_0_5 (1 << 0) +# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */ +# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) +# define DP_TPS4_SUPPORTED (1 << 7) + +#define DP_NORP 0x004 + +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) +# define DP_FORMAT_CONVERSION (1 << 3) +# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 +# define DP_CAP_ANSI_8B10B (1 << 0) +# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */ + +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +# define DP_PORT_COUNT_MASK 0x0f +# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +# define DP_OUI_SUPPORT (1 << 7) + +#define DP_RECEIVE_PORT_0_CAP_0 0x008 +# define DP_LOCAL_EDID_PRESENT (1 << 1) +# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) + +#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 + +#define DP_RECEIVE_PORT_1_CAP_0 0x00a +#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b + +#define DP_I2C_SPEED_CAP 0x00c /* DPI */ +# define DP_I2C_SPEED_1K 0x01 +# define DP_I2C_SPEED_5K 0x02 +# define DP_I2C_SPEED_10K 0x04 +# define DP_I2C_SPEED_100K 0x08 +# define DP_I2C_SPEED_400K 0x10 +# define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) +# define DP_FRAMING_CHANGE_CAP (1 << 1) +# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ + +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ +# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ + +#define DP_ADAPTER_CAP 0x00f /* 1.2 */ +# define DP_FORCE_LOAD_SENSE_CAP (1 << 0) +# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) + +#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ +# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ + +/* Multiple stream transport */ +#define DP_FAUX_CAP 0x020 /* 1.2 */ +# define DP_FAUX_CAP_1 (1 << 0) + +#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */ +# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0) +# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1) +# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2) + +#define DP_MSTM_CAP 0x021 /* 1.2 */ +# define DP_MST_CAP (1 << 0) +# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */ + +#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ + +/* AV_SYNC_DATA_BLOCK 1.2 */ +#define DP_AV_GRANULARITY 0x023 +# define DP_AG_FACTOR_MASK (0xf << 0) +# define DP_AG_FACTOR_3MS (0 << 0) +# define DP_AG_FACTOR_2MS (1 << 0) +# define DP_AG_FACTOR_1MS (2 << 0) +# define DP_AG_FACTOR_500US (3 << 0) +# define DP_AG_FACTOR_200US (4 << 0) +# define DP_AG_FACTOR_100US (5 << 0) +# define DP_AG_FACTOR_10US (6 << 0) +# define DP_AG_FACTOR_1US (7 << 0) +# define DP_VG_FACTOR_MASK (0xf << 4) +# define DP_VG_FACTOR_3MS (0 << 4) +# define DP_VG_FACTOR_2MS (1 << 4) +# define DP_VG_FACTOR_1MS (2 << 4) +# define DP_VG_FACTOR_500US (3 << 4) +# define DP_VG_FACTOR_200US (4 << 4) +# define DP_VG_FACTOR_100US (5 << 4) + +#define DP_AUD_DEC_LAT0 0x024 +#define DP_AUD_DEC_LAT1 0x025 + +#define DP_AUD_PP_LAT0 0x026 +#define DP_AUD_PP_LAT1 0x027 + +#define DP_VID_INTER_LAT 0x028 + +#define DP_VID_PROG_LAT 0x029 + +#define DP_REP_LAT 0x02a + +#define DP_AUD_DEL_INS0 0x02b +#define DP_AUD_DEL_INS1 0x02c +#define DP_AUD_DEL_INS2 0x02d +/* End of AV_SYNC_DATA_BLOCK */ + +#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ +# define DP_ALPM_CAP (1 << 0) + +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ +# define DP_AUX_FRAME_SYNC_CAP (1 << 0) + +#define DP_GUID 0x030 /* 1.2 */ + +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ +# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) + +#define DP_DSC_REV 0x061 +# define DP_DSC_MAJOR_MASK (0xf << 0) +# define DP_DSC_MINOR_MASK (0xf << 4) +# define DP_DSC_MAJOR_SHIFT 0 +# define DP_DSC_MINOR_SHIFT 4 + +#define DP_DSC_RC_BUF_BLK_SIZE 0x062 +# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 +# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 +# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 +# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 + +#define DP_DSC_RC_BUF_SIZE 0x063 + +#define DP_DSC_SLICE_CAP_1 0x064 +# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) +# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) +# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) +# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) +# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) +# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) +# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) + +#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 +# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) +# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 +# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 +# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 +# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 +# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 +# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 +# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 +# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 +# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 + +#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 +# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) + +#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ + +#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) +# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 + +#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 +# define DP_DSC_RGB (1 << 0) +# define DP_DSC_YCbCr444 (1 << 1) +# define DP_DSC_YCbCr422_Simple (1 << 2) +# define DP_DSC_YCbCr422_Native (1 << 3) +# define DP_DSC_YCbCr420_Native (1 << 4) + +#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A +# define DP_DSC_8_BPC (1 << 1) +# define DP_DSC_10_BPC (1 << 2) +# define DP_DSC_12_BPC (1 << 3) + +#define DP_DSC_PEAK_THROUGHPUT 0x06B +# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) +# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 +# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 +# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) +# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ +# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) +# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 +# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0 +# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) +# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4) + +#define DP_DSC_MAX_SLICE_WIDTH 0x06C +#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 +#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 + +#define DP_DSC_SLICE_CAP_2 0x06D +# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) +# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) +# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) + +#define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_BITS_PER_PIXEL_1_16 0x0 +# define DP_DSC_BITS_PER_PIXEL_1_8 0x1 +# define DP_DSC_BITS_PER_PIXEL_1_4 0x2 +# define DP_DSC_BITS_PER_PIXEL_1_2 0x3 +# define DP_DSC_BITS_PER_PIXEL_1 0x4 + +#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ +# define DP_PSR_IS_SUPPORTED 1 +# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ +# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ + +#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1 +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ +# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ + +#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ +#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ + +/* + * 0x80-0x8f describe downstream port capabilities, but there are two layouts + * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, + * each port's descriptor is one byte wide. If it was set, each port's is + * four bytes wide, starting with the one byte from the base info. As of + * DP interop v1.1a only VGA defines additional detail. + */ + +/* offset 0 */ +#define DP_DOWNSTREAM_PORT_0 0x80 +# define DP_DS_PORT_TYPE_MASK (7 << 0) +# define DP_DS_PORT_TYPE_DP 0 +# define DP_DS_PORT_TYPE_VGA 1 +# define DP_DS_PORT_TYPE_DVI 2 +# define DP_DS_PORT_TYPE_HDMI 3 +# define DP_DS_PORT_TYPE_NON_EDID 4 +# define DP_DS_PORT_TYPE_DP_DUALMODE 5 +# define DP_DS_PORT_TYPE_WIRELESS 6 +# define DP_DS_PORT_HPD (1 << 3) +# define DP_DS_NON_EDID_MASK (0xf << 4) +# define DP_DS_NON_EDID_720x480i_60 (1 << 4) +# define DP_DS_NON_EDID_720x480i_50 (2 << 4) +# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4) +# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4) +# define DP_DS_NON_EDID_1280x720_60 (5 << 4) +# define DP_DS_NON_EDID_1280x720_50 (7 << 4) +/* offset 1 for VGA is maximum megapixels per second / 8 */ +/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ +/* offset 2 for VGA/DVI/HDMI */ +# define DP_DS_MAX_BPC_MASK (3 << 0) +# define DP_DS_8BPC 0 +# define DP_DS_10BPC 1 +# define DP_DS_12BPC 2 +# define DP_DS_16BPC 3 +/* HDMI2.1 PCON FRL CONFIGURATION */ +# define DP_PCON_MAX_FRL_BW (7 << 2) +# define DP_PCON_MAX_0GBPS (0 << 2) +# define DP_PCON_MAX_9GBPS (1 << 2) +# define DP_PCON_MAX_18GBPS (2 << 2) +# define DP_PCON_MAX_24GBPS (3 << 2) +# define DP_PCON_MAX_32GBPS (4 << 2) +# define DP_PCON_MAX_40GBPS (5 << 2) +# define DP_PCON_MAX_48GBPS (6 << 2) +# define DP_PCON_SOURCE_CTL_MODE (1 << 5) + +/* offset 3 for DVI */ +# define DP_DS_DVI_DUAL_LINK (1 << 1) +# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2) +/* offset 3 for HDMI */ +# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0) +# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1) +# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2) +# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3) +# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4) + +/* + * VESA DP-to-HDMI PCON Specification adds caps for colorspace + * conversion in DFP cap DPCD 83h. Sec6.1 Table-3. + * Based on the available support the source can enable + * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2 + * DPCD 3052h. + */ +# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5) +# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6) +# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7) + +#define DP_MAX_DOWNSTREAM_PORTS 0x10 + +/* DP Forward error Correction Registers */ +#define DP_FEC_CAPABILITY 0x090 /* 1.4 */ +# define DP_FEC_CAPABLE (1 << 0) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) +# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ + +/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ +#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ +#define DP_PCON_DSC_ENCODER 0x092 +# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0) +# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1) + +/* DP-HDMI2.1 PCON DSC Version */ +#define DP_PCON_DSC_VERSION 0x093 +# define DP_PCON_DSC_MAJOR_MASK (0xF << 0) +# define DP_PCON_DSC_MINOR_MASK (0xF << 4) +# define DP_PCON_DSC_MAJOR_SHIFT 0 +# define DP_PCON_DSC_MINOR_SHIFT 4 + +/* DP-HDMI2.1 PCON DSC RC Buffer block size */ +#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094 +# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0) +# define DP_PCON_DSC_RC_BUF_BLK_1KB 0 +# define DP_PCON_DSC_RC_BUF_BLK_4KB 1 +# define DP_PCON_DSC_RC_BUF_BLK_16KB 2 +# define DP_PCON_DSC_RC_BUF_BLK_64KB 3 + +/* DP-HDMI2.1 PCON DSC RC Buffer size */ +#define DP_PCON_DSC_RC_BUF_SIZE 0x095 + +/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */ +#define DP_PCON_DSC_SLICE_CAP_1 0x096 +# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0) +# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1) +# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3) +# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4) +# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5) +# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6) +# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7) + +#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097 +# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0) +# define DP_PCON_DSC_DEPTH_9_BITS 0 +# define DP_PCON_DSC_DEPTH_10_BITS 1 +# define DP_PCON_DSC_DEPTH_11_BITS 2 +# define DP_PCON_DSC_DEPTH_12_BITS 3 +# define DP_PCON_DSC_DEPTH_13_BITS 4 +# define DP_PCON_DSC_DEPTH_14_BITS 5 +# define DP_PCON_DSC_DEPTH_15_BITS 6 +# define DP_PCON_DSC_DEPTH_16_BITS 7 +# define DP_PCON_DSC_DEPTH_8_BITS 8 + +#define DP_PCON_DSC_BLOCK_PREDICTION 0x098 +# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0) + +#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099 +# define DP_PCON_DSC_ENC_RGB (0x1 << 0) +# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1) +# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2) +# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3) +# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4) + +#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A +# define DP_PCON_DSC_ENC_8BPC (0x1 << 1) +# define DP_PCON_DSC_ENC_10BPC (0x1 << 2) +# define DP_PCON_DSC_ENC_12BPC (0x1 << 3) + +#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B + +/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */ +#define DP_PCON_DSC_SLICE_CAP_2 0x09C +# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0) +# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1) +# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2) + +/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */ +#define DP_PCON_DSC_BPP_INCR 0x09E +# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0) +# define DP_PCON_DSC_ONE_16TH_BPP 0 +# define DP_PCON_DSC_ONE_8TH_BPP 1 +# define DP_PCON_DSC_ONE_4TH_BPP 2 +# define DP_PCON_DSC_ONE_HALF_BPP 3 +# define DP_PCON_DSC_ONE_BPP 4 + +/* DP Extended DSC Capabilities */ +#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ +#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 +#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 + +/* DFP Capability Extension */ +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + +/* Link Configuration */ +#define DP_LINK_BW_SET 0x100 +# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ +# define DP_LINK_BW_1_62 0x06 +# define DP_LINK_BW_2_7 0x0a +# define DP_LINK_BW_5_4 0x14 /* 1.2 */ +# define DP_LINK_BW_8_1 0x1e /* 1.4 */ +# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ +# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ +# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ + +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f +# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) + +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 +# define DP_TRAINING_PATTERN_1 1 +# define DP_TRAINING_PATTERN_2 2 +# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ +# define DP_TRAINING_PATTERN_4 7 /* 1.4 */ +# define DP_TRAINING_PATTERN_MASK 0x3 +# define DP_TRAINING_PATTERN_MASK_1_4 0xf + +/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ +# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) +# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) + +# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) + +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */ + +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4) +# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ + +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +# define DP_SET_ANSI_8B10B (1 << 0) +# define DP_SET_ANSI_128B132B (1 << 1) + +#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ +/* bitmask as for DP_I2C_SPEED_CAP */ + +#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ +# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) +# define DP_FRAMING_CHANGE_ENABLE (1 << 1) +# define DP_PANEL_SELF_TEST_ENABLE (1 << 7) + +#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ +#define DP_LINK_QUAL_LANE1_SET 0x10c +#define DP_LINK_QUAL_LANE2_SET 0x10d +#define DP_LINK_QUAL_LANE3_SET 0x10e +# define DP_LINK_QUAL_PATTERN_DISABLE 0 +# define DP_LINK_QUAL_PATTERN_D10_2 1 +# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 +# define DP_LINK_QUAL_PATTERN_PRBS7 3 +# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 +# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5 +# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6 +# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7 +/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */ +# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08 +# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10 +# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18 +# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20 +# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28 +# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30 +# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38 +# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40 +# define DP_LINK_QUAL_PATTERN_SQUARE 0x48 + +#define DP_TRAINING_LANE0_1_SET2 0x10f +#define DP_TRAINING_LANE2_3_SET2 0x110 +# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) +# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) +# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) +# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) + +#define DP_MSTM_CTRL 0x111 /* 1.2 */ +# define DP_MST_EN (1 << 0) +# define DP_UP_REQ_EN (1 << 1) +# define DP_UPSTREAM_IS_SRC (1 << 2) + +#define DP_AUDIO_DELAY0 0x112 /* 1.2 */ +#define DP_AUDIO_DELAY1 0x113 +#define DP_AUDIO_DELAY2 0x114 + +#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ +# define DP_LINK_RATE_SET_SHIFT 0 +# define DP_LINK_RATE_SET_MASK (7 << 0) + +#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ +# define DP_ALPM_ENABLE (1 << 0) +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) + +#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ +# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) +# define DP_IRQ_HPD_ENABLE (1 << 1) + +#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ +# define DP_PWR_NOT_NEEDED (1 << 0) + +#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ +# define DP_FEC_READY (1 << 0) +# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) +# define DP_FEC_ERR_COUNT_DIS (0 << 1) +# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) +# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) +# define DP_FEC_BIT_ERROR_COUNT (3 << 1) +# define DP_FEC_LANE_SELECT_MASK (3 << 4) +# define DP_FEC_LANE_0_SELECT (0 << 4) +# define DP_FEC_LANE_1_SELECT (1 << 4) +# define DP_FEC_LANE_2_SELECT (2 << 4) +# define DP_FEC_LANE_3_SELECT (3 << 4) + +#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ +# define DP_AUX_FRAME_SYNC_VALID (1 << 0) + +#define DP_DSC_ENABLE 0x160 /* DP 1.4 */ +# define DP_DECOMPRESSION_EN (1 << 0) +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ + +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ +# define DP_PSR_ENABLE BIT(0) +# define DP_PSR_MAIN_LINK_ACTIVE BIT(1) +# define DP_PSR_CRC_VERIFICATION BIT(2) +# define DP_PSR_FRAME_CAPTURE BIT(3) +# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ +# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */ +# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */ + +#define DP_ADAPTER_CTRL 0x1a0 +# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) + +#define DP_BRANCH_DEVICE_CTRL 0x1a1 +# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) + +#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 + +/* Link/Sink Device Status */ +#define DP_SINK_COUNT 0x200 +/* prior to 1.2 bit 7 was reserved mbz */ +# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) +# define DP_SINK_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +# define DP_AUTOMATED_TEST_REQUEST (1 << 1) +# define DP_CP_IRQ (1 << 2) +# define DP_MCCS_IRQ (1 << 3) +# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ +# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ +# define DP_SINK_SPECIFIC_IRQ (1 << 6) + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +# define DP_LANE_CR_DONE (1 << 0) +# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +# define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ + DP_LANE_CHANNEL_EQ_DONE | \ + DP_LANE_SYMBOL_LOCKED) + +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 + +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DP_SINK_STATUS 0x205 +# define DP_RECEIVE_PORT_0_STATUS (1 << 0) +# define DP_RECEIVE_PORT_1_STATUS (1 << 1) +# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 + +/* DP 2.0 128b/132b Link Layer */ +# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0) +# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0 +# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4) +# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4 + +#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c +# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03 +# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0 +# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c +# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2 +# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30 +# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4 +# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0 +# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6 + +#define DP_TEST_REQUEST 0x218 +# define DP_TEST_LINK_TRAINING (1 << 0) +# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) +# define DP_TEST_LINK_EDID_READ (1 << 2) +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ +# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ +# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ + +#define DP_TEST_LINK_RATE 0x219 +# define DP_LINK_RATE_162 (0x6) +# define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 + +#define DP_TEST_PATTERN 0x221 +# define DP_NO_TEST_PATTERN 0x0 +# define DP_COLOR_RAMP 0x1 +# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 +# define DP_COLOR_SQUARE 0x3 + +#define DP_TEST_H_TOTAL_HI 0x222 +#define DP_TEST_H_TOTAL_LO 0x223 + +#define DP_TEST_V_TOTAL_HI 0x224 +#define DP_TEST_V_TOTAL_LO 0x225 + +#define DP_TEST_H_START_HI 0x226 +#define DP_TEST_H_START_LO 0x227 + +#define DP_TEST_V_START_HI 0x228 +#define DP_TEST_V_START_LO 0x229 + +#define DP_TEST_HSYNC_HI 0x22A +# define DP_TEST_HSYNC_POLARITY (1 << 7) +# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) +#define DP_TEST_HSYNC_WIDTH_LO 0x22B + +#define DP_TEST_VSYNC_HI 0x22C +# define DP_TEST_VSYNC_POLARITY (1 << 7) +# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) +#define DP_TEST_VSYNC_WIDTH_LO 0x22D + +#define DP_TEST_H_WIDTH_HI 0x22E +#define DP_TEST_H_WIDTH_LO 0x22F + +#define DP_TEST_V_HEIGHT_HI 0x230 +#define DP_TEST_V_HEIGHT_LO 0x231 + +#define DP_TEST_MISC0 0x232 +# define DP_TEST_SYNC_CLOCK (1 << 0) +# define DP_TEST_COLOR_FORMAT_MASK (3 << 1) +# define DP_TEST_COLOR_FORMAT_SHIFT 1 +# define DP_COLOR_FORMAT_RGB (0 << 1) +# define DP_COLOR_FORMAT_YCbCr422 (1 << 1) +# define DP_COLOR_FORMAT_YCbCr444 (2 << 1) +# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) +# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) +# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) +# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) +# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) +# define DP_TEST_BIT_DEPTH_MASK (7 << 5) +# define DP_TEST_BIT_DEPTH_SHIFT 5 +# define DP_TEST_BIT_DEPTH_6 (0 << 5) +# define DP_TEST_BIT_DEPTH_8 (1 << 5) +# define DP_TEST_BIT_DEPTH_10 (2 << 5) +# define DP_TEST_BIT_DEPTH_12 (3 << 5) +# define DP_TEST_BIT_DEPTH_16 (4 << 5) + +#define DP_TEST_MISC1 0x233 +# define DP_TEST_REFRESH_DENOMINATOR (1 << 0) +# define DP_TEST_INTERLACED (1 << 1) + +#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 + +#define DP_TEST_MISC0 0x232 + +#define DP_TEST_CRC_R_CR 0x240 +#define DP_TEST_CRC_G_Y 0x242 +#define DP_TEST_CRC_B_CB 0x244 + +#define DP_TEST_SINK_MISC 0x246 +# define DP_TEST_CRC_SUPPORTED (1 << 5) +# define DP_TEST_COUNT_MASK 0xf + +#define DP_PHY_TEST_PATTERN 0x248 +# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7 +# define DP_PHY_TEST_PATTERN_NONE 0x0 +# define DP_PHY_TEST_PATTERN_D10_2 0x1 +# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 +# define DP_PHY_TEST_PATTERN_PRBS7 0x3 +# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 +# define DP_PHY_TEST_PATTERN_CP2520 0x5 + +#define DP_PHY_SQUARE_PATTERN 0x249 + +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A +#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 +#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 +#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 +#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 +#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 +#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 +#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 +#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 +#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 +#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 + +#define DP_TEST_RESPONSE 0x260 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_TEST_EDID_CHECKSUM 0x261 + +#define DP_TEST_SINK 0x270 +# define DP_TEST_SINK_START (1 << 0) +#define DP_TEST_AUDIO_MODE 0x271 +#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 +#define DP_TEST_AUDIO_PERIOD_CH1 0x273 +#define DP_TEST_AUDIO_PERIOD_CH2 0x274 +#define DP_TEST_AUDIO_PERIOD_CH3 0x275 +#define DP_TEST_AUDIO_PERIOD_CH4 0x276 +#define DP_TEST_AUDIO_PERIOD_CH5 0x277 +#define DP_TEST_AUDIO_PERIOD_CH6 0x278 +#define DP_TEST_AUDIO_PERIOD_CH7 0x279 +#define DP_TEST_AUDIO_PERIOD_CH8 0x27A + +#define DP_FEC_STATUS 0x280 /* 1.4 */ +# define DP_FEC_DECODE_EN_DETECTED (1 << 0) +# define DP_FEC_DECODE_DIS_DETECTED (1 << 1) + +#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ + +#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ +# define DP_FEC_ERROR_COUNT_MASK 0x7F +# define DP_FEC_ERR_COUNT_VALID (1 << 7) + +#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ +# define DP_PAYLOAD_TABLE_UPDATED (1 << 0) +# define DP_PAYLOAD_ACT_HANDLED (1 << 1) + +#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ +/* up to ID_SLOT_63 at 0x2ff */ + +/* Source Device-specific */ +#define DP_SOURCE_OUI 0x300 + +/* Sink Device-specific */ +#define DP_SINK_OUI 0x400 + +/* Branch Device-specific */ +#define DP_BRANCH_OUI 0x500 +#define DP_BRANCH_ID 0x503 +#define DP_BRANCH_REVISION_START 0x509 +#define DP_BRANCH_HW_REV 0x509 +#define DP_BRANCH_SW_REV 0x50A + +/* Link/Sink Device Power Control */ +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 +# define DP_SET_POWER_MASK 0x3 +# define DP_SET_POWER_D3_AUX_ON 0x5 + +/* eDP-specific */ +#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ +# define DP_EDP_11 0x00 +# define DP_EDP_12 0x01 +# define DP_EDP_13 0x02 +# define DP_EDP_14 0x03 +# define DP_EDP_14a 0x04 /* eDP 1.4a */ +# define DP_EDP_14b 0x05 /* eDP 1.4b */ + +#define DP_EDP_GENERAL_CAP_1 0x701 +# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) +# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) +# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) +# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) +# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) +# define DP_EDP_FRC_ENABLE_CAP (1 << 5) +# define DP_EDP_COLOR_ENGINE_CAP (1 << 6) +# define DP_EDP_SET_POWER_CAP (1 << 7) + +#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 +# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) +# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) +# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) +# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) +# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) +# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) +# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) +# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) + +#define DP_EDP_GENERAL_CAP_2 0x703 +# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) + +#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ +# define DP_EDP_X_REGION_CAP_MASK (0xf << 0) +# define DP_EDP_X_REGION_CAP_SHIFT 0 +# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) +# define DP_EDP_Y_REGION_CAP_SHIFT 4 + +#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 +# define DP_EDP_BACKLIGHT_ENABLE (1 << 0) +# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) +# define DP_EDP_FRC_ENABLE (1 << 2) +# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) +# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) + +#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 +# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) +# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) +# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) +# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) +# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) +# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) +# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ + +#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 +#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 + +#define DP_EDP_PWMGEN_BIT_COUNT 0x724 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 +#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 +# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) + +#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 + +#define DP_EDP_BACKLIGHT_FREQ_SET 0x728 +# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b +#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c + +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e +#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f + +#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 +#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 + +#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ +#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ + +#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ +# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0) +# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0 +# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3) + +/* Sideband MSG Buffers */ +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ + +/* DPRX Event Status Indicator */ +#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */ +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */ + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ +# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) +# define DP_LOCK_ACQUISITION_REQUEST (1 << 1) +# define DP_CEC_IRQ (1 << 2) + +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ +# define RX_CAP_CHANGED (1 << 0) +# define LINK_STATUS_CHANGED (1 << 1) +# define STREAM_STATUS_CHANGED (1 << 2) +# define HDMI_LINK_STATUS_CHANGED (1 << 3) +# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4) + +#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) +# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ + +#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07 + +#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ +# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) +# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 +# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) +# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 + +#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ +# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ +# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ +# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ +# define DP_SU_VALID (1 << 3) /* eDP 1.4 */ +# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ +# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ +# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ + +#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ +# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) + +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ +#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ + +/* Extended Receiver Capability: See DP_DPCD_REV for definitions */ +#define DP_DP13_DPCD_REV 0x2200 + +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ +# define DP_GTC_CAP (1 << 0) /* DP 1.3 */ +# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ +# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ +# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ +# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ +# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ +# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ +# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ + +#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ +# define DP_UHBR10 (1 << 0) +# define DP_UHBR20 (1 << 1) +# define DP_UHBR13_5 (1 << 2) + +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00 +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01 +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02 +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03 +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04 +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05 +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06 + +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 + +/* DSC Extended Capability Branch Total DSC Resources */ +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +# define DP_DSC_DECODER_COUNT_SHIFT 5 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 + +/* Protocol Converter Extension */ +/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ +#define DP_CEC_TUNNELING_CAPABILITY 0x3000 +# define DP_CEC_TUNNELING_CAPABLE (1 << 0) +# define DP_CEC_SNOOPING_CAPABLE (1 << 1) +# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) + +#define DP_CEC_TUNNELING_CONTROL 0x3001 +# define DP_CEC_TUNNELING_ENABLE (1 << 0) +# define DP_CEC_SNOOPING_ENABLE (1 << 1) + +#define DP_CEC_RX_MESSAGE_INFO 0x3002 +# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) +# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 +# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) +# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) +# define DP_CEC_RX_MESSAGE_ACKED (1 << 6) +# define DP_CEC_RX_MESSAGE_ENDED (1 << 7) + +#define DP_CEC_TX_MESSAGE_INFO 0x3003 +# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) +# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 +# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) +# define DP_CEC_TX_RETRY_COUNT_SHIFT 4 +# define DP_CEC_TX_MESSAGE_SEND (1 << 7) + +#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 +# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) +# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) +# define DP_CEC_TX_MESSAGE_SENT (1 << 4) +# define DP_CEC_TX_LINE_ERROR (1 << 5) +# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) +# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) + +#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ +# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) +# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) +# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) +# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) +# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) +# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) +# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) +# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) +#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ +# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) +# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) +# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) +# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) +# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) +# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) +# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) +# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) + +#define DP_CEC_RX_MESSAGE_BUFFER 0x3010 +#define DP_CEC_TX_MESSAGE_BUFFER 0x3020 +#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 + +/* PCON CONFIGURE-1 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A +# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) +# define DP_PCON_ENABLE_MAX_BW_0GBPS 0 +# define DP_PCON_ENABLE_MAX_BW_9GBPS 1 +# define DP_PCON_ENABLE_MAX_BW_18GBPS 2 +# define DP_PCON_ENABLE_MAX_BW_24GBPS 3 +# define DP_PCON_ENABLE_MAX_BW_32GBPS 4 +# define DP_PCON_ENABLE_MAX_BW_40GBPS 5 +# define DP_PCON_ENABLE_MAX_BW_48GBPS 6 +# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) +# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) +# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) +# define DP_PCON_ENABLE_HPD_READY (1 << 6) +# define DP_PCON_ENABLE_HDMI_LINK (1 << 7) + +/* PCON CONFIGURE-2 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B +# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) +# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) +# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) +# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) +# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) +# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) +# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) +# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) + +/* PCON HDMI LINK STATUS */ +#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B +# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) +# define DP_PCON_FRL_READY (1 << 1) + +/* PCON HDMI POST FRL STATUS */ +#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 +# define DP_PCON_HDMI_LINK_MODE (1 << 0) +# define DP_PCON_HDMI_MODE_TMDS 0 +# define DP_PCON_HDMI_MODE_FRL 1 +# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) +# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) +# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) +# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) +# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) +# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) +# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) + +#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */ +# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */ +#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */ +# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */ +# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */ +# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */ +# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */ +#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */ +# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */ +# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1) +# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2) +# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0 +# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1 +# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2 +# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4) +# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4) +# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5) +# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6) + +/* PCON Downstream HDMI ERROR Status per Lane */ +#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037 +#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038 +#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039 +#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A +# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0) +# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0) +# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1) +# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2) + +/* PCON HDMI CONFIG PPS Override Buffer + * Valid Offsets to be added to Base : 0-127 + */ +#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100 + +/* PCON HDMI CONFIG PPS Override Parameter: Slice height + * Offset-0 8LSBs of the Slice height. + * Offset-1 8MSBs of the Slice height. + */ +#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180 + +/* PCON HDMI CONFIG PPS Override Parameter: Slice width + * Offset-0 8LSBs of the Slice width. + * Offset-1 8MSBs of the Slice width. + */ +#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182 + +/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel + * Offset-0 8LSBs of the bits_per_pixel. + * Offset-1 2MSBs of the bits_per_pixel. + */ +#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184 + +/* HDCP 1.3 and HDCP 2.2 */ +#define DP_AUX_HDCP_BKSV 0x68000 +#define DP_AUX_HDCP_RI_PRIME 0x68005 +#define DP_AUX_HDCP_AKSV 0x68007 +#define DP_AUX_HDCP_AN 0x6800C +#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) +#define DP_AUX_HDCP_BCAPS 0x68028 +# define DP_BCAPS_REPEATER_PRESENT BIT(1) +# define DP_BCAPS_HDCP_CAPABLE BIT(0) +#define DP_AUX_HDCP_BSTATUS 0x68029 +# define DP_BSTATUS_REAUTH_REQ BIT(3) +# define DP_BSTATUS_LINK_FAILURE BIT(2) +# define DP_BSTATUS_R0_PRIME_READY BIT(1) +# define DP_BSTATUS_READY BIT(0) +#define DP_AUX_HDCP_BINFO 0x6802A +#define DP_AUX_HDCP_KSV_FIFO 0x6802C +#define DP_AUX_HDCP_AINFO 0x6803B + +/* DP HDCP2.2 parameter offsets in DPCD address space */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/* LTTPR: Link Training (LT)-tunable PHY Repeaters */ +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ +# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ + +enum drm_dp_phy { + DP_PHY_DPRX, + + DP_PHY_LTTPR1, + DP_PHY_LTTPR2, + DP_PHY_LTTPR3, + DP_PHY_LTTPR4, + DP_PHY_LTTPR5, + DP_PHY_LTTPR6, + DP_PHY_LTTPR7, + DP_PHY_LTTPR8, + + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, +}; + +#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) + +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ +#define DP_LTTPR_BASE(dp_phy) \ + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1)) + +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) + +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) + +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1) + +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) + +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ +# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0) +# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1) + +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */ +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) +/* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */ + +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1) + +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ + +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ + +#define __DP_FEC1_BASE 0xf0290 /* 1.4 */ +#define __DP_FEC2_BASE 0xf0298 /* 1.4 */ +#define DP_FEC_BASE(dp_phy) \ + (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1))) + +#define DP_FEC_REG(dp_phy, fec1_reg) \ + (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) + +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ +#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ + DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) + +#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */ +#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */ + +#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ + +#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ + +/* Repeater modes */ +#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ +#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ + +/* DP HDCP message start offsets in DPCD address space */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ + DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +#define HDCP_2_2_DP_RXSTATUS_LEN 1 +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) + +/* DP 1.2 Sideband message defines */ +/* peer device type - DP 1.2a Table 2-92 */ +#define DP_PEER_DEVICE_NONE 0x0 +#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 +#define DP_PEER_DEVICE_MST_BRANCHING 0x2 +#define DP_PEER_DEVICE_SST_SINK 0x3 +#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 + +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ +#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */ +#define DP_LINK_ADDRESS 0x01 +#define DP_CONNECTION_STATUS_NOTIFY 0x02 +#define DP_ENUM_PATH_RESOURCES 0x10 +#define DP_ALLOCATE_PAYLOAD 0x11 +#define DP_QUERY_PAYLOAD 0x12 +#define DP_RESOURCE_STATUS_NOTIFY 0x13 +#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 +#define DP_REMOTE_DPCD_READ 0x20 +#define DP_REMOTE_DPCD_WRITE 0x21 +#define DP_REMOTE_I2C_READ 0x22 +#define DP_REMOTE_I2C_WRITE 0x23 +#define DP_POWER_UP_PHY 0x24 +#define DP_POWER_DOWN_PHY 0x25 +#define DP_SINK_EVENT_NOTIFY 0x30 +#define DP_QUERY_STREAM_ENC_STATUS 0x38 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 +#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 + +/* DP 1.2 MST sideband reply types */ +#define DP_SIDEBAND_REPLY_ACK 0x00 +#define DP_SIDEBAND_REPLY_NAK 0x01 + +/* DP 1.2 MST sideband nak reasons - table 2.84 */ +#define DP_NAK_WRITE_FAILURE 0x01 +#define DP_NAK_INVALID_READ 0x02 +#define DP_NAK_CRC_FAILURE 0x03 +#define DP_NAK_BAD_PARAM 0x04 +#define DP_NAK_DEFER 0x05 +#define DP_NAK_LINK_FAILURE 0x06 +#define DP_NAK_NO_RESOURCES 0x07 +#define DP_NAK_DPCD_FAIL 0x08 +#define DP_NAK_I2C_NAK 0x09 +#define DP_NAK_ALLOCATE_FAIL 0x0a + +#define MODE_I2C_START 1 +#define MODE_I2C_WRITE 2 +#define MODE_I2C_READ 4 +#define MODE_I2C_STOP 8 + +/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ +#define DP_MST_PHYSICAL_PORT_0 0 +#define DP_MST_LOGICAL_PORT_0 8 + +#define DP_LINK_CONSTANT_N_VALUE 0x8000 +#define DP_LINK_STATUS_SIZE 6 +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count); +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane_count); +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); +u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], + int lane); +u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], + unsigned int lane); + +#define DP_BRANCH_OUI_HEADER_SIZE 0xc +#define DP_RECEIVER_CAP_SIZE 0xf +#define DP_DSC_RECEIVER_CAP_SIZE 0xf +#define EDP_PSR_RECEIVER_CAP_SIZE 2 +#define EDP_DISPLAY_CTL_CAP_SIZE 3 +#define DP_LTTPR_COMMON_CAP_SIZE 8 +#define DP_LTTPR_PHY_CAP_SIZE 3 + +int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], + enum drm_dp_phy dp_phy, bool uhbr); +int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], + enum drm_dp_phy dp_phy, bool uhbr); + +void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_lttpr_link_train_clock_recovery_delay(void); +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); + +u8 drm_dp_link_rate_to_bw_code(int link_rate); +int drm_dp_bw_code_to_link_rate(u8 link_bw); + +#define DP_SDP_AUDIO_TIMESTAMP 0x01 +#define DP_SDP_AUDIO_STREAM 0x02 +#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ +#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ +#define DP_SDP_ISRC 0x06 /* DP 1.2 */ +#define DP_SDP_VSC 0x07 /* DP 1.2 */ +#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ +#define DP_SDP_PPS 0x10 /* DP 1.4 */ +#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ +#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ +/* 0x80+ CEA-861 infoframe types */ + +/** + * struct dp_sdp_header - DP secondary data packet header + * @HB0: Secondary Data Packet ID + * @HB1: Secondary Data Packet Type + * @HB2: Secondary Data Packet Specific header, Byte 0 + * @HB3: Secondary Data packet Specific header, Byte 1 + */ +struct dp_sdp_header { + u8 HB0; + u8 HB1; + u8 HB2; + u8 HB3; +} __packed; + +#define EDP_SDP_HEADER_REVISION_MASK 0x1F +#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F +#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F + +/** + * struct dp_sdp - DP secondary data packet + * @sdp_header: DP secondary data packet header + * @db: DP secondaray data packet data blocks + * VSC SDP Payload for PSR + * db[0]: Stereo Interface + * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid + * db[2]: CRC value bits 7:0 of the R or Cr component + * db[3]: CRC value bits 15:8 of the R or Cr component + * db[4]: CRC value bits 7:0 of the G or Y component + * db[5]: CRC value bits 15:8 of the G or Y component + * db[6]: CRC value bits 7:0 of the B or Cb component + * db[7]: CRC value bits 15:8 of the B or Cb component + * db[8] - db[31]: Reserved + * VSC SDP Payload for Pixel Encoding/Colorimetry Format + * db[0] - db[15]: Reserved + * db[16]: Pixel Encoding and Colorimetry Formats + * db[17]: Dynamic Range and Component Bit Depth + * db[18]: Content Type + * db[19] - db[31]: Reserved + */ +struct dp_sdp { + struct dp_sdp_header sdp_header; + u8 db[32]; +} __packed; + +#define EDP_VSC_PSR_STATE_ACTIVE (1<<0) +#define EDP_VSC_PSR_UPDATE_RFB (1<<1) +#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) + +/** + * enum dp_pixelformat - drm DP Pixel encoding formats + * + * This enum is used to indicate DP VSC SDP Pixel encoding formats. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] + * + * @DP_PIXELFORMAT_RGB: RGB pixel encoding format + * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format + * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format + * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format + * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format + * @DP_PIXELFORMAT_RAW: RAW pixel encoding format + * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format + */ +enum dp_pixelformat { + DP_PIXELFORMAT_RGB = 0, + DP_PIXELFORMAT_YUV444 = 0x1, + DP_PIXELFORMAT_YUV422 = 0x2, + DP_PIXELFORMAT_YUV420 = 0x3, + DP_PIXELFORMAT_Y_ONLY = 0x4, + DP_PIXELFORMAT_RAW = 0x5, + DP_PIXELFORMAT_RESERVED = 0x6, +}; + +/** + * enum dp_colorimetry - drm DP Colorimetry formats + * + * This enum is used to indicate DP VSC SDP Colorimetry formats. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition. + * + * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or + * ITU-R BT.601 colorimetry format + * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format + * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format + * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point + * (scRGB (IEC 61966-2-2)) colorimetry format + * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format + * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format + * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format + * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format + * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format + * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format + * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format + * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format + * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format + * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format + */ +enum dp_colorimetry { + DP_COLORIMETRY_DEFAULT = 0, + DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, + DP_COLORIMETRY_BT709_YCC = 0x1, + DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, + DP_COLORIMETRY_XVYCC_601 = 0x2, + DP_COLORIMETRY_OPRGB = 0x3, + DP_COLORIMETRY_XVYCC_709 = 0x3, + DP_COLORIMETRY_DCI_P3_RGB = 0x4, + DP_COLORIMETRY_SYCC_601 = 0x4, + DP_COLORIMETRY_RGB_CUSTOM = 0x5, + DP_COLORIMETRY_OPYCC_601 = 0x5, + DP_COLORIMETRY_BT2020_RGB = 0x6, + DP_COLORIMETRY_BT2020_CYCC = 0x6, + DP_COLORIMETRY_BT2020_YCC = 0x7, +}; + +/** + * enum dp_dynamic_range - drm DP Dynamic Range + * + * This enum is used to indicate DP VSC SDP Dynamic Range. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] + * + * @DP_DYNAMIC_RANGE_VESA: VESA range + * @DP_DYNAMIC_RANGE_CTA: CTA range + */ +enum dp_dynamic_range { + DP_DYNAMIC_RANGE_VESA = 0, + DP_DYNAMIC_RANGE_CTA = 1, +}; + +/** + * enum dp_content_type - drm DP Content Type + * + * This enum is used to indicate DP VSC SDP Content Types. + * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through + * DB18] + * CTA-861-G defines content types and expected processing by a sink device + * + * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type + * @DP_CONTENT_TYPE_GRAPHICS: Graphics type + * @DP_CONTENT_TYPE_PHOTO: Photo type + * @DP_CONTENT_TYPE_VIDEO: Video type + * @DP_CONTENT_TYPE_GAME: Game type + */ +enum dp_content_type { + DP_CONTENT_TYPE_NOT_DEFINED = 0x00, + DP_CONTENT_TYPE_GRAPHICS = 0x01, + DP_CONTENT_TYPE_PHOTO = 0x02, + DP_CONTENT_TYPE_VIDEO = 0x03, + DP_CONTENT_TYPE_GAME = 0x04, +}; + +/** + * struct drm_dp_vsc_sdp - drm DP VSC SDP + * + * This structure represents a DP VSC SDP of drm + * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and + * [Table 2-117: VSC SDP Payload for DB16 through DB18] + * + * @sdp_type: secondary-data packet type + * @revision: revision number + * @length: number of valid data bytes + * @pixelformat: pixel encoding format + * @colorimetry: colorimetry format + * @bpc: bit per color + * @dynamic_range: dynamic range information + * @content_type: CTA-861-G defines content types and expected processing by a sink device + */ +struct drm_dp_vsc_sdp { + unsigned char sdp_type; + unsigned char revision; + unsigned char length; + enum dp_pixelformat pixelformat; + enum dp_colorimetry colorimetry; + int bpc; + enum dp_dynamic_range dynamic_range; + enum dp_content_type content_type; +}; + +void drm_dp_vsc_sdp_log(const char *level, struct device *dev, + const struct drm_dp_vsc_sdp *vsc); + +int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); + +static inline int +drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); +} + +static inline u8 +drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; +} + +static inline bool +drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x11 && + (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); +} + +static inline bool +drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x11 && + (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); +} + +static inline bool +drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x12 && + dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; +} + +static inline bool +drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DPCD_REV] >= 0x14 && + dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; +} + +static inline u8 +drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : + DP_TRAINING_PATTERN_MASK; +} + +static inline bool +drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; +} + +/* DP/eDP DSC support */ +u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], + bool is_edp); +u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); +int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], + u8 dsc_bpc[3]); + +static inline bool +drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & + DP_DSC_DECOMPRESSION_IS_SUPPORTED; +} + +static inline u16 +drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | + (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & + DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << + DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); +} + +static inline u32 +drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + /* Max Slicewidth = Number of Pixels * 320 */ + return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * + DP_DSC_SLICE_WIDTH_MULTIPLIER; +} + +/* Forward Error Correction Support on DP 1.4 */ +static inline bool +drm_dp_sink_supports_fec(const u8 fec_capable) +{ + return fec_capable & DP_FEC_CAPABLE; +} + +static inline bool +drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; +} + +static inline bool +drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_EDP_CONFIGURATION_CAP] & + DP_ALTERNATE_SCRAMBLER_RESET_CAP; +} + +/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ +static inline bool +drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_DOWN_STREAM_PORT_COUNT] & + DP_MSA_TIMING_PAR_IGNORED; +} + +/** + * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support + * @edp_dpcd: The DPCD to check + * + * Note that currently this function will return %false for panels which support various DPCD + * backlight features but which require the brightness be set through PWM, and don't support setting + * the brightness level via the DPCD. + * + * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false + * otherwise + */ +static inline bool +drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) +{ + return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); +} + +/* + * DisplayPort AUX channel + */ + +/** + * struct drm_dp_aux_msg - DisplayPort AUX channel transaction + * @address: address of the (first) register to access + * @request: contains the type of transaction (see DP_AUX_* macros) + * @reply: upon completion, contains the reply type of the transaction + * @buffer: pointer to a transmission or reception buffer + * @size: size of @buffer + */ +struct drm_dp_aux_msg { + unsigned int address; + u8 request; + u8 reply; + void *buffer; + size_t size; +}; + +struct cec_adapter; +struct edid; +struct drm_connector; + +/** + * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX + * @lock: mutex protecting this struct + * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. + * @connector: the connector this CEC adapter is associated with + * @unregister_work: unregister the CEC adapter + */ +struct drm_dp_aux_cec { + struct mutex lock; + struct cec_adapter *adap; + struct drm_connector *connector; + struct delayed_work unregister_work; +}; + +/** + * struct drm_dp_aux - DisplayPort AUX channel + * + * An AUX channel can also be used to transport I2C messages to a sink. A + * typical application of that is to access an EDID that's present in the sink + * device. The @transfer() function can also be used to execute such + * transactions. The drm_dp_aux_register() function registers an I2C adapter + * that can be passed to drm_probe_ddc(). Upon removal, drivers should call + * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long + * transfers by default; if a partial response is received, the adapter will + * drop down to the size given by the partial response for this transaction + * only. + */ +struct drm_dp_aux { + /** + * @name: user-visible name of this AUX channel and the + * I2C-over-AUX adapter. + * + * It's also used to specify the name of the I2C adapter. If set + * to %NULL, dev_name() of @dev will be used. + */ + const char *name; + + /** + * @ddc: I2C adapter that can be used for I2C-over-AUX + * communication + */ + struct i2c_adapter ddc; + + /** + * @dev: pointer to struct device that is the parent for this + * AUX channel. + */ + struct device *dev; + + /** + * @drm_dev: pointer to the &drm_device that owns this AUX channel. + * Beware, this may be %NULL before drm_dp_aux_register() has been + * called. + * + * It should be set to the &drm_device that will be using this AUX + * channel as early as possible. For many graphics drivers this should + * happen before drm_dp_aux_init(), however it's perfectly fine to set + * this field later so long as it's assigned before calling + * drm_dp_aux_register(). + */ + struct drm_device *drm_dev; + + /** + * @crtc: backpointer to the crtc that is currently using this + * AUX channel + */ + struct drm_crtc *crtc; + + /** + * @hw_mutex: internal mutex used for locking transfers. + * + * Note that if the underlying hardware is shared among multiple + * channels, the driver needs to do additional locking to + * prevent concurrent access. + */ + struct mutex hw_mutex; + + /** + * @crc_work: worker that captures CRCs for each frame + */ + struct work_struct crc_work; + + /** + * @crc_count: counter of captured frame CRCs + */ + u8 crc_count; + + /** + * @transfer: transfers a message representing a single AUX + * transaction. + * + * This is a hardware-specific implementation of how + * transactions are executed that the drivers must provide. + * + * A pointer to a &drm_dp_aux_msg structure describing the + * transaction is passed into this function. Upon success, the + * implementation should return the number of payload bytes that + * were transferred, or a negative error-code on failure. + * + * Helpers will propagate these errors, with the exception of + * the %-EBUSY error, which causes a transaction to be retried. + * On a short, helpers will return %-EPROTO to make it simpler + * to check for failure. + * + * The @transfer() function must only modify the reply field of + * the &drm_dp_aux_msg structure. The retry logic and i2c + * helpers assume this is the case. + * + * Also note that this callback can be called no matter the + * state @dev is in. Drivers that need that device to be powered + * to perform this operation will first need to make sure it's + * been properly enabled. + */ + ssize_t (*transfer)(struct drm_dp_aux *aux, + struct drm_dp_aux_msg *msg); + + /** + * @i2c_nack_count: Counts I2C NACKs, used for DP validation. + */ + unsigned i2c_nack_count; + /** + * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. + */ + unsigned i2c_defer_count; + /** + * @cec: struct containing fields used for CEC-Tunneling-over-AUX. + */ + struct drm_dp_aux_cec cec; + /** + * @is_remote: Is this AUX CH actually using sideband messaging. + */ + bool is_remote; +}; + +ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); +ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, + void *buffer, size_t size); + +/** + * drm_dp_dpcd_readb() - read a single byte from the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the register to read + * @valuep: location where the value of the register will be stored + * + * Returns the number of bytes transferred (1) on success, or a negative + * error code on failure. + */ +static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, + unsigned int offset, u8 *valuep) +{ + return drm_dp_dpcd_read(aux, offset, valuep, 1); +} + +/** + * drm_dp_dpcd_writeb() - write a single byte to the DPCD + * @aux: DisplayPort AUX channel + * @offset: address of the register to write + * @value: value to write to the register + * + * Returns the number of bytes transferred (1) on success, or a negative + * error code on failure. + */ +static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, + unsigned int offset, u8 value) +{ + return drm_dp_dpcd_write(aux, offset, &value, 1); +} + +int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]); + +int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, + u8 status[DP_LINK_STATUS_SIZE]); + +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, + enum drm_dp_phy dp_phy, + u8 link_status[DP_LINK_STATUS_SIZE]); + +bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, + u8 real_edid_checksum); + +int drm_dp_read_downstream_info(struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); +bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], u8 type); +bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid); +int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); +int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid); +int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid); +int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid); +bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); +bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); +struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); +int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); +void drm_dp_downstream_debug(struct seq_file *m, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], + const struct edid *edid, + struct drm_dp_aux *aux); +enum drm_mode_subconnector +drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); +void drm_dp_set_subconnector_property(struct drm_connector *connector, + enum drm_connector_status status, + const u8 *dpcd, + const u8 port_cap[4]); + +struct drm_dp_desc; +bool drm_dp_read_sink_count_cap(struct drm_connector *connector, + const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const struct drm_dp_desc *desc); +int drm_dp_read_sink_count(struct drm_dp_aux *aux); + +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, + enum drm_dp_phy dp_phy, + u8 caps[DP_LTTPR_PHY_CAP_SIZE]); +int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); +bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); +bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); + +void drm_dp_remote_aux_init(struct drm_dp_aux *aux); +void drm_dp_aux_init(struct drm_dp_aux *aux); +int drm_dp_aux_register(struct drm_dp_aux *aux); +void drm_dp_aux_unregister(struct drm_dp_aux *aux); + +int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); +int drm_dp_stop_crc(struct drm_dp_aux *aux); + +struct drm_dp_dpcd_ident { + u8 oui[3]; + u8 device_id[6]; + u8 hw_rev; + u8 sw_major_rev; + u8 sw_minor_rev; +} __packed; + +/** + * struct drm_dp_desc - DP branch/sink device descriptor + * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). + * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. + */ +struct drm_dp_desc { + struct drm_dp_dpcd_ident ident; + u32 quirks; +}; + +int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, + bool is_branch); + +/** + * enum drm_dp_quirk - Display Port sink/branch device specific quirks + * + * Display Port sink and branch devices in the wild have a variety of bugs, try + * to collect them here. The quirks are shared, but it's up to the drivers to + * implement workarounds for them. + */ +enum drm_dp_quirk { + /** + * @DP_DPCD_QUIRK_CONSTANT_N: + * + * The device requires main link attributes Mvid and Nvid to be limited + * to 16 bits. So will give a constant value (0x8000) for compatability. + */ + DP_DPCD_QUIRK_CONSTANT_N, + /** + * @DP_DPCD_QUIRK_NO_PSR: + * + * The device does not support PSR even if reports that it supports or + * driver still need to implement proper handling for such device. + */ + DP_DPCD_QUIRK_NO_PSR, + /** + * @DP_DPCD_QUIRK_NO_SINK_COUNT: + * + * The device does not set SINK_COUNT to a non-zero value. + * The driver should ignore SINK_COUNT during detection. Note that + * drm_dp_read_sink_count_cap() automatically checks for this quirk. + */ + DP_DPCD_QUIRK_NO_SINK_COUNT, + /** + * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: + * + * The device supports MST DSC despite not supporting Virtual DPCD. + * The DSC caps can be read from the physical aux instead. + */ + DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, + /** + * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: + * + * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite + * the DP_MAX_LINK_RATE register reporting a lower max multiplier. + */ + DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, +}; + +/** + * drm_dp_has_quirk() - does the DP device have a specific quirk + * @desc: Device descriptor filled by drm_dp_read_desc() + * @quirk: Quirk to query for + * + * Return true if DP device identified by @desc has @quirk. + */ +static inline bool +drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) +{ + return desc->quirks & BIT(quirk); +} + +/** + * struct drm_edp_backlight_info - Probed eDP backlight info struct + * @pwmgen_bit_count: The pwmgen bit count + * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any + * @max: The maximum backlight level that may be set + * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? + * @aux_enable: Does the panel support the AUX enable cap? + * @aux_set: Does the panel support setting the brightness through AUX? + * + * This structure contains various data about an eDP backlight, which can be populated by using + * drm_edp_backlight_init(). + */ +struct drm_edp_backlight_info { + u8 pwmgen_bit_count; + u8 pwm_freq_pre_divider; + u16 max; + + bool lsb_reg_used : 1; + bool aux_enable : 1; + bool aux_set : 1; +}; + +int +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], + u16 *current_level, u8 *current_mode); +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, + u16 level); +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, + u16 level); +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); + +#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ + (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) + +int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); + +#else + +static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, + struct drm_dp_aux *aux) +{ + return 0; +} + +#endif + +#ifdef CONFIG_DRM_DP_CEC +void drm_dp_cec_irq(struct drm_dp_aux *aux); +void drm_dp_cec_register_connector(struct drm_dp_aux *aux, + struct drm_connector *connector); +void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); +void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); +void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); +#else +static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) +{ +} + +static inline void +drm_dp_cec_register_connector(struct drm_dp_aux *aux, + struct drm_connector *connector) +{ +} + +static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) +{ +} + +static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, + const struct edid *edid) +{ +} + +static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) +{ +} + +#endif + +/** + * struct drm_dp_phy_test_params - DP Phy Compliance parameters + * @link_rate: Requested Link rate from DPCD 0x219 + * @num_lanes: Number of lanes requested by sing through DPCD 0x220 + * @phy_pattern: DP Phy test pattern from DPCD 0x248 + * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 + * @enhanced_frame_cap: flag for enhanced frame capability. + */ +struct drm_dp_phy_test_params { + int link_rate; + u8 num_lanes; + u8 phy_pattern; + u8 hbr2_reset[2]; + u8 custom80[10]; + bool enhanced_frame_cap; +}; + +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data); +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, + struct drm_dp_phy_test_params *data, u8 dp_rev); +int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4]); +int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); +bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); +int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, + u8 frl_mode); +int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, + u8 frl_type); +int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); +int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); + +bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); +int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); +void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, + struct drm_connector *connector); +bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); +int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); +int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); +int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); +int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); +int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); +int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); +bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], + const u8 port_cap[4], u8 color_spc); +int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); + +#endif /* _DRM_DP_HELPER_H_ */ diff --git a/include/drm/dp/drm_dp_mst_helper.h b/include/drm/dp/drm_dp_mst_helper.h new file mode 100644 index 000000000000..08276eb8c187 --- /dev/null +++ b/include/drm/dp/drm_dp_mst_helper.h @@ -0,0 +1,972 @@ +/* + * Copyright © 2014 Red Hat. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _DRM_DP_MST_HELPER_H_ +#define _DRM_DP_MST_HELPER_H_ + +#include +#include +#include + +#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) +#include +#include + +enum drm_dp_mst_topology_ref_type { + DRM_DP_MST_TOPOLOGY_REF_GET, + DRM_DP_MST_TOPOLOGY_REF_PUT, +}; + +struct drm_dp_mst_topology_ref_history { + struct drm_dp_mst_topology_ref_entry { + enum drm_dp_mst_topology_ref_type type; + int count; + ktime_t ts_nsec; + depot_stack_handle_t backtrace; + } *entries; + int len; +}; +#endif /* IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) */ + +struct drm_dp_mst_branch; + +/** + * struct drm_dp_vcpi - Virtual Channel Payload Identifier + * @vcpi: Virtual channel ID. + * @pbn: Payload Bandwidth Number for this channel + * @aligned_pbn: PBN aligned with slot size + * @num_slots: number of slots for this PBN + */ +struct drm_dp_vcpi { + int vcpi; + int pbn; + int aligned_pbn; + int num_slots; +}; + +/** + * struct drm_dp_mst_port - MST port + * @port_num: port number + * @input: if this port is an input port. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @mcs: message capability status - DP 1.2 spec. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @ddps: DisplayPort Device Plug Status - DP 1.2. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @pdt: Peer Device Type. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @ldps: Legacy Device Plug Status. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @dpcd_rev: DPCD revision of device on this port. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @num_sdp_streams: Number of simultaneous streams. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @num_sdp_stream_sinks: Number of stream sinks. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @full_pbn: Max possible bandwidth for this port. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @next: link to next port on this branch device + * @aux: i2c aux transport to talk to device connected to this port, protected + * by &drm_dp_mst_topology_mgr.base.lock. + * @parent: branch device parent of this port + * @vcpi: Virtual Channel Payload info for this port. + * @connector: DRM connector this port is connected to. Protected by + * &drm_dp_mst_topology_mgr.base.lock. + * @mgr: topology manager this port lives under. + * + * This structure represents an MST port endpoint on a device somewhere + * in the MST topology. + */ +struct drm_dp_mst_port { + /** + * @topology_kref: refcount for this port's lifetime in the topology, + * only the DP MST helpers should need to touch this + */ + struct kref topology_kref; + + /** + * @malloc_kref: refcount for the memory allocation containing this + * structure. See drm_dp_mst_get_port_malloc() and + * drm_dp_mst_put_port_malloc(). + */ + struct kref malloc_kref; + +#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) + /** + * @topology_ref_history: A history of each topology + * reference/dereference. See CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS. + */ + struct drm_dp_mst_topology_ref_history topology_ref_history; +#endif + + u8 port_num; + bool input; + bool mcs; + bool ddps; + u8 pdt; + bool ldps; + u8 dpcd_rev; + u8 num_sdp_streams; + u8 num_sdp_stream_sinks; + uint16_t full_pbn; + struct list_head next; + /** + * @mstb: the branch device connected to this port, if there is one. + * This should be considered protected for reading by + * &drm_dp_mst_topology_mgr.lock. There are two exceptions to this: + * &drm_dp_mst_topology_mgr.up_req_work and + * &drm_dp_mst_topology_mgr.work, which do not grab + * &drm_dp_mst_topology_mgr.lock during reads but are the only + * updaters of this list and are protected from writing concurrently + * by &drm_dp_mst_topology_mgr.probe_lock. + */ + struct drm_dp_mst_branch *mstb; + struct drm_dp_aux aux; /* i2c bus for this port? */ + struct drm_dp_mst_branch *parent; + + struct drm_dp_vcpi vcpi; + struct drm_connector *connector; + struct drm_dp_mst_topology_mgr *mgr; + + /** + * @cached_edid: for DP logical ports - make tiling work by ensuring + * that the EDID for all connectors is read immediately. + */ + struct edid *cached_edid; + /** + * @has_audio: Tracks whether the sink connector to this port is + * audio-capable. + */ + bool has_audio; + + /** + * @fec_capable: bool indicating if FEC can be supported up to that + * point in the MST topology. + */ + bool fec_capable; +}; + +/* sideband msg header - not bit struct */ +struct drm_dp_sideband_msg_hdr { + u8 lct; + u8 lcr; + u8 rad[8]; + bool broadcast; + bool path_msg; + u8 msg_len; + bool somt; + bool eomt; + bool seqno; +}; + +struct drm_dp_sideband_msg_rx { + u8 chunk[48]; + u8 msg[256]; + u8 curchunk_len; + u8 curchunk_idx; /* chunk we are parsing now */ + u8 curchunk_hdrlen; + u8 curlen; /* total length of the msg */ + bool have_somt; + bool have_eomt; + struct drm_dp_sideband_msg_hdr initial_hdr; +}; + +/** + * struct drm_dp_mst_branch - MST branch device. + * @rad: Relative Address to talk to this branch device. + * @lct: Link count total to talk to this branch device. + * @num_ports: number of ports on the branch. + * @port_parent: pointer to the port parent, NULL if toplevel. + * @mgr: topology manager for this branch device. + * @link_address_sent: if a link address message has been sent to this device yet. + * @guid: guid for DP 1.2 branch device. port under this branch can be + * identified by port #. + * + * This structure represents an MST branch device, there is one + * primary branch device at the root, along with any other branches connected + * to downstream port of parent branches. + */ +struct drm_dp_mst_branch { + /** + * @topology_kref: refcount for this branch device's lifetime in the + * topology, only the DP MST helpers should need to touch this + */ + struct kref topology_kref; + + /** + * @malloc_kref: refcount for the memory allocation containing this + * structure. See drm_dp_mst_get_mstb_malloc() and + * drm_dp_mst_put_mstb_malloc(). + */ + struct kref malloc_kref; + +#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) + /** + * @topology_ref_history: A history of each topology + * reference/dereference. See CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS. + */ + struct drm_dp_mst_topology_ref_history topology_ref_history; +#endif + + /** + * @destroy_next: linked-list entry used by + * drm_dp_delayed_destroy_work() + */ + struct list_head destroy_next; + + u8 rad[8]; + u8 lct; + int num_ports; + + /** + * @ports: the list of ports on this branch device. This should be + * considered protected for reading by &drm_dp_mst_topology_mgr.lock. + * There are two exceptions to this: + * &drm_dp_mst_topology_mgr.up_req_work and + * &drm_dp_mst_topology_mgr.work, which do not grab + * &drm_dp_mst_topology_mgr.lock during reads but are the only + * updaters of this list and are protected from updating the list + * concurrently by @drm_dp_mst_topology_mgr.probe_lock + */ + struct list_head ports; + + struct drm_dp_mst_port *port_parent; + struct drm_dp_mst_topology_mgr *mgr; + + bool link_address_sent; + + /* global unique identifier to identify branch devices */ + u8 guid[16]; +}; + + +struct drm_dp_nak_reply { + u8 guid[16]; + u8 reason; + u8 nak_data; +}; + +struct drm_dp_link_address_ack_reply { + u8 guid[16]; + u8 nports; + struct drm_dp_link_addr_reply_port { + bool input_port; + u8 peer_device_type; + u8 port_number; + bool mcs; + bool ddps; + bool legacy_device_plug_status; + u8 dpcd_revision; + u8 peer_guid[16]; + u8 num_sdp_streams; + u8 num_sdp_stream_sinks; + } ports[16]; +}; + +struct drm_dp_remote_dpcd_read_ack_reply { + u8 port_number; + u8 num_bytes; + u8 bytes[255]; +}; + +struct drm_dp_remote_dpcd_write_ack_reply { + u8 port_number; +}; + +struct drm_dp_remote_dpcd_write_nak_reply { + u8 port_number; + u8 reason; + u8 bytes_written_before_failure; +}; + +struct drm_dp_remote_i2c_read_ack_reply { + u8 port_number; + u8 num_bytes; + u8 bytes[255]; +}; + +struct drm_dp_remote_i2c_read_nak_reply { + u8 port_number; + u8 nak_reason; + u8 i2c_nak_transaction; +}; + +struct drm_dp_remote_i2c_write_ack_reply { + u8 port_number; +}; + +struct drm_dp_query_stream_enc_status_ack_reply { + /* Bit[23:16]- Stream Id */ + u8 stream_id; + + /* Bit[15]- Signed */ + bool reply_signed; + + /* Bit[10:8]- Stream Output Sink Type */ + bool unauthorizable_device_present; + bool legacy_device_present; + bool query_capable_device_present; + + /* Bit[12:11]- Stream Output CP Type */ + bool hdcp_1x_device_present; + bool hdcp_2x_device_present; + + /* Bit[4]- Stream Authentication */ + bool auth_completed; + + /* Bit[3]- Stream Encryption */ + bool encryption_enabled; + + /* Bit[2]- Stream Repeater Function Present */ + bool repeater_present; + + /* Bit[1:0]- Stream State */ + u8 state; +}; + +#define DRM_DP_MAX_SDP_STREAMS 16 +struct drm_dp_allocate_payload { + u8 port_number; + u8 number_sdp_streams; + u8 vcpi; + u16 pbn; + u8 sdp_stream_sink[DRM_DP_MAX_SDP_STREAMS]; +}; + +struct drm_dp_allocate_payload_ack_reply { + u8 port_number; + u8 vcpi; + u16 allocated_pbn; +}; + +struct drm_dp_connection_status_notify { + u8 guid[16]; + u8 port_number; + bool legacy_device_plug_status; + bool displayport_device_plug_status; + bool message_capability_status; + bool input_port; + u8 peer_device_type; +}; + +struct drm_dp_remote_dpcd_read { + u8 port_number; + u32 dpcd_address; + u8 num_bytes; +}; + +struct drm_dp_remote_dpcd_write { + u8 port_number; + u32 dpcd_address; + u8 num_bytes; + u8 *bytes; +}; + +#define DP_REMOTE_I2C_READ_MAX_TRANSACTIONS 4 +struct drm_dp_remote_i2c_read { + u8 num_transactions; + u8 port_number; + struct drm_dp_remote_i2c_read_tx { + u8 i2c_dev_id; + u8 num_bytes; + u8 *bytes; + u8 no_stop_bit; + u8 i2c_transaction_delay; + } transactions[DP_REMOTE_I2C_READ_MAX_TRANSACTIONS]; + u8 read_i2c_device_id; + u8 num_bytes_read; +}; + +struct drm_dp_remote_i2c_write { + u8 port_number; + u8 write_i2c_device_id; + u8 num_bytes; + u8 *bytes; +}; + +struct drm_dp_query_stream_enc_status { + u8 stream_id; + u8 client_id[7]; /* 56-bit nonce */ + u8 stream_event; + bool valid_stream_event; + u8 stream_behavior; + u8 valid_stream_behavior; +}; + +/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ +struct drm_dp_port_number_req { + u8 port_number; +}; + +struct drm_dp_enum_path_resources_ack_reply { + u8 port_number; + bool fec_capable; + u16 full_payload_bw_number; + u16 avail_payload_bw_number; +}; + +/* covers POWER_DOWN_PHY, POWER_UP_PHY */ +struct drm_dp_port_number_rep { + u8 port_number; +}; + +struct drm_dp_query_payload { + u8 port_number; + u8 vcpi; +}; + +struct drm_dp_resource_status_notify { + u8 port_number; + u8 guid[16]; + u16 available_pbn; +}; + +struct drm_dp_query_payload_ack_reply { + u8 port_number; + u16 allocated_pbn; +}; + +struct drm_dp_sideband_msg_req_body { + u8 req_type; + union ack_req { + struct drm_dp_connection_status_notify conn_stat; + struct drm_dp_port_number_req port_num; + struct drm_dp_resource_status_notify resource_stat; + + struct drm_dp_query_payload query_payload; + struct drm_dp_allocate_payload allocate_payload; + + struct drm_dp_remote_dpcd_read dpcd_read; + struct drm_dp_remote_dpcd_write dpcd_write; + + struct drm_dp_remote_i2c_read i2c_read; + struct drm_dp_remote_i2c_write i2c_write; + + struct drm_dp_query_stream_enc_status enc_status; + } u; +}; + +struct drm_dp_sideband_msg_reply_body { + u8 reply_type; + u8 req_type; + union ack_replies { + struct drm_dp_nak_reply nak; + struct drm_dp_link_address_ack_reply link_addr; + struct drm_dp_port_number_rep port_number; + + struct drm_dp_enum_path_resources_ack_reply path_resources; + struct drm_dp_allocate_payload_ack_reply allocate_payload; + struct drm_dp_query_payload_ack_reply query_payload; + + struct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack; + struct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack; + struct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack; + + struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; + struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; + struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack; + + struct drm_dp_query_stream_enc_status_ack_reply enc_status; + } u; +}; + +/* msg is queued to be put into a slot */ +#define DRM_DP_SIDEBAND_TX_QUEUED 0 +/* msg has started transmitting on a slot - still on msgq */ +#define DRM_DP_SIDEBAND_TX_START_SEND 1 +/* msg has finished transmitting on a slot - removed from msgq only in slot */ +#define DRM_DP_SIDEBAND_TX_SENT 2 +/* msg has received a response - removed from slot */ +#define DRM_DP_SIDEBAND_TX_RX 3 +#define DRM_DP_SIDEBAND_TX_TIMEOUT 4 + +struct drm_dp_sideband_msg_tx { + u8 msg[256]; + u8 chunk[48]; + u8 cur_offset; + u8 cur_len; + struct drm_dp_mst_branch *dst; + struct list_head next; + int seqno; + int state; + bool path_msg; + struct drm_dp_sideband_msg_reply_body reply; +}; + +/* sideband msg handler */ +struct drm_dp_mst_topology_mgr; +struct drm_dp_mst_topology_cbs { + /* create a connector for a port */ + struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); + /* + * Checks for any pending MST interrupts, passing them to MST core for + * processing, the same way an HPD IRQ pulse handler would do this. + * If provided MST core calls this callback from a poll-waiting loop + * when waiting for MST down message replies. The driver is expected + * to guard against a race between this callback and the driver's HPD + * IRQ pulse handler. + */ + void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); +}; + +#define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) + +#define DP_PAYLOAD_LOCAL 1 +#define DP_PAYLOAD_REMOTE 2 +#define DP_PAYLOAD_DELETE_LOCAL 3 + +struct drm_dp_payload { + int payload_state; + int start_slot; + int num_slots; + int vcpi; +}; + +#define to_dp_mst_topology_state(x) container_of(x, struct drm_dp_mst_topology_state, base) + +struct drm_dp_vcpi_allocation { + struct drm_dp_mst_port *port; + int vcpi; + int pbn; + bool dsc_enabled; + struct list_head next; +}; + +struct drm_dp_mst_topology_state { + struct drm_private_state base; + struct list_head vcpis; + struct drm_dp_mst_topology_mgr *mgr; + u8 total_avail_slots; + u8 start_slot; +}; + +#define to_dp_mst_topology_mgr(x) container_of(x, struct drm_dp_mst_topology_mgr, base) + +/** + * struct drm_dp_mst_topology_mgr - DisplayPort MST manager + * + * This struct represents the toplevel displayport MST topology manager. + * There should be one instance of this for every MST capable DP connector + * on the GPU. + */ +struct drm_dp_mst_topology_mgr { + /** + * @base: Base private object for atomic + */ + struct drm_private_obj base; + + /** + * @dev: device pointer for adding i2c devices etc. + */ + struct drm_device *dev; + /** + * @cbs: callbacks for connector addition and destruction. + */ + const struct drm_dp_mst_topology_cbs *cbs; + /** + * @max_dpcd_transaction_bytes: maximum number of bytes to read/write + * in one go. + */ + int max_dpcd_transaction_bytes; + /** + * @aux: AUX channel for the DP MST connector this topolgy mgr is + * controlling. + */ + struct drm_dp_aux *aux; + /** + * @max_payloads: maximum number of payloads the GPU can generate. + */ + int max_payloads; + /** + * @max_lane_count: maximum number of lanes the GPU can drive. + */ + int max_lane_count; + /** + * @max_link_rate: maximum link rate per lane GPU can output, in kHz. + */ + int max_link_rate; + /** + * @conn_base_id: DRM connector ID this mgr is connected to. Only used + * to build the MST connector path value. + */ + int conn_base_id; + + /** + * @up_req_recv: Message receiver state for up requests. + */ + struct drm_dp_sideband_msg_rx up_req_recv; + + /** + * @down_rep_recv: Message receiver state for replies to down + * requests. + */ + struct drm_dp_sideband_msg_rx down_rep_recv; + + /** + * @lock: protects @mst_state, @mst_primary, @dpcd, and + * @payload_id_table_cleared. + */ + struct mutex lock; + + /** + * @probe_lock: Prevents @work and @up_req_work, the only writers of + * &drm_dp_mst_port.mstb and &drm_dp_mst_branch.ports, from racing + * while they update the topology. + */ + struct mutex probe_lock; + + /** + * @mst_state: If this manager is enabled for an MST capable port. False + * if no MST sink/branch devices is connected. + */ + bool mst_state : 1; + + /** + * @payload_id_table_cleared: Whether or not we've cleared the payload + * ID table for @mst_primary. Protected by @lock. + */ + bool payload_id_table_cleared : 1; + + /** + * @mst_primary: Pointer to the primary/first branch device. + */ + struct drm_dp_mst_branch *mst_primary; + + /** + * @dpcd: Cache of DPCD for primary port. + */ + u8 dpcd[DP_RECEIVER_CAP_SIZE]; + /** + * @sink_count: Sink count from DEVICE_SERVICE_IRQ_VECTOR_ESI0. + */ + u8 sink_count; + /** + * @pbn_div: PBN to slots divisor. + */ + int pbn_div; + + /** + * @funcs: Atomic helper callbacks + */ + const struct drm_private_state_funcs *funcs; + + /** + * @qlock: protects @tx_msg_downq and &drm_dp_sideband_msg_tx.state + */ + struct mutex qlock; + + /** + * @tx_msg_downq: List of pending down requests + */ + struct list_head tx_msg_downq; + + /** + * @payload_lock: Protect payload information. + */ + struct mutex payload_lock; + /** + * @proposed_vcpis: Array of pointers for the new VCPI allocation. The + * VCPI structure itself is &drm_dp_mst_port.vcpi, and the size of + * this array is determined by @max_payloads. + */ + struct drm_dp_vcpi **proposed_vcpis; + /** + * @payloads: Array of payloads. The size of this array is determined + * by @max_payloads. + */ + struct drm_dp_payload *payloads; + /** + * @payload_mask: Elements of @payloads actually in use. Since + * reallocation of active outputs isn't possible gaps can be created by + * disabling outputs out of order compared to how they've been enabled. + */ + unsigned long payload_mask; + /** + * @vcpi_mask: Similar to @payload_mask, but for @proposed_vcpis. + */ + unsigned long vcpi_mask; + + /** + * @tx_waitq: Wait to queue stall for the tx worker. + */ + wait_queue_head_t tx_waitq; + /** + * @work: Probe work. + */ + struct work_struct work; + /** + * @tx_work: Sideband transmit worker. This can nest within the main + * @work worker for each transaction @work launches. + */ + struct work_struct tx_work; + + /** + * @destroy_port_list: List of to be destroyed connectors. + */ + struct list_head destroy_port_list; + /** + * @destroy_branch_device_list: List of to be destroyed branch + * devices. + */ + struct list_head destroy_branch_device_list; + /** + * @delayed_destroy_lock: Protects @destroy_port_list and + * @destroy_branch_device_list. + */ + struct mutex delayed_destroy_lock; + + /** + * @delayed_destroy_wq: Workqueue used for delayed_destroy_work items. + * A dedicated WQ makes it possible to drain any requeued work items + * on it. + */ + struct workqueue_struct *delayed_destroy_wq; + + /** + * @delayed_destroy_work: Work item to destroy MST port and branch + * devices, needed to avoid locking inversion. + */ + struct work_struct delayed_destroy_work; + + /** + * @up_req_list: List of pending up requests from the topology that + * need to be processed, in chronological order. + */ + struct list_head up_req_list; + /** + * @up_req_lock: Protects @up_req_list + */ + struct mutex up_req_lock; + /** + * @up_req_work: Work item to process up requests received from the + * topology. Needed to avoid blocking hotplug handling and sideband + * transmissions. + */ + struct work_struct up_req_work; + +#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) + /** + * @topology_ref_history_lock: protects + * &drm_dp_mst_port.topology_ref_history and + * &drm_dp_mst_branch.topology_ref_history. + */ + struct mutex topology_ref_history_lock; +#endif +}; + +int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, + struct drm_device *dev, struct drm_dp_aux *aux, + int max_dpcd_transaction_bytes, + int max_payloads, + int max_lane_count, int max_link_rate, + int conn_base_id); + +void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); + +bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state); + +int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled); + + +int +drm_dp_mst_detect_port(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port); + +struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); + +int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, + int link_rate, int link_lane_count); + +int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc); + +bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, int slots); + +int drm_dp_mst_get_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); + + +void drm_dp_mst_reset_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); + +void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap); + +void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port); + + +int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, + int pbn); + + +int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr, int start_slot); + + +int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr); + +int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr); + +void drm_dp_mst_dump_topology(struct seq_file *m, + struct drm_dp_mst_topology_mgr *mgr); + +void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr); +int __must_check +drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, + bool sync); + +ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux, + unsigned int offset, void *buffer, size_t size); +ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux, + unsigned int offset, void *buffer, size_t size); + +int drm_dp_mst_connector_late_register(struct drm_connector *connector, + struct drm_dp_mst_port *port); +void drm_dp_mst_connector_early_unregister(struct drm_connector *connector, + struct drm_dp_mst_port *port); + +struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr); +int __must_check +drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div); +int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state, + struct drm_dp_mst_port *port, + int pbn, int pbn_div, + bool enable); +int __must_check +drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr); +int __must_check +drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port); +int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, bool power_up); +int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, + struct drm_dp_query_stream_enc_status_ack_reply *status); +int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state); + +void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); +void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port); + +struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port); + +extern const struct drm_private_state_funcs drm_dp_mst_topology_state_funcs; + +/** + * __drm_dp_mst_state_iter_get - private atomic state iterator function for + * macro-internal use + * @state: &struct drm_atomic_state pointer + * @mgr: pointer to the &struct drm_dp_mst_topology_mgr iteration cursor + * @old_state: optional pointer to the old &struct drm_dp_mst_topology_state + * iteration cursor + * @new_state: optional pointer to the new &struct drm_dp_mst_topology_state + * iteration cursor + * @i: int iteration cursor, for macro-internal use + * + * Used by for_each_oldnew_mst_mgr_in_state(), + * for_each_old_mst_mgr_in_state(), and for_each_new_mst_mgr_in_state(). Don't + * call this directly. + * + * Returns: + * True if the current &struct drm_private_obj is a &struct + * drm_dp_mst_topology_mgr, false otherwise. + */ +static inline bool +__drm_dp_mst_state_iter_get(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr **mgr, + struct drm_dp_mst_topology_state **old_state, + struct drm_dp_mst_topology_state **new_state, + int i) +{ + struct __drm_private_objs_state *objs_state = &state->private_objs[i]; + + if (objs_state->ptr->funcs != &drm_dp_mst_topology_state_funcs) + return false; + + *mgr = to_dp_mst_topology_mgr(objs_state->ptr); + if (old_state) + *old_state = to_dp_mst_topology_state(objs_state->old_state); + if (new_state) + *new_state = to_dp_mst_topology_state(objs_state->new_state); + + return true; +} + +/** + * for_each_oldnew_mst_mgr_in_state - iterate over all DP MST topology + * managers in an atomic update + * @__state: &struct drm_atomic_state pointer + * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor + * @old_state: &struct drm_dp_mst_topology_state iteration cursor for the old + * state + * @new_state: &struct drm_dp_mst_topology_state iteration cursor for the new + * state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all DRM DP MST topology managers in an atomic update, + * tracking both old and new state. This is useful in places where the state + * delta needs to be considered, for example in atomic check functions. + */ +#define for_each_oldnew_mst_mgr_in_state(__state, mgr, old_state, new_state, __i) \ + for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ + for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), &(old_state), &(new_state), (__i))) + +/** + * for_each_old_mst_mgr_in_state - iterate over all DP MST topology managers + * in an atomic update + * @__state: &struct drm_atomic_state pointer + * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor + * @old_state: &struct drm_dp_mst_topology_state iteration cursor for the old + * state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all DRM DP MST topology managers in an atomic update, + * tracking only the old state. This is useful in disable functions, where we + * need the old state the hardware is still in. + */ +#define for_each_old_mst_mgr_in_state(__state, mgr, old_state, __i) \ + for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ + for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), &(old_state), NULL, (__i))) + +/** + * for_each_new_mst_mgr_in_state - iterate over all DP MST topology managers + * in an atomic update + * @__state: &struct drm_atomic_state pointer + * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor + * @new_state: &struct drm_dp_mst_topology_state iteration cursor for the new + * state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all DRM DP MST topology managers in an atomic update, + * tracking only the new state. This is useful in enable functions, where we + * need the new state the hardware should be in when the atomic commit + * operation has completed. + */ +#define for_each_new_mst_mgr_in_state(__state, mgr, new_state, __i) \ + for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ + for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), NULL, &(new_state), (__i))) + +#endif diff --git a/include/drm/drm_dp_dual_mode_helper.h b/include/drm/drm_dp_dual_mode_helper.h deleted file mode 100644 index 7ee482265087..000000000000 --- a/include/drm/drm_dp_dual_mode_helper.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef DRM_DP_DUAL_MODE_HELPER_H -#define DRM_DP_DUAL_MODE_HELPER_H - -#include - -/* - * Optional for type 1 DVI adaptors - * Mandatory for type 1 HDMI and type 2 adaptors - */ -#define DP_DUAL_MODE_HDMI_ID 0x00 /* 00-0f */ -#define DP_DUAL_MODE_HDMI_ID_LEN 16 -/* - * Optional for type 1 adaptors - * Mandatory for type 2 adaptors - */ -#define DP_DUAL_MODE_ADAPTOR_ID 0x10 -#define DP_DUAL_MODE_REV_MASK 0x07 -#define DP_DUAL_MODE_REV_TYPE2 0x00 -#define DP_DUAL_MODE_TYPE_MASK 0xf0 -#define DP_DUAL_MODE_TYPE_TYPE2 0xa0 -/* This field is marked reserved in dual mode spec, used in LSPCON */ -#define DP_DUAL_MODE_TYPE_HAS_DPCD 0x08 -#define DP_DUAL_MODE_IEEE_OUI 0x11 /* 11-13*/ -#define DP_DUAL_IEEE_OUI_LEN 3 -#define DP_DUAL_DEVICE_ID 0x14 /* 14-19 */ -#define DP_DUAL_DEVICE_ID_LEN 6 -#define DP_DUAL_MODE_HARDWARE_REV 0x1a -#define DP_DUAL_MODE_FIRMWARE_MAJOR_REV 0x1b -#define DP_DUAL_MODE_FIRMWARE_MINOR_REV 0x1c -#define DP_DUAL_MODE_MAX_TMDS_CLOCK 0x1d -#define DP_DUAL_MODE_I2C_SPEED_CAP 0x1e -#define DP_DUAL_MODE_TMDS_OEN 0x20 -#define DP_DUAL_MODE_TMDS_DISABLE 0x01 -#define DP_DUAL_MODE_HDMI_PIN_CTRL 0x21 -#define DP_DUAL_MODE_CEC_ENABLE 0x01 -#define DP_DUAL_MODE_I2C_SPEED_CTRL 0x22 - -/* LSPCON specific registers, defined by MCA */ -#define DP_DUAL_MODE_LSPCON_MODE_CHANGE 0x40 -#define DP_DUAL_MODE_LSPCON_CURRENT_MODE 0x41 -#define DP_DUAL_MODE_LSPCON_MODE_PCON 0x1 - -struct drm_device; -struct i2c_adapter; - -ssize_t drm_dp_dual_mode_read(struct i2c_adapter *adapter, - u8 offset, void *buffer, size_t size); -ssize_t drm_dp_dual_mode_write(struct i2c_adapter *adapter, - u8 offset, const void *buffer, size_t size); - -/** - * enum drm_lspcon_mode - * @DRM_LSPCON_MODE_INVALID: No LSPCON. - * @DRM_LSPCON_MODE_LS: Level shifter mode of LSPCON - * which drives DP++ to HDMI 1.4 conversion. - * @DRM_LSPCON_MODE_PCON: Protocol converter mode of LSPCON - * which drives DP++ to HDMI 2.0 active conversion. - */ -enum drm_lspcon_mode { - DRM_LSPCON_MODE_INVALID, - DRM_LSPCON_MODE_LS, - DRM_LSPCON_MODE_PCON, -}; - -/** - * enum drm_dp_dual_mode_type - Type of the DP dual mode adaptor - * @DRM_DP_DUAL_MODE_NONE: No DP dual mode adaptor - * @DRM_DP_DUAL_MODE_UNKNOWN: Could be either none or type 1 DVI adaptor - * @DRM_DP_DUAL_MODE_TYPE1_DVI: Type 1 DVI adaptor - * @DRM_DP_DUAL_MODE_TYPE1_HDMI: Type 1 HDMI adaptor - * @DRM_DP_DUAL_MODE_TYPE2_DVI: Type 2 DVI adaptor - * @DRM_DP_DUAL_MODE_TYPE2_HDMI: Type 2 HDMI adaptor - * @DRM_DP_DUAL_MODE_LSPCON: Level shifter / protocol converter - */ -enum drm_dp_dual_mode_type { - DRM_DP_DUAL_MODE_NONE, - DRM_DP_DUAL_MODE_UNKNOWN, - DRM_DP_DUAL_MODE_TYPE1_DVI, - DRM_DP_DUAL_MODE_TYPE1_HDMI, - DRM_DP_DUAL_MODE_TYPE2_DVI, - DRM_DP_DUAL_MODE_TYPE2_HDMI, - DRM_DP_DUAL_MODE_LSPCON, -}; - -enum drm_dp_dual_mode_type -drm_dp_dual_mode_detect(const struct drm_device *dev, struct i2c_adapter *adapter); -int drm_dp_dual_mode_max_tmds_clock(const struct drm_device *dev, enum drm_dp_dual_mode_type type, - struct i2c_adapter *adapter); -int drm_dp_dual_mode_get_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type, - struct i2c_adapter *adapter, bool *enabled); -int drm_dp_dual_mode_set_tmds_output(const struct drm_device *dev, enum drm_dp_dual_mode_type type, - struct i2c_adapter *adapter, bool enable); -const char *drm_dp_get_dual_mode_type_name(enum drm_dp_dual_mode_type type); - -int drm_lspcon_get_mode(const struct drm_device *dev, struct i2c_adapter *adapter, - enum drm_lspcon_mode *current_mode); -int drm_lspcon_set_mode(const struct drm_device *dev, struct i2c_adapter *adapter, - enum drm_lspcon_mode reqd_mode); -#endif diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h deleted file mode 100644 index 16d6da3a129f..000000000000 --- a/include/drm/drm_dp_helper.h +++ /dev/null @@ -1,2358 +0,0 @@ -/* - * Copyright © 2008 Keith Packard - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef _DRM_DP_HELPER_H_ -#define _DRM_DP_HELPER_H_ - -#include -#include -#include -#include - -struct drm_device; -struct drm_dp_aux; -struct drm_panel; - -/* - * Unless otherwise noted, all values are from the DP 1.1a spec. Note that - * DP and DPCD versions are independent. Differences from 1.0 are not noted, - * 1.0 devices basically don't exist in the wild. - * - * Abbreviations, in chronological order: - * - * eDP: Embedded DisplayPort version 1 - * DPI: DisplayPort Interoperability Guideline v1.1a - * 1.2: DisplayPort 1.2 - * MST: Multistream Transport - part of DP 1.2a - * - * 1.2 formally includes both eDP and DPI definitions. - */ - -/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */ -#define DP_MSA_MISC_SYNC_CLOCK (1 << 0) -#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8) -#define DP_MSA_MISC_STEREO_NO_3D (0 << 9) -#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9) -#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9) -/* bits per component for non-RAW */ -#define DP_MSA_MISC_6_BPC (0 << 5) -#define DP_MSA_MISC_8_BPC (1 << 5) -#define DP_MSA_MISC_10_BPC (2 << 5) -#define DP_MSA_MISC_12_BPC (3 << 5) -#define DP_MSA_MISC_16_BPC (4 << 5) -/* bits per component for RAW */ -#define DP_MSA_MISC_RAW_6_BPC (1 << 5) -#define DP_MSA_MISC_RAW_7_BPC (2 << 5) -#define DP_MSA_MISC_RAW_8_BPC (3 << 5) -#define DP_MSA_MISC_RAW_10_BPC (4 << 5) -#define DP_MSA_MISC_RAW_12_BPC (5 << 5) -#define DP_MSA_MISC_RAW_14_BPC (6 << 5) -#define DP_MSA_MISC_RAW_16_BPC (7 << 5) -/* pixel encoding/colorimetry format */ -#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \ - ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1)) -#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0) -#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0) -#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0) -#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1) -#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0) -#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0) -#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0) -#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1) -#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0) -#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1) -#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0) -#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1) -#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0) -#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1) -#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1) -#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0) -#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1) -#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14) - -#define DP_AUX_MAX_PAYLOAD_BYTES 16 - -#define DP_AUX_I2C_WRITE 0x0 -#define DP_AUX_I2C_READ 0x1 -#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2 -#define DP_AUX_I2C_MOT 0x4 -#define DP_AUX_NATIVE_WRITE 0x8 -#define DP_AUX_NATIVE_READ 0x9 - -#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) -#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) -#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) -#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) - -#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) -#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) -#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) -#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) - -/* DPCD Field Address Mapping */ - -/* Receiver Capability */ -#define DP_DPCD_REV 0x000 -# define DP_DPCD_REV_10 0x10 -# define DP_DPCD_REV_11 0x11 -# define DP_DPCD_REV_12 0x12 -# define DP_DPCD_REV_13 0x13 -# define DP_DPCD_REV_14 0x14 - -#define DP_MAX_LINK_RATE 0x001 - -#define DP_MAX_LANE_COUNT 0x002 -# define DP_MAX_LANE_COUNT_MASK 0x1f -# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ -# define DP_ENHANCED_FRAME_CAP (1 << 7) - -#define DP_MAX_DOWNSPREAD 0x003 -# define DP_MAX_DOWNSPREAD_0_5 (1 << 0) -# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */ -# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) -# define DP_TPS4_SUPPORTED (1 << 7) - -#define DP_NORP 0x004 - -#define DP_DOWNSTREAMPORT_PRESENT 0x005 -# define DP_DWN_STRM_PORT_PRESENT (1 << 0) -# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 -# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) -# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) -# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) -# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) -# define DP_FORMAT_CONVERSION (1 << 3) -# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ - -#define DP_MAIN_LINK_CHANNEL_CODING 0x006 -# define DP_CAP_ANSI_8B10B (1 << 0) -# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */ - -#define DP_DOWN_STREAM_PORT_COUNT 0x007 -# define DP_PORT_COUNT_MASK 0x0f -# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ -# define DP_OUI_SUPPORT (1 << 7) - -#define DP_RECEIVE_PORT_0_CAP_0 0x008 -# define DP_LOCAL_EDID_PRESENT (1 << 1) -# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2) - -#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009 - -#define DP_RECEIVE_PORT_1_CAP_0 0x00a -#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b - -#define DP_I2C_SPEED_CAP 0x00c /* DPI */ -# define DP_I2C_SPEED_1K 0x01 -# define DP_I2C_SPEED_5K 0x02 -# define DP_I2C_SPEED_10K 0x04 -# define DP_I2C_SPEED_100K 0x08 -# define DP_I2C_SPEED_400K 0x10 -# define DP_I2C_SPEED_1M 0x20 - -#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ -# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0) -# define DP_FRAMING_CHANGE_CAP (1 << 1) -# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */ - -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ -# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */ -# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */ - -#define DP_ADAPTER_CAP 0x00f /* 1.2 */ -# define DP_FORCE_LOAD_SENSE_CAP (1 << 0) -# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1) - -#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */ -# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */ - -/* Multiple stream transport */ -#define DP_FAUX_CAP 0x020 /* 1.2 */ -# define DP_FAUX_CAP_1 (1 << 0) - -#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */ -# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0) -# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1) -# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2) - -#define DP_MSTM_CAP 0x021 /* 1.2 */ -# define DP_MST_CAP (1 << 0) -# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */ - -#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */ - -/* AV_SYNC_DATA_BLOCK 1.2 */ -#define DP_AV_GRANULARITY 0x023 -# define DP_AG_FACTOR_MASK (0xf << 0) -# define DP_AG_FACTOR_3MS (0 << 0) -# define DP_AG_FACTOR_2MS (1 << 0) -# define DP_AG_FACTOR_1MS (2 << 0) -# define DP_AG_FACTOR_500US (3 << 0) -# define DP_AG_FACTOR_200US (4 << 0) -# define DP_AG_FACTOR_100US (5 << 0) -# define DP_AG_FACTOR_10US (6 << 0) -# define DP_AG_FACTOR_1US (7 << 0) -# define DP_VG_FACTOR_MASK (0xf << 4) -# define DP_VG_FACTOR_3MS (0 << 4) -# define DP_VG_FACTOR_2MS (1 << 4) -# define DP_VG_FACTOR_1MS (2 << 4) -# define DP_VG_FACTOR_500US (3 << 4) -# define DP_VG_FACTOR_200US (4 << 4) -# define DP_VG_FACTOR_100US (5 << 4) - -#define DP_AUD_DEC_LAT0 0x024 -#define DP_AUD_DEC_LAT1 0x025 - -#define DP_AUD_PP_LAT0 0x026 -#define DP_AUD_PP_LAT1 0x027 - -#define DP_VID_INTER_LAT 0x028 - -#define DP_VID_PROG_LAT 0x029 - -#define DP_REP_LAT 0x02a - -#define DP_AUD_DEL_INS0 0x02b -#define DP_AUD_DEL_INS1 0x02c -#define DP_AUD_DEL_INS2 0x02d -/* End of AV_SYNC_DATA_BLOCK */ - -#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ -# define DP_ALPM_CAP (1 << 0) - -#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ -# define DP_AUX_FRAME_SYNC_CAP (1 << 0) - -#define DP_GUID 0x030 /* 1.2 */ - -#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ -# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) - -#define DP_DSC_REV 0x061 -# define DP_DSC_MAJOR_MASK (0xf << 0) -# define DP_DSC_MINOR_MASK (0xf << 4) -# define DP_DSC_MAJOR_SHIFT 0 -# define DP_DSC_MINOR_SHIFT 4 - -#define DP_DSC_RC_BUF_BLK_SIZE 0x062 -# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0 -# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1 -# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2 -# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3 - -#define DP_DSC_RC_BUF_SIZE 0x063 - -#define DP_DSC_SLICE_CAP_1 0x064 -# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0) -# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1) -# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3) -# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4) -# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5) -# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6) -# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7) - -#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065 -# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0) -# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0 -# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1 -# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2 -# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3 -# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4 -# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5 -# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6 -# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7 -# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8 - -#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 -# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) - -#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ - -#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ -# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) -# define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 - -#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 -# define DP_DSC_RGB (1 << 0) -# define DP_DSC_YCbCr444 (1 << 1) -# define DP_DSC_YCbCr422_Simple (1 << 2) -# define DP_DSC_YCbCr422_Native (1 << 3) -# define DP_DSC_YCbCr420_Native (1 << 4) - -#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A -# define DP_DSC_8_BPC (1 << 1) -# define DP_DSC_10_BPC (1 << 2) -# define DP_DSC_12_BPC (1 << 3) - -#define DP_DSC_PEAK_THROUGHPUT 0x06B -# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0) -# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0 -# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 -# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0) -# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ -# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4) -# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4 -# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0 -# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4) -# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4) - -#define DP_DSC_MAX_SLICE_WIDTH 0x06C -#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560 -#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320 - -#define DP_DSC_SLICE_CAP_2 0x06D -# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0) -# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1) -# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) - -#define DP_DSC_BITS_PER_PIXEL_INC 0x06F -# define DP_DSC_BITS_PER_PIXEL_1_16 0x0 -# define DP_DSC_BITS_PER_PIXEL_1_8 0x1 -# define DP_DSC_BITS_PER_PIXEL_1_4 0x2 -# define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 - -#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ -# define DP_PSR_IS_SUPPORTED 1 -# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */ -# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ - -#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ -# define DP_PSR_NO_TRAIN_ON_EXIT 1 -# define DP_PSR_SETUP_TIME_330 (0 << 1) -# define DP_PSR_SETUP_TIME_275 (1 << 1) -# define DP_PSR_SETUP_TIME_220 (2 << 1) -# define DP_PSR_SETUP_TIME_165 (3 << 1) -# define DP_PSR_SETUP_TIME_110 (4 << 1) -# define DP_PSR_SETUP_TIME_55 (5 << 1) -# define DP_PSR_SETUP_TIME_0 (6 << 1) -# define DP_PSR_SETUP_TIME_MASK (7 << 1) -# define DP_PSR_SETUP_TIME_SHIFT 1 -# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ -# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ - -#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ -#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ - -/* - * 0x80-0x8f describe downstream port capabilities, but there are two layouts - * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, - * each port's descriptor is one byte wide. If it was set, each port's is - * four bytes wide, starting with the one byte from the base info. As of - * DP interop v1.1a only VGA defines additional detail. - */ - -/* offset 0 */ -#define DP_DOWNSTREAM_PORT_0 0x80 -# define DP_DS_PORT_TYPE_MASK (7 << 0) -# define DP_DS_PORT_TYPE_DP 0 -# define DP_DS_PORT_TYPE_VGA 1 -# define DP_DS_PORT_TYPE_DVI 2 -# define DP_DS_PORT_TYPE_HDMI 3 -# define DP_DS_PORT_TYPE_NON_EDID 4 -# define DP_DS_PORT_TYPE_DP_DUALMODE 5 -# define DP_DS_PORT_TYPE_WIRELESS 6 -# define DP_DS_PORT_HPD (1 << 3) -# define DP_DS_NON_EDID_MASK (0xf << 4) -# define DP_DS_NON_EDID_720x480i_60 (1 << 4) -# define DP_DS_NON_EDID_720x480i_50 (2 << 4) -# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4) -# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4) -# define DP_DS_NON_EDID_1280x720_60 (5 << 4) -# define DP_DS_NON_EDID_1280x720_50 (7 << 4) -/* offset 1 for VGA is maximum megapixels per second / 8 */ -/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */ -/* offset 2 for VGA/DVI/HDMI */ -# define DP_DS_MAX_BPC_MASK (3 << 0) -# define DP_DS_8BPC 0 -# define DP_DS_10BPC 1 -# define DP_DS_12BPC 2 -# define DP_DS_16BPC 3 -/* HDMI2.1 PCON FRL CONFIGURATION */ -# define DP_PCON_MAX_FRL_BW (7 << 2) -# define DP_PCON_MAX_0GBPS (0 << 2) -# define DP_PCON_MAX_9GBPS (1 << 2) -# define DP_PCON_MAX_18GBPS (2 << 2) -# define DP_PCON_MAX_24GBPS (3 << 2) -# define DP_PCON_MAX_32GBPS (4 << 2) -# define DP_PCON_MAX_40GBPS (5 << 2) -# define DP_PCON_MAX_48GBPS (6 << 2) -# define DP_PCON_SOURCE_CTL_MODE (1 << 5) - -/* offset 3 for DVI */ -# define DP_DS_DVI_DUAL_LINK (1 << 1) -# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2) -/* offset 3 for HDMI */ -# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0) -# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1) -# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2) -# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3) -# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4) - -/* - * VESA DP-to-HDMI PCON Specification adds caps for colorspace - * conversion in DFP cap DPCD 83h. Sec6.1 Table-3. - * Based on the available support the source can enable - * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2 - * DPCD 3052h. - */ -# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5) -# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6) -# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7) - -#define DP_MAX_DOWNSTREAM_PORTS 0x10 - -/* DP Forward error Correction Registers */ -#define DP_FEC_CAPABILITY 0x090 /* 1.4 */ -# define DP_FEC_CAPABLE (1 << 0) -# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) -# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) -# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) -#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ - -/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ -#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ -#define DP_PCON_DSC_ENCODER 0x092 -# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0) -# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1) - -/* DP-HDMI2.1 PCON DSC Version */ -#define DP_PCON_DSC_VERSION 0x093 -# define DP_PCON_DSC_MAJOR_MASK (0xF << 0) -# define DP_PCON_DSC_MINOR_MASK (0xF << 4) -# define DP_PCON_DSC_MAJOR_SHIFT 0 -# define DP_PCON_DSC_MINOR_SHIFT 4 - -/* DP-HDMI2.1 PCON DSC RC Buffer block size */ -#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094 -# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0) -# define DP_PCON_DSC_RC_BUF_BLK_1KB 0 -# define DP_PCON_DSC_RC_BUF_BLK_4KB 1 -# define DP_PCON_DSC_RC_BUF_BLK_16KB 2 -# define DP_PCON_DSC_RC_BUF_BLK_64KB 3 - -/* DP-HDMI2.1 PCON DSC RC Buffer size */ -#define DP_PCON_DSC_RC_BUF_SIZE 0x095 - -/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */ -#define DP_PCON_DSC_SLICE_CAP_1 0x096 -# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0) -# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1) -# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3) -# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4) -# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5) -# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6) -# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7) - -#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097 -# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0) -# define DP_PCON_DSC_DEPTH_9_BITS 0 -# define DP_PCON_DSC_DEPTH_10_BITS 1 -# define DP_PCON_DSC_DEPTH_11_BITS 2 -# define DP_PCON_DSC_DEPTH_12_BITS 3 -# define DP_PCON_DSC_DEPTH_13_BITS 4 -# define DP_PCON_DSC_DEPTH_14_BITS 5 -# define DP_PCON_DSC_DEPTH_15_BITS 6 -# define DP_PCON_DSC_DEPTH_16_BITS 7 -# define DP_PCON_DSC_DEPTH_8_BITS 8 - -#define DP_PCON_DSC_BLOCK_PREDICTION 0x098 -# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0) - -#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099 -# define DP_PCON_DSC_ENC_RGB (0x1 << 0) -# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1) -# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2) -# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3) -# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4) - -#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A -# define DP_PCON_DSC_ENC_8BPC (0x1 << 1) -# define DP_PCON_DSC_ENC_10BPC (0x1 << 2) -# define DP_PCON_DSC_ENC_12BPC (0x1 << 3) - -#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B - -/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */ -#define DP_PCON_DSC_SLICE_CAP_2 0x09C -# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0) -# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1) -# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2) - -/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */ -#define DP_PCON_DSC_BPP_INCR 0x09E -# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0) -# define DP_PCON_DSC_ONE_16TH_BPP 0 -# define DP_PCON_DSC_ONE_8TH_BPP 1 -# define DP_PCON_DSC_ONE_4TH_BPP 2 -# define DP_PCON_DSC_ONE_HALF_BPP 3 -# define DP_PCON_DSC_ONE_BPP 4 - -/* DP Extended DSC Capabilities */ -#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ -#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 -#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 - -/* DFP Capability Extension */ -#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ - -/* Link Configuration */ -#define DP_LINK_BW_SET 0x100 -# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ -# define DP_LINK_BW_1_62 0x06 -# define DP_LINK_BW_2_7 0x0a -# define DP_LINK_BW_5_4 0x14 /* 1.2 */ -# define DP_LINK_BW_8_1 0x1e /* 1.4 */ -# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ -# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ -# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ - -#define DP_LANE_COUNT_SET 0x101 -# define DP_LANE_COUNT_MASK 0x0f -# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) - -#define DP_TRAINING_PATTERN_SET 0x102 -# define DP_TRAINING_PATTERN_DISABLE 0 -# define DP_TRAINING_PATTERN_1 1 -# define DP_TRAINING_PATTERN_2 2 -# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ -# define DP_TRAINING_PATTERN_4 7 /* 1.4 */ -# define DP_TRAINING_PATTERN_MASK 0x3 -# define DP_TRAINING_PATTERN_MASK_1_4 0xf - -/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */ -# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2) -# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2) -# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2) -# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2) -# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2) - -# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) -# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) - -# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAINING_LANE0_SET 0x103 -#define DP_TRAINING_LANE1_SET 0x104 -#define DP_TRAINING_LANE2_SET 0x105 -#define DP_TRAINING_LANE3_SET 0x106 - -# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) -# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) -# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) -# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) - -# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) -# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) -# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) -# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) - -# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 -# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - -# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */ - -#define DP_DOWNSPREAD_CTRL 0x107 -# define DP_SPREAD_AMP_0_5 (1 << 4) -# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ - -#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 -# define DP_SET_ANSI_8B10B (1 << 0) -# define DP_SET_ANSI_128B132B (1 << 1) - -#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ -/* bitmask as for DP_I2C_SPEED_CAP */ - -#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ -# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0) -# define DP_FRAMING_CHANGE_ENABLE (1 << 1) -# define DP_PANEL_SELF_TEST_ENABLE (1 << 7) - -#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */ -#define DP_LINK_QUAL_LANE1_SET 0x10c -#define DP_LINK_QUAL_LANE2_SET 0x10d -#define DP_LINK_QUAL_LANE3_SET 0x10e -# define DP_LINK_QUAL_PATTERN_DISABLE 0 -# define DP_LINK_QUAL_PATTERN_D10_2 1 -# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2 -# define DP_LINK_QUAL_PATTERN_PRBS7 3 -# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4 -# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5 -# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6 -# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7 -/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */ -# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08 -# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10 -# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18 -# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20 -# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28 -# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30 -# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38 -# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40 -# define DP_LINK_QUAL_PATTERN_SQUARE 0x48 - -#define DP_TRAINING_LANE0_1_SET2 0x10f -#define DP_TRAINING_LANE2_3_SET2 0x110 -# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0) -# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2) -# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4) -# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6) - -#define DP_MSTM_CTRL 0x111 /* 1.2 */ -# define DP_MST_EN (1 << 0) -# define DP_UP_REQ_EN (1 << 1) -# define DP_UPSTREAM_IS_SRC (1 << 2) - -#define DP_AUDIO_DELAY0 0x112 /* 1.2 */ -#define DP_AUDIO_DELAY1 0x113 -#define DP_AUDIO_DELAY2 0x114 - -#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */ -# define DP_LINK_RATE_SET_SHIFT 0 -# define DP_LINK_RATE_SET_MASK (7 << 0) - -#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ -# define DP_ALPM_ENABLE (1 << 0) -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) - -#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ -# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) -# define DP_IRQ_HPD_ENABLE (1 << 1) - -#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */ -# define DP_PWR_NOT_NEEDED (1 << 0) - -#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */ -# define DP_FEC_READY (1 << 0) -# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1) -# define DP_FEC_ERR_COUNT_DIS (0 << 1) -# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1) -# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1) -# define DP_FEC_BIT_ERROR_COUNT (3 << 1) -# define DP_FEC_LANE_SELECT_MASK (3 << 4) -# define DP_FEC_LANE_0_SELECT (0 << 4) -# define DP_FEC_LANE_1_SELECT (1 << 4) -# define DP_FEC_LANE_2_SELECT (2 << 4) -# define DP_FEC_LANE_3_SELECT (3 << 4) - -#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */ -# define DP_AUX_FRAME_SYNC_VALID (1 << 0) - -#define DP_DSC_ENABLE 0x160 /* DP 1.4 */ -# define DP_DECOMPRESSION_EN (1 << 0) -#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ - -#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ -# define DP_PSR_ENABLE BIT(0) -# define DP_PSR_MAIN_LINK_ACTIVE BIT(1) -# define DP_PSR_CRC_VERIFICATION BIT(2) -# define DP_PSR_FRAME_CAPTURE BIT(3) -# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */ -# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */ -# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */ - -#define DP_ADAPTER_CTRL 0x1a0 -# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) - -#define DP_BRANCH_DEVICE_CTRL 0x1a1 -# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) - -#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 -#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 -#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 - -/* Link/Sink Device Status */ -#define DP_SINK_COUNT 0x200 -/* prior to 1.2 bit 7 was reserved mbz */ -# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) -# define DP_SINK_CP_READY (1 << 6) - -#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 -# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) -# define DP_AUTOMATED_TEST_REQUEST (1 << 1) -# define DP_CP_IRQ (1 << 2) -# define DP_MCCS_IRQ (1 << 3) -# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ -# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ -# define DP_SINK_SPECIFIC_IRQ (1 << 6) - -#define DP_LANE0_1_STATUS 0x202 -#define DP_LANE2_3_STATUS 0x203 -# define DP_LANE_CR_DONE (1 << 0) -# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) -# define DP_LANE_SYMBOL_LOCKED (1 << 2) - -#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ - DP_LANE_CHANNEL_EQ_DONE | \ - DP_LANE_SYMBOL_LOCKED) - -#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 - -#define DP_INTERLANE_ALIGN_DONE (1 << 0) -#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) -#define DP_LINK_STATUS_UPDATED (1 << 7) - -#define DP_SINK_STATUS 0x205 -# define DP_RECEIVE_PORT_0_STATUS (1 << 0) -# define DP_RECEIVE_PORT_1_STATUS (1 << 1) -# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ -# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ - -#define DP_ADJUST_REQUEST_LANE0_1 0x206 -#define DP_ADJUST_REQUEST_LANE2_3 0x207 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 -# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 -# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c -# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 -# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 -# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 - -/* DP 2.0 128b/132b Link Layer */ -# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0) -# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0 -# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4) -# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4 - -#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c -# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03 -# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0 -# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c -# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2 -# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30 -# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4 -# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0 -# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6 - -#define DP_TEST_REQUEST 0x218 -# define DP_TEST_LINK_TRAINING (1 << 0) -# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) -# define DP_TEST_LINK_EDID_READ (1 << 2) -# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ -# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ -# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */ -# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */ - -#define DP_TEST_LINK_RATE 0x219 -# define DP_LINK_RATE_162 (0x6) -# define DP_LINK_RATE_27 (0xa) - -#define DP_TEST_LANE_COUNT 0x220 - -#define DP_TEST_PATTERN 0x221 -# define DP_NO_TEST_PATTERN 0x0 -# define DP_COLOR_RAMP 0x1 -# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2 -# define DP_COLOR_SQUARE 0x3 - -#define DP_TEST_H_TOTAL_HI 0x222 -#define DP_TEST_H_TOTAL_LO 0x223 - -#define DP_TEST_V_TOTAL_HI 0x224 -#define DP_TEST_V_TOTAL_LO 0x225 - -#define DP_TEST_H_START_HI 0x226 -#define DP_TEST_H_START_LO 0x227 - -#define DP_TEST_V_START_HI 0x228 -#define DP_TEST_V_START_LO 0x229 - -#define DP_TEST_HSYNC_HI 0x22A -# define DP_TEST_HSYNC_POLARITY (1 << 7) -# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0) -#define DP_TEST_HSYNC_WIDTH_LO 0x22B - -#define DP_TEST_VSYNC_HI 0x22C -# define DP_TEST_VSYNC_POLARITY (1 << 7) -# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0) -#define DP_TEST_VSYNC_WIDTH_LO 0x22D - -#define DP_TEST_H_WIDTH_HI 0x22E -#define DP_TEST_H_WIDTH_LO 0x22F - -#define DP_TEST_V_HEIGHT_HI 0x230 -#define DP_TEST_V_HEIGHT_LO 0x231 - -#define DP_TEST_MISC0 0x232 -# define DP_TEST_SYNC_CLOCK (1 << 0) -# define DP_TEST_COLOR_FORMAT_MASK (3 << 1) -# define DP_TEST_COLOR_FORMAT_SHIFT 1 -# define DP_COLOR_FORMAT_RGB (0 << 1) -# define DP_COLOR_FORMAT_YCbCr422 (1 << 1) -# define DP_COLOR_FORMAT_YCbCr444 (2 << 1) -# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3) -# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3) -# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4) -# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4) -# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4) -# define DP_TEST_BIT_DEPTH_MASK (7 << 5) -# define DP_TEST_BIT_DEPTH_SHIFT 5 -# define DP_TEST_BIT_DEPTH_6 (0 << 5) -# define DP_TEST_BIT_DEPTH_8 (1 << 5) -# define DP_TEST_BIT_DEPTH_10 (2 << 5) -# define DP_TEST_BIT_DEPTH_12 (3 << 5) -# define DP_TEST_BIT_DEPTH_16 (4 << 5) - -#define DP_TEST_MISC1 0x233 -# define DP_TEST_REFRESH_DENOMINATOR (1 << 0) -# define DP_TEST_INTERLACED (1 << 1) - -#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234 - -#define DP_TEST_MISC0 0x232 - -#define DP_TEST_CRC_R_CR 0x240 -#define DP_TEST_CRC_G_Y 0x242 -#define DP_TEST_CRC_B_CB 0x244 - -#define DP_TEST_SINK_MISC 0x246 -# define DP_TEST_CRC_SUPPORTED (1 << 5) -# define DP_TEST_COUNT_MASK 0xf - -#define DP_PHY_TEST_PATTERN 0x248 -# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7 -# define DP_PHY_TEST_PATTERN_NONE 0x0 -# define DP_PHY_TEST_PATTERN_D10_2 0x1 -# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2 -# define DP_PHY_TEST_PATTERN_PRBS7 0x3 -# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 -# define DP_PHY_TEST_PATTERN_CP2520 0x5 - -#define DP_PHY_SQUARE_PATTERN 0x249 - -#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A -#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 -#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 -#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 -#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 -#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 -#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 -#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 -#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 -#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 -#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 - -#define DP_TEST_RESPONSE 0x260 -# define DP_TEST_ACK (1 << 0) -# define DP_TEST_NAK (1 << 1) -# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) - -#define DP_TEST_EDID_CHECKSUM 0x261 - -#define DP_TEST_SINK 0x270 -# define DP_TEST_SINK_START (1 << 0) -#define DP_TEST_AUDIO_MODE 0x271 -#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 -#define DP_TEST_AUDIO_PERIOD_CH1 0x273 -#define DP_TEST_AUDIO_PERIOD_CH2 0x274 -#define DP_TEST_AUDIO_PERIOD_CH3 0x275 -#define DP_TEST_AUDIO_PERIOD_CH4 0x276 -#define DP_TEST_AUDIO_PERIOD_CH5 0x277 -#define DP_TEST_AUDIO_PERIOD_CH6 0x278 -#define DP_TEST_AUDIO_PERIOD_CH7 0x279 -#define DP_TEST_AUDIO_PERIOD_CH8 0x27A - -#define DP_FEC_STATUS 0x280 /* 1.4 */ -# define DP_FEC_DECODE_EN_DETECTED (1 << 0) -# define DP_FEC_DECODE_DIS_DETECTED (1 << 1) - -#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */ - -#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */ -# define DP_FEC_ERROR_COUNT_MASK 0x7F -# define DP_FEC_ERR_COUNT_VALID (1 << 7) - -#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ -# define DP_PAYLOAD_TABLE_UPDATED (1 << 0) -# define DP_PAYLOAD_ACT_HANDLED (1 << 1) - -#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ -/* up to ID_SLOT_63 at 0x2ff */ - -/* Source Device-specific */ -#define DP_SOURCE_OUI 0x300 - -/* Sink Device-specific */ -#define DP_SINK_OUI 0x400 - -/* Branch Device-specific */ -#define DP_BRANCH_OUI 0x500 -#define DP_BRANCH_ID 0x503 -#define DP_BRANCH_REVISION_START 0x509 -#define DP_BRANCH_HW_REV 0x509 -#define DP_BRANCH_SW_REV 0x50A - -/* Link/Sink Device Power Control */ -#define DP_SET_POWER 0x600 -# define DP_SET_POWER_D0 0x1 -# define DP_SET_POWER_D3 0x2 -# define DP_SET_POWER_MASK 0x3 -# define DP_SET_POWER_D3_AUX_ON 0x5 - -/* eDP-specific */ -#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */ -# define DP_EDP_11 0x00 -# define DP_EDP_12 0x01 -# define DP_EDP_13 0x02 -# define DP_EDP_14 0x03 -# define DP_EDP_14a 0x04 /* eDP 1.4a */ -# define DP_EDP_14b 0x05 /* eDP 1.4b */ - -#define DP_EDP_GENERAL_CAP_1 0x701 -# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0) -# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1) -# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2) -# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3) -# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4) -# define DP_EDP_FRC_ENABLE_CAP (1 << 5) -# define DP_EDP_COLOR_ENGINE_CAP (1 << 6) -# define DP_EDP_SET_POWER_CAP (1 << 7) - -#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702 -# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0) -# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1) -# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2) -# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3) -# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4) -# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) -# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) -# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) - -#define DP_EDP_GENERAL_CAP_2 0x703 -# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) - -#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */ -# define DP_EDP_X_REGION_CAP_MASK (0xf << 0) -# define DP_EDP_X_REGION_CAP_SHIFT 0 -# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4) -# define DP_EDP_Y_REGION_CAP_SHIFT 4 - -#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720 -# define DP_EDP_BACKLIGHT_ENABLE (1 << 0) -# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1) -# define DP_EDP_FRC_ENABLE (1 << 2) -# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3) -# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7) - -#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721 -# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0) -# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0) -# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0) -# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0) -# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0) -# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2) -# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3) -# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4) -# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5) -# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */ - -#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722 -#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723 - -#define DP_EDP_PWMGEN_BIT_COUNT 0x724 -#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725 -#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726 -# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0) - -#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727 - -#define DP_EDP_BACKLIGHT_FREQ_SET 0x728 -# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000 - -#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a -#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b -#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c - -#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d -#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e -#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f - -#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732 -#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733 - -#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */ -#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */ - -#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */ -# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0) -# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0 -# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3) - -/* Sideband MSG Buffers */ -#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ -#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ -#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ -#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ - -/* DPRX Event Status Indicator */ -#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */ -#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */ - -#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ -# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0) -# define DP_LOCK_ACQUISITION_REQUEST (1 << 1) -# define DP_CEC_IRQ (1 << 2) - -#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ -# define RX_CAP_CHANGED (1 << 0) -# define LINK_STATUS_CHANGED (1 << 1) -# define STREAM_STATUS_CHANGED (1 << 2) -# define HDMI_LINK_STATUS_CHANGED (1 << 3) -# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4) - -#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ -# define DP_PSR_LINK_CRC_ERROR (1 << 0) -# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) -# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */ - -#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ -# define DP_PSR_CAPS_CHANGE (1 << 0) - -#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ -# define DP_PSR_SINK_INACTIVE 0 -# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 -# define DP_PSR_SINK_ACTIVE_RFB 2 -# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 -# define DP_PSR_SINK_ACTIVE_RESYNC 4 -# define DP_PSR_SINK_INTERNAL_ERROR 7 -# define DP_PSR_SINK_STATE_MASK 0x07 - -#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */ -# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0) -# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0 -# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4) -# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4 - -#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */ -# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */ -# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */ -# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */ -# define DP_SU_VALID (1 << 3) /* eDP 1.4 */ -# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */ -# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */ -# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */ - -#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */ -# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0) - -#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ -#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ -#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ -#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ - -/* Extended Receiver Capability: See DP_DPCD_REV for definitions */ -#define DP_DP13_DPCD_REV 0x2200 - -#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ -# define DP_GTC_CAP (1 << 0) /* DP 1.3 */ -# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */ -# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */ -# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */ -# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */ -# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */ -# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */ -# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */ - -#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ -# define DP_UHBR10 (1 << 0) -# define DP_UHBR20 (1 << 1) -# define DP_UHBR13_5 (1 << 2) - -#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00 -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01 -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02 -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03 -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04 -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05 -# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06 - -#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 -#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 - -/* DSC Extended Capability Branch Total DSC Resources */ -#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ -# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) -# define DP_DSC_DECODER_COUNT_SHIFT 5 -#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ -# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) -# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 - -/* Protocol Converter Extension */ -/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ -#define DP_CEC_TUNNELING_CAPABILITY 0x3000 -# define DP_CEC_TUNNELING_CAPABLE (1 << 0) -# define DP_CEC_SNOOPING_CAPABLE (1 << 1) -# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2) - -#define DP_CEC_TUNNELING_CONTROL 0x3001 -# define DP_CEC_TUNNELING_ENABLE (1 << 0) -# define DP_CEC_SNOOPING_ENABLE (1 << 1) - -#define DP_CEC_RX_MESSAGE_INFO 0x3002 -# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0) -# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0 -# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4) -# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5) -# define DP_CEC_RX_MESSAGE_ACKED (1 << 6) -# define DP_CEC_RX_MESSAGE_ENDED (1 << 7) - -#define DP_CEC_TX_MESSAGE_INFO 0x3003 -# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0) -# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0 -# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4) -# define DP_CEC_TX_RETRY_COUNT_SHIFT 4 -# define DP_CEC_TX_MESSAGE_SEND (1 << 7) - -#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004 -# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0) -# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1) -# define DP_CEC_TX_MESSAGE_SENT (1 << 4) -# define DP_CEC_TX_LINE_ERROR (1 << 5) -# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6) -# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7) - -#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */ -# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0) -# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1) -# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2) -# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3) -# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4) -# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5) -# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6) -# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7) -#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */ -# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0) -# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1) -# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2) -# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3) -# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4) -# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5) -# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6) -# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7) - -#define DP_CEC_RX_MESSAGE_BUFFER 0x3010 -#define DP_CEC_TX_MESSAGE_BUFFER 0x3020 -#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10 - -/* PCON CONFIGURE-1 FRL FOR HDMI SINK */ -#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A -# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) -# define DP_PCON_ENABLE_MAX_BW_0GBPS 0 -# define DP_PCON_ENABLE_MAX_BW_9GBPS 1 -# define DP_PCON_ENABLE_MAX_BW_18GBPS 2 -# define DP_PCON_ENABLE_MAX_BW_24GBPS 3 -# define DP_PCON_ENABLE_MAX_BW_32GBPS 4 -# define DP_PCON_ENABLE_MAX_BW_40GBPS 5 -# define DP_PCON_ENABLE_MAX_BW_48GBPS 6 -# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) -# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) -# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) -# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) -# define DP_PCON_ENABLE_HPD_READY (1 << 6) -# define DP_PCON_ENABLE_HDMI_LINK (1 << 7) - -/* PCON CONFIGURE-2 FRL FOR HDMI SINK */ -#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B -# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) -# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) -# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) -# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) -# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) -# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) -# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) -# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) -# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) - -/* PCON HDMI LINK STATUS */ -#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B -# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) -# define DP_PCON_FRL_READY (1 << 1) - -/* PCON HDMI POST FRL STATUS */ -#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 -# define DP_PCON_HDMI_LINK_MODE (1 << 0) -# define DP_PCON_HDMI_MODE_TMDS 0 -# define DP_PCON_HDMI_MODE_FRL 1 -# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) -# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) -# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) -# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) -# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) -# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) -# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) - -#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */ -# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */ -#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */ -# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */ -# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */ -# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */ -# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */ -#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */ -# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */ -# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1) -# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2) -# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0 -# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1 -# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2 -# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4) -# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4) -# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5) -# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6) - -/* PCON Downstream HDMI ERROR Status per Lane */ -#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037 -#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038 -#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039 -#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A -# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0) -# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0) -# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1) -# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2) - -/* PCON HDMI CONFIG PPS Override Buffer - * Valid Offsets to be added to Base : 0-127 - */ -#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100 - -/* PCON HDMI CONFIG PPS Override Parameter: Slice height - * Offset-0 8LSBs of the Slice height. - * Offset-1 8MSBs of the Slice height. - */ -#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180 - -/* PCON HDMI CONFIG PPS Override Parameter: Slice width - * Offset-0 8LSBs of the Slice width. - * Offset-1 8MSBs of the Slice width. - */ -#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182 - -/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel - * Offset-0 8LSBs of the bits_per_pixel. - * Offset-1 2MSBs of the bits_per_pixel. - */ -#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184 - -/* HDCP 1.3 and HDCP 2.2 */ -#define DP_AUX_HDCP_BKSV 0x68000 -#define DP_AUX_HDCP_RI_PRIME 0x68005 -#define DP_AUX_HDCP_AKSV 0x68007 -#define DP_AUX_HDCP_AN 0x6800C -#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4) -#define DP_AUX_HDCP_BCAPS 0x68028 -# define DP_BCAPS_REPEATER_PRESENT BIT(1) -# define DP_BCAPS_HDCP_CAPABLE BIT(0) -#define DP_AUX_HDCP_BSTATUS 0x68029 -# define DP_BSTATUS_REAUTH_REQ BIT(3) -# define DP_BSTATUS_LINK_FAILURE BIT(2) -# define DP_BSTATUS_R0_PRIME_READY BIT(1) -# define DP_BSTATUS_READY BIT(0) -#define DP_AUX_HDCP_BINFO 0x6802A -#define DP_AUX_HDCP_KSV_FIFO 0x6802C -#define DP_AUX_HDCP_AINFO 0x6803B - -/* DP HDCP2.2 parameter offsets in DPCD address space */ -#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 -#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 -#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B -#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 -#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D -#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 -#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 -#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 -#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 -#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 -#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 -#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 -#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 -#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 -#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 -#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 -#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 -#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 -#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 -#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 -#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 -#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 -#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 -#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 -#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 -#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 - -/* LTTPR: Link Training (LT)-tunable PHY Repeaters */ -#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ -#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ -#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ -#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ -#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ -#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */ -#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ -#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */ -# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0) -/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ -#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ - -enum drm_dp_phy { - DP_PHY_DPRX, - - DP_PHY_LTTPR1, - DP_PHY_LTTPR2, - DP_PHY_LTTPR3, - DP_PHY_LTTPR4, - DP_PHY_LTTPR5, - DP_PHY_LTTPR6, - DP_PHY_LTTPR7, - DP_PHY_LTTPR8, - - DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, -}; - -#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) - -#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ -#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ -#define DP_LTTPR_BASE(dp_phy) \ - (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ - ((dp_phy) - DP_PHY_LTTPR1)) - -#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ - (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) - -#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ -#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ - DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) - -#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ -#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \ - DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1) - -#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */ -#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */ -#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */ -#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ -#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ - DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) - -#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */ -# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0) -# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1) - -#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */ -#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \ - DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) -/* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */ - -#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ -#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \ - DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1) - -#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */ - -#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */ -#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ -#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */ -#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */ -#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */ -#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */ -#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */ - -#define __DP_FEC1_BASE 0xf0290 /* 1.4 */ -#define __DP_FEC2_BASE 0xf0298 /* 1.4 */ -#define DP_FEC_BASE(dp_phy) \ - (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ - ((dp_phy) - DP_PHY_LTTPR1))) - -#define DP_FEC_REG(dp_phy, fec1_reg) \ - (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) - -#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ -#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ - DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) - -#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */ -#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */ - -#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ - -#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ - -/* Repeater modes */ -#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ -#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ - -/* DP HDCP message start offsets in DPCD address space */ -#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET -#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET -#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET -#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET -#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET -#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ - DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET -#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET -#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET -#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET -#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET -#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET -#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET -#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET - -#define HDCP_2_2_DP_RXSTATUS_LEN 1 -#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) -#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) -#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) -#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) -#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) - -/* DP 1.2 Sideband message defines */ -/* peer device type - DP 1.2a Table 2-92 */ -#define DP_PEER_DEVICE_NONE 0x0 -#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 -#define DP_PEER_DEVICE_MST_BRANCHING 0x2 -#define DP_PEER_DEVICE_SST_SINK 0x3 -#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 - -/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ -#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */ -#define DP_LINK_ADDRESS 0x01 -#define DP_CONNECTION_STATUS_NOTIFY 0x02 -#define DP_ENUM_PATH_RESOURCES 0x10 -#define DP_ALLOCATE_PAYLOAD 0x11 -#define DP_QUERY_PAYLOAD 0x12 -#define DP_RESOURCE_STATUS_NOTIFY 0x13 -#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 -#define DP_REMOTE_DPCD_READ 0x20 -#define DP_REMOTE_DPCD_WRITE 0x21 -#define DP_REMOTE_I2C_READ 0x22 -#define DP_REMOTE_I2C_WRITE 0x23 -#define DP_POWER_UP_PHY 0x24 -#define DP_POWER_DOWN_PHY 0x25 -#define DP_SINK_EVENT_NOTIFY 0x30 -#define DP_QUERY_STREAM_ENC_STATUS 0x38 -#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0 -#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1 -#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2 - -/* DP 1.2 MST sideband reply types */ -#define DP_SIDEBAND_REPLY_ACK 0x00 -#define DP_SIDEBAND_REPLY_NAK 0x01 - -/* DP 1.2 MST sideband nak reasons - table 2.84 */ -#define DP_NAK_WRITE_FAILURE 0x01 -#define DP_NAK_INVALID_READ 0x02 -#define DP_NAK_CRC_FAILURE 0x03 -#define DP_NAK_BAD_PARAM 0x04 -#define DP_NAK_DEFER 0x05 -#define DP_NAK_LINK_FAILURE 0x06 -#define DP_NAK_NO_RESOURCES 0x07 -#define DP_NAK_DPCD_FAIL 0x08 -#define DP_NAK_I2C_NAK 0x09 -#define DP_NAK_ALLOCATE_FAIL 0x0a - -#define MODE_I2C_START 1 -#define MODE_I2C_WRITE 2 -#define MODE_I2C_READ 4 -#define MODE_I2C_STOP 8 - -/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */ -#define DP_MST_PHYSICAL_PORT_0 0 -#define DP_MST_LOGICAL_PORT_0 8 - -#define DP_LINK_CONSTANT_N_VALUE 0x8000 -#define DP_LINK_STATUS_SIZE 6 -bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane_count); -bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane_count); -u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane); -u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane); -u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], - int lane); -u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE], - unsigned int lane); - -#define DP_BRANCH_OUI_HEADER_SIZE 0xc -#define DP_RECEIVER_CAP_SIZE 0xf -#define DP_DSC_RECEIVER_CAP_SIZE 0xf -#define EDP_PSR_RECEIVER_CAP_SIZE 2 -#define EDP_DISPLAY_CTL_CAP_SIZE 3 -#define DP_LTTPR_COMMON_CAP_SIZE 8 -#define DP_LTTPR_PHY_CAP_SIZE 3 - -int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], - enum drm_dp_phy dp_phy, bool uhbr); -int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], - enum drm_dp_phy dp_phy, bool uhbr); - -void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, - const u8 dpcd[DP_RECEIVER_CAP_SIZE]); -void drm_dp_lttpr_link_train_clock_recovery_delay(void); -void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, - const u8 dpcd[DP_RECEIVER_CAP_SIZE]); -void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, - const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); - -u8 drm_dp_link_rate_to_bw_code(int link_rate); -int drm_dp_bw_code_to_link_rate(u8 link_bw); - -#define DP_SDP_AUDIO_TIMESTAMP 0x01 -#define DP_SDP_AUDIO_STREAM 0x02 -#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */ -#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */ -#define DP_SDP_ISRC 0x06 /* DP 1.2 */ -#define DP_SDP_VSC 0x07 /* DP 1.2 */ -#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */ -#define DP_SDP_PPS 0x10 /* DP 1.4 */ -#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */ -#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */ -/* 0x80+ CEA-861 infoframe types */ - -/** - * struct dp_sdp_header - DP secondary data packet header - * @HB0: Secondary Data Packet ID - * @HB1: Secondary Data Packet Type - * @HB2: Secondary Data Packet Specific header, Byte 0 - * @HB3: Secondary Data packet Specific header, Byte 1 - */ -struct dp_sdp_header { - u8 HB0; - u8 HB1; - u8 HB2; - u8 HB3; -} __packed; - -#define EDP_SDP_HEADER_REVISION_MASK 0x1F -#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F -#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F - -/** - * struct dp_sdp - DP secondary data packet - * @sdp_header: DP secondary data packet header - * @db: DP secondaray data packet data blocks - * VSC SDP Payload for PSR - * db[0]: Stereo Interface - * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid - * db[2]: CRC value bits 7:0 of the R or Cr component - * db[3]: CRC value bits 15:8 of the R or Cr component - * db[4]: CRC value bits 7:0 of the G or Y component - * db[5]: CRC value bits 15:8 of the G or Y component - * db[6]: CRC value bits 7:0 of the B or Cb component - * db[7]: CRC value bits 15:8 of the B or Cb component - * db[8] - db[31]: Reserved - * VSC SDP Payload for Pixel Encoding/Colorimetry Format - * db[0] - db[15]: Reserved - * db[16]: Pixel Encoding and Colorimetry Formats - * db[17]: Dynamic Range and Component Bit Depth - * db[18]: Content Type - * db[19] - db[31]: Reserved - */ -struct dp_sdp { - struct dp_sdp_header sdp_header; - u8 db[32]; -} __packed; - -#define EDP_VSC_PSR_STATE_ACTIVE (1<<0) -#define EDP_VSC_PSR_UPDATE_RFB (1<<1) -#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) - -/** - * enum dp_pixelformat - drm DP Pixel encoding formats - * - * This enum is used to indicate DP VSC SDP Pixel encoding formats. - * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through - * DB18] - * - * @DP_PIXELFORMAT_RGB: RGB pixel encoding format - * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format - * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format - * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format - * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format - * @DP_PIXELFORMAT_RAW: RAW pixel encoding format - * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format - */ -enum dp_pixelformat { - DP_PIXELFORMAT_RGB = 0, - DP_PIXELFORMAT_YUV444 = 0x1, - DP_PIXELFORMAT_YUV422 = 0x2, - DP_PIXELFORMAT_YUV420 = 0x3, - DP_PIXELFORMAT_Y_ONLY = 0x4, - DP_PIXELFORMAT_RAW = 0x5, - DP_PIXELFORMAT_RESERVED = 0x6, -}; - -/** - * enum dp_colorimetry - drm DP Colorimetry formats - * - * This enum is used to indicate DP VSC SDP Colorimetry formats. - * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through - * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition. - * - * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or - * ITU-R BT.601 colorimetry format - * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format - * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format - * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point - * (scRGB (IEC 61966-2-2)) colorimetry format - * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format - * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format - * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format - * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format - * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format - * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format - * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format - * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format - * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format - * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format - */ -enum dp_colorimetry { - DP_COLORIMETRY_DEFAULT = 0, - DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1, - DP_COLORIMETRY_BT709_YCC = 0x1, - DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2, - DP_COLORIMETRY_XVYCC_601 = 0x2, - DP_COLORIMETRY_OPRGB = 0x3, - DP_COLORIMETRY_XVYCC_709 = 0x3, - DP_COLORIMETRY_DCI_P3_RGB = 0x4, - DP_COLORIMETRY_SYCC_601 = 0x4, - DP_COLORIMETRY_RGB_CUSTOM = 0x5, - DP_COLORIMETRY_OPYCC_601 = 0x5, - DP_COLORIMETRY_BT2020_RGB = 0x6, - DP_COLORIMETRY_BT2020_CYCC = 0x6, - DP_COLORIMETRY_BT2020_YCC = 0x7, -}; - -/** - * enum dp_dynamic_range - drm DP Dynamic Range - * - * This enum is used to indicate DP VSC SDP Dynamic Range. - * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through - * DB18] - * - * @DP_DYNAMIC_RANGE_VESA: VESA range - * @DP_DYNAMIC_RANGE_CTA: CTA range - */ -enum dp_dynamic_range { - DP_DYNAMIC_RANGE_VESA = 0, - DP_DYNAMIC_RANGE_CTA = 1, -}; - -/** - * enum dp_content_type - drm DP Content Type - * - * This enum is used to indicate DP VSC SDP Content Types. - * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through - * DB18] - * CTA-861-G defines content types and expected processing by a sink device - * - * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type - * @DP_CONTENT_TYPE_GRAPHICS: Graphics type - * @DP_CONTENT_TYPE_PHOTO: Photo type - * @DP_CONTENT_TYPE_VIDEO: Video type - * @DP_CONTENT_TYPE_GAME: Game type - */ -enum dp_content_type { - DP_CONTENT_TYPE_NOT_DEFINED = 0x00, - DP_CONTENT_TYPE_GRAPHICS = 0x01, - DP_CONTENT_TYPE_PHOTO = 0x02, - DP_CONTENT_TYPE_VIDEO = 0x03, - DP_CONTENT_TYPE_GAME = 0x04, -}; - -/** - * struct drm_dp_vsc_sdp - drm DP VSC SDP - * - * This structure represents a DP VSC SDP of drm - * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and - * [Table 2-117: VSC SDP Payload for DB16 through DB18] - * - * @sdp_type: secondary-data packet type - * @revision: revision number - * @length: number of valid data bytes - * @pixelformat: pixel encoding format - * @colorimetry: colorimetry format - * @bpc: bit per color - * @dynamic_range: dynamic range information - * @content_type: CTA-861-G defines content types and expected processing by a sink device - */ -struct drm_dp_vsc_sdp { - unsigned char sdp_type; - unsigned char revision; - unsigned char length; - enum dp_pixelformat pixelformat; - enum dp_colorimetry colorimetry; - int bpc; - enum dp_dynamic_range dynamic_range; - enum dp_content_type content_type; -}; - -void drm_dp_vsc_sdp_log(const char *level, struct device *dev, - const struct drm_dp_vsc_sdp *vsc); - -int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); - -static inline int -drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); -} - -static inline u8 -drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; -} - -static inline bool -drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_DPCD_REV] >= 0x11 && - (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); -} - -static inline bool -drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_DPCD_REV] >= 0x11 && - (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); -} - -static inline bool -drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_DPCD_REV] >= 0x12 && - dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; -} - -static inline bool -drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_DPCD_REV] >= 0x14 && - dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; -} - -static inline u8 -drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : - DP_TRAINING_PATTERN_MASK; -} - -static inline bool -drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; -} - -/* DP/eDP DSC support */ -u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], - bool is_edp); -u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); -int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], - u8 dsc_bpc[3]); - -static inline bool -drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -{ - return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & - DP_DSC_DECOMPRESSION_IS_SUPPORTED; -} - -static inline u16 -drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -{ - return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | - (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & - DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK << - DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT); -} - -static inline u32 -drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -{ - /* Max Slicewidth = Number of Pixels * 320 */ - return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * - DP_DSC_SLICE_WIDTH_MULTIPLIER; -} - -/* Forward Error Correction Support on DP 1.4 */ -static inline bool -drm_dp_sink_supports_fec(const u8 fec_capable) -{ - return fec_capable & DP_FEC_CAPABLE; -} - -static inline bool -drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; -} - -static inline bool -drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_EDP_CONFIGURATION_CAP] & - DP_ALTERNATE_SCRAMBLER_RESET_CAP; -} - -/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ -static inline bool -drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) -{ - return dpcd[DP_DOWN_STREAM_PORT_COUNT] & - DP_MSA_TIMING_PAR_IGNORED; -} - -/** - * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support - * @edp_dpcd: The DPCD to check - * - * Note that currently this function will return %false for panels which support various DPCD - * backlight features but which require the brightness be set through PWM, and don't support setting - * the brightness level via the DPCD. - * - * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false - * otherwise - */ -static inline bool -drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) -{ - return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); -} - -/* - * DisplayPort AUX channel - */ - -/** - * struct drm_dp_aux_msg - DisplayPort AUX channel transaction - * @address: address of the (first) register to access - * @request: contains the type of transaction (see DP_AUX_* macros) - * @reply: upon completion, contains the reply type of the transaction - * @buffer: pointer to a transmission or reception buffer - * @size: size of @buffer - */ -struct drm_dp_aux_msg { - unsigned int address; - u8 request; - u8 reply; - void *buffer; - size_t size; -}; - -struct cec_adapter; -struct edid; -struct drm_connector; - -/** - * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX - * @lock: mutex protecting this struct - * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. - * @connector: the connector this CEC adapter is associated with - * @unregister_work: unregister the CEC adapter - */ -struct drm_dp_aux_cec { - struct mutex lock; - struct cec_adapter *adap; - struct drm_connector *connector; - struct delayed_work unregister_work; -}; - -/** - * struct drm_dp_aux - DisplayPort AUX channel - * - * An AUX channel can also be used to transport I2C messages to a sink. A - * typical application of that is to access an EDID that's present in the sink - * device. The @transfer() function can also be used to execute such - * transactions. The drm_dp_aux_register() function registers an I2C adapter - * that can be passed to drm_probe_ddc(). Upon removal, drivers should call - * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long - * transfers by default; if a partial response is received, the adapter will - * drop down to the size given by the partial response for this transaction - * only. - */ -struct drm_dp_aux { - /** - * @name: user-visible name of this AUX channel and the - * I2C-over-AUX adapter. - * - * It's also used to specify the name of the I2C adapter. If set - * to %NULL, dev_name() of @dev will be used. - */ - const char *name; - - /** - * @ddc: I2C adapter that can be used for I2C-over-AUX - * communication - */ - struct i2c_adapter ddc; - - /** - * @dev: pointer to struct device that is the parent for this - * AUX channel. - */ - struct device *dev; - - /** - * @drm_dev: pointer to the &drm_device that owns this AUX channel. - * Beware, this may be %NULL before drm_dp_aux_register() has been - * called. - * - * It should be set to the &drm_device that will be using this AUX - * channel as early as possible. For many graphics drivers this should - * happen before drm_dp_aux_init(), however it's perfectly fine to set - * this field later so long as it's assigned before calling - * drm_dp_aux_register(). - */ - struct drm_device *drm_dev; - - /** - * @crtc: backpointer to the crtc that is currently using this - * AUX channel - */ - struct drm_crtc *crtc; - - /** - * @hw_mutex: internal mutex used for locking transfers. - * - * Note that if the underlying hardware is shared among multiple - * channels, the driver needs to do additional locking to - * prevent concurrent access. - */ - struct mutex hw_mutex; - - /** - * @crc_work: worker that captures CRCs for each frame - */ - struct work_struct crc_work; - - /** - * @crc_count: counter of captured frame CRCs - */ - u8 crc_count; - - /** - * @transfer: transfers a message representing a single AUX - * transaction. - * - * This is a hardware-specific implementation of how - * transactions are executed that the drivers must provide. - * - * A pointer to a &drm_dp_aux_msg structure describing the - * transaction is passed into this function. Upon success, the - * implementation should return the number of payload bytes that - * were transferred, or a negative error-code on failure. - * - * Helpers will propagate these errors, with the exception of - * the %-EBUSY error, which causes a transaction to be retried. - * On a short, helpers will return %-EPROTO to make it simpler - * to check for failure. - * - * The @transfer() function must only modify the reply field of - * the &drm_dp_aux_msg structure. The retry logic and i2c - * helpers assume this is the case. - * - * Also note that this callback can be called no matter the - * state @dev is in. Drivers that need that device to be powered - * to perform this operation will first need to make sure it's - * been properly enabled. - */ - ssize_t (*transfer)(struct drm_dp_aux *aux, - struct drm_dp_aux_msg *msg); - - /** - * @i2c_nack_count: Counts I2C NACKs, used for DP validation. - */ - unsigned i2c_nack_count; - /** - * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. - */ - unsigned i2c_defer_count; - /** - * @cec: struct containing fields used for CEC-Tunneling-over-AUX. - */ - struct drm_dp_aux_cec cec; - /** - * @is_remote: Is this AUX CH actually using sideband messaging. - */ - bool is_remote; -}; - -ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, - void *buffer, size_t size); -ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, - void *buffer, size_t size); - -/** - * drm_dp_dpcd_readb() - read a single byte from the DPCD - * @aux: DisplayPort AUX channel - * @offset: address of the register to read - * @valuep: location where the value of the register will be stored - * - * Returns the number of bytes transferred (1) on success, or a negative - * error code on failure. - */ -static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, - unsigned int offset, u8 *valuep) -{ - return drm_dp_dpcd_read(aux, offset, valuep, 1); -} - -/** - * drm_dp_dpcd_writeb() - write a single byte to the DPCD - * @aux: DisplayPort AUX channel - * @offset: address of the register to write - * @value: value to write to the register - * - * Returns the number of bytes transferred (1) on success, or a negative - * error code on failure. - */ -static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, - unsigned int offset, u8 value) -{ - return drm_dp_dpcd_write(aux, offset, &value, 1); -} - -int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, - u8 dpcd[DP_RECEIVER_CAP_SIZE]); - -int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, - u8 status[DP_LINK_STATUS_SIZE]); - -int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, - enum drm_dp_phy dp_phy, - u8 link_status[DP_LINK_STATUS_SIZE]); - -bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, - u8 real_edid_checksum); - -int drm_dp_read_downstream_info(struct drm_dp_aux *aux, - const u8 dpcd[DP_RECEIVER_CAP_SIZE], - u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); -bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], u8 type); -bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], - const struct edid *edid); -int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4]); -int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], - const struct edid *edid); -int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], - const struct edid *edid); -int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], - const struct edid *edid); -bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4]); -bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4]); -struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, - const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4]); -int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); -void drm_dp_downstream_debug(struct seq_file *m, - const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], - const struct edid *edid, - struct drm_dp_aux *aux); -enum drm_mode_subconnector -drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4]); -void drm_dp_set_subconnector_property(struct drm_connector *connector, - enum drm_connector_status status, - const u8 *dpcd, - const u8 port_cap[4]); - -struct drm_dp_desc; -bool drm_dp_read_sink_count_cap(struct drm_connector *connector, - const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const struct drm_dp_desc *desc); -int drm_dp_read_sink_count(struct drm_dp_aux *aux); - -int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, - u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); -int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, - enum drm_dp_phy dp_phy, - u8 caps[DP_LTTPR_PHY_CAP_SIZE]); -int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); -int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); -int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); -bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); -bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); - -void drm_dp_remote_aux_init(struct drm_dp_aux *aux); -void drm_dp_aux_init(struct drm_dp_aux *aux); -int drm_dp_aux_register(struct drm_dp_aux *aux); -void drm_dp_aux_unregister(struct drm_dp_aux *aux); - -int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); -int drm_dp_stop_crc(struct drm_dp_aux *aux); - -struct drm_dp_dpcd_ident { - u8 oui[3]; - u8 device_id[6]; - u8 hw_rev; - u8 sw_major_rev; - u8 sw_minor_rev; -} __packed; - -/** - * struct drm_dp_desc - DP branch/sink device descriptor - * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). - * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. - */ -struct drm_dp_desc { - struct drm_dp_dpcd_ident ident; - u32 quirks; -}; - -int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, - bool is_branch); - -/** - * enum drm_dp_quirk - Display Port sink/branch device specific quirks - * - * Display Port sink and branch devices in the wild have a variety of bugs, try - * to collect them here. The quirks are shared, but it's up to the drivers to - * implement workarounds for them. - */ -enum drm_dp_quirk { - /** - * @DP_DPCD_QUIRK_CONSTANT_N: - * - * The device requires main link attributes Mvid and Nvid to be limited - * to 16 bits. So will give a constant value (0x8000) for compatability. - */ - DP_DPCD_QUIRK_CONSTANT_N, - /** - * @DP_DPCD_QUIRK_NO_PSR: - * - * The device does not support PSR even if reports that it supports or - * driver still need to implement proper handling for such device. - */ - DP_DPCD_QUIRK_NO_PSR, - /** - * @DP_DPCD_QUIRK_NO_SINK_COUNT: - * - * The device does not set SINK_COUNT to a non-zero value. - * The driver should ignore SINK_COUNT during detection. Note that - * drm_dp_read_sink_count_cap() automatically checks for this quirk. - */ - DP_DPCD_QUIRK_NO_SINK_COUNT, - /** - * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: - * - * The device supports MST DSC despite not supporting Virtual DPCD. - * The DSC caps can be read from the physical aux instead. - */ - DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, - /** - * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: - * - * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite - * the DP_MAX_LINK_RATE register reporting a lower max multiplier. - */ - DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, -}; - -/** - * drm_dp_has_quirk() - does the DP device have a specific quirk - * @desc: Device descriptor filled by drm_dp_read_desc() - * @quirk: Quirk to query for - * - * Return true if DP device identified by @desc has @quirk. - */ -static inline bool -drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) -{ - return desc->quirks & BIT(quirk); -} - -/** - * struct drm_edp_backlight_info - Probed eDP backlight info struct - * @pwmgen_bit_count: The pwmgen bit count - * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any - * @max: The maximum backlight level that may be set - * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? - * @aux_enable: Does the panel support the AUX enable cap? - * @aux_set: Does the panel support setting the brightness through AUX? - * - * This structure contains various data about an eDP backlight, which can be populated by using - * drm_edp_backlight_init(). - */ -struct drm_edp_backlight_info { - u8 pwmgen_bit_count; - u8 pwm_freq_pre_divider; - u16 max; - - bool lsb_reg_used : 1; - bool aux_enable : 1; - bool aux_set : 1; -}; - -int -drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, - u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], - u16 *current_level, u8 *current_mode); -int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, - u16 level); -int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, - u16 level); -int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); - -#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ - (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) - -int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); - -#else - -static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, - struct drm_dp_aux *aux) -{ - return 0; -} - -#endif - -#ifdef CONFIG_DRM_DP_CEC -void drm_dp_cec_irq(struct drm_dp_aux *aux); -void drm_dp_cec_register_connector(struct drm_dp_aux *aux, - struct drm_connector *connector); -void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); -void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); -void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); -#else -static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) -{ -} - -static inline void -drm_dp_cec_register_connector(struct drm_dp_aux *aux, - struct drm_connector *connector) -{ -} - -static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) -{ -} - -static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, - const struct edid *edid) -{ -} - -static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) -{ -} - -#endif - -/** - * struct drm_dp_phy_test_params - DP Phy Compliance parameters - * @link_rate: Requested Link rate from DPCD 0x219 - * @num_lanes: Number of lanes requested by sing through DPCD 0x220 - * @phy_pattern: DP Phy test pattern from DPCD 0x248 - * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B - * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 - * @enhanced_frame_cap: flag for enhanced frame capability. - */ -struct drm_dp_phy_test_params { - int link_rate; - u8 num_lanes; - u8 phy_pattern; - u8 hbr2_reset[2]; - u8 custom80[10]; - bool enhanced_frame_cap; -}; - -int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, - struct drm_dp_phy_test_params *data); -int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, - struct drm_dp_phy_test_params *data, u8 dp_rev); -int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4]); -int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); -bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); -int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, - u8 frl_mode); -int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, - u8 frl_type); -int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); -int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); - -bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); -int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); -void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, - struct drm_connector *connector); -bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); -int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); -int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); -int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); -int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); -int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); -int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); -bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], - const u8 port_cap[4], u8 color_spc); -int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); - -#endif /* _DRM_DP_HELPER_H_ */ diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h deleted file mode 100644 index 78044ac5b59b..000000000000 --- a/include/drm/drm_dp_mst_helper.h +++ /dev/null @@ -1,972 +0,0 @@ -/* - * Copyright © 2014 Red Hat. - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ -#ifndef _DRM_DP_MST_HELPER_H_ -#define _DRM_DP_MST_HELPER_H_ - -#include -#include -#include - -#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) -#include -#include - -enum drm_dp_mst_topology_ref_type { - DRM_DP_MST_TOPOLOGY_REF_GET, - DRM_DP_MST_TOPOLOGY_REF_PUT, -}; - -struct drm_dp_mst_topology_ref_history { - struct drm_dp_mst_topology_ref_entry { - enum drm_dp_mst_topology_ref_type type; - int count; - ktime_t ts_nsec; - depot_stack_handle_t backtrace; - } *entries; - int len; -}; -#endif /* IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) */ - -struct drm_dp_mst_branch; - -/** - * struct drm_dp_vcpi - Virtual Channel Payload Identifier - * @vcpi: Virtual channel ID. - * @pbn: Payload Bandwidth Number for this channel - * @aligned_pbn: PBN aligned with slot size - * @num_slots: number of slots for this PBN - */ -struct drm_dp_vcpi { - int vcpi; - int pbn; - int aligned_pbn; - int num_slots; -}; - -/** - * struct drm_dp_mst_port - MST port - * @port_num: port number - * @input: if this port is an input port. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @mcs: message capability status - DP 1.2 spec. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @ddps: DisplayPort Device Plug Status - DP 1.2. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @pdt: Peer Device Type. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @ldps: Legacy Device Plug Status. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @dpcd_rev: DPCD revision of device on this port. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @num_sdp_streams: Number of simultaneous streams. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @num_sdp_stream_sinks: Number of stream sinks. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @full_pbn: Max possible bandwidth for this port. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @next: link to next port on this branch device - * @aux: i2c aux transport to talk to device connected to this port, protected - * by &drm_dp_mst_topology_mgr.base.lock. - * @parent: branch device parent of this port - * @vcpi: Virtual Channel Payload info for this port. - * @connector: DRM connector this port is connected to. Protected by - * &drm_dp_mst_topology_mgr.base.lock. - * @mgr: topology manager this port lives under. - * - * This structure represents an MST port endpoint on a device somewhere - * in the MST topology. - */ -struct drm_dp_mst_port { - /** - * @topology_kref: refcount for this port's lifetime in the topology, - * only the DP MST helpers should need to touch this - */ - struct kref topology_kref; - - /** - * @malloc_kref: refcount for the memory allocation containing this - * structure. See drm_dp_mst_get_port_malloc() and - * drm_dp_mst_put_port_malloc(). - */ - struct kref malloc_kref; - -#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) - /** - * @topology_ref_history: A history of each topology - * reference/dereference. See CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS. - */ - struct drm_dp_mst_topology_ref_history topology_ref_history; -#endif - - u8 port_num; - bool input; - bool mcs; - bool ddps; - u8 pdt; - bool ldps; - u8 dpcd_rev; - u8 num_sdp_streams; - u8 num_sdp_stream_sinks; - uint16_t full_pbn; - struct list_head next; - /** - * @mstb: the branch device connected to this port, if there is one. - * This should be considered protected for reading by - * &drm_dp_mst_topology_mgr.lock. There are two exceptions to this: - * &drm_dp_mst_topology_mgr.up_req_work and - * &drm_dp_mst_topology_mgr.work, which do not grab - * &drm_dp_mst_topology_mgr.lock during reads but are the only - * updaters of this list and are protected from writing concurrently - * by &drm_dp_mst_topology_mgr.probe_lock. - */ - struct drm_dp_mst_branch *mstb; - struct drm_dp_aux aux; /* i2c bus for this port? */ - struct drm_dp_mst_branch *parent; - - struct drm_dp_vcpi vcpi; - struct drm_connector *connector; - struct drm_dp_mst_topology_mgr *mgr; - - /** - * @cached_edid: for DP logical ports - make tiling work by ensuring - * that the EDID for all connectors is read immediately. - */ - struct edid *cached_edid; - /** - * @has_audio: Tracks whether the sink connector to this port is - * audio-capable. - */ - bool has_audio; - - /** - * @fec_capable: bool indicating if FEC can be supported up to that - * point in the MST topology. - */ - bool fec_capable; -}; - -/* sideband msg header - not bit struct */ -struct drm_dp_sideband_msg_hdr { - u8 lct; - u8 lcr; - u8 rad[8]; - bool broadcast; - bool path_msg; - u8 msg_len; - bool somt; - bool eomt; - bool seqno; -}; - -struct drm_dp_sideband_msg_rx { - u8 chunk[48]; - u8 msg[256]; - u8 curchunk_len; - u8 curchunk_idx; /* chunk we are parsing now */ - u8 curchunk_hdrlen; - u8 curlen; /* total length of the msg */ - bool have_somt; - bool have_eomt; - struct drm_dp_sideband_msg_hdr initial_hdr; -}; - -/** - * struct drm_dp_mst_branch - MST branch device. - * @rad: Relative Address to talk to this branch device. - * @lct: Link count total to talk to this branch device. - * @num_ports: number of ports on the branch. - * @port_parent: pointer to the port parent, NULL if toplevel. - * @mgr: topology manager for this branch device. - * @link_address_sent: if a link address message has been sent to this device yet. - * @guid: guid for DP 1.2 branch device. port under this branch can be - * identified by port #. - * - * This structure represents an MST branch device, there is one - * primary branch device at the root, along with any other branches connected - * to downstream port of parent branches. - */ -struct drm_dp_mst_branch { - /** - * @topology_kref: refcount for this branch device's lifetime in the - * topology, only the DP MST helpers should need to touch this - */ - struct kref topology_kref; - - /** - * @malloc_kref: refcount for the memory allocation containing this - * structure. See drm_dp_mst_get_mstb_malloc() and - * drm_dp_mst_put_mstb_malloc(). - */ - struct kref malloc_kref; - -#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) - /** - * @topology_ref_history: A history of each topology - * reference/dereference. See CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS. - */ - struct drm_dp_mst_topology_ref_history topology_ref_history; -#endif - - /** - * @destroy_next: linked-list entry used by - * drm_dp_delayed_destroy_work() - */ - struct list_head destroy_next; - - u8 rad[8]; - u8 lct; - int num_ports; - - /** - * @ports: the list of ports on this branch device. This should be - * considered protected for reading by &drm_dp_mst_topology_mgr.lock. - * There are two exceptions to this: - * &drm_dp_mst_topology_mgr.up_req_work and - * &drm_dp_mst_topology_mgr.work, which do not grab - * &drm_dp_mst_topology_mgr.lock during reads but are the only - * updaters of this list and are protected from updating the list - * concurrently by @drm_dp_mst_topology_mgr.probe_lock - */ - struct list_head ports; - - struct drm_dp_mst_port *port_parent; - struct drm_dp_mst_topology_mgr *mgr; - - bool link_address_sent; - - /* global unique identifier to identify branch devices */ - u8 guid[16]; -}; - - -struct drm_dp_nak_reply { - u8 guid[16]; - u8 reason; - u8 nak_data; -}; - -struct drm_dp_link_address_ack_reply { - u8 guid[16]; - u8 nports; - struct drm_dp_link_addr_reply_port { - bool input_port; - u8 peer_device_type; - u8 port_number; - bool mcs; - bool ddps; - bool legacy_device_plug_status; - u8 dpcd_revision; - u8 peer_guid[16]; - u8 num_sdp_streams; - u8 num_sdp_stream_sinks; - } ports[16]; -}; - -struct drm_dp_remote_dpcd_read_ack_reply { - u8 port_number; - u8 num_bytes; - u8 bytes[255]; -}; - -struct drm_dp_remote_dpcd_write_ack_reply { - u8 port_number; -}; - -struct drm_dp_remote_dpcd_write_nak_reply { - u8 port_number; - u8 reason; - u8 bytes_written_before_failure; -}; - -struct drm_dp_remote_i2c_read_ack_reply { - u8 port_number; - u8 num_bytes; - u8 bytes[255]; -}; - -struct drm_dp_remote_i2c_read_nak_reply { - u8 port_number; - u8 nak_reason; - u8 i2c_nak_transaction; -}; - -struct drm_dp_remote_i2c_write_ack_reply { - u8 port_number; -}; - -struct drm_dp_query_stream_enc_status_ack_reply { - /* Bit[23:16]- Stream Id */ - u8 stream_id; - - /* Bit[15]- Signed */ - bool reply_signed; - - /* Bit[10:8]- Stream Output Sink Type */ - bool unauthorizable_device_present; - bool legacy_device_present; - bool query_capable_device_present; - - /* Bit[12:11]- Stream Output CP Type */ - bool hdcp_1x_device_present; - bool hdcp_2x_device_present; - - /* Bit[4]- Stream Authentication */ - bool auth_completed; - - /* Bit[3]- Stream Encryption */ - bool encryption_enabled; - - /* Bit[2]- Stream Repeater Function Present */ - bool repeater_present; - - /* Bit[1:0]- Stream State */ - u8 state; -}; - -#define DRM_DP_MAX_SDP_STREAMS 16 -struct drm_dp_allocate_payload { - u8 port_number; - u8 number_sdp_streams; - u8 vcpi; - u16 pbn; - u8 sdp_stream_sink[DRM_DP_MAX_SDP_STREAMS]; -}; - -struct drm_dp_allocate_payload_ack_reply { - u8 port_number; - u8 vcpi; - u16 allocated_pbn; -}; - -struct drm_dp_connection_status_notify { - u8 guid[16]; - u8 port_number; - bool legacy_device_plug_status; - bool displayport_device_plug_status; - bool message_capability_status; - bool input_port; - u8 peer_device_type; -}; - -struct drm_dp_remote_dpcd_read { - u8 port_number; - u32 dpcd_address; - u8 num_bytes; -}; - -struct drm_dp_remote_dpcd_write { - u8 port_number; - u32 dpcd_address; - u8 num_bytes; - u8 *bytes; -}; - -#define DP_REMOTE_I2C_READ_MAX_TRANSACTIONS 4 -struct drm_dp_remote_i2c_read { - u8 num_transactions; - u8 port_number; - struct drm_dp_remote_i2c_read_tx { - u8 i2c_dev_id; - u8 num_bytes; - u8 *bytes; - u8 no_stop_bit; - u8 i2c_transaction_delay; - } transactions[DP_REMOTE_I2C_READ_MAX_TRANSACTIONS]; - u8 read_i2c_device_id; - u8 num_bytes_read; -}; - -struct drm_dp_remote_i2c_write { - u8 port_number; - u8 write_i2c_device_id; - u8 num_bytes; - u8 *bytes; -}; - -struct drm_dp_query_stream_enc_status { - u8 stream_id; - u8 client_id[7]; /* 56-bit nonce */ - u8 stream_event; - bool valid_stream_event; - u8 stream_behavior; - u8 valid_stream_behavior; -}; - -/* this covers ENUM_RESOURCES, POWER_DOWN_PHY, POWER_UP_PHY */ -struct drm_dp_port_number_req { - u8 port_number; -}; - -struct drm_dp_enum_path_resources_ack_reply { - u8 port_number; - bool fec_capable; - u16 full_payload_bw_number; - u16 avail_payload_bw_number; -}; - -/* covers POWER_DOWN_PHY, POWER_UP_PHY */ -struct drm_dp_port_number_rep { - u8 port_number; -}; - -struct drm_dp_query_payload { - u8 port_number; - u8 vcpi; -}; - -struct drm_dp_resource_status_notify { - u8 port_number; - u8 guid[16]; - u16 available_pbn; -}; - -struct drm_dp_query_payload_ack_reply { - u8 port_number; - u16 allocated_pbn; -}; - -struct drm_dp_sideband_msg_req_body { - u8 req_type; - union ack_req { - struct drm_dp_connection_status_notify conn_stat; - struct drm_dp_port_number_req port_num; - struct drm_dp_resource_status_notify resource_stat; - - struct drm_dp_query_payload query_payload; - struct drm_dp_allocate_payload allocate_payload; - - struct drm_dp_remote_dpcd_read dpcd_read; - struct drm_dp_remote_dpcd_write dpcd_write; - - struct drm_dp_remote_i2c_read i2c_read; - struct drm_dp_remote_i2c_write i2c_write; - - struct drm_dp_query_stream_enc_status enc_status; - } u; -}; - -struct drm_dp_sideband_msg_reply_body { - u8 reply_type; - u8 req_type; - union ack_replies { - struct drm_dp_nak_reply nak; - struct drm_dp_link_address_ack_reply link_addr; - struct drm_dp_port_number_rep port_number; - - struct drm_dp_enum_path_resources_ack_reply path_resources; - struct drm_dp_allocate_payload_ack_reply allocate_payload; - struct drm_dp_query_payload_ack_reply query_payload; - - struct drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack; - struct drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack; - struct drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack; - - struct drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack; - struct drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack; - struct drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack; - - struct drm_dp_query_stream_enc_status_ack_reply enc_status; - } u; -}; - -/* msg is queued to be put into a slot */ -#define DRM_DP_SIDEBAND_TX_QUEUED 0 -/* msg has started transmitting on a slot - still on msgq */ -#define DRM_DP_SIDEBAND_TX_START_SEND 1 -/* msg has finished transmitting on a slot - removed from msgq only in slot */ -#define DRM_DP_SIDEBAND_TX_SENT 2 -/* msg has received a response - removed from slot */ -#define DRM_DP_SIDEBAND_TX_RX 3 -#define DRM_DP_SIDEBAND_TX_TIMEOUT 4 - -struct drm_dp_sideband_msg_tx { - u8 msg[256]; - u8 chunk[48]; - u8 cur_offset; - u8 cur_len; - struct drm_dp_mst_branch *dst; - struct list_head next; - int seqno; - int state; - bool path_msg; - struct drm_dp_sideband_msg_reply_body reply; -}; - -/* sideband msg handler */ -struct drm_dp_mst_topology_mgr; -struct drm_dp_mst_topology_cbs { - /* create a connector for a port */ - struct drm_connector *(*add_connector)(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *path); - /* - * Checks for any pending MST interrupts, passing them to MST core for - * processing, the same way an HPD IRQ pulse handler would do this. - * If provided MST core calls this callback from a poll-waiting loop - * when waiting for MST down message replies. The driver is expected - * to guard against a race between this callback and the driver's HPD - * IRQ pulse handler. - */ - void (*poll_hpd_irq)(struct drm_dp_mst_topology_mgr *mgr); -}; - -#define DP_MAX_PAYLOAD (sizeof(unsigned long) * 8) - -#define DP_PAYLOAD_LOCAL 1 -#define DP_PAYLOAD_REMOTE 2 -#define DP_PAYLOAD_DELETE_LOCAL 3 - -struct drm_dp_payload { - int payload_state; - int start_slot; - int num_slots; - int vcpi; -}; - -#define to_dp_mst_topology_state(x) container_of(x, struct drm_dp_mst_topology_state, base) - -struct drm_dp_vcpi_allocation { - struct drm_dp_mst_port *port; - int vcpi; - int pbn; - bool dsc_enabled; - struct list_head next; -}; - -struct drm_dp_mst_topology_state { - struct drm_private_state base; - struct list_head vcpis; - struct drm_dp_mst_topology_mgr *mgr; - u8 total_avail_slots; - u8 start_slot; -}; - -#define to_dp_mst_topology_mgr(x) container_of(x, struct drm_dp_mst_topology_mgr, base) - -/** - * struct drm_dp_mst_topology_mgr - DisplayPort MST manager - * - * This struct represents the toplevel displayport MST topology manager. - * There should be one instance of this for every MST capable DP connector - * on the GPU. - */ -struct drm_dp_mst_topology_mgr { - /** - * @base: Base private object for atomic - */ - struct drm_private_obj base; - - /** - * @dev: device pointer for adding i2c devices etc. - */ - struct drm_device *dev; - /** - * @cbs: callbacks for connector addition and destruction. - */ - const struct drm_dp_mst_topology_cbs *cbs; - /** - * @max_dpcd_transaction_bytes: maximum number of bytes to read/write - * in one go. - */ - int max_dpcd_transaction_bytes; - /** - * @aux: AUX channel for the DP MST connector this topolgy mgr is - * controlling. - */ - struct drm_dp_aux *aux; - /** - * @max_payloads: maximum number of payloads the GPU can generate. - */ - int max_payloads; - /** - * @max_lane_count: maximum number of lanes the GPU can drive. - */ - int max_lane_count; - /** - * @max_link_rate: maximum link rate per lane GPU can output, in kHz. - */ - int max_link_rate; - /** - * @conn_base_id: DRM connector ID this mgr is connected to. Only used - * to build the MST connector path value. - */ - int conn_base_id; - - /** - * @up_req_recv: Message receiver state for up requests. - */ - struct drm_dp_sideband_msg_rx up_req_recv; - - /** - * @down_rep_recv: Message receiver state for replies to down - * requests. - */ - struct drm_dp_sideband_msg_rx down_rep_recv; - - /** - * @lock: protects @mst_state, @mst_primary, @dpcd, and - * @payload_id_table_cleared. - */ - struct mutex lock; - - /** - * @probe_lock: Prevents @work and @up_req_work, the only writers of - * &drm_dp_mst_port.mstb and &drm_dp_mst_branch.ports, from racing - * while they update the topology. - */ - struct mutex probe_lock; - - /** - * @mst_state: If this manager is enabled for an MST capable port. False - * if no MST sink/branch devices is connected. - */ - bool mst_state : 1; - - /** - * @payload_id_table_cleared: Whether or not we've cleared the payload - * ID table for @mst_primary. Protected by @lock. - */ - bool payload_id_table_cleared : 1; - - /** - * @mst_primary: Pointer to the primary/first branch device. - */ - struct drm_dp_mst_branch *mst_primary; - - /** - * @dpcd: Cache of DPCD for primary port. - */ - u8 dpcd[DP_RECEIVER_CAP_SIZE]; - /** - * @sink_count: Sink count from DEVICE_SERVICE_IRQ_VECTOR_ESI0. - */ - u8 sink_count; - /** - * @pbn_div: PBN to slots divisor. - */ - int pbn_div; - - /** - * @funcs: Atomic helper callbacks - */ - const struct drm_private_state_funcs *funcs; - - /** - * @qlock: protects @tx_msg_downq and &drm_dp_sideband_msg_tx.state - */ - struct mutex qlock; - - /** - * @tx_msg_downq: List of pending down requests - */ - struct list_head tx_msg_downq; - - /** - * @payload_lock: Protect payload information. - */ - struct mutex payload_lock; - /** - * @proposed_vcpis: Array of pointers for the new VCPI allocation. The - * VCPI structure itself is &drm_dp_mst_port.vcpi, and the size of - * this array is determined by @max_payloads. - */ - struct drm_dp_vcpi **proposed_vcpis; - /** - * @payloads: Array of payloads. The size of this array is determined - * by @max_payloads. - */ - struct drm_dp_payload *payloads; - /** - * @payload_mask: Elements of @payloads actually in use. Since - * reallocation of active outputs isn't possible gaps can be created by - * disabling outputs out of order compared to how they've been enabled. - */ - unsigned long payload_mask; - /** - * @vcpi_mask: Similar to @payload_mask, but for @proposed_vcpis. - */ - unsigned long vcpi_mask; - - /** - * @tx_waitq: Wait to queue stall for the tx worker. - */ - wait_queue_head_t tx_waitq; - /** - * @work: Probe work. - */ - struct work_struct work; - /** - * @tx_work: Sideband transmit worker. This can nest within the main - * @work worker for each transaction @work launches. - */ - struct work_struct tx_work; - - /** - * @destroy_port_list: List of to be destroyed connectors. - */ - struct list_head destroy_port_list; - /** - * @destroy_branch_device_list: List of to be destroyed branch - * devices. - */ - struct list_head destroy_branch_device_list; - /** - * @delayed_destroy_lock: Protects @destroy_port_list and - * @destroy_branch_device_list. - */ - struct mutex delayed_destroy_lock; - - /** - * @delayed_destroy_wq: Workqueue used for delayed_destroy_work items. - * A dedicated WQ makes it possible to drain any requeued work items - * on it. - */ - struct workqueue_struct *delayed_destroy_wq; - - /** - * @delayed_destroy_work: Work item to destroy MST port and branch - * devices, needed to avoid locking inversion. - */ - struct work_struct delayed_destroy_work; - - /** - * @up_req_list: List of pending up requests from the topology that - * need to be processed, in chronological order. - */ - struct list_head up_req_list; - /** - * @up_req_lock: Protects @up_req_list - */ - struct mutex up_req_lock; - /** - * @up_req_work: Work item to process up requests received from the - * topology. Needed to avoid blocking hotplug handling and sideband - * transmissions. - */ - struct work_struct up_req_work; - -#if IS_ENABLED(CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS) - /** - * @topology_ref_history_lock: protects - * &drm_dp_mst_port.topology_ref_history and - * &drm_dp_mst_branch.topology_ref_history. - */ - struct mutex topology_ref_history_lock; -#endif -}; - -int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr, - struct drm_device *dev, struct drm_dp_aux *aux, - int max_dpcd_transaction_bytes, - int max_payloads, - int max_lane_count, int max_link_rate, - int conn_base_id); - -void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr); - -bool drm_dp_read_mst_cap(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); -int drm_dp_mst_topology_mgr_set_mst(struct drm_dp_mst_topology_mgr *mgr, bool mst_state); - -int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled); - - -int -drm_dp_mst_detect_port(struct drm_connector *connector, - struct drm_modeset_acquire_ctx *ctx, - struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port); - -struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); - -int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr, - int link_rate, int link_lane_count); - -int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc); - -bool drm_dp_mst_allocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port, int pbn, int slots); - -int drm_dp_mst_get_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); - - -void drm_dp_mst_reset_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port); - -void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap); - -void drm_dp_mst_deallocate_vcpi(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port); - - -int drm_dp_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr, - int pbn); - - -int drm_dp_update_payload_part1(struct drm_dp_mst_topology_mgr *mgr, int start_slot); - - -int drm_dp_update_payload_part2(struct drm_dp_mst_topology_mgr *mgr); - -int drm_dp_check_act_status(struct drm_dp_mst_topology_mgr *mgr); - -void drm_dp_mst_dump_topology(struct seq_file *m, - struct drm_dp_mst_topology_mgr *mgr); - -void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr); -int __must_check -drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, - bool sync); - -ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux, - unsigned int offset, void *buffer, size_t size); -ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux, - unsigned int offset, void *buffer, size_t size); - -int drm_dp_mst_connector_late_register(struct drm_connector *connector, - struct drm_dp_mst_port *port); -void drm_dp_mst_connector_early_unregister(struct drm_connector *connector, - struct drm_dp_mst_port *port); - -struct drm_dp_mst_topology_state *drm_atomic_get_mst_topology_state(struct drm_atomic_state *state, - struct drm_dp_mst_topology_mgr *mgr); -int __must_check -drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, - struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port, int pbn, - int pbn_div); -int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state, - struct drm_dp_mst_port *port, - int pbn, int pbn_div, - bool enable); -int __must_check -drm_dp_mst_add_affected_dsc_crtcs(struct drm_atomic_state *state, - struct drm_dp_mst_topology_mgr *mgr); -int __must_check -drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, - struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port); -int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port, bool power_up); -int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_port *port, - struct drm_dp_query_stream_enc_status_ack_reply *status); -int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state); - -void drm_dp_mst_get_port_malloc(struct drm_dp_mst_port *port); -void drm_dp_mst_put_port_malloc(struct drm_dp_mst_port *port); - -struct drm_dp_aux *drm_dp_mst_dsc_aux_for_port(struct drm_dp_mst_port *port); - -extern const struct drm_private_state_funcs drm_dp_mst_topology_state_funcs; - -/** - * __drm_dp_mst_state_iter_get - private atomic state iterator function for - * macro-internal use - * @state: &struct drm_atomic_state pointer - * @mgr: pointer to the &struct drm_dp_mst_topology_mgr iteration cursor - * @old_state: optional pointer to the old &struct drm_dp_mst_topology_state - * iteration cursor - * @new_state: optional pointer to the new &struct drm_dp_mst_topology_state - * iteration cursor - * @i: int iteration cursor, for macro-internal use - * - * Used by for_each_oldnew_mst_mgr_in_state(), - * for_each_old_mst_mgr_in_state(), and for_each_new_mst_mgr_in_state(). Don't - * call this directly. - * - * Returns: - * True if the current &struct drm_private_obj is a &struct - * drm_dp_mst_topology_mgr, false otherwise. - */ -static inline bool -__drm_dp_mst_state_iter_get(struct drm_atomic_state *state, - struct drm_dp_mst_topology_mgr **mgr, - struct drm_dp_mst_topology_state **old_state, - struct drm_dp_mst_topology_state **new_state, - int i) -{ - struct __drm_private_objs_state *objs_state = &state->private_objs[i]; - - if (objs_state->ptr->funcs != &drm_dp_mst_topology_state_funcs) - return false; - - *mgr = to_dp_mst_topology_mgr(objs_state->ptr); - if (old_state) - *old_state = to_dp_mst_topology_state(objs_state->old_state); - if (new_state) - *new_state = to_dp_mst_topology_state(objs_state->new_state); - - return true; -} - -/** - * for_each_oldnew_mst_mgr_in_state - iterate over all DP MST topology - * managers in an atomic update - * @__state: &struct drm_atomic_state pointer - * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor - * @old_state: &struct drm_dp_mst_topology_state iteration cursor for the old - * state - * @new_state: &struct drm_dp_mst_topology_state iteration cursor for the new - * state - * @__i: int iteration cursor, for macro-internal use - * - * This iterates over all DRM DP MST topology managers in an atomic update, - * tracking both old and new state. This is useful in places where the state - * delta needs to be considered, for example in atomic check functions. - */ -#define for_each_oldnew_mst_mgr_in_state(__state, mgr, old_state, new_state, __i) \ - for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ - for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), &(old_state), &(new_state), (__i))) - -/** - * for_each_old_mst_mgr_in_state - iterate over all DP MST topology managers - * in an atomic update - * @__state: &struct drm_atomic_state pointer - * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor - * @old_state: &struct drm_dp_mst_topology_state iteration cursor for the old - * state - * @__i: int iteration cursor, for macro-internal use - * - * This iterates over all DRM DP MST topology managers in an atomic update, - * tracking only the old state. This is useful in disable functions, where we - * need the old state the hardware is still in. - */ -#define for_each_old_mst_mgr_in_state(__state, mgr, old_state, __i) \ - for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ - for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), &(old_state), NULL, (__i))) - -/** - * for_each_new_mst_mgr_in_state - iterate over all DP MST topology managers - * in an atomic update - * @__state: &struct drm_atomic_state pointer - * @mgr: &struct drm_dp_mst_topology_mgr iteration cursor - * @new_state: &struct drm_dp_mst_topology_state iteration cursor for the new - * state - * @__i: int iteration cursor, for macro-internal use - * - * This iterates over all DRM DP MST topology managers in an atomic update, - * tracking only the new state. This is useful in enable functions, where we - * need the new state the hardware should be in when the atomic commit - * operation has completed. - */ -#define for_each_new_mst_mgr_in_state(__state, mgr, new_state, __i) \ - for ((__i) = 0; (__i) < (__state)->num_private_objs; (__i)++) \ - for_each_if(__drm_dp_mst_state_iter_get((__state), &(mgr), NULL, &(new_state), (__i))) - -#endif diff --git a/include/drm/drm_dsc.h b/include/drm/drm_dsc.h index cf43561e60fa..ca022e960dcc 100644 --- a/include/drm/drm_dsc.h +++ b/include/drm/drm_dsc.h @@ -8,7 +8,7 @@ #ifndef DRM_DSC_H_ #define DRM_DSC_H_ -#include +#include /* VESA Display Stream Compression DSC 1.2 constants */ #define DSC_NUM_BUF_RANGES 15 -- cgit v1.2.3