From eaf963b5c17e611ca35850f65db7ebe929bef774 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 12 Jul 2019 14:40:12 +0800 Subject: drm/amd/powerplay: add socclk profile dpm support. 1.miss socclk profile support when bringup. 2.add feature check for socclk. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/drm/amd/powerplay') diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 04132653e289..5f844357e6ac 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -149,6 +149,11 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, pr_warn("gfxclk dpm is not enabled\n"); return 0; } + case SMU_SOCCLK: + if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { + pr_warn("sockclk dpm is not enabled\n"); + return 0; + } break; default: break; @@ -1388,6 +1393,7 @@ int smu_adjust_power_state_dynamic(struct smu_context *smu, return ret; smu_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); smu_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask); + smu_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); break; case AMD_DPM_FORCED_LEVEL_MANUAL: -- cgit v1.2.3