From a43913ea50a545c437b6e264b46fe3a0485f54f0 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 19 Apr 2019 14:05:58 +0800 Subject: drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10 add callback function get_clock_by_type_with_latency for navi10 asic Signed-off-by: Kevin Wang Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/powerplay/vega20_ppt.c') diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 582b99d8f832..aea14f1a6395 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -1395,7 +1395,7 @@ static int vega20_force_clk_levels(struct smu_context *smu, } static int vega20_get_clock_by_type_with_latency(struct smu_context *smu, - enum amd_pp_clock_type type, + enum smu_clk_type clk_type, struct pp_clock_levels_with_latency *clocks) { int ret; @@ -1407,20 +1407,20 @@ static int vega20_get_clock_by_type_with_latency(struct smu_context *smu, mutex_lock(&smu->mutex); - switch (type) { - case amd_pp_sys_clock: + switch (clk_type) { + case SMU_GFXCLK: single_dpm_table = &(dpm_table->gfx_table); ret = vega20_get_clk_table(smu, clocks, single_dpm_table); break; - case amd_pp_mem_clock: + case SMU_MCLK: single_dpm_table = &(dpm_table->mem_table); ret = vega20_get_clk_table(smu, clocks, single_dpm_table); break; - case amd_pp_dcef_clock: + case SMU_DCEFCLK: single_dpm_table = &(dpm_table->dcef_table); ret = vega20_get_clk_table(smu, clocks, single_dpm_table); break; - case amd_pp_soc_clock: + case SMU_SOCCLK: single_dpm_table = &(dpm_table->soc_table); ret = vega20_get_clk_table(smu, clocks, single_dpm_table); break; -- cgit v1.2.3