From c524c1c9a78f12137da0447e085411cbbd89ab0b Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Sat, 20 Feb 2021 11:58:51 +0800 Subject: drm/amd/pm: optimize the link width/speed retrieving V2 By using the information provided by PMFW when available. V2: put those structures shared around SMU V11 ASICs in smu_v11_0.h Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/pm/inc') diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h index 520979ad2687..901c4b0c1d18 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h @@ -58,6 +58,12 @@ #define CTF_OFFSET_HOTSPOT 5 #define CTF_OFFSET_MEM 5 +#define LINK_WIDTH_MAX 6 +#define LINK_SPEED_MAX 3 + +static __maybe_unused uint8_t link_width[] = {0, 1, 2, 4, 8, 12, 16}; +static __maybe_unused uint8_t link_speed[] = {25, 50, 80, 160}; + static const struct smu_temperature_range __maybe_unused smu11_thermal_policy[] = { @@ -275,11 +281,11 @@ int smu_v11_0_get_dpm_level_range(struct smu_context *smu, int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu); -int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu); +uint8_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu); int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu); -int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); +uint8_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu); int smu_v11_0_gfx_ulv_control(struct smu_context *smu, bool enablement); -- cgit v1.2.3